2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
50 static void sdhci_finish_data(struct sdhci_host *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
82 static void sdhci_dumpregs(struct sdhci_host *host)
84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host->mmc));
87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host, SDHCI_CAPABILITIES),
116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host, SDHCI_COMMAND),
119 sdhci_readl(host, SDHCI_MAX_CURRENT));
120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
135 pr_debug(DRIVER_NAME ": ===========================================\n");
138 /*****************************************************************************\
140 * Low level functions *
142 \*****************************************************************************/
144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
168 sdhci_set_card_detection(host, true);
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
173 sdhci_set_card_detection(host, false);
176 void sdhci_reset(struct sdhci_host *host, u8 mask)
178 unsigned long timeout;
180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
182 if (mask & SDHCI_RESET_ALL) {
184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
189 /* Wait max 100 ms */
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
204 EXPORT_SYMBOL_GPL(sdhci_reset);
206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
214 host->ops->reset(host, mask);
216 if (mask & SDHCI_RESET_ALL) {
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if (host->ops->enable_dma)
219 host->ops->enable_dma(host);
222 /* Resetting the controller clears many */
223 host->preset_enabled = false;
227 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
229 static void sdhci_init(struct sdhci_host *host, int soft)
232 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
234 sdhci_do_reset(host, SDHCI_RESET_ALL);
236 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
238 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
239 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
242 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
243 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
246 /* force clock reconfiguration */
248 sdhci_set_ios(host->mmc, &host->mmc->ios);
252 static void sdhci_reinit(struct sdhci_host *host)
256 * Retuning stuffs are affected by different cards inserted and only
257 * applicable to UHS-I cards. So reset these fields to their initial
258 * value when card is removed.
260 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
261 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
263 del_timer_sync(&host->tuning_timer);
264 host->flags &= ~SDHCI_NEEDS_RETUNING;
266 sdhci_enable_card_detection(host);
269 static void sdhci_activate_led(struct sdhci_host *host)
273 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
274 ctrl |= SDHCI_CTRL_LED;
275 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
278 static void sdhci_deactivate_led(struct sdhci_host *host)
282 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
283 ctrl &= ~SDHCI_CTRL_LED;
284 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
287 #ifdef SDHCI_USE_LEDS_CLASS
288 static void sdhci_led_control(struct led_classdev *led,
289 enum led_brightness brightness)
291 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
294 spin_lock_irqsave(&host->lock, flags);
296 if (host->runtime_suspended)
299 if (brightness == LED_OFF)
300 sdhci_deactivate_led(host);
302 sdhci_activate_led(host);
304 spin_unlock_irqrestore(&host->lock, flags);
308 /*****************************************************************************\
312 \*****************************************************************************/
314 static void sdhci_read_block_pio(struct sdhci_host *host)
317 size_t blksize, len, chunk;
318 u32 uninitialized_var(scratch);
321 DBG("PIO reading\n");
323 blksize = host->data->blksz;
326 local_irq_save(flags);
329 if (!sg_miter_next(&host->sg_miter))
332 len = min(host->sg_miter.length, blksize);
335 host->sg_miter.consumed = len;
337 buf = host->sg_miter.addr;
341 scratch = sdhci_readl(host, SDHCI_BUFFER);
345 *buf = scratch & 0xFF;
354 sg_miter_stop(&host->sg_miter);
356 local_irq_restore(flags);
359 static void sdhci_write_block_pio(struct sdhci_host *host)
362 size_t blksize, len, chunk;
366 DBG("PIO writing\n");
368 blksize = host->data->blksz;
372 local_irq_save(flags);
375 if (!sg_miter_next(&host->sg_miter))
378 len = min(host->sg_miter.length, blksize);
381 host->sg_miter.consumed = len;
383 buf = host->sg_miter.addr;
386 scratch |= (u32)*buf << (chunk * 8);
392 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
393 sdhci_writel(host, scratch, SDHCI_BUFFER);
400 sg_miter_stop(&host->sg_miter);
402 local_irq_restore(flags);
405 static void sdhci_transfer_pio(struct sdhci_host *host)
411 if (host->blocks == 0)
414 if (host->data->flags & MMC_DATA_READ)
415 mask = SDHCI_DATA_AVAILABLE;
417 mask = SDHCI_SPACE_AVAILABLE;
420 * Some controllers (JMicron JMB38x) mess up the buffer bits
421 * for transfers < 4 bytes. As long as it is just one block,
422 * we can ignore the bits.
424 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
425 (host->data->blocks == 1))
428 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
429 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
432 if (host->data->flags & MMC_DATA_READ)
433 sdhci_read_block_pio(host);
435 sdhci_write_block_pio(host);
438 if (host->blocks == 0)
442 DBG("PIO transfer complete.\n");
445 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
447 local_irq_save(*flags);
448 return kmap_atomic(sg_page(sg)) + sg->offset;
451 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
453 kunmap_atomic(buffer);
454 local_irq_restore(*flags);
457 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
458 dma_addr_t addr, int len, unsigned cmd)
460 struct sdhci_adma2_64_desc *dma_desc = desc;
462 /* 32-bit and 64-bit descriptors have these members in same position */
463 dma_desc->cmd = cpu_to_le16(cmd);
464 dma_desc->len = cpu_to_le16(len);
465 dma_desc->addr_lo = cpu_to_le32((u32)addr);
467 if (host->flags & SDHCI_USE_64_BIT_DMA)
468 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
471 static void sdhci_adma_mark_end(void *desc)
473 struct sdhci_adma2_64_desc *dma_desc = desc;
475 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
476 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
479 static int sdhci_adma_table_pre(struct sdhci_host *host,
480 struct mmc_data *data)
487 dma_addr_t align_addr;
490 struct scatterlist *sg;
496 * The spec does not specify endianness of descriptor table.
497 * We currently guess that it is LE.
500 if (data->flags & MMC_DATA_READ)
501 direction = DMA_FROM_DEVICE;
503 direction = DMA_TO_DEVICE;
505 host->align_addr = dma_map_single(mmc_dev(host->mmc),
506 host->align_buffer, host->align_buffer_sz, direction);
507 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
509 BUG_ON(host->align_addr & host->align_mask);
511 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
512 if (host->sg_count < 0)
515 desc = host->adma_table;
516 align = host->align_buffer;
518 align_addr = host->align_addr;
520 for_each_sg(data->sg, sg, host->sg_count, i) {
521 addr = sg_dma_address(sg);
522 len = sg_dma_len(sg);
525 * The SDHCI specification states that ADMA
526 * addresses must be 32-bit aligned. If they
527 * aren't, then we use a bounce buffer for
528 * the (up to three) bytes that screw up the
531 offset = (host->align_sz - (addr & host->align_mask)) &
534 if (data->flags & MMC_DATA_WRITE) {
535 buffer = sdhci_kmap_atomic(sg, &flags);
536 memcpy(align, buffer, offset);
537 sdhci_kunmap_atomic(buffer, &flags);
541 sdhci_adma_write_desc(host, desc, align_addr, offset,
544 BUG_ON(offset > 65536);
546 align += host->align_sz;
547 align_addr += host->align_sz;
549 desc += host->desc_sz;
558 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
559 desc += host->desc_sz;
562 * If this triggers then we have a calculation bug
565 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
568 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
570 * Mark the last descriptor as the terminating descriptor
572 if (desc != host->adma_table) {
573 desc -= host->desc_sz;
574 sdhci_adma_mark_end(desc);
578 * Add a terminating entry.
581 /* nop, end, valid */
582 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
586 * Resync align buffer as we might have changed it.
588 if (data->flags & MMC_DATA_WRITE) {
589 dma_sync_single_for_device(mmc_dev(host->mmc),
590 host->align_addr, host->align_buffer_sz, direction);
596 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
597 host->align_buffer_sz, direction);
602 static void sdhci_adma_table_post(struct sdhci_host *host,
603 struct mmc_data *data)
607 struct scatterlist *sg;
614 if (data->flags & MMC_DATA_READ)
615 direction = DMA_FROM_DEVICE;
617 direction = DMA_TO_DEVICE;
619 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
620 host->align_buffer_sz, direction);
622 /* Do a quick scan of the SG list for any unaligned mappings */
623 has_unaligned = false;
624 for_each_sg(data->sg, sg, host->sg_count, i)
625 if (sg_dma_address(sg) & host->align_mask) {
626 has_unaligned = true;
630 if (has_unaligned && data->flags & MMC_DATA_READ) {
631 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
634 align = host->align_buffer;
636 for_each_sg(data->sg, sg, host->sg_count, i) {
637 if (sg_dma_address(sg) & host->align_mask) {
638 size = host->align_sz -
639 (sg_dma_address(sg) & host->align_mask);
641 buffer = sdhci_kmap_atomic(sg, &flags);
642 memcpy(buffer, align, size);
643 sdhci_kunmap_atomic(buffer, &flags);
645 align += host->align_sz;
650 if (!data->host_cookie)
651 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
652 data->sg_len, direction);
655 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
658 struct mmc_data *data = cmd->data;
659 unsigned target_timeout, current_timeout;
662 * If the host controller provides us with an incorrect timeout
663 * value, just skip the check and use 0xE. The hardware may take
664 * longer to time out, but that's much better than having a too-short
667 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
670 /* Unspecified timeout, assume max */
671 if (!data && !cmd->busy_timeout)
676 target_timeout = cmd->busy_timeout * 1000;
678 target_timeout = data->timeout_ns / 1000;
680 target_timeout += data->timeout_clks / host->clock;
684 * Figure out needed cycles.
685 * We do this in steps in order to fit inside a 32 bit int.
686 * The first step is the minimum timeout, which will have a
687 * minimum resolution of 6 bits:
688 * (1) 2^13*1000 > 2^22,
689 * (2) host->timeout_clk < 2^16
694 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
695 while (current_timeout < target_timeout) {
697 current_timeout <<= 1;
703 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
704 mmc_hostname(host->mmc), count, cmd->opcode);
711 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
713 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
714 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
716 if (host->flags & SDHCI_REQ_USE_DMA)
717 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
719 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
721 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
722 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
725 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
729 if (host->ops->set_timeout) {
730 host->ops->set_timeout(host, cmd);
732 count = sdhci_calc_timeout(host, cmd);
733 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
737 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
740 struct mmc_data *data = cmd->data;
745 if (data || (cmd->flags & MMC_RSP_BUSY))
746 sdhci_set_timeout(host, cmd);
752 BUG_ON(data->blksz * data->blocks > 524288);
753 BUG_ON(data->blksz > host->mmc->max_blk_size);
754 BUG_ON(data->blocks > 65535);
757 host->data_early = 0;
758 host->data->bytes_xfered = 0;
760 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
761 host->flags |= SDHCI_REQ_USE_DMA;
764 * FIXME: This doesn't account for merging when mapping the
767 if (host->flags & SDHCI_REQ_USE_DMA) {
769 struct scatterlist *sg;
772 if (host->flags & SDHCI_USE_ADMA) {
773 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
776 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
780 if (unlikely(broken)) {
781 for_each_sg(data->sg, sg, data->sg_len, i) {
782 if (sg->length & 0x3) {
783 DBG("Reverting to PIO because of "
784 "transfer size (%d)\n",
786 host->flags &= ~SDHCI_REQ_USE_DMA;
794 * The assumption here being that alignment is the same after
795 * translation to device address space.
797 if (host->flags & SDHCI_REQ_USE_DMA) {
799 struct scatterlist *sg;
802 if (host->flags & SDHCI_USE_ADMA) {
804 * As we use 3 byte chunks to work around
805 * alignment problems, we need to check this
808 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
811 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
815 if (unlikely(broken)) {
816 for_each_sg(data->sg, sg, data->sg_len, i) {
817 if (sg->offset & 0x3) {
818 DBG("Reverting to PIO because of "
820 host->flags &= ~SDHCI_REQ_USE_DMA;
827 if (host->flags & SDHCI_REQ_USE_DMA) {
828 if (host->flags & SDHCI_USE_ADMA) {
829 ret = sdhci_adma_table_pre(host, data);
832 * This only happens when someone fed
833 * us an invalid request.
836 host->flags &= ~SDHCI_REQ_USE_DMA;
838 sdhci_writel(host, host->adma_addr,
840 if (host->flags & SDHCI_USE_64_BIT_DMA)
842 (u64)host->adma_addr >> 32,
843 SDHCI_ADMA_ADDRESS_HI);
848 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
851 * This only happens when someone fed
852 * us an invalid request.
855 host->flags &= ~SDHCI_REQ_USE_DMA;
857 WARN_ON(sg_cnt != 1);
858 sdhci_writel(host, sg_dma_address(data->sg),
865 * Always adjust the DMA selection as some controllers
866 * (e.g. JMicron) can't do PIO properly when the selection
869 if (host->version >= SDHCI_SPEC_200) {
870 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
871 ctrl &= ~SDHCI_CTRL_DMA_MASK;
872 if ((host->flags & SDHCI_REQ_USE_DMA) &&
873 (host->flags & SDHCI_USE_ADMA)) {
874 if (host->flags & SDHCI_USE_64_BIT_DMA)
875 ctrl |= SDHCI_CTRL_ADMA64;
877 ctrl |= SDHCI_CTRL_ADMA32;
879 ctrl |= SDHCI_CTRL_SDMA;
881 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
884 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
887 flags = SG_MITER_ATOMIC;
888 if (host->data->flags & MMC_DATA_READ)
889 flags |= SG_MITER_TO_SG;
891 flags |= SG_MITER_FROM_SG;
892 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
893 host->blocks = data->blocks;
896 sdhci_set_transfer_irqs(host);
898 /* Set the DMA boundary value and block size */
899 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
900 data->blksz), SDHCI_BLOCK_SIZE);
901 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
904 static void sdhci_set_transfer_mode(struct sdhci_host *host,
905 struct mmc_command *cmd)
908 struct mmc_data *data = cmd->data;
912 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
913 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
915 /* clear Auto CMD settings for no data CMDs */
916 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
917 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
918 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
923 WARN_ON(!host->data);
925 mode = SDHCI_TRNS_BLK_CNT_EN;
926 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
927 mode |= SDHCI_TRNS_MULTI;
929 * If we are sending CMD23, CMD12 never gets sent
930 * on successful completion (so no Auto-CMD12).
932 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
933 mode |= SDHCI_TRNS_AUTO_CMD12;
934 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
935 mode |= SDHCI_TRNS_AUTO_CMD23;
936 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
940 if (data->flags & MMC_DATA_READ)
941 mode |= SDHCI_TRNS_READ;
942 if (host->flags & SDHCI_REQ_USE_DMA)
943 mode |= SDHCI_TRNS_DMA;
945 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
948 static void sdhci_finish_data(struct sdhci_host *host)
950 struct mmc_data *data;
957 if (host->flags & SDHCI_REQ_USE_DMA) {
958 if (host->flags & SDHCI_USE_ADMA)
959 sdhci_adma_table_post(host, data);
961 if (!data->host_cookie)
962 dma_unmap_sg(mmc_dev(host->mmc),
963 data->sg, data->sg_len,
964 (data->flags & MMC_DATA_READ) ?
965 DMA_FROM_DEVICE : DMA_TO_DEVICE);
970 * The specification states that the block count register must
971 * be updated, but it does not specify at what point in the
972 * data flow. That makes the register entirely useless to read
973 * back so we have to assume that nothing made it to the card
974 * in the event of an error.
977 data->bytes_xfered = 0;
979 data->bytes_xfered = data->blksz * data->blocks;
982 * Need to send CMD12 if -
983 * a) open-ended multiblock transfer (no CMD23)
984 * b) error in multiblock transfer
991 * The controller needs a reset of internal state machines
992 * upon error conditions.
995 sdhci_do_reset(host, SDHCI_RESET_CMD);
996 sdhci_do_reset(host, SDHCI_RESET_DATA);
999 sdhci_send_command(host, data->stop);
1001 tasklet_schedule(&host->finish_tasklet);
1004 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1008 unsigned long timeout;
1012 /* Wait max 10 ms */
1015 mask = SDHCI_CMD_INHIBIT;
1016 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1017 mask |= SDHCI_DATA_INHIBIT;
1019 /* We shouldn't wait for data inihibit for stop commands, even
1020 though they might use busy signaling */
1021 if (host->mrq->data && (cmd == host->mrq->data->stop))
1022 mask &= ~SDHCI_DATA_INHIBIT;
1024 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1026 pr_err("%s: Controller never released "
1027 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1028 sdhci_dumpregs(host);
1030 tasklet_schedule(&host->finish_tasklet);
1038 if (!cmd->data && cmd->busy_timeout > 9000)
1039 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1042 mod_timer(&host->timer, timeout);
1045 host->busy_handle = 0;
1047 sdhci_prepare_data(host, cmd);
1049 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1051 sdhci_set_transfer_mode(host, cmd);
1053 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1054 pr_err("%s: Unsupported response type!\n",
1055 mmc_hostname(host->mmc));
1056 cmd->error = -EINVAL;
1057 tasklet_schedule(&host->finish_tasklet);
1061 if (!(cmd->flags & MMC_RSP_PRESENT))
1062 flags = SDHCI_CMD_RESP_NONE;
1063 else if (cmd->flags & MMC_RSP_136)
1064 flags = SDHCI_CMD_RESP_LONG;
1065 else if (cmd->flags & MMC_RSP_BUSY)
1066 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1068 flags = SDHCI_CMD_RESP_SHORT;
1070 if (cmd->flags & MMC_RSP_CRC)
1071 flags |= SDHCI_CMD_CRC;
1072 if (cmd->flags & MMC_RSP_OPCODE)
1073 flags |= SDHCI_CMD_INDEX;
1075 /* CMD19 is special in that the Data Present Select should be set */
1076 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1077 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1078 flags |= SDHCI_CMD_DATA;
1080 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1082 EXPORT_SYMBOL_GPL(sdhci_send_command);
1084 static void sdhci_finish_command(struct sdhci_host *host)
1088 BUG_ON(host->cmd == NULL);
1090 if (host->cmd->flags & MMC_RSP_PRESENT) {
1091 if (host->cmd->flags & MMC_RSP_136) {
1092 /* CRC is stripped so we need to do some shifting. */
1093 for (i = 0;i < 4;i++) {
1094 host->cmd->resp[i] = sdhci_readl(host,
1095 SDHCI_RESPONSE + (3-i)*4) << 8;
1097 host->cmd->resp[i] |=
1099 SDHCI_RESPONSE + (3-i)*4-1);
1102 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1106 host->cmd->error = 0;
1108 /* Finished CMD23, now send actual command. */
1109 if (host->cmd == host->mrq->sbc) {
1111 sdhci_send_command(host, host->mrq->cmd);
1114 /* Processed actual command. */
1115 if (host->data && host->data_early)
1116 sdhci_finish_data(host);
1118 if (!host->cmd->data)
1119 tasklet_schedule(&host->finish_tasklet);
1125 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1129 switch (host->timing) {
1130 case MMC_TIMING_UHS_SDR12:
1131 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1133 case MMC_TIMING_UHS_SDR25:
1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1136 case MMC_TIMING_UHS_SDR50:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1139 case MMC_TIMING_UHS_SDR104:
1140 case MMC_TIMING_MMC_HS200:
1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1143 case MMC_TIMING_UHS_DDR50:
1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1146 case MMC_TIMING_MMC_HS400:
1147 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1150 pr_warn("%s: Invalid UHS-I mode selected\n",
1151 mmc_hostname(host->mmc));
1152 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1158 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1160 int div = 0; /* Initialized for compiler warning */
1161 int real_div = div, clk_mul = 1;
1163 unsigned long timeout;
1165 host->mmc->actual_clock = 0;
1167 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1172 if (host->version >= SDHCI_SPEC_300) {
1173 if (host->preset_enabled) {
1176 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1177 pre_val = sdhci_get_preset_value(host);
1178 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1179 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1180 if (host->clk_mul &&
1181 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1182 clk = SDHCI_PROG_CLOCK_MODE;
1184 clk_mul = host->clk_mul;
1186 real_div = max_t(int, 1, div << 1);
1192 * Check if the Host Controller supports Programmable Clock
1195 if (host->clk_mul) {
1196 for (div = 1; div <= 1024; div++) {
1197 if ((host->max_clk * host->clk_mul / div)
1202 * Set Programmable Clock Mode in the Clock
1205 clk = SDHCI_PROG_CLOCK_MODE;
1207 clk_mul = host->clk_mul;
1210 /* Version 3.00 divisors must be a multiple of 2. */
1211 if (host->max_clk <= clock)
1214 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1216 if ((host->max_clk / div) <= clock)
1224 /* Version 2.00 divisors must be a power of 2. */
1225 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1226 if ((host->max_clk / div) <= clock)
1235 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1236 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1237 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1238 << SDHCI_DIVIDER_HI_SHIFT;
1239 clk |= SDHCI_CLOCK_INT_EN;
1240 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1242 /* Wait max 20 ms */
1244 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1245 & SDHCI_CLOCK_INT_STABLE)) {
1247 pr_err("%s: Internal clock never "
1248 "stabilised.\n", mmc_hostname(host->mmc));
1249 sdhci_dumpregs(host);
1256 clk |= SDHCI_CLOCK_CARD_EN;
1257 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1259 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1261 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1264 struct mmc_host *mmc = host->mmc;
1267 if (!IS_ERR(mmc->supply.vmmc)) {
1268 spin_unlock_irq(&host->lock);
1269 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1270 spin_lock_irq(&host->lock);
1272 if (mode != MMC_POWER_OFF)
1273 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1275 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1280 if (mode != MMC_POWER_OFF) {
1282 case MMC_VDD_165_195:
1283 pwr = SDHCI_POWER_180;
1287 pwr = SDHCI_POWER_300;
1291 pwr = SDHCI_POWER_330;
1298 if (host->pwr == pwr)
1304 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1305 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1306 sdhci_runtime_pm_bus_off(host);
1310 * Spec says that we should clear the power reg before setting
1311 * a new value. Some controllers don't seem to like this though.
1313 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1314 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1317 * At least the Marvell CaFe chip gets confused if we set the
1318 * voltage and set turn on power at the same time, so set the
1321 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1322 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1324 pwr |= SDHCI_POWER_ON;
1326 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1328 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1329 sdhci_runtime_pm_bus_on(host);
1332 * Some controllers need an extra 10ms delay of 10ms before
1333 * they can apply clock after applying power
1335 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1340 /*****************************************************************************\
1344 \*****************************************************************************/
1346 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1348 struct sdhci_host *host;
1350 unsigned long flags;
1353 host = mmc_priv(mmc);
1355 sdhci_runtime_pm_get(host);
1357 present = mmc_gpio_get_cd(host->mmc);
1359 spin_lock_irqsave(&host->lock, flags);
1361 WARN_ON(host->mrq != NULL);
1363 #ifndef SDHCI_USE_LEDS_CLASS
1364 sdhci_activate_led(host);
1368 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1369 * requests if Auto-CMD12 is enabled.
1371 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1373 mrq->data->stop = NULL;
1381 * Firstly check card presence from cd-gpio. The return could
1382 * be one of the following possibilities:
1383 * negative: cd-gpio is not available
1384 * zero: cd-gpio is used, and card is removed
1385 * one: cd-gpio is used, and card is present
1388 /* If polling, assume that the card is always present. */
1389 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1392 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1396 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1397 host->mrq->cmd->error = -ENOMEDIUM;
1398 tasklet_schedule(&host->finish_tasklet);
1402 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1404 * Check if the re-tuning timer has already expired and there
1405 * is no on-going data transfer and DAT0 is not busy. If so,
1406 * we need to execute tuning procedure before sending command.
1408 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1409 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1410 (present_state & SDHCI_DATA_0_LVL_MASK)) {
1412 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1414 mmc->card->type == MMC_TYPE_MMC ?
1415 MMC_SEND_TUNING_BLOCK_HS200 :
1416 MMC_SEND_TUNING_BLOCK;
1418 /* Here we need to set the host->mrq to NULL,
1419 * in case the pending finish_tasklet
1420 * finishes it incorrectly.
1424 spin_unlock_irqrestore(&host->lock, flags);
1425 sdhci_execute_tuning(mmc, tuning_opcode);
1426 spin_lock_irqsave(&host->lock, flags);
1428 /* Restore original mmc_request structure */
1433 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1434 sdhci_send_command(host, mrq->sbc);
1436 sdhci_send_command(host, mrq->cmd);
1440 spin_unlock_irqrestore(&host->lock, flags);
1443 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1447 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1448 if (width == MMC_BUS_WIDTH_8) {
1449 ctrl &= ~SDHCI_CTRL_4BITBUS;
1450 if (host->version >= SDHCI_SPEC_300)
1451 ctrl |= SDHCI_CTRL_8BITBUS;
1453 if (host->version >= SDHCI_SPEC_300)
1454 ctrl &= ~SDHCI_CTRL_8BITBUS;
1455 if (width == MMC_BUS_WIDTH_4)
1456 ctrl |= SDHCI_CTRL_4BITBUS;
1458 ctrl &= ~SDHCI_CTRL_4BITBUS;
1460 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1462 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1464 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1468 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1469 /* Select Bus Speed Mode for host */
1470 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1471 if ((timing == MMC_TIMING_MMC_HS200) ||
1472 (timing == MMC_TIMING_UHS_SDR104))
1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1474 else if (timing == MMC_TIMING_UHS_SDR12)
1475 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1476 else if (timing == MMC_TIMING_UHS_SDR25)
1477 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1478 else if (timing == MMC_TIMING_UHS_SDR50)
1479 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1480 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1481 (timing == MMC_TIMING_MMC_DDR52))
1482 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1483 else if (timing == MMC_TIMING_MMC_HS400)
1484 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1485 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1487 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1489 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1491 unsigned long flags;
1493 struct mmc_host *mmc = host->mmc;
1495 spin_lock_irqsave(&host->lock, flags);
1497 if (host->flags & SDHCI_DEVICE_DEAD) {
1498 spin_unlock_irqrestore(&host->lock, flags);
1499 if (!IS_ERR(mmc->supply.vmmc) &&
1500 ios->power_mode == MMC_POWER_OFF)
1501 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1506 * Reset the chip on each power off.
1507 * Should clear out any weird states.
1509 if (ios->power_mode == MMC_POWER_OFF) {
1510 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1514 if (host->version >= SDHCI_SPEC_300 &&
1515 (ios->power_mode == MMC_POWER_UP) &&
1516 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1517 sdhci_enable_preset_value(host, false);
1519 if (!ios->clock || ios->clock != host->clock) {
1520 host->ops->set_clock(host, ios->clock);
1521 host->clock = ios->clock;
1523 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1525 host->timeout_clk = host->mmc->actual_clock ?
1526 host->mmc->actual_clock / 1000 :
1528 host->mmc->max_busy_timeout =
1529 host->ops->get_max_timeout_count ?
1530 host->ops->get_max_timeout_count(host) :
1532 host->mmc->max_busy_timeout /= host->timeout_clk;
1536 sdhci_set_power(host, ios->power_mode, ios->vdd);
1538 if (host->ops->platform_send_init_74_clocks)
1539 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1541 host->ops->set_bus_width(host, ios->bus_width);
1543 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1545 if ((ios->timing == MMC_TIMING_SD_HS ||
1546 ios->timing == MMC_TIMING_MMC_HS)
1547 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1548 ctrl |= SDHCI_CTRL_HISPD;
1550 ctrl &= ~SDHCI_CTRL_HISPD;
1552 if (host->version >= SDHCI_SPEC_300) {
1555 /* In case of UHS-I modes, set High Speed Enable */
1556 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1557 (ios->timing == MMC_TIMING_MMC_HS200) ||
1558 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1559 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1560 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1561 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR25))
1563 ctrl |= SDHCI_CTRL_HISPD;
1565 if (!host->preset_enabled) {
1566 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1568 * We only need to set Driver Strength if the
1569 * preset value enable is not set.
1571 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1572 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1573 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1574 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1575 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1576 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1578 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1581 * According to SDHC Spec v3.00, if the Preset Value
1582 * Enable in the Host Control 2 register is set, we
1583 * need to reset SD Clock Enable before changing High
1584 * Speed Enable to avoid generating clock gliches.
1587 /* Reset SD Clock Enable */
1588 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1589 clk &= ~SDHCI_CLOCK_CARD_EN;
1590 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1592 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1594 /* Re-enable SD Clock */
1595 host->ops->set_clock(host, host->clock);
1598 /* Reset SD Clock Enable */
1599 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1600 clk &= ~SDHCI_CLOCK_CARD_EN;
1601 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1603 host->ops->set_uhs_signaling(host, ios->timing);
1604 host->timing = ios->timing;
1606 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1607 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1608 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1609 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1610 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1611 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1614 sdhci_enable_preset_value(host, true);
1615 preset = sdhci_get_preset_value(host);
1616 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1617 >> SDHCI_PRESET_DRV_SHIFT;
1620 /* Re-enable SD Clock */
1621 host->ops->set_clock(host, host->clock);
1623 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1626 * Some (ENE) controllers go apeshit on some ios operation,
1627 * signalling timeout and CRC errors even on CMD0. Resetting
1628 * it on each ios seems to solve the problem.
1630 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1631 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1634 spin_unlock_irqrestore(&host->lock, flags);
1637 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1639 struct sdhci_host *host = mmc_priv(mmc);
1641 sdhci_runtime_pm_get(host);
1642 sdhci_do_set_ios(host, ios);
1643 sdhci_runtime_pm_put(host);
1646 static int sdhci_do_get_cd(struct sdhci_host *host)
1648 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1650 if (host->flags & SDHCI_DEVICE_DEAD)
1653 /* If polling/nonremovable, assume that the card is always present. */
1654 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1655 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1658 /* Try slot gpio detect */
1659 if (!IS_ERR_VALUE(gpio_cd))
1662 /* Host native card detect */
1663 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1666 static int sdhci_get_cd(struct mmc_host *mmc)
1668 struct sdhci_host *host = mmc_priv(mmc);
1671 sdhci_runtime_pm_get(host);
1672 ret = sdhci_do_get_cd(host);
1673 sdhci_runtime_pm_put(host);
1677 static int sdhci_check_ro(struct sdhci_host *host)
1679 unsigned long flags;
1682 spin_lock_irqsave(&host->lock, flags);
1684 if (host->flags & SDHCI_DEVICE_DEAD)
1686 else if (host->ops->get_ro)
1687 is_readonly = host->ops->get_ro(host);
1689 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1690 & SDHCI_WRITE_PROTECT);
1692 spin_unlock_irqrestore(&host->lock, flags);
1694 /* This quirk needs to be replaced by a callback-function later */
1695 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1696 !is_readonly : is_readonly;
1699 #define SAMPLE_COUNT 5
1701 static int sdhci_do_get_ro(struct sdhci_host *host)
1705 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1706 return sdhci_check_ro(host);
1709 for (i = 0; i < SAMPLE_COUNT; i++) {
1710 if (sdhci_check_ro(host)) {
1711 if (++ro_count > SAMPLE_COUNT / 2)
1719 static void sdhci_hw_reset(struct mmc_host *mmc)
1721 struct sdhci_host *host = mmc_priv(mmc);
1723 if (host->ops && host->ops->hw_reset)
1724 host->ops->hw_reset(host);
1727 static int sdhci_get_ro(struct mmc_host *mmc)
1729 struct sdhci_host *host = mmc_priv(mmc);
1732 sdhci_runtime_pm_get(host);
1733 ret = sdhci_do_get_ro(host);
1734 sdhci_runtime_pm_put(host);
1738 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1740 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1742 host->ier |= SDHCI_INT_CARD_INT;
1744 host->ier &= ~SDHCI_INT_CARD_INT;
1746 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1747 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1752 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1754 struct sdhci_host *host = mmc_priv(mmc);
1755 unsigned long flags;
1757 sdhci_runtime_pm_get(host);
1759 spin_lock_irqsave(&host->lock, flags);
1761 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1763 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1765 sdhci_enable_sdio_irq_nolock(host, enable);
1766 spin_unlock_irqrestore(&host->lock, flags);
1768 sdhci_runtime_pm_put(host);
1771 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1772 struct mmc_ios *ios)
1774 struct mmc_host *mmc = host->mmc;
1779 * Signal Voltage Switching is only applicable for Host Controllers
1782 if (host->version < SDHCI_SPEC_300)
1785 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1787 switch (ios->signal_voltage) {
1788 case MMC_SIGNAL_VOLTAGE_330:
1789 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1790 ctrl &= ~SDHCI_CTRL_VDD_180;
1791 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1793 if (!IS_ERR(mmc->supply.vqmmc)) {
1794 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1797 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1803 usleep_range(5000, 5500);
1805 /* 3.3V regulator output should be stable within 5 ms */
1806 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1807 if (!(ctrl & SDHCI_CTRL_VDD_180))
1810 pr_warn("%s: 3.3V regulator output did not became stable\n",
1814 case MMC_SIGNAL_VOLTAGE_180:
1815 if (!IS_ERR(mmc->supply.vqmmc)) {
1816 ret = regulator_set_voltage(mmc->supply.vqmmc,
1819 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1826 * Enable 1.8V Signal Enable in the Host Control2
1829 ctrl |= SDHCI_CTRL_VDD_180;
1830 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1832 /* Some controller need to do more when switching */
1833 if (host->ops->voltage_switch)
1834 host->ops->voltage_switch(host);
1836 /* 1.8V regulator output should be stable within 5 ms */
1837 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1838 if (ctrl & SDHCI_CTRL_VDD_180)
1841 pr_warn("%s: 1.8V regulator output did not became stable\n",
1845 case MMC_SIGNAL_VOLTAGE_120:
1846 if (!IS_ERR(mmc->supply.vqmmc)) {
1847 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1850 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1857 /* No signal voltage switch required */
1862 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1863 struct mmc_ios *ios)
1865 struct sdhci_host *host = mmc_priv(mmc);
1868 if (host->version < SDHCI_SPEC_300)
1870 sdhci_runtime_pm_get(host);
1871 err = sdhci_do_start_signal_voltage_switch(host, ios);
1872 sdhci_runtime_pm_put(host);
1876 static int sdhci_card_busy(struct mmc_host *mmc)
1878 struct sdhci_host *host = mmc_priv(mmc);
1881 sdhci_runtime_pm_get(host);
1882 /* Check whether DAT[3:0] is 0000 */
1883 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1884 sdhci_runtime_pm_put(host);
1886 return !(present_state & SDHCI_DATA_LVL_MASK);
1889 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1891 struct sdhci_host *host = mmc_priv(mmc);
1892 unsigned long flags;
1894 spin_lock_irqsave(&host->lock, flags);
1895 host->flags |= SDHCI_HS400_TUNING;
1896 spin_unlock_irqrestore(&host->lock, flags);
1901 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1903 struct sdhci_host *host = mmc_priv(mmc);
1905 int tuning_loop_counter = MAX_TUNING_LOOP;
1907 unsigned long flags;
1908 unsigned int tuning_count = 0;
1911 sdhci_runtime_pm_get(host);
1912 spin_lock_irqsave(&host->lock, flags);
1914 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1915 host->flags &= ~SDHCI_HS400_TUNING;
1917 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1918 tuning_count = host->tuning_count;
1921 * The Host Controller needs tuning only in case of SDR104 mode
1922 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1923 * Capabilities register.
1924 * If the Host Controller supports the HS200 mode then the
1925 * tuning function has to be executed.
1927 switch (host->timing) {
1928 /* HS400 tuning is done in HS200 mode */
1929 case MMC_TIMING_MMC_HS400:
1933 case MMC_TIMING_MMC_HS200:
1935 * Periodic re-tuning for HS400 is not expected to be needed, so
1942 case MMC_TIMING_UHS_SDR104:
1945 case MMC_TIMING_UHS_SDR50:
1946 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1947 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1955 if (host->ops->platform_execute_tuning) {
1956 spin_unlock_irqrestore(&host->lock, flags);
1957 err = host->ops->platform_execute_tuning(host, opcode);
1958 sdhci_runtime_pm_put(host);
1962 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1963 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1964 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1967 * As per the Host Controller spec v3.00, tuning command
1968 * generates Buffer Read Ready interrupt, so enable that.
1970 * Note: The spec clearly says that when tuning sequence
1971 * is being performed, the controller does not generate
1972 * interrupts other than Buffer Read Ready interrupt. But
1973 * to make sure we don't hit a controller bug, we _only_
1974 * enable Buffer Read Ready interrupt here.
1976 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1977 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1980 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1981 * of loops reaches 40 times or a timeout of 150ms occurs.
1984 struct mmc_command cmd = {0};
1985 struct mmc_request mrq = {NULL};
1987 cmd.opcode = opcode;
1989 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1994 if (tuning_loop_counter-- == 0)
2001 * In response to CMD19, the card sends 64 bytes of tuning
2002 * block to the Host Controller. So we set the block size
2005 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2006 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2007 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2009 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2010 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2013 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2018 * The tuning block is sent by the card to the host controller.
2019 * So we set the TRNS_READ bit in the Transfer Mode register.
2020 * This also takes care of setting DMA Enable and Multi Block
2021 * Select in the same register to 0.
2023 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2025 sdhci_send_command(host, &cmd);
2030 spin_unlock_irqrestore(&host->lock, flags);
2031 /* Wait for Buffer Read Ready interrupt */
2032 wait_event_interruptible_timeout(host->buf_ready_int,
2033 (host->tuning_done == 1),
2034 msecs_to_jiffies(50));
2035 spin_lock_irqsave(&host->lock, flags);
2037 if (!host->tuning_done) {
2038 pr_info(DRIVER_NAME ": Timeout waiting for "
2039 "Buffer Read Ready interrupt during tuning "
2040 "procedure, falling back to fixed sampling "
2042 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2043 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2044 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2045 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2051 host->tuning_done = 0;
2053 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2055 /* eMMC spec does not require a delay between tuning cycles */
2056 if (opcode == MMC_SEND_TUNING_BLOCK)
2058 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2061 * The Host Driver has exhausted the maximum number of loops allowed,
2062 * so use fixed sampling frequency.
2064 if (tuning_loop_counter < 0) {
2065 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2066 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2069 pr_info(DRIVER_NAME ": Tuning procedure"
2070 " failed, falling back to fixed sampling"
2076 host->flags &= ~SDHCI_NEEDS_RETUNING;
2079 host->flags |= SDHCI_USING_RETUNING_TIMER;
2080 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2084 * In case tuning fails, host controllers which support re-tuning can
2085 * try tuning again at a later time, when the re-tuning timer expires.
2086 * So for these controllers, we return 0. Since there might be other
2087 * controllers who do not have this capability, we return error for
2088 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2089 * a retuning timer to do the retuning for the card.
2091 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2094 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2095 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2097 spin_unlock_irqrestore(&host->lock, flags);
2098 sdhci_runtime_pm_put(host);
2104 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2106 /* Host Controller v3.00 defines preset value registers */
2107 if (host->version < SDHCI_SPEC_300)
2111 * We only enable or disable Preset Value if they are not already
2112 * enabled or disabled respectively. Otherwise, we bail out.
2114 if (host->preset_enabled != enable) {
2115 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2118 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2120 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2122 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2125 host->flags |= SDHCI_PV_ENABLED;
2127 host->flags &= ~SDHCI_PV_ENABLED;
2129 host->preset_enabled = enable;
2133 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2136 struct sdhci_host *host = mmc_priv(mmc);
2137 struct mmc_data *data = mrq->data;
2139 if (host->flags & SDHCI_REQ_USE_DMA) {
2140 if (data->host_cookie)
2141 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2142 data->flags & MMC_DATA_WRITE ?
2143 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2144 mrq->data->host_cookie = 0;
2148 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2149 struct mmc_data *data,
2150 struct sdhci_host_next *next)
2154 if (!next && data->host_cookie &&
2155 data->host_cookie != host->next_data.cookie) {
2156 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2157 __func__, data->host_cookie, host->next_data.cookie);
2158 data->host_cookie = 0;
2161 /* Check if next job is already prepared */
2163 (!next && data->host_cookie != host->next_data.cookie)) {
2164 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2166 data->flags & MMC_DATA_WRITE ?
2167 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2170 sg_count = host->next_data.sg_count;
2171 host->next_data.sg_count = 0;
2179 next->sg_count = sg_count;
2180 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2182 host->sg_count = sg_count;
2187 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2190 struct sdhci_host *host = mmc_priv(mmc);
2192 if (mrq->data->host_cookie) {
2193 mrq->data->host_cookie = 0;
2197 if (host->flags & SDHCI_REQ_USE_DMA)
2198 if (sdhci_pre_dma_transfer(host,
2200 &host->next_data) < 0)
2201 mrq->data->host_cookie = 0;
2204 static void sdhci_card_event(struct mmc_host *mmc)
2206 struct sdhci_host *host = mmc_priv(mmc);
2207 unsigned long flags;
2210 /* First check if client has provided their own card event */
2211 if (host->ops->card_event)
2212 host->ops->card_event(host);
2214 present = sdhci_do_get_cd(host);
2216 spin_lock_irqsave(&host->lock, flags);
2218 /* Check host->mrq first in case we are runtime suspended */
2219 if (host->mrq && !present) {
2220 pr_err("%s: Card removed during transfer!\n",
2221 mmc_hostname(host->mmc));
2222 pr_err("%s: Resetting controller.\n",
2223 mmc_hostname(host->mmc));
2225 sdhci_do_reset(host, SDHCI_RESET_CMD);
2226 sdhci_do_reset(host, SDHCI_RESET_DATA);
2228 host->mrq->cmd->error = -ENOMEDIUM;
2229 tasklet_schedule(&host->finish_tasklet);
2232 spin_unlock_irqrestore(&host->lock, flags);
2235 static const struct mmc_host_ops sdhci_ops = {
2236 .request = sdhci_request,
2237 .post_req = sdhci_post_req,
2238 .pre_req = sdhci_pre_req,
2239 .set_ios = sdhci_set_ios,
2240 .get_cd = sdhci_get_cd,
2241 .get_ro = sdhci_get_ro,
2242 .hw_reset = sdhci_hw_reset,
2243 .enable_sdio_irq = sdhci_enable_sdio_irq,
2244 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2245 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2246 .execute_tuning = sdhci_execute_tuning,
2247 .card_event = sdhci_card_event,
2248 .card_busy = sdhci_card_busy,
2251 /*****************************************************************************\
2255 \*****************************************************************************/
2257 static void sdhci_tasklet_finish(unsigned long param)
2259 struct sdhci_host *host;
2260 unsigned long flags;
2261 struct mmc_request *mrq;
2263 host = (struct sdhci_host*)param;
2265 spin_lock_irqsave(&host->lock, flags);
2268 * If this tasklet gets rescheduled while running, it will
2269 * be run again afterwards but without any active request.
2272 spin_unlock_irqrestore(&host->lock, flags);
2276 del_timer(&host->timer);
2281 * The controller needs a reset of internal state machines
2282 * upon error conditions.
2284 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2285 ((mrq->cmd && mrq->cmd->error) ||
2286 (mrq->sbc && mrq->sbc->error) ||
2287 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2288 (mrq->data->stop && mrq->data->stop->error))) ||
2289 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2291 /* Some controllers need this kick or reset won't work here */
2292 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2293 /* This is to force an update */
2294 host->ops->set_clock(host, host->clock);
2296 /* Spec says we should do both at the same time, but Ricoh
2297 controllers do not like that. */
2298 sdhci_do_reset(host, SDHCI_RESET_CMD);
2299 sdhci_do_reset(host, SDHCI_RESET_DATA);
2306 #ifndef SDHCI_USE_LEDS_CLASS
2307 sdhci_deactivate_led(host);
2311 spin_unlock_irqrestore(&host->lock, flags);
2313 mmc_request_done(host->mmc, mrq);
2314 sdhci_runtime_pm_put(host);
2317 static void sdhci_timeout_timer(unsigned long data)
2319 struct sdhci_host *host;
2320 unsigned long flags;
2322 host = (struct sdhci_host*)data;
2324 spin_lock_irqsave(&host->lock, flags);
2327 pr_err("%s: Timeout waiting for hardware "
2328 "interrupt.\n", mmc_hostname(host->mmc));
2329 sdhci_dumpregs(host);
2332 host->data->error = -ETIMEDOUT;
2333 sdhci_finish_data(host);
2336 host->cmd->error = -ETIMEDOUT;
2338 host->mrq->cmd->error = -ETIMEDOUT;
2340 tasklet_schedule(&host->finish_tasklet);
2345 spin_unlock_irqrestore(&host->lock, flags);
2348 static void sdhci_tuning_timer(unsigned long data)
2350 struct sdhci_host *host;
2351 unsigned long flags;
2353 host = (struct sdhci_host *)data;
2355 spin_lock_irqsave(&host->lock, flags);
2357 host->flags |= SDHCI_NEEDS_RETUNING;
2359 spin_unlock_irqrestore(&host->lock, flags);
2362 /*****************************************************************************\
2364 * Interrupt handling *
2366 \*****************************************************************************/
2368 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2370 BUG_ON(intmask == 0);
2373 pr_err("%s: Got command interrupt 0x%08x even "
2374 "though no command operation was in progress.\n",
2375 mmc_hostname(host->mmc), (unsigned)intmask);
2376 sdhci_dumpregs(host);
2380 if (intmask & SDHCI_INT_TIMEOUT)
2381 host->cmd->error = -ETIMEDOUT;
2382 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2384 host->cmd->error = -EILSEQ;
2386 if (host->cmd->error) {
2387 tasklet_schedule(&host->finish_tasklet);
2392 * The host can send and interrupt when the busy state has
2393 * ended, allowing us to wait without wasting CPU cycles.
2394 * Unfortunately this is overloaded on the "data complete"
2395 * interrupt, so we need to take some care when handling
2398 * Note: The 1.0 specification is a bit ambiguous about this
2399 * feature so there might be some problems with older
2402 if (host->cmd->flags & MMC_RSP_BUSY) {
2403 if (host->cmd->data)
2404 DBG("Cannot wait for busy signal when also "
2405 "doing a data transfer");
2406 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2407 && !host->busy_handle) {
2408 /* Mark that command complete before busy is ended */
2409 host->busy_handle = 1;
2413 /* The controller does not support the end-of-busy IRQ,
2414 * fall through and take the SDHCI_INT_RESPONSE */
2415 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2416 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2417 *mask &= ~SDHCI_INT_DATA_END;
2420 if (intmask & SDHCI_INT_RESPONSE)
2421 sdhci_finish_command(host);
2424 #ifdef CONFIG_MMC_DEBUG
2425 static void sdhci_adma_show_error(struct sdhci_host *host)
2427 const char *name = mmc_hostname(host->mmc);
2428 void *desc = host->adma_table;
2430 sdhci_dumpregs(host);
2433 struct sdhci_adma2_64_desc *dma_desc = desc;
2435 if (host->flags & SDHCI_USE_64_BIT_DMA)
2436 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2437 name, desc, le32_to_cpu(dma_desc->addr_hi),
2438 le32_to_cpu(dma_desc->addr_lo),
2439 le16_to_cpu(dma_desc->len),
2440 le16_to_cpu(dma_desc->cmd));
2442 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2443 name, desc, le32_to_cpu(dma_desc->addr_lo),
2444 le16_to_cpu(dma_desc->len),
2445 le16_to_cpu(dma_desc->cmd));
2447 desc += host->desc_sz;
2449 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2454 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2457 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2460 BUG_ON(intmask == 0);
2462 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2463 if (intmask & SDHCI_INT_DATA_AVAIL) {
2464 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2465 if (command == MMC_SEND_TUNING_BLOCK ||
2466 command == MMC_SEND_TUNING_BLOCK_HS200) {
2467 host->tuning_done = 1;
2468 wake_up(&host->buf_ready_int);
2475 * The "data complete" interrupt is also used to
2476 * indicate that a busy state has ended. See comment
2477 * above in sdhci_cmd_irq().
2479 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2480 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2481 host->cmd->error = -ETIMEDOUT;
2482 tasklet_schedule(&host->finish_tasklet);
2485 if (intmask & SDHCI_INT_DATA_END) {
2487 * Some cards handle busy-end interrupt
2488 * before the command completed, so make
2489 * sure we do things in the proper order.
2491 if (host->busy_handle)
2492 sdhci_finish_command(host);
2494 host->busy_handle = 1;
2499 pr_err("%s: Got data interrupt 0x%08x even "
2500 "though no data operation was in progress.\n",
2501 mmc_hostname(host->mmc), (unsigned)intmask);
2502 sdhci_dumpregs(host);
2507 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2508 host->data->error = -ETIMEDOUT;
2509 else if (intmask & SDHCI_INT_DATA_END_BIT)
2510 host->data->error = -EILSEQ;
2511 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2512 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2514 host->data->error = -EILSEQ;
2515 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2516 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2517 sdhci_adma_show_error(host);
2518 host->data->error = -EIO;
2519 if (host->ops->adma_workaround)
2520 host->ops->adma_workaround(host, intmask);
2523 if (host->data->error)
2524 sdhci_finish_data(host);
2526 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2527 sdhci_transfer_pio(host);
2530 * We currently don't do anything fancy with DMA
2531 * boundaries, but as we can't disable the feature
2532 * we need to at least restart the transfer.
2534 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2535 * should return a valid address to continue from, but as
2536 * some controllers are faulty, don't trust them.
2538 if (intmask & SDHCI_INT_DMA_END) {
2539 u32 dmastart, dmanow;
2540 dmastart = sg_dma_address(host->data->sg);
2541 dmanow = dmastart + host->data->bytes_xfered;
2543 * Force update to the next DMA block boundary.
2546 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2547 SDHCI_DEFAULT_BOUNDARY_SIZE;
2548 host->data->bytes_xfered = dmanow - dmastart;
2549 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2551 mmc_hostname(host->mmc), dmastart,
2552 host->data->bytes_xfered, dmanow);
2553 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2556 if (intmask & SDHCI_INT_DATA_END) {
2559 * Data managed to finish before the
2560 * command completed. Make sure we do
2561 * things in the proper order.
2563 host->data_early = 1;
2565 sdhci_finish_data(host);
2571 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2573 irqreturn_t result = IRQ_NONE;
2574 struct sdhci_host *host = dev_id;
2575 u32 intmask, mask, unexpected = 0;
2578 spin_lock(&host->lock);
2580 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2581 spin_unlock(&host->lock);
2585 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2586 if (!intmask || intmask == 0xffffffff) {
2592 /* Clear selected interrupts. */
2593 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2594 SDHCI_INT_BUS_POWER);
2595 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2597 DBG("*** %s got interrupt: 0x%08x\n",
2598 mmc_hostname(host->mmc), intmask);
2600 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2601 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2605 * There is a observation on i.mx esdhc. INSERT
2606 * bit will be immediately set again when it gets
2607 * cleared, if a card is inserted. We have to mask
2608 * the irq to prevent interrupt storm which will
2609 * freeze the system. And the REMOVE gets the
2612 * More testing are needed here to ensure it works
2613 * for other platforms though.
2615 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2616 SDHCI_INT_CARD_REMOVE);
2617 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2618 SDHCI_INT_CARD_INSERT;
2619 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2620 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2622 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2623 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2625 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2626 SDHCI_INT_CARD_REMOVE);
2627 result = IRQ_WAKE_THREAD;
2630 if (intmask & SDHCI_INT_CMD_MASK)
2631 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2634 if (intmask & SDHCI_INT_DATA_MASK)
2635 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2637 if (intmask & SDHCI_INT_BUS_POWER)
2638 pr_err("%s: Card is consuming too much power!\n",
2639 mmc_hostname(host->mmc));
2641 if (intmask & SDHCI_INT_CARD_INT) {
2642 sdhci_enable_sdio_irq_nolock(host, false);
2643 host->thread_isr |= SDHCI_INT_CARD_INT;
2644 result = IRQ_WAKE_THREAD;
2647 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2648 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2649 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2650 SDHCI_INT_CARD_INT);
2653 unexpected |= intmask;
2654 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2657 if (result == IRQ_NONE)
2658 result = IRQ_HANDLED;
2660 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2661 } while (intmask && --max_loops);
2663 spin_unlock(&host->lock);
2666 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2667 mmc_hostname(host->mmc), unexpected);
2668 sdhci_dumpregs(host);
2674 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2676 struct sdhci_host *host = dev_id;
2677 unsigned long flags;
2680 spin_lock_irqsave(&host->lock, flags);
2681 isr = host->thread_isr;
2682 host->thread_isr = 0;
2683 spin_unlock_irqrestore(&host->lock, flags);
2685 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2686 sdhci_card_event(host->mmc);
2687 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2690 if (isr & SDHCI_INT_CARD_INT) {
2691 sdio_run_irqs(host->mmc);
2693 spin_lock_irqsave(&host->lock, flags);
2694 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2695 sdhci_enable_sdio_irq_nolock(host, true);
2696 spin_unlock_irqrestore(&host->lock, flags);
2699 return isr ? IRQ_HANDLED : IRQ_NONE;
2702 /*****************************************************************************\
2706 \*****************************************************************************/
2709 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2712 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2713 | SDHCI_WAKE_ON_INT;
2715 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2717 /* Avoid fake wake up */
2718 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2719 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2720 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2722 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2724 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2727 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2728 | SDHCI_WAKE_ON_INT;
2730 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2732 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2735 int sdhci_suspend_host(struct sdhci_host *host)
2737 sdhci_disable_card_detection(host);
2739 /* Disable tuning since we are suspending */
2740 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2741 del_timer_sync(&host->tuning_timer);
2742 host->flags &= ~SDHCI_NEEDS_RETUNING;
2745 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2747 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2748 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2749 free_irq(host->irq, host);
2751 sdhci_enable_irq_wakeups(host);
2752 enable_irq_wake(host->irq);
2757 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2759 int sdhci_resume_host(struct sdhci_host *host)
2763 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2764 if (host->ops->enable_dma)
2765 host->ops->enable_dma(host);
2768 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2769 ret = request_threaded_irq(host->irq, sdhci_irq,
2770 sdhci_thread_irq, IRQF_SHARED,
2771 mmc_hostname(host->mmc), host);
2775 sdhci_disable_irq_wakeups(host);
2776 disable_irq_wake(host->irq);
2779 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2780 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2781 /* Card keeps power but host controller does not */
2782 sdhci_init(host, 0);
2785 sdhci_do_set_ios(host, &host->mmc->ios);
2787 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2791 sdhci_enable_card_detection(host);
2793 /* Set the re-tuning expiration flag */
2794 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2795 host->flags |= SDHCI_NEEDS_RETUNING;
2800 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2802 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2804 return pm_runtime_get_sync(host->mmc->parent);
2807 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2809 pm_runtime_mark_last_busy(host->mmc->parent);
2810 return pm_runtime_put_autosuspend(host->mmc->parent);
2813 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2815 if (host->runtime_suspended || host->bus_on)
2817 host->bus_on = true;
2818 pm_runtime_get_noresume(host->mmc->parent);
2821 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2823 if (host->runtime_suspended || !host->bus_on)
2825 host->bus_on = false;
2826 pm_runtime_put_noidle(host->mmc->parent);
2829 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2831 unsigned long flags;
2833 /* Disable tuning since we are suspending */
2834 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2835 del_timer_sync(&host->tuning_timer);
2836 host->flags &= ~SDHCI_NEEDS_RETUNING;
2839 spin_lock_irqsave(&host->lock, flags);
2840 host->ier &= SDHCI_INT_CARD_INT;
2841 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2842 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2843 spin_unlock_irqrestore(&host->lock, flags);
2845 synchronize_hardirq(host->irq);
2847 spin_lock_irqsave(&host->lock, flags);
2848 host->runtime_suspended = true;
2849 spin_unlock_irqrestore(&host->lock, flags);
2853 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2855 int sdhci_runtime_resume_host(struct sdhci_host *host)
2857 unsigned long flags;
2858 int host_flags = host->flags;
2860 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2861 if (host->ops->enable_dma)
2862 host->ops->enable_dma(host);
2865 sdhci_init(host, 0);
2867 /* Force clock and power re-program */
2870 sdhci_do_set_ios(host, &host->mmc->ios);
2872 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2873 if ((host_flags & SDHCI_PV_ENABLED) &&
2874 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2875 spin_lock_irqsave(&host->lock, flags);
2876 sdhci_enable_preset_value(host, true);
2877 spin_unlock_irqrestore(&host->lock, flags);
2880 /* Set the re-tuning expiration flag */
2881 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2882 host->flags |= SDHCI_NEEDS_RETUNING;
2884 spin_lock_irqsave(&host->lock, flags);
2886 host->runtime_suspended = false;
2888 /* Enable SDIO IRQ */
2889 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2890 sdhci_enable_sdio_irq_nolock(host, true);
2892 /* Enable Card Detection */
2893 sdhci_enable_card_detection(host);
2895 spin_unlock_irqrestore(&host->lock, flags);
2899 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2901 #endif /* CONFIG_PM */
2903 /*****************************************************************************\
2905 * Device allocation/registration *
2907 \*****************************************************************************/
2909 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2912 struct mmc_host *mmc;
2913 struct sdhci_host *host;
2915 WARN_ON(dev == NULL);
2917 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2919 return ERR_PTR(-ENOMEM);
2921 host = mmc_priv(mmc);
2927 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2929 int sdhci_add_host(struct sdhci_host *host)
2931 struct mmc_host *mmc;
2932 u32 caps[2] = {0, 0};
2933 u32 max_current_caps;
2934 unsigned int ocr_avail;
2935 unsigned int override_timeout_clk;
2938 WARN_ON(host == NULL);
2945 host->quirks = debug_quirks;
2947 host->quirks2 = debug_quirks2;
2949 override_timeout_clk = host->timeout_clk;
2951 sdhci_do_reset(host, SDHCI_RESET_ALL);
2953 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2954 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2955 >> SDHCI_SPEC_VER_SHIFT;
2956 if (host->version > SDHCI_SPEC_300) {
2957 pr_err("%s: Unknown controller version (%d). "
2958 "You may experience problems.\n", mmc_hostname(mmc),
2962 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2963 sdhci_readl(host, SDHCI_CAPABILITIES);
2965 if (host->version >= SDHCI_SPEC_300)
2966 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2968 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2970 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2971 host->flags |= SDHCI_USE_SDMA;
2972 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2973 DBG("Controller doesn't have SDMA capability\n");
2975 host->flags |= SDHCI_USE_SDMA;
2977 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2978 (host->flags & SDHCI_USE_SDMA)) {
2979 DBG("Disabling DMA as it is marked broken\n");
2980 host->flags &= ~SDHCI_USE_SDMA;
2983 if ((host->version >= SDHCI_SPEC_200) &&
2984 (caps[0] & SDHCI_CAN_DO_ADMA2))
2985 host->flags |= SDHCI_USE_ADMA;
2987 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2988 (host->flags & SDHCI_USE_ADMA)) {
2989 DBG("Disabling ADMA as it is marked broken\n");
2990 host->flags &= ~SDHCI_USE_ADMA;
2994 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2995 * and *must* do 64-bit DMA. A driver has the opportunity to change
2996 * that during the first call to ->enable_dma(). Similarly
2997 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3000 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
3001 host->flags |= SDHCI_USE_64_BIT_DMA;
3003 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3004 if (host->ops->enable_dma) {
3005 if (host->ops->enable_dma(host)) {
3006 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3009 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3014 /* SDMA does not support 64-bit DMA */
3015 if (host->flags & SDHCI_USE_64_BIT_DMA)
3016 host->flags &= ~SDHCI_USE_SDMA;
3018 if (host->flags & SDHCI_USE_ADMA) {
3020 * The DMA descriptor table size is calculated as the maximum
3021 * number of segments times 2, to allow for an alignment
3022 * descriptor for each segment, plus 1 for a nop end descriptor,
3023 * all multipled by the descriptor size.
3025 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3026 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3027 SDHCI_ADMA2_64_DESC_SZ;
3028 host->align_buffer_sz = SDHCI_MAX_SEGS *
3029 SDHCI_ADMA2_64_ALIGN;
3030 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3031 host->align_sz = SDHCI_ADMA2_64_ALIGN;
3032 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3034 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3035 SDHCI_ADMA2_32_DESC_SZ;
3036 host->align_buffer_sz = SDHCI_MAX_SEGS *
3037 SDHCI_ADMA2_32_ALIGN;
3038 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3039 host->align_sz = SDHCI_ADMA2_32_ALIGN;
3040 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3042 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3043 host->adma_table_sz,
3046 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3047 if (!host->adma_table || !host->align_buffer) {
3048 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3049 host->adma_table, host->adma_addr);
3050 kfree(host->align_buffer);
3051 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3053 host->flags &= ~SDHCI_USE_ADMA;
3054 host->adma_table = NULL;
3055 host->align_buffer = NULL;
3056 } else if (host->adma_addr & host->align_mask) {
3057 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3059 host->flags &= ~SDHCI_USE_ADMA;
3060 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3061 host->adma_table, host->adma_addr);
3062 kfree(host->align_buffer);
3063 host->adma_table = NULL;
3064 host->align_buffer = NULL;
3069 * If we use DMA, then it's up to the caller to set the DMA
3070 * mask, but PIO does not need the hw shim so we set a new
3071 * mask here in that case.
3073 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3074 host->dma_mask = DMA_BIT_MASK(64);
3075 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3078 if (host->version >= SDHCI_SPEC_300)
3079 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3080 >> SDHCI_CLOCK_BASE_SHIFT;
3082 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3083 >> SDHCI_CLOCK_BASE_SHIFT;
3085 host->max_clk *= 1000000;
3086 if (host->max_clk == 0 || host->quirks &
3087 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3088 if (!host->ops->get_max_clock) {
3089 pr_err("%s: Hardware doesn't specify base clock "
3090 "frequency.\n", mmc_hostname(mmc));
3093 host->max_clk = host->ops->get_max_clock(host);
3096 host->next_data.cookie = 1;
3098 * In case of Host Controller v3.00, find out whether clock
3099 * multiplier is supported.
3101 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3102 SDHCI_CLOCK_MUL_SHIFT;
3105 * In case the value in Clock Multiplier is 0, then programmable
3106 * clock mode is not supported, otherwise the actual clock
3107 * multiplier is one more than the value of Clock Multiplier
3108 * in the Capabilities Register.
3114 * Set host parameters.
3116 mmc->ops = &sdhci_ops;
3117 mmc->f_max = host->max_clk;
3118 if (host->ops->get_min_clock)
3119 mmc->f_min = host->ops->get_min_clock(host);
3120 else if (host->version >= SDHCI_SPEC_300) {
3121 if (host->clk_mul) {
3122 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3123 mmc->f_max = host->max_clk * host->clk_mul;
3125 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3127 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3129 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3130 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3131 SDHCI_TIMEOUT_CLK_SHIFT;
3132 if (host->timeout_clk == 0) {
3133 if (host->ops->get_timeout_clock) {
3135 host->ops->get_timeout_clock(host);
3137 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3143 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3144 host->timeout_clk *= 1000;
3146 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3147 host->ops->get_max_timeout_count(host) : 1 << 27;
3148 mmc->max_busy_timeout /= host->timeout_clk;
3151 if (override_timeout_clk)
3152 host->timeout_clk = override_timeout_clk;
3154 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3155 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3157 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3158 host->flags |= SDHCI_AUTO_CMD12;
3160 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3161 if ((host->version >= SDHCI_SPEC_300) &&
3162 ((host->flags & SDHCI_USE_ADMA) ||
3163 !(host->flags & SDHCI_USE_SDMA))) {
3164 host->flags |= SDHCI_AUTO_CMD23;
3165 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3167 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3171 * A controller may support 8-bit width, but the board itself
3172 * might not have the pins brought out. Boards that support
3173 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3174 * their platform code before calling sdhci_add_host(), and we
3175 * won't assume 8-bit width for hosts without that CAP.
3177 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3178 mmc->caps |= MMC_CAP_4_BIT_DATA;
3180 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3181 mmc->caps &= ~MMC_CAP_CMD23;
3183 if (caps[0] & SDHCI_CAN_DO_HISPD)
3184 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3186 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3187 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3188 mmc->caps |= MMC_CAP_NEEDS_POLL;
3190 /* If there are external regulators, get them */
3191 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3192 return -EPROBE_DEFER;
3194 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3195 if (!IS_ERR(mmc->supply.vqmmc)) {
3196 ret = regulator_enable(mmc->supply.vqmmc);
3197 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3199 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3200 SDHCI_SUPPORT_SDR50 |
3201 SDHCI_SUPPORT_DDR50);
3203 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3204 mmc_hostname(mmc), ret);
3205 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3209 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3210 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3211 SDHCI_SUPPORT_DDR50);
3213 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3214 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3215 SDHCI_SUPPORT_DDR50))
3216 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3218 /* SDR104 supports also implies SDR50 support */
3219 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3220 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3221 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3222 * field can be promoted to support HS200.
3224 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3225 mmc->caps2 |= MMC_CAP2_HS200;
3226 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3227 mmc->caps |= MMC_CAP_UHS_SDR50;
3229 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3230 (caps[1] & SDHCI_SUPPORT_HS400))
3231 mmc->caps2 |= MMC_CAP2_HS400;
3233 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3234 (IS_ERR(mmc->supply.vqmmc) ||
3235 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3237 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3239 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3240 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3241 mmc->caps |= MMC_CAP_UHS_DDR50;
3243 /* Does the host need tuning for SDR50? */
3244 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3245 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3247 /* Does the host need tuning for SDR104 / HS200? */
3248 if (mmc->caps2 & MMC_CAP2_HS200)
3249 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3251 /* Driver Type(s) (A, C, D) supported by the host */
3252 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3253 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3254 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3255 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3256 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3257 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3259 /* Initial value for re-tuning timer count */
3260 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3261 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3264 * In case Re-tuning Timer is not disabled, the actual value of
3265 * re-tuning timer will be 2 ^ (n - 1).
3267 if (host->tuning_count)
3268 host->tuning_count = 1 << (host->tuning_count - 1);
3270 /* Re-tuning mode supported by the Host Controller */
3271 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3272 SDHCI_RETUNING_MODE_SHIFT;
3277 * According to SD Host Controller spec v3.00, if the Host System
3278 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3279 * the value is meaningful only if Voltage Support in the Capabilities
3280 * register is set. The actual current value is 4 times the register
3283 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3284 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3285 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3288 /* convert to SDHCI_MAX_CURRENT format */
3289 curr = curr/1000; /* convert to mA */
3290 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3292 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3294 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3295 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3296 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3300 if (caps[0] & SDHCI_CAN_VDD_330) {
3301 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3303 mmc->max_current_330 = ((max_current_caps &
3304 SDHCI_MAX_CURRENT_330_MASK) >>
3305 SDHCI_MAX_CURRENT_330_SHIFT) *
3306 SDHCI_MAX_CURRENT_MULTIPLIER;
3308 if (caps[0] & SDHCI_CAN_VDD_300) {
3309 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3311 mmc->max_current_300 = ((max_current_caps &
3312 SDHCI_MAX_CURRENT_300_MASK) >>
3313 SDHCI_MAX_CURRENT_300_SHIFT) *
3314 SDHCI_MAX_CURRENT_MULTIPLIER;
3316 if (caps[0] & SDHCI_CAN_VDD_180) {
3317 ocr_avail |= MMC_VDD_165_195;
3319 mmc->max_current_180 = ((max_current_caps &
3320 SDHCI_MAX_CURRENT_180_MASK) >>
3321 SDHCI_MAX_CURRENT_180_SHIFT) *
3322 SDHCI_MAX_CURRENT_MULTIPLIER;
3325 /* If OCR set by external regulators, use it instead */
3327 ocr_avail = mmc->ocr_avail;
3330 ocr_avail &= host->ocr_mask;
3332 mmc->ocr_avail = ocr_avail;
3333 mmc->ocr_avail_sdio = ocr_avail;
3334 if (host->ocr_avail_sdio)
3335 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3336 mmc->ocr_avail_sd = ocr_avail;
3337 if (host->ocr_avail_sd)
3338 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3339 else /* normal SD controllers don't support 1.8V */
3340 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3341 mmc->ocr_avail_mmc = ocr_avail;
3342 if (host->ocr_avail_mmc)
3343 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3345 if (mmc->ocr_avail == 0) {
3346 pr_err("%s: Hardware doesn't report any "
3347 "support voltages.\n", mmc_hostname(mmc));
3351 spin_lock_init(&host->lock);
3354 * Maximum number of segments. Depends on if the hardware
3355 * can do scatter/gather or not.
3357 if (host->flags & SDHCI_USE_ADMA)
3358 mmc->max_segs = SDHCI_MAX_SEGS;
3359 else if (host->flags & SDHCI_USE_SDMA)
3362 mmc->max_segs = SDHCI_MAX_SEGS;
3365 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3366 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3369 mmc->max_req_size = 524288;
3372 * Maximum segment size. Could be one segment with the maximum number
3373 * of bytes. When doing hardware scatter/gather, each entry cannot
3374 * be larger than 64 KiB though.
3376 if (host->flags & SDHCI_USE_ADMA) {
3377 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3378 mmc->max_seg_size = 65535;
3380 mmc->max_seg_size = 65536;
3382 mmc->max_seg_size = mmc->max_req_size;
3386 * Maximum block size. This varies from controller to controller and
3387 * is specified in the capabilities register.
3389 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3390 mmc->max_blk_size = 2;
3392 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3393 SDHCI_MAX_BLOCK_SHIFT;
3394 if (mmc->max_blk_size >= 3) {
3395 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3397 mmc->max_blk_size = 0;
3401 mmc->max_blk_size = 512 << mmc->max_blk_size;
3404 * Maximum block count.
3406 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3411 tasklet_init(&host->finish_tasklet,
3412 sdhci_tasklet_finish, (unsigned long)host);
3414 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3416 init_waitqueue_head(&host->buf_ready_int);
3418 if (host->version >= SDHCI_SPEC_300) {
3419 /* Initialize re-tuning timer */
3420 init_timer(&host->tuning_timer);
3421 host->tuning_timer.data = (unsigned long)host;
3422 host->tuning_timer.function = sdhci_tuning_timer;
3425 sdhci_init(host, 0);
3427 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3428 IRQF_SHARED, mmc_hostname(mmc), host);
3430 pr_err("%s: Failed to request IRQ %d: %d\n",
3431 mmc_hostname(mmc), host->irq, ret);
3435 #ifdef CONFIG_MMC_DEBUG
3436 sdhci_dumpregs(host);
3439 #ifdef SDHCI_USE_LEDS_CLASS
3440 snprintf(host->led_name, sizeof(host->led_name),
3441 "%s::", mmc_hostname(mmc));
3442 host->led.name = host->led_name;
3443 host->led.brightness = LED_OFF;
3444 host->led.default_trigger = mmc_hostname(mmc);
3445 host->led.brightness_set = sdhci_led_control;
3447 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3449 pr_err("%s: Failed to register LED device: %d\n",
3450 mmc_hostname(mmc), ret);
3459 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3460 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3461 (host->flags & SDHCI_USE_ADMA) ?
3462 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3463 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3465 sdhci_enable_card_detection(host);
3469 #ifdef SDHCI_USE_LEDS_CLASS
3471 sdhci_do_reset(host, SDHCI_RESET_ALL);
3472 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3473 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3474 free_irq(host->irq, host);
3477 tasklet_kill(&host->finish_tasklet);
3482 EXPORT_SYMBOL_GPL(sdhci_add_host);
3484 void sdhci_remove_host(struct sdhci_host *host, int dead)
3486 struct mmc_host *mmc = host->mmc;
3487 unsigned long flags;
3490 spin_lock_irqsave(&host->lock, flags);
3492 host->flags |= SDHCI_DEVICE_DEAD;
3495 pr_err("%s: Controller removed during "
3496 " transfer!\n", mmc_hostname(mmc));
3498 host->mrq->cmd->error = -ENOMEDIUM;
3499 tasklet_schedule(&host->finish_tasklet);
3502 spin_unlock_irqrestore(&host->lock, flags);
3505 sdhci_disable_card_detection(host);
3507 mmc_remove_host(mmc);
3509 #ifdef SDHCI_USE_LEDS_CLASS
3510 led_classdev_unregister(&host->led);
3514 sdhci_do_reset(host, SDHCI_RESET_ALL);
3516 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3517 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3518 free_irq(host->irq, host);
3520 del_timer_sync(&host->timer);
3522 tasklet_kill(&host->finish_tasklet);
3524 if (!IS_ERR(mmc->supply.vqmmc))
3525 regulator_disable(mmc->supply.vqmmc);
3527 if (host->adma_table)
3528 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3529 host->adma_table, host->adma_addr);
3530 kfree(host->align_buffer);
3532 host->adma_table = NULL;
3533 host->align_buffer = NULL;
3536 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3538 void sdhci_free_host(struct sdhci_host *host)
3540 mmc_free_host(host->mmc);
3543 EXPORT_SYMBOL_GPL(sdhci_free_host);
3545 /*****************************************************************************\
3547 * Driver init/exit *
3549 \*****************************************************************************/
3551 static int __init sdhci_drv_init(void)
3554 ": Secure Digital Host Controller Interface driver\n");
3555 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3560 static void __exit sdhci_drv_exit(void)
3564 module_init(sdhci_drv_init);
3565 module_exit(sdhci_drv_exit);
3567 module_param(debug_quirks, uint, 0444);
3568 module_param(debug_quirks2, uint, 0444);
3570 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3571 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3572 MODULE_LICENSE("GPL");
3574 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3575 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");