2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
46 #define MAX_TUNING_LOOP 40
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
51 static void sdhci_finish_data(struct sdhci_host *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data);
58 static int sdhci_do_get_cd(struct sdhci_host *host);
61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
82 static void sdhci_dumpregs(struct sdhci_host *host)
84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host->mmc));
87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host, SDHCI_CAPABILITIES),
116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host, SDHCI_COMMAND),
119 sdhci_readl(host, SDHCI_MAX_CURRENT));
120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
135 pr_debug(DRIVER_NAME ": ===========================================\n");
138 /*****************************************************************************\
140 * Low level functions *
142 \*****************************************************************************/
144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
166 static void sdhci_enable_card_detection(struct sdhci_host *host)
168 sdhci_set_card_detection(host, true);
171 static void sdhci_disable_card_detection(struct sdhci_host *host)
173 sdhci_set_card_detection(host, false);
176 void sdhci_reset(struct sdhci_host *host, u8 mask)
178 unsigned long timeout;
180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
182 if (mask & SDHCI_RESET_ALL) {
184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
189 /* Wait max 100 ms */
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
204 EXPORT_SYMBOL_GPL(sdhci_reset);
206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
209 if (!sdhci_do_get_cd(host))
213 host->ops->reset(host, mask);
215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
228 static void sdhci_init(struct sdhci_host *host, int soft)
231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
233 sdhci_do_reset(host, SDHCI_RESET_ALL);
235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
245 /* force clock reconfiguration */
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
251 static void sdhci_reinit(struct sdhci_host *host)
254 sdhci_enable_card_detection(host);
257 static void sdhci_activate_led(struct sdhci_host *host)
261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
262 ctrl |= SDHCI_CTRL_LED;
263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
266 static void sdhci_deactivate_led(struct sdhci_host *host)
270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
271 ctrl &= ~SDHCI_CTRL_LED;
272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
282 spin_lock_irqsave(&host->lock, flags);
284 if (host->runtime_suspended)
287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
290 sdhci_activate_led(host);
292 spin_unlock_irqrestore(&host->lock, flags);
296 /*****************************************************************************\
300 \*****************************************************************************/
302 static void sdhci_read_block_pio(struct sdhci_host *host)
305 size_t blksize, len, chunk;
306 u32 uninitialized_var(scratch);
309 DBG("PIO reading\n");
311 blksize = host->data->blksz;
314 local_irq_save(flags);
317 BUG_ON(!sg_miter_next(&host->sg_miter));
319 len = min(host->sg_miter.length, blksize);
322 host->sg_miter.consumed = len;
324 buf = host->sg_miter.addr;
328 scratch = sdhci_readl(host, SDHCI_BUFFER);
332 *buf = scratch & 0xFF;
341 sg_miter_stop(&host->sg_miter);
343 local_irq_restore(flags);
346 static void sdhci_write_block_pio(struct sdhci_host *host)
349 size_t blksize, len, chunk;
353 DBG("PIO writing\n");
355 blksize = host->data->blksz;
359 local_irq_save(flags);
362 BUG_ON(!sg_miter_next(&host->sg_miter));
364 len = min(host->sg_miter.length, blksize);
367 host->sg_miter.consumed = len;
369 buf = host->sg_miter.addr;
372 scratch |= (u32)*buf << (chunk * 8);
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
379 sdhci_writel(host, scratch, SDHCI_BUFFER);
386 sg_miter_stop(&host->sg_miter);
388 local_irq_restore(flags);
391 static void sdhci_transfer_pio(struct sdhci_host *host)
397 if (host->blocks == 0)
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
403 mask = SDHCI_SPACE_AVAILABLE;
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
421 sdhci_write_block_pio(host);
424 if (host->blocks == 0)
428 DBG("PIO transfer complete.\n");
431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
433 local_irq_save(*flags);
434 return kmap_atomic(sg_page(sg)) + sg->offset;
437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
439 kunmap_atomic(buffer);
440 local_irq_restore(*flags);
443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
446 struct sdhci_adma2_64_desc *dma_desc = desc;
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
457 static void sdhci_adma_mark_end(void *desc)
459 struct sdhci_adma2_64_desc *dma_desc = desc;
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
473 dma_addr_t align_addr;
476 struct scatterlist *sg;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
489 direction = DMA_TO_DEVICE;
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, host->align_buffer_sz, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
495 BUG_ON(host->align_addr & host->align_mask);
497 host->sg_count = sdhci_pre_dma_transfer(host, data);
498 if (host->sg_count < 0)
501 desc = host->adma_table;
502 align = host->align_buffer;
504 align_addr = host->align_addr;
506 for_each_sg(data->sg, sg, host->sg_count, i) {
507 addr = sg_dma_address(sg);
508 len = sg_dma_len(sg);
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
517 offset = (host->align_sz - (addr & host->align_mask)) &
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 memcpy(align, buffer, offset);
523 sdhci_kunmap_atomic(buffer, &flags);
527 sdhci_adma_write_desc(host, desc, align_addr, offset,
530 BUG_ON(offset > 65536);
532 align += host->align_sz;
533 align_addr += host->align_sz;
535 desc += host->desc_sz;
545 sdhci_adma_write_desc(host, desc, addr, len,
547 desc += host->desc_sz;
551 * If this triggers then we have a calculation bug
554 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
557 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
559 * Mark the last descriptor as the terminating descriptor
561 if (desc != host->adma_table) {
562 desc -= host->desc_sz;
563 sdhci_adma_mark_end(desc);
567 * Add a terminating entry.
570 /* nop, end, valid */
571 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
575 * Resync align buffer as we might have changed it.
577 if (data->flags & MMC_DATA_WRITE) {
578 dma_sync_single_for_device(mmc_dev(host->mmc),
579 host->align_addr, host->align_buffer_sz, direction);
585 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
586 host->align_buffer_sz, direction);
591 static void sdhci_adma_table_post(struct sdhci_host *host,
592 struct mmc_data *data)
596 struct scatterlist *sg;
603 if (data->flags & MMC_DATA_READ)
604 direction = DMA_FROM_DEVICE;
606 direction = DMA_TO_DEVICE;
608 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
609 host->align_buffer_sz, direction);
611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned = false;
613 for_each_sg(data->sg, sg, host->sg_count, i)
614 if (sg_dma_address(sg) & host->align_mask) {
615 has_unaligned = true;
619 if (has_unaligned && data->flags & MMC_DATA_READ) {
620 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
621 data->sg_len, direction);
623 align = host->align_buffer;
625 for_each_sg(data->sg, sg, host->sg_count, i) {
626 if (sg_dma_address(sg) & host->align_mask) {
627 size = host->align_sz -
628 (sg_dma_address(sg) & host->align_mask);
630 buffer = sdhci_kmap_atomic(sg, &flags);
631 memcpy(buffer, align, size);
632 sdhci_kunmap_atomic(buffer, &flags);
634 align += host->align_sz;
639 if (data->host_cookie == COOKIE_MAPPED) {
640 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
642 data->host_cookie = COOKIE_UNMAPPED;
646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
649 struct mmc_data *data = cmd->data;
650 unsigned target_timeout, current_timeout;
653 * If the host controller provides us with an incorrect timeout
654 * value, just skip the check and use 0xE. The hardware may take
655 * longer to time out, but that's much better than having a too-short
658 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
661 /* Unspecified timeout, assume max */
662 if (!data && !cmd->busy_timeout)
667 target_timeout = cmd->busy_timeout * 1000;
669 target_timeout = data->timeout_ns / 1000;
671 target_timeout += data->timeout_clks / host->clock;
675 * Figure out needed cycles.
676 * We do this in steps in order to fit inside a 32 bit int.
677 * The first step is the minimum timeout, which will have a
678 * minimum resolution of 6 bits:
679 * (1) 2^13*1000 > 2^22,
680 * (2) host->timeout_clk < 2^16
685 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
686 while (current_timeout < target_timeout) {
688 current_timeout <<= 1;
694 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
695 mmc_hostname(host->mmc), count, cmd->opcode);
702 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
704 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
705 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
707 if (host->flags & SDHCI_REQ_USE_DMA)
708 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
710 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
712 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
713 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
716 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
720 if (host->ops->set_timeout) {
721 host->ops->set_timeout(host, cmd);
723 count = sdhci_calc_timeout(host, cmd);
724 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
728 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
731 struct mmc_data *data = cmd->data;
736 if (data || (cmd->flags & MMC_RSP_BUSY))
737 sdhci_set_timeout(host, cmd);
743 BUG_ON(data->blksz * data->blocks > 524288);
744 BUG_ON(data->blksz > host->mmc->max_blk_size);
745 BUG_ON(data->blocks > 65535);
748 host->data_early = 0;
749 host->data->bytes_xfered = 0;
751 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
752 host->flags |= SDHCI_REQ_USE_DMA;
755 * FIXME: This doesn't account for merging when mapping the
758 if (host->flags & SDHCI_REQ_USE_DMA) {
760 struct scatterlist *sg;
763 if (host->flags & SDHCI_USE_ADMA) {
764 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
767 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
771 if (unlikely(broken)) {
772 for_each_sg(data->sg, sg, data->sg_len, i) {
773 if (sg->length & 0x3) {
774 DBG("Reverting to PIO because of "
775 "transfer size (%d)\n",
777 host->flags &= ~SDHCI_REQ_USE_DMA;
785 * The assumption here being that alignment is the same after
786 * translation to device address space.
788 if (host->flags & SDHCI_REQ_USE_DMA) {
790 struct scatterlist *sg;
793 if (host->flags & SDHCI_USE_ADMA) {
795 * As we use 3 byte chunks to work around
796 * alignment problems, we need to check this
799 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
806 if (unlikely(broken)) {
807 for_each_sg(data->sg, sg, data->sg_len, i) {
808 if (sg->offset & 0x3) {
809 DBG("Reverting to PIO because of "
811 host->flags &= ~SDHCI_REQ_USE_DMA;
818 if (host->flags & SDHCI_REQ_USE_DMA) {
819 if (host->flags & SDHCI_USE_ADMA) {
820 ret = sdhci_adma_table_pre(host, data);
823 * This only happens when someone fed
824 * us an invalid request.
827 host->flags &= ~SDHCI_REQ_USE_DMA;
829 sdhci_writel(host, host->adma_addr,
831 if (host->flags & SDHCI_USE_64_BIT_DMA)
833 (u64)host->adma_addr >> 32,
834 SDHCI_ADMA_ADDRESS_HI);
839 sg_cnt = sdhci_pre_dma_transfer(host, data);
842 * This only happens when someone fed
843 * us an invalid request.
846 host->flags &= ~SDHCI_REQ_USE_DMA;
848 WARN_ON(sg_cnt != 1);
849 sdhci_writel(host, sg_dma_address(data->sg),
856 * Always adjust the DMA selection as some controllers
857 * (e.g. JMicron) can't do PIO properly when the selection
860 if (host->version >= SDHCI_SPEC_200) {
861 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
862 ctrl &= ~SDHCI_CTRL_DMA_MASK;
863 if ((host->flags & SDHCI_REQ_USE_DMA) &&
864 (host->flags & SDHCI_USE_ADMA)) {
865 if (host->flags & SDHCI_USE_64_BIT_DMA)
866 ctrl |= SDHCI_CTRL_ADMA64;
868 ctrl |= SDHCI_CTRL_ADMA32;
870 ctrl |= SDHCI_CTRL_SDMA;
872 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
875 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
878 flags = SG_MITER_ATOMIC;
879 if (host->data->flags & MMC_DATA_READ)
880 flags |= SG_MITER_TO_SG;
882 flags |= SG_MITER_FROM_SG;
883 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
884 host->blocks = data->blocks;
887 sdhci_set_transfer_irqs(host);
889 /* Set the DMA boundary value and block size */
890 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
891 data->blksz), SDHCI_BLOCK_SIZE);
892 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
896 struct mmc_command *cmd)
899 struct mmc_data *data = cmd->data;
903 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
904 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
906 /* clear Auto CMD settings for no data CMDs */
907 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
908 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
909 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
914 WARN_ON(!host->data);
916 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
917 mode = SDHCI_TRNS_BLK_CNT_EN;
919 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
920 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
922 * If we are sending CMD23, CMD12 never gets sent
923 * on successful completion (so no Auto-CMD12).
925 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
926 (cmd->opcode != SD_IO_RW_EXTENDED))
927 mode |= SDHCI_TRNS_AUTO_CMD12;
928 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
929 mode |= SDHCI_TRNS_AUTO_CMD23;
930 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
934 if (data->flags & MMC_DATA_READ)
935 mode |= SDHCI_TRNS_READ;
936 if (host->flags & SDHCI_REQ_USE_DMA)
937 mode |= SDHCI_TRNS_DMA;
939 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
942 static void sdhci_finish_data(struct sdhci_host *host)
944 struct mmc_data *data;
951 if (host->flags & SDHCI_REQ_USE_DMA) {
952 if (host->flags & SDHCI_USE_ADMA)
953 sdhci_adma_table_post(host, data);
955 if (data->host_cookie == COOKIE_MAPPED) {
956 dma_unmap_sg(mmc_dev(host->mmc),
957 data->sg, data->sg_len,
958 (data->flags & MMC_DATA_READ) ?
959 DMA_FROM_DEVICE : DMA_TO_DEVICE);
960 data->host_cookie = COOKIE_UNMAPPED;
966 * The specification states that the block count register must
967 * be updated, but it does not specify at what point in the
968 * data flow. That makes the register entirely useless to read
969 * back so we have to assume that nothing made it to the card
970 * in the event of an error.
973 data->bytes_xfered = 0;
975 data->bytes_xfered = data->blksz * data->blocks;
978 * Need to send CMD12 if -
979 * a) open-ended multiblock transfer (no CMD23)
980 * b) error in multiblock transfer
987 * The controller needs a reset of internal state machines
988 * upon error conditions.
991 sdhci_do_reset(host, SDHCI_RESET_CMD);
992 sdhci_do_reset(host, SDHCI_RESET_DATA);
995 sdhci_send_command(host, data->stop);
997 tasklet_schedule(&host->finish_tasklet);
1000 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1004 unsigned long timeout;
1008 /* Wait max 10 ms */
1011 mask = SDHCI_CMD_INHIBIT;
1012 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1013 mask |= SDHCI_DATA_INHIBIT;
1015 /* We shouldn't wait for data inihibit for stop commands, even
1016 though they might use busy signaling */
1017 if (host->mrq->data && (cmd == host->mrq->data->stop))
1018 mask &= ~SDHCI_DATA_INHIBIT;
1020 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1022 pr_err("%s: Controller never released "
1023 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1024 sdhci_dumpregs(host);
1026 tasklet_schedule(&host->finish_tasklet);
1034 if (!cmd->data && cmd->busy_timeout > 9000)
1035 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1038 mod_timer(&host->timer, timeout);
1041 host->busy_handle = 0;
1043 sdhci_prepare_data(host, cmd);
1045 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1047 sdhci_set_transfer_mode(host, cmd);
1049 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1050 pr_err("%s: Unsupported response type!\n",
1051 mmc_hostname(host->mmc));
1052 cmd->error = -EINVAL;
1053 tasklet_schedule(&host->finish_tasklet);
1057 if (!(cmd->flags & MMC_RSP_PRESENT))
1058 flags = SDHCI_CMD_RESP_NONE;
1059 else if (cmd->flags & MMC_RSP_136)
1060 flags = SDHCI_CMD_RESP_LONG;
1061 else if (cmd->flags & MMC_RSP_BUSY)
1062 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1064 flags = SDHCI_CMD_RESP_SHORT;
1066 if (cmd->flags & MMC_RSP_CRC)
1067 flags |= SDHCI_CMD_CRC;
1068 if (cmd->flags & MMC_RSP_OPCODE)
1069 flags |= SDHCI_CMD_INDEX;
1071 /* CMD19 is special in that the Data Present Select should be set */
1072 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1073 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1074 flags |= SDHCI_CMD_DATA;
1076 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1078 EXPORT_SYMBOL_GPL(sdhci_send_command);
1080 static void sdhci_finish_command(struct sdhci_host *host)
1084 BUG_ON(host->cmd == NULL);
1086 if (host->cmd->flags & MMC_RSP_PRESENT) {
1087 if (host->cmd->flags & MMC_RSP_136) {
1088 /* CRC is stripped so we need to do some shifting. */
1089 for (i = 0;i < 4;i++) {
1090 host->cmd->resp[i] = sdhci_readl(host,
1091 SDHCI_RESPONSE + (3-i)*4) << 8;
1093 host->cmd->resp[i] |=
1095 SDHCI_RESPONSE + (3-i)*4-1);
1098 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1102 host->cmd->error = 0;
1104 /* Finished CMD23, now send actual command. */
1105 if (host->cmd == host->mrq->sbc) {
1107 sdhci_send_command(host, host->mrq->cmd);
1110 /* Processed actual command. */
1111 if (host->data && host->data_early)
1112 sdhci_finish_data(host);
1114 if (!host->cmd->data)
1115 tasklet_schedule(&host->finish_tasklet);
1121 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1125 switch (host->timing) {
1126 case MMC_TIMING_UHS_SDR12:
1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1129 case MMC_TIMING_UHS_SDR25:
1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1132 case MMC_TIMING_UHS_SDR50:
1133 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1135 case MMC_TIMING_UHS_SDR104:
1136 case MMC_TIMING_MMC_HS200:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1139 case MMC_TIMING_UHS_DDR50:
1140 case MMC_TIMING_MMC_DDR52:
1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1143 case MMC_TIMING_MMC_HS400:
1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1147 pr_warn("%s: Invalid UHS-I mode selected\n",
1148 mmc_hostname(host->mmc));
1149 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1155 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1157 int div = 0; /* Initialized for compiler warning */
1158 int real_div = div, clk_mul = 1;
1160 unsigned long timeout;
1161 bool switch_base_clk = false;
1163 host->mmc->actual_clock = 0;
1165 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1166 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1172 if (host->version >= SDHCI_SPEC_300) {
1173 if (host->preset_enabled) {
1176 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1177 pre_val = sdhci_get_preset_value(host);
1178 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1179 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1180 if (host->clk_mul &&
1181 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1182 clk = SDHCI_PROG_CLOCK_MODE;
1184 clk_mul = host->clk_mul;
1186 real_div = max_t(int, 1, div << 1);
1192 * Check if the Host Controller supports Programmable Clock
1195 if (host->clk_mul) {
1196 for (div = 1; div <= 1024; div++) {
1197 if ((host->max_clk * host->clk_mul / div)
1201 if ((host->max_clk * host->clk_mul / div) <= clock) {
1203 * Set Programmable Clock Mode in the Clock
1206 clk = SDHCI_PROG_CLOCK_MODE;
1208 clk_mul = host->clk_mul;
1212 * Divisor can be too small to reach clock
1213 * speed requirement. Then use the base clock.
1215 switch_base_clk = true;
1219 if (!host->clk_mul || switch_base_clk) {
1220 /* Version 3.00 divisors must be a multiple of 2. */
1221 if (host->max_clk <= clock)
1224 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1226 if ((host->max_clk / div) <= clock)
1232 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1233 && !div && host->max_clk <= 25000000)
1237 /* Version 2.00 divisors must be a power of 2. */
1238 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1239 if ((host->max_clk / div) <= clock)
1248 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1249 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1250 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1251 << SDHCI_DIVIDER_HI_SHIFT;
1252 clk |= SDHCI_CLOCK_INT_EN;
1253 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1255 /* Wait max 20 ms */
1257 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1258 & SDHCI_CLOCK_INT_STABLE)) {
1260 pr_err("%s: Internal clock never "
1261 "stabilised.\n", mmc_hostname(host->mmc));
1262 sdhci_dumpregs(host);
1269 clk |= SDHCI_CLOCK_CARD_EN;
1270 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1272 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1274 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1277 struct mmc_host *mmc = host->mmc;
1280 if (!IS_ERR(mmc->supply.vmmc)) {
1281 spin_unlock_irq(&host->lock);
1282 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1283 spin_lock_irq(&host->lock);
1285 if (mode != MMC_POWER_OFF)
1286 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1288 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1293 if (mode != MMC_POWER_OFF) {
1295 case MMC_VDD_165_195:
1296 pwr = SDHCI_POWER_180;
1300 pwr = SDHCI_POWER_300;
1304 pwr = SDHCI_POWER_330;
1311 if (host->pwr == pwr)
1317 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1318 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1319 sdhci_runtime_pm_bus_off(host);
1323 * Spec says that we should clear the power reg before setting
1324 * a new value. Some controllers don't seem to like this though.
1326 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1327 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1330 * At least the Marvell CaFe chip gets confused if we set the
1331 * voltage and set turn on power at the same time, so set the
1334 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1335 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1337 pwr |= SDHCI_POWER_ON;
1339 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1341 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1342 sdhci_runtime_pm_bus_on(host);
1345 * Some controllers need an extra 10ms delay of 10ms before
1346 * they can apply clock after applying power
1348 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1353 /*****************************************************************************\
1357 \*****************************************************************************/
1359 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1361 struct sdhci_host *host;
1363 unsigned long flags;
1365 host = mmc_priv(mmc);
1367 sdhci_runtime_pm_get(host);
1369 /* Firstly check card presence */
1370 present = mmc->ops->get_cd(mmc);
1372 spin_lock_irqsave(&host->lock, flags);
1374 WARN_ON(host->mrq != NULL);
1376 #ifndef SDHCI_USE_LEDS_CLASS
1377 sdhci_activate_led(host);
1381 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1382 * requests if Auto-CMD12 is enabled.
1384 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1386 mrq->data->stop = NULL;
1393 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1394 host->mrq->cmd->error = -ENOMEDIUM;
1395 tasklet_schedule(&host->finish_tasklet);
1397 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1398 sdhci_send_command(host, mrq->sbc);
1400 sdhci_send_command(host, mrq->cmd);
1404 spin_unlock_irqrestore(&host->lock, flags);
1407 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1411 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1412 if (width == MMC_BUS_WIDTH_8) {
1413 ctrl &= ~SDHCI_CTRL_4BITBUS;
1414 if (host->version >= SDHCI_SPEC_300)
1415 ctrl |= SDHCI_CTRL_8BITBUS;
1417 if (host->version >= SDHCI_SPEC_300)
1418 ctrl &= ~SDHCI_CTRL_8BITBUS;
1419 if (width == MMC_BUS_WIDTH_4)
1420 ctrl |= SDHCI_CTRL_4BITBUS;
1422 ctrl &= ~SDHCI_CTRL_4BITBUS;
1424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1426 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1428 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1432 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1433 /* Select Bus Speed Mode for host */
1434 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1435 if ((timing == MMC_TIMING_MMC_HS200) ||
1436 (timing == MMC_TIMING_UHS_SDR104))
1437 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1438 else if (timing == MMC_TIMING_UHS_SDR12)
1439 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1440 else if (timing == MMC_TIMING_UHS_SDR25)
1441 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1442 else if (timing == MMC_TIMING_UHS_SDR50)
1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1444 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1445 (timing == MMC_TIMING_MMC_DDR52))
1446 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1447 else if (timing == MMC_TIMING_MMC_HS400)
1448 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1449 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1451 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1453 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1455 unsigned long flags;
1457 struct mmc_host *mmc = host->mmc;
1459 spin_lock_irqsave(&host->lock, flags);
1461 if (host->flags & SDHCI_DEVICE_DEAD) {
1462 spin_unlock_irqrestore(&host->lock, flags);
1463 if (!IS_ERR(mmc->supply.vmmc) &&
1464 ios->power_mode == MMC_POWER_OFF)
1465 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1470 * Reset the chip on each power off.
1471 * Should clear out any weird states.
1473 if (ios->power_mode == MMC_POWER_OFF) {
1474 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1478 if (host->version >= SDHCI_SPEC_300 &&
1479 (ios->power_mode == MMC_POWER_UP) &&
1480 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1481 sdhci_enable_preset_value(host, false);
1483 if (!ios->clock || ios->clock != host->clock) {
1484 host->ops->set_clock(host, ios->clock);
1485 host->clock = ios->clock;
1487 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1489 host->timeout_clk = host->mmc->actual_clock ?
1490 host->mmc->actual_clock / 1000 :
1492 host->mmc->max_busy_timeout =
1493 host->ops->get_max_timeout_count ?
1494 host->ops->get_max_timeout_count(host) :
1496 host->mmc->max_busy_timeout /= host->timeout_clk;
1500 sdhci_set_power(host, ios->power_mode, ios->vdd);
1502 if (host->ops->platform_send_init_74_clocks)
1503 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1505 host->ops->set_bus_width(host, ios->bus_width);
1507 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1509 if ((ios->timing == MMC_TIMING_SD_HS ||
1510 ios->timing == MMC_TIMING_MMC_HS)
1511 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1512 ctrl |= SDHCI_CTRL_HISPD;
1514 ctrl &= ~SDHCI_CTRL_HISPD;
1516 if (host->version >= SDHCI_SPEC_300) {
1519 /* In case of UHS-I modes, set High Speed Enable */
1520 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1521 (ios->timing == MMC_TIMING_MMC_HS200) ||
1522 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1523 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1524 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1525 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1526 (ios->timing == MMC_TIMING_UHS_SDR25))
1527 ctrl |= SDHCI_CTRL_HISPD;
1529 if (!host->preset_enabled) {
1530 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1532 * We only need to set Driver Strength if the
1533 * preset value enable is not set.
1535 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1536 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1537 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1538 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1539 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1540 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1541 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1542 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1543 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1544 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1546 pr_warn("%s: invalid driver type, default to "
1547 "driver type B\n", mmc_hostname(mmc));
1548 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1551 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1554 * According to SDHC Spec v3.00, if the Preset Value
1555 * Enable in the Host Control 2 register is set, we
1556 * need to reset SD Clock Enable before changing High
1557 * Speed Enable to avoid generating clock gliches.
1560 /* Reset SD Clock Enable */
1561 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1562 clk &= ~SDHCI_CLOCK_CARD_EN;
1563 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1565 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1567 /* Re-enable SD Clock */
1568 host->ops->set_clock(host, host->clock);
1571 /* Reset SD Clock Enable */
1572 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1573 clk &= ~SDHCI_CLOCK_CARD_EN;
1574 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1576 host->ops->set_uhs_signaling(host, ios->timing);
1577 host->timing = ios->timing;
1579 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1580 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1581 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1582 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1583 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1584 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1585 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1588 sdhci_enable_preset_value(host, true);
1589 preset = sdhci_get_preset_value(host);
1590 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1591 >> SDHCI_PRESET_DRV_SHIFT;
1594 /* Re-enable SD Clock */
1595 host->ops->set_clock(host, host->clock);
1597 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1600 * Some (ENE) controllers go apeshit on some ios operation,
1601 * signalling timeout and CRC errors even on CMD0. Resetting
1602 * it on each ios seems to solve the problem.
1604 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1605 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1608 spin_unlock_irqrestore(&host->lock, flags);
1611 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1613 struct sdhci_host *host = mmc_priv(mmc);
1615 sdhci_runtime_pm_get(host);
1616 sdhci_do_set_ios(host, ios);
1617 sdhci_runtime_pm_put(host);
1620 static int sdhci_do_get_cd(struct sdhci_host *host)
1622 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1624 if (host->flags & SDHCI_DEVICE_DEAD)
1627 /* If nonremovable, assume that the card is always present. */
1628 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1632 * Try slot gpio detect, if defined it take precedence
1633 * over build in controller functionality
1635 if (!IS_ERR_VALUE(gpio_cd))
1638 /* If polling, assume that the card is always present. */
1639 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1642 /* Host native card detect */
1643 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1646 static int sdhci_get_cd(struct mmc_host *mmc)
1648 struct sdhci_host *host = mmc_priv(mmc);
1651 sdhci_runtime_pm_get(host);
1652 ret = sdhci_do_get_cd(host);
1653 sdhci_runtime_pm_put(host);
1657 static int sdhci_check_ro(struct sdhci_host *host)
1659 unsigned long flags;
1662 spin_lock_irqsave(&host->lock, flags);
1664 if (host->flags & SDHCI_DEVICE_DEAD)
1666 else if (host->ops->get_ro)
1667 is_readonly = host->ops->get_ro(host);
1669 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1670 & SDHCI_WRITE_PROTECT);
1672 spin_unlock_irqrestore(&host->lock, flags);
1674 /* This quirk needs to be replaced by a callback-function later */
1675 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1676 !is_readonly : is_readonly;
1679 #define SAMPLE_COUNT 5
1681 static int sdhci_do_get_ro(struct sdhci_host *host)
1685 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1686 return sdhci_check_ro(host);
1689 for (i = 0; i < SAMPLE_COUNT; i++) {
1690 if (sdhci_check_ro(host)) {
1691 if (++ro_count > SAMPLE_COUNT / 2)
1699 static void sdhci_hw_reset(struct mmc_host *mmc)
1701 struct sdhci_host *host = mmc_priv(mmc);
1703 if (host->ops && host->ops->hw_reset)
1704 host->ops->hw_reset(host);
1707 static int sdhci_get_ro(struct mmc_host *mmc)
1709 struct sdhci_host *host = mmc_priv(mmc);
1712 sdhci_runtime_pm_get(host);
1713 ret = sdhci_do_get_ro(host);
1714 sdhci_runtime_pm_put(host);
1718 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1720 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1722 host->ier |= SDHCI_INT_CARD_INT;
1724 host->ier &= ~SDHCI_INT_CARD_INT;
1726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1732 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1734 struct sdhci_host *host = mmc_priv(mmc);
1735 unsigned long flags;
1737 sdhci_runtime_pm_get(host);
1739 spin_lock_irqsave(&host->lock, flags);
1741 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1743 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1745 sdhci_enable_sdio_irq_nolock(host, enable);
1746 spin_unlock_irqrestore(&host->lock, flags);
1748 sdhci_runtime_pm_put(host);
1751 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1752 struct mmc_ios *ios)
1754 struct mmc_host *mmc = host->mmc;
1759 * Signal Voltage Switching is only applicable for Host Controllers
1762 if (host->version < SDHCI_SPEC_300)
1765 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767 switch (ios->signal_voltage) {
1768 case MMC_SIGNAL_VOLTAGE_330:
1769 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1770 ctrl &= ~SDHCI_CTRL_VDD_180;
1771 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1773 if (!IS_ERR(mmc->supply.vqmmc)) {
1774 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1777 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1783 usleep_range(5000, 5500);
1785 /* 3.3V regulator output should be stable within 5 ms */
1786 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1787 if (!(ctrl & SDHCI_CTRL_VDD_180))
1790 pr_warn("%s: 3.3V regulator output did not became stable\n",
1794 case MMC_SIGNAL_VOLTAGE_180:
1795 if (!IS_ERR(mmc->supply.vqmmc)) {
1796 ret = regulator_set_voltage(mmc->supply.vqmmc,
1799 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1806 * Enable 1.8V Signal Enable in the Host Control2
1809 ctrl |= SDHCI_CTRL_VDD_180;
1810 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1812 /* Some controller need to do more when switching */
1813 if (host->ops->voltage_switch)
1814 host->ops->voltage_switch(host);
1816 /* 1.8V regulator output should be stable within 5 ms */
1817 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1818 if (ctrl & SDHCI_CTRL_VDD_180)
1821 pr_warn("%s: 1.8V regulator output did not became stable\n",
1825 case MMC_SIGNAL_VOLTAGE_120:
1826 if (!IS_ERR(mmc->supply.vqmmc)) {
1827 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1830 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1837 /* No signal voltage switch required */
1842 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1843 struct mmc_ios *ios)
1845 struct sdhci_host *host = mmc_priv(mmc);
1848 if (host->version < SDHCI_SPEC_300)
1850 sdhci_runtime_pm_get(host);
1851 err = sdhci_do_start_signal_voltage_switch(host, ios);
1852 sdhci_runtime_pm_put(host);
1856 static int sdhci_card_busy(struct mmc_host *mmc)
1858 struct sdhci_host *host = mmc_priv(mmc);
1861 sdhci_runtime_pm_get(host);
1862 /* Check whether DAT[3:0] is 0000 */
1863 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1864 sdhci_runtime_pm_put(host);
1866 return !(present_state & SDHCI_DATA_LVL_MASK);
1869 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1871 struct sdhci_host *host = mmc_priv(mmc);
1872 unsigned long flags;
1874 spin_lock_irqsave(&host->lock, flags);
1875 host->flags |= SDHCI_HS400_TUNING;
1876 spin_unlock_irqrestore(&host->lock, flags);
1881 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1883 struct sdhci_host *host = mmc_priv(mmc);
1885 int tuning_loop_counter = MAX_TUNING_LOOP;
1887 unsigned long flags;
1888 unsigned int tuning_count = 0;
1891 sdhci_runtime_pm_get(host);
1892 spin_lock_irqsave(&host->lock, flags);
1894 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1895 host->flags &= ~SDHCI_HS400_TUNING;
1897 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1898 tuning_count = host->tuning_count;
1901 * The Host Controller needs tuning in case of SDR104 and DDR50
1902 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1903 * the Capabilities register.
1904 * If the Host Controller supports the HS200 mode then the
1905 * tuning function has to be executed.
1907 switch (host->timing) {
1908 /* HS400 tuning is done in HS200 mode */
1909 case MMC_TIMING_MMC_HS400:
1913 case MMC_TIMING_MMC_HS200:
1915 * Periodic re-tuning for HS400 is not expected to be needed, so
1922 case MMC_TIMING_UHS_SDR104:
1923 case MMC_TIMING_UHS_DDR50:
1926 case MMC_TIMING_UHS_SDR50:
1927 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1928 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1936 if (host->ops->platform_execute_tuning) {
1937 spin_unlock_irqrestore(&host->lock, flags);
1938 err = host->ops->platform_execute_tuning(host, opcode);
1939 sdhci_runtime_pm_put(host);
1943 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1944 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1945 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1946 ctrl |= SDHCI_CTRL_TUNED_CLK;
1947 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1950 * As per the Host Controller spec v3.00, tuning command
1951 * generates Buffer Read Ready interrupt, so enable that.
1953 * Note: The spec clearly says that when tuning sequence
1954 * is being performed, the controller does not generate
1955 * interrupts other than Buffer Read Ready interrupt. But
1956 * to make sure we don't hit a controller bug, we _only_
1957 * enable Buffer Read Ready interrupt here.
1959 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1960 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1963 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1964 * of loops reaches 40 times or a timeout of 150ms occurs.
1967 struct mmc_command cmd = {0};
1968 struct mmc_request mrq = {NULL};
1970 cmd.opcode = opcode;
1972 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1977 if (tuning_loop_counter-- == 0)
1984 * In response to CMD19, the card sends 64 bytes of tuning
1985 * block to the Host Controller. So we set the block size
1988 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1989 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1990 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1992 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1993 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1996 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2001 * The tuning block is sent by the card to the host controller.
2002 * So we set the TRNS_READ bit in the Transfer Mode register.
2003 * This also takes care of setting DMA Enable and Multi Block
2004 * Select in the same register to 0.
2006 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2008 sdhci_send_command(host, &cmd);
2013 spin_unlock_irqrestore(&host->lock, flags);
2014 /* Wait for Buffer Read Ready interrupt */
2015 wait_event_interruptible_timeout(host->buf_ready_int,
2016 (host->tuning_done == 1),
2017 msecs_to_jiffies(50));
2018 spin_lock_irqsave(&host->lock, flags);
2020 if (!host->tuning_done) {
2021 pr_info(DRIVER_NAME ": Timeout waiting for "
2022 "Buffer Read Ready interrupt during tuning "
2023 "procedure, falling back to fixed sampling "
2025 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2026 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2027 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2028 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2034 host->tuning_done = 0;
2036 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2038 /* eMMC spec does not require a delay between tuning cycles */
2039 if (opcode == MMC_SEND_TUNING_BLOCK)
2041 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2044 * The Host Driver has exhausted the maximum number of loops allowed,
2045 * so use fixed sampling frequency.
2047 if (tuning_loop_counter < 0) {
2048 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2049 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2051 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2052 pr_info(DRIVER_NAME ": Tuning procedure"
2053 " failed, falling back to fixed sampling"
2061 * In case tuning fails, host controllers which support
2062 * re-tuning can try tuning again at a later time, when the
2063 * re-tuning timer expires. So for these controllers, we
2064 * return 0. Since there might be other controllers who do not
2065 * have this capability, we return error for them.
2070 host->mmc->retune_period = err ? 0 : tuning_count;
2072 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2073 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2075 spin_unlock_irqrestore(&host->lock, flags);
2076 sdhci_runtime_pm_put(host);
2081 static int sdhci_prepare_enhanced_strobe(struct mmc_host *mmc, bool enable)
2084 * Currently we can't find a register to enable enhanced strobe
2085 * function for standard sdhci, so we expect variant drivers to
2091 static int sdhci_select_drive_strength(struct mmc_card *card,
2092 unsigned int max_dtr, int host_drv,
2093 int card_drv, int *drv_type)
2095 struct sdhci_host *host = mmc_priv(card->host);
2097 if (!host->ops->select_drive_strength)
2100 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2101 card_drv, drv_type);
2104 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2106 /* Host Controller v3.00 defines preset value registers */
2107 if (host->version < SDHCI_SPEC_300)
2111 * We only enable or disable Preset Value if they are not already
2112 * enabled or disabled respectively. Otherwise, we bail out.
2114 if (host->preset_enabled != enable) {
2115 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2118 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2120 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2122 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2125 host->flags |= SDHCI_PV_ENABLED;
2127 host->flags &= ~SDHCI_PV_ENABLED;
2129 host->preset_enabled = enable;
2133 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2136 struct sdhci_host *host = mmc_priv(mmc);
2137 struct mmc_data *data = mrq->data;
2139 if (host->flags & SDHCI_REQ_USE_DMA) {
2140 if (data->host_cookie == COOKIE_GIVEN ||
2141 data->host_cookie == COOKIE_MAPPED)
2142 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2143 data->flags & MMC_DATA_WRITE ?
2144 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2145 data->host_cookie = COOKIE_UNMAPPED;
2149 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2150 struct mmc_data *data)
2154 if (data->host_cookie == COOKIE_MAPPED) {
2155 data->host_cookie = COOKIE_GIVEN;
2156 return data->sg_count;
2159 WARN_ON(data->host_cookie == COOKIE_GIVEN);
2161 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2162 data->flags & MMC_DATA_WRITE ?
2163 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2168 data->sg_count = sg_count;
2169 data->host_cookie = COOKIE_MAPPED;
2174 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2177 struct sdhci_host *host = mmc_priv(mmc);
2179 mrq->data->host_cookie = COOKIE_UNMAPPED;
2181 if (host->flags & SDHCI_REQ_USE_DMA)
2182 sdhci_pre_dma_transfer(host, mrq->data);
2185 static void sdhci_card_event(struct mmc_host *mmc)
2187 struct sdhci_host *host = mmc_priv(mmc);
2188 unsigned long flags;
2191 /* First check if client has provided their own card event */
2192 if (host->ops->card_event)
2193 host->ops->card_event(host);
2195 present = sdhci_do_get_cd(host);
2197 spin_lock_irqsave(&host->lock, flags);
2199 /* Check host->mrq first in case we are runtime suspended */
2200 if (host->mrq && !present) {
2201 pr_err("%s: Card removed during transfer!\n",
2202 mmc_hostname(host->mmc));
2203 pr_err("%s: Resetting controller.\n",
2204 mmc_hostname(host->mmc));
2206 sdhci_do_reset(host, SDHCI_RESET_CMD);
2207 sdhci_do_reset(host, SDHCI_RESET_DATA);
2209 host->mrq->cmd->error = -ENOMEDIUM;
2210 tasklet_schedule(&host->finish_tasklet);
2213 spin_unlock_irqrestore(&host->lock, flags);
2216 static const struct mmc_host_ops sdhci_ops = {
2217 .request = sdhci_request,
2218 .post_req = sdhci_post_req,
2219 .pre_req = sdhci_pre_req,
2220 .set_ios = sdhci_set_ios,
2221 .get_cd = sdhci_get_cd,
2222 .get_ro = sdhci_get_ro,
2223 .hw_reset = sdhci_hw_reset,
2224 .enable_sdio_irq = sdhci_enable_sdio_irq,
2225 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2226 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2227 .prepare_enhanced_strobe = sdhci_prepare_enhanced_strobe,
2228 .execute_tuning = sdhci_execute_tuning,
2229 .select_drive_strength = sdhci_select_drive_strength,
2230 .card_event = sdhci_card_event,
2231 .card_busy = sdhci_card_busy,
2234 /*****************************************************************************\
2238 \*****************************************************************************/
2240 static void sdhci_tasklet_finish(unsigned long param)
2242 struct sdhci_host *host;
2243 unsigned long flags;
2244 struct mmc_request *mrq;
2246 host = (struct sdhci_host*)param;
2248 spin_lock_irqsave(&host->lock, flags);
2251 * If this tasklet gets rescheduled while running, it will
2252 * be run again afterwards but without any active request.
2255 spin_unlock_irqrestore(&host->lock, flags);
2259 del_timer(&host->timer);
2264 * The controller needs a reset of internal state machines
2265 * upon error conditions.
2267 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2268 ((mrq->cmd && mrq->cmd->error) ||
2269 (mrq->sbc && mrq->sbc->error) ||
2270 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2271 (mrq->data->stop && mrq->data->stop->error))) ||
2272 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2274 /* Some controllers need this kick or reset won't work here */
2275 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2276 /* This is to force an update */
2277 host->ops->set_clock(host, host->clock);
2279 /* Spec says we should do both at the same time, but Ricoh
2280 controllers do not like that. */
2281 sdhci_do_reset(host, SDHCI_RESET_CMD);
2282 sdhci_do_reset(host, SDHCI_RESET_DATA);
2289 #ifndef SDHCI_USE_LEDS_CLASS
2290 sdhci_deactivate_led(host);
2294 spin_unlock_irqrestore(&host->lock, flags);
2296 mmc_request_done(host->mmc, mrq);
2297 sdhci_runtime_pm_put(host);
2300 static void sdhci_timeout_timer(unsigned long data)
2302 struct sdhci_host *host;
2303 unsigned long flags;
2305 host = (struct sdhci_host*)data;
2307 spin_lock_irqsave(&host->lock, flags);
2310 pr_err("%s: Timeout waiting for hardware "
2311 "interrupt.\n", mmc_hostname(host->mmc));
2312 sdhci_dumpregs(host);
2315 host->data->error = -ETIMEDOUT;
2316 sdhci_finish_data(host);
2319 host->cmd->error = -ETIMEDOUT;
2321 host->mrq->cmd->error = -ETIMEDOUT;
2323 tasklet_schedule(&host->finish_tasklet);
2328 spin_unlock_irqrestore(&host->lock, flags);
2331 /*****************************************************************************\
2333 * Interrupt handling *
2335 \*****************************************************************************/
2337 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2339 BUG_ON(intmask == 0);
2342 pr_err("%s: Got command interrupt 0x%08x even "
2343 "though no command operation was in progress.\n",
2344 mmc_hostname(host->mmc), (unsigned)intmask);
2345 sdhci_dumpregs(host);
2349 if (intmask & SDHCI_INT_TIMEOUT)
2350 host->cmd->error = -ETIMEDOUT;
2351 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2353 host->cmd->error = -EILSEQ;
2355 if (host->cmd->error) {
2356 tasklet_schedule(&host->finish_tasklet);
2361 * The host can send and interrupt when the busy state has
2362 * ended, allowing us to wait without wasting CPU cycles.
2363 * Unfortunately this is overloaded on the "data complete"
2364 * interrupt, so we need to take some care when handling
2367 * Note: The 1.0 specification is a bit ambiguous about this
2368 * feature so there might be some problems with older
2371 if (host->cmd->flags & MMC_RSP_BUSY) {
2372 if (host->cmd->data)
2373 DBG("Cannot wait for busy signal when also "
2374 "doing a data transfer");
2375 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2376 && !host->busy_handle) {
2377 /* Mark that command complete before busy is ended */
2378 host->busy_handle = 1;
2382 /* The controller does not support the end-of-busy IRQ,
2383 * fall through and take the SDHCI_INT_RESPONSE */
2384 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2385 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2386 *mask &= ~SDHCI_INT_DATA_END;
2389 if (intmask & SDHCI_INT_RESPONSE)
2390 sdhci_finish_command(host);
2393 #ifdef CONFIG_MMC_DEBUG
2394 static void sdhci_adma_show_error(struct sdhci_host *host)
2396 const char *name = mmc_hostname(host->mmc);
2397 void *desc = host->adma_table;
2399 sdhci_dumpregs(host);
2402 struct sdhci_adma2_64_desc *dma_desc = desc;
2404 if (host->flags & SDHCI_USE_64_BIT_DMA)
2405 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2406 name, desc, le32_to_cpu(dma_desc->addr_hi),
2407 le32_to_cpu(dma_desc->addr_lo),
2408 le16_to_cpu(dma_desc->len),
2409 le16_to_cpu(dma_desc->cmd));
2411 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2412 name, desc, le32_to_cpu(dma_desc->addr_lo),
2413 le16_to_cpu(dma_desc->len),
2414 le16_to_cpu(dma_desc->cmd));
2416 desc += host->desc_sz;
2418 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2423 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2426 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2429 BUG_ON(intmask == 0);
2431 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2432 if (intmask & SDHCI_INT_DATA_AVAIL) {
2433 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2434 if (command == MMC_SEND_TUNING_BLOCK ||
2435 command == MMC_SEND_TUNING_BLOCK_HS200) {
2436 host->tuning_done = 1;
2437 wake_up(&host->buf_ready_int);
2444 * The "data complete" interrupt is also used to
2445 * indicate that a busy state has ended. See comment
2446 * above in sdhci_cmd_irq().
2448 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2449 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2450 host->cmd->error = -ETIMEDOUT;
2451 tasklet_schedule(&host->finish_tasklet);
2454 if (intmask & SDHCI_INT_DATA_END) {
2456 * Some cards handle busy-end interrupt
2457 * before the command completed, so make
2458 * sure we do things in the proper order.
2460 if (host->busy_handle)
2461 sdhci_finish_command(host);
2463 host->busy_handle = 1;
2468 pr_err("%s: Got data interrupt 0x%08x even "
2469 "though no data operation was in progress.\n",
2470 mmc_hostname(host->mmc), (unsigned)intmask);
2471 sdhci_dumpregs(host);
2476 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2477 host->data->error = -ETIMEDOUT;
2478 else if (intmask & SDHCI_INT_DATA_END_BIT)
2479 host->data->error = -EILSEQ;
2480 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2481 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2483 host->data->error = -EILSEQ;
2484 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2485 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2486 sdhci_adma_show_error(host);
2487 host->data->error = -EIO;
2488 if (host->ops->adma_workaround)
2489 host->ops->adma_workaround(host, intmask);
2492 if (host->data->error)
2493 sdhci_finish_data(host);
2495 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2496 sdhci_transfer_pio(host);
2499 * We currently don't do anything fancy with DMA
2500 * boundaries, but as we can't disable the feature
2501 * we need to at least restart the transfer.
2503 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2504 * should return a valid address to continue from, but as
2505 * some controllers are faulty, don't trust them.
2507 if (intmask & SDHCI_INT_DMA_END) {
2508 u32 dmastart, dmanow;
2509 dmastart = sg_dma_address(host->data->sg);
2510 dmanow = dmastart + host->data->bytes_xfered;
2512 * Force update to the next DMA block boundary.
2515 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2516 SDHCI_DEFAULT_BOUNDARY_SIZE;
2517 host->data->bytes_xfered = dmanow - dmastart;
2518 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2520 mmc_hostname(host->mmc), dmastart,
2521 host->data->bytes_xfered, dmanow);
2522 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2525 if (intmask & SDHCI_INT_DATA_END) {
2528 * Data managed to finish before the
2529 * command completed. Make sure we do
2530 * things in the proper order.
2532 host->data_early = 1;
2534 sdhci_finish_data(host);
2540 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2542 irqreturn_t result = IRQ_NONE;
2543 struct sdhci_host *host = dev_id;
2544 u32 intmask, mask, unexpected = 0;
2547 spin_lock(&host->lock);
2549 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2550 spin_unlock(&host->lock);
2554 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2555 if (!intmask || intmask == 0xffffffff) {
2561 /* Clear selected interrupts. */
2562 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2563 SDHCI_INT_BUS_POWER);
2564 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2566 DBG("*** %s got interrupt: 0x%08x\n",
2567 mmc_hostname(host->mmc), intmask);
2569 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2570 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2574 * There is a observation on i.mx esdhc. INSERT
2575 * bit will be immediately set again when it gets
2576 * cleared, if a card is inserted. We have to mask
2577 * the irq to prevent interrupt storm which will
2578 * freeze the system. And the REMOVE gets the
2581 * More testing are needed here to ensure it works
2582 * for other platforms though.
2584 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2585 SDHCI_INT_CARD_REMOVE);
2586 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2587 SDHCI_INT_CARD_INSERT;
2588 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2589 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2591 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2592 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2594 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2595 SDHCI_INT_CARD_REMOVE);
2596 result = IRQ_WAKE_THREAD;
2599 if (intmask & SDHCI_INT_CMD_MASK)
2600 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2603 if (intmask & SDHCI_INT_DATA_MASK)
2604 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2606 if (intmask & SDHCI_INT_BUS_POWER)
2607 pr_err("%s: Card is consuming too much power!\n",
2608 mmc_hostname(host->mmc));
2610 if (intmask & SDHCI_INT_CARD_INT) {
2611 sdhci_enable_sdio_irq_nolock(host, false);
2612 host->thread_isr |= SDHCI_INT_CARD_INT;
2613 result = IRQ_WAKE_THREAD;
2616 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2617 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2618 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2619 SDHCI_INT_CARD_INT);
2622 unexpected |= intmask;
2623 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2626 if (result == IRQ_NONE)
2627 result = IRQ_HANDLED;
2629 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2630 } while (intmask && --max_loops);
2632 spin_unlock(&host->lock);
2635 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2636 mmc_hostname(host->mmc), unexpected);
2637 sdhci_dumpregs(host);
2643 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2645 struct sdhci_host *host = dev_id;
2646 unsigned long flags;
2649 spin_lock_irqsave(&host->lock, flags);
2650 isr = host->thread_isr;
2651 host->thread_isr = 0;
2652 spin_unlock_irqrestore(&host->lock, flags);
2654 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2655 sdhci_card_event(host->mmc);
2656 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2659 if (isr & SDHCI_INT_CARD_INT) {
2660 sdio_run_irqs(host->mmc);
2662 spin_lock_irqsave(&host->lock, flags);
2663 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2664 sdhci_enable_sdio_irq_nolock(host, true);
2665 spin_unlock_irqrestore(&host->lock, flags);
2668 return isr ? IRQ_HANDLED : IRQ_NONE;
2671 /*****************************************************************************\
2675 \*****************************************************************************/
2678 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2681 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2682 | SDHCI_WAKE_ON_INT;
2684 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2686 /* Avoid fake wake up */
2687 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2688 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2689 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2691 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2693 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2696 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2697 | SDHCI_WAKE_ON_INT;
2699 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2701 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2704 int sdhci_suspend_host(struct sdhci_host *host)
2706 sdhci_disable_card_detection(host);
2708 mmc_retune_timer_stop(host->mmc);
2709 mmc_retune_needed(host->mmc);
2711 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2713 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2714 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2715 free_irq(host->irq, host);
2717 sdhci_enable_irq_wakeups(host);
2718 enable_irq_wake(host->irq);
2723 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2725 int sdhci_resume_host(struct sdhci_host *host)
2729 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2730 if (host->ops->enable_dma)
2731 host->ops->enable_dma(host);
2734 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2735 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2736 /* Card keeps power but host controller does not */
2737 sdhci_init(host, 0);
2740 sdhci_do_set_ios(host, &host->mmc->ios);
2742 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2746 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2747 ret = request_threaded_irq(host->irq, sdhci_irq,
2748 sdhci_thread_irq, IRQF_SHARED,
2749 mmc_hostname(host->mmc), host);
2753 sdhci_disable_irq_wakeups(host);
2754 disable_irq_wake(host->irq);
2757 sdhci_enable_card_detection(host);
2762 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2764 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2766 return pm_runtime_get_sync(host->mmc->parent);
2769 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2771 pm_runtime_mark_last_busy(host->mmc->parent);
2772 return pm_runtime_put_autosuspend(host->mmc->parent);
2775 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2779 host->bus_on = true;
2780 pm_runtime_get_noresume(host->mmc->parent);
2783 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2787 host->bus_on = false;
2788 pm_runtime_put_noidle(host->mmc->parent);
2791 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2793 unsigned long flags;
2795 mmc_retune_timer_stop(host->mmc);
2796 mmc_retune_needed(host->mmc);
2798 spin_lock_irqsave(&host->lock, flags);
2799 host->ier &= SDHCI_INT_CARD_INT;
2800 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2801 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2802 spin_unlock_irqrestore(&host->lock, flags);
2804 synchronize_hardirq(host->irq);
2806 spin_lock_irqsave(&host->lock, flags);
2807 host->runtime_suspended = true;
2808 spin_unlock_irqrestore(&host->lock, flags);
2812 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2814 int sdhci_runtime_resume_host(struct sdhci_host *host)
2816 unsigned long flags;
2817 int host_flags = host->flags;
2819 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2820 if (host->ops->enable_dma)
2821 host->ops->enable_dma(host);
2824 sdhci_init(host, 0);
2826 /* Force clock and power re-program */
2829 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2830 sdhci_do_set_ios(host, &host->mmc->ios);
2832 if ((host_flags & SDHCI_PV_ENABLED) &&
2833 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2834 spin_lock_irqsave(&host->lock, flags);
2835 sdhci_enable_preset_value(host, true);
2836 spin_unlock_irqrestore(&host->lock, flags);
2839 spin_lock_irqsave(&host->lock, flags);
2841 host->runtime_suspended = false;
2843 /* Enable SDIO IRQ */
2844 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2845 sdhci_enable_sdio_irq_nolock(host, true);
2847 /* Enable Card Detection */
2848 sdhci_enable_card_detection(host);
2850 spin_unlock_irqrestore(&host->lock, flags);
2854 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2856 #endif /* CONFIG_PM */
2858 /*****************************************************************************\
2860 * Device allocation/registration *
2862 \*****************************************************************************/
2864 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2867 struct mmc_host *mmc;
2868 struct sdhci_host *host;
2870 WARN_ON(dev == NULL);
2872 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2874 return ERR_PTR(-ENOMEM);
2876 host = mmc_priv(mmc);
2878 host->mmc_host_ops = sdhci_ops;
2879 mmc->ops = &host->mmc_host_ops;
2884 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2886 int sdhci_add_host(struct sdhci_host *host)
2888 struct mmc_host *mmc;
2889 u32 caps[2] = {0, 0};
2890 u32 max_current_caps;
2891 unsigned int ocr_avail;
2892 unsigned int override_timeout_clk;
2896 WARN_ON(host == NULL);
2903 host->quirks = debug_quirks;
2905 host->quirks2 = debug_quirks2;
2907 override_timeout_clk = host->timeout_clk;
2909 sdhci_do_reset(host, SDHCI_RESET_ALL);
2911 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2912 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2913 >> SDHCI_SPEC_VER_SHIFT;
2914 if (host->version > SDHCI_SPEC_300) {
2915 pr_err("%s: Unknown controller version (%d). "
2916 "You may experience problems.\n", mmc_hostname(mmc),
2920 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2921 sdhci_readl(host, SDHCI_CAPABILITIES);
2923 if (host->version >= SDHCI_SPEC_300)
2924 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2926 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2928 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2929 host->flags |= SDHCI_USE_SDMA;
2930 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2931 DBG("Controller doesn't have SDMA capability\n");
2933 host->flags |= SDHCI_USE_SDMA;
2935 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2936 (host->flags & SDHCI_USE_SDMA)) {
2937 DBG("Disabling DMA as it is marked broken\n");
2938 host->flags &= ~SDHCI_USE_SDMA;
2941 if ((host->version >= SDHCI_SPEC_200) &&
2942 (caps[0] & SDHCI_CAN_DO_ADMA2))
2943 host->flags |= SDHCI_USE_ADMA;
2945 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2946 (host->flags & SDHCI_USE_ADMA)) {
2947 DBG("Disabling ADMA as it is marked broken\n");
2948 host->flags &= ~SDHCI_USE_ADMA;
2952 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2953 * and *must* do 64-bit DMA. A driver has the opportunity to change
2954 * that during the first call to ->enable_dma(). Similarly
2955 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2958 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2959 host->flags |= SDHCI_USE_64_BIT_DMA;
2961 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2962 if (host->ops->enable_dma) {
2963 if (host->ops->enable_dma(host)) {
2964 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2967 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2972 /* SDMA does not support 64-bit DMA */
2973 if (host->flags & SDHCI_USE_64_BIT_DMA)
2974 host->flags &= ~SDHCI_USE_SDMA;
2976 if (host->flags & SDHCI_USE_ADMA) {
2978 * The DMA descriptor table size is calculated as the maximum
2979 * number of segments times 2, to allow for an alignment
2980 * descriptor for each segment, plus 1 for a nop end descriptor,
2981 * all multipled by the descriptor size.
2983 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2984 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2985 SDHCI_ADMA2_64_DESC_SZ;
2986 host->align_buffer_sz = SDHCI_MAX_SEGS *
2987 SDHCI_ADMA2_64_ALIGN;
2988 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2989 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2990 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2992 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2993 SDHCI_ADMA2_32_DESC_SZ;
2994 host->align_buffer_sz = SDHCI_MAX_SEGS *
2995 SDHCI_ADMA2_32_ALIGN;
2996 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2997 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2998 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3000 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3001 host->adma_table_sz,
3004 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3005 if (!host->adma_table || !host->align_buffer) {
3006 if (host->adma_table)
3007 dma_free_coherent(mmc_dev(mmc),
3008 host->adma_table_sz,
3011 kfree(host->align_buffer);
3012 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3014 host->flags &= ~SDHCI_USE_ADMA;
3015 host->adma_table = NULL;
3016 host->align_buffer = NULL;
3017 } else if (host->adma_addr & host->align_mask) {
3018 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3020 host->flags &= ~SDHCI_USE_ADMA;
3021 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3022 host->adma_table, host->adma_addr);
3023 kfree(host->align_buffer);
3024 host->adma_table = NULL;
3025 host->align_buffer = NULL;
3030 * If we use DMA, then it's up to the caller to set the DMA
3031 * mask, but PIO does not need the hw shim so we set a new
3032 * mask here in that case.
3034 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3035 host->dma_mask = DMA_BIT_MASK(64);
3036 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3039 if (host->version >= SDHCI_SPEC_300)
3040 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3041 >> SDHCI_CLOCK_BASE_SHIFT;
3043 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3044 >> SDHCI_CLOCK_BASE_SHIFT;
3046 host->max_clk *= 1000000;
3047 if (host->max_clk == 0 || host->quirks &
3048 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3049 if (!host->ops->get_max_clock) {
3050 pr_err("%s: Hardware doesn't specify base clock "
3051 "frequency.\n", mmc_hostname(mmc));
3054 host->max_clk = host->ops->get_max_clock(host);
3058 * In case of Host Controller v3.00, find out whether clock
3059 * multiplier is supported.
3061 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3062 SDHCI_CLOCK_MUL_SHIFT;
3065 * In case the value in Clock Multiplier is 0, then programmable
3066 * clock mode is not supported, otherwise the actual clock
3067 * multiplier is one more than the value of Clock Multiplier
3068 * in the Capabilities Register.
3074 * Set host parameters.
3076 max_clk = host->max_clk;
3078 if (host->ops->get_min_clock)
3079 mmc->f_min = host->ops->get_min_clock(host);
3080 else if (host->version >= SDHCI_SPEC_300) {
3081 if (host->clk_mul) {
3082 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3083 max_clk = host->max_clk * host->clk_mul;
3085 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3087 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3089 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3090 mmc->f_max = max_clk;
3092 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3093 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3094 SDHCI_TIMEOUT_CLK_SHIFT;
3095 if (host->timeout_clk == 0) {
3096 if (host->ops->get_timeout_clock) {
3098 host->ops->get_timeout_clock(host);
3100 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3106 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3107 host->timeout_clk *= 1000;
3109 if (override_timeout_clk)
3110 host->timeout_clk = override_timeout_clk;
3112 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3113 host->ops->get_max_timeout_count(host) : 1 << 27;
3114 mmc->max_busy_timeout /= host->timeout_clk;
3117 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3118 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3120 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3121 host->flags |= SDHCI_AUTO_CMD12;
3123 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3124 if ((host->version >= SDHCI_SPEC_300) &&
3125 ((host->flags & SDHCI_USE_ADMA) ||
3126 !(host->flags & SDHCI_USE_SDMA)) &&
3127 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3128 host->flags |= SDHCI_AUTO_CMD23;
3129 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3131 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3135 * A controller may support 8-bit width, but the board itself
3136 * might not have the pins brought out. Boards that support
3137 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3138 * their platform code before calling sdhci_add_host(), and we
3139 * won't assume 8-bit width for hosts without that CAP.
3141 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3142 mmc->caps |= MMC_CAP_4_BIT_DATA;
3144 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3145 mmc->caps &= ~MMC_CAP_CMD23;
3147 if (caps[0] & SDHCI_CAN_DO_HISPD)
3148 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3151 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3152 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3153 mmc->caps |= MMC_CAP_NEEDS_POLL;
3155 /* If there are external regulators, get them */
3156 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3157 return -EPROBE_DEFER;
3159 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3160 if (!IS_ERR(mmc->supply.vqmmc)) {
3161 ret = regulator_enable(mmc->supply.vqmmc);
3162 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3164 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3165 SDHCI_SUPPORT_SDR50 |
3166 SDHCI_SUPPORT_DDR50);
3168 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3169 mmc_hostname(mmc), ret);
3170 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3174 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3175 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3176 SDHCI_SUPPORT_DDR50);
3178 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3179 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3180 SDHCI_SUPPORT_DDR50))
3181 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3183 /* SDR104 supports also implies SDR50 support */
3184 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3185 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3186 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3187 * field can be promoted to support HS200.
3189 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3190 mmc->caps2 |= MMC_CAP2_HS200;
3191 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3192 mmc->caps |= MMC_CAP_UHS_SDR50;
3194 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3195 (caps[1] & SDHCI_SUPPORT_HS400))
3196 mmc->caps2 |= MMC_CAP2_HS400;
3198 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3199 (IS_ERR(mmc->supply.vqmmc) ||
3200 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3202 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3204 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3205 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3206 mmc->caps |= MMC_CAP_UHS_DDR50;
3208 /* Does the host need tuning for SDR50? */
3209 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3210 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3212 /* Does the host need tuning for SDR104 / HS200? */
3213 if (mmc->caps2 & MMC_CAP2_HS200)
3214 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3216 /* Driver Type(s) (A, C, D) supported by the host */
3217 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3218 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3219 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3220 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3221 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3222 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3224 /* Initial value for re-tuning timer count */
3225 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3226 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3229 * In case Re-tuning Timer is not disabled, the actual value of
3230 * re-tuning timer will be 2 ^ (n - 1).
3232 if (host->tuning_count)
3233 host->tuning_count = 1 << (host->tuning_count - 1);
3235 /* Re-tuning mode supported by the Host Controller */
3236 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3237 SDHCI_RETUNING_MODE_SHIFT;
3242 * According to SD Host Controller spec v3.00, if the Host System
3243 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3244 * the value is meaningful only if Voltage Support in the Capabilities
3245 * register is set. The actual current value is 4 times the register
3248 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3249 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3250 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3253 /* convert to SDHCI_MAX_CURRENT format */
3254 curr = curr/1000; /* convert to mA */
3255 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3257 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3259 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3260 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3261 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3265 if (caps[0] & SDHCI_CAN_VDD_330) {
3266 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3268 mmc->max_current_330 = ((max_current_caps &
3269 SDHCI_MAX_CURRENT_330_MASK) >>
3270 SDHCI_MAX_CURRENT_330_SHIFT) *
3271 SDHCI_MAX_CURRENT_MULTIPLIER;
3273 if (caps[0] & SDHCI_CAN_VDD_300) {
3274 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3276 mmc->max_current_300 = ((max_current_caps &
3277 SDHCI_MAX_CURRENT_300_MASK) >>
3278 SDHCI_MAX_CURRENT_300_SHIFT) *
3279 SDHCI_MAX_CURRENT_MULTIPLIER;
3281 if (caps[0] & SDHCI_CAN_VDD_180) {
3282 ocr_avail |= MMC_VDD_165_195;
3284 mmc->max_current_180 = ((max_current_caps &
3285 SDHCI_MAX_CURRENT_180_MASK) >>
3286 SDHCI_MAX_CURRENT_180_SHIFT) *
3287 SDHCI_MAX_CURRENT_MULTIPLIER;
3290 /* If OCR set by host, use it instead. */
3292 ocr_avail = host->ocr_mask;
3294 /* If OCR set by external regulators, give it highest prio. */
3296 ocr_avail = mmc->ocr_avail;
3298 mmc->ocr_avail = ocr_avail;
3299 mmc->ocr_avail_sdio = ocr_avail;
3300 if (host->ocr_avail_sdio)
3301 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3302 mmc->ocr_avail_sd = ocr_avail;
3303 if (host->ocr_avail_sd)
3304 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3305 else /* normal SD controllers don't support 1.8V */
3306 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3307 mmc->ocr_avail_mmc = ocr_avail;
3308 if (host->ocr_avail_mmc)
3309 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3311 if (mmc->ocr_avail == 0) {
3312 pr_err("%s: Hardware doesn't report any "
3313 "support voltages.\n", mmc_hostname(mmc));
3317 spin_lock_init(&host->lock);
3320 * Maximum number of segments. Depends on if the hardware
3321 * can do scatter/gather or not.
3323 if (host->flags & SDHCI_USE_ADMA)
3324 mmc->max_segs = SDHCI_MAX_SEGS;
3325 else if (host->flags & SDHCI_USE_SDMA)
3328 mmc->max_segs = SDHCI_MAX_SEGS;
3331 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3332 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3335 mmc->max_req_size = 524288;
3338 * Maximum segment size. Could be one segment with the maximum number
3339 * of bytes. When doing hardware scatter/gather, each entry cannot
3340 * be larger than 64 KiB though.
3342 if (host->flags & SDHCI_USE_ADMA) {
3343 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3344 mmc->max_seg_size = 65535;
3346 mmc->max_seg_size = 65536;
3348 mmc->max_seg_size = mmc->max_req_size;
3352 * Maximum block size. This varies from controller to controller and
3353 * is specified in the capabilities register.
3355 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3356 mmc->max_blk_size = 2;
3358 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3359 SDHCI_MAX_BLOCK_SHIFT;
3360 if (mmc->max_blk_size >= 3) {
3361 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3363 mmc->max_blk_size = 0;
3367 mmc->max_blk_size = 512 << mmc->max_blk_size;
3370 * Maximum block count.
3372 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3377 tasklet_init(&host->finish_tasklet,
3378 sdhci_tasklet_finish, (unsigned long)host);
3380 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3382 init_waitqueue_head(&host->buf_ready_int);
3384 sdhci_init(host, 0);
3386 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3387 IRQF_SHARED, mmc_hostname(mmc), host);
3389 pr_err("%s: Failed to request IRQ %d: %d\n",
3390 mmc_hostname(mmc), host->irq, ret);
3394 #ifdef CONFIG_MMC_DEBUG
3395 sdhci_dumpregs(host);
3398 #ifdef SDHCI_USE_LEDS_CLASS
3399 snprintf(host->led_name, sizeof(host->led_name),
3400 "%s::", mmc_hostname(mmc));
3401 host->led.name = host->led_name;
3402 host->led.brightness = LED_OFF;
3403 host->led.default_trigger = mmc_hostname(mmc);
3404 host->led.brightness_set = sdhci_led_control;
3406 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3408 pr_err("%s: Failed to register LED device: %d\n",
3409 mmc_hostname(mmc), ret);
3418 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3419 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3420 (host->flags & SDHCI_USE_ADMA) ?
3421 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3422 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3424 sdhci_enable_card_detection(host);
3428 #ifdef SDHCI_USE_LEDS_CLASS
3430 sdhci_do_reset(host, SDHCI_RESET_ALL);
3431 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3432 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3433 free_irq(host->irq, host);
3436 tasklet_kill(&host->finish_tasklet);
3441 EXPORT_SYMBOL_GPL(sdhci_add_host);
3443 void sdhci_remove_host(struct sdhci_host *host, int dead)
3445 struct mmc_host *mmc = host->mmc;
3446 unsigned long flags;
3449 spin_lock_irqsave(&host->lock, flags);
3451 host->flags |= SDHCI_DEVICE_DEAD;
3454 pr_err("%s: Controller removed during "
3455 " transfer!\n", mmc_hostname(mmc));
3457 host->mrq->cmd->error = -ENOMEDIUM;
3458 tasklet_schedule(&host->finish_tasklet);
3461 spin_unlock_irqrestore(&host->lock, flags);
3464 sdhci_disable_card_detection(host);
3466 mmc_remove_host(mmc);
3468 #ifdef SDHCI_USE_LEDS_CLASS
3469 led_classdev_unregister(&host->led);
3473 sdhci_do_reset(host, SDHCI_RESET_ALL);
3475 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3476 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3477 free_irq(host->irq, host);
3479 del_timer_sync(&host->timer);
3481 tasklet_kill(&host->finish_tasklet);
3483 if (!IS_ERR(mmc->supply.vqmmc))
3484 regulator_disable(mmc->supply.vqmmc);
3486 if (host->adma_table)
3487 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3488 host->adma_table, host->adma_addr);
3489 kfree(host->align_buffer);
3491 host->adma_table = NULL;
3492 host->align_buffer = NULL;
3495 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3497 void sdhci_free_host(struct sdhci_host *host)
3499 mmc_free_host(host->mmc);
3502 EXPORT_SYMBOL_GPL(sdhci_free_host);
3504 /*****************************************************************************\
3506 * Driver init/exit *
3508 \*****************************************************************************/
3510 static int __init sdhci_drv_init(void)
3513 ": Secure Digital Host Controller Interface driver\n");
3514 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3519 static void __exit sdhci_drv_exit(void)
3523 module_init(sdhci_drv_init);
3524 module_exit(sdhci_drv_exit);
3526 module_param(debug_quirks, uint, 0444);
3527 module_param(debug_quirks2, uint, 0444);
3529 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3530 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3531 MODULE_LICENSE("GPL");
3533 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3534 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");