2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
46 #define MAX_TUNING_LOOP 40
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
51 static void sdhci_finish_data(struct sdhci_host *);
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_tuning_timer(unsigned long data);
56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
58 struct mmc_data *data,
59 struct sdhci_host_next *next);
60 static int sdhci_do_get_cd(struct sdhci_host *host);
63 static int sdhci_runtime_pm_get(struct sdhci_host *host);
64 static int sdhci_runtime_pm_put(struct sdhci_host *host);
65 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
66 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
68 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
72 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
76 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
79 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
84 static void sdhci_dumpregs(struct sdhci_host *host)
86 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
87 mmc_hostname(host->mmc));
89 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
90 sdhci_readl(host, SDHCI_DMA_ADDRESS),
91 sdhci_readw(host, SDHCI_HOST_VERSION));
92 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
93 sdhci_readw(host, SDHCI_BLOCK_SIZE),
94 sdhci_readw(host, SDHCI_BLOCK_COUNT));
95 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
96 sdhci_readl(host, SDHCI_ARGUMENT),
97 sdhci_readw(host, SDHCI_TRANSFER_MODE));
98 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
99 sdhci_readl(host, SDHCI_PRESENT_STATE),
100 sdhci_readb(host, SDHCI_HOST_CONTROL));
101 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
102 sdhci_readb(host, SDHCI_POWER_CONTROL),
103 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
104 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
105 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
106 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
107 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
108 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
109 sdhci_readl(host, SDHCI_INT_STATUS));
110 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
111 sdhci_readl(host, SDHCI_INT_ENABLE),
112 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
113 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
114 sdhci_readw(host, SDHCI_ACMD12_ERR),
115 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
116 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
117 sdhci_readl(host, SDHCI_CAPABILITIES),
118 sdhci_readl(host, SDHCI_CAPABILITIES_1));
119 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
120 sdhci_readw(host, SDHCI_COMMAND),
121 sdhci_readl(host, SDHCI_MAX_CURRENT));
122 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
123 sdhci_readw(host, SDHCI_HOST_CONTROL2));
125 if (host->flags & SDHCI_USE_ADMA) {
126 if (host->flags & SDHCI_USE_64_BIT_DMA)
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
132 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
133 readl(host->ioaddr + SDHCI_ADMA_ERROR),
134 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
137 pr_debug(DRIVER_NAME ": ===========================================\n");
140 /*****************************************************************************\
142 * Low level functions *
144 \*****************************************************************************/
146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
158 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
159 SDHCI_INT_CARD_INSERT;
161 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
164 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
165 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
168 static void sdhci_enable_card_detection(struct sdhci_host *host)
170 sdhci_set_card_detection(host, true);
173 static void sdhci_disable_card_detection(struct sdhci_host *host)
175 sdhci_set_card_detection(host, false);
178 void sdhci_reset(struct sdhci_host *host, u8 mask)
180 unsigned long timeout;
182 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
184 if (mask & SDHCI_RESET_ALL) {
186 /* Reset-all turns off SD Bus Power */
187 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
188 sdhci_runtime_pm_bus_off(host);
191 /* Wait max 100 ms */
194 /* hw clears the bit when it's done */
195 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
197 pr_err("%s: Reset 0x%x never completed.\n",
198 mmc_hostname(host->mmc), (int)mask);
199 sdhci_dumpregs(host);
206 EXPORT_SYMBOL_GPL(sdhci_reset);
208 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
210 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
211 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
216 host->ops->reset(host, mask);
218 if (mask & SDHCI_RESET_ALL) {
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if (host->ops->enable_dma)
221 host->ops->enable_dma(host);
224 /* Resetting the controller clears many */
225 host->preset_enabled = false;
229 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
231 static void sdhci_init(struct sdhci_host *host, int soft)
234 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
236 sdhci_do_reset(host, SDHCI_RESET_ALL);
238 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
239 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
240 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
241 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
244 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
245 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
248 /* force clock reconfiguration */
250 sdhci_set_ios(host->mmc, &host->mmc->ios);
254 static void sdhci_reinit(struct sdhci_host *host)
258 * Retuning stuffs are affected by different cards inserted and only
259 * applicable to UHS-I cards. So reset these fields to their initial
260 * value when card is removed.
262 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
263 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
265 del_timer_sync(&host->tuning_timer);
266 host->flags &= ~SDHCI_NEEDS_RETUNING;
268 sdhci_enable_card_detection(host);
271 static void sdhci_activate_led(struct sdhci_host *host)
275 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
276 ctrl |= SDHCI_CTRL_LED;
277 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
280 static void sdhci_deactivate_led(struct sdhci_host *host)
284 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
285 ctrl &= ~SDHCI_CTRL_LED;
286 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
289 #ifdef SDHCI_USE_LEDS_CLASS
290 static void sdhci_led_control(struct led_classdev *led,
291 enum led_brightness brightness)
293 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
296 spin_lock_irqsave(&host->lock, flags);
298 if (host->runtime_suspended)
301 if (brightness == LED_OFF)
302 sdhci_deactivate_led(host);
304 sdhci_activate_led(host);
306 spin_unlock_irqrestore(&host->lock, flags);
310 /*****************************************************************************\
314 \*****************************************************************************/
316 static void sdhci_read_block_pio(struct sdhci_host *host)
319 size_t blksize, len, chunk;
320 u32 uninitialized_var(scratch);
323 DBG("PIO reading\n");
325 blksize = host->data->blksz;
328 local_irq_save(flags);
331 if (!sg_miter_next(&host->sg_miter))
334 len = min(host->sg_miter.length, blksize);
337 host->sg_miter.consumed = len;
339 buf = host->sg_miter.addr;
343 scratch = sdhci_readl(host, SDHCI_BUFFER);
347 *buf = scratch & 0xFF;
356 sg_miter_stop(&host->sg_miter);
358 local_irq_restore(flags);
361 static void sdhci_write_block_pio(struct sdhci_host *host)
364 size_t blksize, len, chunk;
368 DBG("PIO writing\n");
370 blksize = host->data->blksz;
374 local_irq_save(flags);
377 if (!sg_miter_next(&host->sg_miter))
380 len = min(host->sg_miter.length, blksize);
383 host->sg_miter.consumed = len;
385 buf = host->sg_miter.addr;
388 scratch |= (u32)*buf << (chunk * 8);
394 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
395 sdhci_writel(host, scratch, SDHCI_BUFFER);
402 sg_miter_stop(&host->sg_miter);
404 local_irq_restore(flags);
407 static void sdhci_transfer_pio(struct sdhci_host *host)
413 if (host->blocks == 0)
416 if (host->data->flags & MMC_DATA_READ)
417 mask = SDHCI_DATA_AVAILABLE;
419 mask = SDHCI_SPACE_AVAILABLE;
422 * Some controllers (JMicron JMB38x) mess up the buffer bits
423 * for transfers < 4 bytes. As long as it is just one block,
424 * we can ignore the bits.
426 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
427 (host->data->blocks == 1))
430 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
431 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
434 if (host->data->flags & MMC_DATA_READ)
435 sdhci_read_block_pio(host);
437 sdhci_write_block_pio(host);
440 if (host->blocks == 0)
444 DBG("PIO transfer complete.\n");
447 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
449 local_irq_save(*flags);
450 return kmap_atomic(sg_page(sg)) + sg->offset;
453 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
455 kunmap_atomic(buffer);
456 local_irq_restore(*flags);
459 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
460 dma_addr_t addr, int len, unsigned cmd)
462 struct sdhci_adma2_64_desc *dma_desc = desc;
464 /* 32-bit and 64-bit descriptors have these members in same position */
465 dma_desc->cmd = cpu_to_le16(cmd);
466 dma_desc->len = cpu_to_le16(len);
467 dma_desc->addr_lo = cpu_to_le32((u32)addr);
469 if (host->flags & SDHCI_USE_64_BIT_DMA)
470 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
473 static void sdhci_adma_mark_end(void *desc)
475 struct sdhci_adma2_64_desc *dma_desc = desc;
477 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
478 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
481 static int sdhci_adma_table_pre(struct sdhci_host *host,
482 struct mmc_data *data)
489 dma_addr_t align_addr;
492 struct scatterlist *sg;
498 * The spec does not specify endianness of descriptor table.
499 * We currently guess that it is LE.
502 if (data->flags & MMC_DATA_READ)
503 direction = DMA_FROM_DEVICE;
505 direction = DMA_TO_DEVICE;
507 host->align_addr = dma_map_single(mmc_dev(host->mmc),
508 host->align_buffer, host->align_buffer_sz, direction);
509 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
511 BUG_ON(host->align_addr & host->align_mask);
513 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
514 if (host->sg_count < 0)
517 desc = host->adma_table;
518 align = host->align_buffer;
520 align_addr = host->align_addr;
522 for_each_sg(data->sg, sg, host->sg_count, i) {
523 addr = sg_dma_address(sg);
524 len = sg_dma_len(sg);
527 * The SDHCI specification states that ADMA
528 * addresses must be 32-bit aligned. If they
529 * aren't, then we use a bounce buffer for
530 * the (up to three) bytes that screw up the
533 offset = (host->align_sz - (addr & host->align_mask)) &
536 if (data->flags & MMC_DATA_WRITE) {
537 buffer = sdhci_kmap_atomic(sg, &flags);
538 memcpy(align, buffer, offset);
539 sdhci_kunmap_atomic(buffer, &flags);
543 sdhci_adma_write_desc(host, desc, align_addr, offset,
546 BUG_ON(offset > 65536);
548 align += host->align_sz;
549 align_addr += host->align_sz;
551 desc += host->desc_sz;
560 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
561 desc += host->desc_sz;
564 * If this triggers then we have a calculation bug
567 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
570 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
572 * Mark the last descriptor as the terminating descriptor
574 if (desc != host->adma_table) {
575 desc -= host->desc_sz;
576 sdhci_adma_mark_end(desc);
580 * Add a terminating entry.
583 /* nop, end, valid */
584 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
588 * Resync align buffer as we might have changed it.
590 if (data->flags & MMC_DATA_WRITE) {
591 dma_sync_single_for_device(mmc_dev(host->mmc),
592 host->align_addr, host->align_buffer_sz, direction);
598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
599 host->align_buffer_sz, direction);
604 static void sdhci_adma_table_post(struct sdhci_host *host,
605 struct mmc_data *data)
609 struct scatterlist *sg;
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
619 direction = DMA_TO_DEVICE;
621 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
622 host->align_buffer_sz, direction);
624 /* Do a quick scan of the SG list for any unaligned mappings */
625 has_unaligned = false;
626 for_each_sg(data->sg, sg, host->sg_count, i)
627 if (sg_dma_address(sg) & host->align_mask) {
628 has_unaligned = true;
632 if (has_unaligned && data->flags & MMC_DATA_READ) {
633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634 data->sg_len, direction);
636 align = host->align_buffer;
638 for_each_sg(data->sg, sg, host->sg_count, i) {
639 if (sg_dma_address(sg) & host->align_mask) {
640 size = host->align_sz -
641 (sg_dma_address(sg) & host->align_mask);
643 buffer = sdhci_kmap_atomic(sg, &flags);
644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
647 align += host->align_sz;
652 if (!data->host_cookie)
653 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
654 data->sg_len, direction);
657 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
660 struct mmc_data *data = cmd->data;
661 unsigned target_timeout, current_timeout;
664 * If the host controller provides us with an incorrect timeout
665 * value, just skip the check and use 0xE. The hardware may take
666 * longer to time out, but that's much better than having a too-short
669 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
672 /* Unspecified timeout, assume max */
673 if (!data && !cmd->busy_timeout)
678 target_timeout = cmd->busy_timeout * 1000;
680 target_timeout = data->timeout_ns / 1000;
682 target_timeout += data->timeout_clks / host->clock;
686 * Figure out needed cycles.
687 * We do this in steps in order to fit inside a 32 bit int.
688 * The first step is the minimum timeout, which will have a
689 * minimum resolution of 6 bits:
690 * (1) 2^13*1000 > 2^22,
691 * (2) host->timeout_clk < 2^16
696 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
697 while (current_timeout < target_timeout) {
699 current_timeout <<= 1;
705 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
706 mmc_hostname(host->mmc), count, cmd->opcode);
713 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
715 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
716 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
718 if (host->flags & SDHCI_REQ_USE_DMA)
719 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
721 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
723 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
724 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
727 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
731 if (host->ops->set_timeout) {
732 host->ops->set_timeout(host, cmd);
734 count = sdhci_calc_timeout(host, cmd);
735 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
742 struct mmc_data *data = cmd->data;
747 if (data || (cmd->flags & MMC_RSP_BUSY))
748 sdhci_set_timeout(host, cmd);
754 BUG_ON(data->blksz * data->blocks > 524288);
755 BUG_ON(data->blksz > host->mmc->max_blk_size);
756 BUG_ON(data->blocks > 65535);
759 host->data_early = 0;
760 host->data->bytes_xfered = 0;
762 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
763 host->flags |= SDHCI_REQ_USE_DMA;
766 * FIXME: This doesn't account for merging when mapping the
769 if (host->flags & SDHCI_REQ_USE_DMA) {
771 struct scatterlist *sg;
774 if (host->flags & SDHCI_USE_ADMA) {
775 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
782 if (unlikely(broken)) {
783 for_each_sg(data->sg, sg, data->sg_len, i) {
784 if (sg->length & 0x3) {
785 DBG("Reverting to PIO because of "
786 "transfer size (%d)\n",
788 host->flags &= ~SDHCI_REQ_USE_DMA;
796 * The assumption here being that alignment is the same after
797 * translation to device address space.
799 if (host->flags & SDHCI_REQ_USE_DMA) {
801 struct scatterlist *sg;
804 if (host->flags & SDHCI_USE_ADMA) {
806 * As we use 3 byte chunks to work around
807 * alignment problems, we need to check this
810 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
813 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
817 if (unlikely(broken)) {
818 for_each_sg(data->sg, sg, data->sg_len, i) {
819 if (sg->offset & 0x3) {
820 DBG("Reverting to PIO because of "
822 host->flags &= ~SDHCI_REQ_USE_DMA;
829 if (host->flags & SDHCI_REQ_USE_DMA) {
830 if (host->flags & SDHCI_USE_ADMA) {
831 ret = sdhci_adma_table_pre(host, data);
834 * This only happens when someone fed
835 * us an invalid request.
838 host->flags &= ~SDHCI_REQ_USE_DMA;
840 sdhci_writel(host, host->adma_addr,
842 if (host->flags & SDHCI_USE_64_BIT_DMA)
844 (u64)host->adma_addr >> 32,
845 SDHCI_ADMA_ADDRESS_HI);
850 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
853 * This only happens when someone fed
854 * us an invalid request.
857 host->flags &= ~SDHCI_REQ_USE_DMA;
859 WARN_ON(sg_cnt != 1);
860 sdhci_writel(host, sg_dma_address(data->sg),
867 * Always adjust the DMA selection as some controllers
868 * (e.g. JMicron) can't do PIO properly when the selection
871 if (host->version >= SDHCI_SPEC_200) {
872 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
873 ctrl &= ~SDHCI_CTRL_DMA_MASK;
874 if ((host->flags & SDHCI_REQ_USE_DMA) &&
875 (host->flags & SDHCI_USE_ADMA)) {
876 if (host->flags & SDHCI_USE_64_BIT_DMA)
877 ctrl |= SDHCI_CTRL_ADMA64;
879 ctrl |= SDHCI_CTRL_ADMA32;
881 ctrl |= SDHCI_CTRL_SDMA;
883 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
886 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
889 flags = SG_MITER_ATOMIC;
890 if (host->data->flags & MMC_DATA_READ)
891 flags |= SG_MITER_TO_SG;
893 flags |= SG_MITER_FROM_SG;
894 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
895 host->blocks = data->blocks;
898 sdhci_set_transfer_irqs(host);
900 /* Set the DMA boundary value and block size */
901 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
902 data->blksz), SDHCI_BLOCK_SIZE);
903 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
906 static void sdhci_set_transfer_mode(struct sdhci_host *host,
907 struct mmc_command *cmd)
910 struct mmc_data *data = cmd->data;
914 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
915 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
917 /* clear Auto CMD settings for no data CMDs */
918 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
919 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
920 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
925 WARN_ON(!host->data);
927 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
928 mode = SDHCI_TRNS_BLK_CNT_EN;
930 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
931 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
933 * If we are sending CMD23, CMD12 never gets sent
934 * on successful completion (so no Auto-CMD12).
936 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
937 (cmd->opcode != SD_IO_RW_EXTENDED))
938 mode |= SDHCI_TRNS_AUTO_CMD12;
939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940 mode |= SDHCI_TRNS_AUTO_CMD23;
941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
945 if (data->flags & MMC_DATA_READ)
946 mode |= SDHCI_TRNS_READ;
947 if (host->flags & SDHCI_REQ_USE_DMA)
948 mode |= SDHCI_TRNS_DMA;
950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
953 static void sdhci_finish_data(struct sdhci_host *host)
955 struct mmc_data *data;
962 if (host->flags & SDHCI_REQ_USE_DMA) {
963 if (host->flags & SDHCI_USE_ADMA)
964 sdhci_adma_table_post(host, data);
966 if (!data->host_cookie)
967 dma_unmap_sg(mmc_dev(host->mmc),
968 data->sg, data->sg_len,
969 (data->flags & MMC_DATA_READ) ?
970 DMA_FROM_DEVICE : DMA_TO_DEVICE);
975 * The specification states that the block count register must
976 * be updated, but it does not specify at what point in the
977 * data flow. That makes the register entirely useless to read
978 * back so we have to assume that nothing made it to the card
979 * in the event of an error.
982 data->bytes_xfered = 0;
984 data->bytes_xfered = data->blksz * data->blocks;
987 * Need to send CMD12 if -
988 * a) open-ended multiblock transfer (no CMD23)
989 * b) error in multiblock transfer
996 * The controller needs a reset of internal state machines
997 * upon error conditions.
1000 sdhci_do_reset(host, SDHCI_RESET_CMD);
1001 sdhci_do_reset(host, SDHCI_RESET_DATA);
1004 sdhci_send_command(host, data->stop);
1006 tasklet_schedule(&host->finish_tasklet);
1009 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1013 unsigned long timeout;
1017 /* Wait max 10 ms */
1020 mask = SDHCI_CMD_INHIBIT;
1021 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1022 mask |= SDHCI_DATA_INHIBIT;
1024 /* We shouldn't wait for data inihibit for stop commands, even
1025 though they might use busy signaling */
1026 if (host->mrq->data && (cmd == host->mrq->data->stop))
1027 mask &= ~SDHCI_DATA_INHIBIT;
1029 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1031 pr_err("%s: Controller never released "
1032 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1033 sdhci_dumpregs(host);
1035 tasklet_schedule(&host->finish_tasklet);
1043 if (!cmd->data && cmd->busy_timeout > 9000)
1044 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1047 mod_timer(&host->timer, timeout);
1050 host->busy_handle = 0;
1052 sdhci_prepare_data(host, cmd);
1054 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1056 sdhci_set_transfer_mode(host, cmd);
1058 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1059 pr_err("%s: Unsupported response type!\n",
1060 mmc_hostname(host->mmc));
1061 cmd->error = -EINVAL;
1062 tasklet_schedule(&host->finish_tasklet);
1066 if (!(cmd->flags & MMC_RSP_PRESENT))
1067 flags = SDHCI_CMD_RESP_NONE;
1068 else if (cmd->flags & MMC_RSP_136)
1069 flags = SDHCI_CMD_RESP_LONG;
1070 else if (cmd->flags & MMC_RSP_BUSY)
1071 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1073 flags = SDHCI_CMD_RESP_SHORT;
1075 if (cmd->flags & MMC_RSP_CRC)
1076 flags |= SDHCI_CMD_CRC;
1077 if (cmd->flags & MMC_RSP_OPCODE)
1078 flags |= SDHCI_CMD_INDEX;
1080 /* CMD19 is special in that the Data Present Select should be set */
1081 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1082 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1083 flags |= SDHCI_CMD_DATA;
1085 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1087 EXPORT_SYMBOL_GPL(sdhci_send_command);
1089 static void sdhci_finish_command(struct sdhci_host *host)
1093 BUG_ON(host->cmd == NULL);
1095 if (host->cmd->flags & MMC_RSP_PRESENT) {
1096 if (host->cmd->flags & MMC_RSP_136) {
1097 /* CRC is stripped so we need to do some shifting. */
1098 for (i = 0;i < 4;i++) {
1099 host->cmd->resp[i] = sdhci_readl(host,
1100 SDHCI_RESPONSE + (3-i)*4) << 8;
1102 host->cmd->resp[i] |=
1104 SDHCI_RESPONSE + (3-i)*4-1);
1107 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1111 host->cmd->error = 0;
1113 /* Finished CMD23, now send actual command. */
1114 if (host->cmd == host->mrq->sbc) {
1116 sdhci_send_command(host, host->mrq->cmd);
1119 /* Processed actual command. */
1120 if (host->data && host->data_early)
1121 sdhci_finish_data(host);
1123 if (!host->cmd->data)
1124 tasklet_schedule(&host->finish_tasklet);
1130 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1134 switch (host->timing) {
1135 case MMC_TIMING_UHS_SDR12:
1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1138 case MMC_TIMING_UHS_SDR25:
1139 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1141 case MMC_TIMING_UHS_SDR50:
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1144 case MMC_TIMING_UHS_SDR104:
1145 case MMC_TIMING_MMC_HS200:
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1148 case MMC_TIMING_UHS_DDR50:
1149 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1151 case MMC_TIMING_MMC_HS400:
1152 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1155 pr_warn("%s: Invalid UHS-I mode selected\n",
1156 mmc_hostname(host->mmc));
1157 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1163 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1165 int div = 0; /* Initialized for compiler warning */
1166 int real_div = div, clk_mul = 1;
1168 unsigned long timeout;
1170 host->mmc->actual_clock = 0;
1172 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1177 if (host->version >= SDHCI_SPEC_300) {
1178 if (host->preset_enabled) {
1181 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1182 pre_val = sdhci_get_preset_value(host);
1183 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1184 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1185 if (host->clk_mul &&
1186 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1187 clk = SDHCI_PROG_CLOCK_MODE;
1189 clk_mul = host->clk_mul;
1191 real_div = max_t(int, 1, div << 1);
1197 * Check if the Host Controller supports Programmable Clock
1200 if (host->clk_mul) {
1201 for (div = 1; div <= 1024; div++) {
1202 if ((host->max_clk * host->clk_mul / div)
1207 * Set Programmable Clock Mode in the Clock
1210 clk = SDHCI_PROG_CLOCK_MODE;
1212 clk_mul = host->clk_mul;
1215 /* Version 3.00 divisors must be a multiple of 2. */
1216 if (host->max_clk <= clock)
1219 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1221 if ((host->max_clk / div) <= clock)
1229 /* Version 2.00 divisors must be a power of 2. */
1230 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1231 if ((host->max_clk / div) <= clock)
1240 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1241 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1242 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1243 << SDHCI_DIVIDER_HI_SHIFT;
1244 clk |= SDHCI_CLOCK_INT_EN;
1245 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1247 /* Wait max 20 ms */
1249 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1250 & SDHCI_CLOCK_INT_STABLE)) {
1252 pr_err("%s: Internal clock never "
1253 "stabilised.\n", mmc_hostname(host->mmc));
1254 sdhci_dumpregs(host);
1261 clk |= SDHCI_CLOCK_CARD_EN;
1262 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1264 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1266 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1269 struct mmc_host *mmc = host->mmc;
1272 if (!IS_ERR(mmc->supply.vmmc)) {
1273 spin_unlock_irq(&host->lock);
1274 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1275 spin_lock_irq(&host->lock);
1277 if (mode != MMC_POWER_OFF)
1278 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1280 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1285 if (mode != MMC_POWER_OFF) {
1287 case MMC_VDD_165_195:
1288 pwr = SDHCI_POWER_180;
1292 pwr = SDHCI_POWER_300;
1296 pwr = SDHCI_POWER_330;
1303 if (host->pwr == pwr)
1309 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1310 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1311 sdhci_runtime_pm_bus_off(host);
1315 * Spec says that we should clear the power reg before setting
1316 * a new value. Some controllers don't seem to like this though.
1318 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1319 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1322 * At least the Marvell CaFe chip gets confused if we set the
1323 * voltage and set turn on power at the same time, so set the
1326 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1327 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1329 pwr |= SDHCI_POWER_ON;
1331 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1333 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1334 sdhci_runtime_pm_bus_on(host);
1337 * Some controllers need an extra 10ms delay of 10ms before
1338 * they can apply clock after applying power
1340 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1345 /*****************************************************************************\
1349 \*****************************************************************************/
1351 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1353 struct sdhci_host *host;
1355 unsigned long flags;
1358 host = mmc_priv(mmc);
1360 sdhci_runtime_pm_get(host);
1362 /* Firstly check card presence */
1363 present = sdhci_do_get_cd(host);
1365 spin_lock_irqsave(&host->lock, flags);
1367 WARN_ON(host->mrq != NULL);
1369 #ifndef SDHCI_USE_LEDS_CLASS
1370 sdhci_activate_led(host);
1374 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1375 * requests if Auto-CMD12 is enabled.
1377 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1379 mrq->data->stop = NULL;
1386 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1387 host->mrq->cmd->error = -ENOMEDIUM;
1388 tasklet_schedule(&host->finish_tasklet);
1392 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1394 * Check if the re-tuning timer has already expired and there
1395 * is no on-going data transfer and DAT0 is not busy. If so,
1396 * we need to execute tuning procedure before sending command.
1398 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1399 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1400 (present_state & SDHCI_DATA_0_LVL_MASK)) {
1402 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1404 mmc->card->type == MMC_TYPE_MMC ?
1405 MMC_SEND_TUNING_BLOCK_HS200 :
1406 MMC_SEND_TUNING_BLOCK;
1408 /* Here we need to set the host->mrq to NULL,
1409 * in case the pending finish_tasklet
1410 * finishes it incorrectly.
1414 spin_unlock_irqrestore(&host->lock, flags);
1415 sdhci_execute_tuning(mmc, tuning_opcode);
1416 spin_lock_irqsave(&host->lock, flags);
1418 /* Restore original mmc_request structure */
1423 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1424 sdhci_send_command(host, mrq->sbc);
1426 sdhci_send_command(host, mrq->cmd);
1430 spin_unlock_irqrestore(&host->lock, flags);
1433 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1437 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1438 if (width == MMC_BUS_WIDTH_8) {
1439 ctrl &= ~SDHCI_CTRL_4BITBUS;
1440 if (host->version >= SDHCI_SPEC_300)
1441 ctrl |= SDHCI_CTRL_8BITBUS;
1443 if (host->version >= SDHCI_SPEC_300)
1444 ctrl &= ~SDHCI_CTRL_8BITBUS;
1445 if (width == MMC_BUS_WIDTH_4)
1446 ctrl |= SDHCI_CTRL_4BITBUS;
1448 ctrl &= ~SDHCI_CTRL_4BITBUS;
1450 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1452 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1454 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1458 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1459 /* Select Bus Speed Mode for host */
1460 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1461 if ((timing == MMC_TIMING_MMC_HS200) ||
1462 (timing == MMC_TIMING_UHS_SDR104))
1463 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1464 else if (timing == MMC_TIMING_UHS_SDR12)
1465 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1466 else if (timing == MMC_TIMING_UHS_SDR25)
1467 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1468 else if (timing == MMC_TIMING_UHS_SDR50)
1469 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1470 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1471 (timing == MMC_TIMING_MMC_DDR52))
1472 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1473 else if (timing == MMC_TIMING_MMC_HS400)
1474 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1475 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1477 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1479 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1481 unsigned long flags;
1483 struct mmc_host *mmc = host->mmc;
1485 spin_lock_irqsave(&host->lock, flags);
1487 if (host->flags & SDHCI_DEVICE_DEAD) {
1488 spin_unlock_irqrestore(&host->lock, flags);
1489 if (!IS_ERR(mmc->supply.vmmc) &&
1490 ios->power_mode == MMC_POWER_OFF)
1491 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1496 * Reset the chip on each power off.
1497 * Should clear out any weird states.
1499 if (ios->power_mode == MMC_POWER_OFF) {
1500 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1504 if (host->version >= SDHCI_SPEC_300 &&
1505 (ios->power_mode == MMC_POWER_UP) &&
1506 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1507 sdhci_enable_preset_value(host, false);
1509 if (!ios->clock || ios->clock != host->clock) {
1510 host->ops->set_clock(host, ios->clock);
1511 host->clock = ios->clock;
1513 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1515 host->timeout_clk = host->mmc->actual_clock ?
1516 host->mmc->actual_clock / 1000 :
1518 host->mmc->max_busy_timeout =
1519 host->ops->get_max_timeout_count ?
1520 host->ops->get_max_timeout_count(host) :
1522 host->mmc->max_busy_timeout /= host->timeout_clk;
1526 sdhci_set_power(host, ios->power_mode, ios->vdd);
1528 if (host->ops->platform_send_init_74_clocks)
1529 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1531 host->ops->set_bus_width(host, ios->bus_width);
1533 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1535 if ((ios->timing == MMC_TIMING_SD_HS ||
1536 ios->timing == MMC_TIMING_MMC_HS)
1537 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1538 ctrl |= SDHCI_CTRL_HISPD;
1540 ctrl &= ~SDHCI_CTRL_HISPD;
1542 if (host->version >= SDHCI_SPEC_300) {
1545 /* In case of UHS-I modes, set High Speed Enable */
1546 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1547 (ios->timing == MMC_TIMING_MMC_HS200) ||
1548 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1549 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1550 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1551 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1552 (ios->timing == MMC_TIMING_UHS_SDR25))
1553 ctrl |= SDHCI_CTRL_HISPD;
1555 if (!host->preset_enabled) {
1556 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1558 * We only need to set Driver Strength if the
1559 * preset value enable is not set.
1561 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1562 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1563 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1564 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1565 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1566 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1568 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1571 * According to SDHC Spec v3.00, if the Preset Value
1572 * Enable in the Host Control 2 register is set, we
1573 * need to reset SD Clock Enable before changing High
1574 * Speed Enable to avoid generating clock gliches.
1577 /* Reset SD Clock Enable */
1578 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1579 clk &= ~SDHCI_CLOCK_CARD_EN;
1580 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1582 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1584 /* Re-enable SD Clock */
1585 host->ops->set_clock(host, host->clock);
1588 /* Reset SD Clock Enable */
1589 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1590 clk &= ~SDHCI_CLOCK_CARD_EN;
1591 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1593 host->ops->set_uhs_signaling(host, ios->timing);
1594 host->timing = ios->timing;
1596 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1597 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1598 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1599 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1600 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1601 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1604 sdhci_enable_preset_value(host, true);
1605 preset = sdhci_get_preset_value(host);
1606 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1607 >> SDHCI_PRESET_DRV_SHIFT;
1610 /* Re-enable SD Clock */
1611 host->ops->set_clock(host, host->clock);
1613 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1616 * Some (ENE) controllers go apeshit on some ios operation,
1617 * signalling timeout and CRC errors even on CMD0. Resetting
1618 * it on each ios seems to solve the problem.
1620 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1621 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1624 spin_unlock_irqrestore(&host->lock, flags);
1627 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1629 struct sdhci_host *host = mmc_priv(mmc);
1631 sdhci_runtime_pm_get(host);
1632 sdhci_do_set_ios(host, ios);
1633 sdhci_runtime_pm_put(host);
1636 static int sdhci_do_get_cd(struct sdhci_host *host)
1638 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1640 if (host->flags & SDHCI_DEVICE_DEAD)
1643 /* If polling/nonremovable, assume that the card is always present. */
1644 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1645 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1648 /* Try slot gpio detect */
1649 if (!IS_ERR_VALUE(gpio_cd))
1652 /* Host native card detect */
1653 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1656 static int sdhci_get_cd(struct mmc_host *mmc)
1658 struct sdhci_host *host = mmc_priv(mmc);
1661 sdhci_runtime_pm_get(host);
1662 ret = sdhci_do_get_cd(host);
1663 sdhci_runtime_pm_put(host);
1667 static int sdhci_check_ro(struct sdhci_host *host)
1669 unsigned long flags;
1672 spin_lock_irqsave(&host->lock, flags);
1674 if (host->flags & SDHCI_DEVICE_DEAD)
1676 else if (host->ops->get_ro)
1677 is_readonly = host->ops->get_ro(host);
1679 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1680 & SDHCI_WRITE_PROTECT);
1682 spin_unlock_irqrestore(&host->lock, flags);
1684 /* This quirk needs to be replaced by a callback-function later */
1685 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1686 !is_readonly : is_readonly;
1689 #define SAMPLE_COUNT 5
1691 static int sdhci_do_get_ro(struct sdhci_host *host)
1695 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1696 return sdhci_check_ro(host);
1699 for (i = 0; i < SAMPLE_COUNT; i++) {
1700 if (sdhci_check_ro(host)) {
1701 if (++ro_count > SAMPLE_COUNT / 2)
1709 static void sdhci_hw_reset(struct mmc_host *mmc)
1711 struct sdhci_host *host = mmc_priv(mmc);
1713 if (host->ops && host->ops->hw_reset)
1714 host->ops->hw_reset(host);
1717 static int sdhci_get_ro(struct mmc_host *mmc)
1719 struct sdhci_host *host = mmc_priv(mmc);
1722 sdhci_runtime_pm_get(host);
1723 ret = sdhci_do_get_ro(host);
1724 sdhci_runtime_pm_put(host);
1728 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1730 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1732 host->ier |= SDHCI_INT_CARD_INT;
1734 host->ier &= ~SDHCI_INT_CARD_INT;
1736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1742 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1744 struct sdhci_host *host = mmc_priv(mmc);
1745 unsigned long flags;
1747 sdhci_runtime_pm_get(host);
1749 spin_lock_irqsave(&host->lock, flags);
1751 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1753 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1755 sdhci_enable_sdio_irq_nolock(host, enable);
1756 spin_unlock_irqrestore(&host->lock, flags);
1758 sdhci_runtime_pm_put(host);
1761 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1762 struct mmc_ios *ios)
1764 struct mmc_host *mmc = host->mmc;
1769 * Signal Voltage Switching is only applicable for Host Controllers
1772 if (host->version < SDHCI_SPEC_300)
1775 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1777 switch (ios->signal_voltage) {
1778 case MMC_SIGNAL_VOLTAGE_330:
1779 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1780 ctrl &= ~SDHCI_CTRL_VDD_180;
1781 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1783 if (!IS_ERR(mmc->supply.vqmmc)) {
1784 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1787 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1793 usleep_range(5000, 5500);
1795 /* 3.3V regulator output should be stable within 5 ms */
1796 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1797 if (!(ctrl & SDHCI_CTRL_VDD_180))
1800 pr_warn("%s: 3.3V regulator output did not became stable\n",
1804 case MMC_SIGNAL_VOLTAGE_180:
1805 if (!IS_ERR(mmc->supply.vqmmc)) {
1806 ret = regulator_set_voltage(mmc->supply.vqmmc,
1809 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1816 * Enable 1.8V Signal Enable in the Host Control2
1819 ctrl |= SDHCI_CTRL_VDD_180;
1820 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1822 /* Some controller need to do more when switching */
1823 if (host->ops->voltage_switch)
1824 host->ops->voltage_switch(host);
1826 /* 1.8V regulator output should be stable within 5 ms */
1827 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1828 if (ctrl & SDHCI_CTRL_VDD_180)
1831 pr_warn("%s: 1.8V regulator output did not became stable\n",
1835 case MMC_SIGNAL_VOLTAGE_120:
1836 if (!IS_ERR(mmc->supply.vqmmc)) {
1837 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1840 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1847 /* No signal voltage switch required */
1852 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1853 struct mmc_ios *ios)
1855 struct sdhci_host *host = mmc_priv(mmc);
1858 if (host->version < SDHCI_SPEC_300)
1860 sdhci_runtime_pm_get(host);
1861 err = sdhci_do_start_signal_voltage_switch(host, ios);
1862 sdhci_runtime_pm_put(host);
1866 static int sdhci_card_busy(struct mmc_host *mmc)
1868 struct sdhci_host *host = mmc_priv(mmc);
1871 sdhci_runtime_pm_get(host);
1872 /* Check whether DAT[3:0] is 0000 */
1873 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1874 sdhci_runtime_pm_put(host);
1876 return !(present_state & SDHCI_DATA_LVL_MASK);
1879 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1881 struct sdhci_host *host = mmc_priv(mmc);
1882 unsigned long flags;
1884 spin_lock_irqsave(&host->lock, flags);
1885 host->flags |= SDHCI_HS400_TUNING;
1886 spin_unlock_irqrestore(&host->lock, flags);
1891 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1893 struct sdhci_host *host = mmc_priv(mmc);
1895 int tuning_loop_counter = MAX_TUNING_LOOP;
1897 unsigned long flags;
1898 unsigned int tuning_count = 0;
1901 sdhci_runtime_pm_get(host);
1902 spin_lock_irqsave(&host->lock, flags);
1904 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1905 host->flags &= ~SDHCI_HS400_TUNING;
1907 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1908 tuning_count = host->tuning_count;
1911 * The Host Controller needs tuning only in case of SDR104 mode
1912 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1913 * Capabilities register.
1914 * If the Host Controller supports the HS200 mode then the
1915 * tuning function has to be executed.
1917 switch (host->timing) {
1918 /* HS400 tuning is done in HS200 mode */
1919 case MMC_TIMING_MMC_HS400:
1923 case MMC_TIMING_MMC_HS200:
1925 * Periodic re-tuning for HS400 is not expected to be needed, so
1932 case MMC_TIMING_UHS_SDR104:
1935 case MMC_TIMING_UHS_SDR50:
1936 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1937 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1945 if (host->ops->platform_execute_tuning) {
1946 spin_unlock_irqrestore(&host->lock, flags);
1947 err = host->ops->platform_execute_tuning(host, opcode);
1948 sdhci_runtime_pm_put(host);
1952 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1953 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1954 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1955 ctrl |= SDHCI_CTRL_TUNED_CLK;
1956 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1959 * As per the Host Controller spec v3.00, tuning command
1960 * generates Buffer Read Ready interrupt, so enable that.
1962 * Note: The spec clearly says that when tuning sequence
1963 * is being performed, the controller does not generate
1964 * interrupts other than Buffer Read Ready interrupt. But
1965 * to make sure we don't hit a controller bug, we _only_
1966 * enable Buffer Read Ready interrupt here.
1968 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1969 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1972 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1973 * of loops reaches 40 times or a timeout of 150ms occurs.
1976 struct mmc_command cmd = {0};
1977 struct mmc_request mrq = {NULL};
1979 cmd.opcode = opcode;
1981 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1986 if (tuning_loop_counter-- == 0)
1993 * In response to CMD19, the card sends 64 bytes of tuning
1994 * block to the Host Controller. So we set the block size
1997 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1998 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1999 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2001 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2002 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2005 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2010 * The tuning block is sent by the card to the host controller.
2011 * So we set the TRNS_READ bit in the Transfer Mode register.
2012 * This also takes care of setting DMA Enable and Multi Block
2013 * Select in the same register to 0.
2015 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2017 sdhci_send_command(host, &cmd);
2022 spin_unlock_irqrestore(&host->lock, flags);
2023 /* Wait for Buffer Read Ready interrupt */
2024 wait_event_interruptible_timeout(host->buf_ready_int,
2025 (host->tuning_done == 1),
2026 msecs_to_jiffies(50));
2027 spin_lock_irqsave(&host->lock, flags);
2029 if (!host->tuning_done) {
2030 pr_info(DRIVER_NAME ": Timeout waiting for "
2031 "Buffer Read Ready interrupt during tuning "
2032 "procedure, falling back to fixed sampling "
2034 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2035 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2036 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2037 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2043 host->tuning_done = 0;
2045 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2047 /* eMMC spec does not require a delay between tuning cycles */
2048 if (opcode == MMC_SEND_TUNING_BLOCK)
2050 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2053 * The Host Driver has exhausted the maximum number of loops allowed,
2054 * so use fixed sampling frequency.
2056 if (tuning_loop_counter < 0) {
2057 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2058 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2060 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2061 pr_info(DRIVER_NAME ": Tuning procedure"
2062 " failed, falling back to fixed sampling"
2068 host->flags &= ~SDHCI_NEEDS_RETUNING;
2071 host->flags |= SDHCI_USING_RETUNING_TIMER;
2072 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2076 * In case tuning fails, host controllers which support re-tuning can
2077 * try tuning again at a later time, when the re-tuning timer expires.
2078 * So for these controllers, we return 0. Since there might be other
2079 * controllers who do not have this capability, we return error for
2080 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2081 * a retuning timer to do the retuning for the card.
2083 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2086 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2087 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2089 spin_unlock_irqrestore(&host->lock, flags);
2090 sdhci_runtime_pm_put(host);
2096 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2098 /* Host Controller v3.00 defines preset value registers */
2099 if (host->version < SDHCI_SPEC_300)
2103 * We only enable or disable Preset Value if they are not already
2104 * enabled or disabled respectively. Otherwise, we bail out.
2106 if (host->preset_enabled != enable) {
2107 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2110 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2112 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2114 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2117 host->flags |= SDHCI_PV_ENABLED;
2119 host->flags &= ~SDHCI_PV_ENABLED;
2121 host->preset_enabled = enable;
2125 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2128 struct sdhci_host *host = mmc_priv(mmc);
2129 struct mmc_data *data = mrq->data;
2131 if (host->flags & SDHCI_REQ_USE_DMA) {
2132 if (data->host_cookie)
2133 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2134 data->flags & MMC_DATA_WRITE ?
2135 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2136 mrq->data->host_cookie = 0;
2140 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2141 struct mmc_data *data,
2142 struct sdhci_host_next *next)
2146 if (!next && data->host_cookie &&
2147 data->host_cookie != host->next_data.cookie) {
2148 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2149 __func__, data->host_cookie, host->next_data.cookie);
2150 data->host_cookie = 0;
2153 /* Check if next job is already prepared */
2155 (!next && data->host_cookie != host->next_data.cookie)) {
2156 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2158 data->flags & MMC_DATA_WRITE ?
2159 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2162 sg_count = host->next_data.sg_count;
2163 host->next_data.sg_count = 0;
2171 next->sg_count = sg_count;
2172 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2174 host->sg_count = sg_count;
2179 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2182 struct sdhci_host *host = mmc_priv(mmc);
2184 if (mrq->data->host_cookie) {
2185 mrq->data->host_cookie = 0;
2189 if (host->flags & SDHCI_REQ_USE_DMA)
2190 if (sdhci_pre_dma_transfer(host,
2192 &host->next_data) < 0)
2193 mrq->data->host_cookie = 0;
2196 static void sdhci_card_event(struct mmc_host *mmc)
2198 struct sdhci_host *host = mmc_priv(mmc);
2199 unsigned long flags;
2202 /* First check if client has provided their own card event */
2203 if (host->ops->card_event)
2204 host->ops->card_event(host);
2206 present = sdhci_do_get_cd(host);
2208 spin_lock_irqsave(&host->lock, flags);
2210 /* Check host->mrq first in case we are runtime suspended */
2211 if (host->mrq && !present) {
2212 pr_err("%s: Card removed during transfer!\n",
2213 mmc_hostname(host->mmc));
2214 pr_err("%s: Resetting controller.\n",
2215 mmc_hostname(host->mmc));
2217 sdhci_do_reset(host, SDHCI_RESET_CMD);
2218 sdhci_do_reset(host, SDHCI_RESET_DATA);
2220 host->mrq->cmd->error = -ENOMEDIUM;
2221 tasklet_schedule(&host->finish_tasklet);
2224 spin_unlock_irqrestore(&host->lock, flags);
2227 static const struct mmc_host_ops sdhci_ops = {
2228 .request = sdhci_request,
2229 .post_req = sdhci_post_req,
2230 .pre_req = sdhci_pre_req,
2231 .set_ios = sdhci_set_ios,
2232 .get_cd = sdhci_get_cd,
2233 .get_ro = sdhci_get_ro,
2234 .hw_reset = sdhci_hw_reset,
2235 .enable_sdio_irq = sdhci_enable_sdio_irq,
2236 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2237 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2238 .execute_tuning = sdhci_execute_tuning,
2239 .card_event = sdhci_card_event,
2240 .card_busy = sdhci_card_busy,
2243 /*****************************************************************************\
2247 \*****************************************************************************/
2249 static void sdhci_tasklet_finish(unsigned long param)
2251 struct sdhci_host *host;
2252 unsigned long flags;
2253 struct mmc_request *mrq;
2255 host = (struct sdhci_host*)param;
2257 spin_lock_irqsave(&host->lock, flags);
2260 * If this tasklet gets rescheduled while running, it will
2261 * be run again afterwards but without any active request.
2264 spin_unlock_irqrestore(&host->lock, flags);
2268 del_timer(&host->timer);
2273 * The controller needs a reset of internal state machines
2274 * upon error conditions.
2276 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2277 ((mrq->cmd && mrq->cmd->error) ||
2278 (mrq->sbc && mrq->sbc->error) ||
2279 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2280 (mrq->data->stop && mrq->data->stop->error))) ||
2281 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2283 /* Some controllers need this kick or reset won't work here */
2284 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2285 /* This is to force an update */
2286 host->ops->set_clock(host, host->clock);
2288 /* Spec says we should do both at the same time, but Ricoh
2289 controllers do not like that. */
2290 sdhci_do_reset(host, SDHCI_RESET_CMD);
2291 sdhci_do_reset(host, SDHCI_RESET_DATA);
2298 #ifndef SDHCI_USE_LEDS_CLASS
2299 sdhci_deactivate_led(host);
2303 spin_unlock_irqrestore(&host->lock, flags);
2305 mmc_request_done(host->mmc, mrq);
2306 sdhci_runtime_pm_put(host);
2309 static void sdhci_timeout_timer(unsigned long data)
2311 struct sdhci_host *host;
2312 unsigned long flags;
2314 host = (struct sdhci_host*)data;
2316 spin_lock_irqsave(&host->lock, flags);
2319 pr_err("%s: Timeout waiting for hardware "
2320 "interrupt.\n", mmc_hostname(host->mmc));
2321 sdhci_dumpregs(host);
2324 host->data->error = -ETIMEDOUT;
2325 sdhci_finish_data(host);
2328 host->cmd->error = -ETIMEDOUT;
2330 host->mrq->cmd->error = -ETIMEDOUT;
2332 tasklet_schedule(&host->finish_tasklet);
2337 spin_unlock_irqrestore(&host->lock, flags);
2340 static void sdhci_tuning_timer(unsigned long data)
2342 struct sdhci_host *host;
2343 unsigned long flags;
2345 host = (struct sdhci_host *)data;
2347 spin_lock_irqsave(&host->lock, flags);
2349 host->flags |= SDHCI_NEEDS_RETUNING;
2351 spin_unlock_irqrestore(&host->lock, flags);
2354 /*****************************************************************************\
2356 * Interrupt handling *
2358 \*****************************************************************************/
2360 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2362 BUG_ON(intmask == 0);
2365 pr_err("%s: Got command interrupt 0x%08x even "
2366 "though no command operation was in progress.\n",
2367 mmc_hostname(host->mmc), (unsigned)intmask);
2368 sdhci_dumpregs(host);
2372 if (intmask & SDHCI_INT_TIMEOUT)
2373 host->cmd->error = -ETIMEDOUT;
2374 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2376 host->cmd->error = -EILSEQ;
2378 if (host->cmd->error) {
2379 tasklet_schedule(&host->finish_tasklet);
2384 * The host can send and interrupt when the busy state has
2385 * ended, allowing us to wait without wasting CPU cycles.
2386 * Unfortunately this is overloaded on the "data complete"
2387 * interrupt, so we need to take some care when handling
2390 * Note: The 1.0 specification is a bit ambiguous about this
2391 * feature so there might be some problems with older
2394 if (host->cmd->flags & MMC_RSP_BUSY) {
2395 if (host->cmd->data)
2396 DBG("Cannot wait for busy signal when also "
2397 "doing a data transfer");
2398 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2399 && !host->busy_handle) {
2400 /* Mark that command complete before busy is ended */
2401 host->busy_handle = 1;
2405 /* The controller does not support the end-of-busy IRQ,
2406 * fall through and take the SDHCI_INT_RESPONSE */
2407 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2408 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2409 *mask &= ~SDHCI_INT_DATA_END;
2412 if (intmask & SDHCI_INT_RESPONSE)
2413 sdhci_finish_command(host);
2416 #ifdef CONFIG_MMC_DEBUG
2417 static void sdhci_adma_show_error(struct sdhci_host *host)
2419 const char *name = mmc_hostname(host->mmc);
2420 void *desc = host->adma_table;
2422 sdhci_dumpregs(host);
2425 struct sdhci_adma2_64_desc *dma_desc = desc;
2427 if (host->flags & SDHCI_USE_64_BIT_DMA)
2428 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2429 name, desc, le32_to_cpu(dma_desc->addr_hi),
2430 le32_to_cpu(dma_desc->addr_lo),
2431 le16_to_cpu(dma_desc->len),
2432 le16_to_cpu(dma_desc->cmd));
2434 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2435 name, desc, le32_to_cpu(dma_desc->addr_lo),
2436 le16_to_cpu(dma_desc->len),
2437 le16_to_cpu(dma_desc->cmd));
2439 desc += host->desc_sz;
2441 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2446 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2449 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2452 BUG_ON(intmask == 0);
2454 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2455 if (intmask & SDHCI_INT_DATA_AVAIL) {
2456 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2457 if (command == MMC_SEND_TUNING_BLOCK ||
2458 command == MMC_SEND_TUNING_BLOCK_HS200) {
2459 host->tuning_done = 1;
2460 wake_up(&host->buf_ready_int);
2467 * The "data complete" interrupt is also used to
2468 * indicate that a busy state has ended. See comment
2469 * above in sdhci_cmd_irq().
2471 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2472 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2473 host->cmd->error = -ETIMEDOUT;
2474 tasklet_schedule(&host->finish_tasklet);
2477 if (intmask & SDHCI_INT_DATA_END) {
2479 * Some cards handle busy-end interrupt
2480 * before the command completed, so make
2481 * sure we do things in the proper order.
2483 if (host->busy_handle)
2484 sdhci_finish_command(host);
2486 host->busy_handle = 1;
2491 pr_err("%s: Got data interrupt 0x%08x even "
2492 "though no data operation was in progress.\n",
2493 mmc_hostname(host->mmc), (unsigned)intmask);
2494 sdhci_dumpregs(host);
2499 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2500 host->data->error = -ETIMEDOUT;
2501 else if (intmask & SDHCI_INT_DATA_END_BIT)
2502 host->data->error = -EILSEQ;
2503 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2504 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2506 host->data->error = -EILSEQ;
2507 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2508 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2509 sdhci_adma_show_error(host);
2510 host->data->error = -EIO;
2511 if (host->ops->adma_workaround)
2512 host->ops->adma_workaround(host, intmask);
2515 if (host->data->error)
2516 sdhci_finish_data(host);
2518 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2519 sdhci_transfer_pio(host);
2522 * We currently don't do anything fancy with DMA
2523 * boundaries, but as we can't disable the feature
2524 * we need to at least restart the transfer.
2526 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2527 * should return a valid address to continue from, but as
2528 * some controllers are faulty, don't trust them.
2530 if (intmask & SDHCI_INT_DMA_END) {
2531 u32 dmastart, dmanow;
2532 dmastart = sg_dma_address(host->data->sg);
2533 dmanow = dmastart + host->data->bytes_xfered;
2535 * Force update to the next DMA block boundary.
2538 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2539 SDHCI_DEFAULT_BOUNDARY_SIZE;
2540 host->data->bytes_xfered = dmanow - dmastart;
2541 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2543 mmc_hostname(host->mmc), dmastart,
2544 host->data->bytes_xfered, dmanow);
2545 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2548 if (intmask & SDHCI_INT_DATA_END) {
2551 * Data managed to finish before the
2552 * command completed. Make sure we do
2553 * things in the proper order.
2555 host->data_early = 1;
2557 sdhci_finish_data(host);
2563 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2565 irqreturn_t result = IRQ_NONE;
2566 struct sdhci_host *host = dev_id;
2567 u32 intmask, mask, unexpected = 0;
2570 spin_lock(&host->lock);
2572 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2573 spin_unlock(&host->lock);
2577 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2578 if (!intmask || intmask == 0xffffffff) {
2584 /* Clear selected interrupts. */
2585 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2586 SDHCI_INT_BUS_POWER);
2587 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2589 DBG("*** %s got interrupt: 0x%08x\n",
2590 mmc_hostname(host->mmc), intmask);
2592 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2593 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2597 * There is a observation on i.mx esdhc. INSERT
2598 * bit will be immediately set again when it gets
2599 * cleared, if a card is inserted. We have to mask
2600 * the irq to prevent interrupt storm which will
2601 * freeze the system. And the REMOVE gets the
2604 * More testing are needed here to ensure it works
2605 * for other platforms though.
2607 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2608 SDHCI_INT_CARD_REMOVE);
2609 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2610 SDHCI_INT_CARD_INSERT;
2611 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2612 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2614 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2615 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2617 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2618 SDHCI_INT_CARD_REMOVE);
2619 result = IRQ_WAKE_THREAD;
2622 if (intmask & SDHCI_INT_CMD_MASK)
2623 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2626 if (intmask & SDHCI_INT_DATA_MASK)
2627 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2629 if (intmask & SDHCI_INT_BUS_POWER)
2630 pr_err("%s: Card is consuming too much power!\n",
2631 mmc_hostname(host->mmc));
2633 if (intmask & SDHCI_INT_CARD_INT) {
2634 sdhci_enable_sdio_irq_nolock(host, false);
2635 host->thread_isr |= SDHCI_INT_CARD_INT;
2636 result = IRQ_WAKE_THREAD;
2639 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2640 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2641 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2642 SDHCI_INT_CARD_INT);
2645 unexpected |= intmask;
2646 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2649 if (result == IRQ_NONE)
2650 result = IRQ_HANDLED;
2652 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2653 } while (intmask && --max_loops);
2655 spin_unlock(&host->lock);
2658 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2659 mmc_hostname(host->mmc), unexpected);
2660 sdhci_dumpregs(host);
2666 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2668 struct sdhci_host *host = dev_id;
2669 unsigned long flags;
2672 spin_lock_irqsave(&host->lock, flags);
2673 isr = host->thread_isr;
2674 host->thread_isr = 0;
2675 spin_unlock_irqrestore(&host->lock, flags);
2677 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2678 sdhci_card_event(host->mmc);
2679 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2682 if (isr & SDHCI_INT_CARD_INT) {
2683 sdio_run_irqs(host->mmc);
2685 spin_lock_irqsave(&host->lock, flags);
2686 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2687 sdhci_enable_sdio_irq_nolock(host, true);
2688 spin_unlock_irqrestore(&host->lock, flags);
2691 return isr ? IRQ_HANDLED : IRQ_NONE;
2694 /*****************************************************************************\
2698 \*****************************************************************************/
2701 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2704 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2705 | SDHCI_WAKE_ON_INT;
2707 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2709 /* Avoid fake wake up */
2710 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2711 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2712 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2714 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2716 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2719 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2720 | SDHCI_WAKE_ON_INT;
2722 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2724 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2727 int sdhci_suspend_host(struct sdhci_host *host)
2729 sdhci_disable_card_detection(host);
2731 /* Disable tuning since we are suspending */
2732 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2733 del_timer_sync(&host->tuning_timer);
2734 host->flags &= ~SDHCI_NEEDS_RETUNING;
2737 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2739 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2740 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2741 free_irq(host->irq, host);
2743 sdhci_enable_irq_wakeups(host);
2744 enable_irq_wake(host->irq);
2749 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2751 int sdhci_resume_host(struct sdhci_host *host)
2755 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2756 if (host->ops->enable_dma)
2757 host->ops->enable_dma(host);
2760 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2761 ret = request_threaded_irq(host->irq, sdhci_irq,
2762 sdhci_thread_irq, IRQF_SHARED,
2763 mmc_hostname(host->mmc), host);
2767 sdhci_disable_irq_wakeups(host);
2768 disable_irq_wake(host->irq);
2771 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2772 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2773 /* Card keeps power but host controller does not */
2774 sdhci_init(host, 0);
2777 sdhci_do_set_ios(host, &host->mmc->ios);
2779 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2783 sdhci_enable_card_detection(host);
2785 /* Set the re-tuning expiration flag */
2786 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2787 host->flags |= SDHCI_NEEDS_RETUNING;
2792 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2794 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2796 return pm_runtime_get_sync(host->mmc->parent);
2799 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2801 pm_runtime_mark_last_busy(host->mmc->parent);
2802 return pm_runtime_put_autosuspend(host->mmc->parent);
2805 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2807 if (host->runtime_suspended || host->bus_on)
2809 host->bus_on = true;
2810 pm_runtime_get_noresume(host->mmc->parent);
2813 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2815 if (host->runtime_suspended || !host->bus_on)
2817 host->bus_on = false;
2818 pm_runtime_put_noidle(host->mmc->parent);
2821 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2823 unsigned long flags;
2825 /* Disable tuning since we are suspending */
2826 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2827 del_timer_sync(&host->tuning_timer);
2828 host->flags &= ~SDHCI_NEEDS_RETUNING;
2831 spin_lock_irqsave(&host->lock, flags);
2832 host->ier &= SDHCI_INT_CARD_INT;
2833 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2834 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2835 spin_unlock_irqrestore(&host->lock, flags);
2837 synchronize_hardirq(host->irq);
2839 spin_lock_irqsave(&host->lock, flags);
2840 host->runtime_suspended = true;
2841 spin_unlock_irqrestore(&host->lock, flags);
2845 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2847 int sdhci_runtime_resume_host(struct sdhci_host *host)
2849 unsigned long flags;
2850 int host_flags = host->flags;
2852 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2853 if (host->ops->enable_dma)
2854 host->ops->enable_dma(host);
2857 sdhci_init(host, 0);
2859 /* Force clock and power re-program */
2862 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2863 sdhci_do_set_ios(host, &host->mmc->ios);
2865 if ((host_flags & SDHCI_PV_ENABLED) &&
2866 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2867 spin_lock_irqsave(&host->lock, flags);
2868 sdhci_enable_preset_value(host, true);
2869 spin_unlock_irqrestore(&host->lock, flags);
2872 /* Set the re-tuning expiration flag */
2873 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2874 host->flags |= SDHCI_NEEDS_RETUNING;
2876 spin_lock_irqsave(&host->lock, flags);
2878 host->runtime_suspended = false;
2880 /* Enable SDIO IRQ */
2881 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2882 sdhci_enable_sdio_irq_nolock(host, true);
2884 /* Enable Card Detection */
2885 sdhci_enable_card_detection(host);
2887 spin_unlock_irqrestore(&host->lock, flags);
2891 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2893 #endif /* CONFIG_PM */
2895 /*****************************************************************************\
2897 * Device allocation/registration *
2899 \*****************************************************************************/
2901 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2904 struct mmc_host *mmc;
2905 struct sdhci_host *host;
2907 WARN_ON(dev == NULL);
2909 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2911 return ERR_PTR(-ENOMEM);
2913 host = mmc_priv(mmc);
2919 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2921 int sdhci_add_host(struct sdhci_host *host)
2923 struct mmc_host *mmc;
2924 u32 caps[2] = {0, 0};
2925 u32 max_current_caps;
2926 unsigned int ocr_avail;
2927 unsigned int override_timeout_clk;
2930 WARN_ON(host == NULL);
2937 host->quirks = debug_quirks;
2939 host->quirks2 = debug_quirks2;
2941 override_timeout_clk = host->timeout_clk;
2943 sdhci_do_reset(host, SDHCI_RESET_ALL);
2945 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2946 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2947 >> SDHCI_SPEC_VER_SHIFT;
2948 if (host->version > SDHCI_SPEC_300) {
2949 pr_err("%s: Unknown controller version (%d). "
2950 "You may experience problems.\n", mmc_hostname(mmc),
2954 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2955 sdhci_readl(host, SDHCI_CAPABILITIES);
2957 if (host->version >= SDHCI_SPEC_300)
2958 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2960 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2962 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2963 host->flags |= SDHCI_USE_SDMA;
2964 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2965 DBG("Controller doesn't have SDMA capability\n");
2967 host->flags |= SDHCI_USE_SDMA;
2969 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2970 (host->flags & SDHCI_USE_SDMA)) {
2971 DBG("Disabling DMA as it is marked broken\n");
2972 host->flags &= ~SDHCI_USE_SDMA;
2975 if ((host->version >= SDHCI_SPEC_200) &&
2976 (caps[0] & SDHCI_CAN_DO_ADMA2))
2977 host->flags |= SDHCI_USE_ADMA;
2979 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2980 (host->flags & SDHCI_USE_ADMA)) {
2981 DBG("Disabling ADMA as it is marked broken\n");
2982 host->flags &= ~SDHCI_USE_ADMA;
2986 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2987 * and *must* do 64-bit DMA. A driver has the opportunity to change
2988 * that during the first call to ->enable_dma(). Similarly
2989 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2992 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2993 host->flags |= SDHCI_USE_64_BIT_DMA;
2995 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2996 if (host->ops->enable_dma) {
2997 if (host->ops->enable_dma(host)) {
2998 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3001 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3006 /* SDMA does not support 64-bit DMA */
3007 if (host->flags & SDHCI_USE_64_BIT_DMA)
3008 host->flags &= ~SDHCI_USE_SDMA;
3010 if (host->flags & SDHCI_USE_ADMA) {
3012 * The DMA descriptor table size is calculated as the maximum
3013 * number of segments times 2, to allow for an alignment
3014 * descriptor for each segment, plus 1 for a nop end descriptor,
3015 * all multipled by the descriptor size.
3017 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3018 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3019 SDHCI_ADMA2_64_DESC_SZ;
3020 host->align_buffer_sz = SDHCI_MAX_SEGS *
3021 SDHCI_ADMA2_64_ALIGN;
3022 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3023 host->align_sz = SDHCI_ADMA2_64_ALIGN;
3024 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3026 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3027 SDHCI_ADMA2_32_DESC_SZ;
3028 host->align_buffer_sz = SDHCI_MAX_SEGS *
3029 SDHCI_ADMA2_32_ALIGN;
3030 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3031 host->align_sz = SDHCI_ADMA2_32_ALIGN;
3032 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3034 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3035 host->adma_table_sz,
3038 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3039 if (!host->adma_table || !host->align_buffer) {
3040 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3041 host->adma_table, host->adma_addr);
3042 kfree(host->align_buffer);
3043 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3045 host->flags &= ~SDHCI_USE_ADMA;
3046 host->adma_table = NULL;
3047 host->align_buffer = NULL;
3048 } else if (host->adma_addr & host->align_mask) {
3049 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3051 host->flags &= ~SDHCI_USE_ADMA;
3052 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3053 host->adma_table, host->adma_addr);
3054 kfree(host->align_buffer);
3055 host->adma_table = NULL;
3056 host->align_buffer = NULL;
3061 * If we use DMA, then it's up to the caller to set the DMA
3062 * mask, but PIO does not need the hw shim so we set a new
3063 * mask here in that case.
3065 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3066 host->dma_mask = DMA_BIT_MASK(64);
3067 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3070 if (host->version >= SDHCI_SPEC_300)
3071 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3072 >> SDHCI_CLOCK_BASE_SHIFT;
3074 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3075 >> SDHCI_CLOCK_BASE_SHIFT;
3077 host->max_clk *= 1000000;
3078 if (host->max_clk == 0 || host->quirks &
3079 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3080 if (!host->ops->get_max_clock) {
3081 pr_err("%s: Hardware doesn't specify base clock "
3082 "frequency.\n", mmc_hostname(mmc));
3085 host->max_clk = host->ops->get_max_clock(host);
3088 host->next_data.cookie = 1;
3090 * In case of Host Controller v3.00, find out whether clock
3091 * multiplier is supported.
3093 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3094 SDHCI_CLOCK_MUL_SHIFT;
3097 * In case the value in Clock Multiplier is 0, then programmable
3098 * clock mode is not supported, otherwise the actual clock
3099 * multiplier is one more than the value of Clock Multiplier
3100 * in the Capabilities Register.
3106 * Set host parameters.
3108 mmc->ops = &sdhci_ops;
3109 mmc->f_max = host->max_clk;
3110 if (host->ops->get_min_clock)
3111 mmc->f_min = host->ops->get_min_clock(host);
3112 else if (host->version >= SDHCI_SPEC_300) {
3113 if (host->clk_mul) {
3114 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3115 mmc->f_max = host->max_clk * host->clk_mul;
3117 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3119 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3121 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3122 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3123 SDHCI_TIMEOUT_CLK_SHIFT;
3124 if (host->timeout_clk == 0) {
3125 if (host->ops->get_timeout_clock) {
3127 host->ops->get_timeout_clock(host);
3129 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3135 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3136 host->timeout_clk *= 1000;
3138 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3139 host->ops->get_max_timeout_count(host) : 1 << 27;
3140 mmc->max_busy_timeout /= host->timeout_clk;
3143 if (override_timeout_clk)
3144 host->timeout_clk = override_timeout_clk;
3146 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3147 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3149 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3150 host->flags |= SDHCI_AUTO_CMD12;
3152 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3153 if ((host->version >= SDHCI_SPEC_300) &&
3154 ((host->flags & SDHCI_USE_ADMA) ||
3155 !(host->flags & SDHCI_USE_SDMA)) &&
3156 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3157 host->flags |= SDHCI_AUTO_CMD23;
3158 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3160 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3164 * A controller may support 8-bit width, but the board itself
3165 * might not have the pins brought out. Boards that support
3166 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3167 * their platform code before calling sdhci_add_host(), and we
3168 * won't assume 8-bit width for hosts without that CAP.
3170 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3171 mmc->caps |= MMC_CAP_4_BIT_DATA;
3173 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3174 mmc->caps &= ~MMC_CAP_CMD23;
3176 if (caps[0] & SDHCI_CAN_DO_HISPD)
3177 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3179 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3180 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3181 mmc->caps |= MMC_CAP_NEEDS_POLL;
3183 /* If there are external regulators, get them */
3184 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3185 return -EPROBE_DEFER;
3187 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3188 if (!IS_ERR(mmc->supply.vqmmc)) {
3189 ret = regulator_enable(mmc->supply.vqmmc);
3190 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3192 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3193 SDHCI_SUPPORT_SDR50 |
3194 SDHCI_SUPPORT_DDR50);
3196 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3197 mmc_hostname(mmc), ret);
3198 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3202 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3203 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3204 SDHCI_SUPPORT_DDR50);
3206 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3207 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3208 SDHCI_SUPPORT_DDR50))
3209 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3211 /* SDR104 supports also implies SDR50 support */
3212 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3213 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3214 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3215 * field can be promoted to support HS200.
3217 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3218 mmc->caps2 |= MMC_CAP2_HS200;
3219 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3220 mmc->caps |= MMC_CAP_UHS_SDR50;
3222 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3223 (caps[1] & SDHCI_SUPPORT_HS400))
3224 mmc->caps2 |= MMC_CAP2_HS400;
3226 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3227 (IS_ERR(mmc->supply.vqmmc) ||
3228 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3230 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3232 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3233 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3234 mmc->caps |= MMC_CAP_UHS_DDR50;
3236 /* Does the host need tuning for SDR50? */
3237 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3238 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3240 /* Does the host need tuning for SDR104 / HS200? */
3241 if (mmc->caps2 & MMC_CAP2_HS200)
3242 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3244 /* Driver Type(s) (A, C, D) supported by the host */
3245 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3246 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3247 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3248 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3249 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3250 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3252 /* Initial value for re-tuning timer count */
3253 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3254 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3257 * In case Re-tuning Timer is not disabled, the actual value of
3258 * re-tuning timer will be 2 ^ (n - 1).
3260 if (host->tuning_count)
3261 host->tuning_count = 1 << (host->tuning_count - 1);
3263 /* Re-tuning mode supported by the Host Controller */
3264 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3265 SDHCI_RETUNING_MODE_SHIFT;
3270 * According to SD Host Controller spec v3.00, if the Host System
3271 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3272 * the value is meaningful only if Voltage Support in the Capabilities
3273 * register is set. The actual current value is 4 times the register
3276 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3277 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3278 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3281 /* convert to SDHCI_MAX_CURRENT format */
3282 curr = curr/1000; /* convert to mA */
3283 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3285 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3287 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3288 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3289 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3293 if (caps[0] & SDHCI_CAN_VDD_330) {
3294 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3296 mmc->max_current_330 = ((max_current_caps &
3297 SDHCI_MAX_CURRENT_330_MASK) >>
3298 SDHCI_MAX_CURRENT_330_SHIFT) *
3299 SDHCI_MAX_CURRENT_MULTIPLIER;
3301 if (caps[0] & SDHCI_CAN_VDD_300) {
3302 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3304 mmc->max_current_300 = ((max_current_caps &
3305 SDHCI_MAX_CURRENT_300_MASK) >>
3306 SDHCI_MAX_CURRENT_300_SHIFT) *
3307 SDHCI_MAX_CURRENT_MULTIPLIER;
3309 if (caps[0] & SDHCI_CAN_VDD_180) {
3310 ocr_avail |= MMC_VDD_165_195;
3312 mmc->max_current_180 = ((max_current_caps &
3313 SDHCI_MAX_CURRENT_180_MASK) >>
3314 SDHCI_MAX_CURRENT_180_SHIFT) *
3315 SDHCI_MAX_CURRENT_MULTIPLIER;
3318 /* If OCR set by external regulators, use it instead */
3320 ocr_avail = mmc->ocr_avail;
3323 ocr_avail &= host->ocr_mask;
3325 mmc->ocr_avail = ocr_avail;
3326 mmc->ocr_avail_sdio = ocr_avail;
3327 if (host->ocr_avail_sdio)
3328 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3329 mmc->ocr_avail_sd = ocr_avail;
3330 if (host->ocr_avail_sd)
3331 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3332 else /* normal SD controllers don't support 1.8V */
3333 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3334 mmc->ocr_avail_mmc = ocr_avail;
3335 if (host->ocr_avail_mmc)
3336 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3338 if (mmc->ocr_avail == 0) {
3339 pr_err("%s: Hardware doesn't report any "
3340 "support voltages.\n", mmc_hostname(mmc));
3344 spin_lock_init(&host->lock);
3347 * Maximum number of segments. Depends on if the hardware
3348 * can do scatter/gather or not.
3350 if (host->flags & SDHCI_USE_ADMA)
3351 mmc->max_segs = SDHCI_MAX_SEGS;
3352 else if (host->flags & SDHCI_USE_SDMA)
3355 mmc->max_segs = SDHCI_MAX_SEGS;
3358 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3359 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3362 mmc->max_req_size = 524288;
3365 * Maximum segment size. Could be one segment with the maximum number
3366 * of bytes. When doing hardware scatter/gather, each entry cannot
3367 * be larger than 64 KiB though.
3369 if (host->flags & SDHCI_USE_ADMA) {
3370 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3371 mmc->max_seg_size = 65535;
3373 mmc->max_seg_size = 65536;
3375 mmc->max_seg_size = mmc->max_req_size;
3379 * Maximum block size. This varies from controller to controller and
3380 * is specified in the capabilities register.
3382 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3383 mmc->max_blk_size = 2;
3385 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3386 SDHCI_MAX_BLOCK_SHIFT;
3387 if (mmc->max_blk_size >= 3) {
3388 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3390 mmc->max_blk_size = 0;
3394 mmc->max_blk_size = 512 << mmc->max_blk_size;
3397 * Maximum block count.
3399 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3404 tasklet_init(&host->finish_tasklet,
3405 sdhci_tasklet_finish, (unsigned long)host);
3407 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3409 init_waitqueue_head(&host->buf_ready_int);
3411 if (host->version >= SDHCI_SPEC_300) {
3412 /* Initialize re-tuning timer */
3413 init_timer(&host->tuning_timer);
3414 host->tuning_timer.data = (unsigned long)host;
3415 host->tuning_timer.function = sdhci_tuning_timer;
3418 sdhci_init(host, 0);
3420 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3421 IRQF_SHARED, mmc_hostname(mmc), host);
3423 pr_err("%s: Failed to request IRQ %d: %d\n",
3424 mmc_hostname(mmc), host->irq, ret);
3428 #ifdef CONFIG_MMC_DEBUG
3429 sdhci_dumpregs(host);
3432 #ifdef SDHCI_USE_LEDS_CLASS
3433 snprintf(host->led_name, sizeof(host->led_name),
3434 "%s::", mmc_hostname(mmc));
3435 host->led.name = host->led_name;
3436 host->led.brightness = LED_OFF;
3437 host->led.default_trigger = mmc_hostname(mmc);
3438 host->led.brightness_set = sdhci_led_control;
3440 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3442 pr_err("%s: Failed to register LED device: %d\n",
3443 mmc_hostname(mmc), ret);
3452 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3453 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3454 (host->flags & SDHCI_USE_ADMA) ?
3455 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3456 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3458 sdhci_enable_card_detection(host);
3462 #ifdef SDHCI_USE_LEDS_CLASS
3464 sdhci_do_reset(host, SDHCI_RESET_ALL);
3465 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3466 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3467 free_irq(host->irq, host);
3470 tasklet_kill(&host->finish_tasklet);
3475 EXPORT_SYMBOL_GPL(sdhci_add_host);
3477 void sdhci_remove_host(struct sdhci_host *host, int dead)
3479 struct mmc_host *mmc = host->mmc;
3480 unsigned long flags;
3483 spin_lock_irqsave(&host->lock, flags);
3485 host->flags |= SDHCI_DEVICE_DEAD;
3488 pr_err("%s: Controller removed during "
3489 " transfer!\n", mmc_hostname(mmc));
3491 host->mrq->cmd->error = -ENOMEDIUM;
3492 tasklet_schedule(&host->finish_tasklet);
3495 spin_unlock_irqrestore(&host->lock, flags);
3498 sdhci_disable_card_detection(host);
3500 mmc_remove_host(mmc);
3502 #ifdef SDHCI_USE_LEDS_CLASS
3503 led_classdev_unregister(&host->led);
3507 sdhci_do_reset(host, SDHCI_RESET_ALL);
3509 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3510 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3511 free_irq(host->irq, host);
3513 del_timer_sync(&host->timer);
3515 tasklet_kill(&host->finish_tasklet);
3517 if (!IS_ERR(mmc->supply.vqmmc))
3518 regulator_disable(mmc->supply.vqmmc);
3520 if (host->adma_table)
3521 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3522 host->adma_table, host->adma_addr);
3523 kfree(host->align_buffer);
3525 host->adma_table = NULL;
3526 host->align_buffer = NULL;
3529 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3531 void sdhci_free_host(struct sdhci_host *host)
3533 mmc_free_host(host->mmc);
3536 EXPORT_SYMBOL_GPL(sdhci_free_host);
3538 /*****************************************************************************\
3540 * Driver init/exit *
3542 \*****************************************************************************/
3544 static int __init sdhci_drv_init(void)
3547 ": Secure Digital Host Controller Interface driver\n");
3548 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3553 static void __exit sdhci_drv_exit(void)
3557 module_init(sdhci_drv_init);
3558 module_exit(sdhci_drv_exit);
3560 module_param(debug_quirks, uint, 0444);
3561 module_param(debug_quirks2, uint, 0444);
3563 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3564 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3565 MODULE_LICENSE("GPL");
3567 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3568 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");