2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 #define ADMA_SIZE ((128 * 2 + 1) * 4)
49 static unsigned int debug_quirks = 0;
50 static unsigned int debug_quirks2;
52 static void sdhci_finish_data(struct sdhci_host *);
54 static void sdhci_finish_command(struct sdhci_host *);
55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
56 static void sdhci_tuning_timer(unsigned long data);
57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
59 #ifdef CONFIG_PM_RUNTIME
60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
81 static void sdhci_dumpregs(struct sdhci_host *host)
83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
84 mmc_hostname(host->mmc));
86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
114 sdhci_readl(host, SDHCI_CAPABILITIES),
115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
117 sdhci_readw(host, SDHCI_COMMAND),
118 sdhci_readl(host, SDHCI_MAX_CURRENT));
119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122 if (host->flags & SDHCI_USE_ADMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 pr_debug(DRIVER_NAME ": ===========================================\n");
130 /*****************************************************************************\
132 * Low level functions *
134 \*****************************************************************************/
136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
158 static void sdhci_enable_card_detection(struct sdhci_host *host)
160 sdhci_set_card_detection(host, true);
163 static void sdhci_disable_card_detection(struct sdhci_host *host)
165 sdhci_set_card_detection(host, false);
168 void sdhci_reset(struct sdhci_host *host, u8 mask)
170 unsigned long timeout;
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
174 if (mask & SDHCI_RESET_ALL) {
176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
181 /* Wait max 100 ms */
184 /* hw clears the bit when it's done */
185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
187 pr_err("%s: Reset 0x%x never completed.\n",
188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
196 EXPORT_SYMBOL_GPL(sdhci_reset);
198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
206 host->ops->reset(host, mask);
208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
221 static void sdhci_init(struct sdhci_host *host, int soft)
224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
226 sdhci_do_reset(host, SDHCI_RESET_ALL);
228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
238 /* force clock reconfiguration */
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 static void sdhci_reinit(struct sdhci_host *host)
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
260 sdhci_enable_card_detection(host);
263 static void sdhci_activate_led(struct sdhci_host *host)
267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268 ctrl |= SDHCI_CTRL_LED;
269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
272 static void sdhci_deactivate_led(struct sdhci_host *host)
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl &= ~SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
281 #ifdef SDHCI_USE_LEDS_CLASS
282 static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
288 spin_lock_irqsave(&host->lock, flags);
290 if (host->runtime_suspended)
293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
296 sdhci_activate_led(host);
298 spin_unlock_irqrestore(&host->lock, flags);
302 /*****************************************************************************\
306 \*****************************************************************************/
308 static void sdhci_read_block_pio(struct sdhci_host *host)
311 size_t blksize, len, chunk;
312 u32 uninitialized_var(scratch);
315 DBG("PIO reading\n");
317 blksize = host->data->blksz;
320 local_irq_save(flags);
323 if (!sg_miter_next(&host->sg_miter))
326 len = min(host->sg_miter.length, blksize);
329 host->sg_miter.consumed = len;
331 buf = host->sg_miter.addr;
335 scratch = sdhci_readl(host, SDHCI_BUFFER);
339 *buf = scratch & 0xFF;
348 sg_miter_stop(&host->sg_miter);
350 local_irq_restore(flags);
353 static void sdhci_write_block_pio(struct sdhci_host *host)
356 size_t blksize, len, chunk;
360 DBG("PIO writing\n");
362 blksize = host->data->blksz;
366 local_irq_save(flags);
369 if (!sg_miter_next(&host->sg_miter))
372 len = min(host->sg_miter.length, blksize);
375 host->sg_miter.consumed = len;
377 buf = host->sg_miter.addr;
380 scratch |= (u32)*buf << (chunk * 8);
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
387 sdhci_writel(host, scratch, SDHCI_BUFFER);
394 sg_miter_stop(&host->sg_miter);
396 local_irq_restore(flags);
399 static void sdhci_transfer_pio(struct sdhci_host *host)
405 if (host->blocks == 0)
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
411 mask = SDHCI_SPACE_AVAILABLE;
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
429 sdhci_write_block_pio(host);
432 if (host->blocks == 0)
436 DBG("PIO transfer complete.\n");
439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
441 local_irq_save(*flags);
442 return kmap_atomic(sg_page(sg)) + sg->offset;
445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
447 kunmap_atomic(buffer);
448 local_irq_restore(*flags);
451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
462 dataddr[0] = cpu_to_le32(addr);
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
473 dma_addr_t align_addr;
476 struct scatterlist *sg;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
489 direction = DMA_TO_DEVICE;
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
495 BUG_ON(host->align_addr & 0x3);
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
499 if (host->sg_count == 0)
502 desc = host->adma_desc;
503 align = host->align_buffer;
505 align_addr = host->align_addr;
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
518 offset = (4 - (addr & 0x3)) & 0x3;
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
530 BUG_ON(offset > 65536);
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
548 * If this triggers then we have a calculation bug
551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
556 * Mark the last descriptor as the terminating descriptor
558 if (desc != host->adma_desc) {
560 desc[0] |= 0x2; /* end */
564 * Add a terminating entry.
567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
572 * Resync align buffer as we might have changed it.
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
588 static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
593 struct scatterlist *sg;
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
603 direction = DMA_TO_DEVICE;
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
620 align = host->align_buffer;
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
626 buffer = sdhci_kmap_atomic(sg, &flags);
627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
643 struct mmc_data *data = cmd->data;
644 unsigned target_timeout, current_timeout;
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
655 /* Unspecified timeout, assume max */
656 if (!data && !cmd->busy_timeout)
661 target_timeout = cmd->busy_timeout * 1000;
663 target_timeout = data->timeout_ns / 1000;
665 target_timeout += data->timeout_clks / host->clock;
669 * Figure out needed cycles.
670 * We do this in steps in order to fit inside a 32 bit int.
671 * The first step is the minimum timeout, which will have a
672 * minimum resolution of 6 bits:
673 * (1) 2^13*1000 > 2^22,
674 * (2) host->timeout_clk < 2^16
679 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680 while (current_timeout < target_timeout) {
682 current_timeout <<= 1;
688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689 mmc_hostname(host->mmc), count, cmd->opcode);
696 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
701 if (host->flags & SDHCI_REQ_USE_DMA)
702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
710 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
714 if (host->ops->set_timeout) {
715 host->ops->set_timeout(host, cmd);
717 count = sdhci_calc_timeout(host, cmd);
718 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
725 struct mmc_data *data = cmd->data;
730 if (data || (cmd->flags & MMC_RSP_BUSY))
731 sdhci_set_timeout(host, cmd);
737 BUG_ON(data->blksz * data->blocks > 524288);
738 BUG_ON(data->blksz > host->mmc->max_blk_size);
739 BUG_ON(data->blocks > 65535);
742 host->data_early = 0;
743 host->data->bytes_xfered = 0;
745 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
746 host->flags |= SDHCI_REQ_USE_DMA;
749 * FIXME: This doesn't account for merging when mapping the
752 if (host->flags & SDHCI_REQ_USE_DMA) {
754 struct scatterlist *sg;
757 if (host->flags & SDHCI_USE_ADMA) {
758 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
761 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
765 if (unlikely(broken)) {
766 for_each_sg(data->sg, sg, data->sg_len, i) {
767 if (sg->length & 0x3) {
768 DBG("Reverting to PIO because of "
769 "transfer size (%d)\n",
771 host->flags &= ~SDHCI_REQ_USE_DMA;
779 * The assumption here being that alignment is the same after
780 * translation to device address space.
782 if (host->flags & SDHCI_REQ_USE_DMA) {
784 struct scatterlist *sg;
787 if (host->flags & SDHCI_USE_ADMA) {
789 * As we use 3 byte chunks to work around
790 * alignment problems, we need to check this
793 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
800 if (unlikely(broken)) {
801 for_each_sg(data->sg, sg, data->sg_len, i) {
802 if (sg->offset & 0x3) {
803 DBG("Reverting to PIO because of "
805 host->flags &= ~SDHCI_REQ_USE_DMA;
812 if (host->flags & SDHCI_REQ_USE_DMA) {
813 if (host->flags & SDHCI_USE_ADMA) {
814 ret = sdhci_adma_table_pre(host, data);
817 * This only happens when someone fed
818 * us an invalid request.
821 host->flags &= ~SDHCI_REQ_USE_DMA;
823 sdhci_writel(host, host->adma_addr,
829 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
830 data->sg, data->sg_len,
831 (data->flags & MMC_DATA_READ) ?
836 * This only happens when someone fed
837 * us an invalid request.
840 host->flags &= ~SDHCI_REQ_USE_DMA;
842 WARN_ON(sg_cnt != 1);
843 sdhci_writel(host, sg_dma_address(data->sg),
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
854 if (host->version >= SDHCI_SPEC_200) {
855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
858 (host->flags & SDHCI_USE_ADMA))
859 ctrl |= SDHCI_CTRL_ADMA32;
861 ctrl |= SDHCI_CTRL_SDMA;
862 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
865 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
868 flags = SG_MITER_ATOMIC;
869 if (host->data->flags & MMC_DATA_READ)
870 flags |= SG_MITER_TO_SG;
872 flags |= SG_MITER_FROM_SG;
873 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
874 host->blocks = data->blocks;
877 sdhci_set_transfer_irqs(host);
879 /* Set the DMA boundary value and block size */
880 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
881 data->blksz), SDHCI_BLOCK_SIZE);
882 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
885 static void sdhci_set_transfer_mode(struct sdhci_host *host,
886 struct mmc_command *cmd)
889 struct mmc_data *data = cmd->data;
892 /* clear Auto CMD settings for no data CMDs */
893 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
894 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
895 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
899 WARN_ON(!host->data);
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
903 mode |= SDHCI_TRNS_MULTI;
905 * If we are sending CMD23, CMD12 never gets sent
906 * on successful completion (so no Auto-CMD12).
908 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
909 mode |= SDHCI_TRNS_AUTO_CMD12;
910 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
911 mode |= SDHCI_TRNS_AUTO_CMD23;
912 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
916 if (data->flags & MMC_DATA_READ)
917 mode |= SDHCI_TRNS_READ;
918 if (host->flags & SDHCI_REQ_USE_DMA)
919 mode |= SDHCI_TRNS_DMA;
921 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
924 static void sdhci_finish_data(struct sdhci_host *host)
926 struct mmc_data *data;
933 if (host->flags & SDHCI_REQ_USE_DMA) {
934 if (host->flags & SDHCI_USE_ADMA)
935 sdhci_adma_table_post(host, data);
937 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
938 data->sg_len, (data->flags & MMC_DATA_READ) ?
939 DMA_FROM_DEVICE : DMA_TO_DEVICE);
944 * The specification states that the block count register must
945 * be updated, but it does not specify at what point in the
946 * data flow. That makes the register entirely useless to read
947 * back so we have to assume that nothing made it to the card
948 * in the event of an error.
951 data->bytes_xfered = 0;
953 data->bytes_xfered = data->blksz * data->blocks;
956 * Need to send CMD12 if -
957 * a) open-ended multiblock transfer (no CMD23)
958 * b) error in multiblock transfer
965 * The controller needs a reset of internal state machines
966 * upon error conditions.
969 sdhci_do_reset(host, SDHCI_RESET_CMD);
970 sdhci_do_reset(host, SDHCI_RESET_DATA);
973 sdhci_send_command(host, data->stop);
975 tasklet_schedule(&host->finish_tasklet);
978 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
982 unsigned long timeout;
989 mask = SDHCI_CMD_INHIBIT;
990 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
991 mask |= SDHCI_DATA_INHIBIT;
993 /* We shouldn't wait for data inihibit for stop commands, even
994 though they might use busy signaling */
995 if (host->mrq->data && (cmd == host->mrq->data->stop))
996 mask &= ~SDHCI_DATA_INHIBIT;
998 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1000 pr_err("%s: Controller never released "
1001 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1002 sdhci_dumpregs(host);
1004 tasklet_schedule(&host->finish_tasklet);
1012 if (!cmd->data && cmd->busy_timeout > 9000)
1013 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1016 mod_timer(&host->timer, timeout);
1020 sdhci_prepare_data(host, cmd);
1022 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024 sdhci_set_transfer_mode(host, cmd);
1026 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1027 pr_err("%s: Unsupported response type!\n",
1028 mmc_hostname(host->mmc));
1029 cmd->error = -EINVAL;
1030 tasklet_schedule(&host->finish_tasklet);
1034 if (!(cmd->flags & MMC_RSP_PRESENT))
1035 flags = SDHCI_CMD_RESP_NONE;
1036 else if (cmd->flags & MMC_RSP_136)
1037 flags = SDHCI_CMD_RESP_LONG;
1038 else if (cmd->flags & MMC_RSP_BUSY)
1039 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 flags = SDHCI_CMD_RESP_SHORT;
1043 if (cmd->flags & MMC_RSP_CRC)
1044 flags |= SDHCI_CMD_CRC;
1045 if (cmd->flags & MMC_RSP_OPCODE)
1046 flags |= SDHCI_CMD_INDEX;
1048 /* CMD19 is special in that the Data Present Select should be set */
1049 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1050 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1051 flags |= SDHCI_CMD_DATA;
1053 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1055 EXPORT_SYMBOL_GPL(sdhci_send_command);
1057 static void sdhci_finish_command(struct sdhci_host *host)
1061 BUG_ON(host->cmd == NULL);
1063 if (host->cmd->flags & MMC_RSP_PRESENT) {
1064 if (host->cmd->flags & MMC_RSP_136) {
1065 /* CRC is stripped so we need to do some shifting. */
1066 for (i = 0;i < 4;i++) {
1067 host->cmd->resp[i] = sdhci_readl(host,
1068 SDHCI_RESPONSE + (3-i)*4) << 8;
1070 host->cmd->resp[i] |=
1072 SDHCI_RESPONSE + (3-i)*4-1);
1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1079 host->cmd->error = 0;
1081 /* Finished CMD23, now send actual command. */
1082 if (host->cmd == host->mrq->sbc) {
1084 sdhci_send_command(host, host->mrq->cmd);
1087 /* Processed actual command. */
1088 if (host->data && host->data_early)
1089 sdhci_finish_data(host);
1091 if (!host->cmd->data)
1092 tasklet_schedule(&host->finish_tasklet);
1098 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1102 switch (host->timing) {
1103 case MMC_TIMING_UHS_SDR12:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 case MMC_TIMING_UHS_SDR25:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1109 case MMC_TIMING_UHS_SDR50:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1112 case MMC_TIMING_UHS_SDR104:
1113 case MMC_TIMING_MMC_HS200:
1114 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 case MMC_TIMING_UHS_DDR50:
1117 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1120 pr_warn("%s: Invalid UHS-I mode selected\n",
1121 mmc_hostname(host->mmc));
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1128 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130 int div = 0; /* Initialized for compiler warning */
1131 int real_div = div, clk_mul = 1;
1133 unsigned long timeout;
1135 host->mmc->actual_clock = 0;
1137 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1142 if (host->version >= SDHCI_SPEC_300) {
1143 if (host->preset_enabled) {
1146 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1147 pre_val = sdhci_get_preset_value(host);
1148 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1149 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1150 if (host->clk_mul &&
1151 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1152 clk = SDHCI_PROG_CLOCK_MODE;
1154 clk_mul = host->clk_mul;
1156 real_div = max_t(int, 1, div << 1);
1162 * Check if the Host Controller supports Programmable Clock
1165 if (host->clk_mul) {
1166 for (div = 1; div <= 1024; div++) {
1167 if ((host->max_clk * host->clk_mul / div)
1172 * Set Programmable Clock Mode in the Clock
1175 clk = SDHCI_PROG_CLOCK_MODE;
1177 clk_mul = host->clk_mul;
1180 /* Version 3.00 divisors must be a multiple of 2. */
1181 if (host->max_clk <= clock)
1184 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1186 if ((host->max_clk / div) <= clock)
1194 /* Version 2.00 divisors must be a power of 2. */
1195 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1196 if ((host->max_clk / div) <= clock)
1205 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1206 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
1207 host->timeout_clk = host->mmc->actual_clock / 1000;
1208 host->mmc->max_busy_timeout =
1209 host->ops->get_max_timeout_count ?
1210 host->ops->get_max_timeout_count(host) :
1212 host->mmc->max_busy_timeout /= host->timeout_clk;
1216 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1217 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1218 << SDHCI_DIVIDER_HI_SHIFT;
1219 clk |= SDHCI_CLOCK_INT_EN;
1220 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1222 /* Wait max 20 ms */
1224 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1225 & SDHCI_CLOCK_INT_STABLE)) {
1227 pr_err("%s: Internal clock never "
1228 "stabilised.\n", mmc_hostname(host->mmc));
1229 sdhci_dumpregs(host);
1236 clk |= SDHCI_CLOCK_CARD_EN;
1237 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1239 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1241 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1244 struct mmc_host *mmc = host->mmc;
1247 if (!IS_ERR(mmc->supply.vmmc)) {
1248 spin_unlock_irq(&host->lock);
1249 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1250 spin_lock_irq(&host->lock);
1254 if (mode != MMC_POWER_OFF) {
1256 case MMC_VDD_165_195:
1257 pwr = SDHCI_POWER_180;
1261 pwr = SDHCI_POWER_300;
1265 pwr = SDHCI_POWER_330;
1272 if (host->pwr == pwr)
1278 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1279 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1280 sdhci_runtime_pm_bus_off(host);
1284 * Spec says that we should clear the power reg before setting
1285 * a new value. Some controllers don't seem to like this though.
1287 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1288 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1291 * At least the Marvell CaFe chip gets confused if we set the
1292 * voltage and set turn on power at the same time, so set the
1295 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1296 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1298 pwr |= SDHCI_POWER_ON;
1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1302 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1303 sdhci_runtime_pm_bus_on(host);
1306 * Some controllers need an extra 10ms delay of 10ms before
1307 * they can apply clock after applying power
1309 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1314 /*****************************************************************************\
1318 \*****************************************************************************/
1320 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1322 struct sdhci_host *host;
1324 unsigned long flags;
1327 host = mmc_priv(mmc);
1329 sdhci_runtime_pm_get(host);
1331 spin_lock_irqsave(&host->lock, flags);
1333 WARN_ON(host->mrq != NULL);
1335 #ifndef SDHCI_USE_LEDS_CLASS
1336 sdhci_activate_led(host);
1340 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1341 * requests if Auto-CMD12 is enabled.
1343 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1345 mrq->data->stop = NULL;
1353 * Firstly check card presence from cd-gpio. The return could
1354 * be one of the following possibilities:
1355 * negative: cd-gpio is not available
1356 * zero: cd-gpio is used, and card is removed
1357 * one: cd-gpio is used, and card is present
1359 present = mmc_gpio_get_cd(host->mmc);
1361 /* If polling, assume that the card is always present. */
1362 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1365 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1369 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1370 host->mrq->cmd->error = -ENOMEDIUM;
1371 tasklet_schedule(&host->finish_tasklet);
1375 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1377 * Check if the re-tuning timer has already expired and there
1378 * is no on-going data transfer. If so, we need to execute
1379 * tuning procedure before sending command.
1381 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1382 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1384 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1386 mmc->card->type == MMC_TYPE_MMC ?
1387 MMC_SEND_TUNING_BLOCK_HS200 :
1388 MMC_SEND_TUNING_BLOCK;
1390 /* Here we need to set the host->mrq to NULL,
1391 * in case the pending finish_tasklet
1392 * finishes it incorrectly.
1396 spin_unlock_irqrestore(&host->lock, flags);
1397 sdhci_execute_tuning(mmc, tuning_opcode);
1398 spin_lock_irqsave(&host->lock, flags);
1400 /* Restore original mmc_request structure */
1405 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1406 sdhci_send_command(host, mrq->sbc);
1408 sdhci_send_command(host, mrq->cmd);
1412 spin_unlock_irqrestore(&host->lock, flags);
1415 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1419 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1420 if (width == MMC_BUS_WIDTH_8) {
1421 ctrl &= ~SDHCI_CTRL_4BITBUS;
1422 if (host->version >= SDHCI_SPEC_300)
1423 ctrl |= SDHCI_CTRL_8BITBUS;
1425 if (host->version >= SDHCI_SPEC_300)
1426 ctrl &= ~SDHCI_CTRL_8BITBUS;
1427 if (width == MMC_BUS_WIDTH_4)
1428 ctrl |= SDHCI_CTRL_4BITBUS;
1430 ctrl &= ~SDHCI_CTRL_4BITBUS;
1432 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1434 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1436 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1440 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1441 /* Select Bus Speed Mode for host */
1442 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1443 if ((timing == MMC_TIMING_MMC_HS200) ||
1444 (timing == MMC_TIMING_UHS_SDR104))
1445 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1446 else if (timing == MMC_TIMING_UHS_SDR12)
1447 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1448 else if (timing == MMC_TIMING_UHS_SDR25)
1449 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1450 else if (timing == MMC_TIMING_UHS_SDR50)
1451 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1452 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1453 (timing == MMC_TIMING_MMC_DDR52))
1454 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1455 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1457 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1459 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1461 unsigned long flags;
1463 struct mmc_host *mmc = host->mmc;
1465 spin_lock_irqsave(&host->lock, flags);
1467 if (host->flags & SDHCI_DEVICE_DEAD) {
1468 spin_unlock_irqrestore(&host->lock, flags);
1469 if (!IS_ERR(mmc->supply.vmmc) &&
1470 ios->power_mode == MMC_POWER_OFF)
1471 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1476 * Reset the chip on each power off.
1477 * Should clear out any weird states.
1479 if (ios->power_mode == MMC_POWER_OFF) {
1480 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1484 if (host->version >= SDHCI_SPEC_300 &&
1485 (ios->power_mode == MMC_POWER_UP) &&
1486 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1487 sdhci_enable_preset_value(host, false);
1489 if (!ios->clock || ios->clock != host->clock) {
1490 host->ops->set_clock(host, ios->clock);
1491 host->clock = ios->clock;
1494 sdhci_set_power(host, ios->power_mode, ios->vdd);
1496 if (host->ops->platform_send_init_74_clocks)
1497 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1499 host->ops->set_bus_width(host, ios->bus_width);
1501 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1503 if ((ios->timing == MMC_TIMING_SD_HS ||
1504 ios->timing == MMC_TIMING_MMC_HS)
1505 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1506 ctrl |= SDHCI_CTRL_HISPD;
1508 ctrl &= ~SDHCI_CTRL_HISPD;
1510 if (host->version >= SDHCI_SPEC_300) {
1513 /* In case of UHS-I modes, set High Speed Enable */
1514 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1515 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1516 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1517 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1518 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1519 (ios->timing == MMC_TIMING_UHS_SDR25))
1520 ctrl |= SDHCI_CTRL_HISPD;
1522 if (!host->preset_enabled) {
1523 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1525 * We only need to set Driver Strength if the
1526 * preset value enable is not set.
1528 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1529 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1530 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1531 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1532 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1533 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1535 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1538 * According to SDHC Spec v3.00, if the Preset Value
1539 * Enable in the Host Control 2 register is set, we
1540 * need to reset SD Clock Enable before changing High
1541 * Speed Enable to avoid generating clock gliches.
1544 /* Reset SD Clock Enable */
1545 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1546 clk &= ~SDHCI_CLOCK_CARD_EN;
1547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1549 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1551 /* Re-enable SD Clock */
1552 host->ops->set_clock(host, host->clock);
1555 /* Reset SD Clock Enable */
1556 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1557 clk &= ~SDHCI_CLOCK_CARD_EN;
1558 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1560 host->ops->set_uhs_signaling(host, ios->timing);
1561 host->timing = ios->timing;
1563 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1564 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1565 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1566 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1567 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1568 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1571 sdhci_enable_preset_value(host, true);
1572 preset = sdhci_get_preset_value(host);
1573 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1574 >> SDHCI_PRESET_DRV_SHIFT;
1577 /* Re-enable SD Clock */
1578 host->ops->set_clock(host, host->clock);
1580 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1583 * Some (ENE) controllers go apeshit on some ios operation,
1584 * signalling timeout and CRC errors even on CMD0. Resetting
1585 * it on each ios seems to solve the problem.
1587 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1588 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1591 spin_unlock_irqrestore(&host->lock, flags);
1594 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1596 struct sdhci_host *host = mmc_priv(mmc);
1598 sdhci_runtime_pm_get(host);
1599 sdhci_do_set_ios(host, ios);
1600 sdhci_runtime_pm_put(host);
1603 static int sdhci_do_get_cd(struct sdhci_host *host)
1605 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1607 if (host->flags & SDHCI_DEVICE_DEAD)
1610 /* If polling/nonremovable, assume that the card is always present. */
1611 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1612 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1615 /* Try slot gpio detect */
1616 if (!IS_ERR_VALUE(gpio_cd))
1619 /* Host native card detect */
1620 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1623 static int sdhci_get_cd(struct mmc_host *mmc)
1625 struct sdhci_host *host = mmc_priv(mmc);
1628 sdhci_runtime_pm_get(host);
1629 ret = sdhci_do_get_cd(host);
1630 sdhci_runtime_pm_put(host);
1634 static int sdhci_check_ro(struct sdhci_host *host)
1636 unsigned long flags;
1639 spin_lock_irqsave(&host->lock, flags);
1641 if (host->flags & SDHCI_DEVICE_DEAD)
1643 else if (host->ops->get_ro)
1644 is_readonly = host->ops->get_ro(host);
1646 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1647 & SDHCI_WRITE_PROTECT);
1649 spin_unlock_irqrestore(&host->lock, flags);
1651 /* This quirk needs to be replaced by a callback-function later */
1652 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1653 !is_readonly : is_readonly;
1656 #define SAMPLE_COUNT 5
1658 static int sdhci_do_get_ro(struct sdhci_host *host)
1662 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1663 return sdhci_check_ro(host);
1666 for (i = 0; i < SAMPLE_COUNT; i++) {
1667 if (sdhci_check_ro(host)) {
1668 if (++ro_count > SAMPLE_COUNT / 2)
1676 static void sdhci_hw_reset(struct mmc_host *mmc)
1678 struct sdhci_host *host = mmc_priv(mmc);
1680 if (host->ops && host->ops->hw_reset)
1681 host->ops->hw_reset(host);
1684 static int sdhci_get_ro(struct mmc_host *mmc)
1686 struct sdhci_host *host = mmc_priv(mmc);
1689 sdhci_runtime_pm_get(host);
1690 ret = sdhci_do_get_ro(host);
1691 sdhci_runtime_pm_put(host);
1695 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1697 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1699 host->ier |= SDHCI_INT_CARD_INT;
1701 host->ier &= ~SDHCI_INT_CARD_INT;
1703 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1704 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1709 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1711 struct sdhci_host *host = mmc_priv(mmc);
1712 unsigned long flags;
1714 sdhci_runtime_pm_get(host);
1716 spin_lock_irqsave(&host->lock, flags);
1718 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1720 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1722 sdhci_enable_sdio_irq_nolock(host, enable);
1723 spin_unlock_irqrestore(&host->lock, flags);
1725 sdhci_runtime_pm_put(host);
1728 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1729 struct mmc_ios *ios)
1731 struct mmc_host *mmc = host->mmc;
1736 * Signal Voltage Switching is only applicable for Host Controllers
1739 if (host->version < SDHCI_SPEC_300)
1742 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1744 switch (ios->signal_voltage) {
1745 case MMC_SIGNAL_VOLTAGE_330:
1746 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1747 ctrl &= ~SDHCI_CTRL_VDD_180;
1748 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1750 if (!IS_ERR(mmc->supply.vqmmc)) {
1751 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1754 pr_warning("%s: Switching to 3.3V signalling voltage "
1755 " failed\n", mmc_hostname(mmc));
1760 usleep_range(5000, 5500);
1762 /* 3.3V regulator output should be stable within 5 ms */
1763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1764 if (!(ctrl & SDHCI_CTRL_VDD_180))
1767 pr_warning("%s: 3.3V regulator output did not became stable\n",
1771 case MMC_SIGNAL_VOLTAGE_180:
1772 if (!IS_ERR(mmc->supply.vqmmc)) {
1773 ret = regulator_set_voltage(mmc->supply.vqmmc,
1776 pr_warning("%s: Switching to 1.8V signalling voltage "
1777 " failed\n", mmc_hostname(mmc));
1783 * Enable 1.8V Signal Enable in the Host Control2
1786 ctrl |= SDHCI_CTRL_VDD_180;
1787 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1789 /* 1.8V regulator output should be stable within 5 ms */
1790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1791 if (ctrl & SDHCI_CTRL_VDD_180)
1794 pr_warning("%s: 1.8V regulator output did not became stable\n",
1798 case MMC_SIGNAL_VOLTAGE_120:
1799 if (!IS_ERR(mmc->supply.vqmmc)) {
1800 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1803 pr_warning("%s: Switching to 1.2V signalling voltage "
1804 " failed\n", mmc_hostname(mmc));
1810 /* No signal voltage switch required */
1815 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1816 struct mmc_ios *ios)
1818 struct sdhci_host *host = mmc_priv(mmc);
1821 if (host->version < SDHCI_SPEC_300)
1823 sdhci_runtime_pm_get(host);
1824 err = sdhci_do_start_signal_voltage_switch(host, ios);
1825 sdhci_runtime_pm_put(host);
1829 static int sdhci_card_busy(struct mmc_host *mmc)
1831 struct sdhci_host *host = mmc_priv(mmc);
1834 sdhci_runtime_pm_get(host);
1835 /* Check whether DAT[3:0] is 0000 */
1836 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1837 sdhci_runtime_pm_put(host);
1839 return !(present_state & SDHCI_DATA_LVL_MASK);
1842 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1844 struct sdhci_host *host = mmc_priv(mmc);
1846 int tuning_loop_counter = MAX_TUNING_LOOP;
1848 unsigned long flags;
1850 sdhci_runtime_pm_get(host);
1851 spin_lock_irqsave(&host->lock, flags);
1854 * The Host Controller needs tuning only in case of SDR104 mode
1855 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1856 * Capabilities register.
1857 * If the Host Controller supports the HS200 mode then the
1858 * tuning function has to be executed.
1860 switch (host->timing) {
1861 case MMC_TIMING_MMC_HS200:
1862 case MMC_TIMING_UHS_SDR104:
1865 case MMC_TIMING_UHS_SDR50:
1866 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1867 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1872 spin_unlock_irqrestore(&host->lock, flags);
1873 sdhci_runtime_pm_put(host);
1877 if (host->ops->platform_execute_tuning) {
1878 spin_unlock_irqrestore(&host->lock, flags);
1879 err = host->ops->platform_execute_tuning(host, opcode);
1880 sdhci_runtime_pm_put(host);
1884 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1885 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1886 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1889 * As per the Host Controller spec v3.00, tuning command
1890 * generates Buffer Read Ready interrupt, so enable that.
1892 * Note: The spec clearly says that when tuning sequence
1893 * is being performed, the controller does not generate
1894 * interrupts other than Buffer Read Ready interrupt. But
1895 * to make sure we don't hit a controller bug, we _only_
1896 * enable Buffer Read Ready interrupt here.
1898 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1899 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1902 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1903 * of loops reaches 40 times or a timeout of 150ms occurs.
1906 struct mmc_command cmd = {0};
1907 struct mmc_request mrq = {NULL};
1909 cmd.opcode = opcode;
1911 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1916 if (tuning_loop_counter-- == 0)
1923 * In response to CMD19, the card sends 64 bytes of tuning
1924 * block to the Host Controller. So we set the block size
1927 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1928 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1929 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1931 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1932 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1935 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1940 * The tuning block is sent by the card to the host controller.
1941 * So we set the TRNS_READ bit in the Transfer Mode register.
1942 * This also takes care of setting DMA Enable and Multi Block
1943 * Select in the same register to 0.
1945 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1947 sdhci_send_command(host, &cmd);
1952 spin_unlock_irqrestore(&host->lock, flags);
1953 /* Wait for Buffer Read Ready interrupt */
1954 wait_event_interruptible_timeout(host->buf_ready_int,
1955 (host->tuning_done == 1),
1956 msecs_to_jiffies(50));
1957 spin_lock_irqsave(&host->lock, flags);
1959 if (!host->tuning_done) {
1960 pr_info(DRIVER_NAME ": Timeout waiting for "
1961 "Buffer Read Ready interrupt during tuning "
1962 "procedure, falling back to fixed sampling "
1964 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1965 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1966 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1967 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1973 host->tuning_done = 0;
1975 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1977 /* eMMC spec does not require a delay between tuning cycles */
1978 if (opcode == MMC_SEND_TUNING_BLOCK)
1980 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1983 * The Host Driver has exhausted the maximum number of loops allowed,
1984 * so use fixed sampling frequency.
1986 if (tuning_loop_counter < 0) {
1987 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1988 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1990 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1991 pr_info(DRIVER_NAME ": Tuning procedure"
1992 " failed, falling back to fixed sampling"
1999 * If this is the very first time we are here, we start the retuning
2000 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2001 * flag won't be set, we check this condition before actually starting
2004 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2005 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2006 host->flags |= SDHCI_USING_RETUNING_TIMER;
2007 mod_timer(&host->tuning_timer, jiffies +
2008 host->tuning_count * HZ);
2009 /* Tuning mode 1 limits the maximum data length to 4MB */
2010 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2011 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2012 host->flags &= ~SDHCI_NEEDS_RETUNING;
2013 /* Reload the new initial value for timer */
2014 mod_timer(&host->tuning_timer, jiffies +
2015 host->tuning_count * HZ);
2019 * In case tuning fails, host controllers which support re-tuning can
2020 * try tuning again at a later time, when the re-tuning timer expires.
2021 * So for these controllers, we return 0. Since there might be other
2022 * controllers who do not have this capability, we return error for
2023 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2024 * a retuning timer to do the retuning for the card.
2026 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2029 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2030 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2031 spin_unlock_irqrestore(&host->lock, flags);
2032 sdhci_runtime_pm_put(host);
2038 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2040 /* Host Controller v3.00 defines preset value registers */
2041 if (host->version < SDHCI_SPEC_300)
2045 * We only enable or disable Preset Value if they are not already
2046 * enabled or disabled respectively. Otherwise, we bail out.
2048 if (host->preset_enabled != enable) {
2049 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2052 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2054 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2056 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2059 host->flags |= SDHCI_PV_ENABLED;
2061 host->flags &= ~SDHCI_PV_ENABLED;
2063 host->preset_enabled = enable;
2067 static void sdhci_card_event(struct mmc_host *mmc)
2069 struct sdhci_host *host = mmc_priv(mmc);
2070 unsigned long flags;
2072 /* First check if client has provided their own card event */
2073 if (host->ops->card_event)
2074 host->ops->card_event(host);
2076 spin_lock_irqsave(&host->lock, flags);
2078 /* Check host->mrq first in case we are runtime suspended */
2079 if (host->mrq && !sdhci_do_get_cd(host)) {
2080 pr_err("%s: Card removed during transfer!\n",
2081 mmc_hostname(host->mmc));
2082 pr_err("%s: Resetting controller.\n",
2083 mmc_hostname(host->mmc));
2085 sdhci_do_reset(host, SDHCI_RESET_CMD);
2086 sdhci_do_reset(host, SDHCI_RESET_DATA);
2088 host->mrq->cmd->error = -ENOMEDIUM;
2089 tasklet_schedule(&host->finish_tasklet);
2092 spin_unlock_irqrestore(&host->lock, flags);
2095 static const struct mmc_host_ops sdhci_ops = {
2096 .request = sdhci_request,
2097 .set_ios = sdhci_set_ios,
2098 .get_cd = sdhci_get_cd,
2099 .get_ro = sdhci_get_ro,
2100 .hw_reset = sdhci_hw_reset,
2101 .enable_sdio_irq = sdhci_enable_sdio_irq,
2102 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2103 .execute_tuning = sdhci_execute_tuning,
2104 .card_event = sdhci_card_event,
2105 .card_busy = sdhci_card_busy,
2108 /*****************************************************************************\
2112 \*****************************************************************************/
2114 static void sdhci_tasklet_finish(unsigned long param)
2116 struct sdhci_host *host;
2117 unsigned long flags;
2118 struct mmc_request *mrq;
2120 host = (struct sdhci_host*)param;
2122 spin_lock_irqsave(&host->lock, flags);
2125 * If this tasklet gets rescheduled while running, it will
2126 * be run again afterwards but without any active request.
2129 spin_unlock_irqrestore(&host->lock, flags);
2133 del_timer(&host->timer);
2138 * The controller needs a reset of internal state machines
2139 * upon error conditions.
2141 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2142 ((mrq->cmd && mrq->cmd->error) ||
2143 (mrq->data && (mrq->data->error ||
2144 (mrq->data->stop && mrq->data->stop->error))) ||
2145 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2147 /* Some controllers need this kick or reset won't work here */
2148 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2149 /* This is to force an update */
2150 host->ops->set_clock(host, host->clock);
2152 /* Spec says we should do both at the same time, but Ricoh
2153 controllers do not like that. */
2154 sdhci_do_reset(host, SDHCI_RESET_CMD);
2155 sdhci_do_reset(host, SDHCI_RESET_DATA);
2162 #ifndef SDHCI_USE_LEDS_CLASS
2163 sdhci_deactivate_led(host);
2167 spin_unlock_irqrestore(&host->lock, flags);
2169 mmc_request_done(host->mmc, mrq);
2170 sdhci_runtime_pm_put(host);
2173 static void sdhci_timeout_timer(unsigned long data)
2175 struct sdhci_host *host;
2176 unsigned long flags;
2178 host = (struct sdhci_host*)data;
2180 spin_lock_irqsave(&host->lock, flags);
2183 pr_err("%s: Timeout waiting for hardware "
2184 "interrupt.\n", mmc_hostname(host->mmc));
2185 sdhci_dumpregs(host);
2188 host->data->error = -ETIMEDOUT;
2189 sdhci_finish_data(host);
2192 host->cmd->error = -ETIMEDOUT;
2194 host->mrq->cmd->error = -ETIMEDOUT;
2196 tasklet_schedule(&host->finish_tasklet);
2201 spin_unlock_irqrestore(&host->lock, flags);
2204 static void sdhci_tuning_timer(unsigned long data)
2206 struct sdhci_host *host;
2207 unsigned long flags;
2209 host = (struct sdhci_host *)data;
2211 spin_lock_irqsave(&host->lock, flags);
2213 host->flags |= SDHCI_NEEDS_RETUNING;
2215 spin_unlock_irqrestore(&host->lock, flags);
2218 /*****************************************************************************\
2220 * Interrupt handling *
2222 \*****************************************************************************/
2224 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2226 BUG_ON(intmask == 0);
2229 pr_err("%s: Got command interrupt 0x%08x even "
2230 "though no command operation was in progress.\n",
2231 mmc_hostname(host->mmc), (unsigned)intmask);
2232 sdhci_dumpregs(host);
2236 if (intmask & SDHCI_INT_TIMEOUT)
2237 host->cmd->error = -ETIMEDOUT;
2238 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2240 host->cmd->error = -EILSEQ;
2242 if (host->cmd->error) {
2243 tasklet_schedule(&host->finish_tasklet);
2248 * The host can send and interrupt when the busy state has
2249 * ended, allowing us to wait without wasting CPU cycles.
2250 * Unfortunately this is overloaded on the "data complete"
2251 * interrupt, so we need to take some care when handling
2254 * Note: The 1.0 specification is a bit ambiguous about this
2255 * feature so there might be some problems with older
2258 if (host->cmd->flags & MMC_RSP_BUSY) {
2259 if (host->cmd->data)
2260 DBG("Cannot wait for busy signal when also "
2261 "doing a data transfer");
2262 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2265 /* The controller does not support the end-of-busy IRQ,
2266 * fall through and take the SDHCI_INT_RESPONSE */
2269 if (intmask & SDHCI_INT_RESPONSE)
2270 sdhci_finish_command(host);
2273 #ifdef CONFIG_MMC_DEBUG
2274 static void sdhci_show_adma_error(struct sdhci_host *host)
2276 const char *name = mmc_hostname(host->mmc);
2277 u8 *desc = host->adma_desc;
2282 sdhci_dumpregs(host);
2285 dma = (__le32 *)(desc + 4);
2286 len = (__le16 *)(desc + 2);
2289 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2290 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2299 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2302 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2305 BUG_ON(intmask == 0);
2307 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2308 if (intmask & SDHCI_INT_DATA_AVAIL) {
2309 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2310 if (command == MMC_SEND_TUNING_BLOCK ||
2311 command == MMC_SEND_TUNING_BLOCK_HS200) {
2312 host->tuning_done = 1;
2313 wake_up(&host->buf_ready_int);
2320 * The "data complete" interrupt is also used to
2321 * indicate that a busy state has ended. See comment
2322 * above in sdhci_cmd_irq().
2324 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2325 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2326 host->cmd->error = -ETIMEDOUT;
2327 tasklet_schedule(&host->finish_tasklet);
2330 if (intmask & SDHCI_INT_DATA_END) {
2331 sdhci_finish_command(host);
2336 pr_err("%s: Got data interrupt 0x%08x even "
2337 "though no data operation was in progress.\n",
2338 mmc_hostname(host->mmc), (unsigned)intmask);
2339 sdhci_dumpregs(host);
2344 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2345 host->data->error = -ETIMEDOUT;
2346 else if (intmask & SDHCI_INT_DATA_END_BIT)
2347 host->data->error = -EILSEQ;
2348 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2349 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2351 host->data->error = -EILSEQ;
2352 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2353 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2354 sdhci_show_adma_error(host);
2355 host->data->error = -EIO;
2356 if (host->ops->adma_workaround)
2357 host->ops->adma_workaround(host, intmask);
2360 if (host->data->error)
2361 sdhci_finish_data(host);
2363 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2364 sdhci_transfer_pio(host);
2367 * We currently don't do anything fancy with DMA
2368 * boundaries, but as we can't disable the feature
2369 * we need to at least restart the transfer.
2371 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2372 * should return a valid address to continue from, but as
2373 * some controllers are faulty, don't trust them.
2375 if (intmask & SDHCI_INT_DMA_END) {
2376 u32 dmastart, dmanow;
2377 dmastart = sg_dma_address(host->data->sg);
2378 dmanow = dmastart + host->data->bytes_xfered;
2380 * Force update to the next DMA block boundary.
2383 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2384 SDHCI_DEFAULT_BOUNDARY_SIZE;
2385 host->data->bytes_xfered = dmanow - dmastart;
2386 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2388 mmc_hostname(host->mmc), dmastart,
2389 host->data->bytes_xfered, dmanow);
2390 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2393 if (intmask & SDHCI_INT_DATA_END) {
2396 * Data managed to finish before the
2397 * command completed. Make sure we do
2398 * things in the proper order.
2400 host->data_early = 1;
2402 sdhci_finish_data(host);
2408 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2410 irqreturn_t result = IRQ_NONE;
2411 struct sdhci_host *host = dev_id;
2412 u32 intmask, mask, unexpected = 0;
2415 spin_lock(&host->lock);
2417 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2418 spin_unlock(&host->lock);
2422 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2423 if (!intmask || intmask == 0xffffffff) {
2429 /* Clear selected interrupts. */
2430 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2431 SDHCI_INT_BUS_POWER);
2432 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2434 DBG("*** %s got interrupt: 0x%08x\n",
2435 mmc_hostname(host->mmc), intmask);
2437 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2438 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2442 * There is a observation on i.mx esdhc. INSERT
2443 * bit will be immediately set again when it gets
2444 * cleared, if a card is inserted. We have to mask
2445 * the irq to prevent interrupt storm which will
2446 * freeze the system. And the REMOVE gets the
2449 * More testing are needed here to ensure it works
2450 * for other platforms though.
2452 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2453 SDHCI_INT_CARD_REMOVE);
2454 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2455 SDHCI_INT_CARD_INSERT;
2456 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2457 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2459 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2460 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2462 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2463 SDHCI_INT_CARD_REMOVE);
2464 result = IRQ_WAKE_THREAD;
2467 if (intmask & SDHCI_INT_CMD_MASK)
2468 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2470 if (intmask & SDHCI_INT_DATA_MASK)
2471 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2473 if (intmask & SDHCI_INT_BUS_POWER)
2474 pr_err("%s: Card is consuming too much power!\n",
2475 mmc_hostname(host->mmc));
2477 if (intmask & SDHCI_INT_CARD_INT) {
2478 sdhci_enable_sdio_irq_nolock(host, false);
2479 host->thread_isr |= SDHCI_INT_CARD_INT;
2480 result = IRQ_WAKE_THREAD;
2483 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2484 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2485 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2486 SDHCI_INT_CARD_INT);
2489 unexpected |= intmask;
2490 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2493 if (result == IRQ_NONE)
2494 result = IRQ_HANDLED;
2496 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2497 } while (intmask && --max_loops);
2499 spin_unlock(&host->lock);
2502 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2503 mmc_hostname(host->mmc), unexpected);
2504 sdhci_dumpregs(host);
2510 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2512 struct sdhci_host *host = dev_id;
2513 unsigned long flags;
2516 spin_lock_irqsave(&host->lock, flags);
2517 isr = host->thread_isr;
2518 host->thread_isr = 0;
2519 spin_unlock_irqrestore(&host->lock, flags);
2521 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2522 sdhci_card_event(host->mmc);
2523 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2526 if (isr & SDHCI_INT_CARD_INT) {
2527 sdio_run_irqs(host->mmc);
2529 spin_lock_irqsave(&host->lock, flags);
2530 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2531 sdhci_enable_sdio_irq_nolock(host, true);
2532 spin_unlock_irqrestore(&host->lock, flags);
2535 return isr ? IRQ_HANDLED : IRQ_NONE;
2538 /*****************************************************************************\
2542 \*****************************************************************************/
2545 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2548 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2549 | SDHCI_WAKE_ON_INT;
2551 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2553 /* Avoid fake wake up */
2554 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2555 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2556 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2558 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2560 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2563 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2564 | SDHCI_WAKE_ON_INT;
2566 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2568 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2570 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2572 int sdhci_suspend_host(struct sdhci_host *host)
2574 sdhci_disable_card_detection(host);
2576 /* Disable tuning since we are suspending */
2577 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2578 del_timer_sync(&host->tuning_timer);
2579 host->flags &= ~SDHCI_NEEDS_RETUNING;
2582 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2584 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2585 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2586 free_irq(host->irq, host);
2588 sdhci_enable_irq_wakeups(host);
2589 enable_irq_wake(host->irq);
2594 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2596 int sdhci_resume_host(struct sdhci_host *host)
2600 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2601 if (host->ops->enable_dma)
2602 host->ops->enable_dma(host);
2605 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2606 ret = request_threaded_irq(host->irq, sdhci_irq,
2607 sdhci_thread_irq, IRQF_SHARED,
2608 mmc_hostname(host->mmc), host);
2612 sdhci_disable_irq_wakeups(host);
2613 disable_irq_wake(host->irq);
2616 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2617 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2618 /* Card keeps power but host controller does not */
2619 sdhci_init(host, 0);
2622 sdhci_do_set_ios(host, &host->mmc->ios);
2624 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2628 sdhci_enable_card_detection(host);
2630 /* Set the re-tuning expiration flag */
2631 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2632 host->flags |= SDHCI_NEEDS_RETUNING;
2637 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2638 #endif /* CONFIG_PM */
2640 #ifdef CONFIG_PM_RUNTIME
2642 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2644 return pm_runtime_get_sync(host->mmc->parent);
2647 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2649 pm_runtime_mark_last_busy(host->mmc->parent);
2650 return pm_runtime_put_autosuspend(host->mmc->parent);
2653 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2655 if (host->runtime_suspended || host->bus_on)
2657 host->bus_on = true;
2658 pm_runtime_get_noresume(host->mmc->parent);
2661 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2663 if (host->runtime_suspended || !host->bus_on)
2665 host->bus_on = false;
2666 pm_runtime_put_noidle(host->mmc->parent);
2669 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2671 unsigned long flags;
2673 /* Disable tuning since we are suspending */
2674 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2675 del_timer_sync(&host->tuning_timer);
2676 host->flags &= ~SDHCI_NEEDS_RETUNING;
2679 spin_lock_irqsave(&host->lock, flags);
2680 host->ier &= SDHCI_INT_CARD_INT;
2681 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2682 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2683 spin_unlock_irqrestore(&host->lock, flags);
2685 synchronize_hardirq(host->irq);
2687 spin_lock_irqsave(&host->lock, flags);
2688 host->runtime_suspended = true;
2689 spin_unlock_irqrestore(&host->lock, flags);
2693 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2695 int sdhci_runtime_resume_host(struct sdhci_host *host)
2697 unsigned long flags;
2698 int host_flags = host->flags;
2700 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2701 if (host->ops->enable_dma)
2702 host->ops->enable_dma(host);
2705 sdhci_init(host, 0);
2707 /* Force clock and power re-program */
2710 sdhci_do_set_ios(host, &host->mmc->ios);
2712 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2713 if ((host_flags & SDHCI_PV_ENABLED) &&
2714 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2715 spin_lock_irqsave(&host->lock, flags);
2716 sdhci_enable_preset_value(host, true);
2717 spin_unlock_irqrestore(&host->lock, flags);
2720 /* Set the re-tuning expiration flag */
2721 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2722 host->flags |= SDHCI_NEEDS_RETUNING;
2724 spin_lock_irqsave(&host->lock, flags);
2726 host->runtime_suspended = false;
2728 /* Enable SDIO IRQ */
2729 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2730 sdhci_enable_sdio_irq_nolock(host, true);
2732 /* Enable Card Detection */
2733 sdhci_enable_card_detection(host);
2735 spin_unlock_irqrestore(&host->lock, flags);
2739 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2743 /*****************************************************************************\
2745 * Device allocation/registration *
2747 \*****************************************************************************/
2749 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2752 struct mmc_host *mmc;
2753 struct sdhci_host *host;
2755 WARN_ON(dev == NULL);
2757 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2759 return ERR_PTR(-ENOMEM);
2761 host = mmc_priv(mmc);
2767 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2769 int sdhci_add_host(struct sdhci_host *host)
2771 struct mmc_host *mmc;
2772 u32 caps[2] = {0, 0};
2773 u32 max_current_caps;
2774 unsigned int ocr_avail;
2777 WARN_ON(host == NULL);
2784 host->quirks = debug_quirks;
2786 host->quirks2 = debug_quirks2;
2788 sdhci_do_reset(host, SDHCI_RESET_ALL);
2790 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2791 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2792 >> SDHCI_SPEC_VER_SHIFT;
2793 if (host->version > SDHCI_SPEC_300) {
2794 pr_err("%s: Unknown controller version (%d). "
2795 "You may experience problems.\n", mmc_hostname(mmc),
2799 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2800 sdhci_readl(host, SDHCI_CAPABILITIES);
2802 if (host->version >= SDHCI_SPEC_300)
2803 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2805 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2807 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2808 host->flags |= SDHCI_USE_SDMA;
2809 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2810 DBG("Controller doesn't have SDMA capability\n");
2812 host->flags |= SDHCI_USE_SDMA;
2814 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2815 (host->flags & SDHCI_USE_SDMA)) {
2816 DBG("Disabling DMA as it is marked broken\n");
2817 host->flags &= ~SDHCI_USE_SDMA;
2820 if ((host->version >= SDHCI_SPEC_200) &&
2821 (caps[0] & SDHCI_CAN_DO_ADMA2))
2822 host->flags |= SDHCI_USE_ADMA;
2824 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2825 (host->flags & SDHCI_USE_ADMA)) {
2826 DBG("Disabling ADMA as it is marked broken\n");
2827 host->flags &= ~SDHCI_USE_ADMA;
2830 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2831 if (host->ops->enable_dma) {
2832 if (host->ops->enable_dma(host)) {
2833 pr_warning("%s: No suitable DMA "
2834 "available. Falling back to PIO.\n",
2837 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2842 if (host->flags & SDHCI_USE_ADMA) {
2844 * We need to allocate descriptors for all sg entries
2845 * (128) and potentially one alignment transfer for
2846 * each of those entries.
2848 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
2849 ADMA_SIZE, &host->adma_addr,
2851 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2852 if (!host->adma_desc || !host->align_buffer) {
2853 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2854 host->adma_desc, host->adma_addr);
2855 kfree(host->align_buffer);
2856 pr_warning("%s: Unable to allocate ADMA "
2857 "buffers. Falling back to standard DMA.\n",
2859 host->flags &= ~SDHCI_USE_ADMA;
2860 host->adma_desc = NULL;
2861 host->align_buffer = NULL;
2862 } else if (host->adma_addr & 3) {
2863 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2865 host->flags &= ~SDHCI_USE_ADMA;
2866 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2867 host->adma_desc, host->adma_addr);
2868 kfree(host->align_buffer);
2869 host->adma_desc = NULL;
2870 host->align_buffer = NULL;
2875 * If we use DMA, then it's up to the caller to set the DMA
2876 * mask, but PIO does not need the hw shim so we set a new
2877 * mask here in that case.
2879 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2880 host->dma_mask = DMA_BIT_MASK(64);
2881 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2884 if (host->version >= SDHCI_SPEC_300)
2885 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2886 >> SDHCI_CLOCK_BASE_SHIFT;
2888 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2889 >> SDHCI_CLOCK_BASE_SHIFT;
2891 host->max_clk *= 1000000;
2892 if (host->max_clk == 0 || host->quirks &
2893 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2894 if (!host->ops->get_max_clock) {
2895 pr_err("%s: Hardware doesn't specify base clock "
2896 "frequency.\n", mmc_hostname(mmc));
2899 host->max_clk = host->ops->get_max_clock(host);
2903 * In case of Host Controller v3.00, find out whether clock
2904 * multiplier is supported.
2906 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2907 SDHCI_CLOCK_MUL_SHIFT;
2910 * In case the value in Clock Multiplier is 0, then programmable
2911 * clock mode is not supported, otherwise the actual clock
2912 * multiplier is one more than the value of Clock Multiplier
2913 * in the Capabilities Register.
2919 * Set host parameters.
2921 mmc->ops = &sdhci_ops;
2922 mmc->f_max = host->max_clk;
2923 if (host->ops->get_min_clock)
2924 mmc->f_min = host->ops->get_min_clock(host);
2925 else if (host->version >= SDHCI_SPEC_300) {
2926 if (host->clk_mul) {
2927 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2928 mmc->f_max = host->max_clk * host->clk_mul;
2930 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2932 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2934 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2935 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2936 SDHCI_TIMEOUT_CLK_SHIFT;
2937 if (host->timeout_clk == 0) {
2938 if (host->ops->get_timeout_clock) {
2940 host->ops->get_timeout_clock(host);
2942 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2948 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2949 host->timeout_clk *= 1000;
2951 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2952 host->ops->get_max_timeout_count(host) : 1 << 27;
2953 mmc->max_busy_timeout /= host->timeout_clk;
2956 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2957 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2959 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2960 host->flags |= SDHCI_AUTO_CMD12;
2962 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2963 if ((host->version >= SDHCI_SPEC_300) &&
2964 ((host->flags & SDHCI_USE_ADMA) ||
2965 !(host->flags & SDHCI_USE_SDMA))) {
2966 host->flags |= SDHCI_AUTO_CMD23;
2967 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2969 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2973 * A controller may support 8-bit width, but the board itself
2974 * might not have the pins brought out. Boards that support
2975 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2976 * their platform code before calling sdhci_add_host(), and we
2977 * won't assume 8-bit width for hosts without that CAP.
2979 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2980 mmc->caps |= MMC_CAP_4_BIT_DATA;
2982 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2983 mmc->caps &= ~MMC_CAP_CMD23;
2985 if (caps[0] & SDHCI_CAN_DO_HISPD)
2986 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2988 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2989 !(mmc->caps & MMC_CAP_NONREMOVABLE))
2990 mmc->caps |= MMC_CAP_NEEDS_POLL;
2992 /* If there are external regulators, get them */
2993 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
2994 return -EPROBE_DEFER;
2996 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2997 if (!IS_ERR(mmc->supply.vqmmc)) {
2998 ret = regulator_enable(mmc->supply.vqmmc);
2999 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3001 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3002 SDHCI_SUPPORT_SDR50 |
3003 SDHCI_SUPPORT_DDR50);
3005 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3006 mmc_hostname(mmc), ret);
3007 mmc->supply.vqmmc = NULL;
3011 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3012 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3013 SDHCI_SUPPORT_DDR50);
3015 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3016 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3017 SDHCI_SUPPORT_DDR50))
3018 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3020 /* SDR104 supports also implies SDR50 support */
3021 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3022 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3023 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3024 * field can be promoted to support HS200.
3026 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3027 mmc->caps2 |= MMC_CAP2_HS200;
3028 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3029 mmc->caps |= MMC_CAP_UHS_SDR50;
3031 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3032 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3033 mmc->caps |= MMC_CAP_UHS_DDR50;
3035 /* Does the host need tuning for SDR50? */
3036 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3037 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3039 /* Does the host need tuning for SDR104 / HS200? */
3040 if (mmc->caps2 & MMC_CAP2_HS200)
3041 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3043 /* Driver Type(s) (A, C, D) supported by the host */
3044 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3045 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3046 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3047 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3048 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3049 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3051 /* Initial value for re-tuning timer count */
3052 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3053 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3056 * In case Re-tuning Timer is not disabled, the actual value of
3057 * re-tuning timer will be 2 ^ (n - 1).
3059 if (host->tuning_count)
3060 host->tuning_count = 1 << (host->tuning_count - 1);
3062 /* Re-tuning mode supported by the Host Controller */
3063 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3064 SDHCI_RETUNING_MODE_SHIFT;
3069 * According to SD Host Controller spec v3.00, if the Host System
3070 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3071 * the value is meaningful only if Voltage Support in the Capabilities
3072 * register is set. The actual current value is 4 times the register
3075 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3076 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3077 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3080 /* convert to SDHCI_MAX_CURRENT format */
3081 curr = curr/1000; /* convert to mA */
3082 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3084 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3086 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3087 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3088 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3092 if (caps[0] & SDHCI_CAN_VDD_330) {
3093 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3095 mmc->max_current_330 = ((max_current_caps &
3096 SDHCI_MAX_CURRENT_330_MASK) >>
3097 SDHCI_MAX_CURRENT_330_SHIFT) *
3098 SDHCI_MAX_CURRENT_MULTIPLIER;
3100 if (caps[0] & SDHCI_CAN_VDD_300) {
3101 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3103 mmc->max_current_300 = ((max_current_caps &
3104 SDHCI_MAX_CURRENT_300_MASK) >>
3105 SDHCI_MAX_CURRENT_300_SHIFT) *
3106 SDHCI_MAX_CURRENT_MULTIPLIER;
3108 if (caps[0] & SDHCI_CAN_VDD_180) {
3109 ocr_avail |= MMC_VDD_165_195;
3111 mmc->max_current_180 = ((max_current_caps &
3112 SDHCI_MAX_CURRENT_180_MASK) >>
3113 SDHCI_MAX_CURRENT_180_SHIFT) *
3114 SDHCI_MAX_CURRENT_MULTIPLIER;
3117 /* If OCR set by external regulators, use it instead */
3119 ocr_avail = mmc->ocr_avail;
3122 ocr_avail &= host->ocr_mask;
3124 mmc->ocr_avail = ocr_avail;
3125 mmc->ocr_avail_sdio = ocr_avail;
3126 if (host->ocr_avail_sdio)
3127 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3128 mmc->ocr_avail_sd = ocr_avail;
3129 if (host->ocr_avail_sd)
3130 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3131 else /* normal SD controllers don't support 1.8V */
3132 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3133 mmc->ocr_avail_mmc = ocr_avail;
3134 if (host->ocr_avail_mmc)
3135 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3137 if (mmc->ocr_avail == 0) {
3138 pr_err("%s: Hardware doesn't report any "
3139 "support voltages.\n", mmc_hostname(mmc));
3143 spin_lock_init(&host->lock);
3146 * Maximum number of segments. Depends on if the hardware
3147 * can do scatter/gather or not.
3149 if (host->flags & SDHCI_USE_ADMA)
3150 mmc->max_segs = 128;
3151 else if (host->flags & SDHCI_USE_SDMA)
3154 mmc->max_segs = 128;
3157 * Maximum number of sectors in one transfer. Limited by DMA boundary
3160 mmc->max_req_size = 524288;
3163 * Maximum segment size. Could be one segment with the maximum number
3164 * of bytes. When doing hardware scatter/gather, each entry cannot
3165 * be larger than 64 KiB though.
3167 if (host->flags & SDHCI_USE_ADMA) {
3168 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3169 mmc->max_seg_size = 65535;
3171 mmc->max_seg_size = 65536;
3173 mmc->max_seg_size = mmc->max_req_size;
3177 * Maximum block size. This varies from controller to controller and
3178 * is specified in the capabilities register.
3180 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3181 mmc->max_blk_size = 2;
3183 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3184 SDHCI_MAX_BLOCK_SHIFT;
3185 if (mmc->max_blk_size >= 3) {
3186 pr_warning("%s: Invalid maximum block size, "
3187 "assuming 512 bytes\n", mmc_hostname(mmc));
3188 mmc->max_blk_size = 0;
3192 mmc->max_blk_size = 512 << mmc->max_blk_size;
3195 * Maximum block count.
3197 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3202 tasklet_init(&host->finish_tasklet,
3203 sdhci_tasklet_finish, (unsigned long)host);
3205 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3207 if (host->version >= SDHCI_SPEC_300) {
3208 init_waitqueue_head(&host->buf_ready_int);
3210 /* Initialize re-tuning timer */
3211 init_timer(&host->tuning_timer);
3212 host->tuning_timer.data = (unsigned long)host;
3213 host->tuning_timer.function = sdhci_tuning_timer;
3216 sdhci_init(host, 0);
3218 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3219 IRQF_SHARED, mmc_hostname(mmc), host);
3221 pr_err("%s: Failed to request IRQ %d: %d\n",
3222 mmc_hostname(mmc), host->irq, ret);
3226 #ifdef CONFIG_MMC_DEBUG
3227 sdhci_dumpregs(host);
3230 #ifdef SDHCI_USE_LEDS_CLASS
3231 snprintf(host->led_name, sizeof(host->led_name),
3232 "%s::", mmc_hostname(mmc));
3233 host->led.name = host->led_name;
3234 host->led.brightness = LED_OFF;
3235 host->led.default_trigger = mmc_hostname(mmc);
3236 host->led.brightness_set = sdhci_led_control;
3238 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3240 pr_err("%s: Failed to register LED device: %d\n",
3241 mmc_hostname(mmc), ret);
3250 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3251 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3252 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3253 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3255 sdhci_enable_card_detection(host);
3259 #ifdef SDHCI_USE_LEDS_CLASS
3261 sdhci_do_reset(host, SDHCI_RESET_ALL);
3262 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3263 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3264 free_irq(host->irq, host);
3267 tasklet_kill(&host->finish_tasklet);
3272 EXPORT_SYMBOL_GPL(sdhci_add_host);
3274 void sdhci_remove_host(struct sdhci_host *host, int dead)
3276 struct mmc_host *mmc = host->mmc;
3277 unsigned long flags;
3280 spin_lock_irqsave(&host->lock, flags);
3282 host->flags |= SDHCI_DEVICE_DEAD;
3285 pr_err("%s: Controller removed during "
3286 " transfer!\n", mmc_hostname(mmc));
3288 host->mrq->cmd->error = -ENOMEDIUM;
3289 tasklet_schedule(&host->finish_tasklet);
3292 spin_unlock_irqrestore(&host->lock, flags);
3295 sdhci_disable_card_detection(host);
3297 mmc_remove_host(mmc);
3299 #ifdef SDHCI_USE_LEDS_CLASS
3300 led_classdev_unregister(&host->led);
3304 sdhci_do_reset(host, SDHCI_RESET_ALL);
3306 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3307 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3308 free_irq(host->irq, host);
3310 del_timer_sync(&host->timer);
3312 tasklet_kill(&host->finish_tasklet);
3314 if (!IS_ERR(mmc->supply.vmmc))
3315 regulator_disable(mmc->supply.vmmc);
3317 if (!IS_ERR(mmc->supply.vqmmc))
3318 regulator_disable(mmc->supply.vqmmc);
3320 if (host->adma_desc)
3321 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3322 host->adma_desc, host->adma_addr);
3323 kfree(host->align_buffer);
3325 host->adma_desc = NULL;
3326 host->align_buffer = NULL;
3329 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3331 void sdhci_free_host(struct sdhci_host *host)
3333 mmc_free_host(host->mmc);
3336 EXPORT_SYMBOL_GPL(sdhci_free_host);
3338 /*****************************************************************************\
3340 * Driver init/exit *
3342 \*****************************************************************************/
3344 static int __init sdhci_drv_init(void)
3347 ": Secure Digital Host Controller Interface driver\n");
3348 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3353 static void __exit sdhci_drv_exit(void)
3357 module_init(sdhci_drv_init);
3358 module_exit(sdhci_drv_exit);
3360 module_param(debug_quirks, uint, 0444);
3361 module_param(debug_quirks2, uint, 0444);
3363 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3364 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3365 MODULE_LICENSE("GPL");
3367 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3368 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");