drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/mmc/slot-gpio.h>
  58 #include <linux/mod_devicetable.h>
  59 #include <linux/mutex.h>
  60 #include <linux/pagemap.h>
  61 #include <linux/platform_device.h>
  62 #include <linux/pm_qos.h>
  63 #include <linux/pm_runtime.h>
  64 #include <linux/sh_dma.h>
  65 #include <linux/spinlock.h>
  66 #include <linux/module.h>
  67
  68 #define DRIVER_NAME     "sh_mmcif"
  69 #define DRIVER_VERSION  "2010-04-28"
  70
  71 /* CE_CMD_SET */
  72 #define CMD_MASK                0x3f000000
  73 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  74 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  75 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  76 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  77 #define CMD_SET_CCSEN           (1 << 20)
  78 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  79 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  80 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  81 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  82 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  83 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  84 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  85 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  86 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  87 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  88 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  89 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  90 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  91 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  92 #define CMD_SET_CCSH            (1 << 5)
  93 #define CMD_SET_DARS            (1 << 2) /* Dual Data Rate */
  94 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  95 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  96 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  97
  98 /* CE_CMD_CTRL */
  99 #define CMD_CTRL_BREAK          (1 << 0)
 100
 101 /* CE_BLOCK_SET */
 102 #define BLOCK_SIZE_MASK         0x0000ffff
 103
 104 /* CE_INT */
 105 #define INT_CCSDE               (1 << 29)
 106 #define INT_CMD12DRE            (1 << 26)
 107 #define INT_CMD12RBE            (1 << 25)
 108 #define INT_CMD12CRE            (1 << 24)
 109 #define INT_DTRANE              (1 << 23)
 110 #define INT_BUFRE               (1 << 22)
 111 #define INT_BUFWEN              (1 << 21)
 112 #define INT_BUFREN              (1 << 20)
 113 #define INT_CCSRCV              (1 << 19)
 114 #define INT_RBSYE               (1 << 17)
 115 #define INT_CRSPE               (1 << 16)
 116 #define INT_CMDVIO              (1 << 15)
 117 #define INT_BUFVIO              (1 << 14)
 118 #define INT_WDATERR             (1 << 11)
 119 #define INT_RDATERR             (1 << 10)
 120 #define INT_RIDXERR             (1 << 9)
 121 #define INT_RSPERR              (1 << 8)
 122 #define INT_CCSTO               (1 << 5)
 123 #define INT_CRCSTO              (1 << 4)
 124 #define INT_WDATTO              (1 << 3)
 125 #define INT_RDATTO              (1 << 2)
 126 #define INT_RBSYTO              (1 << 1)
 127 #define INT_RSPTO               (1 << 0)
 128 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 129                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 130                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 131                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 132
 133 #define INT_ALL                 (INT_RBSYE | INT_CRSPE | INT_BUFREN |    \
 134                                  INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
 135                                  INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
 136
 137 #define INT_CCS                 (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
 138
 139 /* CE_INT_MASK */
 140 #define MASK_ALL                0x00000000
 141 #define MASK_MCCSDE             (1 << 29)
 142 #define MASK_MCMD12DRE          (1 << 26)
 143 #define MASK_MCMD12RBE          (1 << 25)
 144 #define MASK_MCMD12CRE          (1 << 24)
 145 #define MASK_MDTRANE            (1 << 23)
 146 #define MASK_MBUFRE             (1 << 22)
 147 #define MASK_MBUFWEN            (1 << 21)
 148 #define MASK_MBUFREN            (1 << 20)
 149 #define MASK_MCCSRCV            (1 << 19)
 150 #define MASK_MRBSYE             (1 << 17)
 151 #define MASK_MCRSPE             (1 << 16)
 152 #define MASK_MCMDVIO            (1 << 15)
 153 #define MASK_MBUFVIO            (1 << 14)
 154 #define MASK_MWDATERR           (1 << 11)
 155 #define MASK_MRDATERR           (1 << 10)
 156 #define MASK_MRIDXERR           (1 << 9)
 157 #define MASK_MRSPERR            (1 << 8)
 158 #define MASK_MCCSTO             (1 << 5)
 159 #define MASK_MCRCSTO            (1 << 4)
 160 #define MASK_MWDATTO            (1 << 3)
 161 #define MASK_MRDATTO            (1 << 2)
 162 #define MASK_MRBSYTO            (1 << 1)
 163 #define MASK_MRSPTO             (1 << 0)
 164
 165 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 166                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 167                                  MASK_MCRCSTO | MASK_MWDATTO | \
 168                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 169
 170 #define MASK_CLEAN              (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE |      \
 171                                  MASK_MBUFREN | MASK_MBUFWEN |                  \
 172                                  MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE |  \
 173                                  MASK_MCMD12RBE | MASK_MCMD12CRE)
 174
 175 /* CE_HOST_STS1 */
 176 #define STS1_CMDSEQ             (1 << 31)
 177
 178 /* CE_HOST_STS2 */
 179 #define STS2_CRCSTE             (1 << 31)
 180 #define STS2_CRC16E             (1 << 30)
 181 #define STS2_AC12CRCE           (1 << 29)
 182 #define STS2_RSPCRC7E           (1 << 28)
 183 #define STS2_CRCSTEBE           (1 << 27)
 184 #define STS2_RDATEBE            (1 << 26)
 185 #define STS2_AC12REBE           (1 << 25)
 186 #define STS2_RSPEBE             (1 << 24)
 187 #define STS2_AC12IDXE           (1 << 23)
 188 #define STS2_RSPIDXE            (1 << 22)
 189 #define STS2_CCSTO              (1 << 15)
 190 #define STS2_RDATTO             (1 << 14)
 191 #define STS2_DATBSYTO           (1 << 13)
 192 #define STS2_CRCSTTO            (1 << 12)
 193 #define STS2_AC12BSYTO          (1 << 11)
 194 #define STS2_RSPBSYTO           (1 << 10)
 195 #define STS2_AC12RSPTO          (1 << 9)
 196 #define STS2_RSPTO              (1 << 8)
 197 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 198                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 199 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 200                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 201                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 202                                  STS2_AC12RSPTO | STS2_RSPTO)
 203
 204 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 205 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 206 #define CLKDEV_INIT             400000   /* 400 KHz */
 207
 208 enum mmcif_state {
 209         STATE_IDLE,
 210         STATE_REQUEST,
 211         STATE_IOS,
 212         STATE_TIMEOUT,
 213 };
 214
 215 enum mmcif_wait_for {
 216         MMCIF_WAIT_FOR_REQUEST,
 217         MMCIF_WAIT_FOR_CMD,
 218         MMCIF_WAIT_FOR_MREAD,
 219         MMCIF_WAIT_FOR_MWRITE,
 220         MMCIF_WAIT_FOR_READ,
 221         MMCIF_WAIT_FOR_WRITE,
 222         MMCIF_WAIT_FOR_READ_END,
 223         MMCIF_WAIT_FOR_WRITE_END,
 224         MMCIF_WAIT_FOR_STOP,
 225 };
 226
 227 struct sh_mmcif_host {
 228         struct mmc_host *mmc;
 229         struct mmc_request *mrq;
 230         struct platform_device *pd;
 231         struct clk *clk;
 232         int bus_width;
 233         unsigned char timing;
 234         bool sd_error;
 235         bool dying;
 236         long timeout;
 237         void __iomem *addr;
 238         u32 *pio_ptr;
 239         spinlock_t lock;                /* protect sh_mmcif_host::state */
 240         enum mmcif_state state;
 241         enum mmcif_wait_for wait_for;
 242         struct delayed_work timeout_work;
 243         size_t blocksize;
 244         int sg_idx;
 245         int sg_blkidx;
 246         bool power;
 247         bool card_present;
 248         bool ccs_enable;                /* Command Completion Signal support */
 249         bool clk_ctrl2_enable;
 250         struct mutex thread_lock;
 251
 252         /* DMA support */
 253         struct dma_chan         *chan_rx;
 254         struct dma_chan         *chan_tx;
 255         struct completion       dma_complete;
 256         bool                    dma_active;
 257 };
 258
 259 static const struct of_device_id mmcif_of_match[] = {
 260         { .compatible = "renesas,sh-mmcif" },
 261         { }
 262 };
 263 MODULE_DEVICE_TABLE(of, mmcif_of_match);
 264
 265 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 266                                         unsigned int reg, u32 val)
 267 {
 268         writel(val | readl(host->addr + reg), host->addr + reg);
 269 }
 270
 271 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 272                                         unsigned int reg, u32 val)
 273 {
 274         writel(~val & readl(host->addr + reg), host->addr + reg);
 275 }
 276
 277 static void mmcif_dma_complete(void *arg)
 278 {
 279         struct sh_mmcif_host *host = arg;
 280         struct mmc_request *mrq = host->mrq;
 281
 282         dev_dbg(&host->pd->dev, "Command completed\n");
 283
 284         if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
 285                  dev_name(&host->pd->dev)))
 286                 return;
 287
 288         complete(&host->dma_complete);
 289 }
 290
 291 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 292 {
 293         struct mmc_data *data = host->mrq->data;
 294         struct scatterlist *sg = data->sg;
 295         struct dma_async_tx_descriptor *desc = NULL;
 296         struct dma_chan *chan = host->chan_rx;
 297         dma_cookie_t cookie = -EINVAL;
 298         int ret;
 299
 300         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 301                          DMA_FROM_DEVICE);
 302         if (ret > 0) {
 303                 host->dma_active = true;
 304                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 305                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 306         }
 307
 308         if (desc) {
 309                 desc->callback = mmcif_dma_complete;
 310                 desc->callback_param = host;
 311                 cookie = dmaengine_submit(desc);
 312                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 313                 dma_async_issue_pending(chan);
 314         }
 315         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 316                 __func__, data->sg_len, ret, cookie);
 317
 318         if (!desc) {
 319                 /* DMA failed, fall back to PIO */
 320                 if (ret >= 0)
 321                         ret = -EIO;
 322                 host->chan_rx = NULL;
 323                 host->dma_active = false;
 324                 dma_release_channel(chan);
 325                 /* Free the Tx channel too */
 326                 chan = host->chan_tx;
 327                 if (chan) {
 328                         host->chan_tx = NULL;
 329                         dma_release_channel(chan);
 330                 }
 331                 dev_warn(&host->pd->dev,
 332                          "DMA failed: %d, falling back to PIO\n", ret);
 333                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 334         }
 335
 336         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 337                 desc, cookie, data->sg_len);
 338 }
 339
 340 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 341 {
 342         struct mmc_data *data = host->mrq->data;
 343         struct scatterlist *sg = data->sg;
 344         struct dma_async_tx_descriptor *desc = NULL;
 345         struct dma_chan *chan = host->chan_tx;
 346         dma_cookie_t cookie = -EINVAL;
 347         int ret;
 348
 349         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 350                          DMA_TO_DEVICE);
 351         if (ret > 0) {
 352                 host->dma_active = true;
 353                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 354                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 355         }
 356
 357         if (desc) {
 358                 desc->callback = mmcif_dma_complete;
 359                 desc->callback_param = host;
 360                 cookie = dmaengine_submit(desc);
 361                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 362                 dma_async_issue_pending(chan);
 363         }
 364         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 365                 __func__, data->sg_len, ret, cookie);
 366
 367         if (!desc) {
 368                 /* DMA failed, fall back to PIO */
 369                 if (ret >= 0)
 370                         ret = -EIO;
 371                 host->chan_tx = NULL;
 372                 host->dma_active = false;
 373                 dma_release_channel(chan);
 374                 /* Free the Rx channel too */
 375                 chan = host->chan_rx;
 376                 if (chan) {
 377                         host->chan_rx = NULL;
 378                         dma_release_channel(chan);
 379                 }
 380                 dev_warn(&host->pd->dev,
 381                          "DMA failed: %d, falling back to PIO\n", ret);
 382                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 383         }
 384
 385         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 386                 desc, cookie);
 387 }
 388
 389 static struct dma_chan *
 390 sh_mmcif_request_dma_one(struct sh_mmcif_host *host,
 391                          struct sh_mmcif_plat_data *pdata,
 392                          enum dma_transfer_direction direction)
 393 {
 394         struct dma_slave_config cfg = { 0, };
 395         struct dma_chan *chan;
 396         void *slave_data = NULL;
 397         struct resource *res;
 398         dma_cap_mask_t mask;
 399         int ret;
 400
 401         dma_cap_zero(mask);
 402         dma_cap_set(DMA_SLAVE, mask);
 403
 404         if (pdata)
 405                 slave_data = direction == DMA_MEM_TO_DEV ?
 406                         (void *)pdata->slave_id_tx :
 407                         (void *)pdata->slave_id_rx;
 408
 409         chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
 410                                 slave_data, &host->pd->dev,
 411                                 direction == DMA_MEM_TO_DEV ? "tx" : "rx");
 412
 413         dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__,
 414                 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan);
 415
 416         if (!chan)
 417                 return NULL;
 418
 419         res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
 420
 421         cfg.direction = direction;
 422
 423         if (direction == DMA_DEV_TO_MEM) {
 424                 cfg.src_addr = res->start + MMCIF_CE_DATA;
 425                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 426         } else {
 427                 cfg.dst_addr = res->start + MMCIF_CE_DATA;
 428                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 429         }
 430
 431         ret = dmaengine_slave_config(chan, &cfg);
 432         if (ret < 0) {
 433                 dma_release_channel(chan);
 434                 return NULL;
 435         }
 436
 437         return chan;
 438 }
 439
 440 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 441                                  struct sh_mmcif_plat_data *pdata)
 442 {
 443         host->dma_active = false;
 444
 445         if (pdata) {
 446                 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
 447                         return;
 448         } else if (!host->pd->dev.of_node) {
 449                 return;
 450         }
 451
 452         /* We can only either use DMA for both Tx and Rx or not use it at all */
 453         host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV);
 454         if (!host->chan_tx)
 455                 return;
 456
 457         host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM);
 458         if (!host->chan_rx) {
 459                 dma_release_channel(host->chan_tx);
 460                 host->chan_tx = NULL;
 461         }
 462 }
 463
 464 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 465 {
 466         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 467         /* Descriptors are freed automatically */
 468         if (host->chan_tx) {
 469                 struct dma_chan *chan = host->chan_tx;
 470                 host->chan_tx = NULL;
 471                 dma_release_channel(chan);
 472         }
 473         if (host->chan_rx) {
 474                 struct dma_chan *chan = host->chan_rx;
 475                 host->chan_rx = NULL;
 476                 dma_release_channel(chan);
 477         }
 478
 479         host->dma_active = false;
 480 }
 481
 482 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 483 {
 484         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 485         bool sup_pclk = p ? p->sup_pclk : false;
 486         unsigned int current_clk = clk_get_rate(host->clk);
 487
 488         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 489         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 490
 491         if (!clk)
 492                 return;
 493         if (sup_pclk && clk == current_clk)
 494                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 495         else
 496                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 497                                 ((fls(DIV_ROUND_UP(current_clk,
 498                                                    clk) - 1) - 1) << 16));
 499
 500         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 501 }
 502
 503 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 504 {
 505         u32 tmp;
 506
 507         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 508
 509         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 510         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 511         if (host->ccs_enable)
 512                 tmp |= SCCSTO_29;
 513         if (host->clk_ctrl2_enable)
 514                 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
 515         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 516                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
 517         /* byte swap on */
 518         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 519 }
 520
 521 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 522 {
 523         u32 state1, state2;
 524         int ret, timeout;
 525
 526         host->sd_error = false;
 527
 528         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 529         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 530         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 531         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 532
 533         if (state1 & STS1_CMDSEQ) {
 534                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 535                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 536                 for (timeout = 10000000; timeout; timeout--) {
 537                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 538                               & STS1_CMDSEQ))
 539                                 break;
 540                         mdelay(1);
 541                 }
 542                 if (!timeout) {
 543                         dev_err(&host->pd->dev,
 544                                 "Forced end of command sequence timeout err\n");
 545                         return -EIO;
 546                 }
 547                 sh_mmcif_sync_reset(host);
 548                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 549                 return -EIO;
 550         }
 551
 552         if (state2 & STS2_CRC_ERR) {
 553                 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n",
 554                         host->state, host->wait_for);
 555                 ret = -EIO;
 556         } else if (state2 & STS2_TIMEOUT_ERR) {
 557                 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n",
 558                         host->state, host->wait_for);
 559                 ret = -ETIMEDOUT;
 560         } else {
 561                 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n",
 562                         host->state, host->wait_for);
 563                 ret = -EIO;
 564         }
 565         return ret;
 566 }
 567
 568 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 569 {
 570         struct mmc_data *data = host->mrq->data;
 571
 572         host->sg_blkidx += host->blocksize;
 573
 574         /* data->sg->length must be a multiple of host->blocksize? */
 575         BUG_ON(host->sg_blkidx > data->sg->length);
 576
 577         if (host->sg_blkidx == data->sg->length) {
 578                 host->sg_blkidx = 0;
 579                 if (++host->sg_idx < data->sg_len)
 580                         host->pio_ptr = sg_virt(++data->sg);
 581         } else {
 582                 host->pio_ptr = p;
 583         }
 584
 585         return host->sg_idx != data->sg_len;
 586 }
 587
 588 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 589                                  struct mmc_request *mrq)
 590 {
 591         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 592                            BLOCK_SIZE_MASK) + 3;
 593
 594         host->wait_for = MMCIF_WAIT_FOR_READ;
 595
 596         /* buf read enable */
 597         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 598 }
 599
 600 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 601 {
 602         struct mmc_data *data = host->mrq->data;
 603         u32 *p = sg_virt(data->sg);
 604         int i;
 605
 606         if (host->sd_error) {
 607                 data->error = sh_mmcif_error_manage(host);
 608                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 609                 return false;
 610         }
 611
 612         for (i = 0; i < host->blocksize / 4; i++)
 613                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 614
 615         /* buffer read end */
 616         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 617         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 618
 619         return true;
 620 }
 621
 622 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 623                                 struct mmc_request *mrq)
 624 {
 625         struct mmc_data *data = mrq->data;
 626
 627         if (!data->sg_len || !data->sg->length)
 628                 return;
 629
 630         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 631                 BLOCK_SIZE_MASK;
 632
 633         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 634         host->sg_idx = 0;
 635         host->sg_blkidx = 0;
 636         host->pio_ptr = sg_virt(data->sg);
 637
 638         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 639 }
 640
 641 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 642 {
 643         struct mmc_data *data = host->mrq->data;
 644         u32 *p = host->pio_ptr;
 645         int i;
 646
 647         if (host->sd_error) {
 648                 data->error = sh_mmcif_error_manage(host);
 649                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 650                 return false;
 651         }
 652
 653         BUG_ON(!data->sg->length);
 654
 655         for (i = 0; i < host->blocksize / 4; i++)
 656                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 657
 658         if (!sh_mmcif_next_block(host, p))
 659                 return false;
 660
 661         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 662
 663         return true;
 664 }
 665
 666 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 667                                         struct mmc_request *mrq)
 668 {
 669         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 670                            BLOCK_SIZE_MASK) + 3;
 671
 672         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 673
 674         /* buf write enable */
 675         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 676 }
 677
 678 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 679 {
 680         struct mmc_data *data = host->mrq->data;
 681         u32 *p = sg_virt(data->sg);
 682         int i;
 683
 684         if (host->sd_error) {
 685                 data->error = sh_mmcif_error_manage(host);
 686                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 687                 return false;
 688         }
 689
 690         for (i = 0; i < host->blocksize / 4; i++)
 691                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 692
 693         /* buffer write end */
 694         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 695         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 696
 697         return true;
 698 }
 699
 700 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 701                                 struct mmc_request *mrq)
 702 {
 703         struct mmc_data *data = mrq->data;
 704
 705         if (!data->sg_len || !data->sg->length)
 706                 return;
 707
 708         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 709                 BLOCK_SIZE_MASK;
 710
 711         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 712         host->sg_idx = 0;
 713         host->sg_blkidx = 0;
 714         host->pio_ptr = sg_virt(data->sg);
 715
 716         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 717 }
 718
 719 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 720 {
 721         struct mmc_data *data = host->mrq->data;
 722         u32 *p = host->pio_ptr;
 723         int i;
 724
 725         if (host->sd_error) {
 726                 data->error = sh_mmcif_error_manage(host);
 727                 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
 728                 return false;
 729         }
 730
 731         BUG_ON(!data->sg->length);
 732
 733         for (i = 0; i < host->blocksize / 4; i++)
 734                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 735
 736         if (!sh_mmcif_next_block(host, p))
 737                 return false;
 738
 739         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 740
 741         return true;
 742 }
 743
 744 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 745                                                 struct mmc_command *cmd)
 746 {
 747         if (cmd->flags & MMC_RSP_136) {
 748                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 749                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 750                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 751                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 752         } else
 753                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 754 }
 755
 756 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 757                                                 struct mmc_command *cmd)
 758 {
 759         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 760 }
 761
 762 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 763                             struct mmc_request *mrq)
 764 {
 765         struct mmc_data *data = mrq->data;
 766         struct mmc_command *cmd = mrq->cmd;
 767         u32 opc = cmd->opcode;
 768         u32 tmp = 0;
 769
 770         /* Response Type check */
 771         switch (mmc_resp_type(cmd)) {
 772         case MMC_RSP_NONE:
 773                 tmp |= CMD_SET_RTYP_NO;
 774                 break;
 775         case MMC_RSP_R1:
 776         case MMC_RSP_R1B:
 777         case MMC_RSP_R3:
 778                 tmp |= CMD_SET_RTYP_6B;
 779                 break;
 780         case MMC_RSP_R2:
 781                 tmp |= CMD_SET_RTYP_17B;
 782                 break;
 783         default:
 784                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 785                 break;
 786         }
 787         switch (opc) {
 788         /* RBSY */
 789         case MMC_SLEEP_AWAKE:
 790         case MMC_SWITCH:
 791         case MMC_STOP_TRANSMISSION:
 792         case MMC_SET_WRITE_PROT:
 793         case MMC_CLR_WRITE_PROT:
 794         case MMC_ERASE:
 795                 tmp |= CMD_SET_RBSY;
 796                 break;
 797         }
 798         /* WDAT / DATW */
 799         if (data) {
 800                 tmp |= CMD_SET_WDAT;
 801                 switch (host->bus_width) {
 802                 case MMC_BUS_WIDTH_1:
 803                         tmp |= CMD_SET_DATW_1;
 804                         break;
 805                 case MMC_BUS_WIDTH_4:
 806                         tmp |= CMD_SET_DATW_4;
 807                         break;
 808                 case MMC_BUS_WIDTH_8:
 809                         tmp |= CMD_SET_DATW_8;
 810                         break;
 811                 default:
 812                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 813                         break;
 814                 }
 815                 switch (host->timing) {
 816                 case MMC_TIMING_MMC_DDR52:
 817                         /*
 818                          * MMC core will only set this timing, if the host
 819                          * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
 820                          * capability. MMCIF implementations with this
 821                          * capability, e.g. sh73a0, will have to set it
 822                          * in their platform data.
 823                          */
 824                         tmp |= CMD_SET_DARS;
 825                         break;
 826                 }
 827         }
 828         /* DWEN */
 829         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 830                 tmp |= CMD_SET_DWEN;
 831         /* CMLTE/CMD12EN */
 832         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 833                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 834                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 835                                 data->blocks << 16);
 836         }
 837         /* RIDXC[1:0] check bits */
 838         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 839             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 840                 tmp |= CMD_SET_RIDXC_BITS;
 841         /* RCRC7C[1:0] check bits */
 842         if (opc == MMC_SEND_OP_COND)
 843                 tmp |= CMD_SET_CRC7C_BITS;
 844         /* RCRC7C[1:0] internal CRC7 */
 845         if (opc == MMC_ALL_SEND_CID ||
 846                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 847                 tmp |= CMD_SET_CRC7C_INTERNAL;
 848
 849         return (opc << 24) | tmp;
 850 }
 851
 852 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 853                                struct mmc_request *mrq, u32 opc)
 854 {
 855         switch (opc) {
 856         case MMC_READ_MULTIPLE_BLOCK:
 857                 sh_mmcif_multi_read(host, mrq);
 858                 return 0;
 859         case MMC_WRITE_MULTIPLE_BLOCK:
 860                 sh_mmcif_multi_write(host, mrq);
 861                 return 0;
 862         case MMC_WRITE_BLOCK:
 863                 sh_mmcif_single_write(host, mrq);
 864                 return 0;
 865         case MMC_READ_SINGLE_BLOCK:
 866         case MMC_SEND_EXT_CSD:
 867                 sh_mmcif_single_read(host, mrq);
 868                 return 0;
 869         default:
 870                 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc);
 871                 return -EINVAL;
 872         }
 873 }
 874
 875 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 876                                struct mmc_request *mrq)
 877 {
 878         struct mmc_command *cmd = mrq->cmd;
 879         u32 opc = cmd->opcode;
 880         u32 mask;
 881         unsigned long flags;
 882
 883         switch (opc) {
 884         /* response busy check */
 885         case MMC_SLEEP_AWAKE:
 886         case MMC_SWITCH:
 887         case MMC_STOP_TRANSMISSION:
 888         case MMC_SET_WRITE_PROT:
 889         case MMC_CLR_WRITE_PROT:
 890         case MMC_ERASE:
 891                 mask = MASK_START_CMD | MASK_MRBSYE;
 892                 break;
 893         default:
 894                 mask = MASK_START_CMD | MASK_MCRSPE;
 895                 break;
 896         }
 897
 898         if (host->ccs_enable)
 899                 mask |= MASK_MCCSTO;
 900
 901         if (mrq->data) {
 902                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 903                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 904                                 mrq->data->blksz);
 905         }
 906         opc = sh_mmcif_set_cmd(host, mrq);
 907
 908         if (host->ccs_enable)
 909                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 910         else
 911                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
 912         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 913         /* set arg */
 914         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 915         /* set cmd */
 916         spin_lock_irqsave(&host->lock, flags);
 917         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 918
 919         host->wait_for = MMCIF_WAIT_FOR_CMD;
 920         schedule_delayed_work(&host->timeout_work, host->timeout);
 921         spin_unlock_irqrestore(&host->lock, flags);
 922 }
 923
 924 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 925                               struct mmc_request *mrq)
 926 {
 927         switch (mrq->cmd->opcode) {
 928         case MMC_READ_MULTIPLE_BLOCK:
 929                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 930                 break;
 931         case MMC_WRITE_MULTIPLE_BLOCK:
 932                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 933                 break;
 934         default:
 935                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 936                 mrq->stop->error = sh_mmcif_error_manage(host);
 937                 return;
 938         }
 939
 940         host->wait_for = MMCIF_WAIT_FOR_STOP;
 941 }
 942
 943 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 944 {
 945         struct sh_mmcif_host *host = mmc_priv(mmc);
 946         unsigned long flags;
 947
 948         spin_lock_irqsave(&host->lock, flags);
 949         if (host->state != STATE_IDLE) {
 950                 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
 951                 spin_unlock_irqrestore(&host->lock, flags);
 952                 mrq->cmd->error = -EAGAIN;
 953                 mmc_request_done(mmc, mrq);
 954                 return;
 955         }
 956
 957         host->state = STATE_REQUEST;
 958         spin_unlock_irqrestore(&host->lock, flags);
 959
 960         switch (mrq->cmd->opcode) {
 961         /* MMCIF does not support SD/SDIO command */
 962         case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
 963         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 964                 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
 965                         break;
 966         case MMC_APP_CMD:
 967         case SD_IO_RW_DIRECT:
 968                 host->state = STATE_IDLE;
 969                 mrq->cmd->error = -ETIMEDOUT;
 970                 mmc_request_done(mmc, mrq);
 971                 return;
 972         default:
 973                 break;
 974         }
 975
 976         host->mrq = mrq;
 977
 978         sh_mmcif_start_cmd(host, mrq);
 979 }
 980
 981 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
 982 {
 983         int ret = clk_prepare_enable(host->clk);
 984
 985         if (!ret) {
 986                 unsigned int clk = clk_get_rate(host->clk);
 987
 988                 host->mmc->f_max = clk / 2;
 989                 host->mmc->f_min = clk / 512;
 990         }
 991
 992         return ret;
 993 }
 994
 995 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
 996 {
 997         struct mmc_host *mmc = host->mmc;
 998
 999         if (!IS_ERR(mmc->supply.vmmc))
1000                 /* Errors ignored... */
1001                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1002                                       ios->power_mode ? ios->vdd : 0);
1003 }
1004
1005 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1006 {
1007         struct sh_mmcif_host *host = mmc_priv(mmc);
1008         unsigned long flags;
1009
1010         spin_lock_irqsave(&host->lock, flags);
1011         if (host->state != STATE_IDLE) {
1012                 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
1013                 spin_unlock_irqrestore(&host->lock, flags);
1014                 return;
1015         }
1016
1017         host->state = STATE_IOS;
1018         spin_unlock_irqrestore(&host->lock, flags);
1019
1020         if (ios->power_mode == MMC_POWER_UP) {
1021                 if (!host->card_present) {
1022                         /* See if we also get DMA */
1023                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
1024                         host->card_present = true;
1025                 }
1026                 sh_mmcif_set_power(host, ios);
1027         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
1028                 /* clock stop */
1029                 sh_mmcif_clock_control(host, 0);
1030                 if (ios->power_mode == MMC_POWER_OFF) {
1031                         if (host->card_present) {
1032                                 sh_mmcif_release_dma(host);
1033                                 host->card_present = false;
1034                         }
1035                 }
1036                 if (host->power) {
1037                         pm_runtime_put_sync(&host->pd->dev);
1038                         clk_disable_unprepare(host->clk);
1039                         host->power = false;
1040                         if (ios->power_mode == MMC_POWER_OFF)
1041                                 sh_mmcif_set_power(host, ios);
1042                 }
1043                 host->state = STATE_IDLE;
1044                 return;
1045         }
1046
1047         if (ios->clock) {
1048                 if (!host->power) {
1049                         sh_mmcif_clk_update(host);
1050                         pm_runtime_get_sync(&host->pd->dev);
1051                         host->power = true;
1052                         sh_mmcif_sync_reset(host);
1053                 }
1054                 sh_mmcif_clock_control(host, ios->clock);
1055         }
1056
1057         host->timing = ios->timing;
1058         host->bus_width = ios->bus_width;
1059         host->state = STATE_IDLE;
1060 }
1061
1062 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1063 {
1064         struct sh_mmcif_host *host = mmc_priv(mmc);
1065         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1066         int ret = mmc_gpio_get_cd(mmc);
1067
1068         if (ret >= 0)
1069                 return ret;
1070
1071         if (!p || !p->get_cd)
1072                 return -ENOSYS;
1073         else
1074                 return p->get_cd(host->pd);
1075 }
1076
1077 static struct mmc_host_ops sh_mmcif_ops = {
1078         .request        = sh_mmcif_request,
1079         .set_ios        = sh_mmcif_set_ios,
1080         .get_cd         = sh_mmcif_get_cd,
1081 };
1082
1083 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1084 {
1085         struct mmc_command *cmd = host->mrq->cmd;
1086         struct mmc_data *data = host->mrq->data;
1087         long time;
1088
1089         if (host->sd_error) {
1090                 switch (cmd->opcode) {
1091                 case MMC_ALL_SEND_CID:
1092                 case MMC_SELECT_CARD:
1093                 case MMC_APP_CMD:
1094                         cmd->error = -ETIMEDOUT;
1095                         break;
1096                 default:
1097                         cmd->error = sh_mmcif_error_manage(host);
1098                         break;
1099                 }
1100                 dev_dbg(&host->pd->dev, "CMD%d error %d\n",
1101                         cmd->opcode, cmd->error);
1102                 host->sd_error = false;
1103                 return false;
1104         }
1105         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1106                 cmd->error = 0;
1107                 return false;
1108         }
1109
1110         sh_mmcif_get_response(host, cmd);
1111
1112         if (!data)
1113                 return false;
1114
1115         /*
1116          * Completion can be signalled from DMA callback and error, so, have to
1117          * reset here, before setting .dma_active
1118          */
1119         init_completion(&host->dma_complete);
1120
1121         if (data->flags & MMC_DATA_READ) {
1122                 if (host->chan_rx)
1123                         sh_mmcif_start_dma_rx(host);
1124         } else {
1125                 if (host->chan_tx)
1126                         sh_mmcif_start_dma_tx(host);
1127         }
1128
1129         if (!host->dma_active) {
1130                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1131                 return !data->error;
1132         }
1133
1134         /* Running in the IRQ thread, can sleep */
1135         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1136                                                          host->timeout);
1137
1138         if (data->flags & MMC_DATA_READ)
1139                 dma_unmap_sg(host->chan_rx->device->dev,
1140                              data->sg, data->sg_len,
1141                              DMA_FROM_DEVICE);
1142         else
1143                 dma_unmap_sg(host->chan_tx->device->dev,
1144                              data->sg, data->sg_len,
1145                              DMA_TO_DEVICE);
1146
1147         if (host->sd_error) {
1148                 dev_err(host->mmc->parent,
1149                         "Error IRQ while waiting for DMA completion!\n");
1150                 /* Woken up by an error IRQ: abort DMA */
1151                 data->error = sh_mmcif_error_manage(host);
1152         } else if (!time) {
1153                 dev_err(host->mmc->parent, "DMA timeout!\n");
1154                 data->error = -ETIMEDOUT;
1155         } else if (time < 0) {
1156                 dev_err(host->mmc->parent,
1157                         "wait_for_completion_...() error %ld!\n", time);
1158                 data->error = time;
1159         }
1160         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1161                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1162         host->dma_active = false;
1163
1164         if (data->error) {
1165                 data->bytes_xfered = 0;
1166                 /* Abort DMA */
1167                 if (data->flags & MMC_DATA_READ)
1168                         dmaengine_terminate_all(host->chan_rx);
1169                 else
1170                         dmaengine_terminate_all(host->chan_tx);
1171         }
1172
1173         return false;
1174 }
1175
1176 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1177 {
1178         struct sh_mmcif_host *host = dev_id;
1179         struct mmc_request *mrq;
1180         bool wait = false;
1181         unsigned long flags;
1182         int wait_work;
1183
1184         spin_lock_irqsave(&host->lock, flags);
1185         wait_work = host->wait_for;
1186         spin_unlock_irqrestore(&host->lock, flags);
1187
1188         cancel_delayed_work_sync(&host->timeout_work);
1189
1190         mutex_lock(&host->thread_lock);
1191
1192         mrq = host->mrq;
1193         if (!mrq) {
1194                 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1195                         host->state, host->wait_for);
1196                 mutex_unlock(&host->thread_lock);
1197                 return IRQ_HANDLED;
1198         }
1199
1200         /*
1201          * All handlers return true, if processing continues, and false, if the
1202          * request has to be completed - successfully or not
1203          */
1204         switch (wait_work) {
1205         case MMCIF_WAIT_FOR_REQUEST:
1206                 /* We're too late, the timeout has already kicked in */
1207                 mutex_unlock(&host->thread_lock);
1208                 return IRQ_HANDLED;
1209         case MMCIF_WAIT_FOR_CMD:
1210                 /* Wait for data? */
1211                 wait = sh_mmcif_end_cmd(host);
1212                 break;
1213         case MMCIF_WAIT_FOR_MREAD:
1214                 /* Wait for more data? */
1215                 wait = sh_mmcif_mread_block(host);
1216                 break;
1217         case MMCIF_WAIT_FOR_READ:
1218                 /* Wait for data end? */
1219                 wait = sh_mmcif_read_block(host);
1220                 break;
1221         case MMCIF_WAIT_FOR_MWRITE:
1222                 /* Wait data to write? */
1223                 wait = sh_mmcif_mwrite_block(host);
1224                 break;
1225         case MMCIF_WAIT_FOR_WRITE:
1226                 /* Wait for data end? */
1227                 wait = sh_mmcif_write_block(host);
1228                 break;
1229         case MMCIF_WAIT_FOR_STOP:
1230                 if (host->sd_error) {
1231                         mrq->stop->error = sh_mmcif_error_manage(host);
1232                         dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error);
1233                         break;
1234                 }
1235                 sh_mmcif_get_cmd12response(host, mrq->stop);
1236                 mrq->stop->error = 0;
1237                 break;
1238         case MMCIF_WAIT_FOR_READ_END:
1239         case MMCIF_WAIT_FOR_WRITE_END:
1240                 if (host->sd_error) {
1241                         mrq->data->error = sh_mmcif_error_manage(host);
1242                         dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error);
1243                 }
1244                 break;
1245         default:
1246                 BUG();
1247         }
1248
1249         if (wait) {
1250                 schedule_delayed_work(&host->timeout_work, host->timeout);
1251                 /* Wait for more data */
1252                 mutex_unlock(&host->thread_lock);
1253                 return IRQ_HANDLED;
1254         }
1255
1256         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1257                 struct mmc_data *data = mrq->data;
1258                 if (!mrq->cmd->error && data && !data->error)
1259                         data->bytes_xfered =
1260                                 data->blocks * data->blksz;
1261
1262                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1263                         sh_mmcif_stop_cmd(host, mrq);
1264                         if (!mrq->stop->error) {
1265                                 schedule_delayed_work(&host->timeout_work, host->timeout);
1266                                 mutex_unlock(&host->thread_lock);
1267                                 return IRQ_HANDLED;
1268                         }
1269                 }
1270         }
1271
1272         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1273         host->state = STATE_IDLE;
1274         host->mrq = NULL;
1275         mmc_request_done(host->mmc, mrq);
1276
1277         mutex_unlock(&host->thread_lock);
1278
1279         return IRQ_HANDLED;
1280 }
1281
1282 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1283 {
1284         struct sh_mmcif_host *host = dev_id;
1285         u32 state, mask;
1286
1287         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1288         mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1289         if (host->ccs_enable)
1290                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1291         else
1292                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1293         sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1294
1295         if (state & ~MASK_CLEAN)
1296                 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n",
1297                         state);
1298
1299         if (state & INT_ERR_STS || state & ~INT_ALL) {
1300                 host->sd_error = true;
1301                 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state);
1302         }
1303         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1304                 if (!host->mrq)
1305                         dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state);
1306                 if (!host->dma_active)
1307                         return IRQ_WAKE_THREAD;
1308                 else if (host->sd_error)
1309                         mmcif_dma_complete(host);
1310         } else {
1311                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1312         }
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 static void mmcif_timeout_work(struct work_struct *work)
1318 {
1319         struct delayed_work *d = container_of(work, struct delayed_work, work);
1320         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1321         struct mmc_request *mrq = host->mrq;
1322         unsigned long flags;
1323
1324         if (host->dying)
1325                 /* Don't run after mmc_remove_host() */
1326                 return;
1327
1328         spin_lock_irqsave(&host->lock, flags);
1329         if (host->state == STATE_IDLE) {
1330                 spin_unlock_irqrestore(&host->lock, flags);
1331                 return;
1332         }
1333
1334         dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n",
1335                 host->wait_for, mrq->cmd->opcode);
1336
1337         host->state = STATE_TIMEOUT;
1338         spin_unlock_irqrestore(&host->lock, flags);
1339
1340         /*
1341          * Handle races with cancel_delayed_work(), unless
1342          * cancel_delayed_work_sync() is used
1343          */
1344         switch (host->wait_for) {
1345         case MMCIF_WAIT_FOR_CMD:
1346                 mrq->cmd->error = sh_mmcif_error_manage(host);
1347                 break;
1348         case MMCIF_WAIT_FOR_STOP:
1349                 mrq->stop->error = sh_mmcif_error_manage(host);
1350                 break;
1351         case MMCIF_WAIT_FOR_MREAD:
1352         case MMCIF_WAIT_FOR_MWRITE:
1353         case MMCIF_WAIT_FOR_READ:
1354         case MMCIF_WAIT_FOR_WRITE:
1355         case MMCIF_WAIT_FOR_READ_END:
1356         case MMCIF_WAIT_FOR_WRITE_END:
1357                 mrq->data->error = sh_mmcif_error_manage(host);
1358                 break;
1359         default:
1360                 BUG();
1361         }
1362
1363         host->state = STATE_IDLE;
1364         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1365         host->mrq = NULL;
1366         mmc_request_done(host->mmc, mrq);
1367 }
1368
1369 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1370 {
1371         struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1372         struct mmc_host *mmc = host->mmc;
1373
1374         mmc_regulator_get_supply(mmc);
1375
1376         if (!pd)
1377                 return;
1378
1379         if (!mmc->ocr_avail)
1380                 mmc->ocr_avail = pd->ocr;
1381         else if (pd->ocr)
1382                 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1383 }
1384
1385 static int sh_mmcif_probe(struct platform_device *pdev)
1386 {
1387         int ret = 0, irq[2];
1388         struct mmc_host *mmc;
1389         struct sh_mmcif_host *host;
1390         struct device *dev = &pdev->dev;
1391         struct sh_mmcif_plat_data *pd = dev->platform_data;
1392         struct resource *res;
1393         void __iomem *reg;
1394         const char *name;
1395
1396         irq[0] = platform_get_irq(pdev, 0);
1397         irq[1] = platform_get_irq(pdev, 1);
1398         if (irq[0] < 0) {
1399                 dev_err(dev, "Get irq error\n");
1400                 return -ENXIO;
1401         }
1402
1403         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404         reg = devm_ioremap_resource(dev, res);
1405         if (IS_ERR(reg))
1406                 return PTR_ERR(reg);
1407
1408         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);
1409         if (!mmc)
1410                 return -ENOMEM;
1411
1412         ret = mmc_of_parse(mmc);
1413         if (ret < 0)
1414                 goto err_host;
1415
1416         host            = mmc_priv(mmc);
1417         host->mmc       = mmc;
1418         host->addr      = reg;
1419         host->timeout   = msecs_to_jiffies(10000);
1420         host->ccs_enable = !pd || !pd->ccs_unsupported;
1421         host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1422
1423         host->pd = pdev;
1424
1425         spin_lock_init(&host->lock);
1426
1427         mmc->ops = &sh_mmcif_ops;
1428         sh_mmcif_init_ocr(host);
1429
1430         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1431         if (pd && pd->caps)
1432                 mmc->caps |= pd->caps;
1433         mmc->max_segs = 32;
1434         mmc->max_blk_size = 512;
1435         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1436         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1437         mmc->max_seg_size = mmc->max_req_size;
1438
1439         platform_set_drvdata(pdev, host);
1440
1441         pm_runtime_enable(dev);
1442         host->power = false;
1443
1444         host->clk = devm_clk_get(dev, NULL);
1445         if (IS_ERR(host->clk)) {
1446                 ret = PTR_ERR(host->clk);
1447                 dev_err(dev, "cannot get clock: %d\n", ret);
1448                 goto err_pm;
1449         }
1450         ret = sh_mmcif_clk_update(host);
1451         if (ret < 0)
1452                 goto err_pm;
1453
1454         ret = pm_runtime_resume(dev);
1455         if (ret < 0)
1456                 goto err_clk;
1457
1458         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1459
1460         sh_mmcif_sync_reset(host);
1461         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1462
1463         name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";
1464         ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,
1465                                         sh_mmcif_irqt, 0, name, host);
1466         if (ret) {
1467                 dev_err(dev, "request_irq error (%s)\n", name);
1468                 goto err_clk;
1469         }
1470         if (irq[1] >= 0) {
1471                 ret = devm_request_threaded_irq(dev, irq[1],
1472                                                 sh_mmcif_intr, sh_mmcif_irqt,
1473                                                 0, "sh_mmc:int", host);
1474                 if (ret) {
1475                         dev_err(dev, "request_irq error (sh_mmc:int)\n");
1476                         goto err_clk;
1477                 }
1478         }
1479
1480         if (pd && pd->use_cd_gpio) {
1481                 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1482                 if (ret < 0)
1483                         goto err_clk;
1484         }
1485
1486         mutex_init(&host->thread_lock);
1487
1488         ret = mmc_add_host(mmc);
1489         if (ret < 0)
1490                 goto err_clk;
1491
1492         dev_pm_qos_expose_latency_limit(dev, 100);
1493
1494         dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",
1495                  sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1496                  clk_get_rate(host->clk) / 1000000UL);
1497
1498         clk_disable_unprepare(host->clk);
1499         return ret;
1500
1501 err_clk:
1502         clk_disable_unprepare(host->clk);
1503 err_pm:
1504         pm_runtime_disable(dev);
1505 err_host:
1506         mmc_free_host(mmc);
1507         return ret;
1508 }
1509
1510 static int sh_mmcif_remove(struct platform_device *pdev)
1511 {
1512         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1513
1514         host->dying = true;
1515         clk_prepare_enable(host->clk);
1516         pm_runtime_get_sync(&pdev->dev);
1517
1518         dev_pm_qos_hide_latency_limit(&pdev->dev);
1519
1520         mmc_remove_host(host->mmc);
1521         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1522
1523         /*
1524          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1525          * mmc_remove_host() call above. But swapping order doesn't help either
1526          * (a query on the linux-mmc mailing list didn't bring any replies).
1527          */
1528         cancel_delayed_work_sync(&host->timeout_work);
1529
1530         clk_disable_unprepare(host->clk);
1531         mmc_free_host(host->mmc);
1532         pm_runtime_put_sync(&pdev->dev);
1533         pm_runtime_disable(&pdev->dev);
1534
1535         return 0;
1536 }
1537
1538 #ifdef CONFIG_PM_SLEEP
1539 static int sh_mmcif_suspend(struct device *dev)
1540 {
1541         struct sh_mmcif_host *host = dev_get_drvdata(dev);
1542
1543         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1544
1545         return 0;
1546 }
1547
1548 static int sh_mmcif_resume(struct device *dev)
1549 {
1550         return 0;
1551 }
1552 #endif
1553
1554 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1555         SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1556 };
1557
1558 static struct platform_driver sh_mmcif_driver = {
1559         .probe          = sh_mmcif_probe,
1560         .remove         = sh_mmcif_remove,
1561         .driver         = {
1562                 .name   = DRIVER_NAME,
1563                 .pm     = &sh_mmcif_dev_pm_ops,
1564                 .of_match_table = mmcif_of_match,
1565         },
1566 };
1567
1568 module_platform_driver(sh_mmcif_driver);
1569
1570 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1571 MODULE_LICENSE("GPL");
1572 MODULE_ALIAS("platform:" DRIVER_NAME);
1573 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");