4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
15 * 3. Handle MMC errors better
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/mmc/card.h>
52 #include <linux/mmc/core.h>
53 #include <linux/mmc/host.h>
54 #include <linux/mmc/mmc.h>
55 #include <linux/mmc/sdio.h>
56 #include <linux/mmc/sh_mmcif.h>
57 #include <linux/mmc/slot-gpio.h>
58 #include <linux/mod_devicetable.h>
59 #include <linux/mutex.h>
60 #include <linux/pagemap.h>
61 #include <linux/platform_device.h>
62 #include <linux/pm_qos.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/sh_dma.h>
65 #include <linux/spinlock.h>
66 #include <linux/module.h>
68 #define DRIVER_NAME "sh_mmcif"
69 #define DRIVER_VERSION "2010-04-28"
72 #define CMD_MASK 0x3f000000
73 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
74 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
75 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
76 #define CMD_SET_RBSY (1 << 21) /* R1b */
77 #define CMD_SET_CCSEN (1 << 20)
78 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
79 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
80 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
81 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
82 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
83 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
84 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
85 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
86 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
87 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
88 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
89 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
90 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
91 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
92 #define CMD_SET_CCSH (1 << 5)
93 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
94 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
95 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
96 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
99 #define CMD_CTRL_BREAK (1 << 0)
102 #define BLOCK_SIZE_MASK 0x0000ffff
105 #define INT_CCSDE (1 << 29)
106 #define INT_CMD12DRE (1 << 26)
107 #define INT_CMD12RBE (1 << 25)
108 #define INT_CMD12CRE (1 << 24)
109 #define INT_DTRANE (1 << 23)
110 #define INT_BUFRE (1 << 22)
111 #define INT_BUFWEN (1 << 21)
112 #define INT_BUFREN (1 << 20)
113 #define INT_CCSRCV (1 << 19)
114 #define INT_RBSYE (1 << 17)
115 #define INT_CRSPE (1 << 16)
116 #define INT_CMDVIO (1 << 15)
117 #define INT_BUFVIO (1 << 14)
118 #define INT_WDATERR (1 << 11)
119 #define INT_RDATERR (1 << 10)
120 #define INT_RIDXERR (1 << 9)
121 #define INT_RSPERR (1 << 8)
122 #define INT_CCSTO (1 << 5)
123 #define INT_CRCSTO (1 << 4)
124 #define INT_WDATTO (1 << 3)
125 #define INT_RDATTO (1 << 2)
126 #define INT_RBSYTO (1 << 1)
127 #define INT_RSPTO (1 << 0)
128 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
129 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
130 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
131 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
133 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \
134 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
135 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
137 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
140 #define MASK_ALL 0x00000000
141 #define MASK_MCCSDE (1 << 29)
142 #define MASK_MCMD12DRE (1 << 26)
143 #define MASK_MCMD12RBE (1 << 25)
144 #define MASK_MCMD12CRE (1 << 24)
145 #define MASK_MDTRANE (1 << 23)
146 #define MASK_MBUFRE (1 << 22)
147 #define MASK_MBUFWEN (1 << 21)
148 #define MASK_MBUFREN (1 << 20)
149 #define MASK_MCCSRCV (1 << 19)
150 #define MASK_MRBSYE (1 << 17)
151 #define MASK_MCRSPE (1 << 16)
152 #define MASK_MCMDVIO (1 << 15)
153 #define MASK_MBUFVIO (1 << 14)
154 #define MASK_MWDATERR (1 << 11)
155 #define MASK_MRDATERR (1 << 10)
156 #define MASK_MRIDXERR (1 << 9)
157 #define MASK_MRSPERR (1 << 8)
158 #define MASK_MCCSTO (1 << 5)
159 #define MASK_MCRCSTO (1 << 4)
160 #define MASK_MWDATTO (1 << 3)
161 #define MASK_MRDATTO (1 << 2)
162 #define MASK_MRBSYTO (1 << 1)
163 #define MASK_MRSPTO (1 << 0)
165 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
166 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
167 MASK_MCRCSTO | MASK_MWDATTO | \
168 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
170 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \
171 MASK_MBUFREN | MASK_MBUFWEN | \
172 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \
173 MASK_MCMD12RBE | MASK_MCMD12CRE)
176 #define STS1_CMDSEQ (1 << 31)
179 #define STS2_CRCSTE (1 << 31)
180 #define STS2_CRC16E (1 << 30)
181 #define STS2_AC12CRCE (1 << 29)
182 #define STS2_RSPCRC7E (1 << 28)
183 #define STS2_CRCSTEBE (1 << 27)
184 #define STS2_RDATEBE (1 << 26)
185 #define STS2_AC12REBE (1 << 25)
186 #define STS2_RSPEBE (1 << 24)
187 #define STS2_AC12IDXE (1 << 23)
188 #define STS2_RSPIDXE (1 << 22)
189 #define STS2_CCSTO (1 << 15)
190 #define STS2_RDATTO (1 << 14)
191 #define STS2_DATBSYTO (1 << 13)
192 #define STS2_CRCSTTO (1 << 12)
193 #define STS2_AC12BSYTO (1 << 11)
194 #define STS2_RSPBSYTO (1 << 10)
195 #define STS2_AC12RSPTO (1 << 9)
196 #define STS2_RSPTO (1 << 8)
197 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
198 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
199 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
200 STS2_DATBSYTO | STS2_CRCSTTO | \
201 STS2_AC12BSYTO | STS2_RSPBSYTO | \
202 STS2_AC12RSPTO | STS2_RSPTO)
204 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
205 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
206 #define CLKDEV_INIT 400000 /* 400 KHz */
215 enum mmcif_wait_for {
216 MMCIF_WAIT_FOR_REQUEST,
218 MMCIF_WAIT_FOR_MREAD,
219 MMCIF_WAIT_FOR_MWRITE,
221 MMCIF_WAIT_FOR_WRITE,
222 MMCIF_WAIT_FOR_READ_END,
223 MMCIF_WAIT_FOR_WRITE_END,
227 struct sh_mmcif_host {
228 struct mmc_host *mmc;
229 struct mmc_request *mrq;
230 struct platform_device *pd;
233 unsigned char timing;
239 spinlock_t lock; /* protect sh_mmcif_host::state */
240 enum mmcif_state state;
241 enum mmcif_wait_for wait_for;
242 struct delayed_work timeout_work;
248 bool ccs_enable; /* Command Completion Signal support */
249 bool clk_ctrl2_enable;
250 struct mutex thread_lock;
253 struct dma_chan *chan_rx;
254 struct dma_chan *chan_tx;
255 struct completion dma_complete;
259 static const struct of_device_id mmcif_of_match[] = {
260 { .compatible = "renesas,sh-mmcif" },
263 MODULE_DEVICE_TABLE(of, mmcif_of_match);
265 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
266 unsigned int reg, u32 val)
268 writel(val | readl(host->addr + reg), host->addr + reg);
271 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
272 unsigned int reg, u32 val)
274 writel(~val & readl(host->addr + reg), host->addr + reg);
277 static void mmcif_dma_complete(void *arg)
279 struct sh_mmcif_host *host = arg;
280 struct mmc_request *mrq = host->mrq;
282 dev_dbg(&host->pd->dev, "Command completed\n");
284 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
285 dev_name(&host->pd->dev)))
288 complete(&host->dma_complete);
291 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
293 struct mmc_data *data = host->mrq->data;
294 struct scatterlist *sg = data->sg;
295 struct dma_async_tx_descriptor *desc = NULL;
296 struct dma_chan *chan = host->chan_rx;
297 dma_cookie_t cookie = -EINVAL;
300 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
303 host->dma_active = true;
304 desc = dmaengine_prep_slave_sg(chan, sg, ret,
305 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
309 desc->callback = mmcif_dma_complete;
310 desc->callback_param = host;
311 cookie = dmaengine_submit(desc);
312 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
313 dma_async_issue_pending(chan);
315 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
316 __func__, data->sg_len, ret, cookie);
319 /* DMA failed, fall back to PIO */
322 host->chan_rx = NULL;
323 host->dma_active = false;
324 dma_release_channel(chan);
325 /* Free the Tx channel too */
326 chan = host->chan_tx;
328 host->chan_tx = NULL;
329 dma_release_channel(chan);
331 dev_warn(&host->pd->dev,
332 "DMA failed: %d, falling back to PIO\n", ret);
333 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
336 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
337 desc, cookie, data->sg_len);
340 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
342 struct mmc_data *data = host->mrq->data;
343 struct scatterlist *sg = data->sg;
344 struct dma_async_tx_descriptor *desc = NULL;
345 struct dma_chan *chan = host->chan_tx;
346 dma_cookie_t cookie = -EINVAL;
349 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
352 host->dma_active = true;
353 desc = dmaengine_prep_slave_sg(chan, sg, ret,
354 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
358 desc->callback = mmcif_dma_complete;
359 desc->callback_param = host;
360 cookie = dmaengine_submit(desc);
361 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
362 dma_async_issue_pending(chan);
364 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
365 __func__, data->sg_len, ret, cookie);
368 /* DMA failed, fall back to PIO */
371 host->chan_tx = NULL;
372 host->dma_active = false;
373 dma_release_channel(chan);
374 /* Free the Rx channel too */
375 chan = host->chan_rx;
377 host->chan_rx = NULL;
378 dma_release_channel(chan);
380 dev_warn(&host->pd->dev,
381 "DMA failed: %d, falling back to PIO\n", ret);
382 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
385 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
389 static struct dma_chan *
390 sh_mmcif_request_dma_one(struct sh_mmcif_host *host,
391 struct sh_mmcif_plat_data *pdata,
392 enum dma_transfer_direction direction)
394 struct dma_slave_config cfg = { 0, };
395 struct dma_chan *chan;
396 void *slave_data = NULL;
397 struct resource *res;
402 dma_cap_set(DMA_SLAVE, mask);
405 slave_data = direction == DMA_MEM_TO_DEV ?
406 (void *)pdata->slave_id_tx :
407 (void *)pdata->slave_id_rx;
409 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
410 slave_data, &host->pd->dev,
411 direction == DMA_MEM_TO_DEV ? "tx" : "rx");
413 dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__,
414 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan);
419 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
421 cfg.direction = direction;
423 if (direction == DMA_DEV_TO_MEM) {
424 cfg.src_addr = res->start + MMCIF_CE_DATA;
425 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427 cfg.dst_addr = res->start + MMCIF_CE_DATA;
428 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
431 ret = dmaengine_slave_config(chan, &cfg);
433 dma_release_channel(chan);
440 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
441 struct sh_mmcif_plat_data *pdata)
443 host->dma_active = false;
446 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
448 } else if (!host->pd->dev.of_node) {
452 /* We can only either use DMA for both Tx and Rx or not use it at all */
453 host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV);
457 host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM);
458 if (!host->chan_rx) {
459 dma_release_channel(host->chan_tx);
460 host->chan_tx = NULL;
464 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
466 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
467 /* Descriptors are freed automatically */
469 struct dma_chan *chan = host->chan_tx;
470 host->chan_tx = NULL;
471 dma_release_channel(chan);
474 struct dma_chan *chan = host->chan_rx;
475 host->chan_rx = NULL;
476 dma_release_channel(chan);
479 host->dma_active = false;
482 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
484 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
485 bool sup_pclk = p ? p->sup_pclk : false;
486 unsigned int current_clk = clk_get_rate(host->clk);
488 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
489 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
493 if (sup_pclk && clk == current_clk)
494 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
496 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
497 ((fls(DIV_ROUND_UP(current_clk,
498 clk) - 1) - 1) << 16));
500 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
503 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
507 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
509 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
510 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
511 if (host->ccs_enable)
513 if (host->clk_ctrl2_enable)
514 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
515 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
516 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
518 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
521 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
526 host->sd_error = false;
528 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
529 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
530 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
531 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
533 if (state1 & STS1_CMDSEQ) {
534 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
535 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
536 for (timeout = 10000000; timeout; timeout--) {
537 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
543 dev_err(&host->pd->dev,
544 "Forced end of command sequence timeout err\n");
547 sh_mmcif_sync_reset(host);
548 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
552 if (state2 & STS2_CRC_ERR) {
553 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n",
554 host->state, host->wait_for);
556 } else if (state2 & STS2_TIMEOUT_ERR) {
557 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n",
558 host->state, host->wait_for);
561 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n",
562 host->state, host->wait_for);
568 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
570 struct mmc_data *data = host->mrq->data;
572 host->sg_blkidx += host->blocksize;
574 /* data->sg->length must be a multiple of host->blocksize? */
575 BUG_ON(host->sg_blkidx > data->sg->length);
577 if (host->sg_blkidx == data->sg->length) {
579 if (++host->sg_idx < data->sg_len)
580 host->pio_ptr = sg_virt(++data->sg);
585 return host->sg_idx != data->sg_len;
588 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
589 struct mmc_request *mrq)
591 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
592 BLOCK_SIZE_MASK) + 3;
594 host->wait_for = MMCIF_WAIT_FOR_READ;
596 /* buf read enable */
597 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
600 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
602 struct mmc_data *data = host->mrq->data;
603 u32 *p = sg_virt(data->sg);
606 if (host->sd_error) {
607 data->error = sh_mmcif_error_manage(host);
608 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
612 for (i = 0; i < host->blocksize / 4; i++)
613 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
615 /* buffer read end */
616 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
617 host->wait_for = MMCIF_WAIT_FOR_READ_END;
622 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
623 struct mmc_request *mrq)
625 struct mmc_data *data = mrq->data;
627 if (!data->sg_len || !data->sg->length)
630 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
633 host->wait_for = MMCIF_WAIT_FOR_MREAD;
636 host->pio_ptr = sg_virt(data->sg);
638 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
641 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
643 struct mmc_data *data = host->mrq->data;
644 u32 *p = host->pio_ptr;
647 if (host->sd_error) {
648 data->error = sh_mmcif_error_manage(host);
649 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
653 BUG_ON(!data->sg->length);
655 for (i = 0; i < host->blocksize / 4; i++)
656 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
658 if (!sh_mmcif_next_block(host, p))
661 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
666 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
667 struct mmc_request *mrq)
669 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
670 BLOCK_SIZE_MASK) + 3;
672 host->wait_for = MMCIF_WAIT_FOR_WRITE;
674 /* buf write enable */
675 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
678 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
680 struct mmc_data *data = host->mrq->data;
681 u32 *p = sg_virt(data->sg);
684 if (host->sd_error) {
685 data->error = sh_mmcif_error_manage(host);
686 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
690 for (i = 0; i < host->blocksize / 4; i++)
691 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
693 /* buffer write end */
694 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
695 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
700 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
701 struct mmc_request *mrq)
703 struct mmc_data *data = mrq->data;
705 if (!data->sg_len || !data->sg->length)
708 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
711 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
714 host->pio_ptr = sg_virt(data->sg);
716 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
719 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
721 struct mmc_data *data = host->mrq->data;
722 u32 *p = host->pio_ptr;
725 if (host->sd_error) {
726 data->error = sh_mmcif_error_manage(host);
727 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
731 BUG_ON(!data->sg->length);
733 for (i = 0; i < host->blocksize / 4; i++)
734 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
736 if (!sh_mmcif_next_block(host, p))
739 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
744 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
745 struct mmc_command *cmd)
747 if (cmd->flags & MMC_RSP_136) {
748 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
749 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
750 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
751 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
753 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
756 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
757 struct mmc_command *cmd)
759 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
762 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
763 struct mmc_request *mrq)
765 struct mmc_data *data = mrq->data;
766 struct mmc_command *cmd = mrq->cmd;
767 u32 opc = cmd->opcode;
770 /* Response Type check */
771 switch (mmc_resp_type(cmd)) {
773 tmp |= CMD_SET_RTYP_NO;
778 tmp |= CMD_SET_RTYP_6B;
781 tmp |= CMD_SET_RTYP_17B;
784 dev_err(&host->pd->dev, "Unsupported response type.\n");
789 case MMC_SLEEP_AWAKE:
791 case MMC_STOP_TRANSMISSION:
792 case MMC_SET_WRITE_PROT:
793 case MMC_CLR_WRITE_PROT:
801 switch (host->bus_width) {
802 case MMC_BUS_WIDTH_1:
803 tmp |= CMD_SET_DATW_1;
805 case MMC_BUS_WIDTH_4:
806 tmp |= CMD_SET_DATW_4;
808 case MMC_BUS_WIDTH_8:
809 tmp |= CMD_SET_DATW_8;
812 dev_err(&host->pd->dev, "Unsupported bus width.\n");
815 switch (host->timing) {
816 case MMC_TIMING_MMC_DDR52:
818 * MMC core will only set this timing, if the host
819 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
820 * capability. MMCIF implementations with this
821 * capability, e.g. sh73a0, will have to set it
822 * in their platform data.
829 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
832 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
833 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
834 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
837 /* RIDXC[1:0] check bits */
838 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
839 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
840 tmp |= CMD_SET_RIDXC_BITS;
841 /* RCRC7C[1:0] check bits */
842 if (opc == MMC_SEND_OP_COND)
843 tmp |= CMD_SET_CRC7C_BITS;
844 /* RCRC7C[1:0] internal CRC7 */
845 if (opc == MMC_ALL_SEND_CID ||
846 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
847 tmp |= CMD_SET_CRC7C_INTERNAL;
849 return (opc << 24) | tmp;
852 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
853 struct mmc_request *mrq, u32 opc)
856 case MMC_READ_MULTIPLE_BLOCK:
857 sh_mmcif_multi_read(host, mrq);
859 case MMC_WRITE_MULTIPLE_BLOCK:
860 sh_mmcif_multi_write(host, mrq);
862 case MMC_WRITE_BLOCK:
863 sh_mmcif_single_write(host, mrq);
865 case MMC_READ_SINGLE_BLOCK:
866 case MMC_SEND_EXT_CSD:
867 sh_mmcif_single_read(host, mrq);
870 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc);
875 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
876 struct mmc_request *mrq)
878 struct mmc_command *cmd = mrq->cmd;
879 u32 opc = cmd->opcode;
884 /* response busy check */
885 case MMC_SLEEP_AWAKE:
887 case MMC_STOP_TRANSMISSION:
888 case MMC_SET_WRITE_PROT:
889 case MMC_CLR_WRITE_PROT:
891 mask = MASK_START_CMD | MASK_MRBSYE;
894 mask = MASK_START_CMD | MASK_MCRSPE;
898 if (host->ccs_enable)
902 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
903 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
906 opc = sh_mmcif_set_cmd(host, mrq);
908 if (host->ccs_enable)
909 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
911 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
912 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
914 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
916 spin_lock_irqsave(&host->lock, flags);
917 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
919 host->wait_for = MMCIF_WAIT_FOR_CMD;
920 schedule_delayed_work(&host->timeout_work, host->timeout);
921 spin_unlock_irqrestore(&host->lock, flags);
924 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
925 struct mmc_request *mrq)
927 switch (mrq->cmd->opcode) {
928 case MMC_READ_MULTIPLE_BLOCK:
929 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
931 case MMC_WRITE_MULTIPLE_BLOCK:
932 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
935 dev_err(&host->pd->dev, "unsupported stop cmd\n");
936 mrq->stop->error = sh_mmcif_error_manage(host);
940 host->wait_for = MMCIF_WAIT_FOR_STOP;
943 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
945 struct sh_mmcif_host *host = mmc_priv(mmc);
948 spin_lock_irqsave(&host->lock, flags);
949 if (host->state != STATE_IDLE) {
950 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
951 spin_unlock_irqrestore(&host->lock, flags);
952 mrq->cmd->error = -EAGAIN;
953 mmc_request_done(mmc, mrq);
957 host->state = STATE_REQUEST;
958 spin_unlock_irqrestore(&host->lock, flags);
960 switch (mrq->cmd->opcode) {
961 /* MMCIF does not support SD/SDIO command */
962 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
963 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
964 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
967 case SD_IO_RW_DIRECT:
968 host->state = STATE_IDLE;
969 mrq->cmd->error = -ETIMEDOUT;
970 mmc_request_done(mmc, mrq);
978 sh_mmcif_start_cmd(host, mrq);
981 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)
983 unsigned int clk = clk_get_rate(host->clk);
985 host->mmc->f_max = clk / 2;
986 host->mmc->f_min = clk / 512;
989 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
991 struct mmc_host *mmc = host->mmc;
993 if (!IS_ERR(mmc->supply.vmmc))
994 /* Errors ignored... */
995 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
996 ios->power_mode ? ios->vdd : 0);
999 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1001 struct sh_mmcif_host *host = mmc_priv(mmc);
1002 unsigned long flags;
1004 spin_lock_irqsave(&host->lock, flags);
1005 if (host->state != STATE_IDLE) {
1006 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
1007 spin_unlock_irqrestore(&host->lock, flags);
1011 host->state = STATE_IOS;
1012 spin_unlock_irqrestore(&host->lock, flags);
1014 if (ios->power_mode == MMC_POWER_UP) {
1015 if (!host->card_present) {
1016 /* See if we also get DMA */
1017 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
1018 host->card_present = true;
1020 sh_mmcif_set_power(host, ios);
1021 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
1023 sh_mmcif_clock_control(host, 0);
1024 if (ios->power_mode == MMC_POWER_OFF) {
1025 if (host->card_present) {
1026 sh_mmcif_release_dma(host);
1027 host->card_present = false;
1031 pm_runtime_put_sync(&host->pd->dev);
1032 clk_disable_unprepare(host->clk);
1033 host->power = false;
1034 if (ios->power_mode == MMC_POWER_OFF)
1035 sh_mmcif_set_power(host, ios);
1037 host->state = STATE_IDLE;
1043 clk_prepare_enable(host->clk);
1045 pm_runtime_get_sync(&host->pd->dev);
1047 sh_mmcif_sync_reset(host);
1049 sh_mmcif_clock_control(host, ios->clock);
1052 host->timing = ios->timing;
1053 host->bus_width = ios->bus_width;
1054 host->state = STATE_IDLE;
1057 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1059 struct sh_mmcif_host *host = mmc_priv(mmc);
1060 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1061 int ret = mmc_gpio_get_cd(mmc);
1066 if (!p || !p->get_cd)
1069 return p->get_cd(host->pd);
1072 static struct mmc_host_ops sh_mmcif_ops = {
1073 .request = sh_mmcif_request,
1074 .set_ios = sh_mmcif_set_ios,
1075 .get_cd = sh_mmcif_get_cd,
1078 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1080 struct mmc_command *cmd = host->mrq->cmd;
1081 struct mmc_data *data = host->mrq->data;
1084 if (host->sd_error) {
1085 switch (cmd->opcode) {
1086 case MMC_ALL_SEND_CID:
1087 case MMC_SELECT_CARD:
1089 cmd->error = -ETIMEDOUT;
1092 cmd->error = sh_mmcif_error_manage(host);
1095 dev_dbg(&host->pd->dev, "CMD%d error %d\n",
1096 cmd->opcode, cmd->error);
1097 host->sd_error = false;
1100 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1105 sh_mmcif_get_response(host, cmd);
1111 * Completion can be signalled from DMA callback and error, so, have to
1112 * reset here, before setting .dma_active
1114 init_completion(&host->dma_complete);
1116 if (data->flags & MMC_DATA_READ) {
1118 sh_mmcif_start_dma_rx(host);
1121 sh_mmcif_start_dma_tx(host);
1124 if (!host->dma_active) {
1125 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1126 return !data->error;
1129 /* Running in the IRQ thread, can sleep */
1130 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1133 if (data->flags & MMC_DATA_READ)
1134 dma_unmap_sg(host->chan_rx->device->dev,
1135 data->sg, data->sg_len,
1138 dma_unmap_sg(host->chan_tx->device->dev,
1139 data->sg, data->sg_len,
1142 if (host->sd_error) {
1143 dev_err(host->mmc->parent,
1144 "Error IRQ while waiting for DMA completion!\n");
1145 /* Woken up by an error IRQ: abort DMA */
1146 data->error = sh_mmcif_error_manage(host);
1148 dev_err(host->mmc->parent, "DMA timeout!\n");
1149 data->error = -ETIMEDOUT;
1150 } else if (time < 0) {
1151 dev_err(host->mmc->parent,
1152 "wait_for_completion_...() error %ld!\n", time);
1155 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1156 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1157 host->dma_active = false;
1160 data->bytes_xfered = 0;
1162 if (data->flags & MMC_DATA_READ)
1163 dmaengine_terminate_all(host->chan_rx);
1165 dmaengine_terminate_all(host->chan_tx);
1171 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1173 struct sh_mmcif_host *host = dev_id;
1174 struct mmc_request *mrq;
1176 unsigned long flags;
1179 spin_lock_irqsave(&host->lock, flags);
1180 wait_work = host->wait_for;
1181 spin_unlock_irqrestore(&host->lock, flags);
1183 cancel_delayed_work_sync(&host->timeout_work);
1185 mutex_lock(&host->thread_lock);
1189 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1190 host->state, host->wait_for);
1191 mutex_unlock(&host->thread_lock);
1196 * All handlers return true, if processing continues, and false, if the
1197 * request has to be completed - successfully or not
1199 switch (wait_work) {
1200 case MMCIF_WAIT_FOR_REQUEST:
1201 /* We're too late, the timeout has already kicked in */
1202 mutex_unlock(&host->thread_lock);
1204 case MMCIF_WAIT_FOR_CMD:
1205 /* Wait for data? */
1206 wait = sh_mmcif_end_cmd(host);
1208 case MMCIF_WAIT_FOR_MREAD:
1209 /* Wait for more data? */
1210 wait = sh_mmcif_mread_block(host);
1212 case MMCIF_WAIT_FOR_READ:
1213 /* Wait for data end? */
1214 wait = sh_mmcif_read_block(host);
1216 case MMCIF_WAIT_FOR_MWRITE:
1217 /* Wait data to write? */
1218 wait = sh_mmcif_mwrite_block(host);
1220 case MMCIF_WAIT_FOR_WRITE:
1221 /* Wait for data end? */
1222 wait = sh_mmcif_write_block(host);
1224 case MMCIF_WAIT_FOR_STOP:
1225 if (host->sd_error) {
1226 mrq->stop->error = sh_mmcif_error_manage(host);
1227 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error);
1230 sh_mmcif_get_cmd12response(host, mrq->stop);
1231 mrq->stop->error = 0;
1233 case MMCIF_WAIT_FOR_READ_END:
1234 case MMCIF_WAIT_FOR_WRITE_END:
1235 if (host->sd_error) {
1236 mrq->data->error = sh_mmcif_error_manage(host);
1237 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error);
1245 schedule_delayed_work(&host->timeout_work, host->timeout);
1246 /* Wait for more data */
1247 mutex_unlock(&host->thread_lock);
1251 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1252 struct mmc_data *data = mrq->data;
1253 if (!mrq->cmd->error && data && !data->error)
1254 data->bytes_xfered =
1255 data->blocks * data->blksz;
1257 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1258 sh_mmcif_stop_cmd(host, mrq);
1259 if (!mrq->stop->error) {
1260 schedule_delayed_work(&host->timeout_work, host->timeout);
1261 mutex_unlock(&host->thread_lock);
1267 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1268 host->state = STATE_IDLE;
1270 mmc_request_done(host->mmc, mrq);
1272 mutex_unlock(&host->thread_lock);
1277 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1279 struct sh_mmcif_host *host = dev_id;
1282 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1283 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1284 if (host->ccs_enable)
1285 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1287 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1288 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1290 if (state & ~MASK_CLEAN)
1291 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n",
1294 if (state & INT_ERR_STS || state & ~INT_ALL) {
1295 host->sd_error = true;
1296 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state);
1298 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1300 dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state);
1301 if (!host->dma_active)
1302 return IRQ_WAKE_THREAD;
1303 else if (host->sd_error)
1304 mmcif_dma_complete(host);
1306 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1312 static void mmcif_timeout_work(struct work_struct *work)
1314 struct delayed_work *d = container_of(work, struct delayed_work, work);
1315 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1316 struct mmc_request *mrq = host->mrq;
1317 unsigned long flags;
1320 /* Don't run after mmc_remove_host() */
1323 spin_lock_irqsave(&host->lock, flags);
1324 if (host->state == STATE_IDLE) {
1325 spin_unlock_irqrestore(&host->lock, flags);
1329 dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n",
1330 host->wait_for, mrq->cmd->opcode);
1332 host->state = STATE_TIMEOUT;
1333 spin_unlock_irqrestore(&host->lock, flags);
1336 * Handle races with cancel_delayed_work(), unless
1337 * cancel_delayed_work_sync() is used
1339 switch (host->wait_for) {
1340 case MMCIF_WAIT_FOR_CMD:
1341 mrq->cmd->error = sh_mmcif_error_manage(host);
1343 case MMCIF_WAIT_FOR_STOP:
1344 mrq->stop->error = sh_mmcif_error_manage(host);
1346 case MMCIF_WAIT_FOR_MREAD:
1347 case MMCIF_WAIT_FOR_MWRITE:
1348 case MMCIF_WAIT_FOR_READ:
1349 case MMCIF_WAIT_FOR_WRITE:
1350 case MMCIF_WAIT_FOR_READ_END:
1351 case MMCIF_WAIT_FOR_WRITE_END:
1352 mrq->data->error = sh_mmcif_error_manage(host);
1358 host->state = STATE_IDLE;
1359 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1361 mmc_request_done(host->mmc, mrq);
1364 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1366 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1367 struct mmc_host *mmc = host->mmc;
1369 mmc_regulator_get_supply(mmc);
1374 if (!mmc->ocr_avail)
1375 mmc->ocr_avail = pd->ocr;
1377 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1380 static int sh_mmcif_probe(struct platform_device *pdev)
1382 int ret = 0, irq[2];
1383 struct mmc_host *mmc;
1384 struct sh_mmcif_host *host;
1385 struct device *dev = &pdev->dev;
1386 struct sh_mmcif_plat_data *pd = dev->platform_data;
1387 struct resource *res;
1391 irq[0] = platform_get_irq(pdev, 0);
1392 irq[1] = platform_get_irq(pdev, 1);
1394 dev_err(dev, "Get irq error\n");
1398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1399 reg = devm_ioremap_resource(dev, res);
1401 return PTR_ERR(reg);
1403 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);
1407 ret = mmc_of_parse(mmc);
1411 host = mmc_priv(mmc);
1414 host->timeout = msecs_to_jiffies(10000);
1415 host->ccs_enable = !pd || !pd->ccs_unsupported;
1416 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1420 spin_lock_init(&host->lock);
1422 mmc->ops = &sh_mmcif_ops;
1423 sh_mmcif_init_ocr(host);
1425 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1427 mmc->caps |= pd->caps;
1429 mmc->max_blk_size = 512;
1430 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1431 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1432 mmc->max_seg_size = mmc->max_req_size;
1434 platform_set_drvdata(pdev, host);
1436 pm_runtime_enable(dev);
1437 host->power = false;
1439 host->clk = devm_clk_get(dev, NULL);
1440 if (IS_ERR(host->clk)) {
1441 ret = PTR_ERR(host->clk);
1442 dev_err(dev, "cannot get clock: %d\n", ret);
1446 ret = clk_prepare_enable(host->clk);
1450 sh_mmcif_clk_setup(host);
1452 ret = pm_runtime_resume(dev);
1456 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1458 sh_mmcif_sync_reset(host);
1459 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1461 name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";
1462 ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,
1463 sh_mmcif_irqt, 0, name, host);
1465 dev_err(dev, "request_irq error (%s)\n", name);
1469 ret = devm_request_threaded_irq(dev, irq[1],
1470 sh_mmcif_intr, sh_mmcif_irqt,
1471 0, "sh_mmc:int", host);
1473 dev_err(dev, "request_irq error (sh_mmc:int)\n");
1478 if (pd && pd->use_cd_gpio) {
1479 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1484 mutex_init(&host->thread_lock);
1486 ret = mmc_add_host(mmc);
1490 dev_pm_qos_expose_latency_limit(dev, 100);
1492 dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",
1493 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1494 clk_get_rate(host->clk) / 1000000UL);
1496 clk_disable_unprepare(host->clk);
1500 clk_disable_unprepare(host->clk);
1502 pm_runtime_disable(dev);
1508 static int sh_mmcif_remove(struct platform_device *pdev)
1510 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1513 clk_prepare_enable(host->clk);
1514 pm_runtime_get_sync(&pdev->dev);
1516 dev_pm_qos_hide_latency_limit(&pdev->dev);
1518 mmc_remove_host(host->mmc);
1519 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1522 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1523 * mmc_remove_host() call above. But swapping order doesn't help either
1524 * (a query on the linux-mmc mailing list didn't bring any replies).
1526 cancel_delayed_work_sync(&host->timeout_work);
1528 clk_disable_unprepare(host->clk);
1529 mmc_free_host(host->mmc);
1530 pm_runtime_put_sync(&pdev->dev);
1531 pm_runtime_disable(&pdev->dev);
1536 #ifdef CONFIG_PM_SLEEP
1537 static int sh_mmcif_suspend(struct device *dev)
1539 struct sh_mmcif_host *host = dev_get_drvdata(dev);
1541 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1546 static int sh_mmcif_resume(struct device *dev)
1552 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1553 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1556 static struct platform_driver sh_mmcif_driver = {
1557 .probe = sh_mmcif_probe,
1558 .remove = sh_mmcif_remove,
1560 .name = DRIVER_NAME,
1561 .pm = &sh_mmcif_dev_pm_ops,
1562 .of_match_table = mmcif_of_match,
1566 module_platform_driver(sh_mmcif_driver);
1568 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1569 MODULE_LICENSE("GPL");
1570 MODULE_ALIAS("platform:" DRIVER_NAME);
1571 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");