2 * linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
15 #define PCI_SLOT_INFO 0x40 /* 8 bits */
16 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
17 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
20 * Controller registers
23 #define SDHCI_DMA_ADDRESS 0x00
25 #define SDHCI_BLOCK_SIZE 0x04
26 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
28 #define SDHCI_BLOCK_COUNT 0x06
30 #define SDHCI_ARGUMENT 0x08
32 #define SDHCI_TRANSFER_MODE 0x0C
33 #define SDHCI_TRNS_DMA 0x01
34 #define SDHCI_TRNS_BLK_CNT_EN 0x02
35 #define SDHCI_TRNS_ACMD12 0x04
36 #define SDHCI_TRNS_READ 0x10
37 #define SDHCI_TRNS_MULTI 0x20
39 #define SDHCI_COMMAND 0x0E
40 #define SDHCI_CMD_RESP_MASK 0x03
41 #define SDHCI_CMD_CRC 0x08
42 #define SDHCI_CMD_INDEX 0x10
43 #define SDHCI_CMD_DATA 0x20
45 #define SDHCI_CMD_RESP_NONE 0x00
46 #define SDHCI_CMD_RESP_LONG 0x01
47 #define SDHCI_CMD_RESP_SHORT 0x02
48 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
50 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
52 #define SDHCI_RESPONSE 0x10
54 #define SDHCI_BUFFER 0x20
56 #define SDHCI_PRESENT_STATE 0x24
57 #define SDHCI_CMD_INHIBIT 0x00000001
58 #define SDHCI_DATA_INHIBIT 0x00000002
59 #define SDHCI_DOING_WRITE 0x00000100
60 #define SDHCI_DOING_READ 0x00000200
61 #define SDHCI_SPACE_AVAILABLE 0x00000400
62 #define SDHCI_DATA_AVAILABLE 0x00000800
63 #define SDHCI_CARD_PRESENT 0x00010000
64 #define SDHCI_WRITE_PROTECT 0x00080000
66 #define SDHCI_HOST_CONTROL 0x28
67 #define SDHCI_CTRL_LED 0x01
68 #define SDHCI_CTRL_4BITBUS 0x02
70 #define SDHCI_POWER_CONTROL 0x29
71 #define SDHCI_POWER_ON 0x01
72 #define SDHCI_POWER_180 0x0A
73 #define SDHCI_POWER_300 0x0C
74 #define SDHCI_POWER_330 0x0E
76 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
78 #define SDHCI_WALK_UP_CONTROL 0x2B
80 #define SDHCI_CLOCK_CONTROL 0x2C
81 #define SDHCI_DIVIDER_SHIFT 8
82 #define SDHCI_CLOCK_CARD_EN 0x0004
83 #define SDHCI_CLOCK_INT_STABLE 0x0002
84 #define SDHCI_CLOCK_INT_EN 0x0001
86 #define SDHCI_TIMEOUT_CONTROL 0x2E
88 #define SDHCI_SOFTWARE_RESET 0x2F
89 #define SDHCI_RESET_ALL 0x01
90 #define SDHCI_RESET_CMD 0x02
91 #define SDHCI_RESET_DATA 0x04
93 #define SDHCI_INT_STATUS 0x30
94 #define SDHCI_INT_ENABLE 0x34
95 #define SDHCI_SIGNAL_ENABLE 0x38
96 #define SDHCI_INT_RESPONSE 0x00000001
97 #define SDHCI_INT_DATA_END 0x00000002
98 #define SDHCI_INT_DMA_END 0x00000008
99 #define SDHCI_INT_SPACE_AVAIL 0x00000010
100 #define SDHCI_INT_DATA_AVAIL 0x00000020
101 #define SDHCI_INT_CARD_INSERT 0x00000040
102 #define SDHCI_INT_CARD_REMOVE 0x00000080
103 #define SDHCI_INT_CARD_INT 0x00000100
104 #define SDHCI_INT_TIMEOUT 0x00010000
105 #define SDHCI_INT_CRC 0x00020000
106 #define SDHCI_INT_END_BIT 0x00040000
107 #define SDHCI_INT_INDEX 0x00080000
108 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
109 #define SDHCI_INT_DATA_CRC 0x00200000
110 #define SDHCI_INT_DATA_END_BIT 0x00400000
111 #define SDHCI_INT_BUS_POWER 0x00800000
112 #define SDHCI_INT_ACMD12ERR 0x01000000
114 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
115 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
117 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
118 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
119 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
120 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
121 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
122 SDHCI_INT_DATA_END_BIT)
124 #define SDHCI_ACMD12_ERR 0x3C
128 #define SDHCI_CAPABILITIES 0x40
129 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
130 #define SDHCI_TIMEOUT_CLK_SHIFT 0
131 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
132 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
133 #define SDHCI_CLOCK_BASE_SHIFT 8
134 #define SDHCI_CAN_DO_DMA 0x00400000
135 #define SDHCI_CAN_VDD_330 0x01000000
136 #define SDHCI_CAN_VDD_300 0x02000000
137 #define SDHCI_CAN_VDD_180 0x04000000
139 /* 44-47 reserved for more caps */
141 #define SDHCI_MAX_CURRENT 0x48
143 /* 4C-4F reserved for more max current */
147 #define SDHCI_SLOT_INT_STATUS 0xFC
149 #define SDHCI_HOST_VERSION 0xFE
154 struct sdhci_chip *chip;
155 struct mmc_host *mmc; /* MMC structure */
157 spinlock_t lock; /* Mutex */
159 int flags; /* Host attributes */
160 #define SDHCI_USE_DMA (1<<0)
162 unsigned int max_clk; /* Max possible freq (MHz) */
163 unsigned int timeout_clk; /* Timeout freq (KHz) */
165 unsigned int clock; /* Current clock (MHz) */
166 unsigned short power; /* Current voltage */
168 struct mmc_request *mrq; /* Current request */
169 struct mmc_command *cmd; /* Current command */
170 struct mmc_data *data; /* Current data request */
172 struct scatterlist *cur_sg; /* We're working on this */
173 char *mapped_sg; /* This is where it's mapped */
174 int num_sg; /* Entries left */
175 int offset; /* Offset into current sg */
176 int remain; /* Bytes left in current */
178 int size; /* Remaining bytes in transfer */
180 char slot_descr[20]; /* Name for reservations */
182 int irq; /* Device IRQ */
183 int bar; /* PCI BAR index */
184 unsigned long addr; /* Bus address */
185 void __iomem * ioaddr; /* Mapped address */
187 struct tasklet_struct card_tasklet; /* Tasklet structures */
188 struct tasklet_struct finish_tasklet;
190 struct timer_list timer; /* Timer for timeouts */
194 struct pci_dev *pdev;
196 int num_slots; /* Slots on controller */
197 struct sdhci_host *hosts[0]; /* Pointers to hosts */