1 menu "RAM/ROM/Flash chip drivers"
5 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
9 The Common Flash Interface specification was developed by Intel,
10 AMD and other flash manufactures that provides a universal method
11 for probing the capabilities of flash devices. If you wish to
12 support any device that is CFI-compliant, you need to enable this
13 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
14 for more information on CFI.
17 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
21 This option enables JEDEC-style probing of flash chips which are not
22 compatible with the Common Flash Interface, but will use the common
23 CFI-targeted flash drivers for any chips which are identified which
24 are in fact compatible in all but the probe method. This actually
25 covers most AMD/Fujitsu-compatible chips and also non-CFI
31 config MTD_CFI_ADV_OPTIONS
32 bool "Flash chip driver advanced configuration options"
33 depends on MTD_GEN_PROBE
35 If you need to specify a specific endianness for access to flash
36 chips, or if you wish to reduce the size of the kernel by including
37 support for only specific arrangements of flash chips, say 'Y'. This
38 option does not directly affect the code, but will enable other
39 configuration options which allow you to do so.
44 prompt "Flash cmd/query data swapping"
45 depends on MTD_CFI_ADV_OPTIONS
46 default MTD_CFI_NOSWAP
48 This option defines the way in which the CPU attempts to arrange
49 data bits when writing the 'magic' commands to the chips. Saying
50 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
51 enabled, means that the CPU will not do any swapping; the chips
52 are expected to be wired to the CPU in 'host-endian' form.
53 Specific arrangements are possible with the BIG_ENDIAN_BYTE and
54 LITTLE_ENDIAN_BYTE, if the bytes are reversed.
59 config MTD_CFI_BE_BYTE_SWAP
60 bool "BIG_ENDIAN_BYTE"
62 config MTD_CFI_LE_BYTE_SWAP
63 bool "LITTLE_ENDIAN_BYTE"
67 config MTD_CFI_GEOMETRY
68 bool "Specific CFI Flash geometry selection"
69 depends on MTD_CFI_ADV_OPTIONS
71 This option does not affect the code directly, but will enable
72 some other configuration options which would allow you to reduce
73 the size of the kernel by including support for only certain
74 arrangements of CFI chips. If unsure, say 'N' and all options
75 which are supported by the current code will be enabled.
77 config MTD_MAP_BANK_WIDTH_1
78 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
81 If you wish to support CFI devices on a physical bus which is
84 config MTD_MAP_BANK_WIDTH_2
85 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
88 If you wish to support CFI devices on a physical bus which is
89 16 bits wide, say 'Y'.
91 config MTD_MAP_BANK_WIDTH_4
92 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
95 If you wish to support CFI devices on a physical bus which is
96 32 bits wide, say 'Y'.
98 config MTD_MAP_BANK_WIDTH_8
99 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
102 If you wish to support CFI devices on a physical bus which is
103 64 bits wide, say 'Y'.
105 config MTD_MAP_BANK_WIDTH_16
106 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
109 If you wish to support CFI devices on a physical bus which is
110 128 bits wide, say 'Y'.
112 config MTD_MAP_BANK_WIDTH_32
113 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
116 If you wish to support CFI devices on a physical bus which is
117 256 bits wide, say 'Y'.
120 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
123 If your flash chips are not interleaved - i.e. you only have one
124 flash chip addressed by each bus cycle, then say 'Y'.
127 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
130 If your flash chips are interleaved in pairs - i.e. you have two
131 flash chips addressed by each bus cycle, then say 'Y'.
134 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
137 If your flash chips are interleaved in fours - i.e. you have four
138 flash chips addressed by each bus cycle, then say 'Y'.
141 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
144 If your flash chips are interleaved in eights - i.e. you have eight
145 flash chips addressed by each bus cycle, then say 'Y'.
148 bool "Protection Registers aka one-time programmable (OTP) bits"
149 depends on MTD_CFI_ADV_OPTIONS
152 This enables support for reading, writing and locking so called
153 "Protection Registers" present on some flash chips.
154 A subset of them are pre-programmed at the factory with a
155 unique set of values. The rest is user-programmable.
157 The user-programmable Protection Registers contain one-time
158 programmable (OTP) bits; when programmed, register bits cannot be
159 erased. Each Protection Register can be accessed multiple times to
160 program individual bits, as long as the register remains unlocked.
162 Each Protection Register has an associated Lock Register bit. When a
163 Lock Register bit is programmed, the associated Protection Register
164 can only be read; it can no longer be programmed. Additionally,
165 because the Lock Register bits themselves are OTP, when programmed,
166 Lock Register bits cannot be erased. Therefore, when a Protection
167 Register is locked, it cannot be unlocked.
169 This feature should therefore be used with extreme care. Any mistake
170 in the programming of OTP bits will waste them.
172 config MTD_CFI_INTELEXT
173 tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
174 depends on MTD_GEN_PROBE
177 The Common Flash Interface defines a number of different command
178 sets which a CFI-compliant chip may claim to implement. This code
179 provides support for command set 0001, used on Intel StrataFlash
182 config MTD_CFI_AMDSTD
183 tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
184 depends on MTD_GEN_PROBE
187 The Common Flash Interface defines a number of different command
188 sets which a CFI-compliant chip may claim to implement. This code
189 provides support for command set 0002, used on chips including
193 tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
194 depends on MTD_GEN_PROBE
197 The Common Flash Interface defines a number of different command
198 sets which a CFI-compliant chip may claim to implement. This code
199 provides support for command set 0020.
205 tristate "Support for RAM chips in bus mapping"
207 This option enables basic support for RAM chips accessed through
208 a bus mapping driver.
211 tristate "Support for ROM chips in bus mapping"
213 This option enables basic support for ROM chips accessed through
214 a bus mapping driver.
217 tristate "Support for absent chips in bus mapping"
219 This option enables support for a dummy probing driver used to
220 allocated placeholder MTD devices on systems that have socketed
221 or removable media. Use of this driver as a fallback chip probe
222 preserves the expected registration order of MTD device nodes on
223 the system regardless of media presence. Device nodes created
224 with this driver will return -ENODEV upon access.
227 bool "XIP aware MTD support"
228 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
229 default y if XIP_KERNEL
231 This allows MTD support to work with flash memory which is also
232 used for XIP purposes. If you're not sure what this is all about