2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
4 * Author: Angus Clark <angus.clark@st.com>
6 * Copyright (C) 2010-2014 STicroelectronics Limited
8 * JEDEC probe based on drivers/mtd/devices/m25p80.c
10 * This code is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/platform_device.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/sched.h>
22 #include <linux/delay.h>
26 #include "serial_flash_cmds.h"
29 * FSM SPI Controller Registers
31 #define SPI_CLOCKDIV 0x0010
32 #define SPI_MODESELECT 0x0018
33 #define SPI_CONFIGDATA 0x0020
34 #define SPI_STA_MODE_CHANGE 0x0028
35 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
36 #define SPI_FAST_SEQ_ADD1 0x0104
37 #define SPI_FAST_SEQ_ADD2 0x0108
38 #define SPI_FAST_SEQ_ADD_CFG 0x010c
39 #define SPI_FAST_SEQ_OPC1 0x0110
40 #define SPI_FAST_SEQ_OPC2 0x0114
41 #define SPI_FAST_SEQ_OPC3 0x0118
42 #define SPI_FAST_SEQ_OPC4 0x011c
43 #define SPI_FAST_SEQ_OPC5 0x0120
44 #define SPI_MODE_BITS 0x0124
45 #define SPI_DUMMY_BITS 0x0128
46 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
47 #define SPI_FAST_SEQ_1 0x0130
48 #define SPI_FAST_SEQ_2 0x0134
49 #define SPI_FAST_SEQ_3 0x0138
50 #define SPI_FAST_SEQ_4 0x013c
51 #define SPI_FAST_SEQ_CFG 0x0140
52 #define SPI_FAST_SEQ_STA 0x0144
53 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
54 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
55 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
56 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
57 #define SPI_PROGRAM_ERASE_TIME 0x0158
58 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
59 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
60 #define SPI_STATUS_WR_TIME_REG 0x0164
61 #define SPI_FAST_SEQ_DATA_REG 0x0300
64 * Register: SPI_MODESELECT
66 #define SPI_MODESELECT_CONTIG 0x01
67 #define SPI_MODESELECT_FASTREAD 0x02
68 #define SPI_MODESELECT_DUALIO 0x04
69 #define SPI_MODESELECT_FSM 0x08
70 #define SPI_MODESELECT_QUADBOOT 0x10
73 * Register: SPI_CONFIGDATA
75 #define SPI_CFG_DEVICE_ST 0x1
76 #define SPI_CFG_DEVICE_ATMEL 0x4
77 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
78 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
79 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
81 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA)
82 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0)
83 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00)
86 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
88 #define TRANSFER_SIZE(x) ((x) * 8)
91 * Register: SPI_FAST_SEQ_ADD_CFG
93 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
94 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
95 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
96 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
97 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
98 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
99 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
100 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
101 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
102 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
105 * Register: SPI_FAST_SEQ_n
107 #define SEQ_OPC_OPCODE(x) ((x) << 0)
108 #define SEQ_OPC_CYCLES(x) ((x) << 8)
109 #define SEQ_OPC_PADS_1 (0x0 << 14)
110 #define SEQ_OPC_PADS_2 (0x1 << 14)
111 #define SEQ_OPC_PADS_4 (0x3 << 14)
112 #define SEQ_OPC_CSDEASSERT (1 << 16)
115 * Register: SPI_FAST_SEQ_CFG
117 #define SEQ_CFG_STARTSEQ (1 << 0)
118 #define SEQ_CFG_SWRESET (1 << 5)
119 #define SEQ_CFG_CSDEASSERT (1 << 6)
120 #define SEQ_CFG_READNOTWRITE (1 << 7)
121 #define SEQ_CFG_ERASE (1 << 8)
122 #define SEQ_CFG_PADS_1 (0x0 << 16)
123 #define SEQ_CFG_PADS_2 (0x1 << 16)
124 #define SEQ_CFG_PADS_4 (0x3 << 16)
127 * Register: SPI_MODE_BITS
129 #define MODE_DATA(x) (x & 0xff)
130 #define MODE_CYCLES(x) ((x & 0x3f) << 16)
131 #define MODE_PADS_1 (0x0 << 22)
132 #define MODE_PADS_2 (0x1 << 22)
133 #define MODE_PADS_4 (0x3 << 22)
134 #define DUMMY_CSDEASSERT (1 << 24)
137 * Register: SPI_DUMMY_BITS
139 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16)
140 #define DUMMY_PADS_1 (0x0 << 22)
141 #define DUMMY_PADS_2 (0x1 << 22)
142 #define DUMMY_PADS_4 (0x3 << 22)
143 #define DUMMY_CSDEASSERT (1 << 24)
146 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
148 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0)
149 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8)
150 #define STA_PADS_1 (0x0 << 16)
151 #define STA_PADS_2 (0x1 << 16)
152 #define STA_PADS_4 (0x3 << 16)
153 #define STA_CSDEASSERT (0x1 << 20)
154 #define STA_RDNOTWR (0x1 << 21)
157 * FSM SPI Instruction Opcodes
159 #define STFSM_OPC_CMD 0x1
160 #define STFSM_OPC_ADD 0x2
161 #define STFSM_OPC_STA 0x3
162 #define STFSM_OPC_MODE 0x4
163 #define STFSM_OPC_DUMMY 0x5
164 #define STFSM_OPC_DATA 0x6
165 #define STFSM_OPC_WAIT 0x7
166 #define STFSM_OPC_JUMP 0x8
167 #define STFSM_OPC_GOTO 0x9
168 #define STFSM_OPC_STOP 0xF
171 * FSM SPI Instructions (== opcode + operand).
173 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
175 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1)
176 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2)
177 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3)
178 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4)
179 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5)
180 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1)
181 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2)
183 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1)
184 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2)
186 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
187 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
188 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2)
189 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3)
191 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0)
192 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0)
193 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
194 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
196 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */
197 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
199 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
201 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */
206 struct resource *region;
209 struct flash_info *info;
211 uint32_t fifo_dir_delay;
212 bool booted_from_spi;
228 } __packed __aligned(4);
230 /* Parameters to configure a READ or WRITE FSM sequence */
231 struct seq_rw_config {
232 uint32_t flags; /* flags to support config */
233 uint8_t cmd; /* FLASH command */
234 int write; /* Write Sequence */
235 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */
236 uint8_t data_pads; /* No. of data pads */
237 uint8_t mode_data; /* MODE data */
238 uint8_t mode_cycles; /* No. of MODE cycles */
239 uint8_t dummy_cycles; /* No. of DUMMY cycles */
242 /* SPI Flash Device Table */
246 * JEDEC id zero means "no ID" (most older chips); otherwise it has
247 * a high byte of zero plus three data bytes: the manufacturer id,
248 * then a two byte device id.
253 * The size listed here is what works with FLASH_CMD_SE, which isn't
254 * necessarily called a "sector" by the vendor.
256 unsigned sector_size;
260 * Note, where FAST_READ is supported, freq_max specifies the
261 * FAST_READ frequency, not the READ frequency.
264 int (*config)(struct stfsm *);
267 static struct flash_info flash_types[] = {
269 * ST Microelectronics/Numonyx --
270 * (newer production versions may have feature updates
271 * (eg faster operating frequency)
273 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
274 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL },
275 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL },
276 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL },
277 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL },
278 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL },
279 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL },
281 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \
282 FLASH_FLAG_READ_FAST | \
283 FLASH_FLAG_READ_1_1_2 | \
284 FLASH_FLAG_WRITE_1_1_2)
285 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL },
286 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL },
288 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \
289 FLASH_FLAG_READ_FAST | \
290 FLASH_FLAG_READ_1_1_2 | \
291 FLASH_FLAG_READ_1_2_2 | \
292 FLASH_FLAG_READ_1_1_4 | \
293 FLASH_FLAG_READ_1_4_4 | \
296 { "mx25l25635e", 0xc22019, 0, 64*1024, 512,
297 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, NULL }
299 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \
300 FLASH_FLAG_READ_FAST | \
301 FLASH_FLAG_READ_1_1_2 | \
302 FLASH_FLAG_READ_1_2_2 | \
303 FLASH_FLAG_READ_1_1_4 | \
304 FLASH_FLAG_READ_1_4_4 | \
305 FLASH_FLAG_WRITE_1_1_2 | \
306 FLASH_FLAG_WRITE_1_2_2 | \
307 FLASH_FLAG_WRITE_1_1_4 | \
308 FLASH_FLAG_WRITE_1_4_4)
309 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL },
310 { "n25q256", 0x20ba19, 0, 64 * 1024, 512,
311 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL },
315 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
317 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \
318 FLASH_FLAG_READ_1_1_2 | \
319 FLASH_FLAG_READ_1_2_2 | \
320 FLASH_FLAG_READ_1_1_4 | \
321 FLASH_FLAG_READ_1_4_4 | \
322 FLASH_FLAG_WRITE_1_1_4 | \
323 FLASH_FLAG_READ_FAST)
324 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80,
326 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80,
331 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
332 * - RESET# signal supported by die but not bristled out on all
333 * package types. The package type is a function of board design,
334 * so this information is captured in the board's flags.
335 * - Supports 'DYB' sector protection. Depending on variant, sectors
336 * may default to locked state on power-on.
338 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \
340 FLASH_FLAG_DYB_LOCKING)
341 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80,
343 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80,
345 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
346 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
347 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
348 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
350 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
351 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \
352 FLASH_FLAG_READ_FAST | \
353 FLASH_FLAG_READ_1_1_2 | \
354 FLASH_FLAG_WRITE_1_1_2)
355 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL },
356 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL },
357 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL },
358 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL },
359 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL },
361 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
362 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \
363 FLASH_FLAG_READ_FAST | \
364 FLASH_FLAG_READ_1_1_2 | \
365 FLASH_FLAG_READ_1_2_2 | \
366 FLASH_FLAG_READ_1_1_4 | \
367 FLASH_FLAG_READ_1_4_4 | \
368 FLASH_FLAG_WRITE_1_1_4)
369 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, NULL },
370 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, NULL },
371 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, NULL },
372 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, NULL },
375 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
379 * FSM message sequence configurations:
381 * All configs are presented in order of preference
384 /* Default READ configurations, in order of preference */
385 static struct seq_rw_config default_read_configs[] = {
386 {FLASH_FLAG_READ_1_4_4, FLASH_CMD_READ_1_4_4, 0, 4, 4, 0x00, 2, 4},
387 {FLASH_FLAG_READ_1_1_4, FLASH_CMD_READ_1_1_4, 0, 1, 4, 0x00, 4, 0},
388 {FLASH_FLAG_READ_1_2_2, FLASH_CMD_READ_1_2_2, 0, 2, 2, 0x00, 4, 0},
389 {FLASH_FLAG_READ_1_1_2, FLASH_CMD_READ_1_1_2, 0, 1, 2, 0x00, 0, 8},
390 {FLASH_FLAG_READ_FAST, FLASH_CMD_READ_FAST, 0, 1, 1, 0x00, 0, 8},
391 {FLASH_FLAG_READ_WRITE, FLASH_CMD_READ, 0, 1, 1, 0x00, 0, 0},
392 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
395 /* Default WRITE configurations */
396 static struct seq_rw_config default_write_configs[] = {
397 {FLASH_FLAG_WRITE_1_4_4, FLASH_CMD_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
398 {FLASH_FLAG_WRITE_1_1_4, FLASH_CMD_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
399 {FLASH_FLAG_WRITE_1_2_2, FLASH_CMD_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
400 {FLASH_FLAG_WRITE_1_1_2, FLASH_CMD_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
401 {FLASH_FLAG_READ_WRITE, FLASH_CMD_WRITE, 1, 1, 1, 0x00, 0, 0},
402 {0x00, 0, 0, 0, 0, 0x00, 0, 0},
405 static struct stfsm_seq stfsm_seq_en_32bit_addr;/* Dynamically populated */
407 static struct stfsm_seq stfsm_seq_read_jedec = {
408 .data_size = TRANSFER_SIZE(8),
409 .seq_opc[0] = (SEQ_OPC_PADS_1 |
411 SEQ_OPC_OPCODE(FLASH_CMD_RDID)),
414 STFSM_INST_DATA_READ,
417 .seq_cfg = (SEQ_CFG_PADS_1 |
418 SEQ_CFG_READNOTWRITE |
423 static struct stfsm_seq stfsm_seq_erase_sector = {
424 /* 'addr_cfg' configured during initialisation */
426 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
427 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
429 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
430 SEQ_OPC_OPCODE(FLASH_CMD_SE)),
439 .seq_cfg = (SEQ_CFG_PADS_1 |
440 SEQ_CFG_READNOTWRITE |
445 static struct stfsm_seq stfsm_seq_wrvcr = {
446 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
447 SEQ_OPC_OPCODE(FLASH_CMD_WREN) | SEQ_OPC_CSDEASSERT),
448 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
449 SEQ_OPC_OPCODE(FLASH_CMD_WRVCR)),
456 .seq_cfg = (SEQ_CFG_PADS_1 |
457 SEQ_CFG_READNOTWRITE |
462 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
464 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
465 SEQ_OPC_OPCODE(FLASH_CMD_EN4B_ADDR));
466 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
467 SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
470 seq->seq[0] = STFSM_INST_CMD2;
471 seq->seq[1] = STFSM_INST_CMD1;
472 seq->seq[2] = STFSM_INST_WAIT;
473 seq->seq[3] = STFSM_INST_STOP;
475 seq->seq_cfg = (SEQ_CFG_PADS_1 |
477 SEQ_CFG_READNOTWRITE |
484 static inline int stfsm_is_idle(struct stfsm *fsm)
486 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
489 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
491 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
494 static void stfsm_clear_fifo(struct stfsm *fsm)
499 avail = stfsm_fifo_available(fsm);
504 readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
510 static inline void stfsm_load_seq(struct stfsm *fsm,
511 const struct stfsm_seq *seq)
513 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
514 const uint32_t *src = (const uint32_t *)seq;
515 int words = sizeof(*seq) / sizeof(*src);
517 BUG_ON(!stfsm_is_idle(fsm));
526 static void stfsm_wait_seq(struct stfsm *fsm)
528 unsigned long deadline;
531 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
534 if (time_after_eq(jiffies, deadline))
537 if (stfsm_is_idle(fsm))
543 dev_err(fsm->dev, "timeout on sequence completion\n");
546 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
549 uint32_t remaining = size >> 2;
553 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
555 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
559 avail = stfsm_fifo_available(fsm);
564 words = min(avail, remaining);
567 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
572 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
574 struct stfsm_seq *seq = &stfsm_seq_en_32bit_addr;
575 uint32_t cmd = enter ? FLASH_CMD_EN4B_ADDR : FLASH_CMD_EX4B_ADDR;
577 seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
579 SEQ_OPC_OPCODE(cmd) |
582 stfsm_load_seq(fsm, seq);
589 static int stfsm_wrvcr(struct stfsm *fsm, uint8_t data)
591 struct stfsm_seq *seq = &stfsm_seq_wrvcr;
593 dev_dbg(fsm->dev, "writing VCR 0x%02x\n", data);
595 seq->status = (STA_DATA_BYTE1(data) | STA_PADS_1 | STA_CSDEASSERT);
597 stfsm_load_seq(fsm, seq);
605 * SoC reset on 'boot-from-spi' systems
607 * Certain modes of operation cause the Flash device to enter a particular state
608 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit
609 * Addr' commands). On boot-from-spi systems, it is important to consider what
610 * happens if a warm reset occurs during this period. The SPIBoot controller
611 * assumes that Flash device is in its default reset state, 24-bit address mode,
612 * and ready to accept commands. This can be achieved using some form of
613 * on-board logic/controller to force a device POR in response to a SoC-level
614 * reset or by making use of the device reset signal if available (limited
615 * number of devices only).
617 * Failure to take such precautions can cause problems following a warm reset.
618 * For some operations (e.g. ERASE), there is little that can be done. For
619 * other modes of operation (e.g. 32-bit addressing), options are often
620 * available that can help minimise the window in which a reset could cause a
624 static bool stfsm_can_handle_soc_reset(struct stfsm *fsm)
626 /* Reset signal is available on the board and supported by the device */
627 if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)
630 /* Board-level logic forces a power-on-reset */
634 /* Reset is not properly handled and may result in failure to reboot */
638 /* Configure 'addr_cfg' according to addressing mode */
639 static void stfsm_prepare_erasesec_seq(struct stfsm *fsm,
640 struct stfsm_seq *seq)
642 int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8;
644 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) |
645 ADR_CFG_PADS_1_ADD1 |
646 ADR_CFG_CYCLES_ADD2(16) |
647 ADR_CFG_PADS_1_ADD2 |
648 ADR_CFG_CSDEASSERT_ADD2);
651 /* Search for preferred configuration based on available flags */
652 static struct seq_rw_config *
653 stfsm_search_seq_rw_configs(struct stfsm *fsm,
654 struct seq_rw_config cfgs[])
656 struct seq_rw_config *config;
657 int flags = fsm->info->flags;
659 for (config = cfgs; config->cmd != 0; config++)
660 if ((config->flags & flags) == config->flags)
666 /* Prepare a READ/WRITE sequence according to configuration parameters */
667 static void stfsm_prepare_rw_seq(struct stfsm *fsm,
668 struct stfsm_seq *seq,
669 struct seq_rw_config *cfg)
671 int addr1_cycles, addr2_cycles;
674 memset(seq, 0, sizeof(*seq));
676 /* Add READ/WRITE OPC */
677 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
679 SEQ_OPC_OPCODE(cfg->cmd));
681 /* Add WREN OPC for a WRITE sequence */
683 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
685 SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
688 /* Address configuration (24 or 32-bit addresses) */
689 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
690 addr1_cycles /= cfg->addr_pads;
691 addr2_cycles = 16 / cfg->addr_pads;
692 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */
693 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */
694 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */
695 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */
697 /* Data/Sequence configuration */
698 seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
702 seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
704 /* Mode configuration (no. of pads taken from addr cfg) */
705 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */
706 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */
707 (cfg->addr_pads - 1) << 22); /* pads */
709 /* Dummy configuration (no. of pads taken from addr cfg) */
710 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */
711 (cfg->addr_pads - 1) << 22); /* pads */
714 /* Instruction sequence */
717 seq->seq[i++] = STFSM_INST_CMD2;
719 seq->seq[i++] = STFSM_INST_CMD1;
721 seq->seq[i++] = STFSM_INST_ADD1;
722 seq->seq[i++] = STFSM_INST_ADD2;
724 if (cfg->mode_cycles)
725 seq->seq[i++] = STFSM_INST_MODE;
727 if (cfg->dummy_cycles)
728 seq->seq[i++] = STFSM_INST_DUMMY;
731 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
732 seq->seq[i++] = STFSM_INST_STOP;
735 static int stfsm_search_prepare_rw_seq(struct stfsm *fsm,
736 struct stfsm_seq *seq,
737 struct seq_rw_config *cfgs)
739 struct seq_rw_config *config;
741 config = stfsm_search_seq_rw_configs(fsm, cfgs);
743 dev_err(fsm->dev, "failed to find suitable config\n");
747 stfsm_prepare_rw_seq(fsm, seq, config);
752 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
754 const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
757 stfsm_load_seq(fsm, seq);
759 stfsm_read_fifo(fsm, tmp, 8);
761 memcpy(jedec, tmp, 5);
766 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
768 struct flash_info *info;
773 stfsm_read_jedec(fsm, id);
775 jedec = id[0] << 16 | id[1] << 8 | id[2];
777 * JEDEC also defines an optional "extended device information"
778 * string for after vendor-specific data, after the three bytes
779 * we use here. Supporting some chips might require using it.
781 ext_jedec = id[3] << 8 | id[4];
783 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n",
784 jedec, id[0], id[1], id[2], id[3], id[4]);
786 for (info = flash_types; info->name; info++) {
787 if (info->jedec_id == jedec) {
788 if (info->ext_id && info->ext_id != ext_jedec)
793 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
798 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
800 int ret, timeout = 10;
802 /* Wait for controller to accept mode change */
804 ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
813 writel(mode, fsm->base + SPI_MODESELECT);
818 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
823 /* TODO: Make this dynamic */
824 emi_freq = STFSM_DEFAULT_EMI_FREQ;
827 * Calculate clk_div - values between 2 and 128
828 * Multiple of 2, rounded up
830 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
833 else if (clk_div > 128)
837 * Determine a suitable delay for the IP to complete a change of
838 * direction of the FIFO. The required delay is related to the clock
839 * divider used. The following heuristics are based on empirical tests,
840 * using a 100MHz EMI clock.
843 fsm->fifo_dir_delay = 0;
844 else if (clk_div <= 10)
845 fsm->fifo_dir_delay = 1;
847 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
849 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
850 emi_freq, spi_freq, clk_div);
852 writel(clk_div, fsm->base + SPI_CLOCKDIV);
855 static int stfsm_init(struct stfsm *fsm)
859 /* Perform a soft reset of the FSM controller */
860 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
862 writel(0, fsm->base + SPI_FAST_SEQ_CFG);
864 /* Set clock to 'safe' frequency initially */
865 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
868 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
872 /* Set timing parameters */
873 writel(SPI_CFG_DEVICE_ST |
874 SPI_CFG_DEFAULT_MIN_CS_HIGH |
875 SPI_CFG_DEFAULT_CS_SETUPHOLD |
876 SPI_CFG_DEFAULT_DATA_HOLD,
877 fsm->base + SPI_CONFIGDATA);
878 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
880 /* Clear FIFO, just in case */
881 stfsm_clear_fifo(fsm);
886 static void stfsm_fetch_platform_configs(struct platform_device *pdev)
888 struct stfsm *fsm = platform_get_drvdata(pdev);
889 struct device_node *np = pdev->dev.of_node;
890 struct regmap *regmap;
891 uint32_t boot_device_reg;
892 uint32_t boot_device_spi;
893 uint32_t boot_device; /* Value we read from *boot_device_reg */
896 /* Booting from SPI NOR Flash is the default */
897 fsm->booted_from_spi = true;
899 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
901 goto boot_device_fail;
903 fsm->reset_signal = of_property_read_bool(np, "st,reset-signal");
905 fsm->reset_por = of_property_read_bool(np, "st,reset-por");
907 /* Where in the syscon the boot device information lives */
908 ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg);
910 goto boot_device_fail;
912 /* Boot device value when booted from SPI NOR */
913 ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi);
915 goto boot_device_fail;
917 ret = regmap_read(regmap, boot_device_reg, &boot_device);
919 goto boot_device_fail;
921 if (boot_device != boot_device_spi)
922 fsm->booted_from_spi = false;
928 "failed to fetch boot device, assuming boot from SPI\n");
931 static int stfsm_probe(struct platform_device *pdev)
933 struct device_node *np = pdev->dev.of_node;
934 struct flash_info *info;
935 struct resource *res;
940 dev_err(&pdev->dev, "No DT found\n");
944 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
948 fsm->dev = &pdev->dev;
950 platform_set_drvdata(pdev, fsm);
952 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 dev_err(&pdev->dev, "Resource not found\n");
958 fsm->base = devm_ioremap_resource(&pdev->dev, res);
959 if (IS_ERR(fsm->base)) {
961 "Failed to reserve memory region %pR\n", res);
962 return PTR_ERR(fsm->base);
965 mutex_init(&fsm->lock);
967 ret = stfsm_init(fsm);
969 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
973 stfsm_fetch_platform_configs(pdev);
975 /* Detect SPI FLASH device */
976 info = stfsm_jedec_probe(fsm);
981 /* Use device size to determine address width */
982 if (info->sector_size * info->n_sectors > 0x1000000)
983 info->flags |= FLASH_FLAG_32BIT_ADDR;
985 fsm->mtd.dev.parent = &pdev->dev;
986 fsm->mtd.type = MTD_NORFLASH;
987 fsm->mtd.writesize = 4;
988 fsm->mtd.writebufsize = fsm->mtd.writesize;
989 fsm->mtd.flags = MTD_CAP_NORFLASH;
990 fsm->mtd.size = info->sector_size * info->n_sectors;
991 fsm->mtd.erasesize = info->sector_size;
994 "Found serial flash device: %s\n"
995 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
997 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
998 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
1000 return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
1003 static int stfsm_remove(struct platform_device *pdev)
1005 struct stfsm *fsm = platform_get_drvdata(pdev);
1008 err = mtd_device_unregister(&fsm->mtd);
1015 static struct of_device_id stfsm_match[] = {
1016 { .compatible = "st,spi-fsm", },
1019 MODULE_DEVICE_TABLE(of, stfsm_match);
1021 static struct platform_driver stfsm_driver = {
1022 .probe = stfsm_probe,
1023 .remove = stfsm_remove,
1025 .name = "st-spi-fsm",
1026 .owner = THIS_MODULE,
1027 .of_match_table = stfsm_match,
1030 module_platform_driver(stfsm_driver);
1032 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
1033 MODULE_DESCRIPTION("ST SPI FSM driver");
1034 MODULE_LICENSE("GPL");