2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
4 * Author: Angus Clark <angus.clark@st.com>
6 * Copyright (C) 2010-2014 STicroelectronics Limited
8 * JEDEC probe based on drivers/mtd/devices/m25p80.c
10 * This code is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/sched.h>
20 #include <linux/delay.h>
25 * FSM SPI Controller Registers
27 #define SPI_CLOCKDIV 0x0010
28 #define SPI_MODESELECT 0x0018
29 #define SPI_CONFIGDATA 0x0020
30 #define SPI_STA_MODE_CHANGE 0x0028
31 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
32 #define SPI_FAST_SEQ_ADD1 0x0104
33 #define SPI_FAST_SEQ_ADD2 0x0108
34 #define SPI_FAST_SEQ_ADD_CFG 0x010c
35 #define SPI_FAST_SEQ_OPC1 0x0110
36 #define SPI_FAST_SEQ_OPC2 0x0114
37 #define SPI_FAST_SEQ_OPC3 0x0118
38 #define SPI_FAST_SEQ_OPC4 0x011c
39 #define SPI_FAST_SEQ_OPC5 0x0120
40 #define SPI_MODE_BITS 0x0124
41 #define SPI_DUMMY_BITS 0x0128
42 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
43 #define SPI_FAST_SEQ_1 0x0130
44 #define SPI_FAST_SEQ_2 0x0134
45 #define SPI_FAST_SEQ_3 0x0138
46 #define SPI_FAST_SEQ_4 0x013c
47 #define SPI_FAST_SEQ_CFG 0x0140
48 #define SPI_FAST_SEQ_STA 0x0144
49 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
50 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
51 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
52 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
53 #define SPI_PROGRAM_ERASE_TIME 0x0158
54 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
55 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
56 #define SPI_STATUS_WR_TIME_REG 0x0164
57 #define SPI_FAST_SEQ_DATA_REG 0x0300
60 * Register: SPI_MODESELECT
62 #define SPI_MODESELECT_CONTIG 0x01
63 #define SPI_MODESELECT_FASTREAD 0x02
64 #define SPI_MODESELECT_DUALIO 0x04
65 #define SPI_MODESELECT_FSM 0x08
66 #define SPI_MODESELECT_QUADBOOT 0x10
69 * Register: SPI_CONFIGDATA
71 #define SPI_CFG_DEVICE_ST 0x1
72 #define SPI_CFG_DEVICE_ATMEL 0x4
73 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
74 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
75 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
77 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA)
78 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0)
79 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00)
82 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
84 #define TRANSFER_SIZE(x) ((x) * 8)
87 * Register: SPI_FAST_SEQ_ADD_CFG
89 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
90 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
91 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
92 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
93 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
94 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
95 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
96 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
97 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
98 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
101 * Register: SPI_FAST_SEQ_n
103 #define SEQ_OPC_OPCODE(x) ((x) << 0)
104 #define SEQ_OPC_CYCLES(x) ((x) << 8)
105 #define SEQ_OPC_PADS_1 (0x0 << 14)
106 #define SEQ_OPC_PADS_2 (0x1 << 14)
107 #define SEQ_OPC_PADS_4 (0x3 << 14)
108 #define SEQ_OPC_CSDEASSERT (1 << 16)
111 * Register: SPI_FAST_SEQ_CFG
113 #define SEQ_CFG_STARTSEQ (1 << 0)
114 #define SEQ_CFG_SWRESET (1 << 5)
115 #define SEQ_CFG_CSDEASSERT (1 << 6)
116 #define SEQ_CFG_READNOTWRITE (1 << 7)
117 #define SEQ_CFG_ERASE (1 << 8)
118 #define SEQ_CFG_PADS_1 (0x0 << 16)
119 #define SEQ_CFG_PADS_2 (0x1 << 16)
120 #define SEQ_CFG_PADS_4 (0x3 << 16)
123 * Register: SPI_MODE_BITS
125 #define MODE_DATA(x) (x & 0xff)
126 #define MODE_CYCLES(x) ((x & 0x3f) << 16)
127 #define MODE_PADS_1 (0x0 << 22)
128 #define MODE_PADS_2 (0x1 << 22)
129 #define MODE_PADS_4 (0x3 << 22)
130 #define DUMMY_CSDEASSERT (1 << 24)
133 * Register: SPI_DUMMY_BITS
135 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16)
136 #define DUMMY_PADS_1 (0x0 << 22)
137 #define DUMMY_PADS_2 (0x1 << 22)
138 #define DUMMY_PADS_4 (0x3 << 22)
139 #define DUMMY_CSDEASSERT (1 << 24)
142 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
144 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0)
145 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8)
146 #define STA_PADS_1 (0x0 << 16)
147 #define STA_PADS_2 (0x1 << 16)
148 #define STA_PADS_4 (0x3 << 16)
149 #define STA_CSDEASSERT (0x1 << 20)
150 #define STA_RDNOTWR (0x1 << 21)
153 * FSM SPI Instruction Opcodes
155 #define STFSM_OPC_CMD 0x1
156 #define STFSM_OPC_ADD 0x2
157 #define STFSM_OPC_STA 0x3
158 #define STFSM_OPC_MODE 0x4
159 #define STFSM_OPC_DUMMY 0x5
160 #define STFSM_OPC_DATA 0x6
161 #define STFSM_OPC_WAIT 0x7
162 #define STFSM_OPC_JUMP 0x8
163 #define STFSM_OPC_GOTO 0x9
164 #define STFSM_OPC_STOP 0xF
167 * FSM SPI Instructions (== opcode + operand).
169 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
171 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1)
172 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2)
173 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3)
174 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4)
175 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5)
176 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1)
177 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2)
179 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1)
180 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2)
182 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
183 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
184 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2)
185 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3)
187 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0)
188 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0)
189 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
190 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
192 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */
193 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
195 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
197 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */
202 struct resource *region;
206 uint32_t fifo_dir_delay;
220 } __packed __aligned(4);
222 static inline int stfsm_is_idle(struct stfsm *fsm)
224 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
227 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
229 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
232 static void stfsm_clear_fifo(struct stfsm *fsm)
237 avail = stfsm_fifo_available(fsm);
242 readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
248 static inline void stfsm_load_seq(struct stfsm *fsm,
249 const struct stfsm_seq *seq)
251 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
252 const uint32_t *src = (const uint32_t *)seq;
253 int words = sizeof(*seq) / sizeof(*src);
255 BUG_ON(!stfsm_is_idle(fsm));
264 static void stfsm_wait_seq(struct stfsm *fsm)
266 unsigned long deadline;
269 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
272 if (time_after_eq(jiffies, deadline))
275 if (stfsm_is_idle(fsm))
281 dev_err(fsm->dev, "timeout on sequence completion\n");
284 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
287 uint32_t remaining = size >> 2;
291 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
293 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
297 avail = stfsm_fifo_available(fsm);
302 words = min(avail, remaining);
305 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
310 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
312 int ret, timeout = 10;
314 /* Wait for controller to accept mode change */
316 ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
325 writel(mode, fsm->base + SPI_MODESELECT);
330 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
335 /* TODO: Make this dynamic */
336 emi_freq = STFSM_DEFAULT_EMI_FREQ;
339 * Calculate clk_div - values between 2 and 128
340 * Multiple of 2, rounded up
342 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
345 else if (clk_div > 128)
349 * Determine a suitable delay for the IP to complete a change of
350 * direction of the FIFO. The required delay is related to the clock
351 * divider used. The following heuristics are based on empirical tests,
352 * using a 100MHz EMI clock.
355 fsm->fifo_dir_delay = 0;
356 else if (clk_div <= 10)
357 fsm->fifo_dir_delay = 1;
359 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
361 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
362 emi_freq, spi_freq, clk_div);
364 writel(clk_div, fsm->base + SPI_CLOCKDIV);
367 static int stfsm_init(struct stfsm *fsm)
371 /* Perform a soft reset of the FSM controller */
372 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
374 writel(0, fsm->base + SPI_FAST_SEQ_CFG);
376 /* Set clock to 'safe' frequency initially */
377 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
380 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
384 /* Set timing parameters */
385 writel(SPI_CFG_DEVICE_ST |
386 SPI_CFG_DEFAULT_MIN_CS_HIGH |
387 SPI_CFG_DEFAULT_CS_SETUPHOLD |
388 SPI_CFG_DEFAULT_DATA_HOLD,
389 fsm->base + SPI_CONFIGDATA);
390 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
392 /* Clear FIFO, just in case */
393 stfsm_clear_fifo(fsm);
398 static int stfsm_probe(struct platform_device *pdev)
400 struct device_node *np = pdev->dev.of_node;
401 struct resource *res;
406 dev_err(&pdev->dev, "No DT found\n");
410 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
414 fsm->dev = &pdev->dev;
416 platform_set_drvdata(pdev, fsm);
418 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 dev_err(&pdev->dev, "Resource not found\n");
424 fsm->base = devm_ioremap_resource(&pdev->dev, res);
425 if (IS_ERR(fsm->base)) {
427 "Failed to reserve memory region %pR\n", res);
428 return PTR_ERR(fsm->base);
431 mutex_init(&fsm->lock);
433 ret = stfsm_init(fsm);
435 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
439 fsm->mtd.dev.parent = &pdev->dev;
440 fsm->mtd.type = MTD_NORFLASH;
441 fsm->mtd.writesize = 4;
442 fsm->mtd.writebufsize = fsm->mtd.writesize;
443 fsm->mtd.flags = MTD_CAP_NORFLASH;
445 return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
448 static int stfsm_remove(struct platform_device *pdev)
450 struct stfsm *fsm = platform_get_drvdata(pdev);
453 err = mtd_device_unregister(&fsm->mtd);
460 static struct of_device_id stfsm_match[] = {
461 { .compatible = "st,spi-fsm", },
464 MODULE_DEVICE_TABLE(of, stfsm_match);
466 static struct platform_driver stfsm_driver = {
467 .probe = stfsm_probe,
468 .remove = stfsm_remove,
470 .name = "st-spi-fsm",
471 .owner = THIS_MODULE,
472 .of_match_table = stfsm_match,
475 module_platform_driver(stfsm_driver);
477 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
478 MODULE_DESCRIPTION("ST SPI FSM driver");
479 MODULE_LICENSE("GPL");