2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
4 * Author: Angus Clark <angus.clark@st.com>
6 * Copyright (C) 2010-2014 STicroelectronics Limited
8 * JEDEC probe based on drivers/mtd/devices/m25p80.c
10 * This code is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/sched.h>
20 #include <linux/delay.h>
24 #include "serial_flash_cmds.h"
27 * FSM SPI Controller Registers
29 #define SPI_CLOCKDIV 0x0010
30 #define SPI_MODESELECT 0x0018
31 #define SPI_CONFIGDATA 0x0020
32 #define SPI_STA_MODE_CHANGE 0x0028
33 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100
34 #define SPI_FAST_SEQ_ADD1 0x0104
35 #define SPI_FAST_SEQ_ADD2 0x0108
36 #define SPI_FAST_SEQ_ADD_CFG 0x010c
37 #define SPI_FAST_SEQ_OPC1 0x0110
38 #define SPI_FAST_SEQ_OPC2 0x0114
39 #define SPI_FAST_SEQ_OPC3 0x0118
40 #define SPI_FAST_SEQ_OPC4 0x011c
41 #define SPI_FAST_SEQ_OPC5 0x0120
42 #define SPI_MODE_BITS 0x0124
43 #define SPI_DUMMY_BITS 0x0128
44 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c
45 #define SPI_FAST_SEQ_1 0x0130
46 #define SPI_FAST_SEQ_2 0x0134
47 #define SPI_FAST_SEQ_3 0x0138
48 #define SPI_FAST_SEQ_4 0x013c
49 #define SPI_FAST_SEQ_CFG 0x0140
50 #define SPI_FAST_SEQ_STA 0x0144
51 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148
52 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c
53 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150
54 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154
55 #define SPI_PROGRAM_ERASE_TIME 0x0158
56 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c
57 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160
58 #define SPI_STATUS_WR_TIME_REG 0x0164
59 #define SPI_FAST_SEQ_DATA_REG 0x0300
62 * Register: SPI_MODESELECT
64 #define SPI_MODESELECT_CONTIG 0x01
65 #define SPI_MODESELECT_FASTREAD 0x02
66 #define SPI_MODESELECT_DUALIO 0x04
67 #define SPI_MODESELECT_FSM 0x08
68 #define SPI_MODESELECT_QUADBOOT 0x10
71 * Register: SPI_CONFIGDATA
73 #define SPI_CFG_DEVICE_ST 0x1
74 #define SPI_CFG_DEVICE_ATMEL 0x4
75 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4)
76 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16)
77 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24)
79 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA)
80 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0)
81 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00)
84 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
86 #define TRANSFER_SIZE(x) ((x) * 8)
89 * Register: SPI_FAST_SEQ_ADD_CFG
91 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0)
92 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6)
93 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6)
94 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6)
95 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8)
96 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16))
97 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16))
98 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16))
99 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16))
100 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16))
103 * Register: SPI_FAST_SEQ_n
105 #define SEQ_OPC_OPCODE(x) ((x) << 0)
106 #define SEQ_OPC_CYCLES(x) ((x) << 8)
107 #define SEQ_OPC_PADS_1 (0x0 << 14)
108 #define SEQ_OPC_PADS_2 (0x1 << 14)
109 #define SEQ_OPC_PADS_4 (0x3 << 14)
110 #define SEQ_OPC_CSDEASSERT (1 << 16)
113 * Register: SPI_FAST_SEQ_CFG
115 #define SEQ_CFG_STARTSEQ (1 << 0)
116 #define SEQ_CFG_SWRESET (1 << 5)
117 #define SEQ_CFG_CSDEASSERT (1 << 6)
118 #define SEQ_CFG_READNOTWRITE (1 << 7)
119 #define SEQ_CFG_ERASE (1 << 8)
120 #define SEQ_CFG_PADS_1 (0x0 << 16)
121 #define SEQ_CFG_PADS_2 (0x1 << 16)
122 #define SEQ_CFG_PADS_4 (0x3 << 16)
125 * Register: SPI_MODE_BITS
127 #define MODE_DATA(x) (x & 0xff)
128 #define MODE_CYCLES(x) ((x & 0x3f) << 16)
129 #define MODE_PADS_1 (0x0 << 22)
130 #define MODE_PADS_2 (0x1 << 22)
131 #define MODE_PADS_4 (0x3 << 22)
132 #define DUMMY_CSDEASSERT (1 << 24)
135 * Register: SPI_DUMMY_BITS
137 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16)
138 #define DUMMY_PADS_1 (0x0 << 22)
139 #define DUMMY_PADS_2 (0x1 << 22)
140 #define DUMMY_PADS_4 (0x3 << 22)
141 #define DUMMY_CSDEASSERT (1 << 24)
144 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
146 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0)
147 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8)
148 #define STA_PADS_1 (0x0 << 16)
149 #define STA_PADS_2 (0x1 << 16)
150 #define STA_PADS_4 (0x3 << 16)
151 #define STA_CSDEASSERT (0x1 << 20)
152 #define STA_RDNOTWR (0x1 << 21)
155 * FSM SPI Instruction Opcodes
157 #define STFSM_OPC_CMD 0x1
158 #define STFSM_OPC_ADD 0x2
159 #define STFSM_OPC_STA 0x3
160 #define STFSM_OPC_MODE 0x4
161 #define STFSM_OPC_DUMMY 0x5
162 #define STFSM_OPC_DATA 0x6
163 #define STFSM_OPC_WAIT 0x7
164 #define STFSM_OPC_JUMP 0x8
165 #define STFSM_OPC_GOTO 0x9
166 #define STFSM_OPC_STOP 0xF
169 * FSM SPI Instructions (== opcode + operand).
171 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4))
173 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1)
174 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2)
175 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3)
176 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4)
177 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5)
178 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1)
179 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2)
181 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1)
182 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2)
184 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
185 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1)
186 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2)
187 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3)
189 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0)
190 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0)
191 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0)
192 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0)
194 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */
195 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
197 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */
199 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */
204 struct resource *region;
207 struct flash_info *info;
209 uint32_t fifo_dir_delay;
223 } __packed __aligned(4);
225 /* Parameters to configure a READ or WRITE FSM sequence */
226 struct seq_rw_config {
227 uint32_t flags; /* flags to support config */
228 uint8_t cmd; /* FLASH command */
229 int write; /* Write Sequence */
230 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */
231 uint8_t data_pads; /* No. of data pads */
232 uint8_t mode_data; /* MODE data */
233 uint8_t mode_cycles; /* No. of MODE cycles */
234 uint8_t dummy_cycles; /* No. of DUMMY cycles */
237 /* SPI Flash Device Table */
241 * JEDEC id zero means "no ID" (most older chips); otherwise it has
242 * a high byte of zero plus three data bytes: the manufacturer id,
243 * then a two byte device id.
248 * The size listed here is what works with FLASH_CMD_SE, which isn't
249 * necessarily called a "sector" by the vendor.
251 unsigned sector_size;
255 * Note, where FAST_READ is supported, freq_max specifies the
256 * FAST_READ frequency, not the READ frequency.
259 int (*config)(struct stfsm *);
262 static struct flash_info flash_types[] = {
264 * ST Microelectronics/Numonyx --
265 * (newer production versions may have feature updates
266 * (eg faster operating frequency)
268 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
269 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL },
270 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL },
271 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL },
272 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL },
273 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL },
274 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL },
276 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \
277 FLASH_FLAG_READ_FAST | \
278 FLASH_FLAG_READ_1_1_2 | \
279 FLASH_FLAG_WRITE_1_1_2)
280 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL },
281 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL },
283 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \
284 FLASH_FLAG_READ_FAST | \
285 FLASH_FLAG_READ_1_1_2 | \
286 FLASH_FLAG_READ_1_2_2 | \
287 FLASH_FLAG_READ_1_1_4 | \
288 FLASH_FLAG_READ_1_4_4 | \
291 { "mx25l25635e", 0xc22019, 0, 64*1024, 512,
292 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, NULL }
294 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \
295 FLASH_FLAG_READ_FAST | \
296 FLASH_FLAG_READ_1_1_2 | \
297 FLASH_FLAG_READ_1_2_2 | \
298 FLASH_FLAG_READ_1_1_4 | \
299 FLASH_FLAG_READ_1_4_4 | \
300 FLASH_FLAG_WRITE_1_1_2 | \
301 FLASH_FLAG_WRITE_1_2_2 | \
302 FLASH_FLAG_WRITE_1_1_4 | \
303 FLASH_FLAG_WRITE_1_4_4)
304 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, NULL },
305 { "n25q256", 0x20ba19, 0, 64 * 1024, 512,
306 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, NULL },
310 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
312 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \
313 FLASH_FLAG_READ_1_1_2 | \
314 FLASH_FLAG_READ_1_2_2 | \
315 FLASH_FLAG_READ_1_1_4 | \
316 FLASH_FLAG_READ_1_4_4 | \
317 FLASH_FLAG_WRITE_1_1_4 | \
318 FLASH_FLAG_READ_FAST)
319 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80,
321 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80,
326 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
327 * - RESET# signal supported by die but not bristled out on all
328 * package types. The package type is a function of board design,
329 * so this information is captured in the board's flags.
330 * - Supports 'DYB' sector protection. Depending on variant, sectors
331 * may default to locked state on power-on.
333 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \
335 FLASH_FLAG_DYB_LOCKING)
336 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80,
338 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80,
340 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
341 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
342 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512,
343 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, NULL },
345 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
346 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \
347 FLASH_FLAG_READ_FAST | \
348 FLASH_FLAG_READ_1_1_2 | \
349 FLASH_FLAG_WRITE_1_1_2)
350 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL },
351 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL },
352 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL },
353 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL },
354 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL },
356 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
357 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \
358 FLASH_FLAG_READ_FAST | \
359 FLASH_FLAG_READ_1_1_2 | \
360 FLASH_FLAG_READ_1_2_2 | \
361 FLASH_FLAG_READ_1_1_4 | \
362 FLASH_FLAG_READ_1_4_4 | \
363 FLASH_FLAG_WRITE_1_1_4)
364 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, NULL },
365 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, NULL },
366 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, NULL },
367 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, NULL },
370 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
373 static struct stfsm_seq stfsm_seq_read_jedec = {
374 .data_size = TRANSFER_SIZE(8),
375 .seq_opc[0] = (SEQ_OPC_PADS_1 |
377 SEQ_OPC_OPCODE(FLASH_CMD_RDID)),
380 STFSM_INST_DATA_READ,
383 .seq_cfg = (SEQ_CFG_PADS_1 |
384 SEQ_CFG_READNOTWRITE |
389 static inline int stfsm_is_idle(struct stfsm *fsm)
391 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
394 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
396 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
399 static void stfsm_clear_fifo(struct stfsm *fsm)
404 avail = stfsm_fifo_available(fsm);
409 readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
415 static inline void stfsm_load_seq(struct stfsm *fsm,
416 const struct stfsm_seq *seq)
418 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
419 const uint32_t *src = (const uint32_t *)seq;
420 int words = sizeof(*seq) / sizeof(*src);
422 BUG_ON(!stfsm_is_idle(fsm));
431 static void stfsm_wait_seq(struct stfsm *fsm)
433 unsigned long deadline;
436 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
439 if (time_after_eq(jiffies, deadline))
442 if (stfsm_is_idle(fsm))
448 dev_err(fsm->dev, "timeout on sequence completion\n");
451 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf,
454 uint32_t remaining = size >> 2;
458 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
460 BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3));
464 avail = stfsm_fifo_available(fsm);
469 words = min(avail, remaining);
472 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
477 /* Search for preferred configuration based on available flags */
478 static struct seq_rw_config *
479 stfsm_search_seq_rw_configs(struct stfsm *fsm,
480 struct seq_rw_config cfgs[])
482 struct seq_rw_config *config;
483 int flags = fsm->info->flags;
485 for (config = cfgs; config->cmd != 0; config++)
486 if ((config->flags & flags) == config->flags)
492 /* Prepare a READ/WRITE sequence according to configuration parameters */
493 static void stfsm_prepare_rw_seq(struct stfsm *fsm,
494 struct stfsm_seq *seq,
495 struct seq_rw_config *cfg)
497 int addr1_cycles, addr2_cycles;
500 memset(seq, 0, sizeof(*seq));
502 /* Add READ/WRITE OPC */
503 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
505 SEQ_OPC_OPCODE(cfg->cmd));
507 /* Add WREN OPC for a WRITE sequence */
509 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
511 SEQ_OPC_OPCODE(FLASH_CMD_WREN) |
514 /* Address configuration (24 or 32-bit addresses) */
515 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
516 addr1_cycles /= cfg->addr_pads;
517 addr2_cycles = 16 / cfg->addr_pads;
518 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */
519 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */
520 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */
521 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */
523 /* Data/Sequence configuration */
524 seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
528 seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
530 /* Mode configuration (no. of pads taken from addr cfg) */
531 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */
532 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */
533 (cfg->addr_pads - 1) << 22); /* pads */
535 /* Dummy configuration (no. of pads taken from addr cfg) */
536 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */
537 (cfg->addr_pads - 1) << 22); /* pads */
540 /* Instruction sequence */
543 seq->seq[i++] = STFSM_INST_CMD2;
545 seq->seq[i++] = STFSM_INST_CMD1;
547 seq->seq[i++] = STFSM_INST_ADD1;
548 seq->seq[i++] = STFSM_INST_ADD2;
550 if (cfg->mode_cycles)
551 seq->seq[i++] = STFSM_INST_MODE;
553 if (cfg->dummy_cycles)
554 seq->seq[i++] = STFSM_INST_DUMMY;
557 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
558 seq->seq[i++] = STFSM_INST_STOP;
561 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *const jedec)
563 const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
566 stfsm_load_seq(fsm, seq);
568 stfsm_read_fifo(fsm, tmp, 8);
570 memcpy(jedec, tmp, 5);
575 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
577 struct flash_info *info;
582 stfsm_read_jedec(fsm, id);
584 jedec = id[0] << 16 | id[1] << 8 | id[2];
586 * JEDEC also defines an optional "extended device information"
587 * string for after vendor-specific data, after the three bytes
588 * we use here. Supporting some chips might require using it.
590 ext_jedec = id[3] << 8 | id[4];
592 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%02x %02x %02x %02x %02x]\n",
593 jedec, id[0], id[1], id[2], id[3], id[4]);
595 for (info = flash_types; info->name; info++) {
596 if (info->jedec_id == jedec) {
597 if (info->ext_id && info->ext_id != ext_jedec)
602 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
607 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
609 int ret, timeout = 10;
611 /* Wait for controller to accept mode change */
613 ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
622 writel(mode, fsm->base + SPI_MODESELECT);
627 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
632 /* TODO: Make this dynamic */
633 emi_freq = STFSM_DEFAULT_EMI_FREQ;
636 * Calculate clk_div - values between 2 and 128
637 * Multiple of 2, rounded up
639 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
642 else if (clk_div > 128)
646 * Determine a suitable delay for the IP to complete a change of
647 * direction of the FIFO. The required delay is related to the clock
648 * divider used. The following heuristics are based on empirical tests,
649 * using a 100MHz EMI clock.
652 fsm->fifo_dir_delay = 0;
653 else if (clk_div <= 10)
654 fsm->fifo_dir_delay = 1;
656 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
658 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
659 emi_freq, spi_freq, clk_div);
661 writel(clk_div, fsm->base + SPI_CLOCKDIV);
664 static int stfsm_init(struct stfsm *fsm)
668 /* Perform a soft reset of the FSM controller */
669 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
671 writel(0, fsm->base + SPI_FAST_SEQ_CFG);
673 /* Set clock to 'safe' frequency initially */
674 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
677 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
681 /* Set timing parameters */
682 writel(SPI_CFG_DEVICE_ST |
683 SPI_CFG_DEFAULT_MIN_CS_HIGH |
684 SPI_CFG_DEFAULT_CS_SETUPHOLD |
685 SPI_CFG_DEFAULT_DATA_HOLD,
686 fsm->base + SPI_CONFIGDATA);
687 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
689 /* Clear FIFO, just in case */
690 stfsm_clear_fifo(fsm);
695 static int stfsm_probe(struct platform_device *pdev)
697 struct device_node *np = pdev->dev.of_node;
698 struct flash_info *info;
699 struct resource *res;
704 dev_err(&pdev->dev, "No DT found\n");
708 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
712 fsm->dev = &pdev->dev;
714 platform_set_drvdata(pdev, fsm);
716 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
718 dev_err(&pdev->dev, "Resource not found\n");
722 fsm->base = devm_ioremap_resource(&pdev->dev, res);
723 if (IS_ERR(fsm->base)) {
725 "Failed to reserve memory region %pR\n", res);
726 return PTR_ERR(fsm->base);
729 mutex_init(&fsm->lock);
731 ret = stfsm_init(fsm);
733 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
737 /* Detect SPI FLASH device */
738 info = stfsm_jedec_probe(fsm);
743 /* Use device size to determine address width */
744 if (info->sector_size * info->n_sectors > 0x1000000)
745 info->flags |= FLASH_FLAG_32BIT_ADDR;
747 fsm->mtd.dev.parent = &pdev->dev;
748 fsm->mtd.type = MTD_NORFLASH;
749 fsm->mtd.writesize = 4;
750 fsm->mtd.writebufsize = fsm->mtd.writesize;
751 fsm->mtd.flags = MTD_CAP_NORFLASH;
752 fsm->mtd.size = info->sector_size * info->n_sectors;
753 fsm->mtd.erasesize = info->sector_size;
756 "Found serial flash device: %s\n"
757 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
759 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
760 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
762 return mtd_device_parse_register(&fsm->mtd, NULL, NULL, NULL, 0);
765 static int stfsm_remove(struct platform_device *pdev)
767 struct stfsm *fsm = platform_get_drvdata(pdev);
770 err = mtd_device_unregister(&fsm->mtd);
777 static struct of_device_id stfsm_match[] = {
778 { .compatible = "st,spi-fsm", },
781 MODULE_DEVICE_TABLE(of, stfsm_match);
783 static struct platform_driver stfsm_driver = {
784 .probe = stfsm_probe,
785 .remove = stfsm_remove,
787 .name = "st-spi-fsm",
788 .owner = THIS_MODULE,
789 .of_match_table = stfsm_match,
792 module_platform_driver(stfsm_driver);
794 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
795 MODULE_DESCRIPTION("ST SPI FSM driver");
796 MODULE_LICENSE("GPL");