2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_mtd.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
48 #include <linux/platform_data/atmel.h>
50 static int use_dma = 1;
51 module_param(use_dma, int, 0);
53 static int on_flash_bbt = 0;
54 module_param(on_flash_bbt, int, 0);
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
70 static struct nand_ecclayout atmel_oobinfo_large = {
72 .eccpos = {60, 61, 62, 63},
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
83 static struct nand_ecclayout atmel_oobinfo_small = {
85 .eccpos = {0, 1, 2, 3},
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
100 struct completion comp_nfc;
102 /* Point to the sram bank which include readed data via NFC */
103 void __iomem *data_in_sram;
104 bool will_write_sram;
106 static struct atmel_nfc nand_nfc;
108 struct atmel_nand_host {
109 struct nand_chip nand_chip;
111 void __iomem *io_base;
113 struct atmel_nand_data board;
117 struct completion comp;
118 struct dma_chan *dma_chan;
120 struct atmel_nfc *nfc;
124 u16 pmecc_sector_size;
125 u32 pmecc_lookup_table_offset;
126 u32 pmecc_lookup_table_offset_512;
127 u32 pmecc_lookup_table_offset_1024;
129 int pmecc_bytes_per_sector;
130 int pmecc_sector_number;
131 int pmecc_degree; /* Degree of remainders */
132 int pmecc_cw_len; /* Length of codeword */
134 void __iomem *pmerrloc_base;
135 void __iomem *pmecc_rom_base;
137 /* lookup table for alpha_to and index_of */
138 void __iomem *pmecc_alpha_to;
139 void __iomem *pmecc_index_of;
141 /* data for pmecc computation */
142 int16_t *pmecc_partial_syn;
144 int16_t *pmecc_smu; /* Sigma table */
145 int16_t *pmecc_lmu; /* polynomal order */
151 static struct nand_ecclayout atmel_pmecc_oobinfo;
156 static void atmel_nand_enable(struct atmel_nand_host *host)
158 if (gpio_is_valid(host->board.enable_pin))
159 gpio_set_value(host->board.enable_pin, 0);
165 static void atmel_nand_disable(struct atmel_nand_host *host)
167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 1);
172 * Hardware specific access to control-lines
174 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
176 struct nand_chip *nand_chip = mtd->priv;
177 struct atmel_nand_host *host = nand_chip->priv;
179 if (ctrl & NAND_CTRL_CHANGE) {
181 atmel_nand_enable(host);
183 atmel_nand_disable(host);
185 if (cmd == NAND_CMD_NONE)
189 writeb(cmd, host->io_base + (1 << host->board.cle));
191 writeb(cmd, host->io_base + (1 << host->board.ale));
195 * Read the Device Ready pin.
197 static int atmel_nand_device_ready(struct mtd_info *mtd)
199 struct nand_chip *nand_chip = mtd->priv;
200 struct atmel_nand_host *host = nand_chip->priv;
202 return gpio_get_value(host->board.rdy_pin) ^
203 !!host->board.rdy_pin_active_low;
206 /* Set up for hardware ready pin and enable pin. */
207 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
209 struct nand_chip *chip = mtd->priv;
210 struct atmel_nand_host *host = chip->priv;
213 if (gpio_is_valid(host->board.rdy_pin)) {
214 res = devm_gpio_request(host->dev,
215 host->board.rdy_pin, "nand_rdy");
218 "can't request rdy gpio %d\n",
219 host->board.rdy_pin);
223 res = gpio_direction_input(host->board.rdy_pin);
226 "can't request input direction rdy gpio %d\n",
227 host->board.rdy_pin);
231 chip->dev_ready = atmel_nand_device_ready;
234 if (gpio_is_valid(host->board.enable_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.enable_pin, "nand_enable");
239 "can't request enable gpio %d\n",
240 host->board.enable_pin);
244 res = gpio_direction_output(host->board.enable_pin, 1);
247 "can't request output direction enable gpio %d\n",
248 host->board.enable_pin);
256 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
260 const __iomem u32 *s = src;
262 for (i = 0; i < (size >> 2); i++)
263 *t++ = readl_relaxed(s++);
266 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
269 u32 __iomem *t = trg;
272 for (i = 0; i < (size >> 2); i++)
273 writel_relaxed(*s++, t++);
277 * Minimal-overhead PIO for data access.
279 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
281 struct nand_chip *nand_chip = mtd->priv;
282 struct atmel_nand_host *host = nand_chip->priv;
284 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286 host->nfc->data_in_sram += len;
288 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
292 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
294 struct nand_chip *nand_chip = mtd->priv;
295 struct atmel_nand_host *host = nand_chip->priv;
297 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299 host->nfc->data_in_sram += len;
301 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
305 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
307 struct nand_chip *nand_chip = mtd->priv;
309 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
312 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
314 struct nand_chip *nand_chip = mtd->priv;
316 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
319 static void dma_complete_func(void *completion)
321 complete(completion);
324 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
326 /* NFC only has two banks. Must be 0 or 1 */
331 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332 if (host->mtd.writesize > 2048)
334 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
342 static uint nfc_get_sram_off(struct atmel_nand_host *host)
344 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345 return NFC_SRAM_BANK1_OFFSET;
350 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
355 return host->nfc->sram_bank0_phys;
358 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
361 struct dma_device *dma_dev;
362 enum dma_ctrl_flags flags;
363 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364 struct dma_async_tx_descriptor *tx = NULL;
366 struct nand_chip *chip = mtd->priv;
367 struct atmel_nand_host *host = chip->priv;
370 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
371 struct atmel_nfc *nfc = host->nfc;
373 if (buf >= high_memory)
376 dma_dev = host->dma_chan->device;
378 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
379 DMA_COMPL_SKIP_DEST_UNMAP;
381 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
382 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
383 dev_err(host->dev, "Failed to dma_map_single\n");
388 if (nfc && nfc->data_in_sram)
389 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
390 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
392 dma_src_addr = host->io_phys;
394 dma_dst_addr = phys_addr;
396 dma_src_addr = phys_addr;
398 if (nfc && nfc->write_by_sram)
399 dma_dst_addr = nfc_sram_phys(host);
401 dma_dst_addr = host->io_phys;
404 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
405 dma_src_addr, len, flags);
407 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
411 init_completion(&host->comp);
412 tx->callback = dma_complete_func;
413 tx->callback_param = &host->comp;
415 cookie = tx->tx_submit(tx);
416 if (dma_submit_error(cookie)) {
417 dev_err(host->dev, "Failed to do DMA tx_submit\n");
421 dma_async_issue_pending(host->dma_chan);
422 wait_for_completion(&host->comp);
424 if (is_read && nfc && nfc->data_in_sram)
425 /* After read data from SRAM, need to increase the position */
426 nfc->data_in_sram += len;
431 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
434 dev_warn(host->dev, "Fall back to CPU I/O\n");
438 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
440 struct nand_chip *chip = mtd->priv;
441 struct atmel_nand_host *host = chip->priv;
443 if (use_dma && len > mtd->oobsize)
444 /* only use DMA for bigger than oob size: better performances */
445 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
448 if (host->board.bus_width_16)
449 atmel_read_buf16(mtd, buf, len);
451 atmel_read_buf8(mtd, buf, len);
454 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
456 struct nand_chip *chip = mtd->priv;
457 struct atmel_nand_host *host = chip->priv;
459 if (use_dma && len > mtd->oobsize)
460 /* only use DMA for bigger than oob size: better performances */
461 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
464 if (host->board.bus_width_16)
465 atmel_write_buf16(mtd, buf, len);
467 atmel_write_buf8(mtd, buf, len);
471 * Return number of ecc bytes per sector according to sector size and
472 * correction capability
474 * Following table shows what at91 PMECC supported:
475 * Correction Capability Sector_512_bytes Sector_1024_bytes
476 * ===================== ================ =================
477 * 2-bits 4-bytes 4-bytes
478 * 4-bits 7-bytes 7-bytes
479 * 8-bits 13-bytes 14-bytes
480 * 12-bits 20-bytes 21-bytes
481 * 24-bits 39-bytes 42-bytes
483 static int pmecc_get_ecc_bytes(int cap, int sector_size)
485 int m = 12 + sector_size / 512;
486 return (m * cap + 7) / 8;
489 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
490 int oobsize, int ecc_len)
494 layout->eccbytes = ecc_len;
496 /* ECC will occupy the last ecc_len bytes continuously */
497 for (i = 0; i < ecc_len; i++)
498 layout->eccpos[i] = oobsize - ecc_len + i;
500 layout->oobfree[0].offset = 2;
501 layout->oobfree[0].length =
502 oobsize - ecc_len - layout->oobfree[0].offset;
505 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
509 table_size = host->pmecc_sector_size == 512 ?
510 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
512 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
513 table_size * sizeof(int16_t);
516 static int pmecc_data_alloc(struct atmel_nand_host *host)
518 const int cap = host->pmecc_corr_cap;
521 size = (2 * cap + 1) * sizeof(int16_t);
522 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
523 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
524 host->pmecc_lmu = devm_kzalloc(host->dev,
525 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
526 host->pmecc_smu = devm_kzalloc(host->dev,
527 (cap + 2) * size, GFP_KERNEL);
529 size = (cap + 1) * sizeof(int);
530 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
532 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
534 if (!host->pmecc_partial_syn ||
546 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
548 struct nand_chip *nand_chip = mtd->priv;
549 struct atmel_nand_host *host = nand_chip->priv;
553 /* Fill odd syndromes */
554 for (i = 0; i < host->pmecc_corr_cap; i++) {
555 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
559 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
563 static void pmecc_substitute(struct mtd_info *mtd)
565 struct nand_chip *nand_chip = mtd->priv;
566 struct atmel_nand_host *host = nand_chip->priv;
567 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
568 int16_t __iomem *index_of = host->pmecc_index_of;
569 int16_t *partial_syn = host->pmecc_partial_syn;
570 const int cap = host->pmecc_corr_cap;
574 /* si[] is a table that holds the current syndrome value,
575 * an element of that table belongs to the field
579 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
581 /* Computation 2t syndromes based on S(x) */
583 for (i = 1; i < 2 * cap; i += 2) {
584 for (j = 0; j < host->pmecc_degree; j++) {
585 if (partial_syn[i] & ((unsigned short)0x1 << j))
586 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
589 /* Even syndrome = (Odd syndrome) ** 2 */
590 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
596 tmp = readw_relaxed(index_of + si[j]);
597 tmp = (tmp * 2) % host->pmecc_cw_len;
598 si[i] = readw_relaxed(alpha_to + tmp);
605 static void pmecc_get_sigma(struct mtd_info *mtd)
607 struct nand_chip *nand_chip = mtd->priv;
608 struct atmel_nand_host *host = nand_chip->priv;
610 int16_t *lmu = host->pmecc_lmu;
611 int16_t *si = host->pmecc_si;
612 int *mu = host->pmecc_mu;
613 int *dmu = host->pmecc_dmu; /* Discrepancy */
614 int *delta = host->pmecc_delta; /* Delta order */
615 int cw_len = host->pmecc_cw_len;
616 const int16_t cap = host->pmecc_corr_cap;
617 const int num = 2 * cap + 1;
618 int16_t __iomem *index_of = host->pmecc_index_of;
619 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
621 uint32_t dmu_0_count, tmp;
622 int16_t *smu = host->pmecc_smu;
624 /* index of largest delta */
636 memset(smu, 0, sizeof(int16_t) * num);
639 /* discrepancy set to 1 */
641 /* polynom order set to 0 */
643 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
649 /* Sigma(x) set to 1 */
650 memset(&smu[num], 0, sizeof(int16_t) * num);
653 /* discrepancy set to S1 */
656 /* polynom order set to 0 */
659 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
661 /* Init the Sigma(x) last row */
662 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
664 for (i = 1; i <= cap; i++) {
666 /* Begin Computing Sigma (Mu+1) and L(mu) */
667 /* check if discrepancy is set to 0 */
671 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
672 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
677 if (dmu_0_count == tmp) {
678 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
679 smu[(cap + 1) * num + j] =
682 lmu[cap + 1] = lmu[i];
687 for (j = 0; j <= lmu[i] >> 1; j++)
688 smu[(i + 1) * num + j] = smu[i * num + j];
690 /* copy previous polynom order to the next */
695 /* find largest delta with dmu != 0 */
696 for (j = 0; j < i; j++) {
697 if ((dmu[j]) && (delta[j] > largest)) {
703 /* compute difference */
704 diff = (mu[i] - mu[ro]);
706 /* Compute degree of the new smu polynomial */
707 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
710 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
712 /* Init smu[i+1] with 0 */
713 for (k = 0; k < num; k++)
714 smu[(i + 1) * num + k] = 0;
716 /* Compute smu[i+1] */
717 for (k = 0; k <= lmu[ro] >> 1; k++) {
720 if (!(smu[ro * num + k] && dmu[i]))
722 a = readw_relaxed(index_of + dmu[i]);
723 b = readw_relaxed(index_of + dmu[ro]);
724 c = readw_relaxed(index_of + smu[ro * num + k]);
725 tmp = a + (cw_len - b) + c;
726 a = readw_relaxed(alpha_to + tmp % cw_len);
727 smu[(i + 1) * num + (k + diff)] = a;
730 for (k = 0; k <= lmu[i] >> 1; k++)
731 smu[(i + 1) * num + k] ^= smu[i * num + k];
734 /* End Computing Sigma (Mu+1) and L(mu) */
735 /* In either case compute delta */
736 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
738 /* Do not compute discrepancy for the last iteration */
742 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
745 dmu[i + 1] = si[tmp + 3];
746 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
748 a = readw_relaxed(index_of +
749 smu[(i + 1) * num + k]);
750 b = si[2 * (i - 1) + 3 - k];
751 c = readw_relaxed(index_of + b);
754 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
763 static int pmecc_err_location(struct mtd_info *mtd)
765 struct nand_chip *nand_chip = mtd->priv;
766 struct atmel_nand_host *host = nand_chip->priv;
767 unsigned long end_time;
768 const int cap = host->pmecc_corr_cap;
769 const int num = 2 * cap + 1;
770 int sector_size = host->pmecc_sector_size;
771 int err_nbr = 0; /* number of error */
772 int roots_nbr; /* number of roots */
775 int16_t *smu = host->pmecc_smu;
777 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
779 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
780 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
781 smu[(cap + 1) * num + i]);
785 val = (err_nbr - 1) << 16;
786 if (sector_size == 1024)
789 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
790 pmerrloc_writel(host->pmerrloc_base, ELEN,
791 sector_size * 8 + host->pmecc_degree * cap);
793 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
794 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
795 & PMERRLOC_CALC_DONE)) {
796 if (unlikely(time_after(jiffies, end_time))) {
797 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
803 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
804 & PMERRLOC_ERR_NUM_MASK) >> 8;
805 /* Number of roots == degree of smu hence <= cap */
806 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
809 /* Number of roots does not match the degree of smu
810 * unable to correct error */
814 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
815 int sector_num, int extra_bytes, int err_nbr)
817 struct nand_chip *nand_chip = mtd->priv;
818 struct atmel_nand_host *host = nand_chip->priv;
820 int byte_pos, bit_pos, sector_size, pos;
824 sector_size = host->pmecc_sector_size;
827 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
831 if (byte_pos >= (sector_size + extra_bytes))
832 BUG(); /* should never happen */
834 if (byte_pos < sector_size) {
835 err_byte = *(buf + byte_pos);
836 *(buf + byte_pos) ^= (1 << bit_pos);
838 pos = sector_num * host->pmecc_sector_size + byte_pos;
839 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
840 pos, bit_pos, err_byte, *(buf + byte_pos));
842 /* Bit flip in OOB area */
843 tmp = sector_num * host->pmecc_bytes_per_sector
844 + (byte_pos - sector_size);
846 ecc[tmp] ^= (1 << bit_pos);
848 pos = tmp + nand_chip->ecc.layout->eccpos[0];
849 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
850 pos, bit_pos, err_byte, ecc[tmp]);
860 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
863 struct nand_chip *nand_chip = mtd->priv;
864 struct atmel_nand_host *host = nand_chip->priv;
865 int i, err_nbr, eccbytes;
869 eccbytes = nand_chip->ecc.bytes;
870 for (i = 0; i < eccbytes; i++)
873 /* Erased page, return OK */
877 for (i = 0; i < host->pmecc_sector_number; i++) {
879 if (pmecc_stat & 0x1) {
880 buf_pos = buf + i * host->pmecc_sector_size;
882 pmecc_gen_syndrome(mtd, i);
883 pmecc_substitute(mtd);
884 pmecc_get_sigma(mtd);
886 err_nbr = pmecc_err_location(mtd);
888 dev_err(host->dev, "PMECC: Too many errors\n");
889 mtd->ecc_stats.failed++;
892 pmecc_correct_data(mtd, buf_pos, ecc, i,
893 host->pmecc_bytes_per_sector, err_nbr);
894 mtd->ecc_stats.corrected += err_nbr;
895 total_err += err_nbr;
904 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
908 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
909 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
914 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
915 val = pmecc_readl_relaxed(host->ecc, CFG);
917 if (ecc_op == NAND_ECC_READ)
918 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
919 | PMECC_CFG_AUTO_ENABLE);
921 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
922 & ~PMECC_CFG_AUTO_ENABLE);
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
925 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
928 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
929 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
931 struct atmel_nand_host *host = chip->priv;
932 int eccsize = chip->ecc.size;
933 uint8_t *oob = chip->oob_poi;
934 uint32_t *eccpos = chip->ecc.layout->eccpos;
936 unsigned long end_time;
939 if (!host->nfc || !host->nfc->use_nfc_sram)
940 pmecc_enable(host, NAND_ECC_READ);
942 chip->read_buf(mtd, buf, eccsize);
943 chip->read_buf(mtd, oob, mtd->oobsize);
945 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
946 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
947 if (unlikely(time_after(jiffies, end_time))) {
948 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
954 stat = pmecc_readl_relaxed(host->ecc, ISR);
956 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
958 /* uncorrectable errors */
965 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
966 struct nand_chip *chip, const uint8_t *buf, int oob_required)
968 struct atmel_nand_host *host = chip->priv;
969 uint32_t *eccpos = chip->ecc.layout->eccpos;
971 unsigned long end_time;
973 if (!host->nfc || !host->nfc->write_by_sram) {
974 pmecc_enable(host, NAND_ECC_WRITE);
975 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
978 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
979 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
980 if (unlikely(time_after(jiffies, end_time))) {
981 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
987 for (i = 0; i < host->pmecc_sector_number; i++) {
988 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
991 pos = i * host->pmecc_bytes_per_sector + j;
992 chip->oob_poi[eccpos[pos]] =
993 pmecc_readb_ecc_relaxed(host->ecc, i, j);
996 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1001 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003 struct nand_chip *nand_chip = mtd->priv;
1004 struct atmel_nand_host *host = nand_chip->priv;
1006 struct nand_ecclayout *ecc_layout;
1008 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1009 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1011 switch (host->pmecc_corr_cap) {
1013 val = PMECC_CFG_BCH_ERR2;
1016 val = PMECC_CFG_BCH_ERR4;
1019 val = PMECC_CFG_BCH_ERR8;
1022 val = PMECC_CFG_BCH_ERR12;
1025 val = PMECC_CFG_BCH_ERR24;
1029 if (host->pmecc_sector_size == 512)
1030 val |= PMECC_CFG_SECTOR512;
1031 else if (host->pmecc_sector_size == 1024)
1032 val |= PMECC_CFG_SECTOR1024;
1034 switch (host->pmecc_sector_number) {
1036 val |= PMECC_CFG_PAGE_1SECTOR;
1039 val |= PMECC_CFG_PAGE_2SECTORS;
1042 val |= PMECC_CFG_PAGE_4SECTORS;
1045 val |= PMECC_CFG_PAGE_8SECTORS;
1049 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1050 | PMECC_CFG_AUTO_DISABLE);
1051 pmecc_writel(host->ecc, CFG, val);
1053 ecc_layout = nand_chip->ecc.layout;
1054 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1055 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1056 pmecc_writel(host->ecc, EADDR,
1057 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1058 /* See datasheet about PMECC Clock Control Register */
1059 pmecc_writel(host->ecc, CLK, 2);
1060 pmecc_writel(host->ecc, IDR, 0xff);
1061 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1065 * Get ECC requirement in ONFI parameters, returns -1 if ONFI
1066 * parameters is not supported.
1067 * return 0 if success to get the ECC requirement.
1069 static int get_onfi_ecc_param(struct nand_chip *chip,
1070 int *ecc_bits, int *sector_size)
1072 *ecc_bits = *sector_size = 0;
1074 if (chip->onfi_params.ecc_bits == 0xff)
1075 /* TODO: the sector_size and ecc_bits need to be find in
1076 * extended ecc parameter, currently we don't support it.
1080 *ecc_bits = chip->onfi_params.ecc_bits;
1082 /* The default sector size (ecc codeword size) is 512 */
1089 * Get ecc requirement from ONFI parameters ecc requirement.
1090 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1091 * will set them according to ONFI ecc requirement. Otherwise, use the
1092 * value in DTS file.
1093 * return 0 if success. otherwise return error code.
1095 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1096 int *cap, int *sector_size)
1098 /* Get ECC requirement from ONFI parameters */
1099 *cap = *sector_size = 0;
1100 if (host->nand_chip.onfi_version) {
1101 if (!get_onfi_ecc_param(&host->nand_chip, cap, sector_size))
1102 dev_info(host->dev, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
1103 *cap, *sector_size);
1105 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
1107 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
1109 if (*cap == 0 && *sector_size == 0) {
1114 /* If dts file doesn't specify then use the one in ONFI parameters */
1115 if (host->pmecc_corr_cap == 0) {
1116 /* use the most fitable ecc bits (the near bigger one ) */
1118 host->pmecc_corr_cap = 2;
1120 host->pmecc_corr_cap = 4;
1122 host->pmecc_corr_cap = 8;
1123 else if (*cap <= 12)
1124 host->pmecc_corr_cap = 12;
1125 else if (*cap <= 24)
1126 host->pmecc_corr_cap = 24;
1130 if (host->pmecc_sector_size == 0) {
1131 /* use the most fitable sector size (the near smaller one ) */
1132 if (*sector_size >= 1024)
1133 host->pmecc_sector_size = 1024;
1134 else if (*sector_size >= 512)
1135 host->pmecc_sector_size = 512;
1142 static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev,
1143 struct atmel_nand_host *host)
1145 struct mtd_info *mtd = &host->mtd;
1146 struct nand_chip *nand_chip = &host->nand_chip;
1147 struct resource *regs, *regs_pmerr, *regs_rom;
1148 int cap, sector_size, err_no;
1150 err_no = pmecc_choose_ecc(host, &cap, §or_size);
1152 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1156 if (cap > host->pmecc_corr_cap ||
1157 sector_size != host->pmecc_sector_size)
1158 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1160 cap = host->pmecc_corr_cap;
1161 sector_size = host->pmecc_sector_size;
1162 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1163 host->pmecc_lookup_table_offset_512 :
1164 host->pmecc_lookup_table_offset_1024;
1166 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1169 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1172 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1173 nand_chip->ecc.mode = NAND_ECC_SOFT;
1177 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1178 if (IS_ERR(host->ecc)) {
1179 dev_err(host->dev, "ioremap failed\n");
1180 err_no = PTR_ERR(host->ecc);
1184 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1185 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1186 if (IS_ERR(host->pmerrloc_base)) {
1188 "Can not get I/O resource for PMECC ERRLOC controller!\n");
1189 err_no = PTR_ERR(host->pmerrloc_base);
1193 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1194 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1195 if (IS_ERR(host->pmecc_rom_base)) {
1196 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1197 err_no = PTR_ERR(host->pmecc_rom_base);
1201 /* ECC is calculated for the whole page (1 step) */
1202 nand_chip->ecc.size = mtd->writesize;
1204 /* set ECC page size and oob layout */
1205 switch (mtd->writesize) {
1207 host->pmecc_degree = (sector_size == 512) ?
1208 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1209 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1210 host->pmecc_sector_number = mtd->writesize / sector_size;
1211 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1213 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1214 host->pmecc_index_of = host->pmecc_rom_base +
1215 host->pmecc_lookup_table_offset;
1217 nand_chip->ecc.steps = 1;
1218 nand_chip->ecc.strength = cap;
1219 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1220 host->pmecc_sector_number;
1221 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1222 dev_err(host->dev, "No room for ECC bytes\n");
1226 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1228 nand_chip->ecc.bytes);
1229 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1236 "Unsupported page size for PMECC, use Software ECC\n");
1238 /* page size not handled by HW ECC */
1239 /* switching back to soft ECC */
1240 nand_chip->ecc.mode = NAND_ECC_SOFT;
1244 /* Allocate data for PMECC computation */
1245 err_no = pmecc_data_alloc(host);
1248 "Cannot allocate memory for PMECC computation!\n");
1252 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1253 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1255 atmel_pmecc_core_init(mtd);
1266 * function called after a write
1268 * mtd: MTD block structure
1269 * dat: raw data (unused)
1270 * ecc_code: buffer for ECC
1272 static int atmel_nand_calculate(struct mtd_info *mtd,
1273 const u_char *dat, unsigned char *ecc_code)
1275 struct nand_chip *nand_chip = mtd->priv;
1276 struct atmel_nand_host *host = nand_chip->priv;
1277 unsigned int ecc_value;
1279 /* get the first 2 ECC bytes */
1280 ecc_value = ecc_readl(host->ecc, PR);
1282 ecc_code[0] = ecc_value & 0xFF;
1283 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1285 /* get the last 2 ECC bytes */
1286 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1288 ecc_code[2] = ecc_value & 0xFF;
1289 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1295 * HW ECC read page function
1297 * mtd: mtd info structure
1298 * chip: nand chip info structure
1299 * buf: buffer to store read data
1300 * oob_required: caller expects OOB data read to chip->oob_poi
1302 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1303 uint8_t *buf, int oob_required, int page)
1305 int eccsize = chip->ecc.size;
1306 int eccbytes = chip->ecc.bytes;
1307 uint32_t *eccpos = chip->ecc.layout->eccpos;
1309 uint8_t *oob = chip->oob_poi;
1312 unsigned int max_bitflips = 0;
1315 * Errata: ALE is incorrectly wired up to the ECC controller
1316 * on the AP7000, so it will include the address cycles in the
1319 * Workaround: Reset the parity registers before reading the
1322 struct atmel_nand_host *host = chip->priv;
1323 if (host->board.need_reset_workaround)
1324 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1327 chip->read_buf(mtd, p, eccsize);
1329 /* move to ECC position if needed */
1330 if (eccpos[0] != 0) {
1331 /* This only works on large pages
1332 * because the ECC controller waits for
1333 * NAND_CMD_RNDOUTSTART after the
1335 * anyway, for small pages, the eccpos[0] == 0
1337 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1338 mtd->writesize + eccpos[0], -1);
1341 /* the ECC controller needs to read the ECC just after the data */
1342 ecc_pos = oob + eccpos[0];
1343 chip->read_buf(mtd, ecc_pos, eccbytes);
1345 /* check if there's an error */
1346 stat = chip->ecc.correct(mtd, p, oob, NULL);
1349 mtd->ecc_stats.failed++;
1351 mtd->ecc_stats.corrected += stat;
1352 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1355 /* get back to oob start (end of page) */
1356 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1359 chip->read_buf(mtd, oob, mtd->oobsize);
1361 return max_bitflips;
1367 * function called after a read
1369 * mtd: MTD block structure
1370 * dat: raw data read from the chip
1371 * read_ecc: ECC from the chip (unused)
1374 * Detect and correct a 1 bit error for a page
1376 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1377 u_char *read_ecc, u_char *isnull)
1379 struct nand_chip *nand_chip = mtd->priv;
1380 struct atmel_nand_host *host = nand_chip->priv;
1381 unsigned int ecc_status;
1382 unsigned int ecc_word, ecc_bit;
1384 /* get the status from the Status Register */
1385 ecc_status = ecc_readl(host->ecc, SR);
1387 /* if there's no error */
1388 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1391 /* get error bit offset (4 bits) */
1392 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1393 /* get word address (12 bits) */
1394 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1397 /* if there are multiple errors */
1398 if (ecc_status & ATMEL_ECC_MULERR) {
1399 /* check if it is a freshly erased block
1400 * (filled with 0xff) */
1401 if ((ecc_bit == ATMEL_ECC_BITADDR)
1402 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1403 /* the block has just been erased, return OK */
1406 /* it doesn't seems to be a freshly
1408 * We can't correct so many errors */
1409 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1410 " Unable to correct.\n");
1414 /* if there's a single bit error : we can correct it */
1415 if (ecc_status & ATMEL_ECC_ECCERR) {
1416 /* there's nothing much to do here.
1417 * the bit error is on the ECC itself.
1419 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1420 " Nothing to correct\n");
1424 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1425 " (word offset in the page :"
1426 " 0x%x bit offset : 0x%x)\n",
1428 /* correct the error */
1429 if (nand_chip->options & NAND_BUSWIDTH_16) {
1431 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1434 dat[ecc_word] ^= (1 << ecc_bit);
1436 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1441 * Enable HW ECC : unused on most chips
1443 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1445 struct nand_chip *nand_chip = mtd->priv;
1446 struct atmel_nand_host *host = nand_chip->priv;
1448 if (host->board.need_reset_workaround)
1449 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1452 #if defined(CONFIG_OF)
1453 static int atmel_of_init_port(struct atmel_nand_host *host,
1454 struct device_node *np)
1459 struct atmel_nand_data *board = &host->board;
1460 enum of_gpio_flags flags;
1462 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1464 dev_err(host->dev, "invalid addr-offset %u\n", val);
1470 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1472 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1478 ecc_mode = of_get_nand_ecc_mode(np);
1480 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1482 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1484 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1486 if (of_get_nand_bus_width(np) == 16)
1487 board->bus_width_16 = 1;
1489 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1490 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1492 board->enable_pin = of_get_gpio(np, 1);
1493 board->det_pin = of_get_gpio(np, 2);
1495 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1497 /* load the nfc driver if there is */
1498 of_platform_populate(np, NULL, NULL, host->dev);
1500 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1501 return 0; /* Not using PMECC */
1503 /* use PMECC, get correction capability, sector size and lookup
1505 * If correction bits and sector size are not specified, then find
1506 * them from NAND ONFI parameters.
1508 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1509 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1512 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1516 host->pmecc_corr_cap = (u8)val;
1519 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1520 if ((val != 512) && (val != 1024)) {
1522 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1526 host->pmecc_sector_size = (u16)val;
1529 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1531 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1534 if (!offset[0] && !offset[1]) {
1535 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1538 host->pmecc_lookup_table_offset_512 = offset[0];
1539 host->pmecc_lookup_table_offset_1024 = offset[1];
1544 static int atmel_of_init_port(struct atmel_nand_host *host,
1545 struct device_node *np)
1551 static int __init atmel_hw_nand_init_params(struct platform_device *pdev,
1552 struct atmel_nand_host *host)
1554 struct mtd_info *mtd = &host->mtd;
1555 struct nand_chip *nand_chip = &host->nand_chip;
1556 struct resource *regs;
1558 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1561 "Can't get I/O resource regs, use software ECC\n");
1562 nand_chip->ecc.mode = NAND_ECC_SOFT;
1566 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1567 if (IS_ERR(host->ecc)) {
1568 dev_err(host->dev, "ioremap failed\n");
1569 return PTR_ERR(host->ecc);
1572 /* ECC is calculated for the whole page (1 step) */
1573 nand_chip->ecc.size = mtd->writesize;
1575 /* set ECC page size and oob layout */
1576 switch (mtd->writesize) {
1578 nand_chip->ecc.layout = &atmel_oobinfo_small;
1579 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1582 nand_chip->ecc.layout = &atmel_oobinfo_large;
1583 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1586 nand_chip->ecc.layout = &atmel_oobinfo_large;
1587 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1590 nand_chip->ecc.layout = &atmel_oobinfo_large;
1591 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1594 /* page size not handled by HW ECC */
1595 /* switching back to soft ECC */
1596 nand_chip->ecc.mode = NAND_ECC_SOFT;
1600 /* set up for HW ECC */
1601 nand_chip->ecc.calculate = atmel_nand_calculate;
1602 nand_chip->ecc.correct = atmel_nand_correct;
1603 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1604 nand_chip->ecc.read_page = atmel_nand_read_page;
1605 nand_chip->ecc.bytes = 4;
1606 nand_chip->ecc.strength = 1;
1611 /* SMC interrupt service routine */
1612 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1614 struct atmel_nand_host *host = dev_id;
1615 u32 status, mask, pending;
1616 irqreturn_t ret = IRQ_HANDLED;
1618 status = nfc_readl(host->nfc->hsmc_regs, SR);
1619 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1620 pending = status & mask;
1622 if (pending & NFC_SR_XFR_DONE) {
1623 complete(&host->nfc->comp_nfc);
1624 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1625 } else if (pending & NFC_SR_RB_EDGE) {
1626 complete(&host->nfc->comp_nfc);
1627 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1628 } else if (pending & NFC_SR_CMD_DONE) {
1629 complete(&host->nfc->comp_nfc);
1630 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1638 /* NFC(Nand Flash Controller) related functions */
1639 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1641 unsigned long timeout;
1642 init_completion(&host->nfc->comp_nfc);
1644 /* Enable interrupt that need to wait for */
1645 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1647 timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1648 msecs_to_jiffies(NFC_TIME_OUT_MS));
1652 /* Time out to wait for the interrupt */
1653 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1657 static int nfc_send_command(struct atmel_nand_host *host,
1658 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1660 unsigned long timeout;
1662 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1665 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1666 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1667 & NFCADDR_CMD_NFCBUSY) {
1668 if (time_after(jiffies, timeout)) {
1670 "Time out to wait CMD_NFCBUSY ready!\n");
1674 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1675 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1676 return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1679 static int nfc_device_ready(struct mtd_info *mtd)
1681 struct nand_chip *nand_chip = mtd->priv;
1682 struct atmel_nand_host *host = nand_chip->priv;
1683 if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1688 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1690 struct nand_chip *nand_chip = mtd->priv;
1691 struct atmel_nand_host *host = nand_chip->priv;
1694 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1696 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1699 static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
1700 unsigned int *addr1234, unsigned int *cycle0)
1702 struct nand_chip *chip = mtd->priv;
1705 unsigned char addr_bytes[8];
1706 int index = 0, bit_shift;
1708 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1714 if (chip->options & NAND_BUSWIDTH_16)
1716 addr_bytes[acycle++] = column & 0xff;
1717 if (mtd->writesize > 512)
1718 addr_bytes[acycle++] = (column >> 8) & 0xff;
1721 if (page_addr != -1) {
1722 addr_bytes[acycle++] = page_addr & 0xff;
1723 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1724 if (chip->chipsize > (128 << 20))
1725 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1729 *cycle0 = addr_bytes[index++];
1731 for (bit_shift = 0; index < acycle; bit_shift += 8)
1732 *addr1234 += addr_bytes[index++] << bit_shift;
1734 /* return acycle in cmd register */
1735 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1738 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1739 int column, int page_addr)
1741 struct nand_chip *chip = mtd->priv;
1742 struct atmel_nand_host *host = chip->priv;
1743 unsigned long timeout;
1744 unsigned int nfc_addr_cmd = 0;
1746 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1748 /* Set default settings: no cmd2, no addr cycle. read from nand */
1749 unsigned int cmd2 = 0;
1750 unsigned int vcmd2 = 0;
1751 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1752 int csid = NFCADDR_CMD_CSID_3;
1753 int dataen = NFCADDR_CMD_DATADIS;
1754 int nfcwr = NFCADDR_CMD_NFCRD;
1755 unsigned int addr1234 = 0;
1756 unsigned int cycle0 = 0;
1757 bool do_addr = true;
1758 host->nfc->data_in_sram = NULL;
1760 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1761 __func__, command, column, page_addr);
1764 case NAND_CMD_RESET:
1765 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1766 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1767 udelay(chip->chip_delay);
1769 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1770 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1771 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1772 if (time_after(jiffies, timeout)) {
1774 "Time out to wait status ready!\n");
1779 case NAND_CMD_STATUS:
1782 case NAND_CMD_PARAM:
1783 case NAND_CMD_READID:
1785 acycle = NFCADDR_CMD_ACYCLE_1;
1789 case NAND_CMD_RNDOUT:
1790 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1791 vcmd2 = NFCADDR_CMD_VCMD2;
1793 case NAND_CMD_READ0:
1794 case NAND_CMD_READOOB:
1795 if (command == NAND_CMD_READOOB) {
1796 column += mtd->writesize;
1797 command = NAND_CMD_READ0; /* only READ0 is valid */
1798 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1800 if (host->nfc->use_nfc_sram) {
1801 /* Enable Data transfer to sram */
1802 dataen = NFCADDR_CMD_DATAEN;
1804 /* Need enable PMECC now, since NFC will transfer
1805 * data in bus after sending nfc read command.
1807 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1808 pmecc_enable(host, NAND_ECC_READ);
1811 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1812 vcmd2 = NFCADDR_CMD_VCMD2;
1814 /* For prgramming command, the cmd need set to write enable */
1815 case NAND_CMD_PAGEPROG:
1816 case NAND_CMD_SEQIN:
1817 case NAND_CMD_RNDIN:
1818 nfcwr = NFCADDR_CMD_NFCWR;
1819 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1820 dataen = NFCADDR_CMD_DATAEN;
1827 acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
1830 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1831 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1833 if (dataen == NFCADDR_CMD_DATAEN)
1834 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1835 dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1838 * Program and erase have their own busy handlers status, sequential
1839 * in, and deplete1 need no delay.
1842 case NAND_CMD_CACHEDPROG:
1843 case NAND_CMD_PAGEPROG:
1844 case NAND_CMD_ERASE1:
1845 case NAND_CMD_ERASE2:
1846 case NAND_CMD_RNDIN:
1847 case NAND_CMD_STATUS:
1848 case NAND_CMD_RNDOUT:
1849 case NAND_CMD_SEQIN:
1850 case NAND_CMD_READID:
1853 case NAND_CMD_READ0:
1854 if (dataen == NFCADDR_CMD_DATAEN) {
1855 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1856 nfc_get_sram_off(host);
1861 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1865 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1866 uint32_t offset, int data_len, const uint8_t *buf,
1867 int oob_required, int page, int cached, int raw)
1871 struct atmel_nand_host *host = chip->priv;
1872 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1874 /* Subpage write is not supported */
1875 if (offset || (data_len < mtd->writesize))
1878 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1879 len = mtd->writesize;
1881 if (unlikely(raw)) {
1882 len += mtd->oobsize;
1883 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1885 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1887 /* Copy page data to sram that will write to nand via NFC */
1889 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1890 /* Fall back to use cpu copy */
1891 memcpy32_toio(sram, buf, len);
1893 memcpy32_toio(sram, buf, len);
1896 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1898 * When use NFC sram, need set up PMECC before send
1899 * NAND_CMD_SEQIN command. Since when the nand command
1900 * is sent, nfc will do transfer from sram and nand.
1902 pmecc_enable(host, NAND_ECC_WRITE);
1904 host->nfc->will_write_sram = true;
1905 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1906 host->nfc->will_write_sram = false;
1909 /* Need to write ecc into oob */
1910 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1915 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1916 status = chip->waitfunc(mtd, chip);
1918 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1919 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1921 if (status & NAND_STATUS_FAIL)
1927 static int nfc_sram_init(struct mtd_info *mtd)
1929 struct nand_chip *chip = mtd->priv;
1930 struct atmel_nand_host *host = chip->priv;
1933 /* Initialize the NFC CFG register */
1934 unsigned int cfg_nfc = 0;
1936 /* set page size and oob layout */
1937 switch (mtd->writesize) {
1939 cfg_nfc = NFC_CFG_PAGESIZE_512;
1942 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1945 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1948 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1951 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1954 dev_err(host->dev, "Unsupported page size for NFC.\n");
1959 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1960 * Max support spare size is 512 bytes. */
1961 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1962 & NFC_CFG_NFC_SPARESIZE);
1963 /* default set a max timeout */
1964 cfg_nfc |= NFC_CFG_RSPARE |
1965 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1967 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1969 host->nfc->will_write_sram = false;
1970 nfc_set_sram_bank(host, 0);
1972 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1973 if (host->nfc->write_by_sram) {
1974 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1975 chip->ecc.mode == NAND_ECC_NONE)
1976 chip->write_page = nfc_sram_write_page;
1978 host->nfc->write_by_sram = false;
1981 dev_info(host->dev, "Using NFC Sram read %s\n",
1982 host->nfc->write_by_sram ? "and write" : "");
1986 static struct platform_driver atmel_nand_nfc_driver;
1988 * Probe for the NAND device.
1990 static int __init atmel_nand_probe(struct platform_device *pdev)
1992 struct atmel_nand_host *host;
1993 struct mtd_info *mtd;
1994 struct nand_chip *nand_chip;
1995 struct resource *mem;
1996 struct mtd_part_parser_data ppdata = {};
1999 /* Allocate memory for the device structure (and zero it) */
2000 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2002 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
2006 res = platform_driver_register(&atmel_nand_nfc_driver);
2008 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2010 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2011 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2012 if (IS_ERR(host->io_base)) {
2013 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
2014 res = PTR_ERR(host->io_base);
2015 goto err_nand_ioremap;
2017 host->io_phys = (dma_addr_t)mem->start;
2020 nand_chip = &host->nand_chip;
2021 host->dev = &pdev->dev;
2022 if (pdev->dev.of_node) {
2023 res = atmel_of_init_port(host, pdev->dev.of_node);
2025 goto err_nand_ioremap;
2027 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2028 sizeof(struct atmel_nand_data));
2031 nand_chip->priv = host; /* link the private data structures */
2032 mtd->priv = nand_chip;
2033 mtd->owner = THIS_MODULE;
2035 /* Set address of NAND IO lines */
2036 nand_chip->IO_ADDR_R = host->io_base;
2037 nand_chip->IO_ADDR_W = host->io_base;
2039 if (nand_nfc.is_initialized) {
2040 /* NFC driver is probed and initialized */
2041 host->nfc = &nand_nfc;
2043 nand_chip->select_chip = nfc_select_chip;
2044 nand_chip->dev_ready = nfc_device_ready;
2045 nand_chip->cmdfunc = nfc_nand_command;
2047 /* Initialize the interrupt for NFC */
2048 irq = platform_get_irq(pdev, 0);
2050 dev_err(host->dev, "Cannot get HSMC irq!\n");
2051 goto err_nand_ioremap;
2054 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2057 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2059 goto err_nand_ioremap;
2062 res = atmel_nand_set_enable_ready_pins(mtd);
2064 goto err_nand_ioremap;
2066 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2069 nand_chip->ecc.mode = host->board.ecc_mode;
2070 nand_chip->chip_delay = 20; /* 20us command delay time */
2072 if (host->board.bus_width_16) /* 16-bit bus width */
2073 nand_chip->options |= NAND_BUSWIDTH_16;
2075 nand_chip->read_buf = atmel_read_buf;
2076 nand_chip->write_buf = atmel_write_buf;
2078 platform_set_drvdata(pdev, host);
2079 atmel_nand_enable(host);
2081 if (gpio_is_valid(host->board.det_pin)) {
2082 res = devm_gpio_request(&pdev->dev,
2083 host->board.det_pin, "nand_det");
2086 "can't request det gpio %d\n",
2087 host->board.det_pin);
2091 res = gpio_direction_input(host->board.det_pin);
2094 "can't request input direction det gpio %d\n",
2095 host->board.det_pin);
2099 if (gpio_get_value(host->board.det_pin)) {
2100 printk(KERN_INFO "No SmartMedia card inserted.\n");
2106 if (host->board.on_flash_bbt || on_flash_bbt) {
2107 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
2108 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2111 if (!host->board.has_dma)
2115 dma_cap_mask_t mask;
2118 dma_cap_set(DMA_MEMCPY, mask);
2119 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2120 if (!host->dma_chan) {
2121 dev_err(host->dev, "Failed to request DMA channel\n");
2126 dev_info(host->dev, "Using %s for DMA transfers.\n",
2127 dma_chan_name(host->dma_chan));
2129 dev_info(host->dev, "No DMA support for NAND access.\n");
2131 /* first scan to find the device and get the page size */
2132 if (nand_scan_ident(mtd, 1, NULL)) {
2134 goto err_scan_ident;
2137 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2138 if (host->has_pmecc)
2139 res = atmel_pmecc_nand_init_params(pdev, host);
2141 res = atmel_hw_nand_init_params(pdev, host);
2147 /* initialize the nfc configuration register */
2148 if (host->nfc && host->nfc->use_nfc_sram) {
2149 res = nfc_sram_init(mtd);
2151 host->nfc->use_nfc_sram = false;
2152 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2156 /* second phase scan */
2157 if (nand_scan_tail(mtd)) {
2162 mtd->name = "atmel_nand";
2163 ppdata.of_node = pdev->dev.of_node;
2164 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2165 host->board.parts, host->board.num_parts);
2170 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2171 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2175 atmel_nand_disable(host);
2177 dma_release_channel(host->dma_chan);
2179 platform_driver_unregister(&atmel_nand_nfc_driver);
2184 * Remove a NAND device.
2186 static int __exit atmel_nand_remove(struct platform_device *pdev)
2188 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2189 struct mtd_info *mtd = &host->mtd;
2193 atmel_nand_disable(host);
2195 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2196 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2197 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2202 dma_release_channel(host->dma_chan);
2204 platform_driver_unregister(&atmel_nand_nfc_driver);
2209 #if defined(CONFIG_OF)
2210 static const struct of_device_id atmel_nand_dt_ids[] = {
2211 { .compatible = "atmel,at91rm9200-nand" },
2215 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2218 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2220 struct atmel_nfc *nfc = &nand_nfc;
2221 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2223 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2224 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2225 if (IS_ERR(nfc->base_cmd_regs))
2226 return PTR_ERR(nfc->base_cmd_regs);
2228 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2229 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2230 if (IS_ERR(nfc->hsmc_regs))
2231 return PTR_ERR(nfc->hsmc_regs);
2233 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2235 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2236 if (IS_ERR(nfc->sram_bank0)) {
2237 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2238 PTR_ERR(nfc->sram_bank0));
2240 nfc->use_nfc_sram = true;
2241 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2243 if (pdev->dev.of_node)
2244 nfc->write_by_sram = of_property_read_bool(
2246 "atmel,write-by-sram");
2250 nfc->is_initialized = true;
2251 dev_info(&pdev->dev, "NFC is probed.\n");
2255 #if defined(CONFIG_OF)
2256 static struct of_device_id atmel_nand_nfc_match[] = {
2257 { .compatible = "atmel,sama5d3-nfc" },
2262 static struct platform_driver atmel_nand_nfc_driver = {
2264 .name = "atmel_nand_nfc",
2265 .owner = THIS_MODULE,
2266 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2268 .probe = atmel_nand_nfc_probe,
2271 static struct platform_driver atmel_nand_driver = {
2272 .remove = __exit_p(atmel_nand_remove),
2274 .name = "atmel_nand",
2275 .owner = THIS_MODULE,
2276 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2280 module_platform_driver_probe(atmel_nand_driver, atmel_nand_probe);
2282 MODULE_LICENSE("GPL");
2283 MODULE_AUTHOR("Rick Bronson");
2284 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2285 MODULE_ALIAS("platform:atmel_nand");