drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

   1 /*
   2  * BCM47XX NAND flash driver
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/bcma/bcma.h>
  16
  17 #include "bcm47xxnflash.h"
  18
  19 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
  20  * shown 164 retries as maxiumum. */
  21 #define NFLASH_READY_RETRIES            1000
  22
  23 #define NFLASH_SECTOR_SIZE              512
  24
  25 #define NCTL_CMD0                       0x00010000
  26 #define NCTL_CMD1W                      0x00080000
  27 #define NCTL_READ                       0x00100000
  28 #define NCTL_SPECADDR                   0x01000000
  29 #define NCTL_READY                      0x04000000
  30 #define NCTL_ERR                        0x08000000
  31 #define NCTL_CSA                        0x40000000
  32 #define NCTL_START                      0x80000000
  33
  34 /**************************************************
  35  * Various helpers
  36  **************************************************/
  37
  38 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
  39 {
  40         return ((ns * 1000 * clock) / 1000000) + 1;
  41 }
  42
  43 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
  44 {
  45         int i = 0;
  46
  47         bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
  48         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  49                 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
  50                         i = 0;
  51                         break;
  52                 }
  53         }
  54         if (i) {
  55                 pr_err("NFLASH control command not ready!\n");
  56                 return -EBUSY;
  57         }
  58         return 0;
  59 }
  60
  61 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
  62 {
  63         int i;
  64
  65         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  66                 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
  67                         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
  68                             BCMA_CC_NFLASH_CTL_ERR) {
  69                                 pr_err("Error on polling\n");
  70                                 return -EBUSY;
  71                         } else {
  72                                 return 0;
  73                         }
  74                 }
  75         }
  76
  77         pr_err("Polling timeout!\n");
  78         return -EBUSY;
  79 }
  80
  81 /**************************************************
  82  * R/W
  83  **************************************************/
  84
  85 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
  86                                            int len)
  87 {
  88         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
  89         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
  90
  91         u32 ctlcode;
  92         u32 *dest = (u32 *)buf;
  93         int i;
  94         int toread;
  95
  96         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
  97         /* Don't validate column using nand_chip->page_shift, it may be bigger
  98          * when accessing OOB */
  99
 100         while (len) {
 101                 /* We can read maximum of 0x200 bytes at once */
 102                 toread = min(len, 0x200);
 103
 104                 /* Set page and column */
 105                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
 106                                 b47n->curr_column);
 107                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
 108                                 b47n->curr_page_addr);
 109
 110                 /* Prepare to read */
 111                 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 |
 112                           NCTL_CMD0;
 113                 ctlcode |= NAND_CMD_READSTART << 8;
 114                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
 115                         return;
 116                 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
 117                         return;
 118
 119                 /* Eventually read some data :) */
 120                 for (i = 0; i < toread; i += 4, dest++) {
 121                         ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
 122                         if (i == toread - 4) /* Last read goes without that */
 123                                 ctlcode &= ~NCTL_CSA;
 124                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 125                                                               ctlcode))
 126                                 return;
 127                         *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
 128                 }
 129
 130                 b47n->curr_column += toread;
 131                 len -= toread;
 132         }
 133 }
 134
 135 /**************************************************
 136  * NAND chip ops
 137  **************************************************/
 138
 139 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
 140 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 141                                                   int chip)
 142 {
 143         return;
 144 }
 145
 146 /*
 147  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
 148  * For example, reading chip id is performed in a non-standard way.
 149  * Setting column and page is also handled differently, we use a special
 150  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
 151  * standard commands would be much more complicated.
 152  */
 153 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 154                                               unsigned command, int column,
 155                                               int page_addr)
 156 {
 157         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 158         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 159         u32 ctlcode;
 160         int i;
 161
 162         if (column != -1)
 163                 b47n->curr_column = column;
 164         if (page_addr != -1)
 165                 b47n->curr_page_addr = page_addr;
 166
 167         switch (command) {
 168         case NAND_CMD_RESET:
 169                 pr_warn("Chip reset not implemented yet\n");
 170                 break;
 171         case NAND_CMD_READID:
 172                 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
 173                 ctlcode |= NAND_CMD_READID;
 174                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
 175                         pr_err("READID error\n");
 176                         break;
 177                 }
 178
 179                 /*
 180                  * Reading is specific, last one has to go without NCTL_CSA
 181                  * bit. We don't know how many reads NAND subsystem is going
 182                  * to perform, so cache everything.
 183                  */
 184                 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
 185                         ctlcode = NCTL_CSA | NCTL_READ;
 186                         if (i == ARRAY_SIZE(b47n->id_data) - 1)
 187                                 ctlcode &= ~NCTL_CSA;
 188                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 189                                                               ctlcode)) {
 190                                 pr_err("READID error\n");
 191                                 break;
 192                         }
 193                         b47n->id_data[i] =
 194                                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
 195                                 & 0xFF;
 196                 }
 197
 198                 break;
 199         case NAND_CMD_READ0:
 200                 break;
 201         case NAND_CMD_READOOB:
 202                 if (page_addr != -1)
 203                         b47n->curr_column += mtd->writesize;
 204                 break;
 205         default:
 206                 pr_err("Command 0x%X unsupported\n", command);
 207                 break;
 208         }
 209         b47n->curr_command = command;
 210 }
 211
 212 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 213 {
 214         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 215         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 216         u32 tmp = 0;
 217
 218         switch (b47n->curr_command) {
 219         case NAND_CMD_READID:
 220                 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
 221                         pr_err("Requested invalid id_data: %d\n",
 222                                b47n->curr_column);
 223                         return 0;
 224                 }
 225                 return b47n->id_data[b47n->curr_column++];
 226         case NAND_CMD_READOOB:
 227                 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
 228                 return tmp & 0xFF;
 229         }
 230
 231         pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 232         return 0;
 233 }
 234
 235 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
 236                                                uint8_t *buf, int len)
 237 {
 238         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 239         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 240
 241         switch (b47n->curr_command) {
 242         case NAND_CMD_READ0:
 243         case NAND_CMD_READOOB:
 244                 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
 245                 return;
 246         }
 247
 248         pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 249 }
 250
 251 /**************************************************
 252  * Init
 253  **************************************************/
 254
 255 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 256 {
 257         int err;
 258         u32 freq;
 259         u16 clock;
 260         u8 w0, w1, w2, w3, w4;
 261
 262         unsigned long chipsize; /* MiB */
 263         u8 tbits, col_bits, col_size, row_bits, row_bsize;
 264         u32 val;
 265
 266         b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 267         b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 268         b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 269         b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
 270         b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 271         b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 272
 273         /* Enable NAND flash access */
 274         bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 275                       BCMA_CC_4706_FLASHSCFG_NF1);
 276
 277         /* Configure wait counters */
 278         if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
 279                 freq = 100000000;
 280         } else {
 281                 freq = bcma_chipco_pll_read(b47n->cc, 4);
 282                 freq = (freq * 0xFFF) >> 3;
 283                 freq = (freq * 25000000) >> 3;
 284         }
 285         clock = freq / 1000000;
 286         w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
 287         w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
 288         w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 289         w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 290         w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
 291         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
 292                         (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 293
 294         /* Scan NAND */
 295         err = nand_scan(&b47n->mtd, 1);
 296         if (err) {
 297                 pr_err("Could not scan NAND flash: %d\n", err);
 298                 goto exit;
 299         }
 300
 301         /* Configure FLASH */
 302         chipsize = b47n->nand_chip.chipsize >> 20;
 303         tbits = ffs(chipsize); /* find first bit set */
 304         if (!tbits || tbits != fls(chipsize)) {
 305                 pr_err("Invalid flash size: 0x%lX\n", chipsize);
 306                 err = -ENOTSUPP;
 307                 goto exit;
 308         }
 309         tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
 310
 311         col_bits = b47n->nand_chip.page_shift + 1;
 312         col_size = (col_bits + 7) / 8;
 313
 314         row_bits = tbits - col_bits + 1;
 315         row_bsize = (row_bits + 7) / 8;
 316
 317         val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
 318         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 319
 320 exit:
 321         if (err)
 322                 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 323                                ~BCMA_CC_4706_FLASHSCFG_NF1);
 324         return err;
 325 }