drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

   1 /*
   2  * BCM47XX NAND flash driver
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/bcma/bcma.h>
  16
  17 #include "bcm47xxnflash.h"
  18
  19 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
  20  * shown 164 retries as maxiumum. */
  21 #define NFLASH_READY_RETRIES            1000
  22
  23 #define NFLASH_SECTOR_SIZE              512
  24
  25 /**************************************************
  26  * Various helpers
  27  **************************************************/
  28
  29 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
  30 {
  31         return ((ns * 1000 * clock) / 1000000) + 1;
  32 }
  33
  34 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
  35 {
  36         int i = 0;
  37
  38         bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, 0x80000000 | code);
  39         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  40                 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x80000000)) {
  41                         i = 0;
  42                         break;
  43                 }
  44         }
  45         if (i) {
  46                 pr_err("NFLASH control command not ready!\n");
  47                 return -EBUSY;
  48         }
  49         return 0;
  50 }
  51
  52 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
  53 {
  54         int i;
  55
  56         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  57                 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x04000000) {
  58                         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
  59                             BCMA_CC_NFLASH_CTL_ERR) {
  60                                 pr_err("Error on polling\n");
  61                                 return -EBUSY;
  62                         } else {
  63                                 return 0;
  64                         }
  65                 }
  66         }
  67
  68         pr_err("Polling timeout!\n");
  69         return -EBUSY;
  70 }
  71
  72 /**************************************************
  73  * R/W
  74  **************************************************/
  75
  76 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
  77                                            int len)
  78 {
  79         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
  80         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
  81
  82         u32 ctlcode;
  83         u32 *dest = (u32 *)buf;
  84         int i;
  85         int toread;
  86
  87         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
  88         /* Don't validate column using nand_chip->page_shift, it may be bigger
  89          * when accessing OOB */
  90
  91         while (len) {
  92                 /* We can read maximum of 0x200 bytes at once */
  93                 toread = min(len, 0x200);
  94
  95                 /* Set page and column */
  96                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
  97                                 b47n->curr_column);
  98                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
  99                                 b47n->curr_page_addr);
 100
 101                 /* Prepare to read */
 102                 ctlcode = 0x40000000 | 0x00080000 | 0x00040000 | 0x00020000 |
 103                           0x00010000;
 104                 ctlcode |= NAND_CMD_READSTART << 8;
 105                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
 106                         return;
 107                 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
 108                         return;
 109
 110                 /* Eventually read some data :) */
 111                 for (i = 0; i < toread; i += 4, dest++) {
 112                         ctlcode = 0x40000000 | 0x30000000 | 0x00100000;
 113                         if (i == toread - 4) /* Last read goes without that */
 114                                 ctlcode &= ~0x40000000;
 115                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 116                                                               ctlcode))
 117                                 return;
 118                         *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
 119                 }
 120
 121                 b47n->curr_column += toread;
 122                 len -= toread;
 123         }
 124 }
 125
 126 /**************************************************
 127  * NAND chip ops
 128  **************************************************/
 129
 130 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
 131 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 132                                                   int chip)
 133 {
 134         return;
 135 }
 136
 137 /*
 138  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
 139  * For example, reading chip id is performed in a non-standard way.
 140  * Setting column and page is also handled differently, we use a special
 141  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
 142  * standard commands would be much more complicated.
 143  */
 144 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 145                                               unsigned command, int column,
 146                                               int page_addr)
 147 {
 148         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 149         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 150         u32 ctlcode;
 151         int i;
 152
 153         if (column != -1)
 154                 b47n->curr_column = column;
 155         if (page_addr != -1)
 156                 b47n->curr_page_addr = page_addr;
 157
 158         switch (command) {
 159         case NAND_CMD_RESET:
 160                 pr_warn("Chip reset not implemented yet\n");
 161                 break;
 162         case NAND_CMD_READID:
 163                 ctlcode = 0x40000000 | 0x01000000 | 0x00080000 | 0x00010000;
 164                 ctlcode |= NAND_CMD_READID;
 165                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
 166                         pr_err("READID error\n");
 167                         break;
 168                 }
 169
 170                 /*
 171                  * Reading is specific, last one has to go without 0x40000000
 172                  * bit. We don't know how many reads NAND subsystem is going
 173                  * to perform, so cache everything.
 174                  */
 175                 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
 176                         ctlcode = 0x40000000 | 0x00100000;
 177                         if (i == ARRAY_SIZE(b47n->id_data) - 1)
 178                                 ctlcode &= ~0x40000000;
 179                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 180                                                               ctlcode)) {
 181                                 pr_err("READID error\n");
 182                                 break;
 183                         }
 184                         b47n->id_data[i] =
 185                                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
 186                                 & 0xFF;
 187                 }
 188
 189                 break;
 190         case NAND_CMD_READ0:
 191                 break;
 192         case NAND_CMD_READOOB:
 193                 if (page_addr != -1)
 194                         b47n->curr_column += mtd->writesize;
 195                 break;
 196         default:
 197                 pr_err("Command 0x%X unsupported\n", command);
 198                 break;
 199         }
 200         b47n->curr_command = command;
 201 }
 202
 203 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 204 {
 205         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 206         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 207         u32 tmp = 0;
 208
 209         switch (b47n->curr_command) {
 210         case NAND_CMD_READID:
 211                 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
 212                         pr_err("Requested invalid id_data: %d\n",
 213                                b47n->curr_column);
 214                         return 0;
 215                 }
 216                 return b47n->id_data[b47n->curr_column++];
 217         case NAND_CMD_READOOB:
 218                 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
 219                 return tmp & 0xFF;
 220         }
 221
 222         pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 223         return 0;
 224 }
 225
 226 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
 227                                                uint8_t *buf, int len)
 228 {
 229         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 230         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 231
 232         switch (b47n->curr_command) {
 233         case NAND_CMD_READ0:
 234         case NAND_CMD_READOOB:
 235                 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
 236                 return;
 237         }
 238
 239         pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 240 }
 241
 242 /**************************************************
 243  * Init
 244  **************************************************/
 245
 246 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 247 {
 248         int err;
 249         u32 freq;
 250         u16 clock;
 251         u8 w0, w1, w2, w3, w4;
 252
 253         unsigned long chipsize; /* MiB */
 254         u8 tbits, col_bits, col_size, row_bits, row_bsize;
 255         u32 val;
 256
 257         b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 258         b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 259         b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 260         b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
 261         b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 262         b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 263
 264         /* Enable NAND flash access */
 265         bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 266                       BCMA_CC_4706_FLASHSCFG_NF1);
 267
 268         /* Configure wait counters */
 269         if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
 270                 freq = 100000000;
 271         } else {
 272                 freq = bcma_chipco_pll_read(b47n->cc, 4);
 273                 freq = (freq * 0xFFF) >> 3;
 274                 freq = (freq * 25000000) >> 3;
 275         }
 276         clock = freq / 1000000;
 277         w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
 278         w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
 279         w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 280         w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 281         w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
 282         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
 283                         (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 284
 285         /* Scan NAND */
 286         err = nand_scan(&b47n->mtd, 1);
 287         if (err) {
 288                 pr_err("Could not scan NAND flash: %d\n", err);
 289                 goto exit;
 290         }
 291
 292         /* Configure FLASH */
 293         chipsize = b47n->nand_chip.chipsize >> 20;
 294         tbits = ffs(chipsize); /* find first bit set */
 295         if (!tbits || tbits != fls(chipsize)) {
 296                 pr_err("Invalid flash size: 0x%lX\n", chipsize);
 297                 err = -ENOTSUPP;
 298                 goto exit;
 299         }
 300         tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
 301
 302         col_bits = b47n->nand_chip.page_shift + 1;
 303         col_size = (col_bits + 7) / 8;
 304
 305         row_bits = tbits - col_bits + 1;
 306         row_bsize = (row_bits + 7) / 8;
 307
 308         val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
 309         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 310
 311 exit:
 312         if (err)
 313                 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 314                                ~BCMA_CC_4706_FLASHSCFG_NF1);
 315         return err;
 316 }