drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

   1 /*
   2  * BCM47XX NAND flash driver
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include "bcm47xxnflash.h"
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/bcma/bcma.h>
  18
  19 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
  20  * shown ~1000 retries as maxiumum. */
  21 #define NFLASH_READY_RETRIES            10000
  22
  23 #define NFLASH_SECTOR_SIZE              512
  24
  25 #define NCTL_CMD0                       0x00010000
  26 #define NCTL_CMD1W                      0x00080000
  27 #define NCTL_READ                       0x00100000
  28 #define NCTL_WRITE                      0x00200000
  29 #define NCTL_SPECADDR                   0x01000000
  30 #define NCTL_READY                      0x04000000
  31 #define NCTL_ERR                        0x08000000
  32 #define NCTL_CSA                        0x40000000
  33 #define NCTL_START                      0x80000000
  34
  35 /**************************************************
  36  * Various helpers
  37  **************************************************/
  38
  39 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
  40 {
  41         return ((ns * 1000 * clock) / 1000000) + 1;
  42 }
  43
  44 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
  45 {
  46         int i = 0;
  47
  48         bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
  49         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  50                 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
  51                         i = 0;
  52                         break;
  53                 }
  54         }
  55         if (i) {
  56                 pr_err("NFLASH control command not ready!\n");
  57                 return -EBUSY;
  58         }
  59         return 0;
  60 }
  61
  62 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
  63 {
  64         int i;
  65
  66         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  67                 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
  68                         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
  69                             BCMA_CC_NFLASH_CTL_ERR) {
  70                                 pr_err("Error on polling\n");
  71                                 return -EBUSY;
  72                         } else {
  73                                 return 0;
  74                         }
  75                 }
  76         }
  77
  78         pr_err("Polling timeout!\n");
  79         return -EBUSY;
  80 }
  81
  82 /**************************************************
  83  * R/W
  84  **************************************************/
  85
  86 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
  87                                            int len)
  88 {
  89         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
  90         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
  91
  92         u32 ctlcode;
  93         u32 *dest = (u32 *)buf;
  94         int i;
  95         int toread;
  96
  97         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
  98         /* Don't validate column using nand_chip->page_shift, it may be bigger
  99          * when accessing OOB */
 100
 101         while (len) {
 102                 /* We can read maximum of 0x200 bytes at once */
 103                 toread = min(len, 0x200);
 104
 105                 /* Set page and column */
 106                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
 107                                 b47n->curr_column);
 108                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
 109                                 b47n->curr_page_addr);
 110
 111                 /* Prepare to read */
 112                 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 |
 113                           NCTL_CMD0;
 114                 ctlcode |= NAND_CMD_READSTART << 8;
 115                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
 116                         return;
 117                 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
 118                         return;
 119
 120                 /* Eventually read some data :) */
 121                 for (i = 0; i < toread; i += 4, dest++) {
 122                         ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
 123                         if (i == toread - 4) /* Last read goes without that */
 124                                 ctlcode &= ~NCTL_CSA;
 125                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 126                                                               ctlcode))
 127                                 return;
 128                         *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
 129                 }
 130
 131                 b47n->curr_column += toread;
 132                 len -= toread;
 133         }
 134 }
 135
 136 static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
 137                                             const uint8_t *buf, int len)
 138 {
 139         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 140         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 141         struct bcma_drv_cc *cc = b47n->cc;
 142
 143         u32 ctlcode;
 144         const u32 *data = (u32 *)buf;
 145         int i;
 146
 147         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
 148         /* Don't validate column using nand_chip->page_shift, it may be bigger
 149          * when accessing OOB */
 150
 151         for (i = 0; i < len; i += 4, data++) {
 152                 bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
 153
 154                 ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
 155                 if (i == len - 4) /* Last read goes without that */
 156                         ctlcode &= ~NCTL_CSA;
 157                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
 158                         pr_err("%s ctl_cmd didn't work!\n", __func__);
 159                         return;
 160                 }
 161         }
 162
 163         b47n->curr_column += len;
 164 }
 165
 166 /**************************************************
 167  * NAND chip ops
 168  **************************************************/
 169
 170 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
 171 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 172                                                   int chip)
 173 {
 174         return;
 175 }
 176
 177 static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 180         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 181
 182         return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
 183 }
 184
 185 /*
 186  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
 187  * For example, reading chip id is performed in a non-standard way.
 188  * Setting column and page is also handled differently, we use a special
 189  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
 190  * standard commands would be much more complicated.
 191  */
 192 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 193                                               unsigned command, int column,
 194                                               int page_addr)
 195 {
 196         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 197         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 198         struct bcma_drv_cc *cc = b47n->cc;
 199         u32 ctlcode;
 200         int i;
 201
 202         if (column != -1)
 203                 b47n->curr_column = column;
 204         if (page_addr != -1)
 205                 b47n->curr_page_addr = page_addr;
 206
 207         switch (command) {
 208         case NAND_CMD_RESET:
 209                 pr_warn("Chip reset not implemented yet\n");
 210                 break;
 211         case NAND_CMD_READID:
 212                 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
 213                 ctlcode |= NAND_CMD_READID;
 214                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
 215                         pr_err("READID error\n");
 216                         break;
 217                 }
 218
 219                 /*
 220                  * Reading is specific, last one has to go without NCTL_CSA
 221                  * bit. We don't know how many reads NAND subsystem is going
 222                  * to perform, so cache everything.
 223                  */
 224                 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
 225                         ctlcode = NCTL_CSA | NCTL_READ;
 226                         if (i == ARRAY_SIZE(b47n->id_data) - 1)
 227                                 ctlcode &= ~NCTL_CSA;
 228                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 229                                                               ctlcode)) {
 230                                 pr_err("READID error\n");
 231                                 break;
 232                         }
 233                         b47n->id_data[i] =
 234                                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
 235                                 & 0xFF;
 236                 }
 237
 238                 break;
 239         case NAND_CMD_STATUS:
 240                 ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
 241                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 242                         pr_err("STATUS command error\n");
 243                 break;
 244         case NAND_CMD_READ0:
 245                 break;
 246         case NAND_CMD_READOOB:
 247                 if (page_addr != -1)
 248                         b47n->curr_column += mtd->writesize;
 249                 break;
 250         case NAND_CMD_ERASE1:
 251                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 252                                 b47n->curr_page_addr);
 253                 ctlcode = 0x00040000 | NCTL_CMD1W | NCTL_CMD0 |
 254                           NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
 255                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 256                         pr_err("ERASE1 failed\n");
 257                 break;
 258         case NAND_CMD_ERASE2:
 259                 break;
 260         case NAND_CMD_SEQIN:
 261                 /* Set page and column */
 262                 bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
 263                                 b47n->curr_column);
 264                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 265                                 b47n->curr_page_addr);
 266
 267                 /* Prepare to write */
 268                 ctlcode = 0x40000000 | 0x00040000 | 0x00020000 | 0x00010000;
 269                 ctlcode |= NAND_CMD_SEQIN;
 270                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 271                         pr_err("SEQIN failed\n");
 272                 break;
 273         case NAND_CMD_PAGEPROG:
 274                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, 0x00010000 |
 275                                                           NAND_CMD_PAGEPROG))
 276                         pr_err("PAGEPROG failed\n");
 277                 if (bcm47xxnflash_ops_bcm4706_poll(cc))
 278                         pr_err("PAGEPROG not ready\n");
 279                 break;
 280         default:
 281                 pr_err("Command 0x%X unsupported\n", command);
 282                 break;
 283         }
 284         b47n->curr_command = command;
 285 }
 286
 287 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 288 {
 289         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 290         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 291         struct bcma_drv_cc *cc = b47n->cc;
 292         u32 tmp = 0;
 293
 294         switch (b47n->curr_command) {
 295         case NAND_CMD_READID:
 296                 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
 297                         pr_err("Requested invalid id_data: %d\n",
 298                                b47n->curr_column);
 299                         return 0;
 300                 }
 301                 return b47n->id_data[b47n->curr_column++];
 302         case NAND_CMD_STATUS:
 303                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
 304                         return 0;
 305                 return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
 306         case NAND_CMD_READOOB:
 307                 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
 308                 return tmp & 0xFF;
 309         }
 310
 311         pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 312         return 0;
 313 }
 314
 315 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
 316                                                uint8_t *buf, int len)
 317 {
 318         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 319         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 320
 321         switch (b47n->curr_command) {
 322         case NAND_CMD_READ0:
 323         case NAND_CMD_READOOB:
 324                 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
 325                 return;
 326         }
 327
 328         pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 329 }
 330
 331 static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd,
 332                                                 const uint8_t *buf, int len)
 333 {
 334         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 335         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 336
 337         switch (b47n->curr_command) {
 338         case NAND_CMD_SEQIN:
 339                 bcm47xxnflash_ops_bcm4706_write(mtd, buf, len);
 340                 return;
 341         }
 342
 343         pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
 344 }
 345
 346 /**************************************************
 347  * Init
 348  **************************************************/
 349
 350 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 351 {
 352         struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
 353         int err;
 354         u32 freq;
 355         u16 clock;
 356         u8 w0, w1, w2, w3, w4;
 357
 358         unsigned long chipsize; /* MiB */
 359         u8 tbits, col_bits, col_size, row_bits, row_bsize;
 360         u32 val;
 361
 362         b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 363         nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
 364         b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 365         b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 366         b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
 367         b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
 368
 369         nand_chip->chip_delay = 50;
 370         b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 371         b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 372
 373         /* Enable NAND flash access */
 374         bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 375                       BCMA_CC_4706_FLASHSCFG_NF1);
 376
 377         /* Configure wait counters */
 378         if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
 379                 /* 400 MHz */
 380                 freq = 400000000 / 4;
 381         } else {
 382                 freq = bcma_chipco_pll_read(b47n->cc, 4);
 383                 freq = (freq & 0xFFF) >> 3;
 384                 /* Fixed reference clock 25 MHz and m = 2 */
 385                 freq = (freq * 25000000 / 2) / 4;
 386         }
 387         clock = freq / 1000000;
 388         w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
 389         w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
 390         w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 391         w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 392         w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
 393         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
 394                         (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 395
 396         /* Scan NAND */
 397         err = nand_scan(&b47n->mtd, 1);
 398         if (err) {
 399                 pr_err("Could not scan NAND flash: %d\n", err);
 400                 goto exit;
 401         }
 402
 403         /* Configure FLASH */
 404         chipsize = b47n->nand_chip.chipsize >> 20;
 405         tbits = ffs(chipsize); /* find first bit set */
 406         if (!tbits || tbits != fls(chipsize)) {
 407                 pr_err("Invalid flash size: 0x%lX\n", chipsize);
 408                 err = -ENOTSUPP;
 409                 goto exit;
 410         }
 411         tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
 412
 413         col_bits = b47n->nand_chip.page_shift + 1;
 414         col_size = (col_bits + 7) / 8;
 415
 416         row_bits = tbits - col_bits + 1;
 417         row_bsize = (row_bits + 7) / 8;
 418
 419         val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
 420         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 421
 422 exit:
 423         if (err)
 424                 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 425                                ~BCMA_CC_4706_FLASHSCFG_NF1);
 426         return err;
 427 }