drivers/mtd/nand/brcmnand/brcmnand.c

   1 /*
   2  * Copyright © 2010-2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/version.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/completion.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/ioport.h>
  26 #include <linux/bug.h>
  27 #include <linux/kernel.h>
  28 #include <linux/bitops.h>
  29 #include <linux/mm.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mtd.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/slab.h>
  37 #include <linux/list.h>
  38 #include <linux/log2.h>
  39
  40 #include "brcmnand.h"
  41
  42 /*
  43  * This flag controls if WP stays on between erase/write commands to mitigate
  44  * flash corruption due to power glitches. Values:
  45  * 0: NAND_WP is not used or not available
  46  * 1: NAND_WP is set by default, cleared for erase/write operations
  47  * 2: NAND_WP is always cleared
  48  */
  49 static int wp_on = 1;
  50 module_param(wp_on, int, 0444);
  51
  52 /***********************************************************************
  53  * Definitions
  54  ***********************************************************************/
  55
  56 #define DRV_NAME                        "brcmnand"
  57
  58 #define CMD_NULL                        0x00
  59 #define CMD_PAGE_READ                   0x01
  60 #define CMD_SPARE_AREA_READ             0x02
  61 #define CMD_STATUS_READ                 0x03
  62 #define CMD_PROGRAM_PAGE                0x04
  63 #define CMD_PROGRAM_SPARE_AREA          0x05
  64 #define CMD_COPY_BACK                   0x06
  65 #define CMD_DEVICE_ID_READ              0x07
  66 #define CMD_BLOCK_ERASE                 0x08
  67 #define CMD_FLASH_RESET                 0x09
  68 #define CMD_BLOCKS_LOCK                 0x0a
  69 #define CMD_BLOCKS_LOCK_DOWN            0x0b
  70 #define CMD_BLOCKS_UNLOCK               0x0c
  71 #define CMD_READ_BLOCKS_LOCK_STATUS     0x0d
  72 #define CMD_PARAMETER_READ              0x0e
  73 #define CMD_PARAMETER_CHANGE_COL        0x0f
  74 #define CMD_LOW_LEVEL_OP                0x10
  75
  76 struct brcm_nand_dma_desc {
  77         u32 next_desc;
  78         u32 next_desc_ext;
  79         u32 cmd_irq;
  80         u32 dram_addr;
  81         u32 dram_addr_ext;
  82         u32 tfr_len;
  83         u32 total_len;
  84         u32 flash_addr;
  85         u32 flash_addr_ext;
  86         u32 cs;
  87         u32 pad2[5];
  88         u32 status_valid;
  89 } __packed;
  90
  91 /* Bitfields for brcm_nand_dma_desc::status_valid */
  92 #define FLASH_DMA_ECC_ERROR     (1 << 8)
  93 #define FLASH_DMA_CORR_ERROR    (1 << 9)
  94
  95 /* 512B flash cache in the NAND controller HW */
  96 #define FC_SHIFT                9U
  97 #define FC_BYTES                512U
  98 #define FC_WORDS                (FC_BYTES >> 2)
  99
 100 #define BRCMNAND_MIN_PAGESIZE   512
 101 #define BRCMNAND_MIN_BLOCKSIZE  (8 * 1024)
 102 #define BRCMNAND_MIN_DEVSIZE    (4ULL * 1024 * 1024)
 103
 104 /* Controller feature flags */
 105 enum {
 106         BRCMNAND_HAS_1K_SECTORS                 = BIT(0),
 107         BRCMNAND_HAS_PREFETCH                   = BIT(1),
 108         BRCMNAND_HAS_CACHE_MODE                 = BIT(2),
 109         BRCMNAND_HAS_WP                         = BIT(3),
 110 };
 111
 112 struct brcmnand_controller {
 113         struct device           *dev;
 114         struct nand_hw_control  controller;
 115         void __iomem            *nand_base;
 116         void __iomem            *nand_fc; /* flash cache */
 117         void __iomem            *flash_dma_base;
 118         unsigned int            irq;
 119         unsigned int            dma_irq;
 120         int                     nand_version;
 121
 122         int                     cmd_pending;
 123         bool                    dma_pending;
 124         struct completion       done;
 125         struct completion       dma_done;
 126
 127         /* List of NAND hosts (one for each chip-select) */
 128         struct list_head host_list;
 129
 130         struct brcm_nand_dma_desc *dma_desc;
 131         dma_addr_t              dma_pa;
 132
 133         /* in-memory cache of the FLASH_CACHE, used only for some commands */
 134         u32                     flash_cache[FC_WORDS];
 135
 136         /* Controller revision details */
 137         const u16               *reg_offsets;
 138         unsigned int            reg_spacing; /* between CS1, CS2, ... regs */
 139         const u8                *cs_offsets; /* within each chip-select */
 140         const u8                *cs0_offsets; /* within CS0, if different */
 141         unsigned int            max_block_size;
 142         const unsigned int      *block_sizes;
 143         unsigned int            max_page_size;
 144         const unsigned int      *page_sizes;
 145         unsigned int            max_oob;
 146         u32                     features;
 147
 148         /* for low-power standby/resume only */
 149         u32                     nand_cs_nand_select;
 150         u32                     nand_cs_nand_xor;
 151         u32                     corr_stat_threshold;
 152         u32                     flash_dma_mode;
 153 };
 154
 155 struct brcmnand_cfg {
 156         u64                     device_size;
 157         unsigned int            block_size;
 158         unsigned int            page_size;
 159         unsigned int            spare_area_size;
 160         unsigned int            device_width;
 161         unsigned int            col_adr_bytes;
 162         unsigned int            blk_adr_bytes;
 163         unsigned int            ful_adr_bytes;
 164         unsigned int            sector_size_1k;
 165         unsigned int            ecc_level;
 166         /* use for low-power standby/resume only */
 167         u32                     acc_control;
 168         u32                     config;
 169         u32                     config_ext;
 170         u32                     timing_1;
 171         u32                     timing_2;
 172 };
 173
 174 struct brcmnand_host {
 175         struct list_head        node;
 176         struct device_node      *of_node;
 177
 178         struct nand_chip        chip;
 179         struct mtd_info         mtd;
 180         struct platform_device  *pdev;
 181         int                     cs;
 182
 183         unsigned int            last_cmd;
 184         unsigned int            last_byte;
 185         u64                     last_addr;
 186         struct brcmnand_cfg     hwcfg;
 187         struct brcmnand_controller *ctrl;
 188 };
 189
 190 enum brcmnand_reg {
 191         BRCMNAND_CMD_START = 0,
 192         BRCMNAND_CMD_EXT_ADDRESS,
 193         BRCMNAND_CMD_ADDRESS,
 194         BRCMNAND_INTFC_STATUS,
 195         BRCMNAND_CS_SELECT,
 196         BRCMNAND_CS_XOR,
 197         BRCMNAND_LL_OP,
 198         BRCMNAND_CS0_BASE,
 199         BRCMNAND_CS1_BASE,              /* CS1 regs, if non-contiguous */
 200         BRCMNAND_CORR_THRESHOLD,
 201         BRCMNAND_CORR_THRESHOLD_EXT,
 202         BRCMNAND_UNCORR_COUNT,
 203         BRCMNAND_CORR_COUNT,
 204         BRCMNAND_CORR_EXT_ADDR,
 205         BRCMNAND_CORR_ADDR,
 206         BRCMNAND_UNCORR_EXT_ADDR,
 207         BRCMNAND_UNCORR_ADDR,
 208         BRCMNAND_SEMAPHORE,
 209         BRCMNAND_ID,
 210         BRCMNAND_ID_EXT,
 211         BRCMNAND_LL_RDATA,
 212         BRCMNAND_OOB_READ_BASE,
 213         BRCMNAND_OOB_READ_10_BASE,      /* offset 0x10, if non-contiguous */
 214         BRCMNAND_OOB_WRITE_BASE,
 215         BRCMNAND_OOB_WRITE_10_BASE,     /* offset 0x10, if non-contiguous */
 216         BRCMNAND_FC_BASE,
 217 };
 218
 219 /* BRCMNAND v4.0 */
 220 static const u16 brcmnand_regs_v40[] = {
 221         [BRCMNAND_CMD_START]            =  0x04,
 222         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 223         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 224         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 225         [BRCMNAND_CS_SELECT]            =  0x14,
 226         [BRCMNAND_CS_XOR]               =  0x18,
 227         [BRCMNAND_LL_OP]                = 0x178,
 228         [BRCMNAND_CS0_BASE]             =  0x40,
 229         [BRCMNAND_CS1_BASE]             =  0xd0,
 230         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 231         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 232         [BRCMNAND_UNCORR_COUNT]         =     0,
 233         [BRCMNAND_CORR_COUNT]           =     0,
 234         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 235         [BRCMNAND_CORR_ADDR]            =  0x74,
 236         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 237         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 238         [BRCMNAND_SEMAPHORE]            =  0x58,
 239         [BRCMNAND_ID]                   =  0x60,
 240         [BRCMNAND_ID_EXT]               =  0x64,
 241         [BRCMNAND_LL_RDATA]             = 0x17c,
 242         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 243         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 244         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 245         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 246         [BRCMNAND_FC_BASE]              = 0x200,
 247 };
 248
 249 /* BRCMNAND v5.0 */
 250 static const u16 brcmnand_regs_v50[] = {
 251         [BRCMNAND_CMD_START]            =  0x04,
 252         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 253         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 254         [BRCMNAND_INTFC_STATUS]         =  0x6c,
 255         [BRCMNAND_CS_SELECT]            =  0x14,
 256         [BRCMNAND_CS_XOR]               =  0x18,
 257         [BRCMNAND_LL_OP]                = 0x178,
 258         [BRCMNAND_CS0_BASE]             =  0x40,
 259         [BRCMNAND_CS1_BASE]             =  0xd0,
 260         [BRCMNAND_CORR_THRESHOLD]       =  0x84,
 261         [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
 262         [BRCMNAND_UNCORR_COUNT]         =     0,
 263         [BRCMNAND_CORR_COUNT]           =     0,
 264         [BRCMNAND_CORR_EXT_ADDR]        =  0x70,
 265         [BRCMNAND_CORR_ADDR]            =  0x74,
 266         [BRCMNAND_UNCORR_EXT_ADDR]      =  0x78,
 267         [BRCMNAND_UNCORR_ADDR]          =  0x7c,
 268         [BRCMNAND_SEMAPHORE]            =  0x58,
 269         [BRCMNAND_ID]                   =  0x60,
 270         [BRCMNAND_ID_EXT]               =  0x64,
 271         [BRCMNAND_LL_RDATA]             = 0x17c,
 272         [BRCMNAND_OOB_READ_BASE]        =  0x20,
 273         [BRCMNAND_OOB_READ_10_BASE]     = 0x130,
 274         [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
 275         [BRCMNAND_OOB_WRITE_10_BASE]    = 0x140,
 276         [BRCMNAND_FC_BASE]              = 0x200,
 277 };
 278
 279 /* BRCMNAND v6.0 - v7.1 */
 280 static const u16 brcmnand_regs_v60[] = {
 281         [BRCMNAND_CMD_START]            =  0x04,
 282         [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
 283         [BRCMNAND_CMD_ADDRESS]          =  0x0c,
 284         [BRCMNAND_INTFC_STATUS]         =  0x14,
 285         [BRCMNAND_CS_SELECT]            =  0x18,
 286         [BRCMNAND_CS_XOR]               =  0x1c,
 287         [BRCMNAND_LL_OP]                =  0x20,
 288         [BRCMNAND_CS0_BASE]             =  0x50,
 289         [BRCMNAND_CS1_BASE]             =     0,
 290         [BRCMNAND_CORR_THRESHOLD]       =  0xc0,
 291         [BRCMNAND_CORR_THRESHOLD_EXT]   =  0xc4,
 292         [BRCMNAND_UNCORR_COUNT]         =  0xfc,
 293         [BRCMNAND_CORR_COUNT]           = 0x100,
 294         [BRCMNAND_CORR_EXT_ADDR]        = 0x10c,
 295         [BRCMNAND_CORR_ADDR]            = 0x110,
 296         [BRCMNAND_UNCORR_EXT_ADDR]      = 0x114,
 297         [BRCMNAND_UNCORR_ADDR]          = 0x118,
 298         [BRCMNAND_SEMAPHORE]            = 0x150,
 299         [BRCMNAND_ID]                   = 0x194,
 300         [BRCMNAND_ID_EXT]               = 0x198,
 301         [BRCMNAND_LL_RDATA]             = 0x19c,
 302         [BRCMNAND_OOB_READ_BASE]        = 0x200,
 303         [BRCMNAND_OOB_READ_10_BASE]     =     0,
 304         [BRCMNAND_OOB_WRITE_BASE]       = 0x280,
 305         [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
 306         [BRCMNAND_FC_BASE]              = 0x400,
 307 };
 308
 309 enum brcmnand_cs_reg {
 310         BRCMNAND_CS_CFG_EXT = 0,
 311         BRCMNAND_CS_CFG,
 312         BRCMNAND_CS_ACC_CONTROL,
 313         BRCMNAND_CS_TIMING1,
 314         BRCMNAND_CS_TIMING2,
 315 };
 316
 317 /* Per chip-select offsets for v7.1 */
 318 static const u8 brcmnand_cs_offsets_v71[] = {
 319         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 320         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 321         [BRCMNAND_CS_CFG]               = 0x08,
 322         [BRCMNAND_CS_TIMING1]           = 0x0c,
 323         [BRCMNAND_CS_TIMING2]           = 0x10,
 324 };
 325
 326 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
 327 static const u8 brcmnand_cs_offsets[] = {
 328         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 329         [BRCMNAND_CS_CFG_EXT]           = 0x04,
 330         [BRCMNAND_CS_CFG]               = 0x04,
 331         [BRCMNAND_CS_TIMING1]           = 0x08,
 332         [BRCMNAND_CS_TIMING2]           = 0x0c,
 333 };
 334
 335 /* Per chip-select offset for <= v5.0 on CS0 only */
 336 static const u8 brcmnand_cs_offsets_cs0[] = {
 337         [BRCMNAND_CS_ACC_CONTROL]       = 0x00,
 338         [BRCMNAND_CS_CFG_EXT]           = 0x08,
 339         [BRCMNAND_CS_CFG]               = 0x08,
 340         [BRCMNAND_CS_TIMING1]           = 0x10,
 341         [BRCMNAND_CS_TIMING2]           = 0x14,
 342 };
 343
 344 /* BRCMNAND_INTFC_STATUS */
 345 enum {
 346         INTFC_FLASH_STATUS              = GENMASK(7, 0),
 347
 348         INTFC_ERASED                    = BIT(27),
 349         INTFC_OOB_VALID                 = BIT(28),
 350         INTFC_CACHE_VALID               = BIT(29),
 351         INTFC_FLASH_READY               = BIT(30),
 352         INTFC_CTLR_READY                = BIT(31),
 353 };
 354
 355 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
 356 {
 357         return brcmnand_readl(ctrl->nand_base + offs);
 358 }
 359
 360 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
 361                                  u32 val)
 362 {
 363         brcmnand_writel(val, ctrl->nand_base + offs);
 364 }
 365
 366 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
 367 {
 368         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
 369         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
 370         static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
 371
 372         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
 373
 374         /* Only support v4.0+? */
 375         if (ctrl->nand_version < 0x0400) {
 376                 dev_err(ctrl->dev, "version %#x not supported\n",
 377                         ctrl->nand_version);
 378                 return -ENODEV;
 379         }
 380
 381         /* Register offsets */
 382         if (ctrl->nand_version >= 0x0600)
 383                 ctrl->reg_offsets = brcmnand_regs_v60;
 384         else if (ctrl->nand_version >= 0x0500)
 385                 ctrl->reg_offsets = brcmnand_regs_v50;
 386         else if (ctrl->nand_version >= 0x0400)
 387                 ctrl->reg_offsets = brcmnand_regs_v40;
 388
 389         /* Chip-select stride */
 390         if (ctrl->nand_version >= 0x0701)
 391                 ctrl->reg_spacing = 0x14;
 392         else
 393                 ctrl->reg_spacing = 0x10;
 394
 395         /* Per chip-select registers */
 396         if (ctrl->nand_version >= 0x0701) {
 397                 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
 398         } else {
 399                 ctrl->cs_offsets = brcmnand_cs_offsets;
 400
 401                 /* v5.0 and earlier has a different CS0 offset layout */
 402                 if (ctrl->nand_version <= 0x0500)
 403                         ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
 404         }
 405
 406         /* Page / block sizes */
 407         if (ctrl->nand_version >= 0x0701) {
 408                 /* >= v7.1 use nice power-of-2 values! */
 409                 ctrl->max_page_size = 16 * 1024;
 410                 ctrl->max_block_size = 2 * 1024 * 1024;
 411         } else {
 412                 ctrl->page_sizes = page_sizes;
 413                 if (ctrl->nand_version >= 0x0600)
 414                         ctrl->block_sizes = block_sizes_v6;
 415                 else
 416                         ctrl->block_sizes = block_sizes_v4;
 417
 418                 if (ctrl->nand_version < 0x0400) {
 419                         ctrl->max_page_size = 4096;
 420                         ctrl->max_block_size = 512 * 1024;
 421                 }
 422         }
 423
 424         /* Maximum spare area sector size (per 512B) */
 425         if (ctrl->nand_version >= 0x0600)
 426                 ctrl->max_oob = 64;
 427         else if (ctrl->nand_version >= 0x0500)
 428                 ctrl->max_oob = 32;
 429         else
 430                 ctrl->max_oob = 16;
 431
 432         /* v6.0 and newer (except v6.1) have prefetch support */
 433         if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
 434                 ctrl->features |= BRCMNAND_HAS_PREFETCH;
 435
 436         /*
 437          * v6.x has cache mode, but it's implemented differently. Ignore it for
 438          * now.
 439          */
 440         if (ctrl->nand_version >= 0x0700)
 441                 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
 442
 443         if (ctrl->nand_version >= 0x0500)
 444                 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
 445
 446         if (ctrl->nand_version >= 0x0700)
 447                 ctrl->features |= BRCMNAND_HAS_WP;
 448         else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
 449                 ctrl->features |= BRCMNAND_HAS_WP;
 450
 451         return 0;
 452 }
 453
 454 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
 455                 enum brcmnand_reg reg)
 456 {
 457         u16 offs = ctrl->reg_offsets[reg];
 458
 459         if (offs)
 460                 return nand_readreg(ctrl, offs);
 461         else
 462                 return 0;
 463 }
 464
 465 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
 466                                       enum brcmnand_reg reg, u32 val)
 467 {
 468         u16 offs = ctrl->reg_offsets[reg];
 469
 470         if (offs)
 471                 nand_writereg(ctrl, offs, val);
 472 }
 473
 474 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
 475                                     enum brcmnand_reg reg, u32 mask, unsigned
 476                                     int shift, u32 val)
 477 {
 478         u32 tmp = brcmnand_read_reg(ctrl, reg);
 479
 480         tmp &= ~mask;
 481         tmp |= val << shift;
 482         brcmnand_write_reg(ctrl, reg, tmp);
 483 }
 484
 485 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
 486 {
 487         return __raw_readl(ctrl->nand_fc + word * 4);
 488 }
 489
 490 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
 491                                      int word, u32 val)
 492 {
 493         __raw_writel(val, ctrl->nand_fc + word * 4);
 494 }
 495
 496 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
 497                                      enum brcmnand_cs_reg reg)
 498 {
 499         u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
 500         u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
 501         u8 cs_offs;
 502
 503         if (cs == 0 && ctrl->cs0_offsets)
 504                 cs_offs = ctrl->cs0_offsets[reg];
 505         else
 506                 cs_offs = ctrl->cs_offsets[reg];
 507
 508         if (cs && offs_cs1)
 509                 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
 510
 511         return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
 512 }
 513
 514 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
 515 {
 516         if (ctrl->nand_version < 0x0600)
 517                 return 1;
 518         return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
 519 }
 520
 521 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
 522 {
 523         struct brcmnand_controller *ctrl = host->ctrl;
 524         unsigned int shift = 0, bits;
 525         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 526         int cs = host->cs;
 527
 528         if (ctrl->nand_version >= 0x0600)
 529                 bits = 6;
 530         else if (ctrl->nand_version >= 0x0500)
 531                 bits = 5;
 532         else
 533                 bits = 4;
 534
 535         if (ctrl->nand_version >= 0x0600) {
 536                 if (cs >= 5)
 537                         reg = BRCMNAND_CORR_THRESHOLD_EXT;
 538                 shift = (cs % 5) * bits;
 539         }
 540         brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
 541 }
 542
 543 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
 544 {
 545         if (ctrl->nand_version < 0x0700)
 546                 return 24;
 547         return 0;
 548 }
 549
 550 /***********************************************************************
 551  * NAND ACC CONTROL bitfield
 552  *
 553  * Some bits have remained constant throughout hardware revision, while
 554  * others have shifted around.
 555  ***********************************************************************/
 556
 557 /* Constant for all versions (where supported) */
 558 enum {
 559         /* See BRCMNAND_HAS_CACHE_MODE */
 560         ACC_CONTROL_CACHE_MODE                          = BIT(22),
 561
 562         /* See BRCMNAND_HAS_PREFETCH */
 563         ACC_CONTROL_PREFETCH                            = BIT(23),
 564
 565         ACC_CONTROL_PAGE_HIT                            = BIT(24),
 566         ACC_CONTROL_WR_PREEMPT                          = BIT(25),
 567         ACC_CONTROL_PARTIAL_PAGE                        = BIT(26),
 568         ACC_CONTROL_RD_ERASED                           = BIT(27),
 569         ACC_CONTROL_FAST_PGM_RDIN                       = BIT(28),
 570         ACC_CONTROL_WR_ECC                              = BIT(30),
 571         ACC_CONTROL_RD_ECC                              = BIT(31),
 572 };
 573
 574 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
 575 {
 576         if (ctrl->nand_version >= 0x0600)
 577                 return GENMASK(6, 0);
 578         else
 579                 return GENMASK(5, 0);
 580 }
 581
 582 #define NAND_ACC_CONTROL_ECC_SHIFT      16
 583
 584 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 585 {
 586         u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
 587
 588         return mask << NAND_ACC_CONTROL_ECC_SHIFT;
 589 }
 590
 591 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 592 {
 593         struct brcmnand_controller *ctrl = host->ctrl;
 594         u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
 595         u32 acc_control = nand_readreg(ctrl, offs);
 596         u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
 597
 598         if (en) {
 599                 acc_control |= ecc_flags; /* enable RD/WR ECC */
 600                 acc_control |= host->hwcfg.ecc_level
 601                                << NAND_ACC_CONTROL_ECC_SHIFT;
 602         } else {
 603                 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
 604                 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
 605         }
 606
 607         nand_writereg(ctrl, offs, acc_control);
 608 }
 609
 610 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
 611 {
 612         if (ctrl->nand_version >= 0x0600)
 613                 return 7;
 614         else if (ctrl->nand_version >= 0x0500)
 615                 return 6;
 616         else
 617                 return -1;
 618 }
 619
 620 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
 621 {
 622         struct brcmnand_controller *ctrl = host->ctrl;
 623         int shift = brcmnand_sector_1k_shift(ctrl);
 624         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 625                                                   BRCMNAND_CS_ACC_CONTROL);
 626
 627         if (shift < 0)
 628                 return 0;
 629
 630         return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
 631 }
 632
 633 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 634 {
 635         struct brcmnand_controller *ctrl = host->ctrl;
 636         int shift = brcmnand_sector_1k_shift(ctrl);
 637         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
 638                                                   BRCMNAND_CS_ACC_CONTROL);
 639         u32 tmp;
 640
 641         if (shift < 0)
 642                 return;
 643
 644         tmp = nand_readreg(ctrl, acc_control_offs);
 645         tmp &= ~(1 << shift);
 646         tmp |= (!!val) << shift;
 647         nand_writereg(ctrl, acc_control_offs, tmp);
 648 }
 649
 650 /***********************************************************************
 651  * CS_NAND_SELECT
 652  ***********************************************************************/
 653
 654 enum {
 655         CS_SELECT_NAND_WP                       = BIT(29),
 656         CS_SELECT_AUTO_DEVICE_ID_CFG            = BIT(30),
 657 };
 658
 659 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
 660 {
 661         u32 val = en ? CS_SELECT_NAND_WP : 0;
 662
 663         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
 664 }
 665
 666 /***********************************************************************
 667  * Flash DMA
 668  ***********************************************************************/
 669
 670 enum flash_dma_reg {
 671         FLASH_DMA_REVISION              = 0x00,
 672         FLASH_DMA_FIRST_DESC            = 0x04,
 673         FLASH_DMA_FIRST_DESC_EXT        = 0x08,
 674         FLASH_DMA_CTRL                  = 0x0c,
 675         FLASH_DMA_MODE                  = 0x10,
 676         FLASH_DMA_STATUS                = 0x14,
 677         FLASH_DMA_INTERRUPT_DESC        = 0x18,
 678         FLASH_DMA_INTERRUPT_DESC_EXT    = 0x1c,
 679         FLASH_DMA_ERROR_STATUS          = 0x20,
 680         FLASH_DMA_CURRENT_DESC          = 0x24,
 681         FLASH_DMA_CURRENT_DESC_EXT      = 0x28,
 682 };
 683
 684 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
 685 {
 686         return ctrl->flash_dma_base;
 687 }
 688
 689 static inline bool flash_dma_buf_ok(const void *buf)
 690 {
 691         return buf && !is_vmalloc_addr(buf) &&
 692                 likely(IS_ALIGNED((uintptr_t)buf, 4));
 693 }
 694
 695 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
 696                                     u32 val)
 697 {
 698         brcmnand_writel(val, ctrl->flash_dma_base + offs);
 699 }
 700
 701 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
 702 {
 703         return brcmnand_readl(ctrl->flash_dma_base + offs);
 704 }
 705
 706 /* Low-level operation types: command, address, write, or read */
 707 enum brcmnand_llop_type {
 708         LL_OP_CMD,
 709         LL_OP_ADDR,
 710         LL_OP_WR,
 711         LL_OP_RD,
 712 };
 713
 714 /***********************************************************************
 715  * Internal support functions
 716  ***********************************************************************/
 717
 718 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
 719 {
 720         return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
 721                 cfg->ecc_level == 15;
 722 }
 723
 724 /*
 725  * Returns a nand_ecclayout strucutre for the given layout/configuration.
 726  * Returns NULL on failure.
 727  */
 728 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
 729                                                      struct brcmnand_host *host)
 730 {
 731         struct brcmnand_cfg *cfg = &host->hwcfg;
 732         int i, j;
 733         struct nand_ecclayout *layout;
 734         int req;
 735         int sectors;
 736         int sas;
 737         int idx1, idx2;
 738
 739         layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
 740         if (!layout)
 741                 return NULL;
 742
 743         sectors = cfg->page_size / (512 << cfg->sector_size_1k);
 744         sas = cfg->spare_area_size << cfg->sector_size_1k;
 745
 746         /* Hamming */
 747         if (is_hamming_ecc(cfg)) {
 748                 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 749                         /* First sector of each page may have BBI */
 750                         if (i == 0) {
 751                                 layout->oobfree[idx2].offset = i * sas + 1;
 752                                 /* Small-page NAND use byte 6 for BBI */
 753                                 if (cfg->page_size == 512)
 754                                         layout->oobfree[idx2].offset--;
 755                                 layout->oobfree[idx2].length = 5;
 756                         } else {
 757                                 layout->oobfree[idx2].offset = i * sas;
 758                                 layout->oobfree[idx2].length = 6;
 759                         }
 760                         idx2++;
 761                         layout->eccpos[idx1++] = i * sas + 6;
 762                         layout->eccpos[idx1++] = i * sas + 7;
 763                         layout->eccpos[idx1++] = i * sas + 8;
 764                         layout->oobfree[idx2].offset = i * sas + 9;
 765                         layout->oobfree[idx2].length = 7;
 766                         idx2++;
 767                         /* Leave zero-terminated entry for OOBFREE */
 768                         if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 769                                     idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 770                                 break;
 771                 }
 772                 goto out;
 773         }
 774
 775         /*
 776          * CONTROLLER_VERSION:
 777          *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
 778          *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
 779          * But we will just be conservative.
 780          */
 781         req = DIV_ROUND_UP(ecc_level * 14, 8);
 782         if (req >= sas) {
 783                 dev_err(&host->pdev->dev,
 784                         "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
 785                         req, sas);
 786                 return NULL;
 787         }
 788
 789         layout->eccbytes = req * sectors;
 790         for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
 791                 for (j = sas - req; j < sas && idx1 <
 792                                 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
 793                         layout->eccpos[idx1] = i * sas + j;
 794
 795                 /* First sector of each page may have BBI */
 796                 if (i == 0) {
 797                         if (cfg->page_size == 512 && (sas - req >= 6)) {
 798                                 /* Small-page NAND use byte 6 for BBI */
 799                                 layout->oobfree[idx2].offset = 0;
 800                                 layout->oobfree[idx2].length = 5;
 801                                 idx2++;
 802                                 if (sas - req > 6) {
 803                                         layout->oobfree[idx2].offset = 6;
 804                                         layout->oobfree[idx2].length =
 805                                                 sas - req - 6;
 806                                         idx2++;
 807                                 }
 808                         } else if (sas > req + 1) {
 809                                 layout->oobfree[idx2].offset = i * sas + 1;
 810                                 layout->oobfree[idx2].length = sas - req - 1;
 811                                 idx2++;
 812                         }
 813                 } else if (sas > req) {
 814                         layout->oobfree[idx2].offset = i * sas;
 815                         layout->oobfree[idx2].length = sas - req;
 816                         idx2++;
 817                 }
 818                 /* Leave zero-terminated entry for OOBFREE */
 819                 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
 820                                 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
 821                         break;
 822         }
 823 out:
 824         /* Sum available OOB */
 825         for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
 826                 layout->oobavail += layout->oobfree[i].length;
 827         return layout;
 828 }
 829
 830 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
 831                 struct brcmnand_host *host)
 832 {
 833         struct nand_ecclayout *layout;
 834         struct brcmnand_cfg *p = &host->hwcfg;
 835         unsigned int ecc_level = p->ecc_level;
 836
 837         if (p->sector_size_1k)
 838                 ecc_level <<= 1;
 839
 840         layout = brcmnand_create_layout(ecc_level, host);
 841         if (!layout) {
 842                 dev_err(&host->pdev->dev,
 843                                 "no proper ecc_layout for this NAND cfg\n");
 844                 return NULL;
 845         }
 846
 847         return layout;
 848 }
 849
 850 static void brcmnand_wp(struct mtd_info *mtd, int wp)
 851 {
 852         struct nand_chip *chip = mtd->priv;
 853         struct brcmnand_host *host = chip->priv;
 854         struct brcmnand_controller *ctrl = host->ctrl;
 855
 856         if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
 857                 static int old_wp = -1;
 858
 859                 if (old_wp != wp) {
 860                         dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
 861                         old_wp = wp;
 862                 }
 863                 brcmnand_set_wp(ctrl, wp);
 864         }
 865 }
 866
 867 /* Helper functions for reading and writing OOB registers */
 868 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
 869 {
 870         u16 offset0, offset10, reg_offs;
 871
 872         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
 873         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
 874
 875         if (offs >= ctrl->max_oob)
 876                 return 0x77;
 877
 878         if (offs >= 16 && offset10)
 879                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 880         else
 881                 reg_offs = offset0 + (offs & ~0x03);
 882
 883         return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
 884 }
 885
 886 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
 887                                  u32 data)
 888 {
 889         u16 offset0, offset10, reg_offs;
 890
 891         offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
 892         offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
 893
 894         if (offs >= ctrl->max_oob)
 895                 return;
 896
 897         if (offs >= 16 && offset10)
 898                 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
 899         else
 900                 reg_offs = offset0 + (offs & ~0x03);
 901
 902         nand_writereg(ctrl, reg_offs, data);
 903 }
 904
 905 /*
 906  * read_oob_from_regs - read data from OOB registers
 907  * @ctrl: NAND controller
 908  * @i: sub-page sector index
 909  * @oob: buffer to read to
 910  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 911  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 912  */
 913 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
 914                               int sas, int sector_1k)
 915 {
 916         int tbytes = sas << sector_1k;
 917         int j;
 918
 919         /* Adjust OOB values for 1K sector size */
 920         if (sector_1k && (i & 0x01))
 921                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
 922         tbytes = min_t(int, tbytes, ctrl->max_oob);
 923
 924         for (j = 0; j < tbytes; j++)
 925                 oob[j] = oob_reg_read(ctrl, j);
 926         return tbytes;
 927 }
 928
 929 /*
 930  * write_oob_to_regs - write data to OOB registers
 931  * @i: sub-page sector index
 932  * @oob: buffer to write from
 933  * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
 934  * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
 935  */
 936 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
 937                              const u8 *oob, int sas, int sector_1k)
 938 {
 939         int tbytes = sas << sector_1k;
 940         int j;
 941
 942         /* Adjust OOB values for 1K sector size */
 943         if (sector_1k && (i & 0x01))
 944                 tbytes = max(0, tbytes - (int)ctrl->max_oob);
 945         tbytes = min_t(int, tbytes, ctrl->max_oob);
 946
 947         for (j = 0; j < tbytes; j += 4)
 948                 oob_reg_write(ctrl, j,
 949                                 (oob[j + 0] << 24) |
 950                                 (oob[j + 1] << 16) |
 951                                 (oob[j + 2] <<  8) |
 952                                 (oob[j + 3] <<  0));
 953         return tbytes;
 954 }
 955
 956 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
 957 {
 958         struct brcmnand_controller *ctrl = data;
 959
 960         /* Discard all NAND_CTLRDY interrupts during DMA */
 961         if (ctrl->dma_pending)
 962                 return IRQ_HANDLED;
 963
 964         complete(&ctrl->done);
 965         return IRQ_HANDLED;
 966 }
 967
 968 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
 969 {
 970         struct brcmnand_controller *ctrl = data;
 971
 972         complete(&ctrl->dma_done);
 973
 974         return IRQ_HANDLED;
 975 }
 976
 977 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
 978 {
 979         struct brcmnand_controller *ctrl = host->ctrl;
 980         u32 intfc;
 981
 982         dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
 983                 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
 984         BUG_ON(ctrl->cmd_pending != 0);
 985         ctrl->cmd_pending = cmd;
 986
 987         intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
 988         BUG_ON(!(intfc & INTFC_CTLR_READY));
 989
 990         mb(); /* flush previous writes */
 991         brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
 992                            cmd << brcmnand_cmd_shift(ctrl));
 993 }
 994
 995 /***********************************************************************
 996  * NAND MTD API: read/program/erase
 997  ***********************************************************************/
 998
 999 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1000         unsigned int ctrl)
1001 {
1002         /* intentionally left blank */
1003 }
1004
1005 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1006 {
1007         struct nand_chip *chip = mtd->priv;
1008         struct brcmnand_host *host = chip->priv;
1009         struct brcmnand_controller *ctrl = host->ctrl;
1010         unsigned long timeo = msecs_to_jiffies(100);
1011
1012         dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1013         if (ctrl->cmd_pending &&
1014                         wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1015                 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1016                                         >> brcmnand_cmd_shift(ctrl);
1017
1018                 dev_err_ratelimited(ctrl->dev,
1019                         "timeout waiting for command %#02x\n", cmd);
1020                 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1021                         brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1022         }
1023         ctrl->cmd_pending = 0;
1024         return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1025                                  INTFC_FLASH_STATUS;
1026 }
1027
1028 enum {
1029         LLOP_RE                         = BIT(16),
1030         LLOP_WE                         = BIT(17),
1031         LLOP_ALE                        = BIT(18),
1032         LLOP_CLE                        = BIT(19),
1033         LLOP_RETURN_IDLE                = BIT(31),
1034
1035         LLOP_DATA_MASK                  = GENMASK(15, 0),
1036 };
1037
1038 static int brcmnand_low_level_op(struct brcmnand_host *host,
1039                                  enum brcmnand_llop_type type, u32 data,
1040                                  bool last_op)
1041 {
1042         struct mtd_info *mtd = &host->mtd;
1043         struct nand_chip *chip = &host->chip;
1044         struct brcmnand_controller *ctrl = host->ctrl;
1045         u32 tmp;
1046
1047         tmp = data & LLOP_DATA_MASK;
1048         switch (type) {
1049         case LL_OP_CMD:
1050                 tmp |= LLOP_WE | LLOP_CLE;
1051                 break;
1052         case LL_OP_ADDR:
1053                 /* WE | ALE */
1054                 tmp |= LLOP_WE | LLOP_ALE;
1055                 break;
1056         case LL_OP_WR:
1057                 /* WE */
1058                 tmp |= LLOP_WE;
1059                 break;
1060         case LL_OP_RD:
1061                 /* RE */
1062                 tmp |= LLOP_RE;
1063                 break;
1064         }
1065         if (last_op)
1066                 /* RETURN_IDLE */
1067                 tmp |= LLOP_RETURN_IDLE;
1068
1069         dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1070
1071         brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1072         (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1073
1074         brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1075         return brcmnand_waitfunc(mtd, chip);
1076 }
1077
1078 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1079                              int column, int page_addr)
1080 {
1081         struct nand_chip *chip = mtd->priv;
1082         struct brcmnand_host *host = chip->priv;
1083         struct brcmnand_controller *ctrl = host->ctrl;
1084         u64 addr = (u64)page_addr << chip->page_shift;
1085         int native_cmd = 0;
1086
1087         if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1088                         command == NAND_CMD_RNDOUT)
1089                 addr = (u64)column;
1090         /* Avoid propagating a negative, don't-care address */
1091         else if (page_addr < 0)
1092                 addr = 0;
1093
1094         dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1095                 (unsigned long long)addr);
1096
1097         host->last_cmd = command;
1098         host->last_byte = 0;
1099         host->last_addr = addr;
1100
1101         switch (command) {
1102         case NAND_CMD_RESET:
1103                 native_cmd = CMD_FLASH_RESET;
1104                 break;
1105         case NAND_CMD_STATUS:
1106                 native_cmd = CMD_STATUS_READ;
1107                 break;
1108         case NAND_CMD_READID:
1109                 native_cmd = CMD_DEVICE_ID_READ;
1110                 break;
1111         case NAND_CMD_READOOB:
1112                 native_cmd = CMD_SPARE_AREA_READ;
1113                 break;
1114         case NAND_CMD_ERASE1:
1115                 native_cmd = CMD_BLOCK_ERASE;
1116                 brcmnand_wp(mtd, 0);
1117                 break;
1118         case NAND_CMD_PARAM:
1119                 native_cmd = CMD_PARAMETER_READ;
1120                 break;
1121         case NAND_CMD_SET_FEATURES:
1122         case NAND_CMD_GET_FEATURES:
1123                 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1124                 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1125                 break;
1126         case NAND_CMD_RNDOUT:
1127                 native_cmd = CMD_PARAMETER_CHANGE_COL;
1128                 addr &= ~((u64)(FC_BYTES - 1));
1129                 /*
1130                  * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1131                  * NB: hwcfg.sector_size_1k may not be initialized yet
1132                  */
1133                 if (brcmnand_get_sector_size_1k(host)) {
1134                         host->hwcfg.sector_size_1k =
1135                                 brcmnand_get_sector_size_1k(host);
1136                         brcmnand_set_sector_size_1k(host, 0);
1137                 }
1138                 break;
1139         }
1140
1141         if (!native_cmd)
1142                 return;
1143
1144         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1145                 (host->cs << 16) | ((addr >> 32) & 0xffff));
1146         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1147         brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1148         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1149
1150         brcmnand_send_cmd(host, native_cmd);
1151         brcmnand_waitfunc(mtd, chip);
1152
1153         if (native_cmd == CMD_PARAMETER_READ ||
1154                         native_cmd == CMD_PARAMETER_CHANGE_COL) {
1155                 int i;
1156                 /*
1157                  * Must cache the FLASH_CACHE now, since changes in
1158                  * SECTOR_SIZE_1K may invalidate it
1159                  */
1160                 for (i = 0; i < FC_WORDS; i++)
1161                         ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
1162                 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1163                 if (host->hwcfg.sector_size_1k)
1164                         brcmnand_set_sector_size_1k(host,
1165                                                     host->hwcfg.sector_size_1k);
1166         }
1167
1168         /* Re-enable protection is necessary only after erase */
1169         if (command == NAND_CMD_ERASE1)
1170                 brcmnand_wp(mtd, 1);
1171 }
1172
1173 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1174 {
1175         struct nand_chip *chip = mtd->priv;
1176         struct brcmnand_host *host = chip->priv;
1177         struct brcmnand_controller *ctrl = host->ctrl;
1178         uint8_t ret = 0;
1179         int addr, offs;
1180
1181         switch (host->last_cmd) {
1182         case NAND_CMD_READID:
1183                 if (host->last_byte < 4)
1184                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1185                                 (24 - (host->last_byte << 3));
1186                 else if (host->last_byte < 8)
1187                         ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1188                                 (56 - (host->last_byte << 3));
1189                 break;
1190
1191         case NAND_CMD_READOOB:
1192                 ret = oob_reg_read(ctrl, host->last_byte);
1193                 break;
1194
1195         case NAND_CMD_STATUS:
1196                 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1197                                         INTFC_FLASH_STATUS;
1198                 if (wp_on) /* hide WP status */
1199                         ret |= NAND_STATUS_WP;
1200                 break;
1201
1202         case NAND_CMD_PARAM:
1203         case NAND_CMD_RNDOUT:
1204                 addr = host->last_addr + host->last_byte;
1205                 offs = addr & (FC_BYTES - 1);
1206
1207                 /* At FC_BYTES boundary, switch to next column */
1208                 if (host->last_byte > 0 && offs == 0)
1209                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1210
1211                 ret = ctrl->flash_cache[offs >> 2] >>
1212                                         (24 - ((offs & 0x03) << 3));
1213                 break;
1214         case NAND_CMD_GET_FEATURES:
1215                 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1216                         ret = 0;
1217                 } else {
1218                         bool last = host->last_byte ==
1219                                 ONFI_SUBFEATURE_PARAM_LEN - 1;
1220                         brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1221                         ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1222                 }
1223         }
1224
1225         dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1226         host->last_byte++;
1227
1228         return ret;
1229 }
1230
1231 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1232 {
1233         int i;
1234
1235         for (i = 0; i < len; i++, buf++)
1236                 *buf = brcmnand_read_byte(mtd);
1237 }
1238
1239 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1240                                    int len)
1241 {
1242         int i;
1243         struct nand_chip *chip = mtd->priv;
1244         struct brcmnand_host *host = chip->priv;
1245
1246         switch (host->last_cmd) {
1247         case NAND_CMD_SET_FEATURES:
1248                 for (i = 0; i < len; i++)
1249                         brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1250                                                   (i + 1) == len);
1251                 break;
1252         default:
1253                 BUG();
1254                 break;
1255         }
1256 }
1257
1258 /**
1259  * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1260  * following ahead of time:
1261  *  - Is this descriptor the beginning or end of a linked list?
1262  *  - What is the (DMA) address of the next descriptor in the linked list?
1263  */
1264 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1265                                   struct brcm_nand_dma_desc *desc, u64 addr,
1266                                   dma_addr_t buf, u32 len, u8 dma_cmd,
1267                                   bool begin, bool end,
1268                                   dma_addr_t next_desc)
1269 {
1270         memset(desc, 0, sizeof(*desc));
1271         /* Descriptors are written in native byte order (wordwise) */
1272         desc->next_desc = lower_32_bits(next_desc);
1273         desc->next_desc_ext = upper_32_bits(next_desc);
1274         desc->cmd_irq = (dma_cmd << 24) |
1275                 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1276                 (!!begin) | ((!!end) << 1); /* head, tail */
1277 #ifdef CONFIG_CPU_BIG_ENDIAN
1278         desc->cmd_irq |= 0x01 << 12;
1279 #endif
1280         desc->dram_addr = lower_32_bits(buf);
1281         desc->dram_addr_ext = upper_32_bits(buf);
1282         desc->tfr_len = len;
1283         desc->total_len = len;
1284         desc->flash_addr = lower_32_bits(addr);
1285         desc->flash_addr_ext = upper_32_bits(addr);
1286         desc->cs = host->cs;
1287         desc->status_valid = 0x01;
1288         return 0;
1289 }
1290
1291 /**
1292  * Kick the FLASH_DMA engine, with a given DMA descriptor
1293  */
1294 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1295 {
1296         struct brcmnand_controller *ctrl = host->ctrl;
1297         unsigned long timeo = msecs_to_jiffies(100);
1298
1299         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1300         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1301         flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1302         (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1303
1304         /* Start FLASH_DMA engine */
1305         ctrl->dma_pending = true;
1306         mb(); /* flush previous writes */
1307         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1308
1309         if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1310                 dev_err(ctrl->dev,
1311                                 "timeout waiting for DMA; status %#x, error status %#x\n",
1312                                 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1313                                 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1314         }
1315         ctrl->dma_pending = false;
1316         flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1317 }
1318
1319 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1320                               u32 len, u8 dma_cmd)
1321 {
1322         struct brcmnand_controller *ctrl = host->ctrl;
1323         dma_addr_t buf_pa;
1324         int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1325
1326         buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1327         if (dma_mapping_error(ctrl->dev, buf_pa)) {
1328                 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1329                 return -ENOMEM;
1330         }
1331
1332         brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1333                                    dma_cmd, true, true, 0);
1334
1335         brcmnand_dma_run(host, ctrl->dma_pa);
1336
1337         dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1338
1339         if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1340                 return -EBADMSG;
1341         else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1342                 return -EUCLEAN;
1343
1344         return 0;
1345 }
1346
1347 /*
1348  * Assumes proper CS is already set
1349  */
1350 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1351                                 u64 addr, unsigned int trans, u32 *buf,
1352                                 u8 *oob, u64 *err_addr)
1353 {
1354         struct brcmnand_host *host = chip->priv;
1355         struct brcmnand_controller *ctrl = host->ctrl;
1356         int i, j, ret = 0;
1357
1358         /* Clear error addresses */
1359         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1360         brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1361
1362         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1363                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1364         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1365
1366         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1367                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1368                                    lower_32_bits(addr));
1369                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1370                 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1371                 brcmnand_send_cmd(host, CMD_PAGE_READ);
1372                 brcmnand_waitfunc(mtd, chip);
1373
1374                 if (likely(buf))
1375                         for (j = 0; j < FC_WORDS; j++, buf++)
1376                                 *buf = brcmnand_read_fc(ctrl, j);
1377
1378                 if (oob)
1379                         oob += read_oob_from_regs(ctrl, i, oob,
1380                                         mtd->oobsize / trans,
1381                                         host->hwcfg.sector_size_1k);
1382
1383                 if (!ret) {
1384                         *err_addr = brcmnand_read_reg(ctrl,
1385                                         BRCMNAND_UNCORR_ADDR) |
1386                                 ((u64)(brcmnand_read_reg(ctrl,
1387                                                 BRCMNAND_UNCORR_EXT_ADDR)
1388                                         & 0xffff) << 32);
1389                         if (*err_addr)
1390                                 ret = -EBADMSG;
1391                 }
1392
1393                 if (!ret) {
1394                         *err_addr = brcmnand_read_reg(ctrl,
1395                                         BRCMNAND_CORR_ADDR) |
1396                                 ((u64)(brcmnand_read_reg(ctrl,
1397                                                 BRCMNAND_CORR_EXT_ADDR)
1398                                         & 0xffff) << 32);
1399                         if (*err_addr)
1400                                 ret = -EUCLEAN;
1401                 }
1402         }
1403
1404         return ret;
1405 }
1406
1407 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1408                          u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1409 {
1410         struct brcmnand_host *host = chip->priv;
1411         struct brcmnand_controller *ctrl = host->ctrl;
1412         u64 err_addr = 0;
1413         int err;
1414
1415         dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1416
1417         brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1418
1419         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1420                 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1421                                              CMD_PAGE_READ);
1422                 if (err) {
1423                         if (mtd_is_bitflip_or_eccerr(err))
1424                                 err_addr = addr;
1425                         else
1426                                 return -EIO;
1427                 }
1428         } else {
1429                 if (oob)
1430                         memset(oob, 0x99, mtd->oobsize);
1431
1432                 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1433                                                oob, &err_addr);
1434         }
1435
1436         if (mtd_is_eccerr(err)) {
1437                 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1438                         (unsigned long long)err_addr);
1439                 mtd->ecc_stats.failed++;
1440                 /* NAND layer expects zero on ECC errors */
1441                 return 0;
1442         }
1443
1444         if (mtd_is_bitflip(err)) {
1445                 unsigned int corrected = brcmnand_count_corrected(ctrl);
1446
1447                 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1448                         (unsigned long long)err_addr);
1449                 mtd->ecc_stats.corrected += corrected;
1450                 /* Always exceed the software-imposed threshold */
1451                 return max(mtd->bitflip_threshold, corrected);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1458                               uint8_t *buf, int oob_required, int page)
1459 {
1460         struct brcmnand_host *host = chip->priv;
1461         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1462
1463         return brcmnand_read(mtd, chip, host->last_addr,
1464                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1465 }
1466
1467 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1468                                   uint8_t *buf, int oob_required, int page)
1469 {
1470         struct brcmnand_host *host = chip->priv;
1471         u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1472         int ret;
1473
1474         brcmnand_set_ecc_enabled(host, 0);
1475         ret = brcmnand_read(mtd, chip, host->last_addr,
1476                         mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1477         brcmnand_set_ecc_enabled(host, 1);
1478         return ret;
1479 }
1480
1481 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1482                              int page)
1483 {
1484         return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1485                         mtd->writesize >> FC_SHIFT,
1486                         NULL, (u8 *)chip->oob_poi);
1487 }
1488
1489 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1490                                  int page)
1491 {
1492         struct brcmnand_host *host = chip->priv;
1493
1494         brcmnand_set_ecc_enabled(host, 0);
1495         brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1496                 mtd->writesize >> FC_SHIFT,
1497                 NULL, (u8 *)chip->oob_poi);
1498         brcmnand_set_ecc_enabled(host, 1);
1499         return 0;
1500 }
1501
1502 static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1503                                  uint32_t data_offs, uint32_t readlen,
1504                                  uint8_t *bufpoi, int page)
1505 {
1506         struct brcmnand_host *host = chip->priv;
1507
1508         return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1509                         readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1510 }
1511
1512 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1513                           u64 addr, const u32 *buf, u8 *oob)
1514 {
1515         struct brcmnand_host *host = chip->priv;
1516         struct brcmnand_controller *ctrl = host->ctrl;
1517         unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1518         int status, ret = 0;
1519
1520         dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1521
1522         if (unlikely((u32)buf & 0x03)) {
1523                 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1524                 buf = (u32 *)((u32)buf & ~0x03);
1525         }
1526
1527         brcmnand_wp(mtd, 0);
1528
1529         for (i = 0; i < ctrl->max_oob; i += 4)
1530                 oob_reg_write(ctrl, i, 0xffffffff);
1531
1532         if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1533                 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1534                                         mtd->writesize, CMD_PROGRAM_PAGE))
1535                         ret = -EIO;
1536                 goto out;
1537         }
1538
1539         brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1540                         (host->cs << 16) | ((addr >> 32) & 0xffff));
1541         (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1542
1543         for (i = 0; i < trans; i++, addr += FC_BYTES) {
1544                 /* full address MUST be set before populating FC */
1545                 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1546                                    lower_32_bits(addr));
1547                 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1548
1549                 if (buf)
1550                         for (j = 0; j < FC_WORDS; j++, buf++)
1551                                 brcmnand_write_fc(ctrl, j, *buf);
1552                 else if (oob)
1553                         for (j = 0; j < FC_WORDS; j++)
1554                                 brcmnand_write_fc(ctrl, j, 0xffffffff);
1555
1556                 if (oob) {
1557                         oob += write_oob_to_regs(ctrl, i, oob,
1558                                         mtd->oobsize / trans,
1559                                         host->hwcfg.sector_size_1k);
1560                 }
1561
1562                 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1563                 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1564                 status = brcmnand_waitfunc(mtd, chip);
1565
1566                 if (status & NAND_STATUS_FAIL) {
1567                         dev_info(ctrl->dev, "program failed at %llx\n",
1568                                 (unsigned long long)addr);
1569                         ret = -EIO;
1570                         goto out;
1571                 }
1572         }
1573 out:
1574         brcmnand_wp(mtd, 1);
1575         return ret;
1576 }
1577
1578 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1579                                const uint8_t *buf, int oob_required)
1580 {
1581         struct brcmnand_host *host = chip->priv;
1582         void *oob = oob_required ? chip->oob_poi : NULL;
1583
1584         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1585         return 0;
1586 }
1587
1588 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1589                                    struct nand_chip *chip, const uint8_t *buf,
1590                                    int oob_required)
1591 {
1592         struct brcmnand_host *host = chip->priv;
1593         void *oob = oob_required ? chip->oob_poi : NULL;
1594
1595         brcmnand_set_ecc_enabled(host, 0);
1596         brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1597         brcmnand_set_ecc_enabled(host, 1);
1598         return 0;
1599 }
1600
1601 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1602                                   int page)
1603 {
1604         return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1605                                   NULL, chip->oob_poi);
1606 }
1607
1608 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1609                                   int page)
1610 {
1611         struct brcmnand_host *host = chip->priv;
1612         int ret;
1613
1614         brcmnand_set_ecc_enabled(host, 0);
1615         ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1616                                  (u8 *)chip->oob_poi);
1617         brcmnand_set_ecc_enabled(host, 1);
1618
1619         return ret;
1620 }
1621
1622 /***********************************************************************
1623  * Per-CS setup (1 NAND device)
1624  ***********************************************************************/
1625
1626 static int brcmnand_set_cfg(struct brcmnand_host *host,
1627                             struct brcmnand_cfg *cfg)
1628 {
1629         struct brcmnand_controller *ctrl = host->ctrl;
1630         struct nand_chip *chip = &host->chip;
1631         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1632         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1633                         BRCMNAND_CS_CFG_EXT);
1634         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1635                         BRCMNAND_CS_ACC_CONTROL);
1636         u8 block_size = 0, page_size = 0, device_size = 0;
1637         u32 tmp;
1638
1639         if (ctrl->block_sizes) {
1640                 int i, found;
1641
1642                 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1643                         if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1644                                 block_size = i;
1645                                 found = 1;
1646                         }
1647                 if (!found) {
1648                         dev_warn(ctrl->dev, "invalid block size %u\n",
1649                                         cfg->block_size);
1650                         return -EINVAL;
1651                 }
1652         } else {
1653                 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1654         }
1655
1656         if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1657                                 cfg->block_size > ctrl->max_block_size)) {
1658                 dev_warn(ctrl->dev, "invalid block size %u\n",
1659                                 cfg->block_size);
1660                 block_size = 0;
1661         }
1662
1663         if (ctrl->page_sizes) {
1664                 int i, found;
1665
1666                 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1667                         if (ctrl->page_sizes[i] == cfg->page_size) {
1668                                 page_size = i;
1669                                 found = 1;
1670                         }
1671                 if (!found) {
1672                         dev_warn(ctrl->dev, "invalid page size %u\n",
1673                                         cfg->page_size);
1674                         return -EINVAL;
1675                 }
1676         } else {
1677                 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1678         }
1679
1680         if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1681                                 cfg->page_size > ctrl->max_page_size)) {
1682                 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1683                 return -EINVAL;
1684         }
1685
1686         if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1687                 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1688                         (unsigned long long)cfg->device_size);
1689                 return -EINVAL;
1690         }
1691         device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1692
1693         tmp = (cfg->blk_adr_bytes << 8) |
1694                 (cfg->col_adr_bytes << 12) |
1695                 (cfg->ful_adr_bytes << 16) |
1696                 (!!(cfg->device_width == 16) << 23) |
1697                 (device_size << 24);
1698         if (cfg_offs == cfg_ext_offs) {
1699                 tmp |= (page_size << 20) | (block_size << 28);
1700                 nand_writereg(ctrl, cfg_offs, tmp);
1701         } else {
1702                 nand_writereg(ctrl, cfg_offs, tmp);
1703                 tmp = page_size | (block_size << 4);
1704                 nand_writereg(ctrl, cfg_ext_offs, tmp);
1705         }
1706
1707         tmp = nand_readreg(ctrl, acc_control_offs);
1708         tmp &= ~brcmnand_ecc_level_mask(ctrl);
1709         tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1710         tmp &= ~brcmnand_spare_area_mask(ctrl);
1711         tmp |= cfg->spare_area_size;
1712         nand_writereg(ctrl, acc_control_offs, tmp);
1713
1714         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1715
1716         /* threshold = ceil(BCH-level * 0.75) */
1717         brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1718
1719         return 0;
1720 }
1721
1722 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1723 {
1724         buf += sprintf(buf,
1725                 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1726                 (unsigned long long)cfg->device_size >> 20,
1727                 cfg->block_size >> 10,
1728                 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1729                 cfg->page_size >= 1024 ? "KiB" : "B",
1730                 cfg->spare_area_size, cfg->device_width);
1731
1732         /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1733         if (is_hamming_ecc(cfg))
1734                 sprintf(buf, ", Hamming ECC");
1735         else if (cfg->sector_size_1k)
1736                 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1737         else
1738                 sprintf(buf, ", BCH-%u\n", cfg->ecc_level);
1739 }
1740
1741 /*
1742  * Minimum number of bytes to address a page. Calculated as:
1743  *     roundup(log2(size / page-size) / 8)
1744  *
1745  * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1746  *     OK because many other things will break if 'size' is irregular...
1747  */
1748 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1749 {
1750         return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1751 }
1752
1753 static int brcmnand_setup_dev(struct brcmnand_host *host)
1754 {
1755         struct mtd_info *mtd = &host->mtd;
1756         struct nand_chip *chip = &host->chip;
1757         struct brcmnand_controller *ctrl = host->ctrl;
1758         struct brcmnand_cfg *cfg = &host->hwcfg;
1759         char msg[128];
1760         u32 offs, tmp, oob_sector;
1761         int ret;
1762
1763         memset(cfg, 0, sizeof(*cfg));
1764
1765         ret = of_property_read_u32(chip->dn, "brcm,nand-oob-sector-size",
1766                                    &oob_sector);
1767         if (ret) {
1768                 /* Use detected size */
1769                 cfg->spare_area_size = mtd->oobsize /
1770                                         (mtd->writesize >> FC_SHIFT);
1771         } else {
1772                 cfg->spare_area_size = oob_sector;
1773         }
1774         if (cfg->spare_area_size > ctrl->max_oob)
1775                 cfg->spare_area_size = ctrl->max_oob;
1776         /*
1777          * Set oobsize to be consistent with controller's spare_area_size, as
1778          * the rest is inaccessible.
1779          */
1780         mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1781
1782         cfg->device_size = mtd->size;
1783         cfg->block_size = mtd->erasesize;
1784         cfg->page_size = mtd->writesize;
1785         cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1786         cfg->col_adr_bytes = 2;
1787         cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1788
1789         switch (chip->ecc.size) {
1790         case 512:
1791                 if (chip->ecc.strength == 1) /* Hamming */
1792                         cfg->ecc_level = 15;
1793                 else
1794                         cfg->ecc_level = chip->ecc.strength;
1795                 cfg->sector_size_1k = 0;
1796                 break;
1797         case 1024:
1798                 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1799                         dev_err(ctrl->dev, "1KB sectors not supported\n");
1800                         return -EINVAL;
1801                 }
1802                 if (chip->ecc.strength & 0x1) {
1803                         dev_err(ctrl->dev,
1804                                 "odd ECC not supported with 1KB sectors\n");
1805                         return -EINVAL;
1806                 }
1807
1808                 cfg->ecc_level = chip->ecc.strength >> 1;
1809                 cfg->sector_size_1k = 1;
1810                 break;
1811         default:
1812                 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1813                         chip->ecc.size);
1814                 return -EINVAL;
1815         }
1816
1817         cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1818         if (mtd->writesize > 512)
1819                 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1820         else
1821                 cfg->ful_adr_bytes += 1;
1822
1823         ret = brcmnand_set_cfg(host, cfg);
1824         if (ret)
1825                 return ret;
1826
1827         brcmnand_set_ecc_enabled(host, 1);
1828
1829         brcmnand_print_cfg(msg, cfg);
1830         dev_info(ctrl->dev, "detected %s\n", msg);
1831
1832         /* Configure ACC_CONTROL */
1833         offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1834         tmp = nand_readreg(ctrl, offs);
1835         tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1836         tmp &= ~ACC_CONTROL_RD_ERASED;
1837         tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1838         if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1839                 /*
1840                  * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1841                  * errors
1842                  */
1843                 if (has_flash_dma(ctrl))
1844                         tmp &= ~ACC_CONTROL_PREFETCH;
1845                 else
1846                         tmp |= ACC_CONTROL_PREFETCH;
1847         }
1848         nand_writereg(ctrl, offs, tmp);
1849
1850         return 0;
1851 }
1852
1853 static int brcmnand_init_cs(struct brcmnand_host *host)
1854 {
1855         struct brcmnand_controller *ctrl = host->ctrl;
1856         struct device_node *dn = host->of_node;
1857         struct platform_device *pdev = host->pdev;
1858         struct mtd_info *mtd;
1859         struct nand_chip *chip;
1860         int ret = 0;
1861         struct mtd_part_parser_data ppdata = { .of_node = dn };
1862
1863         ret = of_property_read_u32(dn, "reg", &host->cs);
1864         if (ret) {
1865                 dev_err(&pdev->dev, "can't get chip-select\n");
1866                 return -ENXIO;
1867         }
1868
1869         mtd = &host->mtd;
1870         chip = &host->chip;
1871
1872         chip->dn = dn;
1873         chip->priv = host;
1874         mtd->priv = chip;
1875         mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1876                                    host->cs);
1877         mtd->owner = THIS_MODULE;
1878         mtd->dev.parent = &pdev->dev;
1879
1880         chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1881         chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1882
1883         chip->cmd_ctrl = brcmnand_cmd_ctrl;
1884         chip->cmdfunc = brcmnand_cmdfunc;
1885         chip->waitfunc = brcmnand_waitfunc;
1886         chip->read_byte = brcmnand_read_byte;
1887         chip->read_buf = brcmnand_read_buf;
1888         chip->write_buf = brcmnand_write_buf;
1889
1890         chip->ecc.mode = NAND_ECC_HW;
1891         chip->ecc.read_page = brcmnand_read_page;
1892         chip->ecc.read_subpage = brcmnand_read_subpage;
1893         chip->ecc.write_page = brcmnand_write_page;
1894         chip->ecc.read_page_raw = brcmnand_read_page_raw;
1895         chip->ecc.write_page_raw = brcmnand_write_page_raw;
1896         chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1897         chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1898         chip->ecc.read_oob = brcmnand_read_oob;
1899         chip->ecc.write_oob = brcmnand_write_oob;
1900
1901         chip->controller = &ctrl->controller;
1902
1903         if (nand_scan_ident(mtd, 1, NULL))
1904                 return -ENXIO;
1905
1906         chip->options |= NAND_NO_SUBPAGE_WRITE;
1907         /*
1908          * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
1909          * to/from, and have nand_base pass us a bounce buffer instead, as
1910          * needed.
1911          */
1912         chip->options |= NAND_USE_BOUNCE_BUFFER;
1913
1914         if (of_get_nand_on_flash_bbt(dn))
1915                 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1916
1917         if (brcmnand_setup_dev(host))
1918                 return -ENXIO;
1919
1920         chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
1921         /* only use our internal HW threshold */
1922         mtd->bitflip_threshold = 1;
1923
1924         chip->ecc.layout = brcmstb_choose_ecc_layout(host);
1925         if (!chip->ecc.layout)
1926                 return -ENXIO;
1927
1928         if (nand_scan_tail(mtd))
1929                 return -ENXIO;
1930
1931         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1932 }
1933
1934 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
1935                                             int restore)
1936 {
1937         struct brcmnand_controller *ctrl = host->ctrl;
1938         u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1939         u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1940                         BRCMNAND_CS_CFG_EXT);
1941         u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1942                         BRCMNAND_CS_ACC_CONTROL);
1943         u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
1944         u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
1945
1946         if (restore) {
1947                 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
1948                 if (cfg_offs != cfg_ext_offs)
1949                         nand_writereg(ctrl, cfg_ext_offs,
1950                                       host->hwcfg.config_ext);
1951                 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
1952                 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
1953                 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
1954         } else {
1955                 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
1956                 if (cfg_offs != cfg_ext_offs)
1957                         host->hwcfg.config_ext =
1958                                 nand_readreg(ctrl, cfg_ext_offs);
1959                 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
1960                 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
1961                 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
1962         }
1963 }
1964
1965 static int brcmnand_suspend(struct device *dev)
1966 {
1967         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
1968         struct brcmnand_host *host;
1969
1970         list_for_each_entry(host, &ctrl->host_list, node)
1971                 brcmnand_save_restore_cs_config(host, 0);
1972
1973         ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
1974         ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
1975         ctrl->corr_stat_threshold =
1976                 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
1977
1978         if (has_flash_dma(ctrl))
1979                 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
1980
1981         return 0;
1982 }
1983
1984 static int brcmnand_resume(struct device *dev)
1985 {
1986         struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
1987         struct brcmnand_host *host;
1988
1989         if (has_flash_dma(ctrl)) {
1990                 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
1991                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
1992         }
1993
1994         brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
1995         brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
1996         brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
1997                         ctrl->corr_stat_threshold);
1998
1999         list_for_each_entry(host, &ctrl->host_list, node) {
2000                 struct mtd_info *mtd = &host->mtd;
2001                 struct nand_chip *chip = mtd->priv;
2002
2003                 brcmnand_save_restore_cs_config(host, 1);
2004
2005                 /* Reset the chip, required by some chips after power-up */
2006                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2007         }
2008
2009         return 0;
2010 }
2011
2012 const struct dev_pm_ops brcmnand_pm_ops = {
2013         .suspend                = brcmnand_suspend,
2014         .resume                 = brcmnand_resume,
2015 };
2016 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2017
2018 static const struct of_device_id brcmnand_of_match[] = {
2019         { .compatible = "brcm,brcmnand-v4.0" },
2020         { .compatible = "brcm,brcmnand-v5.0" },
2021         { .compatible = "brcm,brcmnand-v6.0" },
2022         { .compatible = "brcm,brcmnand-v6.1" },
2023         { .compatible = "brcm,brcmnand-v7.0" },
2024         { .compatible = "brcm,brcmnand-v7.1" },
2025         {},
2026 };
2027 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2028
2029 /***********************************************************************
2030  * Platform driver setup (per controller)
2031  ***********************************************************************/
2032
2033 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2034 {
2035         struct device *dev = &pdev->dev;
2036         struct device_node *dn = dev->of_node, *child;
2037         static struct brcmnand_controller *ctrl;
2038         struct resource *res;
2039         int ret;
2040
2041         /* We only support device-tree instantiation */
2042         if (!dn)
2043                 return -ENODEV;
2044
2045         if (!of_match_node(brcmnand_of_match, dn))
2046                 return -ENODEV;
2047
2048         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2049         if (!ctrl)
2050                 return -ENOMEM;
2051
2052         dev_set_drvdata(dev, ctrl);
2053         ctrl->dev = dev;
2054
2055         init_completion(&ctrl->done);
2056         init_completion(&ctrl->dma_done);
2057         spin_lock_init(&ctrl->controller.lock);
2058         init_waitqueue_head(&ctrl->controller.wq);
2059         INIT_LIST_HEAD(&ctrl->host_list);
2060
2061         /* NAND register range */
2062         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2063         ctrl->nand_base = devm_ioremap_resource(dev, res);
2064         if (IS_ERR(ctrl->nand_base))
2065                 return PTR_ERR(ctrl->nand_base);
2066
2067         /* Initialize NAND revision */
2068         ret = brcmnand_revision_init(ctrl);
2069         if (ret)
2070                 return ret;
2071
2072         /*
2073          * Most chips have this cache at a fixed offset within 'nand' block.
2074          * Some must specify this region separately.
2075          */
2076         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2077         if (res) {
2078                 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2079                 if (IS_ERR(ctrl->nand_fc))
2080                         return PTR_ERR(ctrl->nand_fc);
2081         } else {
2082                 ctrl->nand_fc = ctrl->nand_base +
2083                                 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2084         }
2085
2086         /* FLASH_DMA */
2087         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2088         if (res) {
2089                 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2090                 if (IS_ERR(ctrl->flash_dma_base))
2091                         return PTR_ERR(ctrl->flash_dma_base);
2092
2093                 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2094                 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2095
2096                 /* Allocate descriptor(s) */
2097                 ctrl->dma_desc = dmam_alloc_coherent(dev,
2098                                                      sizeof(*ctrl->dma_desc),
2099                                                      &ctrl->dma_pa, GFP_KERNEL);
2100                 if (!ctrl->dma_desc)
2101                         return -ENOMEM;
2102
2103                 ctrl->dma_irq = platform_get_irq(pdev, 1);
2104                 if ((int)ctrl->dma_irq < 0) {
2105                         dev_err(dev, "missing FLASH_DMA IRQ\n");
2106                         return -ENODEV;
2107                 }
2108
2109                 ret = devm_request_irq(dev, ctrl->dma_irq,
2110                                 brcmnand_dma_irq, 0, DRV_NAME,
2111                                 ctrl);
2112                 if (ret < 0) {
2113                         dev_err(dev, "can't allocate IRQ %d: error %d\n",
2114                                         ctrl->dma_irq, ret);
2115                         return ret;
2116                 }
2117
2118                 dev_info(dev, "enabling FLASH_DMA\n");
2119         }
2120
2121         /* Disable automatic device ID config, direct addressing */
2122         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2123                          CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2124         /* Disable XOR addressing */
2125         brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2126
2127         if (ctrl->features & BRCMNAND_HAS_WP) {
2128                 /* Permanently disable write protection */
2129                 if (wp_on == 2)
2130                         brcmnand_set_wp(ctrl, false);
2131         } else {
2132                 wp_on = 0;
2133         }
2134
2135         /* IRQ */
2136         ctrl->irq = platform_get_irq(pdev, 0);
2137         if ((int)ctrl->irq < 0) {
2138                 dev_err(dev, "no IRQ defined\n");
2139                 return -ENODEV;
2140         }
2141
2142         ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2143                         DRV_NAME, ctrl);
2144         if (ret < 0) {
2145                 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2146                         ctrl->irq, ret);
2147                 return ret;
2148         }
2149
2150         for_each_available_child_of_node(dn, child) {
2151                 if (of_device_is_compatible(child, "brcm,nandcs")) {
2152                         struct brcmnand_host *host;
2153
2154                         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2155                         if (!host)
2156                                 return -ENOMEM;
2157                         host->pdev = pdev;
2158                         host->ctrl = ctrl;
2159                         host->of_node = child;
2160
2161                         ret = brcmnand_init_cs(host);
2162                         if (ret)
2163                                 continue; /* Try all chip-selects */
2164
2165                         list_add_tail(&host->node, &ctrl->host_list);
2166                 }
2167         }
2168
2169         /* No chip-selects could initialize properly */
2170         if (list_empty(&ctrl->host_list))
2171                 return -ENODEV;
2172
2173         return 0;
2174 }
2175 EXPORT_SYMBOL_GPL(brcmnand_probe);
2176
2177 int brcmnand_remove(struct platform_device *pdev)
2178 {
2179         struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2180         struct brcmnand_host *host;
2181
2182         list_for_each_entry(host, &ctrl->host_list, node)
2183                 nand_release(&host->mtd);
2184
2185         dev_set_drvdata(&pdev->dev, NULL);
2186
2187         return 0;
2188 }
2189 EXPORT_SYMBOL_GPL(brcmnand_remove);
2190
2191 MODULE_LICENSE("GPL v2");
2192 MODULE_AUTHOR("Kevin Cernekee");
2193 MODULE_AUTHOR("Brian Norris");
2194 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2195 MODULE_ALIAS("platform:brcmnand");