2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/err.h>
30 #include <linux/clk.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/slab.h>
35 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
39 #include <linux/platform_data/mtd-davinci.h>
40 #include <linux/platform_data/mtd-davinci-aemif.h>
43 * This is a device driver for the NAND flash controller found on the
44 * various DaVinci family chips. It handles up to four SoC chipselects,
45 * and some flavors of secondary chipselect (e.g. based on A12) as used
46 * with multichip packages.
48 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
49 * available on chips like the DM355 and OMAP-L137 and needed with the
50 * more error-prone MLC NAND chips.
52 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
53 * outputs in a "wire-AND" configuration, with no per-chip signals.
55 struct davinci_nand_info {
57 struct nand_chip chip;
58 struct nand_ecclayout ecclayout;
71 uint32_t mask_chipsel;
75 uint32_t core_chipsel;
77 struct davinci_aemif_timing *timing;
80 static DEFINE_SPINLOCK(davinci_nand_lock);
81 static bool ecc4_busy;
83 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
86 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
89 return __raw_readl(info->base + offset);
92 static inline void davinci_nand_writel(struct davinci_nand_info *info,
93 int offset, unsigned long value)
95 __raw_writel(value, info->base + offset);
98 /*----------------------------------------------------------------------*/
101 * Access to hardware control lines: ALE, CLE, secondary chipselect.
104 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
107 struct davinci_nand_info *info = to_davinci_nand(mtd);
108 uint32_t addr = info->current_cs;
109 struct nand_chip *nand = mtd->priv;
111 /* Did the control lines change? */
112 if (ctrl & NAND_CTRL_CHANGE) {
113 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
114 addr |= info->mask_cle;
115 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
116 addr |= info->mask_ale;
118 nand->IO_ADDR_W = (void __iomem __force *)addr;
121 if (cmd != NAND_CMD_NONE)
122 iowrite8(cmd, nand->IO_ADDR_W);
125 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
127 struct davinci_nand_info *info = to_davinci_nand(mtd);
128 uint32_t addr = info->ioaddr;
130 /* maybe kick in a second chipselect */
132 addr |= info->mask_chipsel;
133 info->current_cs = addr;
135 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
136 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
139 /*----------------------------------------------------------------------*/
142 * 1-bit hardware ECC ... context maintained for each core chipselect
145 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
147 struct davinci_nand_info *info = to_davinci_nand(mtd);
149 return davinci_nand_readl(info, NANDF1ECC_OFFSET
150 + 4 * info->core_chipsel);
153 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
155 struct davinci_nand_info *info;
159 info = to_davinci_nand(mtd);
161 /* Reset ECC hardware */
162 nand_davinci_readecc_1bit(mtd);
164 spin_lock_irqsave(&davinci_nand_lock, flags);
166 /* Restart ECC hardware */
167 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
168 nandcfr |= BIT(8 + info->core_chipsel);
169 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
171 spin_unlock_irqrestore(&davinci_nand_lock, flags);
175 * Read hardware ECC value and pack into three bytes
177 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
178 const u_char *dat, u_char *ecc_code)
180 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
181 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
183 /* invert so that erased block ecc is correct */
185 ecc_code[0] = (u_char)(ecc24);
186 ecc_code[1] = (u_char)(ecc24 >> 8);
187 ecc_code[2] = (u_char)(ecc24 >> 16);
192 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
193 u_char *read_ecc, u_char *calc_ecc)
195 struct nand_chip *chip = mtd->priv;
196 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
198 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
200 uint32_t diff = eccCalc ^ eccNand;
203 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
204 /* Correctable error */
205 if ((diff >> (12 + 3)) < chip->ecc.size) {
206 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
211 } else if (!(diff & (diff - 1))) {
212 /* Single bit ECC error in the ECC itself,
216 /* Uncorrectable error */
224 /*----------------------------------------------------------------------*/
227 * 4-bit hardware ECC ... context maintained over entire AEMIF
229 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
230 * since that forces use of a problematic "infix OOB" layout.
231 * Among other things, it trashes manufacturer bad block markers.
232 * Also, and specific to this hardware, it ECC-protects the "prepad"
233 * in the OOB ... while having ECC protection for parts of OOB would
234 * seem useful, the current MTD stack sometimes wants to update the
235 * OOB without recomputing ECC.
238 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
240 struct davinci_nand_info *info = to_davinci_nand(mtd);
244 /* Reset ECC hardware */
245 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
247 spin_lock_irqsave(&davinci_nand_lock, flags);
249 /* Start 4-bit ECC calculation for read/write */
250 val = davinci_nand_readl(info, NANDFCR_OFFSET);
252 val |= (info->core_chipsel << 4) | BIT(12);
253 davinci_nand_writel(info, NANDFCR_OFFSET, val);
255 info->is_readmode = (mode == NAND_ECC_READ);
257 spin_unlock_irqrestore(&davinci_nand_lock, flags);
260 /* Read raw ECC code after writing to NAND. */
262 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
264 const u32 mask = 0x03ff03ff;
266 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
267 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
268 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
269 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
272 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
273 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
274 const u_char *dat, u_char *ecc_code)
276 struct davinci_nand_info *info = to_davinci_nand(mtd);
280 /* After a read, terminate ECC calculation by a dummy read
281 * of some 4-bit ECC register. ECC covers everything that
282 * was read; correct() just uses the hardware state, so
283 * ecc_code is not needed.
285 if (info->is_readmode) {
286 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
290 /* Pack eight raw 10-bit ecc values into ten bytes, making
291 * two passes which each convert four values (in upper and
292 * lower halves of two 32-bit words) into five bytes. The
293 * ROM boot loader uses this same packing scheme.
295 nand_davinci_readecc_4bit(info, raw_ecc);
296 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
297 *ecc_code++ = p[0] & 0xff;
298 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
299 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
300 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
301 *ecc_code++ = (p[1] >> 18) & 0xff;
307 /* Correct up to 4 bits in data we just read, using state left in the
308 * hardware plus the ecc_code computed when it was first written.
310 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
311 u_char *data, u_char *ecc_code, u_char *null)
314 struct davinci_nand_info *info = to_davinci_nand(mtd);
315 unsigned short ecc10[8];
316 unsigned short *ecc16;
319 unsigned num_errors, corrected;
322 /* All bytes 0xff? It's an erased page; ignore its ECC. */
323 for (i = 0; i < 10; i++) {
324 if (ecc_code[i] != 0xff)
330 /* Unpack ten bytes into eight 10 bit values. We know we're
331 * little-endian, and use type punning for less shifting/masking.
333 if (WARN_ON(0x01 & (unsigned) ecc_code))
335 ecc16 = (unsigned short *)ecc_code;
337 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
338 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
339 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
340 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
341 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
342 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
343 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
344 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
346 /* Tell ECC controller about the expected ECC codes. */
347 for (i = 7; i >= 0; i--)
348 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
350 /* Allow time for syndrome calculation ... then read it.
351 * A syndrome of all zeroes 0 means no detected errors.
353 davinci_nand_readl(info, NANDFSR_OFFSET);
354 nand_davinci_readecc_4bit(info, syndrome);
355 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
359 * Clear any previous address calculation by doing a dummy read of an
360 * error address register.
362 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
364 /* Start address calculation, and wait for it to complete.
365 * We _could_ start reading more data while this is working,
366 * to speed up the overall page read.
368 davinci_nand_writel(info, NANDFCR_OFFSET,
369 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
372 * ECC_STATE field reads 0x3 (Error correction complete) immediately
373 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
374 * begin trying to poll for the state, you may fall right out of your
375 * loop without any of the correction calculations having taken place.
376 * The recommendation from the hardware team is to initially delay as
377 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
380 timeo = jiffies + usecs_to_jiffies(100);
382 ecc_state = (davinci_nand_readl(info,
383 NANDFSR_OFFSET) >> 8) & 0x0f;
385 } while ((ecc_state < 4) && time_before(jiffies, timeo));
388 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
390 switch ((fsr >> 8) & 0x0f) {
391 case 0: /* no error, should not happen */
392 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
394 case 1: /* five or more errors detected */
395 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
397 case 2: /* error addresses computed */
399 num_errors = 1 + ((fsr >> 16) & 0x03);
401 default: /* still working on it */
408 /* correct each error */
409 for (i = 0, corrected = 0; i < num_errors; i++) {
410 int error_address, error_value;
413 error_address = davinci_nand_readl(info,
414 NAND_ERR_ADD2_OFFSET);
415 error_value = davinci_nand_readl(info,
416 NAND_ERR_ERRVAL2_OFFSET);
418 error_address = davinci_nand_readl(info,
419 NAND_ERR_ADD1_OFFSET);
420 error_value = davinci_nand_readl(info,
421 NAND_ERR_ERRVAL1_OFFSET);
425 error_address >>= 16;
428 error_address &= 0x3ff;
429 error_address = (512 + 7) - error_address;
431 if (error_address < 512) {
432 data[error_address] ^= error_value;
440 /*----------------------------------------------------------------------*/
443 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
444 * how these chips are normally wired. This translates to both 8 and 16
445 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
447 * For now we assume that configuration, or any other one which ignores
448 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
449 * and have that transparently morphed into multiple NAND operations.
451 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
453 struct nand_chip *chip = mtd->priv;
455 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
456 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
457 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
458 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
460 ioread8_rep(chip->IO_ADDR_R, buf, len);
463 static void nand_davinci_write_buf(struct mtd_info *mtd,
464 const uint8_t *buf, int len)
466 struct nand_chip *chip = mtd->priv;
468 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
469 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
470 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
471 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
473 iowrite8_rep(chip->IO_ADDR_R, buf, len);
477 * Check hardware register for wait status. Returns 1 if device is ready,
478 * 0 if it is still busy.
480 static int nand_davinci_dev_ready(struct mtd_info *mtd)
482 struct davinci_nand_info *info = to_davinci_nand(mtd);
484 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
487 /*----------------------------------------------------------------------*/
489 /* An ECC layout for using 4-bit ECC with small-page flash, storing
490 * ten ECC bytes plus the manufacturer's bad block marker byte, and
491 * and not overlapping the default BBT markers.
493 static struct nand_ecclayout hwecc4_small = {
495 .eccpos = { 0, 1, 2, 3, 4,
496 /* offset 5 holds the badblock marker */
500 {.offset = 8, .length = 5, },
505 /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
506 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
507 * and not overlapping the default BBT markers.
509 static struct nand_ecclayout hwecc4_2048 = {
512 /* at the end of spare sector */
513 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
514 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
515 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
516 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
519 /* 2 bytes at offset 0 hold manufacturer badblock markers */
520 {.offset = 2, .length = 22, },
521 /* 5 bytes at offset 8 hold BBT markers */
522 /* 8 bytes at offset 16 hold JFFS2 clean markers */
527 * An ECC layout for using 4-bit ECC with large-page (4096bytes) flash,
528 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
529 * and not overlapping the default BBT markers.
531 static struct nand_ecclayout hwecc4_4096 = {
534 /* at the end of spare sector */
535 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
536 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
537 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
538 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
539 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
540 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
541 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
542 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
545 /* 2 bytes at offset 0 hold manufacturer badblock markers */
546 {.offset = 2, .length = 46, },
547 /* 5 bytes at offset 8 hold BBT markers */
548 /* 8 bytes at offset 16 hold JFFS2 clean markers */
552 #if defined(CONFIG_OF)
553 static const struct of_device_id davinci_nand_of_match[] = {
554 {.compatible = "ti,davinci-nand", },
555 {.compatible = "ti,keystone-nand", },
558 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
560 static struct davinci_nand_pdata
561 *nand_davinci_get_pdata(struct platform_device *pdev)
563 if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
564 struct davinci_nand_pdata *pdata;
568 pdata = devm_kzalloc(&pdev->dev,
569 sizeof(struct davinci_nand_pdata),
571 pdev->dev.platform_data = pdata;
573 return ERR_PTR(-ENOMEM);
574 if (!of_property_read_u32(pdev->dev.of_node,
575 "ti,davinci-chipselect", &prop))
578 return ERR_PTR(-EINVAL);
580 if (!of_property_read_u32(pdev->dev.of_node,
581 "ti,davinci-mask-ale", &prop))
582 pdata->mask_ale = prop;
583 if (!of_property_read_u32(pdev->dev.of_node,
584 "ti,davinci-mask-cle", &prop))
585 pdata->mask_cle = prop;
586 if (!of_property_read_u32(pdev->dev.of_node,
587 "ti,davinci-mask-chipsel", &prop))
588 pdata->mask_chipsel = prop;
589 if (!of_property_read_string(pdev->dev.of_node,
590 "nand-ecc-mode", &mode) ||
591 !of_property_read_string(pdev->dev.of_node,
592 "ti,davinci-ecc-mode", &mode)) {
593 if (!strncmp("none", mode, 4))
594 pdata->ecc_mode = NAND_ECC_NONE;
595 if (!strncmp("soft", mode, 4))
596 pdata->ecc_mode = NAND_ECC_SOFT;
597 if (!strncmp("hw", mode, 2))
598 pdata->ecc_mode = NAND_ECC_HW;
600 if (!of_property_read_u32(pdev->dev.of_node,
601 "ti,davinci-ecc-bits", &prop))
602 pdata->ecc_bits = prop;
604 prop = of_get_nand_bus_width(pdev->dev.of_node);
605 if (0 < prop || !of_property_read_u32(pdev->dev.of_node,
606 "ti,davinci-nand-buswidth", &prop))
608 pdata->options |= NAND_BUSWIDTH_16;
609 if (of_property_read_bool(pdev->dev.of_node,
610 "nand-on-flash-bbt") ||
611 of_property_read_bool(pdev->dev.of_node,
612 "ti,davinci-nand-use-bbt"))
613 pdata->bbt_options = NAND_BBT_USE_FLASH;
615 if (of_device_is_compatible(pdev->dev.of_node,
616 "ti,keystone-nand")) {
617 pdata->options |= NAND_NO_SUBPAGE_WRITE;
621 return dev_get_platdata(&pdev->dev);
624 static struct davinci_nand_pdata
625 *nand_davinci_get_pdata(struct platform_device *pdev)
627 return dev_get_platdata(&pdev->dev);
631 static int nand_davinci_probe(struct platform_device *pdev)
633 struct davinci_nand_pdata *pdata;
634 struct davinci_nand_info *info;
635 struct resource *res1;
636 struct resource *res2;
641 nand_ecc_modes_t ecc_mode;
643 pdata = nand_davinci_get_pdata(pdev);
645 return PTR_ERR(pdata);
647 /* insist on board-specific configuration */
651 /* which external chipselect will we be managing? */
652 if (pdev->id < 0 || pdev->id > 3)
655 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
659 platform_set_drvdata(pdev, info);
661 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
663 if (!res1 || !res2) {
664 dev_err(&pdev->dev, "resource missing\n");
668 vaddr = devm_ioremap_resource(&pdev->dev, res1);
670 return PTR_ERR(vaddr);
673 * This registers range is used to setup NAND settings. In case with
674 * TI AEMIF driver, the same memory address range is requested already
675 * by AEMIF, so we cannot request it twice, just ioremap.
676 * The AEMIF and NAND drivers not use the same registers in this range.
678 base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
680 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
681 return -EADDRNOTAVAIL;
684 info->dev = &pdev->dev;
688 info->mtd.priv = &info->chip;
689 info->mtd.dev.parent = &pdev->dev;
691 info->chip.IO_ADDR_R = vaddr;
692 info->chip.IO_ADDR_W = vaddr;
693 info->chip.chip_delay = 0;
694 info->chip.select_chip = nand_davinci_select_chip;
696 /* options such as NAND_BBT_USE_FLASH */
697 info->chip.bbt_options = pdata->bbt_options;
698 /* options such as 16-bit widths */
699 info->chip.options = pdata->options;
700 info->chip.bbt_td = pdata->bbt_td;
701 info->chip.bbt_md = pdata->bbt_md;
702 info->timing = pdata->timing;
704 info->ioaddr = (uint32_t __force) vaddr;
706 info->current_cs = info->ioaddr;
707 info->core_chipsel = pdev->id;
708 info->mask_chipsel = pdata->mask_chipsel;
710 /* use nandboot-capable ALE/CLE masks by default */
711 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
712 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
714 /* Set address of hardware control function */
715 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
716 info->chip.dev_ready = nand_davinci_dev_ready;
718 /* Speed up buffer I/O */
719 info->chip.read_buf = nand_davinci_read_buf;
720 info->chip.write_buf = nand_davinci_write_buf;
722 /* Use board-specific ECC config */
723 ecc_mode = pdata->ecc_mode;
732 if (pdata->ecc_bits == 4) {
733 /* No sanity checks: CPUs must support this,
734 * and the chips may not use NAND_BUSWIDTH_16.
737 /* No sharing 4-bit hardware between chipselects yet */
738 spin_lock_irq(&davinci_nand_lock);
743 spin_unlock_irq(&davinci_nand_lock);
748 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
749 info->chip.ecc.correct = nand_davinci_correct_4bit;
750 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
751 info->chip.ecc.bytes = 10;
753 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
754 info->chip.ecc.correct = nand_davinci_correct_1bit;
755 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
756 info->chip.ecc.bytes = 3;
758 info->chip.ecc.size = 512;
759 info->chip.ecc.strength = pdata->ecc_bits;
764 info->chip.ecc.mode = ecc_mode;
766 info->clk = devm_clk_get(&pdev->dev, "aemif");
767 if (IS_ERR(info->clk)) {
768 ret = PTR_ERR(info->clk);
769 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
773 ret = clk_prepare_enable(info->clk);
775 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
780 spin_lock_irq(&davinci_nand_lock);
782 /* put CSxNAND into NAND mode */
783 val = davinci_nand_readl(info, NANDFCR_OFFSET);
784 val |= BIT(info->core_chipsel);
785 davinci_nand_writel(info, NANDFCR_OFFSET, val);
787 spin_unlock_irq(&davinci_nand_lock);
789 /* Scan to find existence of the device(s) */
790 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
792 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
796 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
797 * is OK, but it allocates 6 bytes when only 3 are needed (for
798 * each 512 bytes). For the 4-bit HW ECC, that default is not
799 * usable: 10 bytes are needed, not 6.
801 if (pdata->ecc_bits == 4) {
802 int chunks = info->mtd.writesize / 512;
804 if (!chunks || info->mtd.oobsize < 16) {
805 dev_dbg(&pdev->dev, "too small\n");
810 /* For small page chips, preserve the manufacturer's
811 * badblock marking data ... and make sure a flash BBT
812 * table marker fits in the free bytes.
815 info->ecclayout = hwecc4_small;
816 info->ecclayout.oobfree[1].length =
817 info->mtd.oobsize - 16;
821 info->ecclayout = hwecc4_2048;
822 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
826 info->ecclayout = hwecc4_4096;
827 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
835 info->chip.ecc.layout = &info->ecclayout;
838 ret = nand_scan_tail(&info->mtd);
843 ret = mtd_device_parse_register(&info->mtd, NULL, NULL,
844 pdata->parts, pdata->nr_parts);
846 struct mtd_part_parser_data ppdata;
848 ppdata.of_node = pdev->dev.of_node;
849 ret = mtd_device_parse_register(&info->mtd, NULL, &ppdata,
855 val = davinci_nand_readl(info, NRCSR_OFFSET);
856 dev_info(&pdev->dev, "controller rev. %d.%d\n",
857 (val >> 8) & 0xff, val & 0xff);
862 clk_disable_unprepare(info->clk);
865 spin_lock_irq(&davinci_nand_lock);
866 if (ecc_mode == NAND_ECC_HW_SYNDROME)
868 spin_unlock_irq(&davinci_nand_lock);
872 static int nand_davinci_remove(struct platform_device *pdev)
874 struct davinci_nand_info *info = platform_get_drvdata(pdev);
876 spin_lock_irq(&davinci_nand_lock);
877 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
879 spin_unlock_irq(&davinci_nand_lock);
881 nand_release(&info->mtd);
883 clk_disable_unprepare(info->clk);
888 static struct platform_driver nand_davinci_driver = {
889 .probe = nand_davinci_probe,
890 .remove = nand_davinci_remove,
892 .name = "davinci_nand",
893 .of_match_table = of_match_ptr(davinci_nand_of_match),
896 MODULE_ALIAS("platform:davinci_nand");
898 module_platform_driver(nand_davinci_driver);
900 MODULE_LICENSE("GPL");
901 MODULE_AUTHOR("Texas Instruments");
902 MODULE_DESCRIPTION("Davinci NAND flash driver");