2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of_device.h>
36 #include <linux/of_mtd.h>
38 #include <asm/mach/flash.h>
39 #include <linux/platform_data/mtd-mxc_nand.h>
41 #define DRIVER_NAME "mxc_nand"
43 /* Addresses for NFC registers */
44 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
52 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
53 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
56 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
57 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
58 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
59 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
60 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
61 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
62 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
63 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
64 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
65 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
68 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
69 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
70 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
71 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
72 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
73 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
74 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
75 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
76 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
81 * Operation modes for the NFC. Valid for v1, v2 and v3
84 #define NFC_CMD (1 << 0)
85 #define NFC_ADDR (1 << 1)
86 #define NFC_INPUT (1 << 2)
87 #define NFC_OUTPUT (1 << 3)
88 #define NFC_ID (1 << 4)
89 #define NFC_STATUS (1 << 5)
91 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
92 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
95 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
96 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
103 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
104 #define NFC_V3_WRPROT_LOCK (1 << 1)
105 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
106 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
111 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
112 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
113 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
114 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
115 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
116 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
118 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
119 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
121 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
122 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
123 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
126 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
127 #define NFC_V3_CONFIG3_FW8 (1 << 3)
128 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
130 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
131 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133 #define NFC_V3_IPC (host->regs_ip + 0x2C)
134 #define NFC_V3_IPC_CREQ (1 << 0)
135 #define NFC_V3_IPC_INT (1 << 31)
137 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139 struct mxc_nand_host;
141 struct mxc_nand_devtype_data {
142 void (*preset)(struct mtd_info *);
143 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
144 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_page)(struct mtd_info *, unsigned int);
146 void (*send_read_id)(struct mxc_nand_host *);
147 uint16_t (*get_dev_status)(struct mxc_nand_host *);
148 int (*check_int)(struct mxc_nand_host *);
149 void (*irq_control)(struct mxc_nand_host *, int);
150 u32 (*get_ecc_status)(struct mxc_nand_host *);
151 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
152 void (*select_chip)(struct mtd_info *mtd, int chip);
153 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
154 u_char *read_ecc, u_char *calc_ecc);
157 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
158 * (CONFIG1:INT_MSK is set). To handle this the driver uses
159 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 int irqpending_quirk;
165 size_t spare0_offset;
174 struct mxc_nand_host {
176 struct nand_chip nand;
179 void __iomem *spare0;
180 void __iomem *main_area0;
184 void __iomem *regs_axi;
185 void __iomem *regs_ip;
193 struct completion op_completion;
196 unsigned int buf_start;
198 const struct mxc_nand_devtype_data *devtype_data;
199 struct mxc_nand_platform_data pdata;
202 /* OOB placement block for use with hardware ecc generation */
203 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
205 .eccpos = {6, 7, 8, 9, 10},
206 .oobfree = {{0, 5}, {12, 4}, }
209 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
211 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
212 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
213 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
216 /* OOB description for 512 byte pages with 16 byte OOB */
217 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
220 7, 8, 9, 10, 11, 12, 13, 14, 15
223 {.offset = 0, .length = 5}
227 /* OOB description for 2048 byte pages with 64 byte OOB */
228 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
231 7, 8, 9, 10, 11, 12, 13, 14, 15,
232 23, 24, 25, 26, 27, 28, 29, 30, 31,
233 39, 40, 41, 42, 43, 44, 45, 46, 47,
234 55, 56, 57, 58, 59, 60, 61, 62, 63
237 {.offset = 2, .length = 4},
238 {.offset = 16, .length = 7},
239 {.offset = 32, .length = 7},
240 {.offset = 48, .length = 7}
244 /* OOB description for 4096 byte pages with 128 byte OOB */
245 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
248 7, 8, 9, 10, 11, 12, 13, 14, 15,
249 23, 24, 25, 26, 27, 28, 29, 30, 31,
250 39, 40, 41, 42, 43, 44, 45, 46, 47,
251 55, 56, 57, 58, 59, 60, 61, 62, 63,
252 71, 72, 73, 74, 75, 76, 77, 78, 79,
253 87, 88, 89, 90, 91, 92, 93, 94, 95,
254 103, 104, 105, 106, 107, 108, 109, 110, 111,
255 119, 120, 121, 122, 123, 124, 125, 126, 127,
258 {.offset = 2, .length = 4},
259 {.offset = 16, .length = 7},
260 {.offset = 32, .length = 7},
261 {.offset = 48, .length = 7},
262 {.offset = 64, .length = 7},
263 {.offset = 80, .length = 7},
264 {.offset = 96, .length = 7},
265 {.offset = 112, .length = 7},
269 static const char const *part_probes[] = {
270 "cmdlinepart", "RedBoot", "ofpart", NULL };
272 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
276 const __iomem u32 *s = src;
278 for (i = 0; i < (size >> 2); i++)
279 *t++ = __raw_readl(s++);
282 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
285 u32 __iomem *t = trg;
288 for (i = 0; i < (size >> 2); i++)
289 __raw_writel(*s++, t++);
292 static int check_int_v3(struct mxc_nand_host *host)
296 tmp = readl(NFC_V3_IPC);
297 if (!(tmp & NFC_V3_IPC_INT))
300 tmp &= ~NFC_V3_IPC_INT;
301 writel(tmp, NFC_V3_IPC);
306 static int check_int_v1_v2(struct mxc_nand_host *host)
310 tmp = readw(NFC_V1_V2_CONFIG2);
311 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
314 if (!host->devtype_data->irqpending_quirk)
315 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
320 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
324 tmp = readw(NFC_V1_V2_CONFIG1);
327 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
329 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
331 writew(tmp, NFC_V1_V2_CONFIG1);
334 static void irq_control_v3(struct mxc_nand_host *host, int activate)
338 tmp = readl(NFC_V3_CONFIG2);
341 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
343 tmp |= NFC_V3_CONFIG2_INT_MSK;
345 writel(tmp, NFC_V3_CONFIG2);
348 static void irq_control(struct mxc_nand_host *host, int activate)
350 if (host->devtype_data->irqpending_quirk) {
352 enable_irq(host->irq);
354 disable_irq_nosync(host->irq);
356 host->devtype_data->irq_control(host, activate);
360 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
362 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
365 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
367 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
370 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
372 return readl(NFC_V3_ECC_STATUS_RESULT);
375 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
377 struct mxc_nand_host *host = dev_id;
379 if (!host->devtype_data->check_int(host))
382 irq_control(host, 0);
384 complete(&host->op_completion);
389 /* This function polls the NANDFC to wait for the basic operation to
390 * complete by checking the INT bit of config2 register.
392 static void wait_op_done(struct mxc_nand_host *host, int useirq)
394 int max_retries = 8000;
397 if (!host->devtype_data->check_int(host)) {
398 INIT_COMPLETION(host->op_completion);
399 irq_control(host, 1);
400 wait_for_completion(&host->op_completion);
403 while (max_retries-- > 0) {
404 if (host->devtype_data->check_int(host))
410 pr_debug("%s: INT not set\n", __func__);
414 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
417 writel(cmd, NFC_V3_FLASH_CMD);
419 /* send out command */
420 writel(NFC_CMD, NFC_V3_LAUNCH);
422 /* Wait for operation to complete */
423 wait_op_done(host, useirq);
426 /* This function issues the specified command to the NAND device and
427 * waits for completion. */
428 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
430 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
432 writew(cmd, NFC_V1_V2_FLASH_CMD);
433 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
435 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
436 int max_retries = 100;
437 /* Reset completion is indicated by NFC_CONFIG2 */
439 while (max_retries-- > 0) {
440 if (readw(NFC_V1_V2_CONFIG2) == 0) {
446 pr_debug("%s: RESET failed\n", __func__);
448 /* Wait for operation to complete */
449 wait_op_done(host, useirq);
453 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
456 writel(addr, NFC_V3_FLASH_ADDR0);
458 /* send out address */
459 writel(NFC_ADDR, NFC_V3_LAUNCH);
461 wait_op_done(host, 0);
464 /* This function sends an address (or partial address) to the
465 * NAND device. The address is used to select the source/destination for
467 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
469 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
471 writew(addr, NFC_V1_V2_FLASH_ADDR);
472 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
474 /* Wait for operation to complete */
475 wait_op_done(host, islast);
478 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
480 struct nand_chip *nand_chip = mtd->priv;
481 struct mxc_nand_host *host = nand_chip->priv;
484 tmp = readl(NFC_V3_CONFIG1);
486 writel(tmp, NFC_V3_CONFIG1);
488 /* transfer data from NFC ram to nand */
489 writel(ops, NFC_V3_LAUNCH);
491 wait_op_done(host, false);
494 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
496 struct nand_chip *nand_chip = mtd->priv;
497 struct mxc_nand_host *host = nand_chip->priv;
499 /* NANDFC buffer 0 is used for page read/write */
500 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
502 writew(ops, NFC_V1_V2_CONFIG2);
504 /* Wait for operation to complete */
505 wait_op_done(host, true);
508 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
510 struct nand_chip *nand_chip = mtd->priv;
511 struct mxc_nand_host *host = nand_chip->priv;
514 if (mtd->writesize > 512)
519 for (i = 0; i < bufs; i++) {
521 /* NANDFC buffer 0 is used for page read/write */
522 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
524 writew(ops, NFC_V1_V2_CONFIG2);
526 /* Wait for operation to complete */
527 wait_op_done(host, true);
531 static void send_read_id_v3(struct mxc_nand_host *host)
533 struct nand_chip *this = &host->nand;
535 /* Read ID into main buffer */
536 writel(NFC_ID, NFC_V3_LAUNCH);
538 wait_op_done(host, true);
540 memcpy32_fromio(host->data_buf, host->main_area0, 16);
542 if (this->options & NAND_BUSWIDTH_16) {
543 /* compress the ID info */
544 host->data_buf[1] = host->data_buf[2];
545 host->data_buf[2] = host->data_buf[4];
546 host->data_buf[3] = host->data_buf[6];
547 host->data_buf[4] = host->data_buf[8];
548 host->data_buf[5] = host->data_buf[10];
552 /* Request the NANDFC to perform a read of the NAND device ID. */
553 static void send_read_id_v1_v2(struct mxc_nand_host *host)
555 struct nand_chip *this = &host->nand;
557 /* NANDFC buffer 0 is used for device ID output */
558 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
560 writew(NFC_ID, NFC_V1_V2_CONFIG2);
562 /* Wait for operation to complete */
563 wait_op_done(host, true);
565 memcpy32_fromio(host->data_buf, host->main_area0, 16);
567 if (this->options & NAND_BUSWIDTH_16) {
568 /* compress the ID info */
569 host->data_buf[1] = host->data_buf[2];
570 host->data_buf[2] = host->data_buf[4];
571 host->data_buf[3] = host->data_buf[6];
572 host->data_buf[4] = host->data_buf[8];
573 host->data_buf[5] = host->data_buf[10];
577 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
579 writew(NFC_STATUS, NFC_V3_LAUNCH);
580 wait_op_done(host, true);
582 return readl(NFC_V3_CONFIG1) >> 16;
585 /* This function requests the NANDFC to perform a read of the
586 * NAND device status and returns the current status. */
587 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
589 void __iomem *main_buf = host->main_area0;
593 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
596 * The device status is stored in main_area0. To
597 * prevent corruption of the buffer save the value
598 * and restore it afterwards.
600 store = readl(main_buf);
602 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
603 wait_op_done(host, true);
605 ret = readw(main_buf);
607 writel(store, main_buf);
612 /* This functions is used by upper layer to checks if device is ready */
613 static int mxc_nand_dev_ready(struct mtd_info *mtd)
616 * NFC handles R/B internally. Therefore, this function
617 * always returns status as ready.
622 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
625 * If HW ECC is enabled, we turn it on during init. There is
626 * no need to enable again here.
630 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
631 u_char *read_ecc, u_char *calc_ecc)
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
637 * 1-Bit errors are automatically corrected in HW. No need for
638 * additional correction. 2-Bit errors cannot be corrected by
639 * HW ECC, so we need to return failure
641 uint16_t ecc_status = get_ecc_status_v1(host);
643 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
644 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
651 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
659 u8 ecc_bit_mask, err_limit;
661 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
662 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
664 no_subpages = mtd->writesize >> 9;
666 ecc_stat = host->devtype_data->get_ecc_status(host);
669 err = ecc_stat & ecc_bit_mask;
670 if (err > err_limit) {
671 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
677 } while (--no_subpages);
679 mtd->ecc_stats.corrected += ret;
680 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
685 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
691 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
693 struct nand_chip *nand_chip = mtd->priv;
694 struct mxc_nand_host *host = nand_chip->priv;
697 /* Check for status request */
698 if (host->status_request)
699 return host->devtype_data->get_dev_status(host) & 0xFF;
701 ret = *(uint8_t *)(host->data_buf + host->buf_start);
707 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
709 struct nand_chip *nand_chip = mtd->priv;
710 struct mxc_nand_host *host = nand_chip->priv;
713 ret = *(uint16_t *)(host->data_buf + host->buf_start);
714 host->buf_start += 2;
719 /* Write data of length len to buffer buf. The data to be
720 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
721 * Operation by the NFC, the data is written to NAND Flash */
722 static void mxc_nand_write_buf(struct mtd_info *mtd,
723 const u_char *buf, int len)
725 struct nand_chip *nand_chip = mtd->priv;
726 struct mxc_nand_host *host = nand_chip->priv;
727 u16 col = host->buf_start;
728 int n = mtd->oobsize + mtd->writesize - col;
732 memcpy(host->data_buf + col, buf, n);
734 host->buf_start += n;
737 /* Read the data buffer from the NAND Flash. To read the data from NAND
738 * Flash first the data output cycle is initiated by the NFC, which copies
739 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
741 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
743 struct nand_chip *nand_chip = mtd->priv;
744 struct mxc_nand_host *host = nand_chip->priv;
745 u16 col = host->buf_start;
746 int n = mtd->oobsize + mtd->writesize - col;
750 memcpy(buf, host->data_buf + col, n);
752 host->buf_start += n;
755 /* This function is used by upper layer for select and
756 * deselect of the NAND chip */
757 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
759 struct nand_chip *nand_chip = mtd->priv;
760 struct mxc_nand_host *host = nand_chip->priv;
763 /* Disable the NFC clock */
765 clk_disable_unprepare(host->clk);
771 if (!host->clk_act) {
772 /* Enable the NFC clock */
773 clk_prepare_enable(host->clk);
778 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
780 struct nand_chip *nand_chip = mtd->priv;
781 struct mxc_nand_host *host = nand_chip->priv;
784 /* Disable the NFC clock */
786 clk_disable_unprepare(host->clk);
792 if (!host->clk_act) {
793 /* Enable the NFC clock */
794 clk_prepare_enable(host->clk);
798 host->active_cs = chip;
799 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
803 * Function to transfer data to/from spare area.
805 static void copy_spare(struct mtd_info *mtd, bool bfrom)
807 struct nand_chip *this = mtd->priv;
808 struct mxc_nand_host *host = this->priv;
810 u16 n = mtd->writesize >> 9;
811 u8 *d = host->data_buf + mtd->writesize;
812 u8 __iomem *s = host->spare0;
813 u16 t = host->devtype_data->spare_len;
815 j = (mtd->oobsize / n >> 1) << 1;
818 for (i = 0; i < n - 1; i++)
819 memcpy32_fromio(d + i * j, s + i * t, j);
821 /* the last section */
822 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
824 for (i = 0; i < n - 1; i++)
825 memcpy32_toio(&s[i * t], &d[i * j], j);
827 /* the last section */
828 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
832 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
834 struct nand_chip *nand_chip = mtd->priv;
835 struct mxc_nand_host *host = nand_chip->priv;
837 /* Write out column address, if necessary */
840 * MXC NANDFC can only perform full page+spare or
841 * spare-only read/write. When the upper layers
842 * perform a read/write buf operation, the saved column
843 * address is used to index into the full page.
845 host->devtype_data->send_addr(host, 0, page_addr == -1);
846 if (mtd->writesize > 512)
847 /* another col addr cycle for 2k page */
848 host->devtype_data->send_addr(host, 0, false);
851 /* Write out page address, if necessary */
852 if (page_addr != -1) {
853 /* paddr_0 - p_addr_7 */
854 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
856 if (mtd->writesize > 512) {
857 if (mtd->size >= 0x10000000) {
858 /* paddr_8 - paddr_15 */
859 host->devtype_data->send_addr(host,
860 (page_addr >> 8) & 0xff,
862 host->devtype_data->send_addr(host,
863 (page_addr >> 16) & 0xff,
866 /* paddr_8 - paddr_15 */
867 host->devtype_data->send_addr(host,
868 (page_addr >> 8) & 0xff, true);
870 /* One more address cycle for higher density devices */
871 if (mtd->size >= 0x4000000) {
872 /* paddr_8 - paddr_15 */
873 host->devtype_data->send_addr(host,
874 (page_addr >> 8) & 0xff,
876 host->devtype_data->send_addr(host,
877 (page_addr >> 16) & 0xff,
880 /* paddr_8 - paddr_15 */
881 host->devtype_data->send_addr(host,
882 (page_addr >> 8) & 0xff, true);
888 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
889 * on how much oob the nand chip has. For 8bit ecc we need at least
890 * 26 bytes of oob data per 512 byte block.
892 static int get_eccsize(struct mtd_info *mtd)
894 int oobbytes_per_512 = 0;
896 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
898 if (oobbytes_per_512 < 26)
904 static void preset_v1(struct mtd_info *mtd)
906 struct nand_chip *nand_chip = mtd->priv;
907 struct mxc_nand_host *host = nand_chip->priv;
908 uint16_t config1 = 0;
910 if (nand_chip->ecc.mode == NAND_ECC_HW)
911 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
913 if (!host->devtype_data->irqpending_quirk)
914 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
918 writew(config1, NFC_V1_V2_CONFIG1);
919 /* preset operation */
921 /* Unlock the internal RAM Buffer */
922 writew(0x2, NFC_V1_V2_CONFIG);
924 /* Blocks to be unlocked */
925 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
926 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
928 /* Unlock Block Command for given address range */
929 writew(0x4, NFC_V1_V2_WRPROT);
932 static void preset_v2(struct mtd_info *mtd)
934 struct nand_chip *nand_chip = mtd->priv;
935 struct mxc_nand_host *host = nand_chip->priv;
936 uint16_t config1 = 0;
938 if (nand_chip->ecc.mode == NAND_ECC_HW)
939 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
941 config1 |= NFC_V2_CONFIG1_FP_INT;
943 if (!host->devtype_data->irqpending_quirk)
944 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
946 if (mtd->writesize) {
947 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
949 host->eccsize = get_eccsize(mtd);
950 if (host->eccsize == 4)
951 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
953 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
958 writew(config1, NFC_V1_V2_CONFIG1);
959 /* preset operation */
961 /* Unlock the internal RAM Buffer */
962 writew(0x2, NFC_V1_V2_CONFIG);
964 /* Blocks to be unlocked */
965 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
966 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
967 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
968 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
969 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
970 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
971 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
972 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
974 /* Unlock Block Command for given address range */
975 writew(0x4, NFC_V1_V2_WRPROT);
978 static void preset_v3(struct mtd_info *mtd)
980 struct nand_chip *chip = mtd->priv;
981 struct mxc_nand_host *host = chip->priv;
982 uint32_t config2, config3;
985 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
986 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
988 /* Unlock the internal RAM Buffer */
989 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
992 /* Blocks to be unlocked */
993 for (i = 0; i < NAND_MAX_CHIPS; i++)
994 writel(0x0 | (0xffff << 16),
995 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
997 writel(0, NFC_V3_IPC);
999 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1000 NFC_V3_CONFIG2_2CMD_PHASES |
1001 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1002 NFC_V3_CONFIG2_ST_CMD(0x70) |
1003 NFC_V3_CONFIG2_INT_MSK |
1004 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1006 if (chip->ecc.mode == NAND_ECC_HW)
1007 config2 |= NFC_V3_CONFIG2_ECC_EN;
1009 addr_phases = fls(chip->pagemask) >> 3;
1011 if (mtd->writesize == 2048) {
1012 config2 |= NFC_V3_CONFIG2_PS_2048;
1013 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1014 } else if (mtd->writesize == 4096) {
1015 config2 |= NFC_V3_CONFIG2_PS_4096;
1016 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1018 config2 |= NFC_V3_CONFIG2_PS_512;
1019 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1022 if (mtd->writesize) {
1023 config2 |= NFC_V3_CONFIG2_PPB(
1024 ffs(mtd->erasesize / mtd->writesize) - 6,
1025 host->devtype_data->ppb_shift);
1026 host->eccsize = get_eccsize(mtd);
1027 if (host->eccsize == 8)
1028 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1031 writel(config2, NFC_V3_CONFIG2);
1033 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1034 NFC_V3_CONFIG3_NO_SDMA |
1035 NFC_V3_CONFIG3_RBB_MODE |
1036 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1037 NFC_V3_CONFIG3_ADD_OP(0);
1039 if (!(chip->options & NAND_BUSWIDTH_16))
1040 config3 |= NFC_V3_CONFIG3_FW8;
1042 writel(config3, NFC_V3_CONFIG3);
1044 writel(0, NFC_V3_DELAY_LINE);
1047 /* Used by the upper layer to write command to NAND Flash for
1048 * different operations to be carried out on NAND Flash */
1049 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1050 int column, int page_addr)
1052 struct nand_chip *nand_chip = mtd->priv;
1053 struct mxc_nand_host *host = nand_chip->priv;
1055 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1056 command, column, page_addr);
1058 /* Reset command state information */
1059 host->status_request = false;
1061 /* Command pre-processing step */
1063 case NAND_CMD_RESET:
1064 host->devtype_data->preset(mtd);
1065 host->devtype_data->send_cmd(host, command, false);
1068 case NAND_CMD_STATUS:
1069 host->buf_start = 0;
1070 host->status_request = true;
1072 host->devtype_data->send_cmd(host, command, true);
1073 mxc_do_addr_cycle(mtd, column, page_addr);
1076 case NAND_CMD_READ0:
1077 case NAND_CMD_READOOB:
1078 if (command == NAND_CMD_READ0)
1079 host->buf_start = column;
1081 host->buf_start = column + mtd->writesize;
1083 command = NAND_CMD_READ0; /* only READ0 is valid */
1085 host->devtype_data->send_cmd(host, command, false);
1086 mxc_do_addr_cycle(mtd, column, page_addr);
1088 if (mtd->writesize > 512)
1089 host->devtype_data->send_cmd(host,
1090 NAND_CMD_READSTART, true);
1092 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1094 memcpy32_fromio(host->data_buf, host->main_area0,
1096 copy_spare(mtd, true);
1099 case NAND_CMD_SEQIN:
1100 if (column >= mtd->writesize)
1101 /* call ourself to read a page */
1102 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1104 host->buf_start = column;
1106 host->devtype_data->send_cmd(host, command, false);
1107 mxc_do_addr_cycle(mtd, column, page_addr);
1110 case NAND_CMD_PAGEPROG:
1111 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1112 copy_spare(mtd, false);
1113 host->devtype_data->send_page(mtd, NFC_INPUT);
1114 host->devtype_data->send_cmd(host, command, true);
1115 mxc_do_addr_cycle(mtd, column, page_addr);
1118 case NAND_CMD_READID:
1119 host->devtype_data->send_cmd(host, command, true);
1120 mxc_do_addr_cycle(mtd, column, page_addr);
1121 host->devtype_data->send_read_id(host);
1122 host->buf_start = column;
1125 case NAND_CMD_ERASE1:
1126 case NAND_CMD_ERASE2:
1127 host->devtype_data->send_cmd(host, command, false);
1128 mxc_do_addr_cycle(mtd, column, page_addr);
1135 * The generic flash bbt decriptors overlap with our ecc
1136 * hardware, so define some i.MX specific ones.
1138 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1139 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1141 static struct nand_bbt_descr bbt_main_descr = {
1142 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1143 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1148 .pattern = bbt_pattern,
1151 static struct nand_bbt_descr bbt_mirror_descr = {
1152 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1153 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1158 .pattern = mirror_pattern,
1161 /* v1 + irqpending_quirk: i.MX21 */
1162 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1163 .preset = preset_v1,
1164 .send_cmd = send_cmd_v1_v2,
1165 .send_addr = send_addr_v1_v2,
1166 .send_page = send_page_v1,
1167 .send_read_id = send_read_id_v1_v2,
1168 .get_dev_status = get_dev_status_v1_v2,
1169 .check_int = check_int_v1_v2,
1170 .irq_control = irq_control_v1_v2,
1171 .get_ecc_status = get_ecc_status_v1,
1172 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1173 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1174 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1175 .select_chip = mxc_nand_select_chip_v1_v3,
1176 .correct_data = mxc_nand_correct_data_v1,
1177 .irqpending_quirk = 1,
1179 .regs_offset = 0xe00,
1180 .spare0_offset = 0x800,
1186 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1187 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1188 .preset = preset_v1,
1189 .send_cmd = send_cmd_v1_v2,
1190 .send_addr = send_addr_v1_v2,
1191 .send_page = send_page_v1,
1192 .send_read_id = send_read_id_v1_v2,
1193 .get_dev_status = get_dev_status_v1_v2,
1194 .check_int = check_int_v1_v2,
1195 .irq_control = irq_control_v1_v2,
1196 .get_ecc_status = get_ecc_status_v1,
1197 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1198 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1199 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1200 .select_chip = mxc_nand_select_chip_v1_v3,
1201 .correct_data = mxc_nand_correct_data_v1,
1202 .irqpending_quirk = 0,
1204 .regs_offset = 0xe00,
1205 .spare0_offset = 0x800,
1212 /* v21: i.MX25, i.MX35 */
1213 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1214 .preset = preset_v2,
1215 .send_cmd = send_cmd_v1_v2,
1216 .send_addr = send_addr_v1_v2,
1217 .send_page = send_page_v2,
1218 .send_read_id = send_read_id_v1_v2,
1219 .get_dev_status = get_dev_status_v1_v2,
1220 .check_int = check_int_v1_v2,
1221 .irq_control = irq_control_v1_v2,
1222 .get_ecc_status = get_ecc_status_v2,
1223 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1224 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1225 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1226 .select_chip = mxc_nand_select_chip_v2,
1227 .correct_data = mxc_nand_correct_data_v2_v3,
1228 .irqpending_quirk = 0,
1230 .regs_offset = 0x1e00,
1231 .spare0_offset = 0x1000,
1239 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1240 .preset = preset_v3,
1241 .send_cmd = send_cmd_v3,
1242 .send_addr = send_addr_v3,
1243 .send_page = send_page_v3,
1244 .send_read_id = send_read_id_v3,
1245 .get_dev_status = get_dev_status_v3,
1246 .check_int = check_int_v3,
1247 .irq_control = irq_control_v3,
1248 .get_ecc_status = get_ecc_status_v3,
1249 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1250 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1251 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1252 .select_chip = mxc_nand_select_chip_v1_v3,
1253 .correct_data = mxc_nand_correct_data_v2_v3,
1254 .irqpending_quirk = 0,
1257 .spare0_offset = 0x1000,
1258 .axi_offset = 0x1e00,
1266 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1267 .preset = preset_v3,
1268 .send_cmd = send_cmd_v3,
1269 .send_addr = send_addr_v3,
1270 .send_page = send_page_v3,
1271 .send_read_id = send_read_id_v3,
1272 .get_dev_status = get_dev_status_v3,
1273 .check_int = check_int_v3,
1274 .irq_control = irq_control_v3,
1275 .get_ecc_status = get_ecc_status_v3,
1276 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1277 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1278 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1279 .select_chip = mxc_nand_select_chip_v1_v3,
1280 .correct_data = mxc_nand_correct_data_v2_v3,
1281 .irqpending_quirk = 0,
1284 .spare0_offset = 0x1000,
1285 .axi_offset = 0x1e00,
1292 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1294 return host->devtype_data == &imx21_nand_devtype_data;
1297 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1299 return host->devtype_data == &imx27_nand_devtype_data;
1302 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1304 return host->devtype_data == &imx25_nand_devtype_data;
1307 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1309 return host->devtype_data == &imx51_nand_devtype_data;
1312 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1314 return host->devtype_data == &imx53_nand_devtype_data;
1317 static struct platform_device_id mxcnd_devtype[] = {
1319 .name = "imx21-nand",
1320 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1322 .name = "imx27-nand",
1323 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1325 .name = "imx25-nand",
1326 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1328 .name = "imx51-nand",
1329 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1331 .name = "imx53-nand",
1332 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1337 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1339 #ifdef CONFIG_OF_MTD
1340 static const struct of_device_id mxcnd_dt_ids[] = {
1342 .compatible = "fsl,imx21-nand",
1343 .data = &imx21_nand_devtype_data,
1345 .compatible = "fsl,imx27-nand",
1346 .data = &imx27_nand_devtype_data,
1348 .compatible = "fsl,imx25-nand",
1349 .data = &imx25_nand_devtype_data,
1351 .compatible = "fsl,imx51-nand",
1352 .data = &imx51_nand_devtype_data,
1354 .compatible = "fsl,imx53-nand",
1355 .data = &imx53_nand_devtype_data,
1360 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1362 struct device_node *np = host->dev->of_node;
1363 struct mxc_nand_platform_data *pdata = &host->pdata;
1364 const struct of_device_id *of_id =
1365 of_match_device(mxcnd_dt_ids, host->dev);
1371 if (of_get_nand_ecc_mode(np) >= 0)
1374 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1376 buswidth = of_get_nand_bus_width(np);
1380 pdata->width = buswidth / 8;
1382 host->devtype_data = of_id->data;
1387 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1393 static int mxcnd_probe(struct platform_device *pdev)
1395 struct nand_chip *this;
1396 struct mtd_info *mtd;
1397 struct mxc_nand_host *host;
1398 struct resource *res;
1401 /* Allocate memory for MTD device structure and private data */
1402 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
1403 NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
1407 host->data_buf = (uint8_t *)(host + 1);
1409 host->dev = &pdev->dev;
1410 /* structures must be linked */
1414 mtd->owner = THIS_MODULE;
1415 mtd->dev.parent = &pdev->dev;
1416 mtd->name = DRIVER_NAME;
1418 /* 50 us command delay time */
1419 this->chip_delay = 5;
1422 this->dev_ready = mxc_nand_dev_ready;
1423 this->cmdfunc = mxc_nand_command;
1424 this->read_byte = mxc_nand_read_byte;
1425 this->read_word = mxc_nand_read_word;
1426 this->write_buf = mxc_nand_write_buf;
1427 this->read_buf = mxc_nand_read_buf;
1429 host->clk = devm_clk_get(&pdev->dev, NULL);
1430 if (IS_ERR(host->clk))
1431 return PTR_ERR(host->clk);
1433 err = mxcnd_probe_dt(host);
1435 struct mxc_nand_platform_data *pdata =
1436 dev_get_platdata(&pdev->dev);
1438 host->pdata = *pdata;
1439 host->devtype_data = (struct mxc_nand_devtype_data *)
1440 pdev->id_entry->driver_data;
1448 if (host->devtype_data->needs_ip) {
1449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1450 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1451 if (IS_ERR(host->regs_ip))
1452 return PTR_ERR(host->regs_ip);
1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1459 host->base = devm_ioremap_resource(&pdev->dev, res);
1460 if (IS_ERR(host->base))
1461 return PTR_ERR(host->base);
1463 host->main_area0 = host->base;
1465 if (host->devtype_data->regs_offset)
1466 host->regs = host->base + host->devtype_data->regs_offset;
1467 host->spare0 = host->base + host->devtype_data->spare0_offset;
1468 if (host->devtype_data->axi_offset)
1469 host->regs_axi = host->base + host->devtype_data->axi_offset;
1471 this->ecc.bytes = host->devtype_data->eccbytes;
1472 host->eccsize = host->devtype_data->eccsize;
1474 this->select_chip = host->devtype_data->select_chip;
1475 this->ecc.size = 512;
1476 this->ecc.layout = host->devtype_data->ecclayout_512;
1478 if (host->pdata.hw_ecc) {
1479 this->ecc.calculate = mxc_nand_calculate_ecc;
1480 this->ecc.hwctl = mxc_nand_enable_hwecc;
1481 this->ecc.correct = host->devtype_data->correct_data;
1482 this->ecc.mode = NAND_ECC_HW;
1484 this->ecc.mode = NAND_ECC_SOFT;
1487 /* NAND bus width determines access functions used by upper layer */
1488 if (host->pdata.width == 2)
1489 this->options |= NAND_BUSWIDTH_16;
1491 if (host->pdata.flash_bbt) {
1492 this->bbt_td = &bbt_main_descr;
1493 this->bbt_md = &bbt_mirror_descr;
1494 /* update flash based bbt */
1495 this->bbt_options |= NAND_BBT_USE_FLASH;
1498 init_completion(&host->op_completion);
1500 host->irq = platform_get_irq(pdev, 0);
1503 * Use host->devtype_data->irq_control() here instead of irq_control()
1504 * because we must not disable_irq_nosync without having requested the
1507 host->devtype_data->irq_control(host, 0);
1509 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1510 IRQF_DISABLED, DRIVER_NAME, host);
1514 clk_prepare_enable(host->clk);
1518 * Now that we "own" the interrupt make sure the interrupt mask bit is
1519 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1522 if (host->devtype_data->irqpending_quirk) {
1523 disable_irq_nosync(host->irq);
1524 host->devtype_data->irq_control(host, 1);
1527 /* first scan to find the device and get the page size */
1528 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1533 /* Call preset again, with correct writesize this time */
1534 host->devtype_data->preset(mtd);
1536 if (mtd->writesize == 2048)
1537 this->ecc.layout = host->devtype_data->ecclayout_2k;
1538 else if (mtd->writesize == 4096)
1539 this->ecc.layout = host->devtype_data->ecclayout_4k;
1541 if (this->ecc.mode == NAND_ECC_HW) {
1542 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1543 this->ecc.strength = 1;
1545 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1548 /* second phase scan */
1549 if (nand_scan_tail(mtd)) {
1554 /* Register the partitions */
1555 mtd_device_parse_register(mtd, part_probes,
1556 &(struct mtd_part_parser_data){
1557 .of_node = pdev->dev.of_node,
1560 host->pdata.nr_parts);
1562 platform_set_drvdata(pdev, host);
1568 clk_disable_unprepare(host->clk);
1573 static int mxcnd_remove(struct platform_device *pdev)
1575 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1577 nand_release(&host->mtd);
1582 static struct platform_driver mxcnd_driver = {
1584 .name = DRIVER_NAME,
1585 .owner = THIS_MODULE,
1586 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1588 .id_table = mxcnd_devtype,
1589 .probe = mxcnd_probe,
1590 .remove = mxcnd_remove,
1592 module_platform_driver(mxcnd_driver);
1594 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1595 MODULE_DESCRIPTION("MXC NAND MTD driver");
1596 MODULE_LICENSE("GPL");