5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
63 static struct nand_ecclayout nand_oob_16 = {
65 .eccpos = {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64 = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128 = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct mtd_info *mtd, int new_state);
98 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
99 struct mtd_oob_ops *ops);
102 * For devices which display every fart in the system on a separate LED. Is
103 * compiled away when LED support is disabled.
105 DEFINE_LED_TRIGGER(nand_led_trigger);
107 static int check_offs_len(struct mtd_info *mtd,
108 loff_t ofs, uint64_t len)
110 struct nand_chip *chip = mtd->priv;
113 /* Start address must align on block boundary */
114 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
115 pr_debug("%s: unaligned address\n", __func__);
119 /* Length must align on block boundary */
120 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
121 pr_debug("%s: length not block aligned\n", __func__);
129 * nand_release_device - [GENERIC] release chip
130 * @mtd: MTD device structure
132 * Release chip lock and wake up anyone waiting on the device.
134 static void nand_release_device(struct mtd_info *mtd)
136 struct nand_chip *chip = mtd->priv;
138 /* Release the controller and the chip */
139 spin_lock(&chip->controller->lock);
140 chip->controller->active = NULL;
141 chip->state = FL_READY;
142 wake_up(&chip->controller->wq);
143 spin_unlock(&chip->controller->lock);
147 * nand_read_byte - [DEFAULT] read one byte from the chip
148 * @mtd: MTD device structure
150 * Default read function for 8bit buswidth
152 static uint8_t nand_read_byte(struct mtd_info *mtd)
154 struct nand_chip *chip = mtd->priv;
155 return readb(chip->IO_ADDR_R);
159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
160 * @mtd: MTD device structure
162 * Default read function for 16bit buswidth with endianness conversion.
165 static uint8_t nand_read_byte16(struct mtd_info *mtd)
167 struct nand_chip *chip = mtd->priv;
168 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
172 * nand_read_word - [DEFAULT] read one word from the chip
173 * @mtd: MTD device structure
175 * Default read function for 16bit buswidth without endianness conversion.
177 static u16 nand_read_word(struct mtd_info *mtd)
179 struct nand_chip *chip = mtd->priv;
180 return readw(chip->IO_ADDR_R);
184 * nand_select_chip - [DEFAULT] control CE line
185 * @mtd: MTD device structure
186 * @chipnr: chipnumber to select, -1 for deselect
188 * Default select function for 1 chip devices.
190 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
192 struct nand_chip *chip = mtd->priv;
196 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
207 * nand_write_byte - [DEFAULT] write single byte to chip
208 * @mtd: MTD device structure
209 * @byte: value to write
211 * Default function to write a byte to I/O[7:0]
213 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
215 struct nand_chip *chip = mtd->priv;
217 chip->write_buf(mtd, &byte, 1);
221 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
222 * @mtd: MTD device structure
223 * @byte: value to write
225 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
227 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
229 struct nand_chip *chip = mtd->priv;
230 uint16_t word = byte;
233 * It's not entirely clear what should happen to I/O[15:8] when writing
234 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
236 * When the host supports a 16-bit bus width, only data is
237 * transferred at the 16-bit width. All address and command line
238 * transfers shall use only the lower 8-bits of the data bus. During
239 * command transfers, the host may place any value on the upper
240 * 8-bits of the data bus. During address transfers, the host shall
241 * set the upper 8-bits of the data bus to 00h.
243 * One user of the write_byte callback is nand_onfi_set_features. The
244 * four parameters are specified to be written to I/O[7:0], but this is
245 * neither an address nor a command transfer. Let's assume a 0 on the
246 * upper I/O lines is OK.
248 chip->write_buf(mtd, (uint8_t *)&word, 2);
252 * nand_write_buf - [DEFAULT] write buffer to chip
253 * @mtd: MTD device structure
255 * @len: number of bytes to write
257 * Default write function for 8bit buswidth.
259 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
261 struct nand_chip *chip = mtd->priv;
263 iowrite8_rep(chip->IO_ADDR_W, buf, len);
267 * nand_read_buf - [DEFAULT] read chip data into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
272 * Default read function for 8bit buswidth.
274 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
276 struct nand_chip *chip = mtd->priv;
278 ioread8_rep(chip->IO_ADDR_R, buf, len);
282 * nand_write_buf16 - [DEFAULT] write buffer to chip
283 * @mtd: MTD device structure
285 * @len: number of bytes to write
287 * Default write function for 16bit buswidth.
289 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
291 struct nand_chip *chip = mtd->priv;
292 u16 *p = (u16 *) buf;
294 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
298 * nand_read_buf16 - [DEFAULT] read chip data into buffer
299 * @mtd: MTD device structure
300 * @buf: buffer to store date
301 * @len: number of bytes to read
303 * Default read function for 16bit buswidth.
305 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
307 struct nand_chip *chip = mtd->priv;
308 u16 *p = (u16 *) buf;
310 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
314 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
315 * @mtd: MTD device structure
316 * @ofs: offset from device start
317 * @getchip: 0, if the chip is already selected
319 * Check, if the block is bad.
321 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
323 int page, chipnr, res = 0, i = 0;
324 struct nand_chip *chip = mtd->priv;
327 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
328 ofs += mtd->erasesize - mtd->writesize;
330 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
333 chipnr = (int)(ofs >> chip->chip_shift);
335 nand_get_device(mtd, FL_READING);
337 /* Select the NAND device */
338 chip->select_chip(mtd, chipnr);
342 if (chip->options & NAND_BUSWIDTH_16) {
343 chip->cmdfunc(mtd, NAND_CMD_READOOB,
344 chip->badblockpos & 0xFE, page);
345 bad = cpu_to_le16(chip->read_word(mtd));
346 if (chip->badblockpos & 0x1)
351 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
353 bad = chip->read_byte(mtd);
356 if (likely(chip->badblockbits == 8))
359 res = hweight8(bad) < chip->badblockbits;
360 ofs += mtd->writesize;
361 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
366 chip->select_chip(mtd, -1);
367 nand_release_device(mtd);
374 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
375 * @mtd: MTD device structure
376 * @ofs: offset from device start
378 * This is the default implementation, which can be overridden by a hardware
379 * specific driver. It provides the details for writing a bad block marker to a
382 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
384 struct nand_chip *chip = mtd->priv;
385 struct mtd_oob_ops ops;
386 uint8_t buf[2] = { 0, 0 };
387 int ret = 0, res, i = 0;
389 memset(&ops, 0, sizeof(ops));
391 ops.ooboffs = chip->badblockpos;
392 if (chip->options & NAND_BUSWIDTH_16) {
393 ops.ooboffs &= ~0x01;
394 ops.len = ops.ooblen = 2;
396 ops.len = ops.ooblen = 1;
398 ops.mode = MTD_OPS_PLACE_OOB;
400 /* Write to first/last page(s) if necessary */
401 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
402 ofs += mtd->erasesize - mtd->writesize;
404 res = nand_do_write_oob(mtd, ofs, &ops);
409 ofs += mtd->writesize;
410 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
416 * nand_block_markbad_lowlevel - mark a block bad
417 * @mtd: MTD device structure
418 * @ofs: offset from device start
420 * This function performs the generic NAND bad block marking steps (i.e., bad
421 * block table(s) and/or marker(s)). We only allow the hardware driver to
422 * specify how to write bad block markers to OOB (chip->block_markbad).
424 * We try operations in the following order:
425 * (1) erase the affected block, to allow OOB marker to be written cleanly
426 * (2) write bad block marker to OOB area of affected block (unless flag
427 * NAND_BBT_NO_OOB_BBM is present)
429 * Note that we retain the first error encountered in (2) or (3), finish the
430 * procedures, and dump the error in the end.
432 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
434 struct nand_chip *chip = mtd->priv;
437 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
438 struct erase_info einfo;
440 /* Attempt erase before marking OOB */
441 memset(&einfo, 0, sizeof(einfo));
444 einfo.len = 1ULL << chip->phys_erase_shift;
445 nand_erase_nand(mtd, &einfo, 0);
447 /* Write bad block marker to OOB */
448 nand_get_device(mtd, FL_WRITING);
449 ret = chip->block_markbad(mtd, ofs);
450 nand_release_device(mtd);
453 /* Mark block bad in BBT */
455 res = nand_markbad_bbt(mtd, ofs);
461 mtd->ecc_stats.badblocks++;
467 * nand_check_wp - [GENERIC] check if the chip is write protected
468 * @mtd: MTD device structure
470 * Check, if the device is write protected. The function expects, that the
471 * device is already selected.
473 static int nand_check_wp(struct mtd_info *mtd)
475 struct nand_chip *chip = mtd->priv;
477 /* Broken xD cards report WP despite being writable */
478 if (chip->options & NAND_BROKEN_XD)
481 /* Check the WP bit */
482 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
483 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
487 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
488 * @mtd: MTD device structure
489 * @ofs: offset from device start
491 * Check if the block is marked as reserved.
493 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
495 struct nand_chip *chip = mtd->priv;
499 /* Return info from the table */
500 return nand_isreserved_bbt(mtd, ofs);
504 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
505 * @mtd: MTD device structure
506 * @ofs: offset from device start
507 * @getchip: 0, if the chip is already selected
508 * @allowbbt: 1, if its allowed to access the bbt area
510 * Check, if the block is bad. Either by reading the bad block table or
511 * calling of the scan function.
513 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
516 struct nand_chip *chip = mtd->priv;
519 return chip->block_bad(mtd, ofs, getchip);
521 /* Return info from the table */
522 return nand_isbad_bbt(mtd, ofs, allowbbt);
526 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
527 * @mtd: MTD device structure
530 * Helper function for nand_wait_ready used when needing to wait in interrupt
533 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
535 struct nand_chip *chip = mtd->priv;
538 /* Wait for the device to get ready */
539 for (i = 0; i < timeo; i++) {
540 if (chip->dev_ready(mtd))
542 touch_softlockup_watchdog();
547 /* Wait for the ready pin, after a command. The timeout is caught later. */
548 void nand_wait_ready(struct mtd_info *mtd)
550 struct nand_chip *chip = mtd->priv;
551 unsigned long timeo = jiffies + msecs_to_jiffies(20);
554 if (in_interrupt() || oops_in_progress)
555 return panic_nand_wait_ready(mtd, 400);
557 led_trigger_event(nand_led_trigger, LED_FULL);
558 /* Wait until command is processed or timeout occurs */
560 if (chip->dev_ready(mtd))
562 touch_softlockup_watchdog();
563 } while (time_before(jiffies, timeo));
564 led_trigger_event(nand_led_trigger, LED_OFF);
566 EXPORT_SYMBOL_GPL(nand_wait_ready);
569 * nand_command - [DEFAULT] Send command to NAND device
570 * @mtd: MTD device structure
571 * @command: the command to be sent
572 * @column: the column address for this command, -1 if none
573 * @page_addr: the page address for this command, -1 if none
575 * Send command to NAND device. This function is used for small page devices
576 * (512 Bytes per page).
578 static void nand_command(struct mtd_info *mtd, unsigned int command,
579 int column, int page_addr)
581 register struct nand_chip *chip = mtd->priv;
582 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
584 /* Write out the command to the device */
585 if (command == NAND_CMD_SEQIN) {
588 if (column >= mtd->writesize) {
590 column -= mtd->writesize;
591 readcmd = NAND_CMD_READOOB;
592 } else if (column < 256) {
593 /* First 256 bytes --> READ0 */
594 readcmd = NAND_CMD_READ0;
597 readcmd = NAND_CMD_READ1;
599 chip->cmd_ctrl(mtd, readcmd, ctrl);
600 ctrl &= ~NAND_CTRL_CHANGE;
602 chip->cmd_ctrl(mtd, command, ctrl);
604 /* Address cycle, when necessary */
605 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
606 /* Serially input address */
608 /* Adjust columns for 16 bit buswidth */
609 if (chip->options & NAND_BUSWIDTH_16 &&
610 !nand_opcode_8bits(command))
612 chip->cmd_ctrl(mtd, column, ctrl);
613 ctrl &= ~NAND_CTRL_CHANGE;
615 if (page_addr != -1) {
616 chip->cmd_ctrl(mtd, page_addr, ctrl);
617 ctrl &= ~NAND_CTRL_CHANGE;
618 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
619 /* One more address cycle for devices > 32MiB */
620 if (chip->chipsize > (32 << 20))
621 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
623 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
626 * Program and erase have their own busy handlers status and sequential
631 case NAND_CMD_PAGEPROG:
632 case NAND_CMD_ERASE1:
633 case NAND_CMD_ERASE2:
635 case NAND_CMD_STATUS:
641 udelay(chip->chip_delay);
642 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
643 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
645 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
646 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
650 /* This applies to read commands */
653 * If we don't have access to the busy pin, we apply the given
656 if (!chip->dev_ready) {
657 udelay(chip->chip_delay);
662 * Apply this short delay always to ensure that we do wait tWB in
663 * any case on any machine.
667 nand_wait_ready(mtd);
671 * nand_command_lp - [DEFAULT] Send command to NAND large page device
672 * @mtd: MTD device structure
673 * @command: the command to be sent
674 * @column: the column address for this command, -1 if none
675 * @page_addr: the page address for this command, -1 if none
677 * Send command to NAND device. This is the version for the new large page
678 * devices. We don't have the separate regions as we have in the small page
679 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
681 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
682 int column, int page_addr)
684 register struct nand_chip *chip = mtd->priv;
686 /* Emulate NAND_CMD_READOOB */
687 if (command == NAND_CMD_READOOB) {
688 column += mtd->writesize;
689 command = NAND_CMD_READ0;
692 /* Command latch cycle */
693 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 if (column != -1 || page_addr != -1) {
696 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
698 /* Serially input address */
700 /* Adjust columns for 16 bit buswidth */
701 if (chip->options & NAND_BUSWIDTH_16 &&
702 !nand_opcode_8bits(command))
704 chip->cmd_ctrl(mtd, column, ctrl);
705 ctrl &= ~NAND_CTRL_CHANGE;
706 chip->cmd_ctrl(mtd, column >> 8, ctrl);
708 if (page_addr != -1) {
709 chip->cmd_ctrl(mtd, page_addr, ctrl);
710 chip->cmd_ctrl(mtd, page_addr >> 8,
711 NAND_NCE | NAND_ALE);
712 /* One more address cycle for devices > 128MiB */
713 if (chip->chipsize > (128 << 20))
714 chip->cmd_ctrl(mtd, page_addr >> 16,
715 NAND_NCE | NAND_ALE);
718 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
721 * Program and erase have their own busy handlers status, sequential
722 * in and status need no delay.
726 case NAND_CMD_CACHEDPROG:
727 case NAND_CMD_PAGEPROG:
728 case NAND_CMD_ERASE1:
729 case NAND_CMD_ERASE2:
732 case NAND_CMD_STATUS:
738 udelay(chip->chip_delay);
739 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
740 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
741 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
742 NAND_NCE | NAND_CTRL_CHANGE);
743 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
747 case NAND_CMD_RNDOUT:
748 /* No ready / busy check necessary */
749 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
750 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
751 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
752 NAND_NCE | NAND_CTRL_CHANGE);
756 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
757 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
758 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
759 NAND_NCE | NAND_CTRL_CHANGE);
761 /* This applies to read commands */
764 * If we don't have access to the busy pin, we apply the given
767 if (!chip->dev_ready) {
768 udelay(chip->chip_delay);
774 * Apply this short delay always to ensure that we do wait tWB in
775 * any case on any machine.
779 nand_wait_ready(mtd);
783 * panic_nand_get_device - [GENERIC] Get chip for selected access
784 * @chip: the nand chip descriptor
785 * @mtd: MTD device structure
786 * @new_state: the state which is requested
788 * Used when in panic, no locks are taken.
790 static void panic_nand_get_device(struct nand_chip *chip,
791 struct mtd_info *mtd, int new_state)
793 /* Hardware controller shared among independent devices */
794 chip->controller->active = chip;
795 chip->state = new_state;
799 * nand_get_device - [GENERIC] Get chip for selected access
800 * @mtd: MTD device structure
801 * @new_state: the state which is requested
803 * Get the device and lock it for exclusive access
806 nand_get_device(struct mtd_info *mtd, int new_state)
808 struct nand_chip *chip = mtd->priv;
809 spinlock_t *lock = &chip->controller->lock;
810 wait_queue_head_t *wq = &chip->controller->wq;
811 DECLARE_WAITQUEUE(wait, current);
815 /* Hardware controller shared among independent devices */
816 if (!chip->controller->active)
817 chip->controller->active = chip;
819 if (chip->controller->active == chip && chip->state == FL_READY) {
820 chip->state = new_state;
824 if (new_state == FL_PM_SUSPENDED) {
825 if (chip->controller->active->state == FL_PM_SUSPENDED) {
826 chip->state = FL_PM_SUSPENDED;
831 set_current_state(TASK_UNINTERRUPTIBLE);
832 add_wait_queue(wq, &wait);
835 remove_wait_queue(wq, &wait);
840 * panic_nand_wait - [GENERIC] wait until the command is done
841 * @mtd: MTD device structure
842 * @chip: NAND chip structure
845 * Wait for command done. This is a helper function for nand_wait used when
846 * we are in interrupt context. May happen when in panic and trying to write
847 * an oops through mtdoops.
849 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
853 for (i = 0; i < timeo; i++) {
854 if (chip->dev_ready) {
855 if (chip->dev_ready(mtd))
858 if (chip->read_byte(mtd) & NAND_STATUS_READY)
866 * nand_wait - [DEFAULT] wait until the command is done
867 * @mtd: MTD device structure
868 * @chip: NAND chip structure
870 * Wait for command done. This applies to erase and program only. Erase can
871 * take up to 400ms and program up to 20ms according to general NAND and
874 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
877 int status, state = chip->state;
878 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
880 led_trigger_event(nand_led_trigger, LED_FULL);
883 * Apply this short delay always to ensure that we do wait tWB in any
884 * case on any machine.
888 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
890 if (in_interrupt() || oops_in_progress)
891 panic_nand_wait(mtd, chip, timeo);
893 timeo = jiffies + msecs_to_jiffies(timeo);
894 while (time_before(jiffies, timeo)) {
895 if (chip->dev_ready) {
896 if (chip->dev_ready(mtd))
899 if (chip->read_byte(mtd) & NAND_STATUS_READY)
905 led_trigger_event(nand_led_trigger, LED_OFF);
907 status = (int)chip->read_byte(mtd);
908 /* This can happen if in case of timeout or buggy dev_ready */
909 WARN_ON(!(status & NAND_STATUS_READY));
914 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
916 * @ofs: offset to start unlock from
917 * @len: length to unlock
918 * @invert: when = 0, unlock the range of blocks within the lower and
919 * upper boundary address
920 * when = 1, unlock the range of blocks outside the boundaries
921 * of the lower and upper boundary address
923 * Returs unlock status.
925 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
926 uint64_t len, int invert)
930 struct nand_chip *chip = mtd->priv;
932 /* Submit address of first page to unlock */
933 page = ofs >> chip->page_shift;
934 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
936 /* Submit address of last page to unlock */
937 page = (ofs + len) >> chip->page_shift;
938 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
939 (page | invert) & chip->pagemask);
941 /* Call wait ready function */
942 status = chip->waitfunc(mtd, chip);
943 /* See if device thinks it succeeded */
944 if (status & NAND_STATUS_FAIL) {
945 pr_debug("%s: error status = 0x%08x\n",
954 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
956 * @ofs: offset to start unlock from
957 * @len: length to unlock
959 * Returns unlock status.
961 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
965 struct nand_chip *chip = mtd->priv;
967 pr_debug("%s: start = 0x%012llx, len = %llu\n",
968 __func__, (unsigned long long)ofs, len);
970 if (check_offs_len(mtd, ofs, len))
973 /* Align to last block address if size addresses end of the device */
974 if (ofs + len == mtd->size)
975 len -= mtd->erasesize;
977 nand_get_device(mtd, FL_UNLOCKING);
979 /* Shift to get chip number */
980 chipnr = ofs >> chip->chip_shift;
982 chip->select_chip(mtd, chipnr);
986 * If we want to check the WP through READ STATUS and check the bit 7
987 * we must reset the chip
988 * some operation can also clear the bit 7 of status register
989 * eg. erase/program a locked block
991 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
993 /* Check, if it is write protected */
994 if (nand_check_wp(mtd)) {
995 pr_debug("%s: device is write protected!\n",
1001 ret = __nand_unlock(mtd, ofs, len, 0);
1004 chip->select_chip(mtd, -1);
1005 nand_release_device(mtd);
1009 EXPORT_SYMBOL(nand_unlock);
1012 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1014 * @ofs: offset to start unlock from
1015 * @len: length to unlock
1017 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1018 * have this feature, but it allows only to lock all blocks, not for specified
1019 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1022 * Returns lock status.
1024 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1027 int chipnr, status, page;
1028 struct nand_chip *chip = mtd->priv;
1030 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1031 __func__, (unsigned long long)ofs, len);
1033 if (check_offs_len(mtd, ofs, len))
1036 nand_get_device(mtd, FL_LOCKING);
1038 /* Shift to get chip number */
1039 chipnr = ofs >> chip->chip_shift;
1041 chip->select_chip(mtd, chipnr);
1045 * If we want to check the WP through READ STATUS and check the bit 7
1046 * we must reset the chip
1047 * some operation can also clear the bit 7 of status register
1048 * eg. erase/program a locked block
1050 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1052 /* Check, if it is write protected */
1053 if (nand_check_wp(mtd)) {
1054 pr_debug("%s: device is write protected!\n",
1056 status = MTD_ERASE_FAILED;
1061 /* Submit address of first page to lock */
1062 page = ofs >> chip->page_shift;
1063 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1065 /* Call wait ready function */
1066 status = chip->waitfunc(mtd, chip);
1067 /* See if device thinks it succeeded */
1068 if (status & NAND_STATUS_FAIL) {
1069 pr_debug("%s: error status = 0x%08x\n",
1075 ret = __nand_unlock(mtd, ofs, len, 0x1);
1078 chip->select_chip(mtd, -1);
1079 nand_release_device(mtd);
1083 EXPORT_SYMBOL(nand_lock);
1086 * nand_read_page_raw - [INTERN] read raw page data without ecc
1087 * @mtd: mtd info structure
1088 * @chip: nand chip info structure
1089 * @buf: buffer to store read data
1090 * @oob_required: caller requires OOB data read to chip->oob_poi
1091 * @page: page number to read
1093 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1095 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1096 uint8_t *buf, int oob_required, int page)
1098 chip->read_buf(mtd, buf, mtd->writesize);
1100 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1105 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1106 * @mtd: mtd info structure
1107 * @chip: nand chip info structure
1108 * @buf: buffer to store read data
1109 * @oob_required: caller requires OOB data read to chip->oob_poi
1110 * @page: page number to read
1112 * We need a special oob layout and handling even when OOB isn't used.
1114 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1115 struct nand_chip *chip, uint8_t *buf,
1116 int oob_required, int page)
1118 int eccsize = chip->ecc.size;
1119 int eccbytes = chip->ecc.bytes;
1120 uint8_t *oob = chip->oob_poi;
1123 for (steps = chip->ecc.steps; steps > 0; steps--) {
1124 chip->read_buf(mtd, buf, eccsize);
1127 if (chip->ecc.prepad) {
1128 chip->read_buf(mtd, oob, chip->ecc.prepad);
1129 oob += chip->ecc.prepad;
1132 chip->read_buf(mtd, oob, eccbytes);
1135 if (chip->ecc.postpad) {
1136 chip->read_buf(mtd, oob, chip->ecc.postpad);
1137 oob += chip->ecc.postpad;
1141 size = mtd->oobsize - (oob - chip->oob_poi);
1143 chip->read_buf(mtd, oob, size);
1149 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1150 * @mtd: mtd info structure
1151 * @chip: nand chip info structure
1152 * @buf: buffer to store read data
1153 * @oob_required: caller requires OOB data read to chip->oob_poi
1154 * @page: page number to read
1156 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1157 uint8_t *buf, int oob_required, int page)
1159 int i, eccsize = chip->ecc.size;
1160 int eccbytes = chip->ecc.bytes;
1161 int eccsteps = chip->ecc.steps;
1163 uint8_t *ecc_calc = chip->buffers->ecccalc;
1164 uint8_t *ecc_code = chip->buffers->ecccode;
1165 uint32_t *eccpos = chip->ecc.layout->eccpos;
1166 unsigned int max_bitflips = 0;
1168 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1170 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1171 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1173 for (i = 0; i < chip->ecc.total; i++)
1174 ecc_code[i] = chip->oob_poi[eccpos[i]];
1176 eccsteps = chip->ecc.steps;
1179 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1182 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1184 mtd->ecc_stats.failed++;
1186 mtd->ecc_stats.corrected += stat;
1187 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1190 return max_bitflips;
1194 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1195 * @mtd: mtd info structure
1196 * @chip: nand chip info structure
1197 * @data_offs: offset of requested data within the page
1198 * @readlen: data length
1199 * @bufpoi: buffer to store read data
1200 * @page: page number to read
1202 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1203 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1206 int start_step, end_step, num_steps;
1207 uint32_t *eccpos = chip->ecc.layout->eccpos;
1209 int data_col_addr, i, gaps = 0;
1210 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1211 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1213 unsigned int max_bitflips = 0;
1215 /* Column address within the page aligned to ECC size (256bytes) */
1216 start_step = data_offs / chip->ecc.size;
1217 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1218 num_steps = end_step - start_step + 1;
1219 index = start_step * chip->ecc.bytes;
1221 /* Data size aligned to ECC ecc.size */
1222 datafrag_len = num_steps * chip->ecc.size;
1223 eccfrag_len = num_steps * chip->ecc.bytes;
1225 data_col_addr = start_step * chip->ecc.size;
1226 /* If we read not a page aligned data */
1227 if (data_col_addr != 0)
1228 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1230 p = bufpoi + data_col_addr;
1231 chip->read_buf(mtd, p, datafrag_len);
1234 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1235 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1238 * The performance is faster if we position offsets according to
1239 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1241 for (i = 0; i < eccfrag_len - 1; i++) {
1242 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1248 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1249 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1252 * Send the command to read the particular ECC bytes take care
1253 * about buswidth alignment in read_buf.
1255 aligned_pos = eccpos[index] & ~(busw - 1);
1256 aligned_len = eccfrag_len;
1257 if (eccpos[index] & (busw - 1))
1259 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1262 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1263 mtd->writesize + aligned_pos, -1);
1264 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1267 for (i = 0; i < eccfrag_len; i++)
1268 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1270 p = bufpoi + data_col_addr;
1271 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1274 stat = chip->ecc.correct(mtd, p,
1275 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1277 mtd->ecc_stats.failed++;
1279 mtd->ecc_stats.corrected += stat;
1280 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1283 return max_bitflips;
1287 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1288 * @mtd: mtd info structure
1289 * @chip: nand chip info structure
1290 * @buf: buffer to store read data
1291 * @oob_required: caller requires OOB data read to chip->oob_poi
1292 * @page: page number to read
1294 * Not for syndrome calculating ECC controllers which need a special oob layout.
1296 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1297 uint8_t *buf, int oob_required, int page)
1299 int i, eccsize = chip->ecc.size;
1300 int eccbytes = chip->ecc.bytes;
1301 int eccsteps = chip->ecc.steps;
1303 uint8_t *ecc_calc = chip->buffers->ecccalc;
1304 uint8_t *ecc_code = chip->buffers->ecccode;
1305 uint32_t *eccpos = chip->ecc.layout->eccpos;
1306 unsigned int max_bitflips = 0;
1308 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1309 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1310 chip->read_buf(mtd, p, eccsize);
1311 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1313 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1315 for (i = 0; i < chip->ecc.total; i++)
1316 ecc_code[i] = chip->oob_poi[eccpos[i]];
1318 eccsteps = chip->ecc.steps;
1321 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1326 mtd->ecc_stats.failed++;
1328 mtd->ecc_stats.corrected += stat;
1329 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1332 return max_bitflips;
1336 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1337 * @mtd: mtd info structure
1338 * @chip: nand chip info structure
1339 * @buf: buffer to store read data
1340 * @oob_required: caller requires OOB data read to chip->oob_poi
1341 * @page: page number to read
1343 * Hardware ECC for large page chips, require OOB to be read first. For this
1344 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1345 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1346 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1347 * the data area, by overwriting the NAND manufacturer bad block markings.
1349 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1350 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1352 int i, eccsize = chip->ecc.size;
1353 int eccbytes = chip->ecc.bytes;
1354 int eccsteps = chip->ecc.steps;
1356 uint8_t *ecc_code = chip->buffers->ecccode;
1357 uint32_t *eccpos = chip->ecc.layout->eccpos;
1358 uint8_t *ecc_calc = chip->buffers->ecccalc;
1359 unsigned int max_bitflips = 0;
1361 /* Read the OOB area first */
1362 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1363 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1364 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1366 for (i = 0; i < chip->ecc.total; i++)
1367 ecc_code[i] = chip->oob_poi[eccpos[i]];
1369 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1372 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1373 chip->read_buf(mtd, p, eccsize);
1374 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1376 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1378 mtd->ecc_stats.failed++;
1380 mtd->ecc_stats.corrected += stat;
1381 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1384 return max_bitflips;
1388 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1389 * @mtd: mtd info structure
1390 * @chip: nand chip info structure
1391 * @buf: buffer to store read data
1392 * @oob_required: caller requires OOB data read to chip->oob_poi
1393 * @page: page number to read
1395 * The hw generator calculates the error syndrome automatically. Therefore we
1396 * need a special oob layout and handling.
1398 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1399 uint8_t *buf, int oob_required, int page)
1401 int i, eccsize = chip->ecc.size;
1402 int eccbytes = chip->ecc.bytes;
1403 int eccsteps = chip->ecc.steps;
1405 uint8_t *oob = chip->oob_poi;
1406 unsigned int max_bitflips = 0;
1408 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1411 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1412 chip->read_buf(mtd, p, eccsize);
1414 if (chip->ecc.prepad) {
1415 chip->read_buf(mtd, oob, chip->ecc.prepad);
1416 oob += chip->ecc.prepad;
1419 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1420 chip->read_buf(mtd, oob, eccbytes);
1421 stat = chip->ecc.correct(mtd, p, oob, NULL);
1424 mtd->ecc_stats.failed++;
1426 mtd->ecc_stats.corrected += stat;
1427 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1432 if (chip->ecc.postpad) {
1433 chip->read_buf(mtd, oob, chip->ecc.postpad);
1434 oob += chip->ecc.postpad;
1438 /* Calculate remaining oob bytes */
1439 i = mtd->oobsize - (oob - chip->oob_poi);
1441 chip->read_buf(mtd, oob, i);
1443 return max_bitflips;
1447 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1448 * @chip: nand chip structure
1449 * @oob: oob destination address
1450 * @ops: oob ops structure
1451 * @len: size of oob to transfer
1453 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1454 struct mtd_oob_ops *ops, size_t len)
1456 switch (ops->mode) {
1458 case MTD_OPS_PLACE_OOB:
1460 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1463 case MTD_OPS_AUTO_OOB: {
1464 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1465 uint32_t boffs = 0, roffs = ops->ooboffs;
1468 for (; free->length && len; free++, len -= bytes) {
1469 /* Read request not from offset 0? */
1470 if (unlikely(roffs)) {
1471 if (roffs >= free->length) {
1472 roffs -= free->length;
1475 boffs = free->offset + roffs;
1476 bytes = min_t(size_t, len,
1477 (free->length - roffs));
1480 bytes = min_t(size_t, len, free->length);
1481 boffs = free->offset;
1483 memcpy(oob, chip->oob_poi + boffs, bytes);
1495 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1496 * @mtd: MTD device structure
1497 * @retry_mode: the retry mode to use
1499 * Some vendors supply a special command to shift the Vt threshold, to be used
1500 * when there are too many bitflips in a page (i.e., ECC error). After setting
1501 * a new threshold, the host should retry reading the page.
1503 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1505 struct nand_chip *chip = mtd->priv;
1507 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1509 if (retry_mode >= chip->read_retries)
1512 if (!chip->setup_read_retry)
1515 return chip->setup_read_retry(mtd, retry_mode);
1519 * nand_do_read_ops - [INTERN] Read data with ECC
1520 * @mtd: MTD device structure
1521 * @from: offset to read from
1522 * @ops: oob ops structure
1524 * Internal function. Called with chip held.
1526 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1527 struct mtd_oob_ops *ops)
1529 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1530 struct nand_chip *chip = mtd->priv;
1532 uint32_t readlen = ops->len;
1533 uint32_t oobreadlen = ops->ooblen;
1534 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1535 mtd->oobavail : mtd->oobsize;
1537 uint8_t *bufpoi, *oob, *buf;
1539 unsigned int max_bitflips = 0;
1541 bool ecc_fail = false;
1543 chipnr = (int)(from >> chip->chip_shift);
1544 chip->select_chip(mtd, chipnr);
1546 realpage = (int)(from >> chip->page_shift);
1547 page = realpage & chip->pagemask;
1549 col = (int)(from & (mtd->writesize - 1));
1553 oob_required = oob ? 1 : 0;
1556 unsigned int ecc_failures = mtd->ecc_stats.failed;
1558 bytes = min(mtd->writesize - col, readlen);
1559 aligned = (bytes == mtd->writesize);
1563 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1564 use_bufpoi = !virt_addr_valid(buf);
1568 /* Is the current page in the buffer? */
1569 if (realpage != chip->pagebuf || oob) {
1570 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1572 if (use_bufpoi && aligned)
1573 pr_debug("%s: using read bounce buffer for buf@%p\n",
1577 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1580 * Now read the page into the buffer. Absent an error,
1581 * the read methods return max bitflips per ecc step.
1583 if (unlikely(ops->mode == MTD_OPS_RAW))
1584 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1587 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1589 ret = chip->ecc.read_subpage(mtd, chip,
1593 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1594 oob_required, page);
1597 /* Invalidate page cache */
1602 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1604 /* Transfer not aligned data */
1606 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1607 !(mtd->ecc_stats.failed - ecc_failures) &&
1608 (ops->mode != MTD_OPS_RAW)) {
1609 chip->pagebuf = realpage;
1610 chip->pagebuf_bitflips = ret;
1612 /* Invalidate page cache */
1615 memcpy(buf, chip->buffers->databuf + col, bytes);
1618 if (unlikely(oob)) {
1619 int toread = min(oobreadlen, max_oobsize);
1622 oob = nand_transfer_oob(chip,
1624 oobreadlen -= toread;
1628 if (chip->options & NAND_NEED_READRDY) {
1629 /* Apply delay or wait for ready/busy pin */
1630 if (!chip->dev_ready)
1631 udelay(chip->chip_delay);
1633 nand_wait_ready(mtd);
1636 if (mtd->ecc_stats.failed - ecc_failures) {
1637 if (retry_mode + 1 < chip->read_retries) {
1639 ret = nand_setup_read_retry(mtd,
1644 /* Reset failures; retry */
1645 mtd->ecc_stats.failed = ecc_failures;
1648 /* No more retry modes; real failure */
1655 memcpy(buf, chip->buffers->databuf + col, bytes);
1657 max_bitflips = max_t(unsigned int, max_bitflips,
1658 chip->pagebuf_bitflips);
1663 /* Reset to retry mode 0 */
1665 ret = nand_setup_read_retry(mtd, 0);
1674 /* For subsequent reads align to page boundary */
1676 /* Increment page address */
1679 page = realpage & chip->pagemask;
1680 /* Check, if we cross a chip boundary */
1683 chip->select_chip(mtd, -1);
1684 chip->select_chip(mtd, chipnr);
1687 chip->select_chip(mtd, -1);
1689 ops->retlen = ops->len - (size_t) readlen;
1691 ops->oobretlen = ops->ooblen - oobreadlen;
1699 return max_bitflips;
1703 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1704 * @mtd: MTD device structure
1705 * @from: offset to read from
1706 * @len: number of bytes to read
1707 * @retlen: pointer to variable to store the number of read bytes
1708 * @buf: the databuffer to put data
1710 * Get hold of the chip and call nand_do_read.
1712 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1713 size_t *retlen, uint8_t *buf)
1715 struct mtd_oob_ops ops;
1718 nand_get_device(mtd, FL_READING);
1719 memset(&ops, 0, sizeof(ops));
1722 ops.mode = MTD_OPS_PLACE_OOB;
1723 ret = nand_do_read_ops(mtd, from, &ops);
1724 *retlen = ops.retlen;
1725 nand_release_device(mtd);
1730 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1731 * @mtd: mtd info structure
1732 * @chip: nand chip info structure
1733 * @page: page number to read
1735 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1738 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1739 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1744 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1746 * @mtd: mtd info structure
1747 * @chip: nand chip info structure
1748 * @page: page number to read
1750 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1753 int length = mtd->oobsize;
1754 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1755 int eccsize = chip->ecc.size;
1756 uint8_t *bufpoi = chip->oob_poi;
1757 int i, toread, sndrnd = 0, pos;
1759 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1760 for (i = 0; i < chip->ecc.steps; i++) {
1762 pos = eccsize + i * (eccsize + chunk);
1763 if (mtd->writesize > 512)
1764 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1766 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1769 toread = min_t(int, length, chunk);
1770 chip->read_buf(mtd, bufpoi, toread);
1775 chip->read_buf(mtd, bufpoi, length);
1781 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1782 * @mtd: mtd info structure
1783 * @chip: nand chip info structure
1784 * @page: page number to write
1786 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1790 const uint8_t *buf = chip->oob_poi;
1791 int length = mtd->oobsize;
1793 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1794 chip->write_buf(mtd, buf, length);
1795 /* Send command to program the OOB data */
1796 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1798 status = chip->waitfunc(mtd, chip);
1800 return status & NAND_STATUS_FAIL ? -EIO : 0;
1804 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1805 * with syndrome - only for large page flash
1806 * @mtd: mtd info structure
1807 * @chip: nand chip info structure
1808 * @page: page number to write
1810 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1811 struct nand_chip *chip, int page)
1813 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1814 int eccsize = chip->ecc.size, length = mtd->oobsize;
1815 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1816 const uint8_t *bufpoi = chip->oob_poi;
1819 * data-ecc-data-ecc ... ecc-oob
1821 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1823 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1824 pos = steps * (eccsize + chunk);
1829 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1830 for (i = 0; i < steps; i++) {
1832 if (mtd->writesize <= 512) {
1833 uint32_t fill = 0xFFFFFFFF;
1837 int num = min_t(int, len, 4);
1838 chip->write_buf(mtd, (uint8_t *)&fill,
1843 pos = eccsize + i * (eccsize + chunk);
1844 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1848 len = min_t(int, length, chunk);
1849 chip->write_buf(mtd, bufpoi, len);
1854 chip->write_buf(mtd, bufpoi, length);
1856 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1857 status = chip->waitfunc(mtd, chip);
1859 return status & NAND_STATUS_FAIL ? -EIO : 0;
1863 * nand_do_read_oob - [INTERN] NAND read out-of-band
1864 * @mtd: MTD device structure
1865 * @from: offset to read from
1866 * @ops: oob operations description structure
1868 * NAND read out-of-band data from the spare area.
1870 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1871 struct mtd_oob_ops *ops)
1873 int page, realpage, chipnr;
1874 struct nand_chip *chip = mtd->priv;
1875 struct mtd_ecc_stats stats;
1876 int readlen = ops->ooblen;
1878 uint8_t *buf = ops->oobbuf;
1881 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1882 __func__, (unsigned long long)from, readlen);
1884 stats = mtd->ecc_stats;
1886 if (ops->mode == MTD_OPS_AUTO_OOB)
1887 len = chip->ecc.layout->oobavail;
1891 if (unlikely(ops->ooboffs >= len)) {
1892 pr_debug("%s: attempt to start read outside oob\n",
1897 /* Do not allow reads past end of device */
1898 if (unlikely(from >= mtd->size ||
1899 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1900 (from >> chip->page_shift)) * len)) {
1901 pr_debug("%s: attempt to read beyond end of device\n",
1906 chipnr = (int)(from >> chip->chip_shift);
1907 chip->select_chip(mtd, chipnr);
1909 /* Shift to get page */
1910 realpage = (int)(from >> chip->page_shift);
1911 page = realpage & chip->pagemask;
1914 if (ops->mode == MTD_OPS_RAW)
1915 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1917 ret = chip->ecc.read_oob(mtd, chip, page);
1922 len = min(len, readlen);
1923 buf = nand_transfer_oob(chip, buf, ops, len);
1925 if (chip->options & NAND_NEED_READRDY) {
1926 /* Apply delay or wait for ready/busy pin */
1927 if (!chip->dev_ready)
1928 udelay(chip->chip_delay);
1930 nand_wait_ready(mtd);
1937 /* Increment page address */
1940 page = realpage & chip->pagemask;
1941 /* Check, if we cross a chip boundary */
1944 chip->select_chip(mtd, -1);
1945 chip->select_chip(mtd, chipnr);
1948 chip->select_chip(mtd, -1);
1950 ops->oobretlen = ops->ooblen - readlen;
1955 if (mtd->ecc_stats.failed - stats.failed)
1958 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1962 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1963 * @mtd: MTD device structure
1964 * @from: offset to read from
1965 * @ops: oob operation description structure
1967 * NAND read data and/or out-of-band data.
1969 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1970 struct mtd_oob_ops *ops)
1972 int ret = -ENOTSUPP;
1976 /* Do not allow reads past end of device */
1977 if (ops->datbuf && (from + ops->len) > mtd->size) {
1978 pr_debug("%s: attempt to read beyond end of device\n",
1983 nand_get_device(mtd, FL_READING);
1985 switch (ops->mode) {
1986 case MTD_OPS_PLACE_OOB:
1987 case MTD_OPS_AUTO_OOB:
1996 ret = nand_do_read_oob(mtd, from, ops);
1998 ret = nand_do_read_ops(mtd, from, ops);
2001 nand_release_device(mtd);
2007 * nand_write_page_raw - [INTERN] raw page write function
2008 * @mtd: mtd info structure
2009 * @chip: nand chip info structure
2011 * @oob_required: must write chip->oob_poi to OOB
2013 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2015 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2016 const uint8_t *buf, int oob_required)
2018 chip->write_buf(mtd, buf, mtd->writesize);
2020 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2026 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2027 * @mtd: mtd info structure
2028 * @chip: nand chip info structure
2030 * @oob_required: must write chip->oob_poi to OOB
2032 * We need a special oob layout and handling even when ECC isn't checked.
2034 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2035 struct nand_chip *chip,
2036 const uint8_t *buf, int oob_required)
2038 int eccsize = chip->ecc.size;
2039 int eccbytes = chip->ecc.bytes;
2040 uint8_t *oob = chip->oob_poi;
2043 for (steps = chip->ecc.steps; steps > 0; steps--) {
2044 chip->write_buf(mtd, buf, eccsize);
2047 if (chip->ecc.prepad) {
2048 chip->write_buf(mtd, oob, chip->ecc.prepad);
2049 oob += chip->ecc.prepad;
2052 chip->write_buf(mtd, oob, eccbytes);
2055 if (chip->ecc.postpad) {
2056 chip->write_buf(mtd, oob, chip->ecc.postpad);
2057 oob += chip->ecc.postpad;
2061 size = mtd->oobsize - (oob - chip->oob_poi);
2063 chip->write_buf(mtd, oob, size);
2068 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2069 * @mtd: mtd info structure
2070 * @chip: nand chip info structure
2072 * @oob_required: must write chip->oob_poi to OOB
2074 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2075 const uint8_t *buf, int oob_required)
2077 int i, eccsize = chip->ecc.size;
2078 int eccbytes = chip->ecc.bytes;
2079 int eccsteps = chip->ecc.steps;
2080 uint8_t *ecc_calc = chip->buffers->ecccalc;
2081 const uint8_t *p = buf;
2082 uint32_t *eccpos = chip->ecc.layout->eccpos;
2084 /* Software ECC calculation */
2085 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2086 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2088 for (i = 0; i < chip->ecc.total; i++)
2089 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2091 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2095 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2096 * @mtd: mtd info structure
2097 * @chip: nand chip info structure
2099 * @oob_required: must write chip->oob_poi to OOB
2101 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2102 const uint8_t *buf, int oob_required)
2104 int i, eccsize = chip->ecc.size;
2105 int eccbytes = chip->ecc.bytes;
2106 int eccsteps = chip->ecc.steps;
2107 uint8_t *ecc_calc = chip->buffers->ecccalc;
2108 const uint8_t *p = buf;
2109 uint32_t *eccpos = chip->ecc.layout->eccpos;
2111 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2112 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2113 chip->write_buf(mtd, p, eccsize);
2114 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2117 for (i = 0; i < chip->ecc.total; i++)
2118 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2120 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2127 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2128 * @mtd: mtd info structure
2129 * @chip: nand chip info structure
2130 * @offset: column address of subpage within the page
2131 * @data_len: data length
2133 * @oob_required: must write chip->oob_poi to OOB
2135 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2136 struct nand_chip *chip, uint32_t offset,
2137 uint32_t data_len, const uint8_t *buf,
2140 uint8_t *oob_buf = chip->oob_poi;
2141 uint8_t *ecc_calc = chip->buffers->ecccalc;
2142 int ecc_size = chip->ecc.size;
2143 int ecc_bytes = chip->ecc.bytes;
2144 int ecc_steps = chip->ecc.steps;
2145 uint32_t *eccpos = chip->ecc.layout->eccpos;
2146 uint32_t start_step = offset / ecc_size;
2147 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2148 int oob_bytes = mtd->oobsize / ecc_steps;
2151 for (step = 0; step < ecc_steps; step++) {
2152 /* configure controller for WRITE access */
2153 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2155 /* write data (untouched subpages already masked by 0xFF) */
2156 chip->write_buf(mtd, buf, ecc_size);
2158 /* mask ECC of un-touched subpages by padding 0xFF */
2159 if ((step < start_step) || (step > end_step))
2160 memset(ecc_calc, 0xff, ecc_bytes);
2162 chip->ecc.calculate(mtd, buf, ecc_calc);
2164 /* mask OOB of un-touched subpages by padding 0xFF */
2165 /* if oob_required, preserve OOB metadata of written subpage */
2166 if (!oob_required || (step < start_step) || (step > end_step))
2167 memset(oob_buf, 0xff, oob_bytes);
2170 ecc_calc += ecc_bytes;
2171 oob_buf += oob_bytes;
2174 /* copy calculated ECC for whole page to chip->buffer->oob */
2175 /* this include masked-value(0xFF) for unwritten subpages */
2176 ecc_calc = chip->buffers->ecccalc;
2177 for (i = 0; i < chip->ecc.total; i++)
2178 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2180 /* write OOB buffer to NAND device */
2181 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2188 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2189 * @mtd: mtd info structure
2190 * @chip: nand chip info structure
2192 * @oob_required: must write chip->oob_poi to OOB
2194 * The hw generator calculates the error syndrome automatically. Therefore we
2195 * need a special oob layout and handling.
2197 static int nand_write_page_syndrome(struct mtd_info *mtd,
2198 struct nand_chip *chip,
2199 const uint8_t *buf, int oob_required)
2201 int i, eccsize = chip->ecc.size;
2202 int eccbytes = chip->ecc.bytes;
2203 int eccsteps = chip->ecc.steps;
2204 const uint8_t *p = buf;
2205 uint8_t *oob = chip->oob_poi;
2207 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2209 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2210 chip->write_buf(mtd, p, eccsize);
2212 if (chip->ecc.prepad) {
2213 chip->write_buf(mtd, oob, chip->ecc.prepad);
2214 oob += chip->ecc.prepad;
2217 chip->ecc.calculate(mtd, p, oob);
2218 chip->write_buf(mtd, oob, eccbytes);
2221 if (chip->ecc.postpad) {
2222 chip->write_buf(mtd, oob, chip->ecc.postpad);
2223 oob += chip->ecc.postpad;
2227 /* Calculate remaining oob bytes */
2228 i = mtd->oobsize - (oob - chip->oob_poi);
2230 chip->write_buf(mtd, oob, i);
2236 * nand_write_page - [REPLACEABLE] write one page
2237 * @mtd: MTD device structure
2238 * @chip: NAND chip descriptor
2239 * @offset: address offset within the page
2240 * @data_len: length of actual data to be written
2241 * @buf: the data to write
2242 * @oob_required: must write chip->oob_poi to OOB
2243 * @page: page number to write
2244 * @cached: cached programming
2245 * @raw: use _raw version of write_page
2247 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2248 uint32_t offset, int data_len, const uint8_t *buf,
2249 int oob_required, int page, int cached, int raw)
2251 int status, subpage;
2253 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2254 chip->ecc.write_subpage)
2255 subpage = offset || (data_len < mtd->writesize);
2259 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2262 status = chip->ecc.write_page_raw(mtd, chip, buf,
2265 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2268 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2274 * Cached progamming disabled for now. Not sure if it's worth the
2275 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2279 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2281 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2282 status = chip->waitfunc(mtd, chip);
2284 * See if operation failed and additional status checks are
2287 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2288 status = chip->errstat(mtd, chip, FL_WRITING, status,
2291 if (status & NAND_STATUS_FAIL)
2294 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2295 status = chip->waitfunc(mtd, chip);
2302 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2303 * @mtd: MTD device structure
2304 * @oob: oob data buffer
2305 * @len: oob data write length
2306 * @ops: oob ops structure
2308 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2309 struct mtd_oob_ops *ops)
2311 struct nand_chip *chip = mtd->priv;
2314 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2315 * data from a previous OOB read.
2317 memset(chip->oob_poi, 0xff, mtd->oobsize);
2319 switch (ops->mode) {
2321 case MTD_OPS_PLACE_OOB:
2323 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2326 case MTD_OPS_AUTO_OOB: {
2327 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2328 uint32_t boffs = 0, woffs = ops->ooboffs;
2331 for (; free->length && len; free++, len -= bytes) {
2332 /* Write request not from offset 0? */
2333 if (unlikely(woffs)) {
2334 if (woffs >= free->length) {
2335 woffs -= free->length;
2338 boffs = free->offset + woffs;
2339 bytes = min_t(size_t, len,
2340 (free->length - woffs));
2343 bytes = min_t(size_t, len, free->length);
2344 boffs = free->offset;
2346 memcpy(chip->oob_poi + boffs, oob, bytes);
2357 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2360 * nand_do_write_ops - [INTERN] NAND write with ECC
2361 * @mtd: MTD device structure
2362 * @to: offset to write to
2363 * @ops: oob operations description structure
2365 * NAND write with ECC.
2367 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2368 struct mtd_oob_ops *ops)
2370 int chipnr, realpage, page, blockmask, column;
2371 struct nand_chip *chip = mtd->priv;
2372 uint32_t writelen = ops->len;
2374 uint32_t oobwritelen = ops->ooblen;
2375 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2376 mtd->oobavail : mtd->oobsize;
2378 uint8_t *oob = ops->oobbuf;
2379 uint8_t *buf = ops->datbuf;
2381 int oob_required = oob ? 1 : 0;
2387 /* Reject writes, which are not page aligned */
2388 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2389 pr_notice("%s: attempt to write non page aligned data\n",
2394 column = to & (mtd->writesize - 1);
2396 chipnr = (int)(to >> chip->chip_shift);
2397 chip->select_chip(mtd, chipnr);
2399 /* Check, if it is write protected */
2400 if (nand_check_wp(mtd)) {
2405 realpage = (int)(to >> chip->page_shift);
2406 page = realpage & chip->pagemask;
2407 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2409 /* Invalidate the page cache, when we write to the cached page */
2410 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2411 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2414 /* Don't allow multipage oob writes with offset */
2415 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2421 int bytes = mtd->writesize;
2422 int cached = writelen > bytes && page != blockmask;
2423 uint8_t *wbuf = buf;
2425 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2429 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2430 use_bufpoi = !virt_addr_valid(buf);
2434 /* Partial page write?, or need to use bounce buffer */
2436 pr_debug("%s: using write bounce buffer for buf@%p\n",
2440 bytes = min_t(int, bytes - column, writelen);
2442 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2443 memcpy(&chip->buffers->databuf[column], buf, bytes);
2444 wbuf = chip->buffers->databuf;
2447 if (unlikely(oob)) {
2448 size_t len = min(oobwritelen, oobmaxlen);
2449 oob = nand_fill_oob(mtd, oob, len, ops);
2452 /* We still need to erase leftover OOB data */
2453 memset(chip->oob_poi, 0xff, mtd->oobsize);
2455 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2456 oob_required, page, cached,
2457 (ops->mode == MTD_OPS_RAW));
2469 page = realpage & chip->pagemask;
2470 /* Check, if we cross a chip boundary */
2473 chip->select_chip(mtd, -1);
2474 chip->select_chip(mtd, chipnr);
2478 ops->retlen = ops->len - writelen;
2480 ops->oobretlen = ops->ooblen;
2483 chip->select_chip(mtd, -1);
2488 * panic_nand_write - [MTD Interface] NAND write with ECC
2489 * @mtd: MTD device structure
2490 * @to: offset to write to
2491 * @len: number of bytes to write
2492 * @retlen: pointer to variable to store the number of written bytes
2493 * @buf: the data to write
2495 * NAND write with ECC. Used when performing writes in interrupt context, this
2496 * may for example be called by mtdoops when writing an oops while in panic.
2498 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2499 size_t *retlen, const uint8_t *buf)
2501 struct nand_chip *chip = mtd->priv;
2502 struct mtd_oob_ops ops;
2505 /* Wait for the device to get ready */
2506 panic_nand_wait(mtd, chip, 400);
2508 /* Grab the device */
2509 panic_nand_get_device(chip, mtd, FL_WRITING);
2511 memset(&ops, 0, sizeof(ops));
2513 ops.datbuf = (uint8_t *)buf;
2514 ops.mode = MTD_OPS_PLACE_OOB;
2516 ret = nand_do_write_ops(mtd, to, &ops);
2518 *retlen = ops.retlen;
2523 * nand_write - [MTD Interface] NAND write with ECC
2524 * @mtd: MTD device structure
2525 * @to: offset to write to
2526 * @len: number of bytes to write
2527 * @retlen: pointer to variable to store the number of written bytes
2528 * @buf: the data to write
2530 * NAND write with ECC.
2532 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2533 size_t *retlen, const uint8_t *buf)
2535 struct mtd_oob_ops ops;
2538 nand_get_device(mtd, FL_WRITING);
2539 memset(&ops, 0, sizeof(ops));
2541 ops.datbuf = (uint8_t *)buf;
2542 ops.mode = MTD_OPS_PLACE_OOB;
2543 ret = nand_do_write_ops(mtd, to, &ops);
2544 *retlen = ops.retlen;
2545 nand_release_device(mtd);
2550 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2551 * @mtd: MTD device structure
2552 * @to: offset to write to
2553 * @ops: oob operation description structure
2555 * NAND write out-of-band.
2557 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2558 struct mtd_oob_ops *ops)
2560 int chipnr, page, status, len;
2561 struct nand_chip *chip = mtd->priv;
2563 pr_debug("%s: to = 0x%08x, len = %i\n",
2564 __func__, (unsigned int)to, (int)ops->ooblen);
2566 if (ops->mode == MTD_OPS_AUTO_OOB)
2567 len = chip->ecc.layout->oobavail;
2571 /* Do not allow write past end of page */
2572 if ((ops->ooboffs + ops->ooblen) > len) {
2573 pr_debug("%s: attempt to write past end of page\n",
2578 if (unlikely(ops->ooboffs >= len)) {
2579 pr_debug("%s: attempt to start write outside oob\n",
2584 /* Do not allow write past end of device */
2585 if (unlikely(to >= mtd->size ||
2586 ops->ooboffs + ops->ooblen >
2587 ((mtd->size >> chip->page_shift) -
2588 (to >> chip->page_shift)) * len)) {
2589 pr_debug("%s: attempt to write beyond end of device\n",
2594 chipnr = (int)(to >> chip->chip_shift);
2595 chip->select_chip(mtd, chipnr);
2597 /* Shift to get page */
2598 page = (int)(to >> chip->page_shift);
2601 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2602 * of my DiskOnChip 2000 test units) will clear the whole data page too
2603 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2604 * it in the doc2000 driver in August 1999. dwmw2.
2606 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2608 /* Check, if it is write protected */
2609 if (nand_check_wp(mtd)) {
2610 chip->select_chip(mtd, -1);
2614 /* Invalidate the page cache, if we write to the cached page */
2615 if (page == chip->pagebuf)
2618 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2620 if (ops->mode == MTD_OPS_RAW)
2621 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2623 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2625 chip->select_chip(mtd, -1);
2630 ops->oobretlen = ops->ooblen;
2636 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2637 * @mtd: MTD device structure
2638 * @to: offset to write to
2639 * @ops: oob operation description structure
2641 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2642 struct mtd_oob_ops *ops)
2644 int ret = -ENOTSUPP;
2648 /* Do not allow writes past end of device */
2649 if (ops->datbuf && (to + ops->len) > mtd->size) {
2650 pr_debug("%s: attempt to write beyond end of device\n",
2655 nand_get_device(mtd, FL_WRITING);
2657 switch (ops->mode) {
2658 case MTD_OPS_PLACE_OOB:
2659 case MTD_OPS_AUTO_OOB:
2668 ret = nand_do_write_oob(mtd, to, ops);
2670 ret = nand_do_write_ops(mtd, to, ops);
2673 nand_release_device(mtd);
2678 * single_erase - [GENERIC] NAND standard block erase command function
2679 * @mtd: MTD device structure
2680 * @page: the page address of the block which will be erased
2682 * Standard erase command for NAND chips. Returns NAND status.
2684 static int single_erase(struct mtd_info *mtd, int page)
2686 struct nand_chip *chip = mtd->priv;
2687 /* Send commands to erase a block */
2688 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2689 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2691 return chip->waitfunc(mtd, chip);
2695 * nand_erase - [MTD Interface] erase block(s)
2696 * @mtd: MTD device structure
2697 * @instr: erase instruction
2699 * Erase one ore more blocks.
2701 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2703 return nand_erase_nand(mtd, instr, 0);
2707 * nand_erase_nand - [INTERN] erase block(s)
2708 * @mtd: MTD device structure
2709 * @instr: erase instruction
2710 * @allowbbt: allow erasing the bbt area
2712 * Erase one ore more blocks.
2714 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2717 int page, status, pages_per_block, ret, chipnr;
2718 struct nand_chip *chip = mtd->priv;
2721 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2722 __func__, (unsigned long long)instr->addr,
2723 (unsigned long long)instr->len);
2725 if (check_offs_len(mtd, instr->addr, instr->len))
2728 /* Grab the lock and see if the device is available */
2729 nand_get_device(mtd, FL_ERASING);
2731 /* Shift to get first page */
2732 page = (int)(instr->addr >> chip->page_shift);
2733 chipnr = (int)(instr->addr >> chip->chip_shift);
2735 /* Calculate pages in each block */
2736 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2738 /* Select the NAND device */
2739 chip->select_chip(mtd, chipnr);
2741 /* Check, if it is write protected */
2742 if (nand_check_wp(mtd)) {
2743 pr_debug("%s: device is write protected!\n",
2745 instr->state = MTD_ERASE_FAILED;
2749 /* Loop through the pages */
2752 instr->state = MTD_ERASING;
2755 /* Check if we have a bad block, we do not erase bad blocks! */
2756 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2757 chip->page_shift, 0, allowbbt)) {
2758 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2760 instr->state = MTD_ERASE_FAILED;
2765 * Invalidate the page cache, if we erase the block which
2766 * contains the current cached page.
2768 if (page <= chip->pagebuf && chip->pagebuf <
2769 (page + pages_per_block))
2772 status = chip->erase(mtd, page & chip->pagemask);
2775 * See if operation failed and additional status checks are
2778 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2779 status = chip->errstat(mtd, chip, FL_ERASING,
2782 /* See if block erase succeeded */
2783 if (status & NAND_STATUS_FAIL) {
2784 pr_debug("%s: failed erase, page 0x%08x\n",
2786 instr->state = MTD_ERASE_FAILED;
2788 ((loff_t)page << chip->page_shift);
2792 /* Increment page address and decrement length */
2793 len -= (1ULL << chip->phys_erase_shift);
2794 page += pages_per_block;
2796 /* Check, if we cross a chip boundary */
2797 if (len && !(page & chip->pagemask)) {
2799 chip->select_chip(mtd, -1);
2800 chip->select_chip(mtd, chipnr);
2803 instr->state = MTD_ERASE_DONE;
2807 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2809 /* Deselect and wake up anyone waiting on the device */
2810 chip->select_chip(mtd, -1);
2811 nand_release_device(mtd);
2813 /* Do call back function */
2815 mtd_erase_callback(instr);
2817 /* Return more or less happy */
2822 * nand_sync - [MTD Interface] sync
2823 * @mtd: MTD device structure
2825 * Sync is actually a wait for chip ready function.
2827 static void nand_sync(struct mtd_info *mtd)
2829 pr_debug("%s: called\n", __func__);
2831 /* Grab the lock and see if the device is available */
2832 nand_get_device(mtd, FL_SYNCING);
2833 /* Release it and go back */
2834 nand_release_device(mtd);
2838 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2839 * @mtd: MTD device structure
2840 * @offs: offset relative to mtd start
2842 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2844 return nand_block_checkbad(mtd, offs, 1, 0);
2848 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2849 * @mtd: MTD device structure
2850 * @ofs: offset relative to mtd start
2852 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2856 ret = nand_block_isbad(mtd, ofs);
2858 /* If it was bad already, return success and do nothing */
2864 return nand_block_markbad_lowlevel(mtd, ofs);
2868 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2869 * @mtd: MTD device structure
2870 * @chip: nand chip info structure
2871 * @addr: feature address.
2872 * @subfeature_param: the subfeature parameters, a four bytes array.
2874 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2875 int addr, uint8_t *subfeature_param)
2880 if (!chip->onfi_version ||
2881 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2882 & ONFI_OPT_CMD_SET_GET_FEATURES))
2885 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2886 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2887 chip->write_byte(mtd, subfeature_param[i]);
2889 status = chip->waitfunc(mtd, chip);
2890 if (status & NAND_STATUS_FAIL)
2896 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2897 * @mtd: MTD device structure
2898 * @chip: nand chip info structure
2899 * @addr: feature address.
2900 * @subfeature_param: the subfeature parameters, a four bytes array.
2902 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2903 int addr, uint8_t *subfeature_param)
2907 if (!chip->onfi_version ||
2908 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2909 & ONFI_OPT_CMD_SET_GET_FEATURES))
2912 /* clear the sub feature parameters */
2913 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2915 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2916 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2917 *subfeature_param++ = chip->read_byte(mtd);
2922 * nand_suspend - [MTD Interface] Suspend the NAND flash
2923 * @mtd: MTD device structure
2925 static int nand_suspend(struct mtd_info *mtd)
2927 return nand_get_device(mtd, FL_PM_SUSPENDED);
2931 * nand_resume - [MTD Interface] Resume the NAND flash
2932 * @mtd: MTD device structure
2934 static void nand_resume(struct mtd_info *mtd)
2936 struct nand_chip *chip = mtd->priv;
2938 if (chip->state == FL_PM_SUSPENDED)
2939 nand_release_device(mtd);
2941 pr_err("%s called for a chip which is not in suspended state\n",
2946 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
2947 * prevent further operations
2948 * @mtd: MTD device structure
2950 static void nand_shutdown(struct mtd_info *mtd)
2952 nand_get_device(mtd, FL_SHUTDOWN);
2955 /* Set default functions */
2956 static void nand_set_defaults(struct nand_chip *chip, int busw)
2958 /* check for proper chip_delay setup, set 20us if not */
2959 if (!chip->chip_delay)
2960 chip->chip_delay = 20;
2962 /* check, if a user supplied command function given */
2963 if (chip->cmdfunc == NULL)
2964 chip->cmdfunc = nand_command;
2966 /* check, if a user supplied wait function given */
2967 if (chip->waitfunc == NULL)
2968 chip->waitfunc = nand_wait;
2970 if (!chip->select_chip)
2971 chip->select_chip = nand_select_chip;
2973 /* set for ONFI nand */
2974 if (!chip->onfi_set_features)
2975 chip->onfi_set_features = nand_onfi_set_features;
2976 if (!chip->onfi_get_features)
2977 chip->onfi_get_features = nand_onfi_get_features;
2979 /* If called twice, pointers that depend on busw may need to be reset */
2980 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2981 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2982 if (!chip->read_word)
2983 chip->read_word = nand_read_word;
2984 if (!chip->block_bad)
2985 chip->block_bad = nand_block_bad;
2986 if (!chip->block_markbad)
2987 chip->block_markbad = nand_default_block_markbad;
2988 if (!chip->write_buf || chip->write_buf == nand_write_buf)
2989 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2990 if (!chip->write_byte || chip->write_byte == nand_write_byte)
2991 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
2992 if (!chip->read_buf || chip->read_buf == nand_read_buf)
2993 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2994 if (!chip->scan_bbt)
2995 chip->scan_bbt = nand_default_bbt;
2997 if (!chip->controller) {
2998 chip->controller = &chip->hwcontrol;
2999 spin_lock_init(&chip->controller->lock);
3000 init_waitqueue_head(&chip->controller->wq);
3005 /* Sanitize ONFI strings so we can safely print them */
3006 static void sanitize_string(uint8_t *s, size_t len)
3010 /* Null terminate */
3013 /* Remove non printable chars */
3014 for (i = 0; i < len - 1; i++) {
3015 if (s[i] < ' ' || s[i] > 127)
3019 /* Remove trailing spaces */
3023 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3028 for (i = 0; i < 8; i++)
3029 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3035 /* Parse the Extended Parameter Page. */
3036 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3037 struct nand_chip *chip, struct nand_onfi_params *p)
3039 struct onfi_ext_param_page *ep;
3040 struct onfi_ext_section *s;
3041 struct onfi_ext_ecc_info *ecc;
3047 len = le16_to_cpu(p->ext_param_page_length) * 16;
3048 ep = kmalloc(len, GFP_KERNEL);
3052 /* Send our own NAND_CMD_PARAM. */
3053 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3055 /* Use the Change Read Column command to skip the ONFI param pages. */
3056 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3057 sizeof(*p) * p->num_of_param_pages , -1);
3059 /* Read out the Extended Parameter Page. */
3060 chip->read_buf(mtd, (uint8_t *)ep, len);
3061 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3062 != le16_to_cpu(ep->crc))) {
3063 pr_debug("fail in the CRC.\n");
3068 * Check the signature.
3069 * Do not strictly follow the ONFI spec, maybe changed in future.
3071 if (strncmp(ep->sig, "EPPS", 4)) {
3072 pr_debug("The signature is invalid.\n");
3076 /* find the ECC section. */
3077 cursor = (uint8_t *)(ep + 1);
3078 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3079 s = ep->sections + i;
3080 if (s->type == ONFI_SECTION_TYPE_2)
3082 cursor += s->length * 16;
3084 if (i == ONFI_EXT_SECTION_MAX) {
3085 pr_debug("We can not find the ECC section.\n");
3089 /* get the info we want. */
3090 ecc = (struct onfi_ext_ecc_info *)cursor;
3092 if (!ecc->codeword_size) {
3093 pr_debug("Invalid codeword size\n");
3097 chip->ecc_strength_ds = ecc->ecc_bits;
3098 chip->ecc_step_ds = 1 << ecc->codeword_size;
3106 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3108 struct nand_chip *chip = mtd->priv;
3109 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3111 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3116 * Configure chip properties from Micron vendor-specific ONFI table
3118 static void nand_onfi_detect_micron(struct nand_chip *chip,
3119 struct nand_onfi_params *p)
3121 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3123 if (le16_to_cpu(p->vendor_revision) < 1)
3126 chip->read_retries = micron->read_retry_options;
3127 chip->setup_read_retry = nand_setup_read_retry_micron;
3131 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3133 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3136 struct nand_onfi_params *p = &chip->onfi_params;
3140 /* Try ONFI for unknown chip or LP */
3141 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3142 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3143 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3146 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3147 for (i = 0; i < 3; i++) {
3148 for (j = 0; j < sizeof(*p); j++)
3149 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3150 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3151 le16_to_cpu(p->crc)) {
3157 pr_err("Could not find valid ONFI parameter page; aborting\n");
3162 val = le16_to_cpu(p->revision);
3164 chip->onfi_version = 23;
3165 else if (val & (1 << 4))
3166 chip->onfi_version = 22;
3167 else if (val & (1 << 3))
3168 chip->onfi_version = 21;
3169 else if (val & (1 << 2))
3170 chip->onfi_version = 20;
3171 else if (val & (1 << 1))
3172 chip->onfi_version = 10;
3174 if (!chip->onfi_version) {
3175 pr_info("unsupported ONFI version: %d\n", val);
3179 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3180 sanitize_string(p->model, sizeof(p->model));
3182 mtd->name = p->model;
3184 mtd->writesize = le32_to_cpu(p->byte_per_page);
3187 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3188 * (don't ask me who thought of this...). MTD assumes that these
3189 * dimensions will be power-of-2, so just truncate the remaining area.
3191 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3192 mtd->erasesize *= mtd->writesize;
3194 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3196 /* See erasesize comment */
3197 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3198 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3199 chip->bits_per_cell = p->bits_per_cell;
3201 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3202 *busw = NAND_BUSWIDTH_16;
3206 if (p->ecc_bits != 0xff) {
3207 chip->ecc_strength_ds = p->ecc_bits;
3208 chip->ecc_step_ds = 512;
3209 } else if (chip->onfi_version >= 21 &&
3210 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3213 * The nand_flash_detect_ext_param_page() uses the
3214 * Change Read Column command which maybe not supported
3215 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3216 * now. We do not replace user supplied command function.
3218 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3219 chip->cmdfunc = nand_command_lp;
3221 /* The Extended Parameter Page is supported since ONFI 2.1. */
3222 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3223 pr_warn("Failed to detect ONFI extended param page\n");
3225 pr_warn("Could not retrieve ONFI ECC requirements\n");
3228 if (p->jedec_id == NAND_MFR_MICRON)
3229 nand_onfi_detect_micron(chip, p);
3235 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3237 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3240 struct nand_jedec_params *p = &chip->jedec_params;
3241 struct jedec_ecc_info *ecc;
3245 /* Try JEDEC for unknown chip or LP */
3246 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3247 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3248 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3249 chip->read_byte(mtd) != 'C')
3252 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3253 for (i = 0; i < 3; i++) {
3254 for (j = 0; j < sizeof(*p); j++)
3255 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3257 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3258 le16_to_cpu(p->crc))
3263 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3268 val = le16_to_cpu(p->revision);
3270 chip->jedec_version = 10;
3271 else if (val & (1 << 1))
3272 chip->jedec_version = 1; /* vendor specific version */
3274 if (!chip->jedec_version) {
3275 pr_info("unsupported JEDEC version: %d\n", val);
3279 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3280 sanitize_string(p->model, sizeof(p->model));
3282 mtd->name = p->model;
3284 mtd->writesize = le32_to_cpu(p->byte_per_page);
3286 /* Please reference to the comment for nand_flash_detect_onfi. */
3287 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3288 mtd->erasesize *= mtd->writesize;
3290 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3292 /* Please reference to the comment for nand_flash_detect_onfi. */
3293 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3294 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3295 chip->bits_per_cell = p->bits_per_cell;
3297 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3298 *busw = NAND_BUSWIDTH_16;
3303 ecc = &p->ecc_info[0];
3305 if (ecc->codeword_size >= 9) {
3306 chip->ecc_strength_ds = ecc->ecc_bits;
3307 chip->ecc_step_ds = 1 << ecc->codeword_size;
3309 pr_warn("Invalid codeword size\n");
3316 * nand_id_has_period - Check if an ID string has a given wraparound period
3317 * @id_data: the ID string
3318 * @arrlen: the length of the @id_data array
3319 * @period: the period of repitition
3321 * Check if an ID string is repeated within a given sequence of bytes at
3322 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3323 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3324 * if the repetition has a period of @period; otherwise, returns zero.
3326 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3329 for (i = 0; i < period; i++)
3330 for (j = i + period; j < arrlen; j += period)
3331 if (id_data[i] != id_data[j])
3337 * nand_id_len - Get the length of an ID string returned by CMD_READID
3338 * @id_data: the ID string
3339 * @arrlen: the length of the @id_data array
3341 * Returns the length of the ID string, according to known wraparound/trailing
3342 * zero patterns. If no pattern exists, returns the length of the array.
3344 static int nand_id_len(u8 *id_data, int arrlen)
3346 int last_nonzero, period;
3348 /* Find last non-zero byte */
3349 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3350 if (id_data[last_nonzero])
3354 if (last_nonzero < 0)
3357 /* Calculate wraparound period */
3358 for (period = 1; period < arrlen; period++)
3359 if (nand_id_has_period(id_data, arrlen, period))
3362 /* There's a repeated pattern */
3363 if (period < arrlen)
3366 /* There are trailing zeros */
3367 if (last_nonzero < arrlen - 1)
3368 return last_nonzero + 1;
3370 /* No pattern detected */
3374 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3375 static int nand_get_bits_per_cell(u8 cellinfo)
3379 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3380 bits >>= NAND_CI_CELLTYPE_SHIFT;
3385 * Many new NAND share similar device ID codes, which represent the size of the
3386 * chip. The rest of the parameters must be decoded according to generic or
3387 * manufacturer-specific "extended ID" decoding patterns.
3389 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3390 u8 id_data[8], int *busw)
3393 /* The 3rd id byte holds MLC / multichip data */
3394 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3395 /* The 4th id byte is the important one */
3398 id_len = nand_id_len(id_data, 8);
3401 * Field definitions are in the following datasheets:
3402 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3403 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3404 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3406 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3407 * ID to decide what to do.
3409 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3410 !nand_is_slc(chip) && id_data[5] != 0x00) {
3412 mtd->writesize = 2048 << (extid & 0x03);
3415 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3435 default: /* Other cases are "reserved" (unknown) */
3436 mtd->oobsize = 1024;
3440 /* Calc blocksize */
3441 mtd->erasesize = (128 * 1024) <<
3442 (((extid >> 1) & 0x04) | (extid & 0x03));
3444 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3445 !nand_is_slc(chip)) {
3449 mtd->writesize = 2048 << (extid & 0x03);
3452 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3476 /* Calc blocksize */
3477 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3479 mtd->erasesize = (128 * 1024) << tmp;
3480 else if (tmp == 0x03)
3481 mtd->erasesize = 768 * 1024;
3483 mtd->erasesize = (64 * 1024) << tmp;
3487 mtd->writesize = 1024 << (extid & 0x03);
3490 mtd->oobsize = (8 << (extid & 0x01)) *
3491 (mtd->writesize >> 9);
3493 /* Calc blocksize. Blocksize is multiples of 64KiB */
3494 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3496 /* Get buswidth information */
3497 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3500 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3501 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3503 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3505 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3507 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3508 nand_is_slc(chip) &&
3509 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3510 !(id_data[4] & 0x80) /* !BENAND */) {
3511 mtd->oobsize = 32 * mtd->writesize >> 9;
3518 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3519 * decodes a matching ID table entry and assigns the MTD size parameters for
3522 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3523 struct nand_flash_dev *type, u8 id_data[8],
3526 int maf_id = id_data[0];
3528 mtd->erasesize = type->erasesize;
3529 mtd->writesize = type->pagesize;
3530 mtd->oobsize = mtd->writesize / 32;
3531 *busw = type->options & NAND_BUSWIDTH_16;
3533 /* All legacy ID NAND are small-page, SLC */
3534 chip->bits_per_cell = 1;
3537 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3538 * some Spansion chips have erasesize that conflicts with size
3539 * listed in nand_ids table.
3540 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3542 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3543 && id_data[6] == 0x00 && id_data[7] == 0x00
3544 && mtd->writesize == 512) {
3545 mtd->erasesize = 128 * 1024;
3546 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3551 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3552 * heuristic patterns using various detected parameters (e.g., manufacturer,
3553 * page size, cell-type information).
3555 static void nand_decode_bbm_options(struct mtd_info *mtd,
3556 struct nand_chip *chip, u8 id_data[8])
3558 int maf_id = id_data[0];
3560 /* Set the bad block position */
3561 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3562 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3564 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3567 * Bad block marker is stored in the last page of each block on Samsung
3568 * and Hynix MLC devices; stored in first two pages of each block on
3569 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3570 * AMD/Spansion, and Macronix. All others scan only the first page.
3572 if (!nand_is_slc(chip) &&
3573 (maf_id == NAND_MFR_SAMSUNG ||
3574 maf_id == NAND_MFR_HYNIX))
3575 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3576 else if ((nand_is_slc(chip) &&
3577 (maf_id == NAND_MFR_SAMSUNG ||
3578 maf_id == NAND_MFR_HYNIX ||
3579 maf_id == NAND_MFR_TOSHIBA ||
3580 maf_id == NAND_MFR_AMD ||
3581 maf_id == NAND_MFR_MACRONIX)) ||
3582 (mtd->writesize == 2048 &&
3583 maf_id == NAND_MFR_MICRON))
3584 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3587 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3589 return type->id_len;
3592 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3593 struct nand_flash_dev *type, u8 *id_data, int *busw)
3595 if (!strncmp(type->id, id_data, type->id_len)) {
3596 mtd->writesize = type->pagesize;
3597 mtd->erasesize = type->erasesize;
3598 mtd->oobsize = type->oobsize;
3600 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3601 chip->chipsize = (uint64_t)type->chipsize << 20;
3602 chip->options |= type->options;
3603 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3604 chip->ecc_step_ds = NAND_ECC_STEP(type);
3605 chip->onfi_timing_mode_default =
3606 type->onfi_timing_mode_default;
3608 *busw = type->options & NAND_BUSWIDTH_16;
3611 mtd->name = type->name;
3619 * Get the flash and manufacturer id and lookup if the type is supported.
3621 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3622 struct nand_chip *chip,
3623 int *maf_id, int *dev_id,
3624 struct nand_flash_dev *type)
3630 /* Select the device */
3631 chip->select_chip(mtd, 0);
3634 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3637 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3639 /* Send the command for reading device ID */
3640 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3642 /* Read manufacturer and device IDs */
3643 *maf_id = chip->read_byte(mtd);
3644 *dev_id = chip->read_byte(mtd);
3647 * Try again to make sure, as some systems the bus-hold or other
3648 * interface concerns can cause random data which looks like a
3649 * possibly credible NAND flash to appear. If the two results do
3650 * not match, ignore the device completely.
3653 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3655 /* Read entire ID string */
3656 for (i = 0; i < 8; i++)
3657 id_data[i] = chip->read_byte(mtd);
3659 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3660 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3661 *maf_id, *dev_id, id_data[0], id_data[1]);
3662 return ERR_PTR(-ENODEV);
3666 type = nand_flash_ids;
3668 for (; type->name != NULL; type++) {
3669 if (is_full_id_nand(type)) {
3670 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3672 } else if (*dev_id == type->dev_id) {
3677 chip->onfi_version = 0;
3678 if (!type->name || !type->pagesize) {
3679 /* Check if the chip is ONFI compliant */
3680 if (nand_flash_detect_onfi(mtd, chip, &busw))
3683 /* Check if the chip is JEDEC compliant */
3684 if (nand_flash_detect_jedec(mtd, chip, &busw))
3689 return ERR_PTR(-ENODEV);
3692 mtd->name = type->name;
3694 chip->chipsize = (uint64_t)type->chipsize << 20;
3696 if (!type->pagesize && chip->init_size) {
3697 /* Set the pagesize, oobsize, erasesize by the driver */
3698 busw = chip->init_size(mtd, chip, id_data);
3699 } else if (!type->pagesize) {
3700 /* Decode parameters from extended ID */
3701 nand_decode_ext_id(mtd, chip, id_data, &busw);
3703 nand_decode_id(mtd, chip, type, id_data, &busw);
3705 /* Get chip options */
3706 chip->options |= type->options;
3709 * Check if chip is not a Samsung device. Do not clear the
3710 * options for chips which do not have an extended id.
3712 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3713 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3716 /* Try to identify manufacturer */
3717 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3718 if (nand_manuf_ids[maf_idx].id == *maf_id)
3722 if (chip->options & NAND_BUSWIDTH_AUTO) {
3723 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3724 chip->options |= busw;
3725 nand_set_defaults(chip, busw);
3726 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3728 * Check, if buswidth is correct. Hardware drivers should set
3731 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3733 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3734 pr_warn("bus width %d instead %d bit\n",
3735 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3737 return ERR_PTR(-EINVAL);
3740 nand_decode_bbm_options(mtd, chip, id_data);
3742 /* Calculate the address shift from the page size */
3743 chip->page_shift = ffs(mtd->writesize) - 1;
3744 /* Convert chipsize to number of pages per chip -1 */
3745 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3747 chip->bbt_erase_shift = chip->phys_erase_shift =
3748 ffs(mtd->erasesize) - 1;
3749 if (chip->chipsize & 0xffffffff)
3750 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3752 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3753 chip->chip_shift += 32 - 1;
3756 chip->badblockbits = 8;
3757 chip->erase = single_erase;
3759 /* Do not replace user supplied command function! */
3760 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3761 chip->cmdfunc = nand_command_lp;
3763 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3766 if (chip->onfi_version)
3767 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3768 chip->onfi_params.model);
3769 else if (chip->jedec_version)
3770 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3771 chip->jedec_params.model);
3773 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3776 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3777 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3778 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3783 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3784 * @mtd: MTD device structure
3785 * @maxchips: number of chips to scan for
3786 * @table: alternative NAND ID table
3788 * This is the first phase of the normal nand_scan() function. It reads the
3789 * flash ID and sets up MTD fields accordingly.
3791 * The mtd->owner field must be set to the module of the caller.
3793 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3794 struct nand_flash_dev *table)
3796 int i, nand_maf_id, nand_dev_id;
3797 struct nand_chip *chip = mtd->priv;
3798 struct nand_flash_dev *type;
3800 /* Set the default functions */
3801 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3803 /* Read the flash type */
3804 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3805 &nand_dev_id, table);
3808 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3809 pr_warn("No NAND device found\n");
3810 chip->select_chip(mtd, -1);
3811 return PTR_ERR(type);
3814 chip->select_chip(mtd, -1);
3816 /* Check for a chip array */
3817 for (i = 1; i < maxchips; i++) {
3818 chip->select_chip(mtd, i);
3819 /* See comment in nand_get_flash_type for reset */
3820 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3821 /* Send the command for reading device ID */
3822 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3823 /* Read manufacturer and device IDs */
3824 if (nand_maf_id != chip->read_byte(mtd) ||
3825 nand_dev_id != chip->read_byte(mtd)) {
3826 chip->select_chip(mtd, -1);
3829 chip->select_chip(mtd, -1);
3832 pr_info("%d chips detected\n", i);
3834 /* Store the number of chips and calc total size for mtd */
3836 mtd->size = i * chip->chipsize;
3840 EXPORT_SYMBOL(nand_scan_ident);
3843 * Check if the chip configuration meet the datasheet requirements.
3845 * If our configuration corrects A bits per B bytes and the minimum
3846 * required correction level is X bits per Y bytes, then we must ensure
3847 * both of the following are true:
3849 * (1) A / B >= X / Y
3852 * Requirement (1) ensures we can correct for the required bitflip density.
3853 * Requirement (2) ensures we can correct even when all bitflips are clumped
3854 * in the same sector.
3856 static bool nand_ecc_strength_good(struct mtd_info *mtd)
3858 struct nand_chip *chip = mtd->priv;
3859 struct nand_ecc_ctrl *ecc = &chip->ecc;
3862 if (ecc->size == 0 || chip->ecc_step_ds == 0)
3863 /* Not enough information */
3867 * We get the number of corrected bits per page to compare
3868 * the correction density.
3870 corr = (mtd->writesize * ecc->strength) / ecc->size;
3871 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3873 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3877 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3878 * @mtd: MTD device structure
3880 * This is the second phase of the normal nand_scan() function. It fills out
3881 * all the uninitialized function pointers with the defaults and scans for a
3882 * bad block table if appropriate.
3884 int nand_scan_tail(struct mtd_info *mtd)
3887 struct nand_chip *chip = mtd->priv;
3888 struct nand_ecc_ctrl *ecc = &chip->ecc;
3889 struct nand_buffers *nbuf;
3891 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3892 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3893 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3895 if (!(chip->options & NAND_OWN_BUFFERS)) {
3896 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3897 + mtd->oobsize * 3, GFP_KERNEL);
3900 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3901 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3902 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3904 chip->buffers = nbuf;
3910 /* Set the internal oob buffer location, just after the page data */
3911 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3914 * If no default placement scheme is given, select an appropriate one.
3916 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3917 switch (mtd->oobsize) {
3919 ecc->layout = &nand_oob_8;
3922 ecc->layout = &nand_oob_16;
3925 ecc->layout = &nand_oob_64;
3928 ecc->layout = &nand_oob_128;
3931 pr_warn("No oob scheme defined for oobsize %d\n",
3937 if (!chip->write_page)
3938 chip->write_page = nand_write_page;
3941 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3942 * selected and we have 256 byte pagesize fallback to software ECC
3945 switch (ecc->mode) {
3946 case NAND_ECC_HW_OOB_FIRST:
3947 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3948 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3949 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3952 if (!ecc->read_page)
3953 ecc->read_page = nand_read_page_hwecc_oob_first;
3956 /* Use standard hwecc read page function? */
3957 if (!ecc->read_page)
3958 ecc->read_page = nand_read_page_hwecc;
3959 if (!ecc->write_page)
3960 ecc->write_page = nand_write_page_hwecc;
3961 if (!ecc->read_page_raw)
3962 ecc->read_page_raw = nand_read_page_raw;
3963 if (!ecc->write_page_raw)
3964 ecc->write_page_raw = nand_write_page_raw;
3966 ecc->read_oob = nand_read_oob_std;
3967 if (!ecc->write_oob)
3968 ecc->write_oob = nand_write_oob_std;
3969 if (!ecc->read_subpage)
3970 ecc->read_subpage = nand_read_subpage;
3971 if (!ecc->write_subpage)
3972 ecc->write_subpage = nand_write_subpage_hwecc;
3974 case NAND_ECC_HW_SYNDROME:
3975 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
3977 ecc->read_page == nand_read_page_hwecc ||
3979 ecc->write_page == nand_write_page_hwecc)) {
3980 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
3983 /* Use standard syndrome read/write page function? */
3984 if (!ecc->read_page)
3985 ecc->read_page = nand_read_page_syndrome;
3986 if (!ecc->write_page)
3987 ecc->write_page = nand_write_page_syndrome;
3988 if (!ecc->read_page_raw)
3989 ecc->read_page_raw = nand_read_page_raw_syndrome;
3990 if (!ecc->write_page_raw)
3991 ecc->write_page_raw = nand_write_page_raw_syndrome;
3993 ecc->read_oob = nand_read_oob_syndrome;
3994 if (!ecc->write_oob)
3995 ecc->write_oob = nand_write_oob_syndrome;
3997 if (mtd->writesize >= ecc->size) {
3998 if (!ecc->strength) {
3999 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4004 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4005 ecc->size, mtd->writesize);
4006 ecc->mode = NAND_ECC_SOFT;
4009 ecc->calculate = nand_calculate_ecc;
4010 ecc->correct = nand_correct_data;
4011 ecc->read_page = nand_read_page_swecc;
4012 ecc->read_subpage = nand_read_subpage;
4013 ecc->write_page = nand_write_page_swecc;
4014 ecc->read_page_raw = nand_read_page_raw;
4015 ecc->write_page_raw = nand_write_page_raw;
4016 ecc->read_oob = nand_read_oob_std;
4017 ecc->write_oob = nand_write_oob_std;
4024 case NAND_ECC_SOFT_BCH:
4025 if (!mtd_nand_has_bch()) {
4026 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4029 ecc->calculate = nand_bch_calculate_ecc;
4030 ecc->correct = nand_bch_correct_data;
4031 ecc->read_page = nand_read_page_swecc;
4032 ecc->read_subpage = nand_read_subpage;
4033 ecc->write_page = nand_write_page_swecc;
4034 ecc->read_page_raw = nand_read_page_raw;
4035 ecc->write_page_raw = nand_write_page_raw;
4036 ecc->read_oob = nand_read_oob_std;
4037 ecc->write_oob = nand_write_oob_std;
4039 * Board driver should supply ecc.size and ecc.strength values
4040 * to select how many bits are correctable. Otherwise, default
4041 * to 4 bits for large page devices.
4043 if (!ecc->size && (mtd->oobsize >= 64)) {
4048 /* See nand_bch_init() for details. */
4049 ecc->bytes = DIV_ROUND_UP(
4050 ecc->strength * fls(8 * ecc->size), 8);
4051 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4054 pr_warn("BCH ECC initialization failed!\n");
4060 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4061 ecc->read_page = nand_read_page_raw;
4062 ecc->write_page = nand_write_page_raw;
4063 ecc->read_oob = nand_read_oob_std;
4064 ecc->read_page_raw = nand_read_page_raw;
4065 ecc->write_page_raw = nand_write_page_raw;
4066 ecc->write_oob = nand_write_oob_std;
4067 ecc->size = mtd->writesize;
4073 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4077 /* For many systems, the standard OOB write also works for raw */
4078 if (!ecc->read_oob_raw)
4079 ecc->read_oob_raw = ecc->read_oob;
4080 if (!ecc->write_oob_raw)
4081 ecc->write_oob_raw = ecc->write_oob;
4084 * The number of bytes available for a client to place data into
4085 * the out of band area.
4087 ecc->layout->oobavail = 0;
4088 for (i = 0; ecc->layout->oobfree[i].length
4089 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4090 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4091 mtd->oobavail = ecc->layout->oobavail;
4093 /* ECC sanity check: warn if it's too weak */
4094 if (!nand_ecc_strength_good(mtd))
4095 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4099 * Set the number of read / write steps for one page depending on ECC
4102 ecc->steps = mtd->writesize / ecc->size;
4103 if (ecc->steps * ecc->size != mtd->writesize) {
4104 pr_warn("Invalid ECC parameters\n");
4107 ecc->total = ecc->steps * ecc->bytes;
4109 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4110 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4111 switch (ecc->steps) {
4113 mtd->subpage_sft = 1;
4118 mtd->subpage_sft = 2;
4122 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4124 /* Initialize state */
4125 chip->state = FL_READY;
4127 /* Invalidate the pagebuffer reference */
4130 /* Large page NAND with SOFT_ECC should support subpage reads */
4131 switch (ecc->mode) {
4133 case NAND_ECC_SOFT_BCH:
4134 if (chip->page_shift > 9)
4135 chip->options |= NAND_SUBPAGE_READ;
4142 /* Fill in remaining MTD driver data */
4143 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4144 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4146 mtd->_erase = nand_erase;
4148 mtd->_unpoint = NULL;
4149 mtd->_read = nand_read;
4150 mtd->_write = nand_write;
4151 mtd->_panic_write = panic_nand_write;
4152 mtd->_read_oob = nand_read_oob;
4153 mtd->_write_oob = nand_write_oob;
4154 mtd->_sync = nand_sync;
4156 mtd->_unlock = NULL;
4157 mtd->_suspend = nand_suspend;
4158 mtd->_resume = nand_resume;
4159 mtd->_reboot = nand_shutdown;
4160 mtd->_block_isreserved = nand_block_isreserved;
4161 mtd->_block_isbad = nand_block_isbad;
4162 mtd->_block_markbad = nand_block_markbad;
4163 mtd->writebufsize = mtd->writesize;
4165 /* propagate ecc info to mtd_info */
4166 mtd->ecclayout = ecc->layout;
4167 mtd->ecc_strength = ecc->strength;
4168 mtd->ecc_step_size = ecc->size;
4170 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4171 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4174 if (!mtd->bitflip_threshold)
4175 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4177 /* Check, if we should skip the bad block table scan */
4178 if (chip->options & NAND_SKIP_BBTSCAN)
4181 /* Build bad block table */
4182 return chip->scan_bbt(mtd);
4184 EXPORT_SYMBOL(nand_scan_tail);
4187 * is_module_text_address() isn't exported, and it's mostly a pointless
4188 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4189 * to call us from in-kernel code if the core NAND support is modular.
4192 #define caller_is_module() (1)
4194 #define caller_is_module() \
4195 is_module_text_address((unsigned long)__builtin_return_address(0))
4199 * nand_scan - [NAND Interface] Scan for the NAND device
4200 * @mtd: MTD device structure
4201 * @maxchips: number of chips to scan for
4203 * This fills out all the uninitialized function pointers with the defaults.
4204 * The flash ID is read and the mtd/chip structures are filled with the
4205 * appropriate values. The mtd->owner field must be set to the module of the
4208 int nand_scan(struct mtd_info *mtd, int maxchips)
4212 /* Many callers got this wrong, so check for it for a while... */
4213 if (!mtd->owner && caller_is_module()) {
4214 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4218 ret = nand_scan_ident(mtd, maxchips, NULL);
4220 ret = nand_scan_tail(mtd);
4223 EXPORT_SYMBOL(nand_scan);
4226 * nand_release - [NAND Interface] Free resources held by the NAND device
4227 * @mtd: MTD device structure
4229 void nand_release(struct mtd_info *mtd)
4231 struct nand_chip *chip = mtd->priv;
4233 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4234 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4236 mtd_device_unregister(mtd);
4238 /* Free bad block table memory */
4240 if (!(chip->options & NAND_OWN_BUFFERS))
4241 kfree(chip->buffers);
4243 /* Free bad block descriptor memory */
4244 if (chip->badblock_pattern && chip->badblock_pattern->options
4245 & NAND_BBT_DYNAMICSTRUCT)
4246 kfree(chip->badblock_pattern);
4248 EXPORT_SYMBOL_GPL(nand_release);
4250 static int __init nand_base_init(void)
4252 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4256 static void __exit nand_base_exit(void)
4258 led_trigger_unregister_simple(nand_led_trigger);
4261 module_init(nand_base_init);
4262 module_exit(nand_base_exit);
4264 MODULE_LICENSE("GPL");
4265 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4266 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4267 MODULE_DESCRIPTION("Generic NAND flash driver code");