3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
46 #include <linux/leds.h>
48 #include <linux/mtd/partitions.h>
49 #include <linux/of_mtd.h>
51 /* Define default oob placement schemes for large and small page devices */
52 static struct nand_ecclayout nand_oob_8 = {
62 static struct nand_ecclayout nand_oob_16 = {
64 .eccpos = {0, 1, 2, 3, 6, 7},
70 static struct nand_ecclayout nand_oob_64 = {
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
81 static struct nand_ecclayout nand_oob_128 = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
95 static int nand_get_device(struct mtd_info *mtd, int new_state);
97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
101 * For devices which display every fart in the system on a separate LED. Is
102 * compiled away when LED support is disabled.
104 DEFINE_LED_TRIGGER(nand_led_trigger);
106 static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
109 struct nand_chip *chip = mtd->priv;
112 /* Start address must align on block boundary */
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
114 pr_debug("%s: unaligned address\n", __func__);
118 /* Length must align on block boundary */
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
120 pr_debug("%s: length not block aligned\n", __func__);
128 * nand_release_device - [GENERIC] release chip
129 * @mtd: MTD device structure
131 * Release chip lock and wake up anyone waiting on the device.
133 static void nand_release_device(struct mtd_info *mtd)
135 struct nand_chip *chip = mtd->priv;
137 /* Release the controller and the chip */
138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
146 * nand_read_byte - [DEFAULT] read one byte from the chip
147 * @mtd: MTD device structure
149 * Default read function for 8bit buswidth
151 static uint8_t nand_read_byte(struct mtd_info *mtd)
153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
159 * @mtd: MTD device structure
161 * Default read function for 16bit buswidth with endianness conversion.
164 static uint8_t nand_read_byte16(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
167 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
171 * nand_read_word - [DEFAULT] read one word from the chip
172 * @mtd: MTD device structure
174 * Default read function for 16bit buswidth without endianness conversion.
176 static u16 nand_read_word(struct mtd_info *mtd)
178 struct nand_chip *chip = mtd->priv;
179 return readw(chip->IO_ADDR_R);
183 * nand_select_chip - [DEFAULT] control CE line
184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
187 * Default select function for 1 chip devices.
189 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
191 struct nand_chip *chip = mtd->priv;
195 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
210 * Default function to write a byte to I/O[7:0]
212 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
214 struct nand_chip *chip = mtd->priv;
216 chip->write_buf(mtd, &byte, 1);
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
228 struct nand_chip *chip = mtd->priv;
229 uint16_t word = byte;
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
247 chip->write_buf(mtd, (uint8_t *)&word, 2);
251 * nand_write_buf - [DEFAULT] write buffer to chip
252 * @mtd: MTD device structure
254 * @len: number of bytes to write
256 * Default write function for 8bit buswidth.
258 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 iowrite8_rep(chip->IO_ADDR_W, buf, len);
266 * nand_read_buf - [DEFAULT] read chip data into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
271 * Default read function for 8bit buswidth.
273 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
277 ioread8_rep(chip->IO_ADDR_R, buf, len);
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 * Default write function for 16bit buswidth.
288 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
290 struct nand_chip *chip = mtd->priv;
291 u16 *p = (u16 *) buf;
293 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
302 * Default read function for 16bit buswidth.
304 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
309 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
318 * Check, if the block is bad.
320 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
322 int page, chipnr, res = 0, i = 0;
323 struct nand_chip *chip = mtd->priv;
326 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
327 ofs += mtd->erasesize - mtd->writesize;
329 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
332 chipnr = (int)(ofs >> chip->chip_shift);
334 nand_get_device(mtd, FL_READING);
336 /* Select the NAND device */
337 chip->select_chip(mtd, chipnr);
341 if (chip->options & NAND_BUSWIDTH_16) {
342 chip->cmdfunc(mtd, NAND_CMD_READOOB,
343 chip->badblockpos & 0xFE, page);
344 bad = cpu_to_le16(chip->read_word(mtd));
345 if (chip->badblockpos & 0x1)
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
352 bad = chip->read_byte(mtd);
355 if (likely(chip->badblockbits == 8))
358 res = hweight8(bad) < chip->badblockbits;
359 ofs += mtd->writesize;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
362 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
365 chip->select_chip(mtd, -1);
366 nand_release_device(mtd);
373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
374 * @mtd: MTD device structure
375 * @ofs: offset from device start
377 * This is the default implementation, which can be overridden by a hardware
378 * specific driver. It provides the details for writing a bad block marker to a
381 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
383 struct nand_chip *chip = mtd->priv;
384 struct mtd_oob_ops ops;
385 uint8_t buf[2] = { 0, 0 };
386 int ret = 0, res, i = 0;
388 memset(&ops, 0, sizeof(ops));
390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
395 ops.len = ops.ooblen = 1;
397 ops.mode = MTD_OPS_PLACE_OOB;
399 /* Write to first/last page(s) if necessary */
400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 ofs += mtd->erasesize - mtd->writesize;
403 res = nand_do_write_oob(mtd, ofs, &ops);
408 ofs += mtd->writesize;
409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
423 * We try operations in the following order:
424 * (1) erase the affected block, to allow OOB marker to be written cleanly
425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
428 * Note that we retain the first error encountered in (2) or (3), finish the
429 * procedures, and dump the error in the end.
431 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
433 struct nand_chip *chip = mtd->priv;
436 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
437 struct erase_info einfo;
439 /* Attempt erase before marking OOB */
440 memset(&einfo, 0, sizeof(einfo));
443 einfo.len = 1ULL << chip->phys_erase_shift;
444 nand_erase_nand(mtd, &einfo, 0);
446 /* Write bad block marker to OOB */
447 nand_get_device(mtd, FL_WRITING);
448 ret = chip->block_markbad(mtd, ofs);
449 nand_release_device(mtd);
452 /* Mark block bad in BBT */
454 res = nand_markbad_bbt(mtd, ofs);
460 mtd->ecc_stats.badblocks++;
466 * nand_check_wp - [GENERIC] check if the chip is write protected
467 * @mtd: MTD device structure
469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
472 static int nand_check_wp(struct mtd_info *mtd)
474 struct nand_chip *chip = mtd->priv;
476 /* Broken xD cards report WP despite being writable */
477 if (chip->options & NAND_BROKEN_XD)
480 /* Check the WP bit */
481 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
482 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
487 * @mtd: MTD device structure
488 * @ofs: offset from device start
490 * Check if the block is marked as reserved.
492 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
494 struct nand_chip *chip = mtd->priv;
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd, ofs);
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
512 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
515 struct nand_chip *chip = mtd->priv;
518 return chip->block_bad(mtd, ofs, getchip);
520 /* Return info from the table */
521 return nand_isbad_bbt(mtd, ofs, allowbbt);
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
526 * @mtd: MTD device structure
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
532 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
534 struct nand_chip *chip = mtd->priv;
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
541 touch_softlockup_watchdog();
546 /* Wait for the ready pin, after a command. The timeout is caught later. */
547 void nand_wait_ready(struct mtd_info *mtd)
549 struct nand_chip *chip = mtd->priv;
550 unsigned long timeo = jiffies + msecs_to_jiffies(20);
553 if (in_interrupt() || oops_in_progress)
554 return panic_nand_wait_ready(mtd, 400);
556 led_trigger_event(nand_led_trigger, LED_FULL);
557 /* Wait until command is processed or timeout occurs */
559 if (chip->dev_ready(mtd))
561 touch_softlockup_watchdog();
562 } while (time_before(jiffies, timeo));
563 led_trigger_event(nand_led_trigger, LED_OFF);
565 EXPORT_SYMBOL_GPL(nand_wait_ready);
568 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
569 * @mtd: MTD device structure
570 * @timeo: Timeout in ms
572 * Wait for status ready (i.e. command done) or timeout.
574 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
576 register struct nand_chip *chip = mtd->priv;
578 timeo = jiffies + msecs_to_jiffies(timeo);
580 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
582 touch_softlockup_watchdog();
583 } while (time_before(jiffies, timeo));
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info *mtd, unsigned int command,
597 int column, int page_addr)
599 register struct nand_chip *chip = mtd->priv;
600 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
602 /* Write out the command to the device */
603 if (command == NAND_CMD_SEQIN) {
606 if (column >= mtd->writesize) {
608 column -= mtd->writesize;
609 readcmd = NAND_CMD_READOOB;
610 } else if (column < 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd = NAND_CMD_READ0;
615 readcmd = NAND_CMD_READ1;
617 chip->cmd_ctrl(mtd, readcmd, ctrl);
618 ctrl &= ~NAND_CTRL_CHANGE;
620 chip->cmd_ctrl(mtd, command, ctrl);
622 /* Address cycle, when necessary */
623 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip->options & NAND_BUSWIDTH_16 &&
628 !nand_opcode_8bits(command))
630 chip->cmd_ctrl(mtd, column, ctrl);
631 ctrl &= ~NAND_CTRL_CHANGE;
633 if (page_addr != -1) {
634 chip->cmd_ctrl(mtd, page_addr, ctrl);
635 ctrl &= ~NAND_CTRL_CHANGE;
636 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
637 /* One more address cycle for devices > 32MiB */
638 if (chip->chipsize > (32 << 20))
639 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
641 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
644 * Program and erase have their own busy handlers status and sequential
649 case NAND_CMD_PAGEPROG:
650 case NAND_CMD_ERASE1:
651 case NAND_CMD_ERASE2:
653 case NAND_CMD_STATUS:
659 udelay(chip->chip_delay);
660 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
661 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
663 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
664 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
665 nand_wait_status_ready(mtd, 250);
668 /* This applies to read commands */
671 * If we don't have access to the busy pin, we apply the given
674 if (!chip->dev_ready) {
675 udelay(chip->chip_delay);
680 * Apply this short delay always to ensure that we do wait tWB in
681 * any case on any machine.
685 nand_wait_ready(mtd);
689 * nand_command_lp - [DEFAULT] Send command to NAND large page device
690 * @mtd: MTD device structure
691 * @command: the command to be sent
692 * @column: the column address for this command, -1 if none
693 * @page_addr: the page address for this command, -1 if none
695 * Send command to NAND device. This is the version for the new large page
696 * devices. We don't have the separate regions as we have in the small page
697 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
699 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
700 int column, int page_addr)
702 register struct nand_chip *chip = mtd->priv;
704 /* Emulate NAND_CMD_READOOB */
705 if (command == NAND_CMD_READOOB) {
706 column += mtd->writesize;
707 command = NAND_CMD_READ0;
710 /* Command latch cycle */
711 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
713 if (column != -1 || page_addr != -1) {
714 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
716 /* Serially input address */
718 /* Adjust columns for 16 bit buswidth */
719 if (chip->options & NAND_BUSWIDTH_16 &&
720 !nand_opcode_8bits(command))
722 chip->cmd_ctrl(mtd, column, ctrl);
723 ctrl &= ~NAND_CTRL_CHANGE;
724 chip->cmd_ctrl(mtd, column >> 8, ctrl);
726 if (page_addr != -1) {
727 chip->cmd_ctrl(mtd, page_addr, ctrl);
728 chip->cmd_ctrl(mtd, page_addr >> 8,
729 NAND_NCE | NAND_ALE);
730 /* One more address cycle for devices > 128MiB */
731 if (chip->chipsize > (128 << 20))
732 chip->cmd_ctrl(mtd, page_addr >> 16,
733 NAND_NCE | NAND_ALE);
736 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
739 * Program and erase have their own busy handlers status, sequential
740 * in and status need no delay.
744 case NAND_CMD_CACHEDPROG:
745 case NAND_CMD_PAGEPROG:
746 case NAND_CMD_ERASE1:
747 case NAND_CMD_ERASE2:
750 case NAND_CMD_STATUS:
756 udelay(chip->chip_delay);
757 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
758 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
759 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
760 NAND_NCE | NAND_CTRL_CHANGE);
761 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
762 nand_wait_status_ready(mtd, 250);
765 case NAND_CMD_RNDOUT:
766 /* No ready / busy check necessary */
767 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
768 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
769 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
770 NAND_NCE | NAND_CTRL_CHANGE);
774 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
775 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
776 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
777 NAND_NCE | NAND_CTRL_CHANGE);
779 /* This applies to read commands */
782 * If we don't have access to the busy pin, we apply the given
785 if (!chip->dev_ready) {
786 udelay(chip->chip_delay);
792 * Apply this short delay always to ensure that we do wait tWB in
793 * any case on any machine.
797 nand_wait_ready(mtd);
801 * panic_nand_get_device - [GENERIC] Get chip for selected access
802 * @chip: the nand chip descriptor
803 * @mtd: MTD device structure
804 * @new_state: the state which is requested
806 * Used when in panic, no locks are taken.
808 static void panic_nand_get_device(struct nand_chip *chip,
809 struct mtd_info *mtd, int new_state)
811 /* Hardware controller shared among independent devices */
812 chip->controller->active = chip;
813 chip->state = new_state;
817 * nand_get_device - [GENERIC] Get chip for selected access
818 * @mtd: MTD device structure
819 * @new_state: the state which is requested
821 * Get the device and lock it for exclusive access
824 nand_get_device(struct mtd_info *mtd, int new_state)
826 struct nand_chip *chip = mtd->priv;
827 spinlock_t *lock = &chip->controller->lock;
828 wait_queue_head_t *wq = &chip->controller->wq;
829 DECLARE_WAITQUEUE(wait, current);
833 /* Hardware controller shared among independent devices */
834 if (!chip->controller->active)
835 chip->controller->active = chip;
837 if (chip->controller->active == chip && chip->state == FL_READY) {
838 chip->state = new_state;
842 if (new_state == FL_PM_SUSPENDED) {
843 if (chip->controller->active->state == FL_PM_SUSPENDED) {
844 chip->state = FL_PM_SUSPENDED;
849 set_current_state(TASK_UNINTERRUPTIBLE);
850 add_wait_queue(wq, &wait);
853 remove_wait_queue(wq, &wait);
858 * panic_nand_wait - [GENERIC] wait until the command is done
859 * @mtd: MTD device structure
860 * @chip: NAND chip structure
863 * Wait for command done. This is a helper function for nand_wait used when
864 * we are in interrupt context. May happen when in panic and trying to write
865 * an oops through mtdoops.
867 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
871 for (i = 0; i < timeo; i++) {
872 if (chip->dev_ready) {
873 if (chip->dev_ready(mtd))
876 if (chip->read_byte(mtd) & NAND_STATUS_READY)
884 * nand_wait - [DEFAULT] wait until the command is done
885 * @mtd: MTD device structure
886 * @chip: NAND chip structure
888 * Wait for command done. This applies to erase and program only. Erase can
889 * take up to 400ms and program up to 20ms according to general NAND and
892 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
895 int status, state = chip->state;
896 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
898 led_trigger_event(nand_led_trigger, LED_FULL);
901 * Apply this short delay always to ensure that we do wait tWB in any
902 * case on any machine.
906 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
908 if (in_interrupt() || oops_in_progress)
909 panic_nand_wait(mtd, chip, timeo);
911 timeo = jiffies + msecs_to_jiffies(timeo);
912 while (time_before(jiffies, timeo)) {
913 if (chip->dev_ready) {
914 if (chip->dev_ready(mtd))
917 if (chip->read_byte(mtd) & NAND_STATUS_READY)
923 led_trigger_event(nand_led_trigger, LED_OFF);
925 status = (int)chip->read_byte(mtd);
926 /* This can happen if in case of timeout or buggy dev_ready */
927 WARN_ON(!(status & NAND_STATUS_READY));
932 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
934 * @ofs: offset to start unlock from
935 * @len: length to unlock
936 * @invert: when = 0, unlock the range of blocks within the lower and
937 * upper boundary address
938 * when = 1, unlock the range of blocks outside the boundaries
939 * of the lower and upper boundary address
941 * Returs unlock status.
943 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
944 uint64_t len, int invert)
948 struct nand_chip *chip = mtd->priv;
950 /* Submit address of first page to unlock */
951 page = ofs >> chip->page_shift;
952 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
954 /* Submit address of last page to unlock */
955 page = (ofs + len) >> chip->page_shift;
956 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
957 (page | invert) & chip->pagemask);
959 /* Call wait ready function */
960 status = chip->waitfunc(mtd, chip);
961 /* See if device thinks it succeeded */
962 if (status & NAND_STATUS_FAIL) {
963 pr_debug("%s: error status = 0x%08x\n",
972 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
974 * @ofs: offset to start unlock from
975 * @len: length to unlock
977 * Returns unlock status.
979 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
983 struct nand_chip *chip = mtd->priv;
985 pr_debug("%s: start = 0x%012llx, len = %llu\n",
986 __func__, (unsigned long long)ofs, len);
988 if (check_offs_len(mtd, ofs, len))
991 /* Align to last block address if size addresses end of the device */
992 if (ofs + len == mtd->size)
993 len -= mtd->erasesize;
995 nand_get_device(mtd, FL_UNLOCKING);
997 /* Shift to get chip number */
998 chipnr = ofs >> chip->chip_shift;
1000 chip->select_chip(mtd, chipnr);
1004 * If we want to check the WP through READ STATUS and check the bit 7
1005 * we must reset the chip
1006 * some operation can also clear the bit 7 of status register
1007 * eg. erase/program a locked block
1009 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1011 /* Check, if it is write protected */
1012 if (nand_check_wp(mtd)) {
1013 pr_debug("%s: device is write protected!\n",
1019 ret = __nand_unlock(mtd, ofs, len, 0);
1022 chip->select_chip(mtd, -1);
1023 nand_release_device(mtd);
1027 EXPORT_SYMBOL(nand_unlock);
1030 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1032 * @ofs: offset to start unlock from
1033 * @len: length to unlock
1035 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1036 * have this feature, but it allows only to lock all blocks, not for specified
1037 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1040 * Returns lock status.
1042 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1045 int chipnr, status, page;
1046 struct nand_chip *chip = mtd->priv;
1048 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1049 __func__, (unsigned long long)ofs, len);
1051 if (check_offs_len(mtd, ofs, len))
1054 nand_get_device(mtd, FL_LOCKING);
1056 /* Shift to get chip number */
1057 chipnr = ofs >> chip->chip_shift;
1059 chip->select_chip(mtd, chipnr);
1063 * If we want to check the WP through READ STATUS and check the bit 7
1064 * we must reset the chip
1065 * some operation can also clear the bit 7 of status register
1066 * eg. erase/program a locked block
1068 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1070 /* Check, if it is write protected */
1071 if (nand_check_wp(mtd)) {
1072 pr_debug("%s: device is write protected!\n",
1074 status = MTD_ERASE_FAILED;
1079 /* Submit address of first page to lock */
1080 page = ofs >> chip->page_shift;
1081 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1083 /* Call wait ready function */
1084 status = chip->waitfunc(mtd, chip);
1085 /* See if device thinks it succeeded */
1086 if (status & NAND_STATUS_FAIL) {
1087 pr_debug("%s: error status = 0x%08x\n",
1093 ret = __nand_unlock(mtd, ofs, len, 0x1);
1096 chip->select_chip(mtd, -1);
1097 nand_release_device(mtd);
1101 EXPORT_SYMBOL(nand_lock);
1104 * nand_read_page_raw - [INTERN] read raw page data without ecc
1105 * @mtd: mtd info structure
1106 * @chip: nand chip info structure
1107 * @buf: buffer to store read data
1108 * @oob_required: caller requires OOB data read to chip->oob_poi
1109 * @page: page number to read
1111 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1113 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1114 uint8_t *buf, int oob_required, int page)
1116 chip->read_buf(mtd, buf, mtd->writesize);
1118 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1123 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1124 * @mtd: mtd info structure
1125 * @chip: nand chip info structure
1126 * @buf: buffer to store read data
1127 * @oob_required: caller requires OOB data read to chip->oob_poi
1128 * @page: page number to read
1130 * We need a special oob layout and handling even when OOB isn't used.
1132 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1133 struct nand_chip *chip, uint8_t *buf,
1134 int oob_required, int page)
1136 int eccsize = chip->ecc.size;
1137 int eccbytes = chip->ecc.bytes;
1138 uint8_t *oob = chip->oob_poi;
1141 for (steps = chip->ecc.steps; steps > 0; steps--) {
1142 chip->read_buf(mtd, buf, eccsize);
1145 if (chip->ecc.prepad) {
1146 chip->read_buf(mtd, oob, chip->ecc.prepad);
1147 oob += chip->ecc.prepad;
1150 chip->read_buf(mtd, oob, eccbytes);
1153 if (chip->ecc.postpad) {
1154 chip->read_buf(mtd, oob, chip->ecc.postpad);
1155 oob += chip->ecc.postpad;
1159 size = mtd->oobsize - (oob - chip->oob_poi);
1161 chip->read_buf(mtd, oob, size);
1167 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1168 * @mtd: mtd info structure
1169 * @chip: nand chip info structure
1170 * @buf: buffer to store read data
1171 * @oob_required: caller requires OOB data read to chip->oob_poi
1172 * @page: page number to read
1174 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1175 uint8_t *buf, int oob_required, int page)
1177 int i, eccsize = chip->ecc.size;
1178 int eccbytes = chip->ecc.bytes;
1179 int eccsteps = chip->ecc.steps;
1181 uint8_t *ecc_calc = chip->buffers->ecccalc;
1182 uint8_t *ecc_code = chip->buffers->ecccode;
1183 uint32_t *eccpos = chip->ecc.layout->eccpos;
1184 unsigned int max_bitflips = 0;
1186 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1188 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1189 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1191 for (i = 0; i < chip->ecc.total; i++)
1192 ecc_code[i] = chip->oob_poi[eccpos[i]];
1194 eccsteps = chip->ecc.steps;
1197 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1200 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1202 mtd->ecc_stats.failed++;
1204 mtd->ecc_stats.corrected += stat;
1205 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1208 return max_bitflips;
1212 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1213 * @mtd: mtd info structure
1214 * @chip: nand chip info structure
1215 * @data_offs: offset of requested data within the page
1216 * @readlen: data length
1217 * @bufpoi: buffer to store read data
1218 * @page: page number to read
1220 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1221 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1224 int start_step, end_step, num_steps;
1225 uint32_t *eccpos = chip->ecc.layout->eccpos;
1227 int data_col_addr, i, gaps = 0;
1228 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1229 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1231 unsigned int max_bitflips = 0;
1233 /* Column address within the page aligned to ECC size (256bytes) */
1234 start_step = data_offs / chip->ecc.size;
1235 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1236 num_steps = end_step - start_step + 1;
1237 index = start_step * chip->ecc.bytes;
1239 /* Data size aligned to ECC ecc.size */
1240 datafrag_len = num_steps * chip->ecc.size;
1241 eccfrag_len = num_steps * chip->ecc.bytes;
1243 data_col_addr = start_step * chip->ecc.size;
1244 /* If we read not a page aligned data */
1245 if (data_col_addr != 0)
1246 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1248 p = bufpoi + data_col_addr;
1249 chip->read_buf(mtd, p, datafrag_len);
1252 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1253 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1256 * The performance is faster if we position offsets according to
1257 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1259 for (i = 0; i < eccfrag_len - 1; i++) {
1260 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1266 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1267 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1270 * Send the command to read the particular ECC bytes take care
1271 * about buswidth alignment in read_buf.
1273 aligned_pos = eccpos[index] & ~(busw - 1);
1274 aligned_len = eccfrag_len;
1275 if (eccpos[index] & (busw - 1))
1277 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1280 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1281 mtd->writesize + aligned_pos, -1);
1282 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1285 for (i = 0; i < eccfrag_len; i++)
1286 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1288 p = bufpoi + data_col_addr;
1289 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1292 stat = chip->ecc.correct(mtd, p,
1293 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1295 mtd->ecc_stats.failed++;
1297 mtd->ecc_stats.corrected += stat;
1298 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1301 return max_bitflips;
1305 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1306 * @mtd: mtd info structure
1307 * @chip: nand chip info structure
1308 * @buf: buffer to store read data
1309 * @oob_required: caller requires OOB data read to chip->oob_poi
1310 * @page: page number to read
1312 * Not for syndrome calculating ECC controllers which need a special oob layout.
1314 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1315 uint8_t *buf, int oob_required, int page)
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1321 uint8_t *ecc_calc = chip->buffers->ecccalc;
1322 uint8_t *ecc_code = chip->buffers->ecccode;
1323 uint32_t *eccpos = chip->ecc.layout->eccpos;
1324 unsigned int max_bitflips = 0;
1326 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1329 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1331 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1333 for (i = 0; i < chip->ecc.total; i++)
1334 ecc_code[i] = chip->oob_poi[eccpos[i]];
1336 eccsteps = chip->ecc.steps;
1339 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1342 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1344 mtd->ecc_stats.failed++;
1346 mtd->ecc_stats.corrected += stat;
1347 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1350 return max_bitflips;
1354 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1355 * @mtd: mtd info structure
1356 * @chip: nand chip info structure
1357 * @buf: buffer to store read data
1358 * @oob_required: caller requires OOB data read to chip->oob_poi
1359 * @page: page number to read
1361 * Hardware ECC for large page chips, require OOB to be read first. For this
1362 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1363 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1364 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1365 * the data area, by overwriting the NAND manufacturer bad block markings.
1367 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1368 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1370 int i, eccsize = chip->ecc.size;
1371 int eccbytes = chip->ecc.bytes;
1372 int eccsteps = chip->ecc.steps;
1374 uint8_t *ecc_code = chip->buffers->ecccode;
1375 uint32_t *eccpos = chip->ecc.layout->eccpos;
1376 uint8_t *ecc_calc = chip->buffers->ecccalc;
1377 unsigned int max_bitflips = 0;
1379 /* Read the OOB area first */
1380 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1381 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1382 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1384 for (i = 0; i < chip->ecc.total; i++)
1385 ecc_code[i] = chip->oob_poi[eccpos[i]];
1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1392 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1394 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1396 mtd->ecc_stats.failed++;
1398 mtd->ecc_stats.corrected += stat;
1399 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1402 return max_bitflips;
1406 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1407 * @mtd: mtd info structure
1408 * @chip: nand chip info structure
1409 * @buf: buffer to store read data
1410 * @oob_required: caller requires OOB data read to chip->oob_poi
1411 * @page: page number to read
1413 * The hw generator calculates the error syndrome automatically. Therefore we
1414 * need a special oob layout and handling.
1416 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1417 uint8_t *buf, int oob_required, int page)
1419 int i, eccsize = chip->ecc.size;
1420 int eccbytes = chip->ecc.bytes;
1421 int eccsteps = chip->ecc.steps;
1423 uint8_t *oob = chip->oob_poi;
1424 unsigned int max_bitflips = 0;
1426 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1429 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1430 chip->read_buf(mtd, p, eccsize);
1432 if (chip->ecc.prepad) {
1433 chip->read_buf(mtd, oob, chip->ecc.prepad);
1434 oob += chip->ecc.prepad;
1437 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1438 chip->read_buf(mtd, oob, eccbytes);
1439 stat = chip->ecc.correct(mtd, p, oob, NULL);
1442 mtd->ecc_stats.failed++;
1444 mtd->ecc_stats.corrected += stat;
1445 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1450 if (chip->ecc.postpad) {
1451 chip->read_buf(mtd, oob, chip->ecc.postpad);
1452 oob += chip->ecc.postpad;
1456 /* Calculate remaining oob bytes */
1457 i = mtd->oobsize - (oob - chip->oob_poi);
1459 chip->read_buf(mtd, oob, i);
1461 return max_bitflips;
1465 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1466 * @chip: nand chip structure
1467 * @oob: oob destination address
1468 * @ops: oob ops structure
1469 * @len: size of oob to transfer
1471 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1472 struct mtd_oob_ops *ops, size_t len)
1474 switch (ops->mode) {
1476 case MTD_OPS_PLACE_OOB:
1478 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1481 case MTD_OPS_AUTO_OOB: {
1482 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1483 uint32_t boffs = 0, roffs = ops->ooboffs;
1486 for (; free->length && len; free++, len -= bytes) {
1487 /* Read request not from offset 0? */
1488 if (unlikely(roffs)) {
1489 if (roffs >= free->length) {
1490 roffs -= free->length;
1493 boffs = free->offset + roffs;
1494 bytes = min_t(size_t, len,
1495 (free->length - roffs));
1498 bytes = min_t(size_t, len, free->length);
1499 boffs = free->offset;
1501 memcpy(oob, chip->oob_poi + boffs, bytes);
1513 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1514 * @mtd: MTD device structure
1515 * @retry_mode: the retry mode to use
1517 * Some vendors supply a special command to shift the Vt threshold, to be used
1518 * when there are too many bitflips in a page (i.e., ECC error). After setting
1519 * a new threshold, the host should retry reading the page.
1521 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1523 struct nand_chip *chip = mtd->priv;
1525 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1527 if (retry_mode >= chip->read_retries)
1530 if (!chip->setup_read_retry)
1533 return chip->setup_read_retry(mtd, retry_mode);
1537 * nand_do_read_ops - [INTERN] Read data with ECC
1538 * @mtd: MTD device structure
1539 * @from: offset to read from
1540 * @ops: oob ops structure
1542 * Internal function. Called with chip held.
1544 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1545 struct mtd_oob_ops *ops)
1547 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1548 struct nand_chip *chip = mtd->priv;
1550 uint32_t readlen = ops->len;
1551 uint32_t oobreadlen = ops->ooblen;
1552 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1553 mtd->oobavail : mtd->oobsize;
1555 uint8_t *bufpoi, *oob, *buf;
1557 unsigned int max_bitflips = 0;
1559 bool ecc_fail = false;
1561 chipnr = (int)(from >> chip->chip_shift);
1562 chip->select_chip(mtd, chipnr);
1564 realpage = (int)(from >> chip->page_shift);
1565 page = realpage & chip->pagemask;
1567 col = (int)(from & (mtd->writesize - 1));
1571 oob_required = oob ? 1 : 0;
1574 unsigned int ecc_failures = mtd->ecc_stats.failed;
1576 bytes = min(mtd->writesize - col, readlen);
1577 aligned = (bytes == mtd->writesize);
1581 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1582 use_bufpoi = !virt_addr_valid(buf);
1586 /* Is the current page in the buffer? */
1587 if (realpage != chip->pagebuf || oob) {
1588 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1590 if (use_bufpoi && aligned)
1591 pr_debug("%s: using read bounce buffer for buf@%p\n",
1595 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1598 * Now read the page into the buffer. Absent an error,
1599 * the read methods return max bitflips per ecc step.
1601 if (unlikely(ops->mode == MTD_OPS_RAW))
1602 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1605 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1607 ret = chip->ecc.read_subpage(mtd, chip,
1611 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1612 oob_required, page);
1615 /* Invalidate page cache */
1620 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1622 /* Transfer not aligned data */
1624 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1625 !(mtd->ecc_stats.failed - ecc_failures) &&
1626 (ops->mode != MTD_OPS_RAW)) {
1627 chip->pagebuf = realpage;
1628 chip->pagebuf_bitflips = ret;
1630 /* Invalidate page cache */
1633 memcpy(buf, chip->buffers->databuf + col, bytes);
1636 if (unlikely(oob)) {
1637 int toread = min(oobreadlen, max_oobsize);
1640 oob = nand_transfer_oob(chip,
1642 oobreadlen -= toread;
1646 if (chip->options & NAND_NEED_READRDY) {
1647 /* Apply delay or wait for ready/busy pin */
1648 if (!chip->dev_ready)
1649 udelay(chip->chip_delay);
1651 nand_wait_ready(mtd);
1654 if (mtd->ecc_stats.failed - ecc_failures) {
1655 if (retry_mode + 1 < chip->read_retries) {
1657 ret = nand_setup_read_retry(mtd,
1662 /* Reset failures; retry */
1663 mtd->ecc_stats.failed = ecc_failures;
1666 /* No more retry modes; real failure */
1673 memcpy(buf, chip->buffers->databuf + col, bytes);
1675 max_bitflips = max_t(unsigned int, max_bitflips,
1676 chip->pagebuf_bitflips);
1681 /* Reset to retry mode 0 */
1683 ret = nand_setup_read_retry(mtd, 0);
1692 /* For subsequent reads align to page boundary */
1694 /* Increment page address */
1697 page = realpage & chip->pagemask;
1698 /* Check, if we cross a chip boundary */
1701 chip->select_chip(mtd, -1);
1702 chip->select_chip(mtd, chipnr);
1705 chip->select_chip(mtd, -1);
1707 ops->retlen = ops->len - (size_t) readlen;
1709 ops->oobretlen = ops->ooblen - oobreadlen;
1717 return max_bitflips;
1721 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1722 * @mtd: MTD device structure
1723 * @from: offset to read from
1724 * @len: number of bytes to read
1725 * @retlen: pointer to variable to store the number of read bytes
1726 * @buf: the databuffer to put data
1728 * Get hold of the chip and call nand_do_read.
1730 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1731 size_t *retlen, uint8_t *buf)
1733 struct mtd_oob_ops ops;
1736 nand_get_device(mtd, FL_READING);
1737 memset(&ops, 0, sizeof(ops));
1740 ops.mode = MTD_OPS_PLACE_OOB;
1741 ret = nand_do_read_ops(mtd, from, &ops);
1742 *retlen = ops.retlen;
1743 nand_release_device(mtd);
1748 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1749 * @mtd: mtd info structure
1750 * @chip: nand chip info structure
1751 * @page: page number to read
1753 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1756 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1757 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1762 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1764 * @mtd: mtd info structure
1765 * @chip: nand chip info structure
1766 * @page: page number to read
1768 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1771 int length = mtd->oobsize;
1772 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1773 int eccsize = chip->ecc.size;
1774 uint8_t *bufpoi = chip->oob_poi;
1775 int i, toread, sndrnd = 0, pos;
1777 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1778 for (i = 0; i < chip->ecc.steps; i++) {
1780 pos = eccsize + i * (eccsize + chunk);
1781 if (mtd->writesize > 512)
1782 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1784 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1787 toread = min_t(int, length, chunk);
1788 chip->read_buf(mtd, bufpoi, toread);
1793 chip->read_buf(mtd, bufpoi, length);
1799 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1800 * @mtd: mtd info structure
1801 * @chip: nand chip info structure
1802 * @page: page number to write
1804 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1808 const uint8_t *buf = chip->oob_poi;
1809 int length = mtd->oobsize;
1811 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1812 chip->write_buf(mtd, buf, length);
1813 /* Send command to program the OOB data */
1814 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1816 status = chip->waitfunc(mtd, chip);
1818 return status & NAND_STATUS_FAIL ? -EIO : 0;
1822 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1823 * with syndrome - only for large page flash
1824 * @mtd: mtd info structure
1825 * @chip: nand chip info structure
1826 * @page: page number to write
1828 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1829 struct nand_chip *chip, int page)
1831 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1832 int eccsize = chip->ecc.size, length = mtd->oobsize;
1833 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1834 const uint8_t *bufpoi = chip->oob_poi;
1837 * data-ecc-data-ecc ... ecc-oob
1839 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1841 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1842 pos = steps * (eccsize + chunk);
1847 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1848 for (i = 0; i < steps; i++) {
1850 if (mtd->writesize <= 512) {
1851 uint32_t fill = 0xFFFFFFFF;
1855 int num = min_t(int, len, 4);
1856 chip->write_buf(mtd, (uint8_t *)&fill,
1861 pos = eccsize + i * (eccsize + chunk);
1862 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1866 len = min_t(int, length, chunk);
1867 chip->write_buf(mtd, bufpoi, len);
1872 chip->write_buf(mtd, bufpoi, length);
1874 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1875 status = chip->waitfunc(mtd, chip);
1877 return status & NAND_STATUS_FAIL ? -EIO : 0;
1881 * nand_do_read_oob - [INTERN] NAND read out-of-band
1882 * @mtd: MTD device structure
1883 * @from: offset to read from
1884 * @ops: oob operations description structure
1886 * NAND read out-of-band data from the spare area.
1888 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1889 struct mtd_oob_ops *ops)
1891 int page, realpage, chipnr;
1892 struct nand_chip *chip = mtd->priv;
1893 struct mtd_ecc_stats stats;
1894 int readlen = ops->ooblen;
1896 uint8_t *buf = ops->oobbuf;
1899 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1900 __func__, (unsigned long long)from, readlen);
1902 stats = mtd->ecc_stats;
1904 if (ops->mode == MTD_OPS_AUTO_OOB)
1905 len = chip->ecc.layout->oobavail;
1909 if (unlikely(ops->ooboffs >= len)) {
1910 pr_debug("%s: attempt to start read outside oob\n",
1915 /* Do not allow reads past end of device */
1916 if (unlikely(from >= mtd->size ||
1917 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1918 (from >> chip->page_shift)) * len)) {
1919 pr_debug("%s: attempt to read beyond end of device\n",
1924 chipnr = (int)(from >> chip->chip_shift);
1925 chip->select_chip(mtd, chipnr);
1927 /* Shift to get page */
1928 realpage = (int)(from >> chip->page_shift);
1929 page = realpage & chip->pagemask;
1932 if (ops->mode == MTD_OPS_RAW)
1933 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1935 ret = chip->ecc.read_oob(mtd, chip, page);
1940 len = min(len, readlen);
1941 buf = nand_transfer_oob(chip, buf, ops, len);
1943 if (chip->options & NAND_NEED_READRDY) {
1944 /* Apply delay or wait for ready/busy pin */
1945 if (!chip->dev_ready)
1946 udelay(chip->chip_delay);
1948 nand_wait_ready(mtd);
1955 /* Increment page address */
1958 page = realpage & chip->pagemask;
1959 /* Check, if we cross a chip boundary */
1962 chip->select_chip(mtd, -1);
1963 chip->select_chip(mtd, chipnr);
1966 chip->select_chip(mtd, -1);
1968 ops->oobretlen = ops->ooblen - readlen;
1973 if (mtd->ecc_stats.failed - stats.failed)
1976 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1980 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1981 * @mtd: MTD device structure
1982 * @from: offset to read from
1983 * @ops: oob operation description structure
1985 * NAND read data and/or out-of-band data.
1987 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1988 struct mtd_oob_ops *ops)
1990 int ret = -ENOTSUPP;
1994 /* Do not allow reads past end of device */
1995 if (ops->datbuf && (from + ops->len) > mtd->size) {
1996 pr_debug("%s: attempt to read beyond end of device\n",
2001 nand_get_device(mtd, FL_READING);
2003 switch (ops->mode) {
2004 case MTD_OPS_PLACE_OOB:
2005 case MTD_OPS_AUTO_OOB:
2014 ret = nand_do_read_oob(mtd, from, ops);
2016 ret = nand_do_read_ops(mtd, from, ops);
2019 nand_release_device(mtd);
2025 * nand_write_page_raw - [INTERN] raw page write function
2026 * @mtd: mtd info structure
2027 * @chip: nand chip info structure
2029 * @oob_required: must write chip->oob_poi to OOB
2031 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2033 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2034 const uint8_t *buf, int oob_required)
2036 chip->write_buf(mtd, buf, mtd->writesize);
2038 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2044 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2045 * @mtd: mtd info structure
2046 * @chip: nand chip info structure
2048 * @oob_required: must write chip->oob_poi to OOB
2050 * We need a special oob layout and handling even when ECC isn't checked.
2052 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2053 struct nand_chip *chip,
2054 const uint8_t *buf, int oob_required)
2056 int eccsize = chip->ecc.size;
2057 int eccbytes = chip->ecc.bytes;
2058 uint8_t *oob = chip->oob_poi;
2061 for (steps = chip->ecc.steps; steps > 0; steps--) {
2062 chip->write_buf(mtd, buf, eccsize);
2065 if (chip->ecc.prepad) {
2066 chip->write_buf(mtd, oob, chip->ecc.prepad);
2067 oob += chip->ecc.prepad;
2070 chip->write_buf(mtd, oob, eccbytes);
2073 if (chip->ecc.postpad) {
2074 chip->write_buf(mtd, oob, chip->ecc.postpad);
2075 oob += chip->ecc.postpad;
2079 size = mtd->oobsize - (oob - chip->oob_poi);
2081 chip->write_buf(mtd, oob, size);
2086 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2087 * @mtd: mtd info structure
2088 * @chip: nand chip info structure
2090 * @oob_required: must write chip->oob_poi to OOB
2092 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2093 const uint8_t *buf, int oob_required)
2095 int i, eccsize = chip->ecc.size;
2096 int eccbytes = chip->ecc.bytes;
2097 int eccsteps = chip->ecc.steps;
2098 uint8_t *ecc_calc = chip->buffers->ecccalc;
2099 const uint8_t *p = buf;
2100 uint32_t *eccpos = chip->ecc.layout->eccpos;
2102 /* Software ECC calculation */
2103 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2104 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2106 for (i = 0; i < chip->ecc.total; i++)
2107 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2109 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2113 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2114 * @mtd: mtd info structure
2115 * @chip: nand chip info structure
2117 * @oob_required: must write chip->oob_poi to OOB
2119 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2120 const uint8_t *buf, int oob_required)
2122 int i, eccsize = chip->ecc.size;
2123 int eccbytes = chip->ecc.bytes;
2124 int eccsteps = chip->ecc.steps;
2125 uint8_t *ecc_calc = chip->buffers->ecccalc;
2126 const uint8_t *p = buf;
2127 uint32_t *eccpos = chip->ecc.layout->eccpos;
2129 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2130 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2131 chip->write_buf(mtd, p, eccsize);
2132 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2135 for (i = 0; i < chip->ecc.total; i++)
2136 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2138 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2145 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2146 * @mtd: mtd info structure
2147 * @chip: nand chip info structure
2148 * @offset: column address of subpage within the page
2149 * @data_len: data length
2151 * @oob_required: must write chip->oob_poi to OOB
2153 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2154 struct nand_chip *chip, uint32_t offset,
2155 uint32_t data_len, const uint8_t *buf,
2158 uint8_t *oob_buf = chip->oob_poi;
2159 uint8_t *ecc_calc = chip->buffers->ecccalc;
2160 int ecc_size = chip->ecc.size;
2161 int ecc_bytes = chip->ecc.bytes;
2162 int ecc_steps = chip->ecc.steps;
2163 uint32_t *eccpos = chip->ecc.layout->eccpos;
2164 uint32_t start_step = offset / ecc_size;
2165 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2166 int oob_bytes = mtd->oobsize / ecc_steps;
2169 for (step = 0; step < ecc_steps; step++) {
2170 /* configure controller for WRITE access */
2171 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2173 /* write data (untouched subpages already masked by 0xFF) */
2174 chip->write_buf(mtd, buf, ecc_size);
2176 /* mask ECC of un-touched subpages by padding 0xFF */
2177 if ((step < start_step) || (step > end_step))
2178 memset(ecc_calc, 0xff, ecc_bytes);
2180 chip->ecc.calculate(mtd, buf, ecc_calc);
2182 /* mask OOB of un-touched subpages by padding 0xFF */
2183 /* if oob_required, preserve OOB metadata of written subpage */
2184 if (!oob_required || (step < start_step) || (step > end_step))
2185 memset(oob_buf, 0xff, oob_bytes);
2188 ecc_calc += ecc_bytes;
2189 oob_buf += oob_bytes;
2192 /* copy calculated ECC for whole page to chip->buffer->oob */
2193 /* this include masked-value(0xFF) for unwritten subpages */
2194 ecc_calc = chip->buffers->ecccalc;
2195 for (i = 0; i < chip->ecc.total; i++)
2196 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2198 /* write OOB buffer to NAND device */
2199 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2206 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2207 * @mtd: mtd info structure
2208 * @chip: nand chip info structure
2210 * @oob_required: must write chip->oob_poi to OOB
2212 * The hw generator calculates the error syndrome automatically. Therefore we
2213 * need a special oob layout and handling.
2215 static int nand_write_page_syndrome(struct mtd_info *mtd,
2216 struct nand_chip *chip,
2217 const uint8_t *buf, int oob_required)
2219 int i, eccsize = chip->ecc.size;
2220 int eccbytes = chip->ecc.bytes;
2221 int eccsteps = chip->ecc.steps;
2222 const uint8_t *p = buf;
2223 uint8_t *oob = chip->oob_poi;
2225 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2227 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2228 chip->write_buf(mtd, p, eccsize);
2230 if (chip->ecc.prepad) {
2231 chip->write_buf(mtd, oob, chip->ecc.prepad);
2232 oob += chip->ecc.prepad;
2235 chip->ecc.calculate(mtd, p, oob);
2236 chip->write_buf(mtd, oob, eccbytes);
2239 if (chip->ecc.postpad) {
2240 chip->write_buf(mtd, oob, chip->ecc.postpad);
2241 oob += chip->ecc.postpad;
2245 /* Calculate remaining oob bytes */
2246 i = mtd->oobsize - (oob - chip->oob_poi);
2248 chip->write_buf(mtd, oob, i);
2254 * nand_write_page - [REPLACEABLE] write one page
2255 * @mtd: MTD device structure
2256 * @chip: NAND chip descriptor
2257 * @offset: address offset within the page
2258 * @data_len: length of actual data to be written
2259 * @buf: the data to write
2260 * @oob_required: must write chip->oob_poi to OOB
2261 * @page: page number to write
2262 * @cached: cached programming
2263 * @raw: use _raw version of write_page
2265 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2266 uint32_t offset, int data_len, const uint8_t *buf,
2267 int oob_required, int page, int cached, int raw)
2269 int status, subpage;
2271 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2272 chip->ecc.write_subpage)
2273 subpage = offset || (data_len < mtd->writesize);
2277 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2280 status = chip->ecc.write_page_raw(mtd, chip, buf,
2283 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2286 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2292 * Cached progamming disabled for now. Not sure if it's worth the
2293 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2297 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2299 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2300 status = chip->waitfunc(mtd, chip);
2302 * See if operation failed and additional status checks are
2305 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2306 status = chip->errstat(mtd, chip, FL_WRITING, status,
2309 if (status & NAND_STATUS_FAIL)
2312 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2313 status = chip->waitfunc(mtd, chip);
2320 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2321 * @mtd: MTD device structure
2322 * @oob: oob data buffer
2323 * @len: oob data write length
2324 * @ops: oob ops structure
2326 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2327 struct mtd_oob_ops *ops)
2329 struct nand_chip *chip = mtd->priv;
2332 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2333 * data from a previous OOB read.
2335 memset(chip->oob_poi, 0xff, mtd->oobsize);
2337 switch (ops->mode) {
2339 case MTD_OPS_PLACE_OOB:
2341 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2344 case MTD_OPS_AUTO_OOB: {
2345 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2346 uint32_t boffs = 0, woffs = ops->ooboffs;
2349 for (; free->length && len; free++, len -= bytes) {
2350 /* Write request not from offset 0? */
2351 if (unlikely(woffs)) {
2352 if (woffs >= free->length) {
2353 woffs -= free->length;
2356 boffs = free->offset + woffs;
2357 bytes = min_t(size_t, len,
2358 (free->length - woffs));
2361 bytes = min_t(size_t, len, free->length);
2362 boffs = free->offset;
2364 memcpy(chip->oob_poi + boffs, oob, bytes);
2375 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2378 * nand_do_write_ops - [INTERN] NAND write with ECC
2379 * @mtd: MTD device structure
2380 * @to: offset to write to
2381 * @ops: oob operations description structure
2383 * NAND write with ECC.
2385 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2386 struct mtd_oob_ops *ops)
2388 int chipnr, realpage, page, blockmask, column;
2389 struct nand_chip *chip = mtd->priv;
2390 uint32_t writelen = ops->len;
2392 uint32_t oobwritelen = ops->ooblen;
2393 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2394 mtd->oobavail : mtd->oobsize;
2396 uint8_t *oob = ops->oobbuf;
2397 uint8_t *buf = ops->datbuf;
2399 int oob_required = oob ? 1 : 0;
2405 /* Reject writes, which are not page aligned */
2406 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2407 pr_notice("%s: attempt to write non page aligned data\n",
2412 column = to & (mtd->writesize - 1);
2414 chipnr = (int)(to >> chip->chip_shift);
2415 chip->select_chip(mtd, chipnr);
2417 /* Check, if it is write protected */
2418 if (nand_check_wp(mtd)) {
2423 realpage = (int)(to >> chip->page_shift);
2424 page = realpage & chip->pagemask;
2425 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2427 /* Invalidate the page cache, when we write to the cached page */
2428 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2429 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2432 /* Don't allow multipage oob writes with offset */
2433 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2439 int bytes = mtd->writesize;
2440 int cached = writelen > bytes && page != blockmask;
2441 uint8_t *wbuf = buf;
2443 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2447 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2448 use_bufpoi = !virt_addr_valid(buf);
2452 /* Partial page write?, or need to use bounce buffer */
2454 pr_debug("%s: using write bounce buffer for buf@%p\n",
2458 bytes = min_t(int, bytes - column, writelen);
2460 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2461 memcpy(&chip->buffers->databuf[column], buf, bytes);
2462 wbuf = chip->buffers->databuf;
2465 if (unlikely(oob)) {
2466 size_t len = min(oobwritelen, oobmaxlen);
2467 oob = nand_fill_oob(mtd, oob, len, ops);
2470 /* We still need to erase leftover OOB data */
2471 memset(chip->oob_poi, 0xff, mtd->oobsize);
2473 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2474 oob_required, page, cached,
2475 (ops->mode == MTD_OPS_RAW));
2487 page = realpage & chip->pagemask;
2488 /* Check, if we cross a chip boundary */
2491 chip->select_chip(mtd, -1);
2492 chip->select_chip(mtd, chipnr);
2496 ops->retlen = ops->len - writelen;
2498 ops->oobretlen = ops->ooblen;
2501 chip->select_chip(mtd, -1);
2506 * panic_nand_write - [MTD Interface] NAND write with ECC
2507 * @mtd: MTD device structure
2508 * @to: offset to write to
2509 * @len: number of bytes to write
2510 * @retlen: pointer to variable to store the number of written bytes
2511 * @buf: the data to write
2513 * NAND write with ECC. Used when performing writes in interrupt context, this
2514 * may for example be called by mtdoops when writing an oops while in panic.
2516 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2517 size_t *retlen, const uint8_t *buf)
2519 struct nand_chip *chip = mtd->priv;
2520 struct mtd_oob_ops ops;
2523 /* Wait for the device to get ready */
2524 panic_nand_wait(mtd, chip, 400);
2526 /* Grab the device */
2527 panic_nand_get_device(chip, mtd, FL_WRITING);
2529 memset(&ops, 0, sizeof(ops));
2531 ops.datbuf = (uint8_t *)buf;
2532 ops.mode = MTD_OPS_PLACE_OOB;
2534 ret = nand_do_write_ops(mtd, to, &ops);
2536 *retlen = ops.retlen;
2541 * nand_write - [MTD Interface] NAND write with ECC
2542 * @mtd: MTD device structure
2543 * @to: offset to write to
2544 * @len: number of bytes to write
2545 * @retlen: pointer to variable to store the number of written bytes
2546 * @buf: the data to write
2548 * NAND write with ECC.
2550 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2551 size_t *retlen, const uint8_t *buf)
2553 struct mtd_oob_ops ops;
2556 nand_get_device(mtd, FL_WRITING);
2557 memset(&ops, 0, sizeof(ops));
2559 ops.datbuf = (uint8_t *)buf;
2560 ops.mode = MTD_OPS_PLACE_OOB;
2561 ret = nand_do_write_ops(mtd, to, &ops);
2562 *retlen = ops.retlen;
2563 nand_release_device(mtd);
2568 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2569 * @mtd: MTD device structure
2570 * @to: offset to write to
2571 * @ops: oob operation description structure
2573 * NAND write out-of-band.
2575 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2576 struct mtd_oob_ops *ops)
2578 int chipnr, page, status, len;
2579 struct nand_chip *chip = mtd->priv;
2581 pr_debug("%s: to = 0x%08x, len = %i\n",
2582 __func__, (unsigned int)to, (int)ops->ooblen);
2584 if (ops->mode == MTD_OPS_AUTO_OOB)
2585 len = chip->ecc.layout->oobavail;
2589 /* Do not allow write past end of page */
2590 if ((ops->ooboffs + ops->ooblen) > len) {
2591 pr_debug("%s: attempt to write past end of page\n",
2596 if (unlikely(ops->ooboffs >= len)) {
2597 pr_debug("%s: attempt to start write outside oob\n",
2602 /* Do not allow write past end of device */
2603 if (unlikely(to >= mtd->size ||
2604 ops->ooboffs + ops->ooblen >
2605 ((mtd->size >> chip->page_shift) -
2606 (to >> chip->page_shift)) * len)) {
2607 pr_debug("%s: attempt to write beyond end of device\n",
2612 chipnr = (int)(to >> chip->chip_shift);
2613 chip->select_chip(mtd, chipnr);
2615 /* Shift to get page */
2616 page = (int)(to >> chip->page_shift);
2619 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2620 * of my DiskOnChip 2000 test units) will clear the whole data page too
2621 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2622 * it in the doc2000 driver in August 1999. dwmw2.
2624 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2626 /* Check, if it is write protected */
2627 if (nand_check_wp(mtd)) {
2628 chip->select_chip(mtd, -1);
2632 /* Invalidate the page cache, if we write to the cached page */
2633 if (page == chip->pagebuf)
2636 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2638 if (ops->mode == MTD_OPS_RAW)
2639 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2641 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2643 chip->select_chip(mtd, -1);
2648 ops->oobretlen = ops->ooblen;
2654 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2655 * @mtd: MTD device structure
2656 * @to: offset to write to
2657 * @ops: oob operation description structure
2659 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2660 struct mtd_oob_ops *ops)
2662 int ret = -ENOTSUPP;
2666 /* Do not allow writes past end of device */
2667 if (ops->datbuf && (to + ops->len) > mtd->size) {
2668 pr_debug("%s: attempt to write beyond end of device\n",
2673 nand_get_device(mtd, FL_WRITING);
2675 switch (ops->mode) {
2676 case MTD_OPS_PLACE_OOB:
2677 case MTD_OPS_AUTO_OOB:
2686 ret = nand_do_write_oob(mtd, to, ops);
2688 ret = nand_do_write_ops(mtd, to, ops);
2691 nand_release_device(mtd);
2696 * single_erase - [GENERIC] NAND standard block erase command function
2697 * @mtd: MTD device structure
2698 * @page: the page address of the block which will be erased
2700 * Standard erase command for NAND chips. Returns NAND status.
2702 static int single_erase(struct mtd_info *mtd, int page)
2704 struct nand_chip *chip = mtd->priv;
2705 /* Send commands to erase a block */
2706 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2707 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2709 return chip->waitfunc(mtd, chip);
2713 * nand_erase - [MTD Interface] erase block(s)
2714 * @mtd: MTD device structure
2715 * @instr: erase instruction
2717 * Erase one ore more blocks.
2719 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2721 return nand_erase_nand(mtd, instr, 0);
2725 * nand_erase_nand - [INTERN] erase block(s)
2726 * @mtd: MTD device structure
2727 * @instr: erase instruction
2728 * @allowbbt: allow erasing the bbt area
2730 * Erase one ore more blocks.
2732 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2735 int page, status, pages_per_block, ret, chipnr;
2736 struct nand_chip *chip = mtd->priv;
2739 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2740 __func__, (unsigned long long)instr->addr,
2741 (unsigned long long)instr->len);
2743 if (check_offs_len(mtd, instr->addr, instr->len))
2746 /* Grab the lock and see if the device is available */
2747 nand_get_device(mtd, FL_ERASING);
2749 /* Shift to get first page */
2750 page = (int)(instr->addr >> chip->page_shift);
2751 chipnr = (int)(instr->addr >> chip->chip_shift);
2753 /* Calculate pages in each block */
2754 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2756 /* Select the NAND device */
2757 chip->select_chip(mtd, chipnr);
2759 /* Check, if it is write protected */
2760 if (nand_check_wp(mtd)) {
2761 pr_debug("%s: device is write protected!\n",
2763 instr->state = MTD_ERASE_FAILED;
2767 /* Loop through the pages */
2770 instr->state = MTD_ERASING;
2773 /* Check if we have a bad block, we do not erase bad blocks! */
2774 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2775 chip->page_shift, 0, allowbbt)) {
2776 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2778 instr->state = MTD_ERASE_FAILED;
2783 * Invalidate the page cache, if we erase the block which
2784 * contains the current cached page.
2786 if (page <= chip->pagebuf && chip->pagebuf <
2787 (page + pages_per_block))
2790 status = chip->erase(mtd, page & chip->pagemask);
2793 * See if operation failed and additional status checks are
2796 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2797 status = chip->errstat(mtd, chip, FL_ERASING,
2800 /* See if block erase succeeded */
2801 if (status & NAND_STATUS_FAIL) {
2802 pr_debug("%s: failed erase, page 0x%08x\n",
2804 instr->state = MTD_ERASE_FAILED;
2806 ((loff_t)page << chip->page_shift);
2810 /* Increment page address and decrement length */
2811 len -= (1ULL << chip->phys_erase_shift);
2812 page += pages_per_block;
2814 /* Check, if we cross a chip boundary */
2815 if (len && !(page & chip->pagemask)) {
2817 chip->select_chip(mtd, -1);
2818 chip->select_chip(mtd, chipnr);
2821 instr->state = MTD_ERASE_DONE;
2825 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2827 /* Deselect and wake up anyone waiting on the device */
2828 chip->select_chip(mtd, -1);
2829 nand_release_device(mtd);
2831 /* Do call back function */
2833 mtd_erase_callback(instr);
2835 /* Return more or less happy */
2840 * nand_sync - [MTD Interface] sync
2841 * @mtd: MTD device structure
2843 * Sync is actually a wait for chip ready function.
2845 static void nand_sync(struct mtd_info *mtd)
2847 pr_debug("%s: called\n", __func__);
2849 /* Grab the lock and see if the device is available */
2850 nand_get_device(mtd, FL_SYNCING);
2851 /* Release it and go back */
2852 nand_release_device(mtd);
2856 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2857 * @mtd: MTD device structure
2858 * @offs: offset relative to mtd start
2860 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2862 return nand_block_checkbad(mtd, offs, 1, 0);
2866 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2867 * @mtd: MTD device structure
2868 * @ofs: offset relative to mtd start
2870 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2874 ret = nand_block_isbad(mtd, ofs);
2876 /* If it was bad already, return success and do nothing */
2882 return nand_block_markbad_lowlevel(mtd, ofs);
2886 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2887 * @mtd: MTD device structure
2888 * @chip: nand chip info structure
2889 * @addr: feature address.
2890 * @subfeature_param: the subfeature parameters, a four bytes array.
2892 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2893 int addr, uint8_t *subfeature_param)
2898 if (!chip->onfi_version ||
2899 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2900 & ONFI_OPT_CMD_SET_GET_FEATURES))
2903 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2904 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2905 chip->write_byte(mtd, subfeature_param[i]);
2907 status = chip->waitfunc(mtd, chip);
2908 if (status & NAND_STATUS_FAIL)
2914 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2915 * @mtd: MTD device structure
2916 * @chip: nand chip info structure
2917 * @addr: feature address.
2918 * @subfeature_param: the subfeature parameters, a four bytes array.
2920 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2921 int addr, uint8_t *subfeature_param)
2925 if (!chip->onfi_version ||
2926 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2927 & ONFI_OPT_CMD_SET_GET_FEATURES))
2930 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2931 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2932 *subfeature_param++ = chip->read_byte(mtd);
2937 * nand_suspend - [MTD Interface] Suspend the NAND flash
2938 * @mtd: MTD device structure
2940 static int nand_suspend(struct mtd_info *mtd)
2942 return nand_get_device(mtd, FL_PM_SUSPENDED);
2946 * nand_resume - [MTD Interface] Resume the NAND flash
2947 * @mtd: MTD device structure
2949 static void nand_resume(struct mtd_info *mtd)
2951 struct nand_chip *chip = mtd->priv;
2953 if (chip->state == FL_PM_SUSPENDED)
2954 nand_release_device(mtd);
2956 pr_err("%s called for a chip which is not in suspended state\n",
2961 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
2962 * prevent further operations
2963 * @mtd: MTD device structure
2965 static void nand_shutdown(struct mtd_info *mtd)
2967 nand_get_device(mtd, FL_SHUTDOWN);
2970 /* Set default functions */
2971 static void nand_set_defaults(struct nand_chip *chip, int busw)
2973 /* check for proper chip_delay setup, set 20us if not */
2974 if (!chip->chip_delay)
2975 chip->chip_delay = 20;
2977 /* check, if a user supplied command function given */
2978 if (chip->cmdfunc == NULL)
2979 chip->cmdfunc = nand_command;
2981 /* check, if a user supplied wait function given */
2982 if (chip->waitfunc == NULL)
2983 chip->waitfunc = nand_wait;
2985 if (!chip->select_chip)
2986 chip->select_chip = nand_select_chip;
2988 /* set for ONFI nand */
2989 if (!chip->onfi_set_features)
2990 chip->onfi_set_features = nand_onfi_set_features;
2991 if (!chip->onfi_get_features)
2992 chip->onfi_get_features = nand_onfi_get_features;
2994 /* If called twice, pointers that depend on busw may need to be reset */
2995 if (!chip->read_byte || chip->read_byte == nand_read_byte)
2996 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2997 if (!chip->read_word)
2998 chip->read_word = nand_read_word;
2999 if (!chip->block_bad)
3000 chip->block_bad = nand_block_bad;
3001 if (!chip->block_markbad)
3002 chip->block_markbad = nand_default_block_markbad;
3003 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3004 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3005 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3006 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3007 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3008 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3009 if (!chip->scan_bbt)
3010 chip->scan_bbt = nand_default_bbt;
3012 if (!chip->controller) {
3013 chip->controller = &chip->hwcontrol;
3014 spin_lock_init(&chip->controller->lock);
3015 init_waitqueue_head(&chip->controller->wq);
3020 /* Sanitize ONFI strings so we can safely print them */
3021 static void sanitize_string(uint8_t *s, size_t len)
3025 /* Null terminate */
3028 /* Remove non printable chars */
3029 for (i = 0; i < len - 1; i++) {
3030 if (s[i] < ' ' || s[i] > 127)
3034 /* Remove trailing spaces */
3038 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3043 for (i = 0; i < 8; i++)
3044 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3050 /* Parse the Extended Parameter Page. */
3051 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3052 struct nand_chip *chip, struct nand_onfi_params *p)
3054 struct onfi_ext_param_page *ep;
3055 struct onfi_ext_section *s;
3056 struct onfi_ext_ecc_info *ecc;
3062 len = le16_to_cpu(p->ext_param_page_length) * 16;
3063 ep = kmalloc(len, GFP_KERNEL);
3067 /* Send our own NAND_CMD_PARAM. */
3068 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3070 /* Use the Change Read Column command to skip the ONFI param pages. */
3071 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3072 sizeof(*p) * p->num_of_param_pages , -1);
3074 /* Read out the Extended Parameter Page. */
3075 chip->read_buf(mtd, (uint8_t *)ep, len);
3076 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3077 != le16_to_cpu(ep->crc))) {
3078 pr_debug("fail in the CRC.\n");
3083 * Check the signature.
3084 * Do not strictly follow the ONFI spec, maybe changed in future.
3086 if (strncmp(ep->sig, "EPPS", 4)) {
3087 pr_debug("The signature is invalid.\n");
3091 /* find the ECC section. */
3092 cursor = (uint8_t *)(ep + 1);
3093 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3094 s = ep->sections + i;
3095 if (s->type == ONFI_SECTION_TYPE_2)
3097 cursor += s->length * 16;
3099 if (i == ONFI_EXT_SECTION_MAX) {
3100 pr_debug("We can not find the ECC section.\n");
3104 /* get the info we want. */
3105 ecc = (struct onfi_ext_ecc_info *)cursor;
3107 if (!ecc->codeword_size) {
3108 pr_debug("Invalid codeword size\n");
3112 chip->ecc_strength_ds = ecc->ecc_bits;
3113 chip->ecc_step_ds = 1 << ecc->codeword_size;
3121 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3123 struct nand_chip *chip = mtd->priv;
3124 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3126 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3131 * Configure chip properties from Micron vendor-specific ONFI table
3133 static void nand_onfi_detect_micron(struct nand_chip *chip,
3134 struct nand_onfi_params *p)
3136 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3138 if (le16_to_cpu(p->vendor_revision) < 1)
3141 chip->read_retries = micron->read_retry_options;
3142 chip->setup_read_retry = nand_setup_read_retry_micron;
3146 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3148 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3151 struct nand_onfi_params *p = &chip->onfi_params;
3155 /* Try ONFI for unknown chip or LP */
3156 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3157 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3158 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3161 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3162 for (i = 0; i < 3; i++) {
3163 for (j = 0; j < sizeof(*p); j++)
3164 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3165 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3166 le16_to_cpu(p->crc)) {
3172 pr_err("Could not find valid ONFI parameter page; aborting\n");
3177 val = le16_to_cpu(p->revision);
3179 chip->onfi_version = 23;
3180 else if (val & (1 << 4))
3181 chip->onfi_version = 22;
3182 else if (val & (1 << 3))
3183 chip->onfi_version = 21;
3184 else if (val & (1 << 2))
3185 chip->onfi_version = 20;
3186 else if (val & (1 << 1))
3187 chip->onfi_version = 10;
3189 if (!chip->onfi_version) {
3190 pr_info("unsupported ONFI version: %d\n", val);
3194 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3195 sanitize_string(p->model, sizeof(p->model));
3197 mtd->name = p->model;
3199 mtd->writesize = le32_to_cpu(p->byte_per_page);
3202 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3203 * (don't ask me who thought of this...). MTD assumes that these
3204 * dimensions will be power-of-2, so just truncate the remaining area.
3206 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3207 mtd->erasesize *= mtd->writesize;
3209 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3211 /* See erasesize comment */
3212 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3213 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3214 chip->bits_per_cell = p->bits_per_cell;
3216 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3217 *busw = NAND_BUSWIDTH_16;
3221 if (p->ecc_bits != 0xff) {
3222 chip->ecc_strength_ds = p->ecc_bits;
3223 chip->ecc_step_ds = 512;
3224 } else if (chip->onfi_version >= 21 &&
3225 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3228 * The nand_flash_detect_ext_param_page() uses the
3229 * Change Read Column command which maybe not supported
3230 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3231 * now. We do not replace user supplied command function.
3233 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3234 chip->cmdfunc = nand_command_lp;
3236 /* The Extended Parameter Page is supported since ONFI 2.1. */
3237 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3238 pr_warn("Failed to detect ONFI extended param page\n");
3240 pr_warn("Could not retrieve ONFI ECC requirements\n");
3243 if (p->jedec_id == NAND_MFR_MICRON)
3244 nand_onfi_detect_micron(chip, p);
3250 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3252 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3255 struct nand_jedec_params *p = &chip->jedec_params;
3256 struct jedec_ecc_info *ecc;
3260 /* Try JEDEC for unknown chip or LP */
3261 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3262 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3263 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3264 chip->read_byte(mtd) != 'C')
3267 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3268 for (i = 0; i < 3; i++) {
3269 for (j = 0; j < sizeof(*p); j++)
3270 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3272 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3273 le16_to_cpu(p->crc))
3278 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3283 val = le16_to_cpu(p->revision);
3285 chip->jedec_version = 10;
3286 else if (val & (1 << 1))
3287 chip->jedec_version = 1; /* vendor specific version */
3289 if (!chip->jedec_version) {
3290 pr_info("unsupported JEDEC version: %d\n", val);
3294 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3295 sanitize_string(p->model, sizeof(p->model));
3297 mtd->name = p->model;
3299 mtd->writesize = le32_to_cpu(p->byte_per_page);
3301 /* Please reference to the comment for nand_flash_detect_onfi. */
3302 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3303 mtd->erasesize *= mtd->writesize;
3305 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3307 /* Please reference to the comment for nand_flash_detect_onfi. */
3308 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3309 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3310 chip->bits_per_cell = p->bits_per_cell;
3312 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3313 *busw = NAND_BUSWIDTH_16;
3318 ecc = &p->ecc_info[0];
3320 if (ecc->codeword_size >= 9) {
3321 chip->ecc_strength_ds = ecc->ecc_bits;
3322 chip->ecc_step_ds = 1 << ecc->codeword_size;
3324 pr_warn("Invalid codeword size\n");
3331 * nand_id_has_period - Check if an ID string has a given wraparound period
3332 * @id_data: the ID string
3333 * @arrlen: the length of the @id_data array
3334 * @period: the period of repitition
3336 * Check if an ID string is repeated within a given sequence of bytes at
3337 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3338 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3339 * if the repetition has a period of @period; otherwise, returns zero.
3341 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3344 for (i = 0; i < period; i++)
3345 for (j = i + period; j < arrlen; j += period)
3346 if (id_data[i] != id_data[j])
3352 * nand_id_len - Get the length of an ID string returned by CMD_READID
3353 * @id_data: the ID string
3354 * @arrlen: the length of the @id_data array
3356 * Returns the length of the ID string, according to known wraparound/trailing
3357 * zero patterns. If no pattern exists, returns the length of the array.
3359 static int nand_id_len(u8 *id_data, int arrlen)
3361 int last_nonzero, period;
3363 /* Find last non-zero byte */
3364 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3365 if (id_data[last_nonzero])
3369 if (last_nonzero < 0)
3372 /* Calculate wraparound period */
3373 for (period = 1; period < arrlen; period++)
3374 if (nand_id_has_period(id_data, arrlen, period))
3377 /* There's a repeated pattern */
3378 if (period < arrlen)
3381 /* There are trailing zeros */
3382 if (last_nonzero < arrlen - 1)
3383 return last_nonzero + 1;
3385 /* No pattern detected */
3389 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3390 static int nand_get_bits_per_cell(u8 cellinfo)
3394 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3395 bits >>= NAND_CI_CELLTYPE_SHIFT;
3400 * Many new NAND share similar device ID codes, which represent the size of the
3401 * chip. The rest of the parameters must be decoded according to generic or
3402 * manufacturer-specific "extended ID" decoding patterns.
3404 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3405 u8 id_data[8], int *busw)
3408 /* The 3rd id byte holds MLC / multichip data */
3409 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3410 /* The 4th id byte is the important one */
3413 id_len = nand_id_len(id_data, 8);
3416 * Field definitions are in the following datasheets:
3417 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3418 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3419 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3421 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3422 * ID to decide what to do.
3424 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3425 !nand_is_slc(chip) && id_data[5] != 0x00) {
3427 mtd->writesize = 2048 << (extid & 0x03);
3430 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3450 default: /* Other cases are "reserved" (unknown) */
3451 mtd->oobsize = 1024;
3455 /* Calc blocksize */
3456 mtd->erasesize = (128 * 1024) <<
3457 (((extid >> 1) & 0x04) | (extid & 0x03));
3459 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3460 !nand_is_slc(chip)) {
3464 mtd->writesize = 2048 << (extid & 0x03);
3467 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3491 /* Calc blocksize */
3492 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3494 mtd->erasesize = (128 * 1024) << tmp;
3495 else if (tmp == 0x03)
3496 mtd->erasesize = 768 * 1024;
3498 mtd->erasesize = (64 * 1024) << tmp;
3502 mtd->writesize = 1024 << (extid & 0x03);
3505 mtd->oobsize = (8 << (extid & 0x01)) *
3506 (mtd->writesize >> 9);
3508 /* Calc blocksize. Blocksize is multiples of 64KiB */
3509 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3511 /* Get buswidth information */
3512 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3515 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3516 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3518 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3520 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3522 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3523 nand_is_slc(chip) &&
3524 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3525 !(id_data[4] & 0x80) /* !BENAND */) {
3526 mtd->oobsize = 32 * mtd->writesize >> 9;
3533 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3534 * decodes a matching ID table entry and assigns the MTD size parameters for
3537 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3538 struct nand_flash_dev *type, u8 id_data[8],
3541 int maf_id = id_data[0];
3543 mtd->erasesize = type->erasesize;
3544 mtd->writesize = type->pagesize;
3545 mtd->oobsize = mtd->writesize / 32;
3546 *busw = type->options & NAND_BUSWIDTH_16;
3548 /* All legacy ID NAND are small-page, SLC */
3549 chip->bits_per_cell = 1;
3552 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3553 * some Spansion chips have erasesize that conflicts with size
3554 * listed in nand_ids table.
3555 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3557 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3558 && id_data[6] == 0x00 && id_data[7] == 0x00
3559 && mtd->writesize == 512) {
3560 mtd->erasesize = 128 * 1024;
3561 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3566 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3567 * heuristic patterns using various detected parameters (e.g., manufacturer,
3568 * page size, cell-type information).
3570 static void nand_decode_bbm_options(struct mtd_info *mtd,
3571 struct nand_chip *chip, u8 id_data[8])
3573 int maf_id = id_data[0];
3575 /* Set the bad block position */
3576 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3577 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3579 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3582 * Bad block marker is stored in the last page of each block on Samsung
3583 * and Hynix MLC devices; stored in first two pages of each block on
3584 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3585 * AMD/Spansion, and Macronix. All others scan only the first page.
3587 if (!nand_is_slc(chip) &&
3588 (maf_id == NAND_MFR_SAMSUNG ||
3589 maf_id == NAND_MFR_HYNIX))
3590 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3591 else if ((nand_is_slc(chip) &&
3592 (maf_id == NAND_MFR_SAMSUNG ||
3593 maf_id == NAND_MFR_HYNIX ||
3594 maf_id == NAND_MFR_TOSHIBA ||
3595 maf_id == NAND_MFR_AMD ||
3596 maf_id == NAND_MFR_MACRONIX)) ||
3597 (mtd->writesize == 2048 &&
3598 maf_id == NAND_MFR_MICRON))
3599 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3602 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3604 return type->id_len;
3607 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3608 struct nand_flash_dev *type, u8 *id_data, int *busw)
3610 if (!strncmp(type->id, id_data, type->id_len)) {
3611 mtd->writesize = type->pagesize;
3612 mtd->erasesize = type->erasesize;
3613 mtd->oobsize = type->oobsize;
3615 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3616 chip->chipsize = (uint64_t)type->chipsize << 20;
3617 chip->options |= type->options;
3618 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3619 chip->ecc_step_ds = NAND_ECC_STEP(type);
3620 chip->onfi_timing_mode_default =
3621 type->onfi_timing_mode_default;
3623 *busw = type->options & NAND_BUSWIDTH_16;
3626 mtd->name = type->name;
3634 * Get the flash and manufacturer id and lookup if the type is supported.
3636 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3637 struct nand_chip *chip,
3638 int *maf_id, int *dev_id,
3639 struct nand_flash_dev *type)
3645 /* Select the device */
3646 chip->select_chip(mtd, 0);
3649 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3652 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3654 /* Send the command for reading device ID */
3655 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3657 /* Read manufacturer and device IDs */
3658 *maf_id = chip->read_byte(mtd);
3659 *dev_id = chip->read_byte(mtd);
3662 * Try again to make sure, as some systems the bus-hold or other
3663 * interface concerns can cause random data which looks like a
3664 * possibly credible NAND flash to appear. If the two results do
3665 * not match, ignore the device completely.
3668 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3670 /* Read entire ID string */
3671 for (i = 0; i < 8; i++)
3672 id_data[i] = chip->read_byte(mtd);
3674 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3675 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3676 *maf_id, *dev_id, id_data[0], id_data[1]);
3677 return ERR_PTR(-ENODEV);
3681 type = nand_flash_ids;
3683 for (; type->name != NULL; type++) {
3684 if (is_full_id_nand(type)) {
3685 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3687 } else if (*dev_id == type->dev_id) {
3692 chip->onfi_version = 0;
3693 if (!type->name || !type->pagesize) {
3694 /* Check if the chip is ONFI compliant */
3695 if (nand_flash_detect_onfi(mtd, chip, &busw))
3698 /* Check if the chip is JEDEC compliant */
3699 if (nand_flash_detect_jedec(mtd, chip, &busw))
3704 return ERR_PTR(-ENODEV);
3707 mtd->name = type->name;
3709 chip->chipsize = (uint64_t)type->chipsize << 20;
3711 if (!type->pagesize && chip->init_size) {
3712 /* Set the pagesize, oobsize, erasesize by the driver */
3713 busw = chip->init_size(mtd, chip, id_data);
3714 } else if (!type->pagesize) {
3715 /* Decode parameters from extended ID */
3716 nand_decode_ext_id(mtd, chip, id_data, &busw);
3718 nand_decode_id(mtd, chip, type, id_data, &busw);
3720 /* Get chip options */
3721 chip->options |= type->options;
3724 * Check if chip is not a Samsung device. Do not clear the
3725 * options for chips which do not have an extended id.
3727 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3728 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3731 /* Try to identify manufacturer */
3732 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3733 if (nand_manuf_ids[maf_idx].id == *maf_id)
3737 if (chip->options & NAND_BUSWIDTH_AUTO) {
3738 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3739 chip->options |= busw;
3740 nand_set_defaults(chip, busw);
3741 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3743 * Check, if buswidth is correct. Hardware drivers should set
3746 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3748 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3749 pr_warn("bus width %d instead %d bit\n",
3750 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3752 return ERR_PTR(-EINVAL);
3755 nand_decode_bbm_options(mtd, chip, id_data);
3757 /* Calculate the address shift from the page size */
3758 chip->page_shift = ffs(mtd->writesize) - 1;
3759 /* Convert chipsize to number of pages per chip -1 */
3760 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3762 chip->bbt_erase_shift = chip->phys_erase_shift =
3763 ffs(mtd->erasesize) - 1;
3764 if (chip->chipsize & 0xffffffff)
3765 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3767 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3768 chip->chip_shift += 32 - 1;
3771 chip->badblockbits = 8;
3772 chip->erase = single_erase;
3774 /* Do not replace user supplied command function! */
3775 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3776 chip->cmdfunc = nand_command_lp;
3778 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3781 if (chip->onfi_version)
3782 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3783 chip->onfi_params.model);
3784 else if (chip->jedec_version)
3785 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3786 chip->jedec_params.model);
3788 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3791 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3792 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3793 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3797 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip,
3798 struct device_node *dn)
3800 int ecc_mode, ecc_strength, ecc_step;
3802 if (of_get_nand_bus_width(dn) == 16)
3803 chip->options |= NAND_BUSWIDTH_16;
3805 if (of_get_nand_on_flash_bbt(dn))
3806 chip->bbt_options |= NAND_BBT_USE_FLASH;
3808 ecc_mode = of_get_nand_ecc_mode(dn);
3809 ecc_strength = of_get_nand_ecc_strength(dn);
3810 ecc_step = of_get_nand_ecc_step_size(dn);
3812 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3813 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3814 pr_err("must set both strength and step size in DT\n");
3819 chip->ecc.mode = ecc_mode;
3821 if (ecc_strength >= 0)
3822 chip->ecc.strength = ecc_strength;
3825 chip->ecc.size = ecc_step;
3831 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3832 * @mtd: MTD device structure
3833 * @maxchips: number of chips to scan for
3834 * @table: alternative NAND ID table
3836 * This is the first phase of the normal nand_scan() function. It reads the
3837 * flash ID and sets up MTD fields accordingly.
3839 * The mtd->owner field must be set to the module of the caller.
3841 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3842 struct nand_flash_dev *table)
3844 int i, nand_maf_id, nand_dev_id;
3845 struct nand_chip *chip = mtd->priv;
3846 struct nand_flash_dev *type;
3850 ret = nand_dt_init(mtd, chip, chip->dn);
3855 /* Set the default functions */
3856 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3858 /* Read the flash type */
3859 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3860 &nand_dev_id, table);
3863 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3864 pr_warn("No NAND device found\n");
3865 chip->select_chip(mtd, -1);
3866 return PTR_ERR(type);
3869 chip->select_chip(mtd, -1);
3871 /* Check for a chip array */
3872 for (i = 1; i < maxchips; i++) {
3873 chip->select_chip(mtd, i);
3874 /* See comment in nand_get_flash_type for reset */
3875 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3876 /* Send the command for reading device ID */
3877 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3878 /* Read manufacturer and device IDs */
3879 if (nand_maf_id != chip->read_byte(mtd) ||
3880 nand_dev_id != chip->read_byte(mtd)) {
3881 chip->select_chip(mtd, -1);
3884 chip->select_chip(mtd, -1);
3887 pr_info("%d chips detected\n", i);
3889 /* Store the number of chips and calc total size for mtd */
3891 mtd->size = i * chip->chipsize;
3895 EXPORT_SYMBOL(nand_scan_ident);
3898 * Check if the chip configuration meet the datasheet requirements.
3900 * If our configuration corrects A bits per B bytes and the minimum
3901 * required correction level is X bits per Y bytes, then we must ensure
3902 * both of the following are true:
3904 * (1) A / B >= X / Y
3907 * Requirement (1) ensures we can correct for the required bitflip density.
3908 * Requirement (2) ensures we can correct even when all bitflips are clumped
3909 * in the same sector.
3911 static bool nand_ecc_strength_good(struct mtd_info *mtd)
3913 struct nand_chip *chip = mtd->priv;
3914 struct nand_ecc_ctrl *ecc = &chip->ecc;
3917 if (ecc->size == 0 || chip->ecc_step_ds == 0)
3918 /* Not enough information */
3922 * We get the number of corrected bits per page to compare
3923 * the correction density.
3925 corr = (mtd->writesize * ecc->strength) / ecc->size;
3926 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
3928 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
3932 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3933 * @mtd: MTD device structure
3935 * This is the second phase of the normal nand_scan() function. It fills out
3936 * all the uninitialized function pointers with the defaults and scans for a
3937 * bad block table if appropriate.
3939 int nand_scan_tail(struct mtd_info *mtd)
3942 struct nand_chip *chip = mtd->priv;
3943 struct nand_ecc_ctrl *ecc = &chip->ecc;
3944 struct nand_buffers *nbuf;
3946 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3947 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3948 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3950 if (!(chip->options & NAND_OWN_BUFFERS)) {
3951 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3952 + mtd->oobsize * 3, GFP_KERNEL);
3955 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3956 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3957 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3959 chip->buffers = nbuf;
3965 /* Set the internal oob buffer location, just after the page data */
3966 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3969 * If no default placement scheme is given, select an appropriate one.
3971 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3972 switch (mtd->oobsize) {
3974 ecc->layout = &nand_oob_8;
3977 ecc->layout = &nand_oob_16;
3980 ecc->layout = &nand_oob_64;
3983 ecc->layout = &nand_oob_128;
3986 pr_warn("No oob scheme defined for oobsize %d\n",
3992 if (!chip->write_page)
3993 chip->write_page = nand_write_page;
3996 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3997 * selected and we have 256 byte pagesize fallback to software ECC
4000 switch (ecc->mode) {
4001 case NAND_ECC_HW_OOB_FIRST:
4002 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4003 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4004 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4007 if (!ecc->read_page)
4008 ecc->read_page = nand_read_page_hwecc_oob_first;
4011 /* Use standard hwecc read page function? */
4012 if (!ecc->read_page)
4013 ecc->read_page = nand_read_page_hwecc;
4014 if (!ecc->write_page)
4015 ecc->write_page = nand_write_page_hwecc;
4016 if (!ecc->read_page_raw)
4017 ecc->read_page_raw = nand_read_page_raw;
4018 if (!ecc->write_page_raw)
4019 ecc->write_page_raw = nand_write_page_raw;
4021 ecc->read_oob = nand_read_oob_std;
4022 if (!ecc->write_oob)
4023 ecc->write_oob = nand_write_oob_std;
4024 if (!ecc->read_subpage)
4025 ecc->read_subpage = nand_read_subpage;
4026 if (!ecc->write_subpage)
4027 ecc->write_subpage = nand_write_subpage_hwecc;
4029 case NAND_ECC_HW_SYNDROME:
4030 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4032 ecc->read_page == nand_read_page_hwecc ||
4034 ecc->write_page == nand_write_page_hwecc)) {
4035 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4038 /* Use standard syndrome read/write page function? */
4039 if (!ecc->read_page)
4040 ecc->read_page = nand_read_page_syndrome;
4041 if (!ecc->write_page)
4042 ecc->write_page = nand_write_page_syndrome;
4043 if (!ecc->read_page_raw)
4044 ecc->read_page_raw = nand_read_page_raw_syndrome;
4045 if (!ecc->write_page_raw)
4046 ecc->write_page_raw = nand_write_page_raw_syndrome;
4048 ecc->read_oob = nand_read_oob_syndrome;
4049 if (!ecc->write_oob)
4050 ecc->write_oob = nand_write_oob_syndrome;
4052 if (mtd->writesize >= ecc->size) {
4053 if (!ecc->strength) {
4054 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4059 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4060 ecc->size, mtd->writesize);
4061 ecc->mode = NAND_ECC_SOFT;
4064 ecc->calculate = nand_calculate_ecc;
4065 ecc->correct = nand_correct_data;
4066 ecc->read_page = nand_read_page_swecc;
4067 ecc->read_subpage = nand_read_subpage;
4068 ecc->write_page = nand_write_page_swecc;
4069 ecc->read_page_raw = nand_read_page_raw;
4070 ecc->write_page_raw = nand_write_page_raw;
4071 ecc->read_oob = nand_read_oob_std;
4072 ecc->write_oob = nand_write_oob_std;
4079 case NAND_ECC_SOFT_BCH:
4080 if (!mtd_nand_has_bch()) {
4081 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4084 ecc->calculate = nand_bch_calculate_ecc;
4085 ecc->correct = nand_bch_correct_data;
4086 ecc->read_page = nand_read_page_swecc;
4087 ecc->read_subpage = nand_read_subpage;
4088 ecc->write_page = nand_write_page_swecc;
4089 ecc->read_page_raw = nand_read_page_raw;
4090 ecc->write_page_raw = nand_write_page_raw;
4091 ecc->read_oob = nand_read_oob_std;
4092 ecc->write_oob = nand_write_oob_std;
4094 * Board driver should supply ecc.size and ecc.strength values
4095 * to select how many bits are correctable. Otherwise, default
4096 * to 4 bits for large page devices.
4098 if (!ecc->size && (mtd->oobsize >= 64)) {
4103 /* See nand_bch_init() for details. */
4104 ecc->bytes = DIV_ROUND_UP(
4105 ecc->strength * fls(8 * ecc->size), 8);
4106 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4109 pr_warn("BCH ECC initialization failed!\n");
4115 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4116 ecc->read_page = nand_read_page_raw;
4117 ecc->write_page = nand_write_page_raw;
4118 ecc->read_oob = nand_read_oob_std;
4119 ecc->read_page_raw = nand_read_page_raw;
4120 ecc->write_page_raw = nand_write_page_raw;
4121 ecc->write_oob = nand_write_oob_std;
4122 ecc->size = mtd->writesize;
4128 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4132 /* For many systems, the standard OOB write also works for raw */
4133 if (!ecc->read_oob_raw)
4134 ecc->read_oob_raw = ecc->read_oob;
4135 if (!ecc->write_oob_raw)
4136 ecc->write_oob_raw = ecc->write_oob;
4139 * The number of bytes available for a client to place data into
4140 * the out of band area.
4142 ecc->layout->oobavail = 0;
4143 for (i = 0; ecc->layout->oobfree[i].length
4144 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4145 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4146 mtd->oobavail = ecc->layout->oobavail;
4148 /* ECC sanity check: warn if it's too weak */
4149 if (!nand_ecc_strength_good(mtd))
4150 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4154 * Set the number of read / write steps for one page depending on ECC
4157 ecc->steps = mtd->writesize / ecc->size;
4158 if (ecc->steps * ecc->size != mtd->writesize) {
4159 pr_warn("Invalid ECC parameters\n");
4162 ecc->total = ecc->steps * ecc->bytes;
4164 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4165 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4166 switch (ecc->steps) {
4168 mtd->subpage_sft = 1;
4173 mtd->subpage_sft = 2;
4177 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4179 /* Initialize state */
4180 chip->state = FL_READY;
4182 /* Invalidate the pagebuffer reference */
4185 /* Large page NAND with SOFT_ECC should support subpage reads */
4186 switch (ecc->mode) {
4188 case NAND_ECC_SOFT_BCH:
4189 if (chip->page_shift > 9)
4190 chip->options |= NAND_SUBPAGE_READ;
4197 /* Fill in remaining MTD driver data */
4198 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4199 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4201 mtd->_erase = nand_erase;
4203 mtd->_unpoint = NULL;
4204 mtd->_read = nand_read;
4205 mtd->_write = nand_write;
4206 mtd->_panic_write = panic_nand_write;
4207 mtd->_read_oob = nand_read_oob;
4208 mtd->_write_oob = nand_write_oob;
4209 mtd->_sync = nand_sync;
4211 mtd->_unlock = NULL;
4212 mtd->_suspend = nand_suspend;
4213 mtd->_resume = nand_resume;
4214 mtd->_reboot = nand_shutdown;
4215 mtd->_block_isreserved = nand_block_isreserved;
4216 mtd->_block_isbad = nand_block_isbad;
4217 mtd->_block_markbad = nand_block_markbad;
4218 mtd->writebufsize = mtd->writesize;
4220 /* propagate ecc info to mtd_info */
4221 mtd->ecclayout = ecc->layout;
4222 mtd->ecc_strength = ecc->strength;
4223 mtd->ecc_step_size = ecc->size;
4225 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4226 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4229 if (!mtd->bitflip_threshold)
4230 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4232 /* Check, if we should skip the bad block table scan */
4233 if (chip->options & NAND_SKIP_BBTSCAN)
4236 /* Build bad block table */
4237 return chip->scan_bbt(mtd);
4239 EXPORT_SYMBOL(nand_scan_tail);
4242 * is_module_text_address() isn't exported, and it's mostly a pointless
4243 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4244 * to call us from in-kernel code if the core NAND support is modular.
4247 #define caller_is_module() (1)
4249 #define caller_is_module() \
4250 is_module_text_address((unsigned long)__builtin_return_address(0))
4254 * nand_scan - [NAND Interface] Scan for the NAND device
4255 * @mtd: MTD device structure
4256 * @maxchips: number of chips to scan for
4258 * This fills out all the uninitialized function pointers with the defaults.
4259 * The flash ID is read and the mtd/chip structures are filled with the
4260 * appropriate values. The mtd->owner field must be set to the module of the
4263 int nand_scan(struct mtd_info *mtd, int maxchips)
4267 /* Many callers got this wrong, so check for it for a while... */
4268 if (!mtd->owner && caller_is_module()) {
4269 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4273 ret = nand_scan_ident(mtd, maxchips, NULL);
4275 ret = nand_scan_tail(mtd);
4278 EXPORT_SYMBOL(nand_scan);
4281 * nand_release - [NAND Interface] Free resources held by the NAND device
4282 * @mtd: MTD device structure
4284 void nand_release(struct mtd_info *mtd)
4286 struct nand_chip *chip = mtd->priv;
4288 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4289 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4291 mtd_device_unregister(mtd);
4293 /* Free bad block table memory */
4295 if (!(chip->options & NAND_OWN_BUFFERS))
4296 kfree(chip->buffers);
4298 /* Free bad block descriptor memory */
4299 if (chip->badblock_pattern && chip->badblock_pattern->options
4300 & NAND_BBT_DYNAMICSTRUCT)
4301 kfree(chip->badblock_pattern);
4303 EXPORT_SYMBOL_GPL(nand_release);
4305 static int __init nand_base_init(void)
4307 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4311 static void __exit nand_base_exit(void)
4313 led_trigger_unregister_simple(nand_led_trigger);
4316 module_init(nand_base_init);
4317 module_exit(nand_base_exit);
4319 MODULE_LICENSE("GPL");
4320 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4321 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4322 MODULE_DESCRIPTION("Generic NAND flash driver code");