3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
46 #include <linux/leds.h>
48 #include <linux/mtd/partitions.h>
49 #include <linux/of_mtd.h>
51 /* Define default oob placement schemes for large and small page devices */
52 static struct nand_ecclayout nand_oob_8 = {
62 static struct nand_ecclayout nand_oob_16 = {
64 .eccpos = {0, 1, 2, 3, 6, 7},
70 static struct nand_ecclayout nand_oob_64 = {
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
81 static struct nand_ecclayout nand_oob_128 = {
84 80, 81, 82, 83, 84, 85, 86, 87,
85 88, 89, 90, 91, 92, 93, 94, 95,
86 96, 97, 98, 99, 100, 101, 102, 103,
87 104, 105, 106, 107, 108, 109, 110, 111,
88 112, 113, 114, 115, 116, 117, 118, 119,
89 120, 121, 122, 123, 124, 125, 126, 127},
95 static int nand_get_device(struct mtd_info *mtd, int new_state);
97 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
98 struct mtd_oob_ops *ops);
101 * For devices which display every fart in the system on a separate LED. Is
102 * compiled away when LED support is disabled.
104 DEFINE_LED_TRIGGER(nand_led_trigger);
106 static int check_offs_len(struct mtd_info *mtd,
107 loff_t ofs, uint64_t len)
109 struct nand_chip *chip = mtd->priv;
112 /* Start address must align on block boundary */
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
114 pr_debug("%s: unaligned address\n", __func__);
118 /* Length must align on block boundary */
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
120 pr_debug("%s: length not block aligned\n", __func__);
128 * nand_release_device - [GENERIC] release chip
129 * @mtd: MTD device structure
131 * Release chip lock and wake up anyone waiting on the device.
133 static void nand_release_device(struct mtd_info *mtd)
135 struct nand_chip *chip = mtd->priv;
137 /* Release the controller and the chip */
138 spin_lock(&chip->controller->lock);
139 chip->controller->active = NULL;
140 chip->state = FL_READY;
141 wake_up(&chip->controller->wq);
142 spin_unlock(&chip->controller->lock);
146 * nand_read_byte - [DEFAULT] read one byte from the chip
147 * @mtd: MTD device structure
149 * Default read function for 8bit buswidth
151 static uint8_t nand_read_byte(struct mtd_info *mtd)
153 struct nand_chip *chip = mtd->priv;
154 return readb(chip->IO_ADDR_R);
158 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
159 * @mtd: MTD device structure
161 * Default read function for 16bit buswidth with endianness conversion.
164 static uint8_t nand_read_byte16(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
167 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
171 * nand_read_word - [DEFAULT] read one word from the chip
172 * @mtd: MTD device structure
174 * Default read function for 16bit buswidth without endianness conversion.
176 static u16 nand_read_word(struct mtd_info *mtd)
178 struct nand_chip *chip = mtd->priv;
179 return readw(chip->IO_ADDR_R);
183 * nand_select_chip - [DEFAULT] control CE line
184 * @mtd: MTD device structure
185 * @chipnr: chipnumber to select, -1 for deselect
187 * Default select function for 1 chip devices.
189 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
191 struct nand_chip *chip = mtd->priv;
195 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
206 * nand_write_byte - [DEFAULT] write single byte to chip
207 * @mtd: MTD device structure
208 * @byte: value to write
210 * Default function to write a byte to I/O[7:0]
212 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
214 struct nand_chip *chip = mtd->priv;
216 chip->write_buf(mtd, &byte, 1);
220 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
221 * @mtd: MTD device structure
222 * @byte: value to write
224 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
226 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
228 struct nand_chip *chip = mtd->priv;
229 uint16_t word = byte;
232 * It's not entirely clear what should happen to I/O[15:8] when writing
233 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
235 * When the host supports a 16-bit bus width, only data is
236 * transferred at the 16-bit width. All address and command line
237 * transfers shall use only the lower 8-bits of the data bus. During
238 * command transfers, the host may place any value on the upper
239 * 8-bits of the data bus. During address transfers, the host shall
240 * set the upper 8-bits of the data bus to 00h.
242 * One user of the write_byte callback is nand_onfi_set_features. The
243 * four parameters are specified to be written to I/O[7:0], but this is
244 * neither an address nor a command transfer. Let's assume a 0 on the
245 * upper I/O lines is OK.
247 chip->write_buf(mtd, (uint8_t *)&word, 2);
251 * nand_write_buf - [DEFAULT] write buffer to chip
252 * @mtd: MTD device structure
254 * @len: number of bytes to write
256 * Default write function for 8bit buswidth.
258 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 iowrite8_rep(chip->IO_ADDR_W, buf, len);
266 * nand_read_buf - [DEFAULT] read chip data into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
271 * Default read function for 8bit buswidth.
273 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
277 ioread8_rep(chip->IO_ADDR_R, buf, len);
281 * nand_write_buf16 - [DEFAULT] write buffer to chip
282 * @mtd: MTD device structure
284 * @len: number of bytes to write
286 * Default write function for 16bit buswidth.
288 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
290 struct nand_chip *chip = mtd->priv;
291 u16 *p = (u16 *) buf;
293 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
297 * nand_read_buf16 - [DEFAULT] read chip data into buffer
298 * @mtd: MTD device structure
299 * @buf: buffer to store date
300 * @len: number of bytes to read
302 * Default read function for 16bit buswidth.
304 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
309 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
313 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
314 * @mtd: MTD device structure
315 * @ofs: offset from device start
316 * @getchip: 0, if the chip is already selected
318 * Check, if the block is bad.
320 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
322 int page, chipnr, res = 0, i = 0;
323 struct nand_chip *chip = mtd->priv;
326 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
327 ofs += mtd->erasesize - mtd->writesize;
329 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
332 chipnr = (int)(ofs >> chip->chip_shift);
334 nand_get_device(mtd, FL_READING);
336 /* Select the NAND device */
337 chip->select_chip(mtd, chipnr);
341 if (chip->options & NAND_BUSWIDTH_16) {
342 chip->cmdfunc(mtd, NAND_CMD_READOOB,
343 chip->badblockpos & 0xFE, page);
344 bad = cpu_to_le16(chip->read_word(mtd));
345 if (chip->badblockpos & 0x1)
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
352 bad = chip->read_byte(mtd);
355 if (likely(chip->badblockbits == 8))
358 res = hweight8(bad) < chip->badblockbits;
359 ofs += mtd->writesize;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
362 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
365 chip->select_chip(mtd, -1);
366 nand_release_device(mtd);
373 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
374 * @mtd: MTD device structure
375 * @ofs: offset from device start
377 * This is the default implementation, which can be overridden by a hardware
378 * specific driver. It provides the details for writing a bad block marker to a
381 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
383 struct nand_chip *chip = mtd->priv;
384 struct mtd_oob_ops ops;
385 uint8_t buf[2] = { 0, 0 };
386 int ret = 0, res, i = 0;
388 memset(&ops, 0, sizeof(ops));
390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
395 ops.len = ops.ooblen = 1;
397 ops.mode = MTD_OPS_PLACE_OOB;
399 /* Write to first/last page(s) if necessary */
400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 ofs += mtd->erasesize - mtd->writesize;
403 res = nand_do_write_oob(mtd, ofs, &ops);
408 ofs += mtd->writesize;
409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
415 * nand_block_markbad_lowlevel - mark a block bad
416 * @mtd: MTD device structure
417 * @ofs: offset from device start
419 * This function performs the generic NAND bad block marking steps (i.e., bad
420 * block table(s) and/or marker(s)). We only allow the hardware driver to
421 * specify how to write bad block markers to OOB (chip->block_markbad).
423 * We try operations in the following order:
424 * (1) erase the affected block, to allow OOB marker to be written cleanly
425 * (2) write bad block marker to OOB area of affected block (unless flag
426 * NAND_BBT_NO_OOB_BBM is present)
428 * Note that we retain the first error encountered in (2) or (3), finish the
429 * procedures, and dump the error in the end.
431 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
433 struct nand_chip *chip = mtd->priv;
436 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
437 struct erase_info einfo;
439 /* Attempt erase before marking OOB */
440 memset(&einfo, 0, sizeof(einfo));
443 einfo.len = 1ULL << chip->phys_erase_shift;
444 nand_erase_nand(mtd, &einfo, 0);
446 /* Write bad block marker to OOB */
447 nand_get_device(mtd, FL_WRITING);
448 ret = chip->block_markbad(mtd, ofs);
449 nand_release_device(mtd);
452 /* Mark block bad in BBT */
454 res = nand_markbad_bbt(mtd, ofs);
460 mtd->ecc_stats.badblocks++;
466 * nand_check_wp - [GENERIC] check if the chip is write protected
467 * @mtd: MTD device structure
469 * Check, if the device is write protected. The function expects, that the
470 * device is already selected.
472 static int nand_check_wp(struct mtd_info *mtd)
474 struct nand_chip *chip = mtd->priv;
476 /* Broken xD cards report WP despite being writable */
477 if (chip->options & NAND_BROKEN_XD)
480 /* Check the WP bit */
481 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
482 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
486 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
487 * @mtd: MTD device structure
488 * @ofs: offset from device start
490 * Check if the block is marked as reserved.
492 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
494 struct nand_chip *chip = mtd->priv;
498 /* Return info from the table */
499 return nand_isreserved_bbt(mtd, ofs);
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
512 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
515 struct nand_chip *chip = mtd->priv;
518 return chip->block_bad(mtd, ofs, getchip);
520 /* Return info from the table */
521 return nand_isbad_bbt(mtd, ofs, allowbbt);
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
526 * @mtd: MTD device structure
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
532 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
534 struct nand_chip *chip = mtd->priv;
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
541 touch_softlockup_watchdog();
547 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
548 * @mtd: MTD device structure
550 * Wait for the ready pin after a command, and warn if a timeout occurs.
552 void nand_wait_ready(struct mtd_info *mtd)
554 struct nand_chip *chip = mtd->priv;
555 unsigned long timeo = 400;
557 if (in_interrupt() || oops_in_progress)
558 return panic_nand_wait_ready(mtd, timeo);
560 led_trigger_event(nand_led_trigger, LED_FULL);
561 /* Wait until command is processed or timeout occurs */
562 timeo = jiffies + msecs_to_jiffies(timeo);
564 if (chip->dev_ready(mtd))
567 } while (time_before(jiffies, timeo));
570 "timeout while waiting for chip to become ready\n");
572 led_trigger_event(nand_led_trigger, LED_OFF);
574 EXPORT_SYMBOL_GPL(nand_wait_ready);
577 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
578 * @mtd: MTD device structure
579 * @timeo: Timeout in ms
581 * Wait for status ready (i.e. command done) or timeout.
583 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
585 register struct nand_chip *chip = mtd->priv;
587 timeo = jiffies + msecs_to_jiffies(timeo);
589 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
591 touch_softlockup_watchdog();
592 } while (time_before(jiffies, timeo));
596 * nand_command - [DEFAULT] Send command to NAND device
597 * @mtd: MTD device structure
598 * @command: the command to be sent
599 * @column: the column address for this command, -1 if none
600 * @page_addr: the page address for this command, -1 if none
602 * Send command to NAND device. This function is used for small page devices
603 * (512 Bytes per page).
605 static void nand_command(struct mtd_info *mtd, unsigned int command,
606 int column, int page_addr)
608 register struct nand_chip *chip = mtd->priv;
609 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
611 /* Write out the command to the device */
612 if (command == NAND_CMD_SEQIN) {
615 if (column >= mtd->writesize) {
617 column -= mtd->writesize;
618 readcmd = NAND_CMD_READOOB;
619 } else if (column < 256) {
620 /* First 256 bytes --> READ0 */
621 readcmd = NAND_CMD_READ0;
624 readcmd = NAND_CMD_READ1;
626 chip->cmd_ctrl(mtd, readcmd, ctrl);
627 ctrl &= ~NAND_CTRL_CHANGE;
629 chip->cmd_ctrl(mtd, command, ctrl);
631 /* Address cycle, when necessary */
632 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
633 /* Serially input address */
635 /* Adjust columns for 16 bit buswidth */
636 if (chip->options & NAND_BUSWIDTH_16 &&
637 !nand_opcode_8bits(command))
639 chip->cmd_ctrl(mtd, column, ctrl);
640 ctrl &= ~NAND_CTRL_CHANGE;
642 if (page_addr != -1) {
643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 ctrl &= ~NAND_CTRL_CHANGE;
645 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
646 /* One more address cycle for devices > 32MiB */
647 if (chip->chipsize > (32 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
650 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
653 * Program and erase have their own busy handlers status and sequential
658 case NAND_CMD_PAGEPROG:
659 case NAND_CMD_ERASE1:
660 case NAND_CMD_ERASE2:
662 case NAND_CMD_STATUS:
668 udelay(chip->chip_delay);
669 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
670 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
672 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
673 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
674 nand_wait_status_ready(mtd, 250);
677 /* This applies to read commands */
680 * If we don't have access to the busy pin, we apply the given
683 if (!chip->dev_ready) {
684 udelay(chip->chip_delay);
689 * Apply this short delay always to ensure that we do wait tWB in
690 * any case on any machine.
694 nand_wait_ready(mtd);
698 * nand_command_lp - [DEFAULT] Send command to NAND large page device
699 * @mtd: MTD device structure
700 * @command: the command to be sent
701 * @column: the column address for this command, -1 if none
702 * @page_addr: the page address for this command, -1 if none
704 * Send command to NAND device. This is the version for the new large page
705 * devices. We don't have the separate regions as we have in the small page
706 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
708 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
709 int column, int page_addr)
711 register struct nand_chip *chip = mtd->priv;
713 /* Emulate NAND_CMD_READOOB */
714 if (command == NAND_CMD_READOOB) {
715 column += mtd->writesize;
716 command = NAND_CMD_READ0;
719 /* Command latch cycle */
720 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
722 if (column != -1 || page_addr != -1) {
723 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
725 /* Serially input address */
727 /* Adjust columns for 16 bit buswidth */
728 if (chip->options & NAND_BUSWIDTH_16 &&
729 !nand_opcode_8bits(command))
731 chip->cmd_ctrl(mtd, column, ctrl);
732 ctrl &= ~NAND_CTRL_CHANGE;
733 chip->cmd_ctrl(mtd, column >> 8, ctrl);
735 if (page_addr != -1) {
736 chip->cmd_ctrl(mtd, page_addr, ctrl);
737 chip->cmd_ctrl(mtd, page_addr >> 8,
738 NAND_NCE | NAND_ALE);
739 /* One more address cycle for devices > 128MiB */
740 if (chip->chipsize > (128 << 20))
741 chip->cmd_ctrl(mtd, page_addr >> 16,
742 NAND_NCE | NAND_ALE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
748 * Program and erase have their own busy handlers status, sequential
749 * in and status need no delay.
753 case NAND_CMD_CACHEDPROG:
754 case NAND_CMD_PAGEPROG:
755 case NAND_CMD_ERASE1:
756 case NAND_CMD_ERASE2:
759 case NAND_CMD_STATUS:
765 udelay(chip->chip_delay);
766 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
767 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
768 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
769 NAND_NCE | NAND_CTRL_CHANGE);
770 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
771 nand_wait_status_ready(mtd, 250);
774 case NAND_CMD_RNDOUT:
775 /* No ready / busy check necessary */
776 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
777 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
778 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
779 NAND_NCE | NAND_CTRL_CHANGE);
783 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
784 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
785 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
786 NAND_NCE | NAND_CTRL_CHANGE);
788 /* This applies to read commands */
791 * If we don't have access to the busy pin, we apply the given
794 if (!chip->dev_ready) {
795 udelay(chip->chip_delay);
801 * Apply this short delay always to ensure that we do wait tWB in
802 * any case on any machine.
806 nand_wait_ready(mtd);
810 * panic_nand_get_device - [GENERIC] Get chip for selected access
811 * @chip: the nand chip descriptor
812 * @mtd: MTD device structure
813 * @new_state: the state which is requested
815 * Used when in panic, no locks are taken.
817 static void panic_nand_get_device(struct nand_chip *chip,
818 struct mtd_info *mtd, int new_state)
820 /* Hardware controller shared among independent devices */
821 chip->controller->active = chip;
822 chip->state = new_state;
826 * nand_get_device - [GENERIC] Get chip for selected access
827 * @mtd: MTD device structure
828 * @new_state: the state which is requested
830 * Get the device and lock it for exclusive access
833 nand_get_device(struct mtd_info *mtd, int new_state)
835 struct nand_chip *chip = mtd->priv;
836 spinlock_t *lock = &chip->controller->lock;
837 wait_queue_head_t *wq = &chip->controller->wq;
838 DECLARE_WAITQUEUE(wait, current);
842 /* Hardware controller shared among independent devices */
843 if (!chip->controller->active)
844 chip->controller->active = chip;
846 if (chip->controller->active == chip && chip->state == FL_READY) {
847 chip->state = new_state;
851 if (new_state == FL_PM_SUSPENDED) {
852 if (chip->controller->active->state == FL_PM_SUSPENDED) {
853 chip->state = FL_PM_SUSPENDED;
858 set_current_state(TASK_UNINTERRUPTIBLE);
859 add_wait_queue(wq, &wait);
862 remove_wait_queue(wq, &wait);
867 * panic_nand_wait - [GENERIC] wait until the command is done
868 * @mtd: MTD device structure
869 * @chip: NAND chip structure
872 * Wait for command done. This is a helper function for nand_wait used when
873 * we are in interrupt context. May happen when in panic and trying to write
874 * an oops through mtdoops.
876 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
880 for (i = 0; i < timeo; i++) {
881 if (chip->dev_ready) {
882 if (chip->dev_ready(mtd))
885 if (chip->read_byte(mtd) & NAND_STATUS_READY)
893 * nand_wait - [DEFAULT] wait until the command is done
894 * @mtd: MTD device structure
895 * @chip: NAND chip structure
897 * Wait for command done. This applies to erase and program only.
899 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
903 unsigned long timeo = 400;
905 led_trigger_event(nand_led_trigger, LED_FULL);
908 * Apply this short delay always to ensure that we do wait tWB in any
909 * case on any machine.
913 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
915 if (in_interrupt() || oops_in_progress)
916 panic_nand_wait(mtd, chip, timeo);
918 timeo = jiffies + msecs_to_jiffies(timeo);
920 if (chip->dev_ready) {
921 if (chip->dev_ready(mtd))
924 if (chip->read_byte(mtd) & NAND_STATUS_READY)
928 } while (time_before(jiffies, timeo));
930 led_trigger_event(nand_led_trigger, LED_OFF);
932 status = (int)chip->read_byte(mtd);
933 /* This can happen if in case of timeout or buggy dev_ready */
934 WARN_ON(!(status & NAND_STATUS_READY));
939 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
941 * @ofs: offset to start unlock from
942 * @len: length to unlock
943 * @invert: when = 0, unlock the range of blocks within the lower and
944 * upper boundary address
945 * when = 1, unlock the range of blocks outside the boundaries
946 * of the lower and upper boundary address
948 * Returs unlock status.
950 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
951 uint64_t len, int invert)
955 struct nand_chip *chip = mtd->priv;
957 /* Submit address of first page to unlock */
958 page = ofs >> chip->page_shift;
959 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
961 /* Submit address of last page to unlock */
962 page = (ofs + len) >> chip->page_shift;
963 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
964 (page | invert) & chip->pagemask);
966 /* Call wait ready function */
967 status = chip->waitfunc(mtd, chip);
968 /* See if device thinks it succeeded */
969 if (status & NAND_STATUS_FAIL) {
970 pr_debug("%s: error status = 0x%08x\n",
979 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
981 * @ofs: offset to start unlock from
982 * @len: length to unlock
984 * Returns unlock status.
986 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
990 struct nand_chip *chip = mtd->priv;
992 pr_debug("%s: start = 0x%012llx, len = %llu\n",
993 __func__, (unsigned long long)ofs, len);
995 if (check_offs_len(mtd, ofs, len))
998 /* Align to last block address if size addresses end of the device */
999 if (ofs + len == mtd->size)
1000 len -= mtd->erasesize;
1002 nand_get_device(mtd, FL_UNLOCKING);
1004 /* Shift to get chip number */
1005 chipnr = ofs >> chip->chip_shift;
1007 chip->select_chip(mtd, chipnr);
1011 * If we want to check the WP through READ STATUS and check the bit 7
1012 * we must reset the chip
1013 * some operation can also clear the bit 7 of status register
1014 * eg. erase/program a locked block
1016 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1018 /* Check, if it is write protected */
1019 if (nand_check_wp(mtd)) {
1020 pr_debug("%s: device is write protected!\n",
1026 ret = __nand_unlock(mtd, ofs, len, 0);
1029 chip->select_chip(mtd, -1);
1030 nand_release_device(mtd);
1034 EXPORT_SYMBOL(nand_unlock);
1037 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1039 * @ofs: offset to start unlock from
1040 * @len: length to unlock
1042 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1043 * have this feature, but it allows only to lock all blocks, not for specified
1044 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1047 * Returns lock status.
1049 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1052 int chipnr, status, page;
1053 struct nand_chip *chip = mtd->priv;
1055 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1056 __func__, (unsigned long long)ofs, len);
1058 if (check_offs_len(mtd, ofs, len))
1061 nand_get_device(mtd, FL_LOCKING);
1063 /* Shift to get chip number */
1064 chipnr = ofs >> chip->chip_shift;
1066 chip->select_chip(mtd, chipnr);
1070 * If we want to check the WP through READ STATUS and check the bit 7
1071 * we must reset the chip
1072 * some operation can also clear the bit 7 of status register
1073 * eg. erase/program a locked block
1075 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1077 /* Check, if it is write protected */
1078 if (nand_check_wp(mtd)) {
1079 pr_debug("%s: device is write protected!\n",
1081 status = MTD_ERASE_FAILED;
1086 /* Submit address of first page to lock */
1087 page = ofs >> chip->page_shift;
1088 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1090 /* Call wait ready function */
1091 status = chip->waitfunc(mtd, chip);
1092 /* See if device thinks it succeeded */
1093 if (status & NAND_STATUS_FAIL) {
1094 pr_debug("%s: error status = 0x%08x\n",
1100 ret = __nand_unlock(mtd, ofs, len, 0x1);
1103 chip->select_chip(mtd, -1);
1104 nand_release_device(mtd);
1108 EXPORT_SYMBOL(nand_lock);
1111 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1112 * @buf: buffer to test
1113 * @len: buffer length
1114 * @bitflips_threshold: maximum number of bitflips
1116 * Check if a buffer contains only 0xff, which means the underlying region
1117 * has been erased and is ready to be programmed.
1118 * The bitflips_threshold specify the maximum number of bitflips before
1119 * considering the region is not erased.
1120 * Note: The logic of this function has been extracted from the memweight
1121 * implementation, except that nand_check_erased_buf function exit before
1122 * testing the whole buffer if the number of bitflips exceed the
1123 * bitflips_threshold value.
1125 * Returns a positive number of bitflips less than or equal to
1126 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1129 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1131 const unsigned char *bitmap = buf;
1135 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1137 weight = hweight8(*bitmap);
1138 bitflips += BITS_PER_BYTE - weight;
1139 if (unlikely(bitflips > bitflips_threshold))
1143 for (; len >= sizeof(long);
1144 len -= sizeof(long), bitmap += sizeof(long)) {
1145 weight = hweight_long(*((unsigned long *)bitmap));
1146 bitflips += BITS_PER_LONG - weight;
1147 if (unlikely(bitflips > bitflips_threshold))
1151 for (; len > 0; len--, bitmap++) {
1152 weight = hweight8(*bitmap);
1153 bitflips += BITS_PER_BYTE - weight;
1154 if (unlikely(bitflips > bitflips_threshold))
1162 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1164 * @data: data buffer to test
1165 * @datalen: data length
1167 * @ecclen: ECC length
1168 * @extraoob: extra OOB buffer
1169 * @extraooblen: extra OOB length
1170 * @bitflips_threshold: maximum number of bitflips
1172 * Check if a data buffer and its associated ECC and OOB data contains only
1173 * 0xff pattern, which means the underlying region has been erased and is
1174 * ready to be programmed.
1175 * The bitflips_threshold specify the maximum number of bitflips before
1176 * considering the region as not erased.
1179 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1180 * different from the NAND page size. When fixing bitflips, ECC engines will
1181 * report the number of errors per chunk, and the NAND core infrastructure
1182 * expect you to return the maximum number of bitflips for the whole page.
1183 * This is why you should always use this function on a single chunk and
1184 * not on the whole page. After checking each chunk you should update your
1185 * max_bitflips value accordingly.
1186 * 2/ When checking for bitflips in erased pages you should not only check
1187 * the payload data but also their associated ECC data, because a user might
1188 * have programmed almost all bits to 1 but a few. In this case, we
1189 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1191 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1192 * data are protected by the ECC engine.
1193 * It could also be used if you support subpages and want to attach some
1194 * extra OOB data to an ECC chunk.
1196 * Returns a positive number of bitflips less than or equal to
1197 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1198 * threshold. In case of success, the passed buffers are filled with 0xff.
1200 int nand_check_erased_ecc_chunk(void *data, int datalen,
1201 void *ecc, int ecclen,
1202 void *extraoob, int extraooblen,
1203 int bitflips_threshold)
1205 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1207 data_bitflips = nand_check_erased_buf(data, datalen,
1208 bitflips_threshold);
1209 if (data_bitflips < 0)
1210 return data_bitflips;
1212 bitflips_threshold -= data_bitflips;
1214 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1215 if (ecc_bitflips < 0)
1216 return ecc_bitflips;
1218 bitflips_threshold -= ecc_bitflips;
1220 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1221 bitflips_threshold);
1222 if (extraoob_bitflips < 0)
1223 return extraoob_bitflips;
1226 memset(data, 0xff, datalen);
1229 memset(ecc, 0xff, ecclen);
1231 if (extraoob_bitflips)
1232 memset(extraoob, 0xff, extraooblen);
1234 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1236 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1239 * nand_read_page_raw - [INTERN] read raw page data without ecc
1240 * @mtd: mtd info structure
1241 * @chip: nand chip info structure
1242 * @buf: buffer to store read data
1243 * @oob_required: caller requires OOB data read to chip->oob_poi
1244 * @page: page number to read
1246 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1248 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1249 uint8_t *buf, int oob_required, int page)
1251 chip->read_buf(mtd, buf, mtd->writesize);
1253 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1258 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1259 * @mtd: mtd info structure
1260 * @chip: nand chip info structure
1261 * @buf: buffer to store read data
1262 * @oob_required: caller requires OOB data read to chip->oob_poi
1263 * @page: page number to read
1265 * We need a special oob layout and handling even when OOB isn't used.
1267 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1268 struct nand_chip *chip, uint8_t *buf,
1269 int oob_required, int page)
1271 int eccsize = chip->ecc.size;
1272 int eccbytes = chip->ecc.bytes;
1273 uint8_t *oob = chip->oob_poi;
1276 for (steps = chip->ecc.steps; steps > 0; steps--) {
1277 chip->read_buf(mtd, buf, eccsize);
1280 if (chip->ecc.prepad) {
1281 chip->read_buf(mtd, oob, chip->ecc.prepad);
1282 oob += chip->ecc.prepad;
1285 chip->read_buf(mtd, oob, eccbytes);
1288 if (chip->ecc.postpad) {
1289 chip->read_buf(mtd, oob, chip->ecc.postpad);
1290 oob += chip->ecc.postpad;
1294 size = mtd->oobsize - (oob - chip->oob_poi);
1296 chip->read_buf(mtd, oob, size);
1302 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1303 * @mtd: mtd info structure
1304 * @chip: nand chip info structure
1305 * @buf: buffer to store read data
1306 * @oob_required: caller requires OOB data read to chip->oob_poi
1307 * @page: page number to read
1309 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1310 uint8_t *buf, int oob_required, int page)
1312 int i, eccsize = chip->ecc.size;
1313 int eccbytes = chip->ecc.bytes;
1314 int eccsteps = chip->ecc.steps;
1316 uint8_t *ecc_calc = chip->buffers->ecccalc;
1317 uint8_t *ecc_code = chip->buffers->ecccode;
1318 uint32_t *eccpos = chip->ecc.layout->eccpos;
1319 unsigned int max_bitflips = 0;
1321 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1324 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1326 for (i = 0; i < chip->ecc.total; i++)
1327 ecc_code[i] = chip->oob_poi[eccpos[i]];
1329 eccsteps = chip->ecc.steps;
1332 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1335 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1337 mtd->ecc_stats.failed++;
1339 mtd->ecc_stats.corrected += stat;
1340 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1343 return max_bitflips;
1347 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1348 * @mtd: mtd info structure
1349 * @chip: nand chip info structure
1350 * @data_offs: offset of requested data within the page
1351 * @readlen: data length
1352 * @bufpoi: buffer to store read data
1353 * @page: page number to read
1355 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1356 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1359 int start_step, end_step, num_steps;
1360 uint32_t *eccpos = chip->ecc.layout->eccpos;
1362 int data_col_addr, i, gaps = 0;
1363 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1364 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1366 unsigned int max_bitflips = 0;
1368 /* Column address within the page aligned to ECC size (256bytes) */
1369 start_step = data_offs / chip->ecc.size;
1370 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1371 num_steps = end_step - start_step + 1;
1372 index = start_step * chip->ecc.bytes;
1374 /* Data size aligned to ECC ecc.size */
1375 datafrag_len = num_steps * chip->ecc.size;
1376 eccfrag_len = num_steps * chip->ecc.bytes;
1378 data_col_addr = start_step * chip->ecc.size;
1379 /* If we read not a page aligned data */
1380 if (data_col_addr != 0)
1381 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1383 p = bufpoi + data_col_addr;
1384 chip->read_buf(mtd, p, datafrag_len);
1387 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1388 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1391 * The performance is faster if we position offsets according to
1392 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1394 for (i = 0; i < eccfrag_len - 1; i++) {
1395 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
1401 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1402 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1405 * Send the command to read the particular ECC bytes take care
1406 * about buswidth alignment in read_buf.
1408 aligned_pos = eccpos[index] & ~(busw - 1);
1409 aligned_len = eccfrag_len;
1410 if (eccpos[index] & (busw - 1))
1412 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1415 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1416 mtd->writesize + aligned_pos, -1);
1417 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1420 for (i = 0; i < eccfrag_len; i++)
1421 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1423 p = bufpoi + data_col_addr;
1424 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1427 stat = chip->ecc.correct(mtd, p,
1428 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1430 mtd->ecc_stats.failed++;
1432 mtd->ecc_stats.corrected += stat;
1433 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1436 return max_bitflips;
1440 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1441 * @mtd: mtd info structure
1442 * @chip: nand chip info structure
1443 * @buf: buffer to store read data
1444 * @oob_required: caller requires OOB data read to chip->oob_poi
1445 * @page: page number to read
1447 * Not for syndrome calculating ECC controllers which need a special oob layout.
1449 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1450 uint8_t *buf, int oob_required, int page)
1452 int i, eccsize = chip->ecc.size;
1453 int eccbytes = chip->ecc.bytes;
1454 int eccsteps = chip->ecc.steps;
1456 uint8_t *ecc_calc = chip->buffers->ecccalc;
1457 uint8_t *ecc_code = chip->buffers->ecccode;
1458 uint32_t *eccpos = chip->ecc.layout->eccpos;
1459 unsigned int max_bitflips = 0;
1461 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1462 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1463 chip->read_buf(mtd, p, eccsize);
1464 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1466 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1468 for (i = 0; i < chip->ecc.total; i++)
1469 ecc_code[i] = chip->oob_poi[eccpos[i]];
1471 eccsteps = chip->ecc.steps;
1474 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1477 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1479 mtd->ecc_stats.failed++;
1481 mtd->ecc_stats.corrected += stat;
1482 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1485 return max_bitflips;
1489 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1490 * @mtd: mtd info structure
1491 * @chip: nand chip info structure
1492 * @buf: buffer to store read data
1493 * @oob_required: caller requires OOB data read to chip->oob_poi
1494 * @page: page number to read
1496 * Hardware ECC for large page chips, require OOB to be read first. For this
1497 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1498 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1499 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1500 * the data area, by overwriting the NAND manufacturer bad block markings.
1502 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1503 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1505 int i, eccsize = chip->ecc.size;
1506 int eccbytes = chip->ecc.bytes;
1507 int eccsteps = chip->ecc.steps;
1509 uint8_t *ecc_code = chip->buffers->ecccode;
1510 uint32_t *eccpos = chip->ecc.layout->eccpos;
1511 uint8_t *ecc_calc = chip->buffers->ecccalc;
1512 unsigned int max_bitflips = 0;
1514 /* Read the OOB area first */
1515 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1516 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1517 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1519 for (i = 0; i < chip->ecc.total; i++)
1520 ecc_code[i] = chip->oob_poi[eccpos[i]];
1522 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1525 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1526 chip->read_buf(mtd, p, eccsize);
1527 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1529 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1531 mtd->ecc_stats.failed++;
1533 mtd->ecc_stats.corrected += stat;
1534 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1537 return max_bitflips;
1541 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1542 * @mtd: mtd info structure
1543 * @chip: nand chip info structure
1544 * @buf: buffer to store read data
1545 * @oob_required: caller requires OOB data read to chip->oob_poi
1546 * @page: page number to read
1548 * The hw generator calculates the error syndrome automatically. Therefore we
1549 * need a special oob layout and handling.
1551 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1552 uint8_t *buf, int oob_required, int page)
1554 int i, eccsize = chip->ecc.size;
1555 int eccbytes = chip->ecc.bytes;
1556 int eccsteps = chip->ecc.steps;
1558 uint8_t *oob = chip->oob_poi;
1559 unsigned int max_bitflips = 0;
1561 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1564 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1565 chip->read_buf(mtd, p, eccsize);
1567 if (chip->ecc.prepad) {
1568 chip->read_buf(mtd, oob, chip->ecc.prepad);
1569 oob += chip->ecc.prepad;
1572 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1573 chip->read_buf(mtd, oob, eccbytes);
1574 stat = chip->ecc.correct(mtd, p, oob, NULL);
1577 mtd->ecc_stats.failed++;
1579 mtd->ecc_stats.corrected += stat;
1580 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1585 if (chip->ecc.postpad) {
1586 chip->read_buf(mtd, oob, chip->ecc.postpad);
1587 oob += chip->ecc.postpad;
1591 /* Calculate remaining oob bytes */
1592 i = mtd->oobsize - (oob - chip->oob_poi);
1594 chip->read_buf(mtd, oob, i);
1596 return max_bitflips;
1600 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1601 * @chip: nand chip structure
1602 * @oob: oob destination address
1603 * @ops: oob ops structure
1604 * @len: size of oob to transfer
1606 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1607 struct mtd_oob_ops *ops, size_t len)
1609 switch (ops->mode) {
1611 case MTD_OPS_PLACE_OOB:
1613 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1616 case MTD_OPS_AUTO_OOB: {
1617 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1618 uint32_t boffs = 0, roffs = ops->ooboffs;
1621 for (; free->length && len; free++, len -= bytes) {
1622 /* Read request not from offset 0? */
1623 if (unlikely(roffs)) {
1624 if (roffs >= free->length) {
1625 roffs -= free->length;
1628 boffs = free->offset + roffs;
1629 bytes = min_t(size_t, len,
1630 (free->length - roffs));
1633 bytes = min_t(size_t, len, free->length);
1634 boffs = free->offset;
1636 memcpy(oob, chip->oob_poi + boffs, bytes);
1648 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1649 * @mtd: MTD device structure
1650 * @retry_mode: the retry mode to use
1652 * Some vendors supply a special command to shift the Vt threshold, to be used
1653 * when there are too many bitflips in a page (i.e., ECC error). After setting
1654 * a new threshold, the host should retry reading the page.
1656 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1658 struct nand_chip *chip = mtd->priv;
1660 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1662 if (retry_mode >= chip->read_retries)
1665 if (!chip->setup_read_retry)
1668 return chip->setup_read_retry(mtd, retry_mode);
1672 * nand_do_read_ops - [INTERN] Read data with ECC
1673 * @mtd: MTD device structure
1674 * @from: offset to read from
1675 * @ops: oob ops structure
1677 * Internal function. Called with chip held.
1679 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1680 struct mtd_oob_ops *ops)
1682 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1683 struct nand_chip *chip = mtd->priv;
1685 uint32_t readlen = ops->len;
1686 uint32_t oobreadlen = ops->ooblen;
1687 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1688 mtd->oobavail : mtd->oobsize;
1690 uint8_t *bufpoi, *oob, *buf;
1692 unsigned int max_bitflips = 0;
1694 bool ecc_fail = false;
1696 chipnr = (int)(from >> chip->chip_shift);
1697 chip->select_chip(mtd, chipnr);
1699 realpage = (int)(from >> chip->page_shift);
1700 page = realpage & chip->pagemask;
1702 col = (int)(from & (mtd->writesize - 1));
1706 oob_required = oob ? 1 : 0;
1709 unsigned int ecc_failures = mtd->ecc_stats.failed;
1711 bytes = min(mtd->writesize - col, readlen);
1712 aligned = (bytes == mtd->writesize);
1716 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1717 use_bufpoi = !virt_addr_valid(buf);
1721 /* Is the current page in the buffer? */
1722 if (realpage != chip->pagebuf || oob) {
1723 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1725 if (use_bufpoi && aligned)
1726 pr_debug("%s: using read bounce buffer for buf@%p\n",
1730 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1733 * Now read the page into the buffer. Absent an error,
1734 * the read methods return max bitflips per ecc step.
1736 if (unlikely(ops->mode == MTD_OPS_RAW))
1737 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1740 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1742 ret = chip->ecc.read_subpage(mtd, chip,
1746 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1747 oob_required, page);
1750 /* Invalidate page cache */
1755 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1757 /* Transfer not aligned data */
1759 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1760 !(mtd->ecc_stats.failed - ecc_failures) &&
1761 (ops->mode != MTD_OPS_RAW)) {
1762 chip->pagebuf = realpage;
1763 chip->pagebuf_bitflips = ret;
1765 /* Invalidate page cache */
1768 memcpy(buf, chip->buffers->databuf + col, bytes);
1771 if (unlikely(oob)) {
1772 int toread = min(oobreadlen, max_oobsize);
1775 oob = nand_transfer_oob(chip,
1777 oobreadlen -= toread;
1781 if (chip->options & NAND_NEED_READRDY) {
1782 /* Apply delay or wait for ready/busy pin */
1783 if (!chip->dev_ready)
1784 udelay(chip->chip_delay);
1786 nand_wait_ready(mtd);
1789 if (mtd->ecc_stats.failed - ecc_failures) {
1790 if (retry_mode + 1 < chip->read_retries) {
1792 ret = nand_setup_read_retry(mtd,
1797 /* Reset failures; retry */
1798 mtd->ecc_stats.failed = ecc_failures;
1801 /* No more retry modes; real failure */
1808 memcpy(buf, chip->buffers->databuf + col, bytes);
1810 max_bitflips = max_t(unsigned int, max_bitflips,
1811 chip->pagebuf_bitflips);
1816 /* Reset to retry mode 0 */
1818 ret = nand_setup_read_retry(mtd, 0);
1827 /* For subsequent reads align to page boundary */
1829 /* Increment page address */
1832 page = realpage & chip->pagemask;
1833 /* Check, if we cross a chip boundary */
1836 chip->select_chip(mtd, -1);
1837 chip->select_chip(mtd, chipnr);
1840 chip->select_chip(mtd, -1);
1842 ops->retlen = ops->len - (size_t) readlen;
1844 ops->oobretlen = ops->ooblen - oobreadlen;
1852 return max_bitflips;
1856 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1857 * @mtd: MTD device structure
1858 * @from: offset to read from
1859 * @len: number of bytes to read
1860 * @retlen: pointer to variable to store the number of read bytes
1861 * @buf: the databuffer to put data
1863 * Get hold of the chip and call nand_do_read.
1865 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1866 size_t *retlen, uint8_t *buf)
1868 struct mtd_oob_ops ops;
1871 nand_get_device(mtd, FL_READING);
1872 memset(&ops, 0, sizeof(ops));
1875 ops.mode = MTD_OPS_PLACE_OOB;
1876 ret = nand_do_read_ops(mtd, from, &ops);
1877 *retlen = ops.retlen;
1878 nand_release_device(mtd);
1883 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1884 * @mtd: mtd info structure
1885 * @chip: nand chip info structure
1886 * @page: page number to read
1888 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1891 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1892 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1897 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1899 * @mtd: mtd info structure
1900 * @chip: nand chip info structure
1901 * @page: page number to read
1903 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1906 int length = mtd->oobsize;
1907 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1908 int eccsize = chip->ecc.size;
1909 uint8_t *bufpoi = chip->oob_poi;
1910 int i, toread, sndrnd = 0, pos;
1912 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1913 for (i = 0; i < chip->ecc.steps; i++) {
1915 pos = eccsize + i * (eccsize + chunk);
1916 if (mtd->writesize > 512)
1917 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1919 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1922 toread = min_t(int, length, chunk);
1923 chip->read_buf(mtd, bufpoi, toread);
1928 chip->read_buf(mtd, bufpoi, length);
1934 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1935 * @mtd: mtd info structure
1936 * @chip: nand chip info structure
1937 * @page: page number to write
1939 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1943 const uint8_t *buf = chip->oob_poi;
1944 int length = mtd->oobsize;
1946 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1947 chip->write_buf(mtd, buf, length);
1948 /* Send command to program the OOB data */
1949 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1951 status = chip->waitfunc(mtd, chip);
1953 return status & NAND_STATUS_FAIL ? -EIO : 0;
1957 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1958 * with syndrome - only for large page flash
1959 * @mtd: mtd info structure
1960 * @chip: nand chip info structure
1961 * @page: page number to write
1963 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1964 struct nand_chip *chip, int page)
1966 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1967 int eccsize = chip->ecc.size, length = mtd->oobsize;
1968 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1969 const uint8_t *bufpoi = chip->oob_poi;
1972 * data-ecc-data-ecc ... ecc-oob
1974 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1976 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1977 pos = steps * (eccsize + chunk);
1982 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1983 for (i = 0; i < steps; i++) {
1985 if (mtd->writesize <= 512) {
1986 uint32_t fill = 0xFFFFFFFF;
1990 int num = min_t(int, len, 4);
1991 chip->write_buf(mtd, (uint8_t *)&fill,
1996 pos = eccsize + i * (eccsize + chunk);
1997 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2001 len = min_t(int, length, chunk);
2002 chip->write_buf(mtd, bufpoi, len);
2007 chip->write_buf(mtd, bufpoi, length);
2009 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2010 status = chip->waitfunc(mtd, chip);
2012 return status & NAND_STATUS_FAIL ? -EIO : 0;
2016 * nand_do_read_oob - [INTERN] NAND read out-of-band
2017 * @mtd: MTD device structure
2018 * @from: offset to read from
2019 * @ops: oob operations description structure
2021 * NAND read out-of-band data from the spare area.
2023 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2024 struct mtd_oob_ops *ops)
2026 int page, realpage, chipnr;
2027 struct nand_chip *chip = mtd->priv;
2028 struct mtd_ecc_stats stats;
2029 int readlen = ops->ooblen;
2031 uint8_t *buf = ops->oobbuf;
2034 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2035 __func__, (unsigned long long)from, readlen);
2037 stats = mtd->ecc_stats;
2039 if (ops->mode == MTD_OPS_AUTO_OOB)
2040 len = chip->ecc.layout->oobavail;
2044 if (unlikely(ops->ooboffs >= len)) {
2045 pr_debug("%s: attempt to start read outside oob\n",
2050 /* Do not allow reads past end of device */
2051 if (unlikely(from >= mtd->size ||
2052 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2053 (from >> chip->page_shift)) * len)) {
2054 pr_debug("%s: attempt to read beyond end of device\n",
2059 chipnr = (int)(from >> chip->chip_shift);
2060 chip->select_chip(mtd, chipnr);
2062 /* Shift to get page */
2063 realpage = (int)(from >> chip->page_shift);
2064 page = realpage & chip->pagemask;
2067 if (ops->mode == MTD_OPS_RAW)
2068 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2070 ret = chip->ecc.read_oob(mtd, chip, page);
2075 len = min(len, readlen);
2076 buf = nand_transfer_oob(chip, buf, ops, len);
2078 if (chip->options & NAND_NEED_READRDY) {
2079 /* Apply delay or wait for ready/busy pin */
2080 if (!chip->dev_ready)
2081 udelay(chip->chip_delay);
2083 nand_wait_ready(mtd);
2090 /* Increment page address */
2093 page = realpage & chip->pagemask;
2094 /* Check, if we cross a chip boundary */
2097 chip->select_chip(mtd, -1);
2098 chip->select_chip(mtd, chipnr);
2101 chip->select_chip(mtd, -1);
2103 ops->oobretlen = ops->ooblen - readlen;
2108 if (mtd->ecc_stats.failed - stats.failed)
2111 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2115 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2116 * @mtd: MTD device structure
2117 * @from: offset to read from
2118 * @ops: oob operation description structure
2120 * NAND read data and/or out-of-band data.
2122 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2123 struct mtd_oob_ops *ops)
2125 int ret = -ENOTSUPP;
2129 /* Do not allow reads past end of device */
2130 if (ops->datbuf && (from + ops->len) > mtd->size) {
2131 pr_debug("%s: attempt to read beyond end of device\n",
2136 nand_get_device(mtd, FL_READING);
2138 switch (ops->mode) {
2139 case MTD_OPS_PLACE_OOB:
2140 case MTD_OPS_AUTO_OOB:
2149 ret = nand_do_read_oob(mtd, from, ops);
2151 ret = nand_do_read_ops(mtd, from, ops);
2154 nand_release_device(mtd);
2160 * nand_write_page_raw - [INTERN] raw page write function
2161 * @mtd: mtd info structure
2162 * @chip: nand chip info structure
2164 * @oob_required: must write chip->oob_poi to OOB
2165 * @page: page number to write
2167 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2169 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2170 const uint8_t *buf, int oob_required, int page)
2172 chip->write_buf(mtd, buf, mtd->writesize);
2174 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2180 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2181 * @mtd: mtd info structure
2182 * @chip: nand chip info structure
2184 * @oob_required: must write chip->oob_poi to OOB
2185 * @page: page number to write
2187 * We need a special oob layout and handling even when ECC isn't checked.
2189 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2190 struct nand_chip *chip,
2191 const uint8_t *buf, int oob_required,
2194 int eccsize = chip->ecc.size;
2195 int eccbytes = chip->ecc.bytes;
2196 uint8_t *oob = chip->oob_poi;
2199 for (steps = chip->ecc.steps; steps > 0; steps--) {
2200 chip->write_buf(mtd, buf, eccsize);
2203 if (chip->ecc.prepad) {
2204 chip->write_buf(mtd, oob, chip->ecc.prepad);
2205 oob += chip->ecc.prepad;
2208 chip->write_buf(mtd, oob, eccbytes);
2211 if (chip->ecc.postpad) {
2212 chip->write_buf(mtd, oob, chip->ecc.postpad);
2213 oob += chip->ecc.postpad;
2217 size = mtd->oobsize - (oob - chip->oob_poi);
2219 chip->write_buf(mtd, oob, size);
2224 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2225 * @mtd: mtd info structure
2226 * @chip: nand chip info structure
2228 * @oob_required: must write chip->oob_poi to OOB
2229 * @page: page number to write
2231 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2232 const uint8_t *buf, int oob_required,
2235 int i, eccsize = chip->ecc.size;
2236 int eccbytes = chip->ecc.bytes;
2237 int eccsteps = chip->ecc.steps;
2238 uint8_t *ecc_calc = chip->buffers->ecccalc;
2239 const uint8_t *p = buf;
2240 uint32_t *eccpos = chip->ecc.layout->eccpos;
2242 /* Software ECC calculation */
2243 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2244 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2246 for (i = 0; i < chip->ecc.total; i++)
2247 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2249 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2253 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2254 * @mtd: mtd info structure
2255 * @chip: nand chip info structure
2257 * @oob_required: must write chip->oob_poi to OOB
2258 * @page: page number to write
2260 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2261 const uint8_t *buf, int oob_required,
2264 int i, eccsize = chip->ecc.size;
2265 int eccbytes = chip->ecc.bytes;
2266 int eccsteps = chip->ecc.steps;
2267 uint8_t *ecc_calc = chip->buffers->ecccalc;
2268 const uint8_t *p = buf;
2269 uint32_t *eccpos = chip->ecc.layout->eccpos;
2271 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2272 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2273 chip->write_buf(mtd, p, eccsize);
2274 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2277 for (i = 0; i < chip->ecc.total; i++)
2278 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2280 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2287 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2288 * @mtd: mtd info structure
2289 * @chip: nand chip info structure
2290 * @offset: column address of subpage within the page
2291 * @data_len: data length
2293 * @oob_required: must write chip->oob_poi to OOB
2294 * @page: page number to write
2296 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2297 struct nand_chip *chip, uint32_t offset,
2298 uint32_t data_len, const uint8_t *buf,
2299 int oob_required, int page)
2301 uint8_t *oob_buf = chip->oob_poi;
2302 uint8_t *ecc_calc = chip->buffers->ecccalc;
2303 int ecc_size = chip->ecc.size;
2304 int ecc_bytes = chip->ecc.bytes;
2305 int ecc_steps = chip->ecc.steps;
2306 uint32_t *eccpos = chip->ecc.layout->eccpos;
2307 uint32_t start_step = offset / ecc_size;
2308 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2309 int oob_bytes = mtd->oobsize / ecc_steps;
2312 for (step = 0; step < ecc_steps; step++) {
2313 /* configure controller for WRITE access */
2314 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2316 /* write data (untouched subpages already masked by 0xFF) */
2317 chip->write_buf(mtd, buf, ecc_size);
2319 /* mask ECC of un-touched subpages by padding 0xFF */
2320 if ((step < start_step) || (step > end_step))
2321 memset(ecc_calc, 0xff, ecc_bytes);
2323 chip->ecc.calculate(mtd, buf, ecc_calc);
2325 /* mask OOB of un-touched subpages by padding 0xFF */
2326 /* if oob_required, preserve OOB metadata of written subpage */
2327 if (!oob_required || (step < start_step) || (step > end_step))
2328 memset(oob_buf, 0xff, oob_bytes);
2331 ecc_calc += ecc_bytes;
2332 oob_buf += oob_bytes;
2335 /* copy calculated ECC for whole page to chip->buffer->oob */
2336 /* this include masked-value(0xFF) for unwritten subpages */
2337 ecc_calc = chip->buffers->ecccalc;
2338 for (i = 0; i < chip->ecc.total; i++)
2339 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2341 /* write OOB buffer to NAND device */
2342 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2349 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2350 * @mtd: mtd info structure
2351 * @chip: nand chip info structure
2353 * @oob_required: must write chip->oob_poi to OOB
2354 * @page: page number to write
2356 * The hw generator calculates the error syndrome automatically. Therefore we
2357 * need a special oob layout and handling.
2359 static int nand_write_page_syndrome(struct mtd_info *mtd,
2360 struct nand_chip *chip,
2361 const uint8_t *buf, int oob_required,
2364 int i, eccsize = chip->ecc.size;
2365 int eccbytes = chip->ecc.bytes;
2366 int eccsteps = chip->ecc.steps;
2367 const uint8_t *p = buf;
2368 uint8_t *oob = chip->oob_poi;
2370 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2372 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2373 chip->write_buf(mtd, p, eccsize);
2375 if (chip->ecc.prepad) {
2376 chip->write_buf(mtd, oob, chip->ecc.prepad);
2377 oob += chip->ecc.prepad;
2380 chip->ecc.calculate(mtd, p, oob);
2381 chip->write_buf(mtd, oob, eccbytes);
2384 if (chip->ecc.postpad) {
2385 chip->write_buf(mtd, oob, chip->ecc.postpad);
2386 oob += chip->ecc.postpad;
2390 /* Calculate remaining oob bytes */
2391 i = mtd->oobsize - (oob - chip->oob_poi);
2393 chip->write_buf(mtd, oob, i);
2399 * nand_write_page - [REPLACEABLE] write one page
2400 * @mtd: MTD device structure
2401 * @chip: NAND chip descriptor
2402 * @offset: address offset within the page
2403 * @data_len: length of actual data to be written
2404 * @buf: the data to write
2405 * @oob_required: must write chip->oob_poi to OOB
2406 * @page: page number to write
2407 * @cached: cached programming
2408 * @raw: use _raw version of write_page
2410 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2411 uint32_t offset, int data_len, const uint8_t *buf,
2412 int oob_required, int page, int cached, int raw)
2414 int status, subpage;
2416 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2417 chip->ecc.write_subpage)
2418 subpage = offset || (data_len < mtd->writesize);
2422 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2425 status = chip->ecc.write_page_raw(mtd, chip, buf,
2426 oob_required, page);
2428 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2429 buf, oob_required, page);
2431 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2438 * Cached progamming disabled for now. Not sure if it's worth the
2439 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2443 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2445 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2446 status = chip->waitfunc(mtd, chip);
2448 * See if operation failed and additional status checks are
2451 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2452 status = chip->errstat(mtd, chip, FL_WRITING, status,
2455 if (status & NAND_STATUS_FAIL)
2458 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2459 status = chip->waitfunc(mtd, chip);
2466 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2467 * @mtd: MTD device structure
2468 * @oob: oob data buffer
2469 * @len: oob data write length
2470 * @ops: oob ops structure
2472 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2473 struct mtd_oob_ops *ops)
2475 struct nand_chip *chip = mtd->priv;
2478 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2479 * data from a previous OOB read.
2481 memset(chip->oob_poi, 0xff, mtd->oobsize);
2483 switch (ops->mode) {
2485 case MTD_OPS_PLACE_OOB:
2487 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2490 case MTD_OPS_AUTO_OOB: {
2491 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2492 uint32_t boffs = 0, woffs = ops->ooboffs;
2495 for (; free->length && len; free++, len -= bytes) {
2496 /* Write request not from offset 0? */
2497 if (unlikely(woffs)) {
2498 if (woffs >= free->length) {
2499 woffs -= free->length;
2502 boffs = free->offset + woffs;
2503 bytes = min_t(size_t, len,
2504 (free->length - woffs));
2507 bytes = min_t(size_t, len, free->length);
2508 boffs = free->offset;
2510 memcpy(chip->oob_poi + boffs, oob, bytes);
2521 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2524 * nand_do_write_ops - [INTERN] NAND write with ECC
2525 * @mtd: MTD device structure
2526 * @to: offset to write to
2527 * @ops: oob operations description structure
2529 * NAND write with ECC.
2531 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2532 struct mtd_oob_ops *ops)
2534 int chipnr, realpage, page, blockmask, column;
2535 struct nand_chip *chip = mtd->priv;
2536 uint32_t writelen = ops->len;
2538 uint32_t oobwritelen = ops->ooblen;
2539 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2540 mtd->oobavail : mtd->oobsize;
2542 uint8_t *oob = ops->oobbuf;
2543 uint8_t *buf = ops->datbuf;
2545 int oob_required = oob ? 1 : 0;
2551 /* Reject writes, which are not page aligned */
2552 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2553 pr_notice("%s: attempt to write non page aligned data\n",
2558 column = to & (mtd->writesize - 1);
2560 chipnr = (int)(to >> chip->chip_shift);
2561 chip->select_chip(mtd, chipnr);
2563 /* Check, if it is write protected */
2564 if (nand_check_wp(mtd)) {
2569 realpage = (int)(to >> chip->page_shift);
2570 page = realpage & chip->pagemask;
2571 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2573 /* Invalidate the page cache, when we write to the cached page */
2574 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2575 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2578 /* Don't allow multipage oob writes with offset */
2579 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2585 int bytes = mtd->writesize;
2586 int cached = writelen > bytes && page != blockmask;
2587 uint8_t *wbuf = buf;
2589 int part_pagewr = (column || writelen < (mtd->writesize - 1));
2593 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2594 use_bufpoi = !virt_addr_valid(buf);
2598 /* Partial page write?, or need to use bounce buffer */
2600 pr_debug("%s: using write bounce buffer for buf@%p\n",
2604 bytes = min_t(int, bytes - column, writelen);
2606 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2607 memcpy(&chip->buffers->databuf[column], buf, bytes);
2608 wbuf = chip->buffers->databuf;
2611 if (unlikely(oob)) {
2612 size_t len = min(oobwritelen, oobmaxlen);
2613 oob = nand_fill_oob(mtd, oob, len, ops);
2616 /* We still need to erase leftover OOB data */
2617 memset(chip->oob_poi, 0xff, mtd->oobsize);
2619 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2620 oob_required, page, cached,
2621 (ops->mode == MTD_OPS_RAW));
2633 page = realpage & chip->pagemask;
2634 /* Check, if we cross a chip boundary */
2637 chip->select_chip(mtd, -1);
2638 chip->select_chip(mtd, chipnr);
2642 ops->retlen = ops->len - writelen;
2644 ops->oobretlen = ops->ooblen;
2647 chip->select_chip(mtd, -1);
2652 * panic_nand_write - [MTD Interface] NAND write with ECC
2653 * @mtd: MTD device structure
2654 * @to: offset to write to
2655 * @len: number of bytes to write
2656 * @retlen: pointer to variable to store the number of written bytes
2657 * @buf: the data to write
2659 * NAND write with ECC. Used when performing writes in interrupt context, this
2660 * may for example be called by mtdoops when writing an oops while in panic.
2662 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2663 size_t *retlen, const uint8_t *buf)
2665 struct nand_chip *chip = mtd->priv;
2666 struct mtd_oob_ops ops;
2669 /* Wait for the device to get ready */
2670 panic_nand_wait(mtd, chip, 400);
2672 /* Grab the device */
2673 panic_nand_get_device(chip, mtd, FL_WRITING);
2675 memset(&ops, 0, sizeof(ops));
2677 ops.datbuf = (uint8_t *)buf;
2678 ops.mode = MTD_OPS_PLACE_OOB;
2680 ret = nand_do_write_ops(mtd, to, &ops);
2682 *retlen = ops.retlen;
2687 * nand_write - [MTD Interface] NAND write with ECC
2688 * @mtd: MTD device structure
2689 * @to: offset to write to
2690 * @len: number of bytes to write
2691 * @retlen: pointer to variable to store the number of written bytes
2692 * @buf: the data to write
2694 * NAND write with ECC.
2696 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2697 size_t *retlen, const uint8_t *buf)
2699 struct mtd_oob_ops ops;
2702 nand_get_device(mtd, FL_WRITING);
2703 memset(&ops, 0, sizeof(ops));
2705 ops.datbuf = (uint8_t *)buf;
2706 ops.mode = MTD_OPS_PLACE_OOB;
2707 ret = nand_do_write_ops(mtd, to, &ops);
2708 *retlen = ops.retlen;
2709 nand_release_device(mtd);
2714 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2715 * @mtd: MTD device structure
2716 * @to: offset to write to
2717 * @ops: oob operation description structure
2719 * NAND write out-of-band.
2721 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2722 struct mtd_oob_ops *ops)
2724 int chipnr, page, status, len;
2725 struct nand_chip *chip = mtd->priv;
2727 pr_debug("%s: to = 0x%08x, len = %i\n",
2728 __func__, (unsigned int)to, (int)ops->ooblen);
2730 if (ops->mode == MTD_OPS_AUTO_OOB)
2731 len = chip->ecc.layout->oobavail;
2735 /* Do not allow write past end of page */
2736 if ((ops->ooboffs + ops->ooblen) > len) {
2737 pr_debug("%s: attempt to write past end of page\n",
2742 if (unlikely(ops->ooboffs >= len)) {
2743 pr_debug("%s: attempt to start write outside oob\n",
2748 /* Do not allow write past end of device */
2749 if (unlikely(to >= mtd->size ||
2750 ops->ooboffs + ops->ooblen >
2751 ((mtd->size >> chip->page_shift) -
2752 (to >> chip->page_shift)) * len)) {
2753 pr_debug("%s: attempt to write beyond end of device\n",
2758 chipnr = (int)(to >> chip->chip_shift);
2759 chip->select_chip(mtd, chipnr);
2761 /* Shift to get page */
2762 page = (int)(to >> chip->page_shift);
2765 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2766 * of my DiskOnChip 2000 test units) will clear the whole data page too
2767 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2768 * it in the doc2000 driver in August 1999. dwmw2.
2770 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2772 /* Check, if it is write protected */
2773 if (nand_check_wp(mtd)) {
2774 chip->select_chip(mtd, -1);
2778 /* Invalidate the page cache, if we write to the cached page */
2779 if (page == chip->pagebuf)
2782 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2784 if (ops->mode == MTD_OPS_RAW)
2785 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2787 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2789 chip->select_chip(mtd, -1);
2794 ops->oobretlen = ops->ooblen;
2800 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2801 * @mtd: MTD device structure
2802 * @to: offset to write to
2803 * @ops: oob operation description structure
2805 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2806 struct mtd_oob_ops *ops)
2808 int ret = -ENOTSUPP;
2812 /* Do not allow writes past end of device */
2813 if (ops->datbuf && (to + ops->len) > mtd->size) {
2814 pr_debug("%s: attempt to write beyond end of device\n",
2819 nand_get_device(mtd, FL_WRITING);
2821 switch (ops->mode) {
2822 case MTD_OPS_PLACE_OOB:
2823 case MTD_OPS_AUTO_OOB:
2832 ret = nand_do_write_oob(mtd, to, ops);
2834 ret = nand_do_write_ops(mtd, to, ops);
2837 nand_release_device(mtd);
2842 * single_erase - [GENERIC] NAND standard block erase command function
2843 * @mtd: MTD device structure
2844 * @page: the page address of the block which will be erased
2846 * Standard erase command for NAND chips. Returns NAND status.
2848 static int single_erase(struct mtd_info *mtd, int page)
2850 struct nand_chip *chip = mtd->priv;
2851 /* Send commands to erase a block */
2852 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2853 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2855 return chip->waitfunc(mtd, chip);
2859 * nand_erase - [MTD Interface] erase block(s)
2860 * @mtd: MTD device structure
2861 * @instr: erase instruction
2863 * Erase one ore more blocks.
2865 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2867 return nand_erase_nand(mtd, instr, 0);
2871 * nand_erase_nand - [INTERN] erase block(s)
2872 * @mtd: MTD device structure
2873 * @instr: erase instruction
2874 * @allowbbt: allow erasing the bbt area
2876 * Erase one ore more blocks.
2878 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2881 int page, status, pages_per_block, ret, chipnr;
2882 struct nand_chip *chip = mtd->priv;
2885 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2886 __func__, (unsigned long long)instr->addr,
2887 (unsigned long long)instr->len);
2889 if (check_offs_len(mtd, instr->addr, instr->len))
2892 /* Grab the lock and see if the device is available */
2893 nand_get_device(mtd, FL_ERASING);
2895 /* Shift to get first page */
2896 page = (int)(instr->addr >> chip->page_shift);
2897 chipnr = (int)(instr->addr >> chip->chip_shift);
2899 /* Calculate pages in each block */
2900 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2902 /* Select the NAND device */
2903 chip->select_chip(mtd, chipnr);
2905 /* Check, if it is write protected */
2906 if (nand_check_wp(mtd)) {
2907 pr_debug("%s: device is write protected!\n",
2909 instr->state = MTD_ERASE_FAILED;
2913 /* Loop through the pages */
2916 instr->state = MTD_ERASING;
2919 /* Check if we have a bad block, we do not erase bad blocks! */
2920 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2921 chip->page_shift, 0, allowbbt)) {
2922 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2924 instr->state = MTD_ERASE_FAILED;
2929 * Invalidate the page cache, if we erase the block which
2930 * contains the current cached page.
2932 if (page <= chip->pagebuf && chip->pagebuf <
2933 (page + pages_per_block))
2936 status = chip->erase(mtd, page & chip->pagemask);
2939 * See if operation failed and additional status checks are
2942 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2943 status = chip->errstat(mtd, chip, FL_ERASING,
2946 /* See if block erase succeeded */
2947 if (status & NAND_STATUS_FAIL) {
2948 pr_debug("%s: failed erase, page 0x%08x\n",
2950 instr->state = MTD_ERASE_FAILED;
2952 ((loff_t)page << chip->page_shift);
2956 /* Increment page address and decrement length */
2957 len -= (1ULL << chip->phys_erase_shift);
2958 page += pages_per_block;
2960 /* Check, if we cross a chip boundary */
2961 if (len && !(page & chip->pagemask)) {
2963 chip->select_chip(mtd, -1);
2964 chip->select_chip(mtd, chipnr);
2967 instr->state = MTD_ERASE_DONE;
2971 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2973 /* Deselect and wake up anyone waiting on the device */
2974 chip->select_chip(mtd, -1);
2975 nand_release_device(mtd);
2977 /* Do call back function */
2979 mtd_erase_callback(instr);
2981 /* Return more or less happy */
2986 * nand_sync - [MTD Interface] sync
2987 * @mtd: MTD device structure
2989 * Sync is actually a wait for chip ready function.
2991 static void nand_sync(struct mtd_info *mtd)
2993 pr_debug("%s: called\n", __func__);
2995 /* Grab the lock and see if the device is available */
2996 nand_get_device(mtd, FL_SYNCING);
2997 /* Release it and go back */
2998 nand_release_device(mtd);
3002 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3003 * @mtd: MTD device structure
3004 * @offs: offset relative to mtd start
3006 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3008 return nand_block_checkbad(mtd, offs, 1, 0);
3012 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3013 * @mtd: MTD device structure
3014 * @ofs: offset relative to mtd start
3016 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3020 ret = nand_block_isbad(mtd, ofs);
3022 /* If it was bad already, return success and do nothing */
3028 return nand_block_markbad_lowlevel(mtd, ofs);
3032 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3033 * @mtd: MTD device structure
3034 * @chip: nand chip info structure
3035 * @addr: feature address.
3036 * @subfeature_param: the subfeature parameters, a four bytes array.
3038 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3039 int addr, uint8_t *subfeature_param)
3044 if (!chip->onfi_version ||
3045 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3046 & ONFI_OPT_CMD_SET_GET_FEATURES))
3049 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3050 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3051 chip->write_byte(mtd, subfeature_param[i]);
3053 status = chip->waitfunc(mtd, chip);
3054 if (status & NAND_STATUS_FAIL)
3060 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3061 * @mtd: MTD device structure
3062 * @chip: nand chip info structure
3063 * @addr: feature address.
3064 * @subfeature_param: the subfeature parameters, a four bytes array.
3066 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3067 int addr, uint8_t *subfeature_param)
3071 if (!chip->onfi_version ||
3072 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3073 & ONFI_OPT_CMD_SET_GET_FEATURES))
3076 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3077 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3078 *subfeature_param++ = chip->read_byte(mtd);
3083 * nand_suspend - [MTD Interface] Suspend the NAND flash
3084 * @mtd: MTD device structure
3086 static int nand_suspend(struct mtd_info *mtd)
3088 return nand_get_device(mtd, FL_PM_SUSPENDED);
3092 * nand_resume - [MTD Interface] Resume the NAND flash
3093 * @mtd: MTD device structure
3095 static void nand_resume(struct mtd_info *mtd)
3097 struct nand_chip *chip = mtd->priv;
3099 if (chip->state == FL_PM_SUSPENDED)
3100 nand_release_device(mtd);
3102 pr_err("%s called for a chip which is not in suspended state\n",
3107 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3108 * prevent further operations
3109 * @mtd: MTD device structure
3111 static void nand_shutdown(struct mtd_info *mtd)
3113 nand_get_device(mtd, FL_SHUTDOWN);
3116 /* Set default functions */
3117 static void nand_set_defaults(struct nand_chip *chip, int busw)
3119 /* check for proper chip_delay setup, set 20us if not */
3120 if (!chip->chip_delay)
3121 chip->chip_delay = 20;
3123 /* check, if a user supplied command function given */
3124 if (chip->cmdfunc == NULL)
3125 chip->cmdfunc = nand_command;
3127 /* check, if a user supplied wait function given */
3128 if (chip->waitfunc == NULL)
3129 chip->waitfunc = nand_wait;
3131 if (!chip->select_chip)
3132 chip->select_chip = nand_select_chip;
3134 /* set for ONFI nand */
3135 if (!chip->onfi_set_features)
3136 chip->onfi_set_features = nand_onfi_set_features;
3137 if (!chip->onfi_get_features)
3138 chip->onfi_get_features = nand_onfi_get_features;
3140 /* If called twice, pointers that depend on busw may need to be reset */
3141 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3142 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3143 if (!chip->read_word)
3144 chip->read_word = nand_read_word;
3145 if (!chip->block_bad)
3146 chip->block_bad = nand_block_bad;
3147 if (!chip->block_markbad)
3148 chip->block_markbad = nand_default_block_markbad;
3149 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3150 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3151 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3152 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3153 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3154 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3155 if (!chip->scan_bbt)
3156 chip->scan_bbt = nand_default_bbt;
3158 if (!chip->controller) {
3159 chip->controller = &chip->hwcontrol;
3160 spin_lock_init(&chip->controller->lock);
3161 init_waitqueue_head(&chip->controller->wq);
3166 /* Sanitize ONFI strings so we can safely print them */
3167 static void sanitize_string(uint8_t *s, size_t len)
3171 /* Null terminate */
3174 /* Remove non printable chars */
3175 for (i = 0; i < len - 1; i++) {
3176 if (s[i] < ' ' || s[i] > 127)
3180 /* Remove trailing spaces */
3184 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3189 for (i = 0; i < 8; i++)
3190 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3196 /* Parse the Extended Parameter Page. */
3197 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3198 struct nand_chip *chip, struct nand_onfi_params *p)
3200 struct onfi_ext_param_page *ep;
3201 struct onfi_ext_section *s;
3202 struct onfi_ext_ecc_info *ecc;
3208 len = le16_to_cpu(p->ext_param_page_length) * 16;
3209 ep = kmalloc(len, GFP_KERNEL);
3213 /* Send our own NAND_CMD_PARAM. */
3214 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3216 /* Use the Change Read Column command to skip the ONFI param pages. */
3217 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3218 sizeof(*p) * p->num_of_param_pages , -1);
3220 /* Read out the Extended Parameter Page. */
3221 chip->read_buf(mtd, (uint8_t *)ep, len);
3222 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3223 != le16_to_cpu(ep->crc))) {
3224 pr_debug("fail in the CRC.\n");
3229 * Check the signature.
3230 * Do not strictly follow the ONFI spec, maybe changed in future.
3232 if (strncmp(ep->sig, "EPPS", 4)) {
3233 pr_debug("The signature is invalid.\n");
3237 /* find the ECC section. */
3238 cursor = (uint8_t *)(ep + 1);
3239 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3240 s = ep->sections + i;
3241 if (s->type == ONFI_SECTION_TYPE_2)
3243 cursor += s->length * 16;
3245 if (i == ONFI_EXT_SECTION_MAX) {
3246 pr_debug("We can not find the ECC section.\n");
3250 /* get the info we want. */
3251 ecc = (struct onfi_ext_ecc_info *)cursor;
3253 if (!ecc->codeword_size) {
3254 pr_debug("Invalid codeword size\n");
3258 chip->ecc_strength_ds = ecc->ecc_bits;
3259 chip->ecc_step_ds = 1 << ecc->codeword_size;
3267 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3269 struct nand_chip *chip = mtd->priv;
3270 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3272 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3277 * Configure chip properties from Micron vendor-specific ONFI table
3279 static void nand_onfi_detect_micron(struct nand_chip *chip,
3280 struct nand_onfi_params *p)
3282 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3284 if (le16_to_cpu(p->vendor_revision) < 1)
3287 chip->read_retries = micron->read_retry_options;
3288 chip->setup_read_retry = nand_setup_read_retry_micron;
3292 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3294 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3297 struct nand_onfi_params *p = &chip->onfi_params;
3301 /* Try ONFI for unknown chip or LP */
3302 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3303 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3304 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3307 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3308 for (i = 0; i < 3; i++) {
3309 for (j = 0; j < sizeof(*p); j++)
3310 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3311 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3312 le16_to_cpu(p->crc)) {
3318 pr_err("Could not find valid ONFI parameter page; aborting\n");
3323 val = le16_to_cpu(p->revision);
3325 chip->onfi_version = 23;
3326 else if (val & (1 << 4))
3327 chip->onfi_version = 22;
3328 else if (val & (1 << 3))
3329 chip->onfi_version = 21;
3330 else if (val & (1 << 2))
3331 chip->onfi_version = 20;
3332 else if (val & (1 << 1))
3333 chip->onfi_version = 10;
3335 if (!chip->onfi_version) {
3336 pr_info("unsupported ONFI version: %d\n", val);
3340 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3341 sanitize_string(p->model, sizeof(p->model));
3343 mtd->name = p->model;
3345 mtd->writesize = le32_to_cpu(p->byte_per_page);
3348 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3349 * (don't ask me who thought of this...). MTD assumes that these
3350 * dimensions will be power-of-2, so just truncate the remaining area.
3352 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3353 mtd->erasesize *= mtd->writesize;
3355 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3357 /* See erasesize comment */
3358 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3359 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3360 chip->bits_per_cell = p->bits_per_cell;
3362 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3363 *busw = NAND_BUSWIDTH_16;
3367 if (p->ecc_bits != 0xff) {
3368 chip->ecc_strength_ds = p->ecc_bits;
3369 chip->ecc_step_ds = 512;
3370 } else if (chip->onfi_version >= 21 &&
3371 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3374 * The nand_flash_detect_ext_param_page() uses the
3375 * Change Read Column command which maybe not supported
3376 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3377 * now. We do not replace user supplied command function.
3379 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3380 chip->cmdfunc = nand_command_lp;
3382 /* The Extended Parameter Page is supported since ONFI 2.1. */
3383 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3384 pr_warn("Failed to detect ONFI extended param page\n");
3386 pr_warn("Could not retrieve ONFI ECC requirements\n");
3389 if (p->jedec_id == NAND_MFR_MICRON)
3390 nand_onfi_detect_micron(chip, p);
3396 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3398 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3401 struct nand_jedec_params *p = &chip->jedec_params;
3402 struct jedec_ecc_info *ecc;
3406 /* Try JEDEC for unknown chip or LP */
3407 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3408 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3409 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3410 chip->read_byte(mtd) != 'C')
3413 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3414 for (i = 0; i < 3; i++) {
3415 for (j = 0; j < sizeof(*p); j++)
3416 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3418 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3419 le16_to_cpu(p->crc))
3424 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3429 val = le16_to_cpu(p->revision);
3431 chip->jedec_version = 10;
3432 else if (val & (1 << 1))
3433 chip->jedec_version = 1; /* vendor specific version */
3435 if (!chip->jedec_version) {
3436 pr_info("unsupported JEDEC version: %d\n", val);
3440 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3441 sanitize_string(p->model, sizeof(p->model));
3443 mtd->name = p->model;
3445 mtd->writesize = le32_to_cpu(p->byte_per_page);
3447 /* Please reference to the comment for nand_flash_detect_onfi. */
3448 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3449 mtd->erasesize *= mtd->writesize;
3451 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3453 /* Please reference to the comment for nand_flash_detect_onfi. */
3454 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3455 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3456 chip->bits_per_cell = p->bits_per_cell;
3458 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3459 *busw = NAND_BUSWIDTH_16;
3464 ecc = &p->ecc_info[0];
3466 if (ecc->codeword_size >= 9) {
3467 chip->ecc_strength_ds = ecc->ecc_bits;
3468 chip->ecc_step_ds = 1 << ecc->codeword_size;
3470 pr_warn("Invalid codeword size\n");
3477 * nand_id_has_period - Check if an ID string has a given wraparound period
3478 * @id_data: the ID string
3479 * @arrlen: the length of the @id_data array
3480 * @period: the period of repitition
3482 * Check if an ID string is repeated within a given sequence of bytes at
3483 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3484 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3485 * if the repetition has a period of @period; otherwise, returns zero.
3487 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3490 for (i = 0; i < period; i++)
3491 for (j = i + period; j < arrlen; j += period)
3492 if (id_data[i] != id_data[j])
3498 * nand_id_len - Get the length of an ID string returned by CMD_READID
3499 * @id_data: the ID string
3500 * @arrlen: the length of the @id_data array
3502 * Returns the length of the ID string, according to known wraparound/trailing
3503 * zero patterns. If no pattern exists, returns the length of the array.
3505 static int nand_id_len(u8 *id_data, int arrlen)
3507 int last_nonzero, period;
3509 /* Find last non-zero byte */
3510 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3511 if (id_data[last_nonzero])
3515 if (last_nonzero < 0)
3518 /* Calculate wraparound period */
3519 for (period = 1; period < arrlen; period++)
3520 if (nand_id_has_period(id_data, arrlen, period))
3523 /* There's a repeated pattern */
3524 if (period < arrlen)
3527 /* There are trailing zeros */
3528 if (last_nonzero < arrlen - 1)
3529 return last_nonzero + 1;
3531 /* No pattern detected */
3535 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3536 static int nand_get_bits_per_cell(u8 cellinfo)
3540 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3541 bits >>= NAND_CI_CELLTYPE_SHIFT;
3546 * Many new NAND share similar device ID codes, which represent the size of the
3547 * chip. The rest of the parameters must be decoded according to generic or
3548 * manufacturer-specific "extended ID" decoding patterns.
3550 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3551 u8 id_data[8], int *busw)
3554 /* The 3rd id byte holds MLC / multichip data */
3555 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3556 /* The 4th id byte is the important one */
3559 id_len = nand_id_len(id_data, 8);
3562 * Field definitions are in the following datasheets:
3563 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3564 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3565 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3567 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3568 * ID to decide what to do.
3570 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3571 !nand_is_slc(chip) && id_data[5] != 0x00) {
3573 mtd->writesize = 2048 << (extid & 0x03);
3576 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3596 default: /* Other cases are "reserved" (unknown) */
3597 mtd->oobsize = 1024;
3601 /* Calc blocksize */
3602 mtd->erasesize = (128 * 1024) <<
3603 (((extid >> 1) & 0x04) | (extid & 0x03));
3605 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3606 !nand_is_slc(chip)) {
3610 mtd->writesize = 2048 << (extid & 0x03);
3613 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3637 /* Calc blocksize */
3638 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3640 mtd->erasesize = (128 * 1024) << tmp;
3641 else if (tmp == 0x03)
3642 mtd->erasesize = 768 * 1024;
3644 mtd->erasesize = (64 * 1024) << tmp;
3648 mtd->writesize = 1024 << (extid & 0x03);
3651 mtd->oobsize = (8 << (extid & 0x01)) *
3652 (mtd->writesize >> 9);
3654 /* Calc blocksize. Blocksize is multiples of 64KiB */
3655 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3657 /* Get buswidth information */
3658 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3661 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3662 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3664 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3666 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3668 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3669 nand_is_slc(chip) &&
3670 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3671 !(id_data[4] & 0x80) /* !BENAND */) {
3672 mtd->oobsize = 32 * mtd->writesize >> 9;
3679 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3680 * decodes a matching ID table entry and assigns the MTD size parameters for
3683 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3684 struct nand_flash_dev *type, u8 id_data[8],
3687 int maf_id = id_data[0];
3689 mtd->erasesize = type->erasesize;
3690 mtd->writesize = type->pagesize;
3691 mtd->oobsize = mtd->writesize / 32;
3692 *busw = type->options & NAND_BUSWIDTH_16;
3694 /* All legacy ID NAND are small-page, SLC */
3695 chip->bits_per_cell = 1;
3698 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3699 * some Spansion chips have erasesize that conflicts with size
3700 * listed in nand_ids table.
3701 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3703 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3704 && id_data[6] == 0x00 && id_data[7] == 0x00
3705 && mtd->writesize == 512) {
3706 mtd->erasesize = 128 * 1024;
3707 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3712 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3713 * heuristic patterns using various detected parameters (e.g., manufacturer,
3714 * page size, cell-type information).
3716 static void nand_decode_bbm_options(struct mtd_info *mtd,
3717 struct nand_chip *chip, u8 id_data[8])
3719 int maf_id = id_data[0];
3721 /* Set the bad block position */
3722 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3723 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3725 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3728 * Bad block marker is stored in the last page of each block on Samsung
3729 * and Hynix MLC devices; stored in first two pages of each block on
3730 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3731 * AMD/Spansion, and Macronix. All others scan only the first page.
3733 if (!nand_is_slc(chip) &&
3734 (maf_id == NAND_MFR_SAMSUNG ||
3735 maf_id == NAND_MFR_HYNIX))
3736 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3737 else if ((nand_is_slc(chip) &&
3738 (maf_id == NAND_MFR_SAMSUNG ||
3739 maf_id == NAND_MFR_HYNIX ||
3740 maf_id == NAND_MFR_TOSHIBA ||
3741 maf_id == NAND_MFR_AMD ||
3742 maf_id == NAND_MFR_MACRONIX)) ||
3743 (mtd->writesize == 2048 &&
3744 maf_id == NAND_MFR_MICRON))
3745 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3748 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3750 return type->id_len;
3753 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3754 struct nand_flash_dev *type, u8 *id_data, int *busw)
3756 if (!strncmp(type->id, id_data, type->id_len)) {
3757 mtd->writesize = type->pagesize;
3758 mtd->erasesize = type->erasesize;
3759 mtd->oobsize = type->oobsize;
3761 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3762 chip->chipsize = (uint64_t)type->chipsize << 20;
3763 chip->options |= type->options;
3764 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3765 chip->ecc_step_ds = NAND_ECC_STEP(type);
3766 chip->onfi_timing_mode_default =
3767 type->onfi_timing_mode_default;
3769 *busw = type->options & NAND_BUSWIDTH_16;
3772 mtd->name = type->name;
3780 * Get the flash and manufacturer id and lookup if the type is supported.
3782 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3783 struct nand_chip *chip,
3784 int *maf_id, int *dev_id,
3785 struct nand_flash_dev *type)
3791 /* Select the device */
3792 chip->select_chip(mtd, 0);
3795 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3798 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3800 /* Send the command for reading device ID */
3801 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3803 /* Read manufacturer and device IDs */
3804 *maf_id = chip->read_byte(mtd);
3805 *dev_id = chip->read_byte(mtd);
3808 * Try again to make sure, as some systems the bus-hold or other
3809 * interface concerns can cause random data which looks like a
3810 * possibly credible NAND flash to appear. If the two results do
3811 * not match, ignore the device completely.
3814 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3816 /* Read entire ID string */
3817 for (i = 0; i < 8; i++)
3818 id_data[i] = chip->read_byte(mtd);
3820 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3821 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3822 *maf_id, *dev_id, id_data[0], id_data[1]);
3823 return ERR_PTR(-ENODEV);
3827 type = nand_flash_ids;
3829 for (; type->name != NULL; type++) {
3830 if (is_full_id_nand(type)) {
3831 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3833 } else if (*dev_id == type->dev_id) {
3838 chip->onfi_version = 0;
3839 if (!type->name || !type->pagesize) {
3840 /* Check if the chip is ONFI compliant */
3841 if (nand_flash_detect_onfi(mtd, chip, &busw))
3844 /* Check if the chip is JEDEC compliant */
3845 if (nand_flash_detect_jedec(mtd, chip, &busw))
3850 return ERR_PTR(-ENODEV);
3853 mtd->name = type->name;
3855 chip->chipsize = (uint64_t)type->chipsize << 20;
3857 if (!type->pagesize) {
3858 /* Decode parameters from extended ID */
3859 nand_decode_ext_id(mtd, chip, id_data, &busw);
3861 nand_decode_id(mtd, chip, type, id_data, &busw);
3863 /* Get chip options */
3864 chip->options |= type->options;
3867 * Check if chip is not a Samsung device. Do not clear the
3868 * options for chips which do not have an extended id.
3870 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3871 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3874 /* Try to identify manufacturer */
3875 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3876 if (nand_manuf_ids[maf_idx].id == *maf_id)
3880 if (chip->options & NAND_BUSWIDTH_AUTO) {
3881 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3882 chip->options |= busw;
3883 nand_set_defaults(chip, busw);
3884 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3886 * Check, if buswidth is correct. Hardware drivers should set
3889 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3891 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3892 pr_warn("bus width %d instead %d bit\n",
3893 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3895 return ERR_PTR(-EINVAL);
3898 nand_decode_bbm_options(mtd, chip, id_data);
3900 /* Calculate the address shift from the page size */
3901 chip->page_shift = ffs(mtd->writesize) - 1;
3902 /* Convert chipsize to number of pages per chip -1 */
3903 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3905 chip->bbt_erase_shift = chip->phys_erase_shift =
3906 ffs(mtd->erasesize) - 1;
3907 if (chip->chipsize & 0xffffffff)
3908 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3910 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3911 chip->chip_shift += 32 - 1;
3914 chip->badblockbits = 8;
3915 chip->erase = single_erase;
3917 /* Do not replace user supplied command function! */
3918 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3919 chip->cmdfunc = nand_command_lp;
3921 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3924 if (chip->onfi_version)
3925 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3926 chip->onfi_params.model);
3927 else if (chip->jedec_version)
3928 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3929 chip->jedec_params.model);
3931 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3934 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3935 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3936 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
3940 static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip,
3941 struct device_node *dn)
3943 int ecc_mode, ecc_strength, ecc_step;
3945 if (of_get_nand_bus_width(dn) == 16)
3946 chip->options |= NAND_BUSWIDTH_16;
3948 if (of_get_nand_on_flash_bbt(dn))
3949 chip->bbt_options |= NAND_BBT_USE_FLASH;
3951 ecc_mode = of_get_nand_ecc_mode(dn);
3952 ecc_strength = of_get_nand_ecc_strength(dn);
3953 ecc_step = of_get_nand_ecc_step_size(dn);
3955 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
3956 (!(ecc_step >= 0) && ecc_strength >= 0)) {
3957 pr_err("must set both strength and step size in DT\n");
3962 chip->ecc.mode = ecc_mode;
3964 if (ecc_strength >= 0)
3965 chip->ecc.strength = ecc_strength;
3968 chip->ecc.size = ecc_step;
3974 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3975 * @mtd: MTD device structure
3976 * @maxchips: number of chips to scan for
3977 * @table: alternative NAND ID table
3979 * This is the first phase of the normal nand_scan() function. It reads the
3980 * flash ID and sets up MTD fields accordingly.
3982 * The mtd->owner field must be set to the module of the caller.
3984 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3985 struct nand_flash_dev *table)
3987 int i, nand_maf_id, nand_dev_id;
3988 struct nand_chip *chip = mtd->priv;
3989 struct nand_flash_dev *type;
3992 if (chip->flash_node) {
3993 ret = nand_dt_init(mtd, chip, chip->flash_node);
3998 /* Set the default functions */
3999 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4001 /* Read the flash type */
4002 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4003 &nand_dev_id, table);
4006 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4007 pr_warn("No NAND device found\n");
4008 chip->select_chip(mtd, -1);
4009 return PTR_ERR(type);
4012 chip->select_chip(mtd, -1);
4014 /* Check for a chip array */
4015 for (i = 1; i < maxchips; i++) {
4016 chip->select_chip(mtd, i);
4017 /* See comment in nand_get_flash_type for reset */
4018 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4019 /* Send the command for reading device ID */
4020 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4021 /* Read manufacturer and device IDs */
4022 if (nand_maf_id != chip->read_byte(mtd) ||
4023 nand_dev_id != chip->read_byte(mtd)) {
4024 chip->select_chip(mtd, -1);
4027 chip->select_chip(mtd, -1);
4030 pr_info("%d chips detected\n", i);
4032 /* Store the number of chips and calc total size for mtd */
4034 mtd->size = i * chip->chipsize;
4038 EXPORT_SYMBOL(nand_scan_ident);
4041 * Check if the chip configuration meet the datasheet requirements.
4043 * If our configuration corrects A bits per B bytes and the minimum
4044 * required correction level is X bits per Y bytes, then we must ensure
4045 * both of the following are true:
4047 * (1) A / B >= X / Y
4050 * Requirement (1) ensures we can correct for the required bitflip density.
4051 * Requirement (2) ensures we can correct even when all bitflips are clumped
4052 * in the same sector.
4054 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4056 struct nand_chip *chip = mtd->priv;
4057 struct nand_ecc_ctrl *ecc = &chip->ecc;
4060 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4061 /* Not enough information */
4065 * We get the number of corrected bits per page to compare
4066 * the correction density.
4068 corr = (mtd->writesize * ecc->strength) / ecc->size;
4069 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4071 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4075 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4076 * @mtd: MTD device structure
4078 * This is the second phase of the normal nand_scan() function. It fills out
4079 * all the uninitialized function pointers with the defaults and scans for a
4080 * bad block table if appropriate.
4082 int nand_scan_tail(struct mtd_info *mtd)
4085 struct nand_chip *chip = mtd->priv;
4086 struct nand_ecc_ctrl *ecc = &chip->ecc;
4087 struct nand_buffers *nbuf;
4089 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4090 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4091 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4093 if (!(chip->options & NAND_OWN_BUFFERS)) {
4094 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4095 + mtd->oobsize * 3, GFP_KERNEL);
4098 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4099 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4100 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4102 chip->buffers = nbuf;
4108 /* Set the internal oob buffer location, just after the page data */
4109 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4112 * If no default placement scheme is given, select an appropriate one.
4114 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4115 switch (mtd->oobsize) {
4117 ecc->layout = &nand_oob_8;
4120 ecc->layout = &nand_oob_16;
4123 ecc->layout = &nand_oob_64;
4126 ecc->layout = &nand_oob_128;
4129 pr_warn("No oob scheme defined for oobsize %d\n",
4135 if (!chip->write_page)
4136 chip->write_page = nand_write_page;
4139 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4140 * selected and we have 256 byte pagesize fallback to software ECC
4143 switch (ecc->mode) {
4144 case NAND_ECC_HW_OOB_FIRST:
4145 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4146 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4147 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4150 if (!ecc->read_page)
4151 ecc->read_page = nand_read_page_hwecc_oob_first;
4154 /* Use standard hwecc read page function? */
4155 if (!ecc->read_page)
4156 ecc->read_page = nand_read_page_hwecc;
4157 if (!ecc->write_page)
4158 ecc->write_page = nand_write_page_hwecc;
4159 if (!ecc->read_page_raw)
4160 ecc->read_page_raw = nand_read_page_raw;
4161 if (!ecc->write_page_raw)
4162 ecc->write_page_raw = nand_write_page_raw;
4164 ecc->read_oob = nand_read_oob_std;
4165 if (!ecc->write_oob)
4166 ecc->write_oob = nand_write_oob_std;
4167 if (!ecc->read_subpage)
4168 ecc->read_subpage = nand_read_subpage;
4169 if (!ecc->write_subpage)
4170 ecc->write_subpage = nand_write_subpage_hwecc;
4172 case NAND_ECC_HW_SYNDROME:
4173 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4175 ecc->read_page == nand_read_page_hwecc ||
4177 ecc->write_page == nand_write_page_hwecc)) {
4178 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4181 /* Use standard syndrome read/write page function? */
4182 if (!ecc->read_page)
4183 ecc->read_page = nand_read_page_syndrome;
4184 if (!ecc->write_page)
4185 ecc->write_page = nand_write_page_syndrome;
4186 if (!ecc->read_page_raw)
4187 ecc->read_page_raw = nand_read_page_raw_syndrome;
4188 if (!ecc->write_page_raw)
4189 ecc->write_page_raw = nand_write_page_raw_syndrome;
4191 ecc->read_oob = nand_read_oob_syndrome;
4192 if (!ecc->write_oob)
4193 ecc->write_oob = nand_write_oob_syndrome;
4195 if (mtd->writesize >= ecc->size) {
4196 if (!ecc->strength) {
4197 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4202 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4203 ecc->size, mtd->writesize);
4204 ecc->mode = NAND_ECC_SOFT;
4207 ecc->calculate = nand_calculate_ecc;
4208 ecc->correct = nand_correct_data;
4209 ecc->read_page = nand_read_page_swecc;
4210 ecc->read_subpage = nand_read_subpage;
4211 ecc->write_page = nand_write_page_swecc;
4212 ecc->read_page_raw = nand_read_page_raw;
4213 ecc->write_page_raw = nand_write_page_raw;
4214 ecc->read_oob = nand_read_oob_std;
4215 ecc->write_oob = nand_write_oob_std;
4222 case NAND_ECC_SOFT_BCH:
4223 if (!mtd_nand_has_bch()) {
4224 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4227 ecc->calculate = nand_bch_calculate_ecc;
4228 ecc->correct = nand_bch_correct_data;
4229 ecc->read_page = nand_read_page_swecc;
4230 ecc->read_subpage = nand_read_subpage;
4231 ecc->write_page = nand_write_page_swecc;
4232 ecc->read_page_raw = nand_read_page_raw;
4233 ecc->write_page_raw = nand_write_page_raw;
4234 ecc->read_oob = nand_read_oob_std;
4235 ecc->write_oob = nand_write_oob_std;
4237 * Board driver should supply ecc.size and ecc.strength values
4238 * to select how many bits are correctable. Otherwise, default
4239 * to 4 bits for large page devices.
4241 if (!ecc->size && (mtd->oobsize >= 64)) {
4246 /* See nand_bch_init() for details. */
4247 ecc->bytes = DIV_ROUND_UP(
4248 ecc->strength * fls(8 * ecc->size), 8);
4249 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4252 pr_warn("BCH ECC initialization failed!\n");
4258 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4259 ecc->read_page = nand_read_page_raw;
4260 ecc->write_page = nand_write_page_raw;
4261 ecc->read_oob = nand_read_oob_std;
4262 ecc->read_page_raw = nand_read_page_raw;
4263 ecc->write_page_raw = nand_write_page_raw;
4264 ecc->write_oob = nand_write_oob_std;
4265 ecc->size = mtd->writesize;
4271 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4275 /* For many systems, the standard OOB write also works for raw */
4276 if (!ecc->read_oob_raw)
4277 ecc->read_oob_raw = ecc->read_oob;
4278 if (!ecc->write_oob_raw)
4279 ecc->write_oob_raw = ecc->write_oob;
4282 * The number of bytes available for a client to place data into
4283 * the out of band area.
4285 ecc->layout->oobavail = 0;
4286 for (i = 0; ecc->layout->oobfree[i].length
4287 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4288 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4289 mtd->oobavail = ecc->layout->oobavail;
4291 /* ECC sanity check: warn if it's too weak */
4292 if (!nand_ecc_strength_good(mtd))
4293 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4297 * Set the number of read / write steps for one page depending on ECC
4300 ecc->steps = mtd->writesize / ecc->size;
4301 if (ecc->steps * ecc->size != mtd->writesize) {
4302 pr_warn("Invalid ECC parameters\n");
4305 ecc->total = ecc->steps * ecc->bytes;
4307 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4308 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4309 switch (ecc->steps) {
4311 mtd->subpage_sft = 1;
4316 mtd->subpage_sft = 2;
4320 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4322 /* Initialize state */
4323 chip->state = FL_READY;
4325 /* Invalidate the pagebuffer reference */
4328 /* Large page NAND with SOFT_ECC should support subpage reads */
4329 switch (ecc->mode) {
4331 case NAND_ECC_SOFT_BCH:
4332 if (chip->page_shift > 9)
4333 chip->options |= NAND_SUBPAGE_READ;
4340 /* Fill in remaining MTD driver data */
4341 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4342 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4344 mtd->_erase = nand_erase;
4346 mtd->_unpoint = NULL;
4347 mtd->_read = nand_read;
4348 mtd->_write = nand_write;
4349 mtd->_panic_write = panic_nand_write;
4350 mtd->_read_oob = nand_read_oob;
4351 mtd->_write_oob = nand_write_oob;
4352 mtd->_sync = nand_sync;
4354 mtd->_unlock = NULL;
4355 mtd->_suspend = nand_suspend;
4356 mtd->_resume = nand_resume;
4357 mtd->_reboot = nand_shutdown;
4358 mtd->_block_isreserved = nand_block_isreserved;
4359 mtd->_block_isbad = nand_block_isbad;
4360 mtd->_block_markbad = nand_block_markbad;
4361 mtd->writebufsize = mtd->writesize;
4363 /* propagate ecc info to mtd_info */
4364 mtd->ecclayout = ecc->layout;
4365 mtd->ecc_strength = ecc->strength;
4366 mtd->ecc_step_size = ecc->size;
4368 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4369 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4372 if (!mtd->bitflip_threshold)
4373 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4375 /* Check, if we should skip the bad block table scan */
4376 if (chip->options & NAND_SKIP_BBTSCAN)
4379 /* Build bad block table */
4380 return chip->scan_bbt(mtd);
4382 EXPORT_SYMBOL(nand_scan_tail);
4385 * is_module_text_address() isn't exported, and it's mostly a pointless
4386 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4387 * to call us from in-kernel code if the core NAND support is modular.
4390 #define caller_is_module() (1)
4392 #define caller_is_module() \
4393 is_module_text_address((unsigned long)__builtin_return_address(0))
4397 * nand_scan - [NAND Interface] Scan for the NAND device
4398 * @mtd: MTD device structure
4399 * @maxchips: number of chips to scan for
4401 * This fills out all the uninitialized function pointers with the defaults.
4402 * The flash ID is read and the mtd/chip structures are filled with the
4403 * appropriate values. The mtd->owner field must be set to the module of the
4406 int nand_scan(struct mtd_info *mtd, int maxchips)
4410 /* Many callers got this wrong, so check for it for a while... */
4411 if (!mtd->owner && caller_is_module()) {
4412 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4416 ret = nand_scan_ident(mtd, maxchips, NULL);
4418 ret = nand_scan_tail(mtd);
4421 EXPORT_SYMBOL(nand_scan);
4424 * nand_release - [NAND Interface] Free resources held by the NAND device
4425 * @mtd: MTD device structure
4427 void nand_release(struct mtd_info *mtd)
4429 struct nand_chip *chip = mtd->priv;
4431 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4432 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4434 mtd_device_unregister(mtd);
4436 /* Free bad block table memory */
4438 if (!(chip->options & NAND_OWN_BUFFERS))
4439 kfree(chip->buffers);
4441 /* Free bad block descriptor memory */
4442 if (chip->badblock_pattern && chip->badblock_pattern->options
4443 & NAND_BBT_DYNAMICSTRUCT)
4444 kfree(chip->badblock_pattern);
4446 EXPORT_SYMBOL_GPL(nand_release);
4448 static int __init nand_base_init(void)
4450 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4454 static void __exit nand_base_exit(void)
4456 led_trigger_unregister_simple(nand_led_trigger);
4459 module_init(nand_base_init);
4460 module_exit(nand_base_exit);
4462 MODULE_LICENSE("GPL");
4463 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4464 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4465 MODULE_DESCRIPTION("Generic NAND flash driver code");