drivers/mtd/nand/rk2818_nand.c

   1
   2 /*
   3  * drivers/mtd/nand/rk2818_nand.c
   4  *
   5  * Copyright (C) 2010 RockChip, Inc.
   6  * Author: hxy@rock-chips.com
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/cpufreq.h>
  30 #include <linux/err.h>
  31 #include <linux/io.h>
  32
  33 #include <mach/rk2818_nand.h>
  34 #include <mach/rk2818_iomap.h>
  35 #include <mach/iomux.h>
  36
  37 #define PROGRAM_BUSY_COUNT   10000
  38 #define ERASE_BUSY_COUNT            20000
  39 #define READ_BUSY_COUNT             5000
  40 #define RESET_BUSY_COUNT                        20000
  41
  42 /* Define delays in microsec for NAND device operations */
  43 #define TROP_US_DELAY   2000
  44
  45 static struct mutex  rknand_mutex;
  46 //static  spinlock_t    rknand_lock;
  47
  48
  49 struct rk2818_nand_mtd {
  50         struct mtd_info         mtd;
  51         struct nand_chip                nand;
  52         struct mtd_partition    *parts;
  53         struct device           *dev;
  54        const struct rk2818_nand_flash *flash_info;
  55
  56         struct clk                      *clk;
  57         unsigned long                   clk_rate;
  58         void __iomem                    *regs;
  59         int                                     cs;                     // support muliple nand chip,record current chip select
  60         u_char                          accesstime;
  61 #ifdef CONFIG_CPU_FREQ
  62         struct notifier_block   freq_transition;
  63 #endif
  64
  65 };
  66
  67 /* OOB placement block for use with software ecc generation */
  68 static struct nand_ecclayout nand_sw_eccoob_8 = {
  69         .eccbytes = 48,
  70         .eccpos = { 8, 9, 10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,
  71                           32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55},
  72         .oobfree = {{0,8},{56, 72}}
  73 };
  74
  75 /* OOB placement block for use with hardware ecc generation */
  76 static struct nand_ecclayout nand_hw_eccoob_16 = {
  77         .eccbytes = 28,
  78         .eccpos = { 4,  5, 6,  7,  8, 9, 10,11,12,13,14,15,16,17,
  79                           18,19,20,21,22,23,24,25,26,27,28,29,30,31},
  80         .oobfree = {{0, 4}}
  81 };
  82
  83 #ifdef CONFIG_MTD_PARTITIONS
  84 static const char *part_probes[] = { "cmdlinepart", NULL };
  85 #endif
  86
  87
  88 static void rk2818_nand_wait_busy(struct mtd_info *mtd, uint32_t timeout)
  89 {
  90
  91         struct nand_chip *nand_chip = mtd->priv;
  92         struct rk2818_nand_mtd *master = nand_chip->priv;
  93         pNANDC pRK28NC=  (pNANDC)(master->regs);
  94
  95         while (timeout > 0)
  96         {
  97                 timeout--;
  98                 udelay(10);
  99                 if ( pRK28NC->FMCTL& FMC_FRDY)
 100                         break;
 101
 102         }
 103
 104     return;
 105 }
 106
 107 static void rk2818_nand_wait_bchdone(struct mtd_info *mtd, uint32_t timeout)
 108 {
 109
 110         struct nand_chip *nand_chip = mtd->priv;
 111         struct rk2818_nand_mtd *master = nand_chip->priv;
 112         pNANDC pRK28NC=  (pNANDC)(master->regs);
 113
 114         while (timeout > 0)
 115         {
 116                 timeout--;
 117                 udelay(1);
 118                 if(pRK28NC->BCHST &(1<<1))
 119                         break;
 120         }
 121
 122     return;
 123 }
 124
 125 // only for dma mode
 126 static void wait_op_done(struct mtd_info *mtd, int max_retries, uint16_t param)
 127 {
 128        struct nand_chip *nand_chip = mtd->priv;
 129         struct rk2818_nand_mtd *master = nand_chip->priv;
 130         pNANDC pRK28NC=  (pNANDC)(master->regs);
 131
 132         while (max_retries-- > 0) {
 133                 udelay(1);
 134                 if (pRK28NC->FLCTL & FL_RDY)
 135                         break;
 136         }
 137 }
 138
 139 static int rk2818_nand_dev_ready(struct mtd_info *mtd)
 140 {
 141         struct nand_chip *nand_chip = mtd->priv;
 142         struct rk2818_nand_mtd *master = nand_chip->priv;
 143         pNANDC pRK28NC=  (pNANDC)(master->regs);
 144
 145         if(pRK28NC->FMCTL& FMC_FRDY)
 146            return 1;
 147         else
 148            return 0;
 149 }
 150
 151 /*
 152 *  ÉèÖÃÆ¬Ñ¡
 153 */
 154 static void rk2818_nand_select_chip(struct mtd_info *mtd, int chip)
 155 {
 156         struct nand_chip *nand_chip = mtd->priv;
 157         struct rk2818_nand_mtd *master = nand_chip->priv;
 158         pNANDC pRK28NC=  (pNANDC)(master->regs);
 159
 160
 161         if( chip<0 )
 162              pRK28NC->FMCTL &=0xffffff00;   // release chip select
 163         else
 164           {
 165                master->cs = chip;
 166                 pRK28NC->FMCTL &=0xffffff00;
 167                 pRK28NC ->FMCTL |= 0x1<<chip;  // select chip
 168           }
 169
 170 }
 171
 172 /*
 173  *   ¶ÁÒ»¸ö×Ö½ÚÊý¾Ý
 174 */
 175 static u_char rk2818_nand_read_byte(struct mtd_info *mtd)
 176 {
 177         struct nand_chip *nand_chip = mtd->priv;
 178         struct rk2818_nand_mtd *master = nand_chip->priv;
 179         pNANDC pRK28NC=  (pNANDC)(master->regs);
 180
 181         u_char ret = 0;
 182
 183         ret = (u_char)(pRK28NC ->chip[master->cs].data);
 184
 185         return ret;
 186 }
 187
 188 /*
 189  *   ¶ÁÒ»¸öword ³¤¶ÈÊý¾Ý
 190 */
 191 static u16 rk2818_nand_read_word(struct mtd_info *mtd)
 192 {
 193         struct nand_chip *nand_chip = mtd->priv;
 194         struct rk2818_nand_mtd *master = nand_chip->priv;
 195         pNANDC pRK28NC=  (pNANDC)(master->regs);
 196
 197
 198         u_char tmp1 = 0,tmp2=0;
 199         u16 ret=0;
 200
 201         tmp1 = (u_char)(pRK28NC ->chip[master->cs].data);
 202         tmp2 = (u_char)(pRK28NC ->chip[master->cs].data);
 203
 204         ret =   (tmp2 <<8)|tmp1;
 205
 206         return ret;
 207 }
 208
 209 static void rk2818_nand_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 210 {
 211        struct nand_chip *nand_chip = mtd->priv;
 212         struct rk2818_nand_mtd *master = nand_chip->priv;
 213         pNANDC pRK28NC=  (pNANDC)(master->regs);
 214         uint32_t  i, chipnr;
 215
 216        mutex_lock(&rknand_mutex);
 217
 218        chipnr = master->cs ;
 219
 220         rk2818_nand_select_chip(mtd,chipnr);
 221
 222
 223
 224         if ( len < mtd->writesize )   // read oob
 225         {
 226                 pRK28NC ->BCHCTL = BCH_RST;
 227                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 228                 wait_op_done(mtd,TROP_US_DELAY,0);
 229                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 230                 memcpy(buf,(u_char *)(pRK28NC->spare),4);  //  only use nandc sram0
 231         }
 232         else
 233        {
 234            pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 235             for(i=0;i<mtd->writesize/0x400;i++)
 236                 {
 237                        pRK28NC ->BCHCTL = BCH_RST;
 238                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 239                         wait_op_done(mtd,TROP_US_DELAY,0);
 240                         rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 241                 memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 242                 }
 243         }
 244
 245
 246
 247         rk2818_nand_select_chip(mtd,-1);
 248
 249         mutex_unlock(&rknand_mutex);
 250
 251
 252         return;
 253
 254 }
 255
 256 static void rk2818_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 257 {
 258        struct nand_chip *nand_chip = mtd->priv;
 259         struct rk2818_nand_mtd *master = nand_chip->priv;
 260         pNANDC pRK28NC=  (pNANDC)(master->regs);
 261
 262         uint32_t  i = 0, chipnr;
 263
 264
 265          mutex_lock(&rknand_mutex);
 266
 267          chipnr = master->cs ;
 268
 269         rk2818_nand_select_chip(mtd,chipnr);
 270
 271          pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 272
 273
 274           for(i=0;i<mtd->writesize/0x400;i++)
 275             {
 276                memcpy((u_char *)(pRK28NC->buf),buf+i*0x400,0x400);  //  only use nandc sram0
 277                 pRK28NC ->BCHCTL =BCH_WR|BCH_RST;
 278                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|0x1<<5|FL_RDN|FL_BYPASS|FL_START;
 279                 wait_op_done(mtd,TROP_US_DELAY,0);
 280             }
 281
 282
 283
 284        rk2818_nand_select_chip(mtd,-1);
 285
 286           mutex_unlock(&rknand_mutex);
 287
 288
 289 }
 290
 291
 292 static void rk2818_nand_cmdfunc(struct mtd_info *mtd, unsigned command,int column, int page_addr)
 293 {
 294        struct nand_chip *nand_chip = mtd->priv;
 295         struct rk2818_nand_mtd *master = nand_chip->priv;
 296         pNANDC pRK28NC=  (pNANDC)(master->regs);
 297
 298        uint32_t timeout = 1000;
 299         char status,ret;
 300
 301
 302         switch (command) {
 303
 304        case NAND_CMD_READID:
 305                 pRK28NC ->chip[master->cs].cmd = command;
 306                 pRK28NC ->chip[master->cs].addr = 0x0;
 307                 while (timeout>0)
 308                 {
 309                  timeout --;
 310                    udelay(1);
 311                   if(pRK28NC->FLCTL&FL_INTCLR)
 312                          break;
 313
 314                 }
 315
 316                 rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 317                 break;
 318
 319        case NAND_CMD_READ0:
 320               pRK28NC ->chip[master->cs].cmd = command;
 321                if ( column>= 0 )
 322                  {
 323                    pRK28NC ->chip[master->cs].addr = column & 0xff;
 324                    if( mtd->writesize > 512)
 325                          pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff;
 326                  }
 327                 if ( page_addr>=0 )
 328                    {
 329                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 330                         pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF;
 331                         pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff;
 332                    }
 333                 if( mtd->writesize > 512)
 334                     pRK28NC ->chip[0].cmd = NAND_CMD_READSTART;
 335
 336                 rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 337
 338                 break;
 339
 340         case NAND_CMD_READ1:
 341               pRK28NC ->chip[master->cs].cmd = command;
 342                 break;
 343
 344        case NAND_CMD_READOOB:
 345                 pRK28NC ->BCHCTL = 0x0;
 346                 if( mtd->writesize > 512 )
 347                         command = NAND_CMD_READ0;  // È«²¿¶Á£¬°üÀ¨¶Áoob
 348
 349                 pRK28NC ->chip[master->cs].cmd = command;
 350
 351               if ( mtd->writesize >512 )
 352                {
 353                         if ( column>= 0 )
 354                          {
 355                            pRK28NC ->chip[master->cs].addr = column  & 0xff;
 356                              pRK28NC ->chip[master->cs].addr = ( column   >> 8) & 0xff;
 357                          }
 358                         if ( page_addr>=0 )
 359                            {
 360                                 pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 361                                 pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF;
 362                                 pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff;
 363                            }
 364                         pRK28NC ->chip[master->cs].cmd = NAND_CMD_READSTART;
 365               }
 366                 else
 367                 {
 368                    pRK28NC ->chip[master->cs].addr = column;
 369                 }
 370
 371                 rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 372
 373
 374                 break;
 375
 376         case NAND_CMD_PAGEPROG:
 377                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 378                 pRK28NC ->chip[master->cs].cmd = command;
 379                 rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT);
 380
 381                 pRK28NC ->chip[master->cs].cmd  = NAND_CMD_STATUS;
 382                 status = pRK28NC ->chip[master->cs].data;
 383
 384                 if(status&0x1)
 385                         ret = -1;
 386                 else
 387                         ret =0;
 388
 389                 break;
 390
 391         case NAND_CMD_ERASE1:
 392                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 393                 pRK28NC ->BCHCTL = 0x0;
 394                 pRK28NC ->chip[master->cs].cmd  = command;
 395                 if ( page_addr>=0 )
 396                    {
 397                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 398                         pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff;
 399                         pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff;
 400                    }
 401                 break;
 402
 403         case NAND_CMD_ERASE2:
 404                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 405                 pRK28NC ->chip[master->cs].cmd  = command;
 406                 rk2818_nand_wait_busy(mtd,ERASE_BUSY_COUNT);
 407                 pRK28NC ->chip[master->cs].cmd  = NAND_CMD_STATUS;
 408                 status = pRK28NC ->chip[master->cs].data;
 409
 410                 if(status&0x1)
 411                         ret = -1;
 412                 else
 413                         ret =0;
 414
 415                 break;
 416
 417         case NAND_CMD_SEQIN:
 418                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 419                 pRK28NC ->chip[master->cs].cmd  = command;
 420                udelay(1);
 421                 if ( column>= 0 )
 422                   {
 423                    pRK28NC ->chip[master->cs].addr = column;
 424                      if( mtd->writesize > 512)
 425                        pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff;
 426                   }
 427                 if( page_addr>=0 )
 428                   {
 429                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 430                         pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff;
 431                         pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff;
 432                  }
 433
 434                 break;
 435
 436         case NAND_CMD_STATUS:
 437                 pRK28NC ->BCHCTL = 0x0;
 438                 pRK28NC ->chip[master->cs].cmd = command;
 439                 while (timeout>0)
 440                 {
 441                  timeout --;
 442                    udelay(1);
 443                   if(pRK28NC->FLCTL&FL_INTCLR)
 444                          break;
 445
 446                 }
 447                 break;
 448
 449         case NAND_CMD_RESET:
 450                 pRK28NC ->chip[master->cs].cmd = command;
 451                 while (timeout>0)
 452                 {
 453                  timeout --;
 454                    udelay(1);
 455                   if(pRK28NC->FLCTL&FL_INTCLR)
 456                          break;
 457
 458                 }
 459                 rk2818_nand_wait_busy(mtd,RESET_BUSY_COUNT);
 460                 break;
 461
 462         /* This applies to read commands */
 463         default:
 464                pRK28NC ->chip[master->cs].cmd = command;
 465                 break;
 466         }
 467
 468         udelay (1);
 469
 470 }
 471
 472 int rk2818_nand_calculate_ecc(struct mtd_info *mtd,const uint8_t *dat,uint8_t *ecc_code)
 473 {
 474      struct nand_chip *nand_chip = mtd->priv;
 475      struct rk2818_nand_mtd *master = nand_chip->priv;
 476      pNANDC pRK28NC=  (pNANDC)(master->regs);
 477
 478      int eccdata[7],i;
 479
 480         for(i=0;i<7;i++)
 481          {
 482             eccdata[i] = pRK28NC->spare[i+1];
 483
 484
 485             ecc_code[i*4] = eccdata[i]& 0xff;
 486             ecc_code[i*4+1] = (eccdata[i]>> 8)& 0xff;
 487             ecc_code[i*4+2] = (eccdata[i]>>16)& 0xff;
 488             ecc_code[i*4+3] = (eccdata[i]>>24)& 0xff;
 489
 490           }
 491
 492      return 0;
 493 }
 494
 495  void rk2818_nand_hwctl_ecc(struct mtd_info *mtd, int mode)
 496  {
 497        struct nand_chip *nand_chip = mtd->priv;
 498         struct rk2818_nand_mtd *master = nand_chip->priv;
 499         pNANDC pRK28NC=  (pNANDC)(master->regs);
 500
 501         pRK28NC->BCHCTL = 1;  // reset bch and enable hw ecc
 502
 503        return;
 504  }
 505
 506  int rk2818_nand_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,uint8_t *calc_ecc)
 507  {
 508        struct nand_chip *nand_chip = mtd->priv;
 509         struct rk2818_nand_mtd *master = nand_chip->priv;
 510         pNANDC pRK28NC=  (pNANDC)(master->regs);
 511
 512         // hw correct data
 513        if( pRK28NC->BCHST & (1<<2) )
 514          {
 515                 DEBUG(MTD_DEBUG_LEVEL0,
 516                       "rk2818 nand :hw ecc uncorrectable error\n");
 517                 return -1;
 518         }
 519
 520        return 0;
 521  }
 522
 523  int rk2818_nand_read_page(struct mtd_info *mtd,struct nand_chip *chip,uint8_t *buf, int page)
 524  {
 525        struct nand_chip *nand_chip = mtd->priv;
 526         struct rk2818_nand_mtd *master = nand_chip->priv;
 527         pNANDC pRK28NC=  (pNANDC)(master->regs);
 528
 529         int i,chipnr;
 530
 531
 532         mutex_lock(&rknand_mutex);
 533
 534         chipnr = master->cs ;
 535
 536         rk2818_nand_select_chip(mtd,chipnr);
 537
 538
 539         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 540
 541        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 542
 543         for(i=0;i<mtd->writesize/0x400;i++)
 544         {
 545                pRK28NC ->BCHCTL = BCH_RST;
 546                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 547                 wait_op_done(mtd,TROP_US_DELAY,0);
 548                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 549
 550               memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 551         }
 552
 553
 554         rk2818_nand_select_chip(mtd,-1);
 555
 556         mutex_unlock(&rknand_mutex);
 557
 558     return 0;
 559
 560  }
 561
 562 void  rk2818_nand_write_page(struct mtd_info *mtd,struct nand_chip *chip,const uint8_t *buf)
 563  {
 564        struct nand_chip *nand_chip = mtd->priv;
 565         struct rk2818_nand_mtd *master = nand_chip->priv;
 566         pNANDC pRK28NC=  (pNANDC)(master->regs);
 567        uint32_t  i = 0, chipnr;
 568
 569         mutex_lock(&rknand_mutex);
 570
 571        chipnr = master->cs ;
 572
 573         rk2818_nand_select_chip(mtd,chipnr);
 574
 575         pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 576
 577
 578           for(i=0;i<mtd->writesize/0x400;i++)
 579            {
 580                memcpy((u_char *)(pRK28NC->buf),(buf+i*0x400),0x400);  //  only use nandc sram0
 581                if(i==0)
 582                    memcpy((u_char *)(pRK28NC->spare),(u_char *)(chip->oob_poi + chip->ops.ooboffs),4);
 583
 584                 pRK28NC ->BCHCTL = BCH_WR|BCH_RST;
 585                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_RDN|FL_BYPASS|FL_START;
 586                 wait_op_done(mtd,TROP_US_DELAY,0);
 587            }
 588
 589          pRK28NC ->chip[0].cmd = NAND_CMD_PAGEPROG;
 590
 591
 592
 593           rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT);
 594
 595          rk2818_nand_select_chip(mtd,-1);
 596
 597      mutex_unlock(&rknand_mutex);
 598
 599     return;
 600
 601  }
 602
 603 int rk2818_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd)
 604 {
 605        struct nand_chip *nand_chip = mtd->priv;
 606         struct rk2818_nand_mtd *master = nand_chip->priv;
 607         pNANDC pRK28NC=  (pNANDC)(master->regs);
 608        int i,chipnr;
 609
 610
 611         if (sndcmd) {
 612                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 613                 sndcmd = 0;
 614         }
 615
 616         mutex_lock(&rknand_mutex);
 617
 618         chipnr = master->cs ;
 619
 620         rk2818_nand_select_chip(mtd,chipnr);
 621
 622         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 623
 624
 625        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 626
 627
 628
 629
 630         for(i=0;i<mtd->writesize/0x400;i++)
 631         {
 632                pRK28NC ->BCHCTL = BCH_RST;
 633                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 634                 wait_op_done(mtd,TROP_US_DELAY,0);
 635                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 636               if(i==0)
 637                  memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4);
 638         }
 639
 640
 641          rk2818_nand_select_chip(mtd,-1);
 642
 643          mutex_unlock(&rknand_mutex);
 644
 645
 646         return sndcmd;
 647 }
 648
 649 int     rk2818_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page)
 650 {
 651        struct nand_chip *nand_chip = mtd->priv;
 652         struct rk2818_nand_mtd *master = nand_chip->priv;
 653         pNANDC pRK28NC=  (pNANDC)(master->regs);
 654
 655         int i,chipnr;
 656
 657
 658     mutex_lock(&rknand_mutex);
 659
 660         chipnr = master->cs ;
 661
 662         rk2818_nand_select_chip(mtd,chipnr);
 663
 664         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 665
 666        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 667
 668
 669
 670         for(i=0;i<mtd->writesize/0x400;i++)
 671         {
 672                pRK28NC ->BCHCTL = BCH_RST;
 673                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 674                 wait_op_done(mtd,TROP_US_DELAY,0);
 675                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 676               memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 677               if(i==0)
 678                  memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4);
 679         }
 680
 681
 682          rk2818_nand_select_chip(mtd,-1);
 683          mutex_unlock(&rknand_mutex);
 684
 685
 686     return 0;
 687 }
 688
 689 static int rk2818_nand_setrate(struct rk2818_nand_mtd *info)
 690 {
 691         pNANDC pRK28NC=  (pNANDC)(info->regs);
 692
 693         unsigned long clkrate = clk_get_rate(info->clk);
 694
 695        u_char accesstime,rwpw,csrw,rwcs;
 696
 697         unsigned int ns=0,timingcfg;
 698
 699        unsigned long flags;
 700
 701        //scan nand flash access time
 702        if ( info->accesstime ==0x00 )
 703               accesstime=50;
 704        else if ( info->accesstime==0x80)
 705                 accesstime=25;
 706         else if ( info->accesstime==0x08)
 707                 accesstime=20;
 708         else
 709                 accesstime=60;   //60ns
 710
 711        info->clk_rate = clkrate;
 712         clkrate /= 1000000;     /* turn clock into MHz for ease of use */
 713
 714        if(clkrate>0 && clkrate<200)
 715            ns= 1000/clkrate; // ns
 716          else
 717            return -1;
 718
 719         timingcfg = (accesstime + ns -1)/ns;
 720
 721         timingcfg = (timingcfg>=3) ? (timingcfg-2) : timingcfg;           //csrw+1, rwcs+1
 722
 723         rwpw = timingcfg-timingcfg/4;
 724         csrw = timingcfg/4;
 725         rwcs = (timingcfg/4 >=1)?(timingcfg/4):1;
 726
 727         mutex_lock(&rknand_mutex);
 728
 729         pRK28NC ->FMWAIT |=  (rwcs<<FMW_RWCS_OFFSET)|(rwpw<<FMW_RWPW_OFFSET)|(csrw<<FMW_CSRW_OFFSET);
 730
 731         mutex_unlock(&rknand_mutex);
 732
 733
 734         return 0;
 735 }
 736
 737 /* cpufreq driver support */
 738
 739 #ifdef CONFIG_CPU_FREQ
 740
 741 static int rk2818_nand_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
 742 {
 743         struct rk2818_nand_mtd *info;
 744         unsigned long newclk;
 745
 746         info = container_of(nb, struct rk2818_nand_mtd, freq_transition);
 747         newclk = clk_get_rate(info->clk);
 748
 749         if (val == CPUFREQ_POSTCHANGE && newclk != info->clk_rate)
 750          {
 751                 rk2818_nand_setrate(info);
 752         }
 753
 754         return 0;
 755 }
 756
 757 static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info)
 758 {
 759         info->freq_transition.notifier_call = rk2818_nand_cpufreq_transition;
 760
 761         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 762 }
 763
 764 static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info)
 765 {
 766         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 767 }
 768
 769 #else
 770 static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info)
 771 {
 772         return 0;
 773 }
 774
 775 static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info)
 776 {
 777 }
 778 #endif
 779
 780
 781 static int rk2818_nand_probe(struct platform_device *pdev)
 782 {
 783        struct nand_chip *this;
 784         struct mtd_info *mtd;
 785         struct rk2818_nand_platform_data *pdata = pdev->dev.platform_data;
 786         struct rk2818_nand_mtd *master;
 787         struct resource *res;
 788         int err = 0;
 789         pNANDC pRK28NC;
 790         u_char  maf_id,dev_id,ext_id3,ext_id4;
 791     struct nand_chip *chip;
 792
 793 #ifdef CONFIG_MTD_PARTITIONS
 794         struct mtd_partition *partitions = NULL;
 795         int num_partitions = 0;
 796 #endif
 797
 798       /* Allocate memory for MTD device structure and private data */
 799         master = kzalloc(sizeof(struct rk2818_nand_mtd), GFP_KERNEL);
 800         if (!master)
 801                 return -ENOMEM;
 802
 803          master->dev = &pdev->dev;
 804         /* structures must be linked */
 805         this = &master->nand;
 806         mtd = &master->mtd;
 807         mtd->priv = this;
 808         mtd->owner = THIS_MODULE;
 809        mtd->name = dev_name(&pdev->dev);
 810
 811         /* 50 us command delay time */
 812         this->chip_delay = 5;
 813
 814         this->priv = master;
 815         this->dev_ready = rk2818_nand_dev_ready;
 816         this->cmdfunc = rk2818_nand_cmdfunc;
 817         this->select_chip = rk2818_nand_select_chip;
 818         this->read_byte = rk2818_nand_read_byte;
 819         this->read_word = rk2818_nand_read_word;
 820         this->write_buf = rk2818_nand_write_buf;
 821         this->read_buf = rk2818_nand_read_buf;
 822         this->options |= NAND_USE_FLASH_BBT;    // open bbt options
 823
 824
 825         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 826         if (!res) {
 827                 err = -ENODEV;
 828                 goto outres;
 829         }
 830
 831         master->regs = ioremap(res->start, res->end - res->start + 1);
 832         if (!master->regs) {
 833                 err = -EIO;
 834                 goto outres;
 835         }
 836
 837         if (pdata->hw_ecc) {
 838                 this->ecc.calculate = rk2818_nand_calculate_ecc;
 839                 this->ecc.hwctl = rk2818_nand_hwctl_ecc;
 840                 this->ecc.correct = rk2818_nand_correct_data;
 841                 this->ecc.mode = NAND_ECC_HW;
 842                 this->ecc.read_page = rk2818_nand_read_page;
 843                 this->ecc.write_page = rk2818_nand_write_page;
 844                 this->ecc.read_oob = rk2818_nand_read_oob;
 845                 this->ecc.read_page_raw = rk2818_nand_read_page_raw;
 846                 this->ecc.size = 1024;
 847                 this->ecc.bytes = 28;
 848                 this->ecc.layout = &nand_hw_eccoob_16;
 849         } else {
 850                 this->ecc.size = 256;
 851                 this->ecc.bytes = 3;
 852                 this->ecc.layout = &nand_sw_eccoob_8;
 853                 this->ecc.mode = NAND_ECC_SOFT;
 854         }
 855
 856
 857        mutex_init(&rknand_mutex);
 858
 859         master->clk = clk_get(NULL, "nandc");
 860
 861         clk_enable(master->clk);
 862
 863        pRK28NC =  (pNANDC)(master->regs);
 864        pRK28NC ->FMCTL = FMC_WP|FMC_FRDY;
 865        pRK28NC ->FMWAIT |=  (1<<FMW_RWCS_OFFSET)|(4<<FMW_RWPW_OFFSET)|(1<<FMW_CSRW_OFFSET);
 866         pRK28NC ->BCHCTL = 0x1;
 867
 868        this->select_chip(mtd, 0);
 869         this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 870         maf_id = this->read_byte(mtd);
 871         dev_id = this->read_byte(mtd);
 872        ext_id3 = this->read_byte(mtd);
 873         ext_id4 = this->read_byte(mtd);
 874
 875        master->accesstime = ext_id4&0x88;
 876
 877         rk2818_nand_setrate(master);
 878
 879         /* Reset NAND */
 880         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 881         /* NAND bus width determines access funtions used by upper layer */
 882         if (pdata->width == 2) {
 883                 this->options |= NAND_BUSWIDTH_16;
 884                 this->ecc.layout = &nand_hw_eccoob_16;
 885         }
 886       // iomux flash  cs1~cs7
 887       rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1);
 888       rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2);
 889       rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3);
 890       rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45);
 891       rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67);
 892
 893         /* Scan to find existence of the device */
 894            if (nand_scan(mtd, 8)) {     // rk2818 nandc support max 8 cs
 895
 896                 DEBUG(MTD_DEBUG_LEVEL0,
 897                       "RK2818 NAND: Unable to find any NAND device.\n");
 898                 err = -ENXIO;
 899                 goto outscan;
 900         }
 901
 902         //¸ù¾ÝÆ¬Ñ¡Çé¿ö»Ö¸´IO MUXÔÊ¼Öµ
 903     chip = mtd->priv;
 904     switch(chip->numchips)
 905     {
 906         case 1:
 907             rk2818_mux_api_mode_resume(GPIOA5_FLASHCS1_SEL_NAME);
 908         case 2:
 909             rk2818_mux_api_mode_resume(GPIOA6_FLASHCS2_SEL_NAME);
 910         case 3:
 911             rk2818_mux_api_mode_resume(GPIOA7_FLASHCS3_SEL_NAME);
 912         case 4:
 913             rk2818_mux_api_mode_resume(GPIOE_SPI1_FLASH_SEL1_NAME);
 914         case 5:
 915         case 6:
 916             rk2818_mux_api_mode_resume(GPIOE_SPI1_FLASH_SEL_NAME);
 917         case 7:
 918         case 8:
 919             break;
 920         default:
 921             DEBUG(MTD_DEBUG_LEVEL0, "RK2818 NAND: numchips error!!!\n");
 922     }
 923 #if 0
 924       // rk281x dma mode bch must  (1k data + 32 oob) bytes align , so cheat system writesize =1024,oobsize=32
 925         mtd->writesize = 1024;
 926         mtd->oobsize = 32;
 927 #endif
 928
 929 #ifdef CONFIG_MTD_PARTITIONS
 930         num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0);
 931         if (num_partitions > 0) {
 932                 printk(KERN_INFO "Using commandline partition definition\n");
 933               add_mtd_partitions(mtd, partitions, num_partitions);
 934                 if(partitions)
 935                  kfree(partitions);
 936         } else if (pdata->nr_parts) {
 937                 printk(KERN_INFO "Using board partition definition\n");
 938                 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
 939         } else
 940 #endif
 941         {
 942                 printk(KERN_INFO "no partition info available, registering whole flash at once\n");
 943                 add_mtd_device(mtd);
 944         }
 945
 946         platform_set_drvdata(pdev, master);
 947
 948         err =rk2818_nand_cpufreq_register(master);
 949         if (err < 0) {
 950                 printk(KERN_ERR"rk2818 nand failed to init cpufreq support\n");
 951                 goto outscan;
 952         }
 953
 954         return 0;
 955
 956 outres:
 957 outscan:
 958         iounmap(master->regs);
 959         kfree(master);
 960
 961         return err;
 962
 963 }
 964
 965 static int rk2818_nand_remove(struct platform_device *pdev)
 966 {
 967         struct rk2818_nand_mtd *master = platform_get_drvdata(pdev);
 968
 969         platform_set_drvdata(pdev, NULL);
 970
 971        if(master == NULL)
 972                 return 0;
 973
 974         rk2818_nand_cpufreq_deregister(master);
 975
 976
 977         nand_release(&master->mtd);
 978
 979         if(master->regs!=NULL){
 980                 iounmap(master->regs);
 981                 master->regs = NULL;
 982         }
 983
 984         if (master->clk != NULL && !IS_ERR(master->clk)) {
 985                 clk_disable(master->clk);
 986                 clk_put(master->clk);
 987         }
 988
 989         kfree(master);
 990
 991         return 0;
 992 }
 993
 994 #ifdef CONFIG_PM
 995 static int rk2818_nand_suspend(struct platform_device *pdev, pm_message_t state)
 996 {
 997         struct mtd_info *info = platform_get_drvdata(pdev);
 998         int ret = 0;
 999
1000         DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND suspend\n");
1001         if (info)
1002                 ret = info->suspend(info);
1003         return ret;
1004 }
1005
1006 static int rk2818_nand_resume(struct platform_device *pdev)
1007 {
1008         struct mtd_info *info = platform_get_drvdata(pdev);
1009         int ret = 0;
1010
1011         DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND resume\n");
1012         /* Enable the NFC clock */
1013
1014         if (info)
1015                 info->resume(info);
1016
1017         return ret;
1018 }
1019 #else
1020 #define rk2818_nand_suspend   NULL
1021 #define rk2818_nand_resume    NULL
1022 #endif  /* CONFIG_PM */
1023
1024
1025 static struct platform_driver rk2818_nand_driver = {
1026         .driver = {
1027                    .name = "rk2818-nand",
1028                    },
1029        .probe    = rk2818_nand_probe,
1030         .remove = rk2818_nand_remove,
1031         .suspend = rk2818_nand_suspend,
1032         .resume = rk2818_nand_resume,
1033 };
1034
1035 static int __init rk2818_nand_init(void)
1036 {
1037         /* Register the device driver structure. */
1038         printk("rk2818_nand_init\n");
1039         return platform_driver_register(&rk2818_nand_driver);;
1040 }
1041
1042 static void __exit rk2818_nand_exit(void)
1043 {
1044         /* Unregister the device structure */
1045         platform_driver_unregister(&rk2818_nand_driver);
1046 }
1047
1048
1049 // nandc dma cs mutex for dm9000 interface
1050 void rk2818_nand_status_mutex_lock(void)
1051 {
1052      pNANDC pRK28NC=  (pNANDC)RK2818_NANDC_BASE;
1053      mutex_lock(&rknand_mutex);
1054      pRK28NC->FMCTL &=0xffffff00;   // release chip select
1055
1056 }
1057
1058 int rk2818_nand_status_mutex_trylock(void)
1059 {
1060      pNANDC pRK28NC=  (pNANDC)RK2818_NANDC_BASE;
1061      if( mutex_trylock(&rknand_mutex))
1062         {
1063                 pRK28NC->FMCTL &=0xffffff00;   // release chip select
1064                 return 1;      // ready
1065         }
1066       else
1067                 return 0;     // busy
1068 }
1069
1070 void rk2818_nand_status_mutex_unlock(void)
1071 {
1072      mutex_unlock(&rknand_mutex);
1073      return;
1074 }
1075
1076 module_init(rk2818_nand_init);
1077 module_exit(rk2818_nand_exit);
1078
1079 MODULE_LICENSE("GPL");
1080 MODULE_AUTHOR("hxy <hxy@rock-chips.com>");
1081 MODULE_DESCRIPTION("MTD NAND driver for rk2818 device");
1082