drivers/mtd/nand/rk2818_nand.c

   1
   2 /*
   3  * drivers/mtd/nand/rk2818_nand.c
   4  *
   5  * Copyright (C) 2010 RockChip, Inc.
   6  * Author: hxy@rock-chips.com
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/mtd/mtd.h>
  23 #include <linux/mtd/nand.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/cpufreq.h>
  30 #include <linux/err.h>
  31 #include <linux/io.h>
  32
  33 #include <mach/rk2818_nand.h>
  34 #include <mach/rk2818_iomap.h>
  35 #include <mach/iomux.h>
  36
  37 #define PROGRAM_BUSY_COUNT   10000
  38 #define ERASE_BUSY_COUNT            20000
  39 #define READ_BUSY_COUNT             5000
  40
  41 /* Define delays in microsec for NAND device operations */
  42 #define TROP_US_DELAY   2000
  43
  44 static struct mutex  rknand_mutex;
  45 //static  spinlock_t    rknand_lock;
  46
  47
  48 struct rk2818_nand_mtd {
  49         struct mtd_info         mtd;
  50         struct nand_chip                nand;
  51         struct mtd_partition    *parts;
  52         struct device           *dev;
  53        const struct rk2818_nand_flash *flash_info;
  54
  55         struct clk                      *clk;
  56         unsigned long                   clk_rate;
  57         void __iomem                    *regs;
  58         int                                     cs;                     // support muliple nand chip,record current chip select
  59         u_char                          accesstime;
  60 #ifdef CONFIG_CPU_FREQ
  61         struct notifier_block   freq_transition;
  62 #endif
  63
  64 };
  65
  66 /* OOB placement block for use with software ecc generation */
  67 static struct nand_ecclayout nand_sw_eccoob_8 = {
  68         .eccbytes = 48,
  69         .eccpos = { 8, 9, 10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,
  70                           32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55},
  71         .oobfree = {{0,8},{56, 72}}
  72 };
  73
  74 /* OOB placement block for use with hardware ecc generation */
  75 static struct nand_ecclayout nand_hw_eccoob_16 = {
  76         .eccbytes = 28,
  77         .eccpos = { 4,  5, 6,  7,  8, 9, 10,11,12,13,14,15,16,17,
  78                           18,19,20,21,22,23,24,25,26,27,28,29,30,31},
  79         .oobfree = {{0, 4}}
  80 };
  81
  82 #ifdef CONFIG_MTD_PARTITIONS
  83 static const char *part_probes[] = { "cmdlinepart", NULL };
  84 #endif
  85
  86
  87 static void rk2818_nand_wait_busy(struct mtd_info *mtd, uint32_t timeout)
  88 {
  89
  90         struct nand_chip *nand_chip = mtd->priv;
  91         struct rk2818_nand_mtd *master = nand_chip->priv;
  92         pNANDC pRK28NC=  (pNANDC)(master->regs);
  93
  94         while (timeout > 0)
  95         {
  96                 timeout--;
  97                 udelay(10);
  98                 if ( pRK28NC->FMCTL& FMC_FRDY)
  99                         break;
 100
 101         }
 102
 103     return;
 104 }
 105
 106 static void rk2818_nand_wait_bchdone(struct mtd_info *mtd, uint32_t timeout)
 107 {
 108
 109         struct nand_chip *nand_chip = mtd->priv;
 110         struct rk2818_nand_mtd *master = nand_chip->priv;
 111         pNANDC pRK28NC=  (pNANDC)(master->regs);
 112
 113         while (timeout > 0)
 114         {
 115                 timeout--;
 116                 udelay(1);
 117                 if(pRK28NC->BCHST &(1<<1))
 118                         break;
 119         }
 120
 121     return;
 122 }
 123
 124 // only for dma mode
 125 static void wait_op_done(struct mtd_info *mtd, int max_retries, uint16_t param)
 126 {
 127        struct nand_chip *nand_chip = mtd->priv;
 128         struct rk2818_nand_mtd *master = nand_chip->priv;
 129         pNANDC pRK28NC=  (pNANDC)(master->regs);
 130
 131         while (max_retries-- > 0) {
 132                 udelay(1);
 133                 if (pRK28NC->FLCTL & FL_RDY)
 134                         break;
 135         }
 136 }
 137
 138 static int rk2818_nand_dev_ready(struct mtd_info *mtd)
 139 {
 140         struct nand_chip *nand_chip = mtd->priv;
 141         struct rk2818_nand_mtd *master = nand_chip->priv;
 142         pNANDC pRK28NC=  (pNANDC)(master->regs);
 143
 144         if(pRK28NC->FMCTL& FMC_FRDY)
 145            return 1;
 146         else
 147            return 0;
 148 }
 149
 150 /*
 151 *  ÉèÖÃÆ¬Ñ¡
 152 */
 153 static void rk2818_nand_select_chip(struct mtd_info *mtd, int chip)
 154 {
 155         struct nand_chip *nand_chip = mtd->priv;
 156         struct rk2818_nand_mtd *master = nand_chip->priv;
 157         pNANDC pRK28NC=  (pNANDC)(master->regs);
 158
 159
 160         if( chip<0 )
 161              pRK28NC->FMCTL &=0xffffff00;   // release chip select
 162         else
 163           {
 164                master->cs = chip;
 165                 pRK28NC->FMCTL &=0xffffff00;
 166                 pRK28NC ->FMCTL |= 0x1<<chip;  // select chip
 167           }
 168
 169 }
 170
 171 /*
 172  *   ¶ÁÒ»¸ö×Ö½ÚÊý¾Ý
 173 */
 174 static u_char rk2818_nand_read_byte(struct mtd_info *mtd)
 175 {
 176         struct nand_chip *nand_chip = mtd->priv;
 177         struct rk2818_nand_mtd *master = nand_chip->priv;
 178         pNANDC pRK28NC=  (pNANDC)(master->regs);
 179
 180         u_char ret = 0;
 181
 182         ret = (u_char)(pRK28NC ->chip[master->cs].data);
 183
 184         return ret;
 185 }
 186
 187 /*
 188  *   ¶ÁÒ»¸öword ³¤¶ÈÊý¾Ý
 189 */
 190 static u16 rk2818_nand_read_word(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *nand_chip = mtd->priv;
 193         struct rk2818_nand_mtd *master = nand_chip->priv;
 194         pNANDC pRK28NC=  (pNANDC)(master->regs);
 195
 196
 197         u_char tmp1 = 0,tmp2=0;
 198         u16 ret=0;
 199
 200         tmp1 = (u_char)(pRK28NC ->chip[master->cs].data);
 201         tmp2 = (u_char)(pRK28NC ->chip[master->cs].data);
 202
 203         ret =   (tmp2 <<8)|tmp1;
 204
 205         return ret;
 206 }
 207
 208 static void rk2818_nand_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 209 {
 210        struct nand_chip *nand_chip = mtd->priv;
 211         struct rk2818_nand_mtd *master = nand_chip->priv;
 212         pNANDC pRK28NC=  (pNANDC)(master->regs);
 213         uint32_t  i, chipnr;
 214
 215        mutex_lock(&rknand_mutex);
 216
 217        chipnr = master->cs ;
 218
 219         rk2818_nand_select_chip(mtd,chipnr);
 220
 221
 222
 223         if ( len < mtd->writesize )   // read oob
 224         {
 225                 pRK28NC ->BCHCTL = BCH_RST;
 226                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 227                 wait_op_done(mtd,TROP_US_DELAY,0);
 228                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 229                 memcpy(buf,(u_char *)(pRK28NC->spare),4);  //  only use nandc sram0
 230         }
 231         else
 232        {
 233            pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 234             for(i=0;i<mtd->writesize/0x400;i++)
 235                 {
 236                        pRK28NC ->BCHCTL = BCH_RST;
 237                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 238                         wait_op_done(mtd,TROP_US_DELAY,0);
 239                         rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 240                 memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 241                 }
 242         }
 243
 244
 245
 246         rk2818_nand_select_chip(mtd,-1);
 247
 248         mutex_unlock(&rknand_mutex);
 249
 250
 251         return;
 252
 253 }
 254
 255 static void rk2818_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 256 {
 257        struct nand_chip *nand_chip = mtd->priv;
 258         struct rk2818_nand_mtd *master = nand_chip->priv;
 259         pNANDC pRK28NC=  (pNANDC)(master->regs);
 260
 261         uint32_t  i = 0, chipnr;
 262
 263
 264          mutex_lock(&rknand_mutex);
 265
 266          chipnr = master->cs ;
 267
 268         rk2818_nand_select_chip(mtd,chipnr);
 269
 270          pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 271
 272
 273           for(i=0;i<mtd->writesize/0x400;i++)
 274             {
 275                memcpy((u_char *)(pRK28NC->buf),buf+i*0x400,0x400);  //  only use nandc sram0
 276                 pRK28NC ->BCHCTL =BCH_WR|BCH_RST;
 277                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|0x1<<5|FL_RDN|FL_BYPASS|FL_START;
 278                 wait_op_done(mtd,TROP_US_DELAY,0);
 279             }
 280
 281
 282
 283        rk2818_nand_select_chip(mtd,-1);
 284
 285           mutex_unlock(&rknand_mutex);
 286
 287
 288 }
 289
 290
 291 static void rk2818_nand_cmdfunc(struct mtd_info *mtd, unsigned command,int column, int page_addr)
 292 {
 293        struct nand_chip *nand_chip = mtd->priv;
 294         struct rk2818_nand_mtd *master = nand_chip->priv;
 295         pNANDC pRK28NC=  (pNANDC)(master->regs);
 296
 297        uint32_t timeout = 1000;
 298         char status,ret;
 299
 300
 301         switch (command) {
 302
 303        case NAND_CMD_READID:
 304                 pRK28NC ->chip[master->cs].cmd = command;
 305                 pRK28NC ->chip[master->cs].addr = 0x0;
 306                 while (timeout>0)
 307                 {
 308                  timeout --;
 309                    udelay(1);
 310                   if(pRK28NC->FLCTL&FL_INTCLR)
 311                          break;
 312
 313                 }
 314
 315                 break;
 316
 317        case NAND_CMD_READ0:
 318               pRK28NC ->chip[master->cs].cmd = command;
 319                if ( column>= 0 )
 320                  {
 321                    pRK28NC ->chip[master->cs].addr = column & 0xff;
 322                    if( mtd->writesize > 512)
 323                          pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff;
 324                  }
 325                 if ( page_addr>=0 )
 326                    {
 327                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 328                         pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF;
 329                         pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff;
 330                    }
 331                 if( mtd->writesize > 512)
 332                     pRK28NC ->chip[0].cmd = NAND_CMD_READSTART;
 333
 334                 rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 335
 336                 break;
 337
 338         case NAND_CMD_READ1:
 339               pRK28NC ->chip[master->cs].cmd = command;
 340                 break;
 341
 342        case NAND_CMD_READOOB:
 343                 pRK28NC ->BCHCTL = 0x0;
 344                 if( mtd->writesize > 512 )
 345                         command = NAND_CMD_READ0;  // È«²¿¶Á£¬°üÀ¨¶Áoob
 346
 347                 pRK28NC ->chip[master->cs].cmd = command;
 348
 349               if ( mtd->writesize >512 )
 350                {
 351                         if ( column>= 0 )
 352                          {
 353                            pRK28NC ->chip[master->cs].addr = (column + mtd->writesize) & 0xff;
 354                              pRK28NC ->chip[master->cs].addr = ( (column + mtd->writesize)  >> 8) & 0xff;
 355                          }
 356                         if ( page_addr>=0 )
 357                            {
 358                                 pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 359                                 pRK28NC ->chip[master->cs].addr = (page_addr >> 8) & 0xFF;
 360                                 pRK28NC ->chip[master->cs].addr = (page_addr >> 16) & 0xff;
 361                            }
 362                         pRK28NC ->chip[master->cs].cmd = NAND_CMD_READSTART;
 363               }
 364                 else
 365                 {
 366                    pRK28NC ->chip[master->cs].addr = column;
 367                 }
 368
 369                 rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 370
 371
 372                 break;
 373
 374         case NAND_CMD_PAGEPROG:
 375                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 376                 pRK28NC ->chip[master->cs].cmd = command;
 377                 rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT);
 378
 379                 pRK28NC ->chip[master->cs].cmd  = NAND_CMD_STATUS;
 380                 status = pRK28NC ->chip[master->cs].data;
 381
 382                 if(status&0x1)
 383                         ret = -1;
 384                 else
 385                         ret =0;
 386
 387                 break;
 388
 389         case NAND_CMD_ERASE1:
 390                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 391                 pRK28NC ->BCHCTL = 0x0;
 392                 pRK28NC ->chip[master->cs].cmd  = command;
 393                 if ( page_addr>=0 )
 394                    {
 395                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 396                         pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff;
 397                         pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff;
 398                    }
 399                 break;
 400
 401         case NAND_CMD_ERASE2:
 402                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 403                 pRK28NC ->chip[master->cs].cmd  = command;
 404                 rk2818_nand_wait_busy(mtd,ERASE_BUSY_COUNT);
 405                 pRK28NC ->chip[master->cs].cmd  = NAND_CMD_STATUS;
 406                 status = pRK28NC ->chip[master->cs].data;
 407
 408                 if(status&0x1)
 409                         ret = -1;
 410                 else
 411                         ret =0;
 412
 413                 break;
 414
 415         case NAND_CMD_SEQIN:
 416                 pRK28NC ->FMCTL |= FMC_WP;  //½â³ýÐ´±£»¤
 417                 pRK28NC ->chip[master->cs].cmd  = command;
 418                udelay(1);
 419                 if ( column>= 0 )
 420                   {
 421                    pRK28NC ->chip[master->cs].addr = column;
 422                      if( mtd->writesize > 512)
 423                        pRK28NC ->chip[master->cs].addr = (column >> 8) & 0xff;
 424                   }
 425                 if( page_addr>=0 )
 426                   {
 427                         pRK28NC ->chip[master->cs].addr = page_addr & 0xff;
 428                         pRK28NC ->chip[master->cs].addr = (page_addr>>8)&0xff;
 429                         pRK28NC ->chip[master->cs].addr = (page_addr>>16)&0xff;
 430                  }
 431
 432                 break;
 433
 434         case NAND_CMD_STATUS:
 435                 pRK28NC ->BCHCTL = 0x0;
 436                 pRK28NC ->chip[master->cs].cmd = command;
 437                 break;
 438
 439         case NAND_CMD_RESET:
 440                 pRK28NC ->chip[master->cs].cmd = command;
 441                 break;
 442
 443         /* This applies to read commands */
 444         default:
 445                pRK28NC ->chip[master->cs].cmd = command;
 446                 break;
 447         }
 448
 449         udelay (1);
 450
 451 }
 452
 453 int rk2818_nand_calculate_ecc(struct mtd_info *mtd,const uint8_t *dat,uint8_t *ecc_code)
 454 {
 455      struct nand_chip *nand_chip = mtd->priv;
 456      struct rk2818_nand_mtd *master = nand_chip->priv;
 457      pNANDC pRK28NC=  (pNANDC)(master->regs);
 458
 459      int eccdata[7],i;
 460
 461         for(i=0;i<7;i++)
 462          {
 463             eccdata[i] = pRK28NC->spare[i+1];
 464
 465
 466             ecc_code[i*4] = eccdata[i]& 0xff;
 467             ecc_code[i*4+1] = (eccdata[i]>> 8)& 0xff;
 468             ecc_code[i*4+2] = (eccdata[i]>>16)& 0xff;
 469             ecc_code[i*4+3] = (eccdata[i]>>24)& 0xff;
 470
 471           }
 472
 473      return 0;
 474 }
 475
 476  void rk2818_nand_hwctl_ecc(struct mtd_info *mtd, int mode)
 477  {
 478        struct nand_chip *nand_chip = mtd->priv;
 479         struct rk2818_nand_mtd *master = nand_chip->priv;
 480         pNANDC pRK28NC=  (pNANDC)(master->regs);
 481
 482         pRK28NC->BCHCTL = 1;  // reset bch and enable hw ecc
 483
 484        return;
 485  }
 486
 487  int rk2818_nand_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,uint8_t *calc_ecc)
 488  {
 489        struct nand_chip *nand_chip = mtd->priv;
 490         struct rk2818_nand_mtd *master = nand_chip->priv;
 491         pNANDC pRK28NC=  (pNANDC)(master->regs);
 492
 493         // hw correct data
 494        if( pRK28NC->BCHST & (1<<2) )
 495          {
 496                 DEBUG(MTD_DEBUG_LEVEL0,
 497                       "rk2818 nand :hw ecc uncorrectable error\n");
 498                 return -1;
 499         }
 500
 501        return 0;
 502  }
 503
 504  int rk2818_nand_read_page(struct mtd_info *mtd,struct nand_chip *chip,uint8_t *buf, int page)
 505  {
 506        struct nand_chip *nand_chip = mtd->priv;
 507         struct rk2818_nand_mtd *master = nand_chip->priv;
 508         pNANDC pRK28NC=  (pNANDC)(master->regs);
 509
 510         int i,chipnr;
 511
 512
 513         mutex_lock(&rknand_mutex);
 514
 515         chipnr = master->cs ;
 516
 517         rk2818_nand_select_chip(mtd,chipnr);
 518
 519
 520         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 521
 522        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 523
 524         for(i=0;i<mtd->writesize/0x400;i++)
 525         {
 526                pRK28NC ->BCHCTL = BCH_RST;
 527                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 528                 wait_op_done(mtd,TROP_US_DELAY,0);
 529                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 530
 531               memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 532         }
 533
 534
 535         rk2818_nand_select_chip(mtd,-1);
 536
 537         mutex_unlock(&rknand_mutex);
 538
 539     return 0;
 540
 541  }
 542
 543 void  rk2818_nand_write_page(struct mtd_info *mtd,struct nand_chip *chip,const uint8_t *buf)
 544  {
 545        struct nand_chip *nand_chip = mtd->priv;
 546         struct rk2818_nand_mtd *master = nand_chip->priv;
 547         pNANDC pRK28NC=  (pNANDC)(master->regs);
 548        uint32_t  i = 0, chipnr;
 549
 550         mutex_lock(&rknand_mutex);
 551
 552        chipnr = master->cs ;
 553
 554         rk2818_nand_select_chip(mtd,chipnr);
 555
 556         pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 557
 558
 559           for(i=0;i<mtd->writesize/0x400;i++)
 560            {
 561                memcpy((u_char *)(pRK28NC->buf),(buf+i*0x400),0x400);  //  only use nandc sram0
 562                if(i==0)
 563                    memcpy((u_char *)(pRK28NC->spare),(u_char *)(chip->oob_poi + chip->ops.ooboffs),4);
 564
 565                 pRK28NC ->BCHCTL = BCH_WR|BCH_RST;
 566                 pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_RDN|FL_BYPASS|FL_START;
 567                 wait_op_done(mtd,TROP_US_DELAY,0);
 568            }
 569
 570          pRK28NC ->chip[0].cmd = NAND_CMD_PAGEPROG;
 571
 572
 573
 574           rk2818_nand_wait_busy(mtd,PROGRAM_BUSY_COUNT);
 575
 576          rk2818_nand_select_chip(mtd,-1);
 577
 578      mutex_unlock(&rknand_mutex);
 579
 580     return;
 581
 582  }
 583
 584 int rk2818_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd)
 585 {
 586        struct nand_chip *nand_chip = mtd->priv;
 587         struct rk2818_nand_mtd *master = nand_chip->priv;
 588         pNANDC pRK28NC=  (pNANDC)(master->regs);
 589        int i,chipnr;
 590
 591
 592         if (sndcmd) {
 593                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 594                 sndcmd = 0;
 595         }
 596
 597         mutex_lock(&rknand_mutex);
 598
 599         chipnr = master->cs ;
 600
 601         rk2818_nand_select_chip(mtd,chipnr);
 602
 603         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 604
 605
 606        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 607
 608
 609
 610
 611         for(i=0;i<mtd->writesize/0x400;i++)
 612         {
 613                pRK28NC ->BCHCTL = BCH_RST;
 614                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 615                 wait_op_done(mtd,TROP_US_DELAY,0);
 616                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 617               if(i==0)
 618                  memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4);
 619         }
 620
 621
 622          rk2818_nand_select_chip(mtd,-1);
 623
 624          mutex_unlock(&rknand_mutex);
 625
 626
 627         return sndcmd;
 628 }
 629
 630 int     rk2818_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page)
 631 {
 632        struct nand_chip *nand_chip = mtd->priv;
 633         struct rk2818_nand_mtd *master = nand_chip->priv;
 634         pNANDC pRK28NC=  (pNANDC)(master->regs);
 635
 636         int i,chipnr;
 637
 638
 639     mutex_lock(&rknand_mutex);
 640
 641         chipnr = master->cs ;
 642
 643         rk2818_nand_select_chip(mtd,chipnr);
 644
 645         rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
 646
 647        pRK28NC->FLCTL |= FL_BYPASS;  // dma mode
 648
 649
 650
 651         for(i=0;i<mtd->writesize/0x400;i++)
 652         {
 653                pRK28NC ->BCHCTL = BCH_RST;
 654                pRK28NC ->FLCTL = (0<<4)|FL_COR_EN|(0x1<<5)|FL_BYPASS|FL_START ;
 655                 wait_op_done(mtd,TROP_US_DELAY,0);
 656                 rk2818_nand_wait_bchdone(mtd,TROP_US_DELAY) ;
 657               memcpy(buf+i*0x400,(u_char *)(pRK28NC->buf),0x400);  //  only use nandc sram0
 658               if(i==0)
 659                  memcpy((u_char *)(chip->oob_poi+ chip->ops.ooboffs),(u_char *)(pRK28NC->spare),4);
 660         }
 661
 662
 663          rk2818_nand_select_chip(mtd,-1);
 664          mutex_unlock(&rknand_mutex);
 665
 666
 667     return 0;
 668 }
 669
 670 static int rk2818_nand_setrate(struct rk2818_nand_mtd *info)
 671 {
 672         pNANDC pRK28NC=  (pNANDC)(info->regs);
 673
 674         unsigned long clkrate = clk_get_rate(info->clk);
 675
 676        u_char accesstime,rwpw,csrw,rwcs;
 677
 678         unsigned int ns=0,timingcfg;
 679
 680        unsigned long flags;
 681
 682        //scan nand flash access time
 683        if ( info->accesstime ==0x00 )
 684               accesstime=50;
 685        else if ( info->accesstime==0x80)
 686                 accesstime=25;
 687         else if ( info->accesstime==0x08)
 688                 accesstime=20;
 689         else
 690                 accesstime=60;   //60ns
 691
 692        info->clk_rate = clkrate;
 693         clkrate /= 1000000;     /* turn clock into MHz for ease of use */
 694
 695        if(clkrate>0 && clkrate<200)
 696            ns= 1000/clkrate; // ns
 697          else
 698            return -1;
 699
 700         timingcfg = (accesstime + ns -1)/ns;
 701
 702         timingcfg = (timingcfg>=3) ? (timingcfg-2) : timingcfg;           //csrw+1, rwcs+1
 703
 704         rwpw = timingcfg-timingcfg/4;
 705         csrw = timingcfg/4;
 706         rwcs = (timingcfg/4 >=1)?(timingcfg/4):1;
 707
 708         mutex_lock(&rknand_mutex);
 709
 710         pRK28NC ->FMWAIT |=  (rwcs<<FMW_RWCS_OFFSET)|(rwpw<<FMW_RWPW_OFFSET)|(csrw<<FMW_CSRW_OFFSET);
 711
 712         mutex_unlock(&rknand_mutex);
 713
 714
 715         return 0;
 716 }
 717
 718 /* cpufreq driver support */
 719
 720 #ifdef CONFIG_CPU_FREQ
 721
 722 static int rk2818_nand_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
 723 {
 724         struct rk2818_nand_mtd *info;
 725         unsigned long newclk;
 726
 727         info = container_of(nb, struct rk2818_nand_mtd, freq_transition);
 728         newclk = clk_get_rate(info->clk);
 729
 730         if (val == CPUFREQ_POSTCHANGE && newclk != info->clk_rate)
 731          {
 732                 rk2818_nand_setrate(info);
 733         }
 734
 735         return 0;
 736 }
 737
 738 static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info)
 739 {
 740         info->freq_transition.notifier_call = rk2818_nand_cpufreq_transition;
 741
 742         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 743 }
 744
 745 static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info)
 746 {
 747         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 748 }
 749
 750 #else
 751 static inline int rk2818_nand_cpufreq_register(struct rk2818_nand_mtd *info)
 752 {
 753         return 0;
 754 }
 755
 756 static inline void rk2818_nand_cpufreq_deregister(struct rk2818_nand_mtd *info)
 757 {
 758 }
 759 #endif
 760
 761
 762 static int rk2818_nand_probe(struct platform_device *pdev)
 763 {
 764        struct nand_chip *this;
 765         struct mtd_info *mtd;
 766         struct rk2818_nand_platform_data *pdata = pdev->dev.platform_data;
 767         struct rk2818_nand_mtd *master;
 768         struct resource *res;
 769         int err = 0;
 770         pNANDC pRK28NC;
 771         u_char  maf_id,dev_id,ext_id3,ext_id4;
 772
 773 #ifdef CONFIG_MTD_PARTITIONS
 774         struct mtd_partition *partitions = NULL;
 775         int num_partitions = 0;
 776 #endif
 777
 778       /* Allocate memory for MTD device structure and private data */
 779         master = kzalloc(sizeof(struct rk2818_nand_mtd), GFP_KERNEL);
 780         if (!master)
 781                 return -ENOMEM;
 782
 783          master->dev = &pdev->dev;
 784         /* structures must be linked */
 785         this = &master->nand;
 786         mtd = &master->mtd;
 787         mtd->priv = this;
 788         mtd->owner = THIS_MODULE;
 789        mtd->name = dev_name(&pdev->dev);
 790
 791         /* 50 us command delay time */
 792         this->chip_delay = 5;
 793
 794         this->priv = master;
 795         this->dev_ready = rk2818_nand_dev_ready;
 796         this->cmdfunc = rk2818_nand_cmdfunc;
 797         this->select_chip = rk2818_nand_select_chip;
 798         this->read_byte = rk2818_nand_read_byte;
 799         this->read_word = rk2818_nand_read_word;
 800         this->write_buf = rk2818_nand_write_buf;
 801         this->read_buf = rk2818_nand_read_buf;
 802         this->options |= NAND_USE_FLASH_BBT;    // open bbt options
 803
 804
 805         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 806         if (!res) {
 807                 err = -ENODEV;
 808                 goto outres;
 809         }
 810
 811         master->regs = ioremap(res->start, res->end - res->start + 1);
 812         if (!master->regs) {
 813                 err = -EIO;
 814                 goto outres;
 815         }
 816
 817         if (pdata->hw_ecc) {
 818                 this->ecc.calculate = rk2818_nand_calculate_ecc;
 819                 this->ecc.hwctl = rk2818_nand_hwctl_ecc;
 820                 this->ecc.correct = rk2818_nand_correct_data;
 821                 this->ecc.mode = NAND_ECC_HW;
 822                 this->ecc.read_page = rk2818_nand_read_page;
 823                 this->ecc.write_page = rk2818_nand_write_page;
 824                 this->ecc.read_oob = rk2818_nand_read_oob;
 825                 this->ecc.read_page_raw = rk2818_nand_read_page_raw;
 826                 this->ecc.size = 1024;
 827                 this->ecc.bytes = 28;
 828                 this->ecc.layout = &nand_hw_eccoob_16;
 829         } else {
 830                 this->ecc.size = 256;
 831                 this->ecc.bytes = 3;
 832                 this->ecc.layout = &nand_sw_eccoob_8;
 833                 this->ecc.mode = NAND_ECC_SOFT;
 834         }
 835
 836
 837        mutex_init(&rknand_mutex);
 838
 839         master->clk = clk_get(NULL, "nandc");
 840
 841         clk_enable(master->clk);
 842
 843        pRK28NC =  (pNANDC)(master->regs);
 844        pRK28NC ->FMCTL = FMC_WP|FMC_FRDY;
 845        pRK28NC ->FMWAIT |=  (1<<FMW_RWCS_OFFSET)|(4<<FMW_RWPW_OFFSET)|(1<<FMW_CSRW_OFFSET);
 846         pRK28NC ->BCHCTL = 0x1;
 847
 848        this->select_chip(mtd, 0);
 849         this->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 850         maf_id = this->read_byte(mtd);
 851         dev_id = this->read_byte(mtd);
 852        ext_id3 = this->read_byte(mtd);
 853         ext_id4 = this->read_byte(mtd);
 854
 855        master->accesstime = ext_id4&0x88;
 856
 857         rk2818_nand_setrate(master);
 858
 859         /* Reset NAND */
 860         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 861         /* NAND bus width determines access funtions used by upper layer */
 862         if (pdata->width == 2) {
 863                 this->options |= NAND_BUSWIDTH_16;
 864                 this->ecc.layout = &nand_hw_eccoob_16;
 865         }
 866
 867       // iomux flash  cs1~cs7
 868       rk2818_mux_api_set(GPIOA5_FLASHCS1_SEL_NAME, IOMUXB_FLASH_CS1);
 869       rk2818_mux_api_set(GPIOA6_FLASHCS2_SEL_NAME, IOMUXB_FLASH_CS2);
 870       rk2818_mux_api_set(GPIOA7_FLASHCS3_SEL_NAME, IOMUXB_FLASH_CS3);
 871       rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL1_NAME, IOMUXA_FLASH_CS45);
 872       rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_FLASH_CS67);
 873
 874         /* Scan to find existence of the device */
 875            if (nand_scan(mtd, 8)) {     // rk2818 nandc support max 8 cs
 876
 877                 DEBUG(MTD_DEBUG_LEVEL0,
 878                       "RK2818 NAND: Unable to find any NAND device.\n");
 879                 err = -ENXIO;
 880                 goto outscan;
 881         }
 882
 883 #if 0
 884       // rk281x dma mode bch must  (1k data + 32 oob) bytes align , so cheat system writesize =1024,oobsize=32
 885         mtd->writesize = 1024;
 886         mtd->oobsize = 32;
 887 #endif
 888
 889 #ifdef CONFIG_MTD_PARTITIONS
 890         num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0);
 891         if (num_partitions > 0) {
 892                 printk(KERN_INFO "Using commandline partition definition\n");
 893               add_mtd_partitions(mtd, partitions, num_partitions);
 894                 if(partitions)
 895                  kfree(partitions);
 896         } else if (pdata->nr_parts) {
 897                 printk(KERN_INFO "Using board partition definition\n");
 898                 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
 899         } else
 900 #endif
 901         {
 902                 printk(KERN_INFO "no partition info available, registering whole flash at once\n");
 903                 add_mtd_device(mtd);
 904         }
 905
 906         platform_set_drvdata(pdev, master);
 907
 908         err =rk2818_nand_cpufreq_register(master);
 909         if (err < 0) {
 910                 printk(KERN_ERR"rk2818 nand failed to init cpufreq support\n");
 911                 goto outscan;
 912         }
 913
 914         return 0;
 915
 916 outres:
 917 outscan:
 918         iounmap(master->regs);
 919         kfree(master);
 920
 921         return err;
 922
 923 }
 924
 925 static int rk2818_nand_remove(struct platform_device *pdev)
 926 {
 927         struct rk2818_nand_mtd *master = platform_get_drvdata(pdev);
 928
 929         platform_set_drvdata(pdev, NULL);
 930
 931        if(master == NULL)
 932                 return 0;
 933
 934         rk2818_nand_cpufreq_deregister(master);
 935
 936
 937         nand_release(&master->mtd);
 938
 939         if(master->regs!=NULL){
 940                 iounmap(master->regs);
 941                 master->regs = NULL;
 942         }
 943
 944         if (master->clk != NULL && !IS_ERR(master->clk)) {
 945                 clk_disable(master->clk);
 946                 clk_put(master->clk);
 947         }
 948
 949         kfree(master);
 950
 951         return 0;
 952 }
 953
 954 #ifdef CONFIG_PM
 955 static int rk2818_nand_suspend(struct platform_device *pdev, pm_message_t state)
 956 {
 957         struct mtd_info *info = platform_get_drvdata(pdev);
 958         int ret = 0;
 959
 960         DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND suspend\n");
 961         if (info)
 962                 ret = info->suspend(info);
 963         return ret;
 964 }
 965
 966 static int rk2818_nand_resume(struct platform_device *pdev)
 967 {
 968         struct mtd_info *info = platform_get_drvdata(pdev);
 969         int ret = 0;
 970
 971         DEBUG(MTD_DEBUG_LEVEL0, "RK2818_NAND : NAND resume\n");
 972         /* Enable the NFC clock */
 973
 974         if (info)
 975                 info->resume(info);
 976
 977         return ret;
 978 }
 979 #else
 980 #define rk2818_nand_suspend   NULL
 981 #define rk2818_nand_resume    NULL
 982 #endif  /* CONFIG_PM */
 983
 984
 985 static struct platform_driver rk2818_nand_driver = {
 986         .driver = {
 987                    .name = "rk2818-nand",
 988                    },
 989        .probe    = rk2818_nand_probe,
 990         .remove = rk2818_nand_remove,
 991         .suspend = rk2818_nand_suspend,
 992         .resume = rk2818_nand_resume,
 993 };
 994
 995 static int __init rk2818_nand_init(void)
 996 {
 997         /* Register the device driver structure. */
 998         printk("rk2818_nand_init\n");
 999         return platform_driver_register(&rk2818_nand_driver);;
1000 }
1001
1002 static void __exit rk2818_nand_exit(void)
1003 {
1004         /* Unregister the device structure */
1005         platform_driver_unregister(&rk2818_nand_driver);
1006 }
1007
1008
1009 // nandc dma cs mutex for dm9000 interface
1010 int rk2818_nand_status_mutex_trylock(void)
1011 {
1012      pNANDC pRK28NC=  (pNANDC)RK2818_NANDC_BASE;
1013      if( mutex_trylock(&rknand_mutex))
1014         {
1015                 pRK28NC->FMCTL &=0xffffff00;   // release chip select
1016                 return 1;      // ready
1017         }
1018       else
1019                 return 0;     // busy
1020 }
1021
1022 void rk2818_nand_status_mutex_unlock(void)
1023 {
1024      mutex_unlock(&rknand_mutex);
1025      return;
1026 }
1027
1028 module_init(rk2818_nand_init);
1029 module_exit(rk2818_nand_exit);
1030
1031 MODULE_LICENSE("GPL");
1032 MODULE_AUTHOR("hxy <hxy@rock-chips.com>");
1033 MODULE_DESCRIPTION("MTD NAND driver for rk2818 device");
1034