2 * TXx9 NAND flash memory controller driver
3 * Based on RBTX49xx patch from CELF patch archive.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * (C) Copyright TOSHIBA CORPORATION 2004-2007
10 * All Rights Reserved.
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/nand_ecc.h>
20 #include <linux/mtd/partitions.h>
22 #include <asm/txx9/ndfmc.h>
24 /* TXX9 NDFMC Registers */
25 #define TXX9_NDFDTR 0x00
26 #define TXX9_NDFMCR 0x04
27 #define TXX9_NDFSR 0x08
28 #define TXX9_NDFISR 0x0c
29 #define TXX9_NDFIMR 0x10
30 #define TXX9_NDFSPR 0x14
31 #define TXX9_NDFRSTR 0x18 /* not TX4939 */
33 /* NDFMCR : NDFMC Mode Control */
34 #define TXX9_NDFMCR_WE 0x80
35 #define TXX9_NDFMCR_ECC_ALL 0x60
36 #define TXX9_NDFMCR_ECC_RESET 0x60
37 #define TXX9_NDFMCR_ECC_READ 0x40
38 #define TXX9_NDFMCR_ECC_ON 0x20
39 #define TXX9_NDFMCR_ECC_OFF 0x00
40 #define TXX9_NDFMCR_CE 0x10
41 #define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
42 #define TXX9_NDFMCR_ALE 0x02
43 #define TXX9_NDFMCR_CLE 0x01
45 #define TXX9_NDFMCR_X16 0x0400
46 #define TXX9_NDFMCR_DMAREQ_MASK 0x0300
47 #define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
48 #define TXX9_NDFMCR_DMAREQ_128 0x0100
49 #define TXX9_NDFMCR_DMAREQ_256 0x0200
50 #define TXX9_NDFMCR_DMAREQ_512 0x0300
51 #define TXX9_NDFMCR_CS_MASK 0x0c
52 #define TXX9_NDFMCR_CS(ch) ((ch) << 2)
54 /* NDFMCR : NDFMC Status */
55 #define TXX9_NDFSR_BUSY 0x80
57 #define TXX9_NDFSR_DMARUN 0x40
59 /* NDFMCR : NDFMC Reset */
60 #define TXX9_NDFRSTR_RST 0x01
62 struct txx9ndfmc_priv {
63 struct platform_device *dev;
64 struct nand_chip chip;
70 #define MAX_TXX9NDFMC_DEV 4
71 struct txx9ndfmc_drvdata {
72 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
74 unsigned char hold; /* in gbusclock */
75 unsigned char spw; /* in gbusclock */
76 struct nand_hw_control hw_control;
79 static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
81 struct nand_chip *chip = mtd->priv;
82 struct txx9ndfmc_priv *txx9_priv = chip->priv;
83 return txx9_priv->dev;
86 static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
88 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
89 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
91 return drvdata->base + (reg << plat->shift);
94 static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
96 return __raw_readl(ndregaddr(dev, reg));
99 static void txx9ndfmc_write(struct platform_device *dev,
100 u32 val, unsigned int reg)
102 __raw_writel(val, ndregaddr(dev, reg));
105 static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
107 struct platform_device *dev = mtd_to_platdev(mtd);
109 return txx9ndfmc_read(dev, TXX9_NDFDTR);
112 static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
115 struct platform_device *dev = mtd_to_platdev(mtd);
116 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
117 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
119 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
121 __raw_writel(*buf++, ndfdtr);
122 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
125 static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
127 struct platform_device *dev = mtd_to_platdev(mtd);
128 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
131 *buf++ = __raw_readl(ndfdtr);
134 static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
137 struct platform_device *dev = mtd_to_platdev(mtd);
138 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
141 if (*buf++ != (uint8_t)__raw_readl(ndfdtr))
146 static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
149 struct nand_chip *chip = mtd->priv;
150 struct txx9ndfmc_priv *txx9_priv = chip->priv;
151 struct platform_device *dev = txx9_priv->dev;
152 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
154 if (ctrl & NAND_CTRL_CHANGE) {
155 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
157 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
158 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
159 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
160 /* TXX9_NDFMCR_CE bit is 0:high 1:low */
161 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
162 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
163 mcr &= ~TXX9_NDFMCR_CS_MASK;
164 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
166 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
168 if (cmd != NAND_CMD_NONE)
169 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
170 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
171 /* dummy write to update external latch */
172 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
173 txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
178 static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
180 struct platform_device *dev = mtd_to_platdev(mtd);
182 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
185 static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
188 struct platform_device *dev = mtd_to_platdev(mtd);
189 struct nand_chip *chip = mtd->priv;
191 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
193 mcr &= ~TXX9_NDFMCR_ECC_ALL;
194 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
195 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
196 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
197 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
198 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
199 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
202 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
206 static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
207 unsigned char *read_ecc, unsigned char *calc_ecc)
209 struct nand_chip *chip = mtd->priv;
214 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
215 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
226 static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
228 struct platform_device *dev = mtd_to_platdev(mtd);
229 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
231 mcr &= ~TXX9_NDFMCR_ECC_ALL;
232 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
233 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
234 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
237 static void txx9ndfmc_initialize(struct platform_device *dev)
239 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
240 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
243 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
244 ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
248 txx9ndfmc_read(dev, TXX9_NDFRSTR) |
251 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
253 dev_err(&dev->dev, "reset failed.\n");
259 /* setup Hold Time, Strobe Pulse Width */
260 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
262 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
263 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
266 #define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
267 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
269 static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
271 struct nand_chip *chip = mtd->priv;
274 ret = nand_scan_ident(mtd, 1, NULL);
276 if (mtd->writesize >= 512) {
277 /* Hardware ECC 6 byte ECC per 512 Byte data */
278 chip->ecc.size = 512;
281 ret = nand_scan_tail(mtd);
286 static int __init txx9ndfmc_probe(struct platform_device *dev)
288 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
291 struct txx9ndfmc_drvdata *drvdata;
292 unsigned long gbusclk = plat->gbus_clock;
293 struct resource *res;
295 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
298 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
301 drvdata->base = devm_request_and_ioremap(&dev->dev, res);
305 hold = plat->hold ?: 20; /* tDH */
306 spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
308 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
309 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
310 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
311 hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
312 spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
313 hold = clamp(hold, 1, 15);
314 drvdata->hold = hold;
315 spw = clamp(spw, 1, 15);
317 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
318 (gbusclk + 500000) / 1000000, hold, spw);
320 spin_lock_init(&drvdata->hw_control.lock);
321 init_waitqueue_head(&drvdata->hw_control.wq);
323 platform_set_drvdata(dev, drvdata);
324 txx9ndfmc_initialize(dev);
326 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
327 struct txx9ndfmc_priv *txx9_priv;
328 struct nand_chip *chip;
329 struct mtd_info *mtd;
331 if (!(plat->ch_mask & (1 << i)))
333 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
336 dev_err(&dev->dev, "Unable to allocate "
337 "TXx9 NDFMC MTD device structure.\n");
340 chip = &txx9_priv->chip;
341 mtd = &txx9_priv->mtd;
342 mtd->owner = THIS_MODULE;
346 chip->read_byte = txx9ndfmc_read_byte;
347 chip->read_buf = txx9ndfmc_read_buf;
348 chip->write_buf = txx9ndfmc_write_buf;
349 chip->verify_buf = txx9ndfmc_verify_buf;
350 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
351 chip->dev_ready = txx9ndfmc_dev_ready;
352 chip->ecc.calculate = txx9ndfmc_calculate_ecc;
353 chip->ecc.correct = txx9ndfmc_correct_data;
354 chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
355 chip->ecc.mode = NAND_ECC_HW;
356 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
357 chip->ecc.size = 256;
359 chip->ecc.strength = 1;
360 chip->chip_delay = 100;
361 chip->controller = &drvdata->hw_control;
363 chip->priv = txx9_priv;
364 txx9_priv->dev = dev;
366 if (plat->ch_mask != 1) {
368 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
369 dev_name(&dev->dev), i);
372 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
375 if (!txx9_priv->mtdname) {
377 dev_err(&dev->dev, "Unable to allocate MTD name.\n");
380 if (plat->wide_mask & (1 << i))
381 chip->options |= NAND_BUSWIDTH_16;
383 if (txx9ndfmc_nand_scan(mtd)) {
384 kfree(txx9_priv->mtdname);
388 mtd->name = txx9_priv->mtdname;
390 mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
391 drvdata->mtds[i] = mtd;
397 static int __exit txx9ndfmc_remove(struct platform_device *dev)
399 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
402 platform_set_drvdata(dev, NULL);
405 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
406 struct mtd_info *mtd = drvdata->mtds[i];
407 struct nand_chip *chip;
408 struct txx9ndfmc_priv *txx9_priv;
413 txx9_priv = chip->priv;
416 kfree(txx9_priv->mtdname);
423 static int txx9ndfmc_resume(struct platform_device *dev)
425 if (platform_get_drvdata(dev))
426 txx9ndfmc_initialize(dev);
430 #define txx9ndfmc_resume NULL
433 static struct platform_driver txx9ndfmc_driver = {
434 .remove = __exit_p(txx9ndfmc_remove),
435 .resume = txx9ndfmc_resume,
438 .owner = THIS_MODULE,
442 static int __init txx9ndfmc_init(void)
444 return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
447 static void __exit txx9ndfmc_exit(void)
449 platform_driver_unregister(&txx9ndfmc_driver);
452 module_init(txx9ndfmc_init);
453 module_exit(txx9ndfmc_exit);
455 MODULE_LICENSE("GPL");
456 MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
457 MODULE_ALIAS("platform:txx9ndfmc");