2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2 / OMAP3
6 * Copyright © 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
39 #include <asm/mach/flash.h>
40 #include <plat/gpmc.h>
41 #include <plat/onenand.h>
42 #include <mach/gpio.h>
46 #include <plat/board.h>
48 #define DRIVER_NAME "omap2-onenand"
50 #define ONENAND_IO_SIZE SZ_128K
51 #define ONENAND_BUFRAM_SIZE (1024 * 5)
53 struct omap2_onenand {
54 struct platform_device *pdev;
56 unsigned long phys_base;
59 struct mtd_partition *parts;
60 struct onenand_chip onenand;
61 struct completion irq_done;
62 struct completion dma_done;
65 int (*setup)(void __iomem *base, int freq);
68 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
70 struct omap2_onenand *c = data;
72 complete(&c->dma_done);
75 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
77 struct omap2_onenand *c = dev_id;
79 complete(&c->irq_done);
84 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
86 return readw(c->onenand.base + reg);
89 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
92 writew(value, c->onenand.base + reg);
95 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
97 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
98 msg, state, ctrl, intr);
101 static void wait_warn(char *msg, int state, unsigned int ctrl,
104 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
105 "intr 0x%04x\n", msg, state, ctrl, intr);
108 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
110 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
111 unsigned int intr = 0;
113 unsigned long timeout;
116 if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
117 state == FL_VERIFYING_ERASE) {
119 unsigned int intr_flags = ONENAND_INT_MASTER;
123 intr_flags |= ONENAND_INT_RESET;
125 case FL_PREPARING_ERASE:
126 intr_flags |= ONENAND_INT_ERASE;
128 case FL_VERIFYING_ERASE:
135 intr = read_reg(c, ONENAND_REG_INTERRUPT);
136 if (intr & ONENAND_INT_MASTER)
139 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
140 if (ctrl & ONENAND_CTRL_ERROR) {
141 wait_err("controller error", state, ctrl, intr);
144 if ((intr & intr_flags) != intr_flags) {
145 wait_err("timeout", state, ctrl, intr);
151 if (state != FL_READING) {
154 /* Turn interrupts on */
155 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
156 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
157 syscfg |= ONENAND_SYS_CFG1_IOBE;
158 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
159 if (cpu_is_omap34xx())
160 /* Add a delay to let GPIO settle */
161 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
164 INIT_COMPLETION(c->irq_done);
166 result = gpio_get_value(c->gpio_irq);
168 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
169 intr = read_reg(c, ONENAND_REG_INTERRUPT);
170 wait_err("gpio error", state, ctrl, intr);
178 result = wait_for_completion_timeout(&c->irq_done,
179 msecs_to_jiffies(20));
181 /* Timeout after 20ms */
182 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
183 if (ctrl & ONENAND_CTRL_ONGO) {
185 * The operation seems to be still going
186 * so give it some more time.
192 ONENAND_REG_INTERRUPT);
193 wait_err("timeout", state, ctrl, intr);
196 intr = read_reg(c, ONENAND_REG_INTERRUPT);
197 if ((intr & ONENAND_INT_MASTER) == 0)
198 wait_warn("timeout", state, ctrl, intr);
204 /* Turn interrupts off */
205 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
206 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
207 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
209 timeout = jiffies + msecs_to_jiffies(20);
211 if (time_before(jiffies, timeout)) {
212 intr = read_reg(c, ONENAND_REG_INTERRUPT);
213 if (intr & ONENAND_INT_MASTER)
216 /* Timeout after 20ms */
217 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
218 if (ctrl & ONENAND_CTRL_ONGO) {
220 * The operation seems to be still going
221 * so give it some more time.
226 msecs_to_jiffies(20);
235 intr = read_reg(c, ONENAND_REG_INTERRUPT);
236 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
238 if (intr & ONENAND_INT_READ) {
239 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
242 unsigned int addr1, addr8;
244 addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
245 addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
246 if (ecc & ONENAND_ECC_2BIT_ALL) {
247 printk(KERN_ERR "onenand_wait: ECC error = "
248 "0x%04x, addr1 %#x, addr8 %#x\n",
250 mtd->ecc_stats.failed++;
252 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
253 printk(KERN_NOTICE "onenand_wait: correctable "
254 "ECC error = 0x%04x, addr1 %#x, "
255 "addr8 %#x\n", ecc, addr1, addr8);
256 mtd->ecc_stats.corrected++;
259 } else if (state == FL_READING) {
260 wait_err("timeout", state, ctrl, intr);
264 if (ctrl & ONENAND_CTRL_ERROR) {
265 wait_err("controller error", state, ctrl, intr);
266 if (ctrl & ONENAND_CTRL_LOCK)
267 printk(KERN_ERR "onenand_wait: "
268 "Device is write protected!!!\n");
273 wait_warn("unexpected controller status", state, ctrl, intr);
278 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
280 struct onenand_chip *this = mtd->priv;
282 if (ONENAND_CURRENT_BUFFERRAM(this)) {
283 if (area == ONENAND_DATARAM)
284 return this->writesize;
285 if (area == ONENAND_SPARERAM)
292 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
294 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
295 unsigned char *buffer, int offset,
298 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
299 struct onenand_chip *this = mtd->priv;
300 dma_addr_t dma_src, dma_dst;
302 unsigned long timeout;
303 void *buf = (void *)buffer;
305 volatile unsigned *done;
307 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
308 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
311 /* panic_write() may be in an interrupt context */
312 if (in_interrupt() || oops_in_progress)
315 if (buf >= high_memory) {
318 if (((size_t)buf & PAGE_MASK) !=
319 ((size_t)(buf + count - 1) & PAGE_MASK))
321 p1 = vmalloc_to_page(buf);
324 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
330 memcpy(buf + count, this->base + bram_offset + count, xtra);
333 dma_src = c->phys_base + bram_offset;
334 dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
335 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
336 dev_err(&c->pdev->dev,
337 "Couldn't DMA map a %d byte buffer\n",
342 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
343 count >> 2, 1, 0, 0, 0);
344 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
346 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
349 INIT_COMPLETION(c->dma_done);
350 omap_start_dma(c->dma_channel);
352 timeout = jiffies + msecs_to_jiffies(20);
353 done = &c->dma_done.done;
354 while (time_before(jiffies, timeout))
358 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
361 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
368 memcpy(buf, this->base + bram_offset, count);
372 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
373 const unsigned char *buffer,
374 int offset, size_t count)
376 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
377 struct onenand_chip *this = mtd->priv;
378 dma_addr_t dma_src, dma_dst;
380 unsigned long timeout;
381 void *buf = (void *)buffer;
382 volatile unsigned *done;
384 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
385 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
388 /* panic_write() may be in an interrupt context */
389 if (in_interrupt() || oops_in_progress)
392 if (buf >= high_memory) {
395 if (((size_t)buf & PAGE_MASK) !=
396 ((size_t)(buf + count - 1) & PAGE_MASK))
398 p1 = vmalloc_to_page(buf);
401 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
404 dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
405 dma_dst = c->phys_base + bram_offset;
406 if (dma_mapping_error(&c->pdev->dev, dma_src)) {
407 dev_err(&c->pdev->dev,
408 "Couldn't DMA map a %d byte buffer\n",
413 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
414 count >> 2, 1, 0, 0, 0);
415 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
417 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
420 INIT_COMPLETION(c->dma_done);
421 omap_start_dma(c->dma_channel);
423 timeout = jiffies + msecs_to_jiffies(20);
424 done = &c->dma_done.done;
425 while (time_before(jiffies, timeout))
429 dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
432 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
439 memcpy(this->base + bram_offset, buf, count);
445 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
446 unsigned char *buffer, int offset,
449 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
450 const unsigned char *buffer,
451 int offset, size_t count);
455 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
457 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
458 unsigned char *buffer, int offset,
461 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
462 struct onenand_chip *this = mtd->priv;
463 dma_addr_t dma_src, dma_dst;
466 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
467 /* DMA is not used. Revisit PM requirements before enabling it. */
468 if (1 || (c->dma_channel < 0) ||
469 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
470 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
471 memcpy(buffer, (__force void *)(this->base + bram_offset),
476 dma_src = c->phys_base + bram_offset;
477 dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
479 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
480 dev_err(&c->pdev->dev,
481 "Couldn't DMA map a %d byte buffer\n",
486 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
487 count / 4, 1, 0, 0, 0);
488 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
490 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
493 INIT_COMPLETION(c->dma_done);
494 omap_start_dma(c->dma_channel);
495 wait_for_completion(&c->dma_done);
497 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
502 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
503 const unsigned char *buffer,
504 int offset, size_t count)
506 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
507 struct onenand_chip *this = mtd->priv;
508 dma_addr_t dma_src, dma_dst;
511 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
512 /* DMA is not used. Revisit PM requirements before enabling it. */
513 if (1 || (c->dma_channel < 0) ||
514 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
515 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
516 memcpy((__force void *)(this->base + bram_offset), buffer,
521 dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
523 dma_dst = c->phys_base + bram_offset;
524 if (dma_mapping_error(&c->pdev->dev, dma_src)) {
525 dev_err(&c->pdev->dev,
526 "Couldn't DMA map a %d byte buffer\n",
531 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
532 count / 2, 1, 0, 0, 0);
533 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
535 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
538 INIT_COMPLETION(c->dma_done);
539 omap_start_dma(c->dma_channel);
540 wait_for_completion(&c->dma_done);
542 dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
549 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
550 unsigned char *buffer, int offset,
553 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
554 const unsigned char *buffer,
555 int offset, size_t count);
559 static struct platform_driver omap2_onenand_driver;
561 static int __adjust_timing(struct device *dev, void *data)
564 struct omap2_onenand *c;
566 c = dev_get_drvdata(dev);
568 BUG_ON(c->setup == NULL);
570 /* DMA is not in use so this is all that is needed */
571 /* Revisit for OMAP3! */
572 ret = c->setup(c->onenand.base, c->freq);
577 int omap2_onenand_rephase(void)
579 return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
580 NULL, __adjust_timing);
583 static void omap2_onenand_shutdown(struct platform_device *pdev)
585 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
587 /* With certain content in the buffer RAM, the OMAP boot ROM code
588 * can recognize the flash chip incorrectly. Zero it out before
591 memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
594 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
596 struct omap_onenand_platform_data *pdata;
597 struct omap2_onenand *c;
600 pdata = pdev->dev.platform_data;
602 dev_err(&pdev->dev, "platform data missing\n");
606 c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
610 init_completion(&c->irq_done);
611 init_completion(&c->dma_done);
612 c->gpmc_cs = pdata->cs;
613 c->gpio_irq = pdata->gpio_irq;
614 c->dma_channel = pdata->dma_channel;
615 if (c->dma_channel < 0) {
616 /* if -1, don't use DMA */
620 r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
622 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
626 if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
627 pdev->dev.driver->name) == NULL) {
628 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
629 "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
633 c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
634 if (c->onenand.base == NULL) {
636 goto err_release_mem_region;
639 if (pdata->onenand_setup != NULL) {
640 r = pdata->onenand_setup(c->onenand.base, c->freq);
642 dev_err(&pdev->dev, "Onenand platform setup failed: "
646 c->setup = pdata->onenand_setup;
650 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
651 dev_err(&pdev->dev, "Failed to request GPIO%d for "
652 "OneNAND\n", c->gpio_irq);
655 gpio_direction_input(c->gpio_irq);
657 if ((r = request_irq(gpio_to_irq(c->gpio_irq),
658 omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
659 pdev->dev.driver->name, c)) < 0)
660 goto err_release_gpio;
663 if (c->dma_channel >= 0) {
664 r = omap_request_dma(0, pdev->dev.driver->name,
665 omap2_onenand_dma_cb, (void *) c,
668 omap_set_dma_write_mode(c->dma_channel,
669 OMAP_DMA_WRITE_NON_POSTED);
670 omap_set_dma_src_data_pack(c->dma_channel, 1);
671 omap_set_dma_src_burst_mode(c->dma_channel,
672 OMAP_DMA_DATA_BURST_8);
673 omap_set_dma_dest_data_pack(c->dma_channel, 1);
674 omap_set_dma_dest_burst_mode(c->dma_channel,
675 OMAP_DMA_DATA_BURST_8);
678 "failed to allocate DMA for OneNAND, "
679 "using PIO instead\n");
684 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
685 "base %p\n", c->gpmc_cs, c->phys_base,
689 c->mtd.name = dev_name(&pdev->dev);
690 c->mtd.priv = &c->onenand;
691 c->mtd.owner = THIS_MODULE;
693 c->mtd.dev.parent = &pdev->dev;
695 if (c->dma_channel >= 0) {
696 struct onenand_chip *this = &c->onenand;
698 this->wait = omap2_onenand_wait;
699 if (cpu_is_omap34xx()) {
700 this->read_bufferram = omap3_onenand_read_bufferram;
701 this->write_bufferram = omap3_onenand_write_bufferram;
703 this->read_bufferram = omap2_onenand_read_bufferram;
704 this->write_bufferram = omap2_onenand_write_bufferram;
708 if ((r = onenand_scan(&c->mtd, 1)) < 0)
709 goto err_release_dma;
711 switch ((c->onenand.version_id >> 4) & 0xf) {
729 #ifdef CONFIG_MTD_PARTITIONS
730 if (pdata->parts != NULL)
731 r = add_mtd_partitions(&c->mtd, pdata->parts,
735 r = add_mtd_device(&c->mtd);
737 goto err_release_onenand;
739 platform_set_drvdata(pdev, c);
744 onenand_release(&c->mtd);
746 if (c->dma_channel != -1)
747 omap_free_dma(c->dma_channel);
749 free_irq(gpio_to_irq(c->gpio_irq), c);
752 gpio_free(c->gpio_irq);
754 iounmap(c->onenand.base);
755 err_release_mem_region:
756 release_mem_region(c->phys_base, ONENAND_IO_SIZE);
758 gpmc_cs_free(c->gpmc_cs);
765 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
767 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
771 #ifdef CONFIG_MTD_PARTITIONS
773 del_mtd_partitions(&c->mtd);
775 del_mtd_device(&c->mtd);
777 del_mtd_device(&c->mtd);
780 onenand_release(&c->mtd);
781 if (c->dma_channel != -1)
782 omap_free_dma(c->dma_channel);
783 omap2_onenand_shutdown(pdev);
784 platform_set_drvdata(pdev, NULL);
786 free_irq(gpio_to_irq(c->gpio_irq), c);
787 gpio_free(c->gpio_irq);
789 iounmap(c->onenand.base);
790 release_mem_region(c->phys_base, ONENAND_IO_SIZE);
791 gpmc_cs_free(c->gpmc_cs);
797 static struct platform_driver omap2_onenand_driver = {
798 .probe = omap2_onenand_probe,
799 .remove = __devexit_p(omap2_onenand_remove),
800 .shutdown = omap2_onenand_shutdown,
803 .owner = THIS_MODULE,
807 static int __init omap2_onenand_init(void)
809 printk(KERN_INFO "OneNAND driver initializing\n");
810 return platform_driver_register(&omap2_onenand_driver);
813 static void __exit omap2_onenand_exit(void)
815 platform_driver_unregister(&omap2_onenand_driver);
818 module_init(omap2_onenand_init);
819 module_exit(omap2_onenand_exit);
821 MODULE_ALIAS(DRIVER_NAME);
822 MODULE_LICENSE("GPL");
823 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
824 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");