2 * Freescale QuadSPI driver.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
31 #define QUADSPI_MCR 0x00
32 #define QUADSPI_MCR_RESERVED_SHIFT 16
33 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
34 #define QUADSPI_MCR_MDIS_SHIFT 14
35 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
36 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
37 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
38 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
39 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
40 #define QUADSPI_MCR_DDR_EN_SHIFT 7
41 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
42 #define QUADSPI_MCR_END_CFG_SHIFT 2
43 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
44 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
45 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
46 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
47 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
49 #define QUADSPI_IPCR 0x08
50 #define QUADSPI_IPCR_SEQID_SHIFT 24
51 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
53 #define QUADSPI_BUF0CR 0x10
54 #define QUADSPI_BUF1CR 0x14
55 #define QUADSPI_BUF2CR 0x18
56 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
58 #define QUADSPI_BUF3CR 0x1c
59 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
60 #define QUADSPI_BUF3CR_ALLMST (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
62 #define QUADSPI_BFGENCR 0x20
63 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
64 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
65 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
66 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
68 #define QUADSPI_BUF0IND 0x30
69 #define QUADSPI_BUF1IND 0x34
70 #define QUADSPI_BUF2IND 0x38
71 #define QUADSPI_SFAR 0x100
73 #define QUADSPI_SMPR 0x108
74 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
75 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
76 #define QUADSPI_SMPR_FSDLY_SHIFT 6
77 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
78 #define QUADSPI_SMPR_FSPHS_SHIFT 5
79 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
80 #define QUADSPI_SMPR_HSENA_SHIFT 0
81 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
83 #define QUADSPI_RBSR 0x10c
84 #define QUADSPI_RBSR_RDBFL_SHIFT 8
85 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
87 #define QUADSPI_RBCT 0x110
88 #define QUADSPI_RBCT_WMRK_MASK 0x1F
89 #define QUADSPI_RBCT_RXBRD_SHIFT 8
90 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
92 #define QUADSPI_TBSR 0x150
93 #define QUADSPI_TBDR 0x154
94 #define QUADSPI_SR 0x15c
95 #define QUADSPI_SR_IP_ACC_SHIFT 1
96 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
97 #define QUADSPI_SR_AHB_ACC_SHIFT 2
98 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
100 #define QUADSPI_FR 0x160
101 #define QUADSPI_FR_TFF_MASK 0x1
103 #define QUADSPI_SFA1AD 0x180
104 #define QUADSPI_SFA2AD 0x184
105 #define QUADSPI_SFB1AD 0x188
106 #define QUADSPI_SFB2AD 0x18c
107 #define QUADSPI_RBDR 0x200
109 #define QUADSPI_LUTKEY 0x300
110 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
112 #define QUADSPI_LCKCR 0x304
113 #define QUADSPI_LCKER_LOCK 0x1
114 #define QUADSPI_LCKER_UNLOCK 0x2
116 #define QUADSPI_RSER 0x164
117 #define QUADSPI_RSER_TFIE (0x1 << 0)
119 #define QUADSPI_LUT_BASE 0x310
122 * The definition of the LUT register shows below:
124 * ---------------------------------------------------
125 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
126 * ---------------------------------------------------
128 #define OPRND0_SHIFT 0
130 #define INSTR0_SHIFT 10
131 #define OPRND1_SHIFT 16
133 /* Instruction set for the LUT register. */
143 #define LUT_JMP_ON_CS 9
144 #define LUT_ADDR_DDR 10
145 #define LUT_MODE_DDR 11
146 #define LUT_MODE2_DDR 12
147 #define LUT_MODE4_DDR 13
148 #define LUT_READ_DDR 14
149 #define LUT_WRITE_DDR 15
150 #define LUT_DATA_LEARN 16
153 * The PAD definitions for LUT register.
155 * The pad stands for the lines number of IO[0:3].
156 * For example, the Quad read need four IO lines, so you should
157 * set LUT_PAD4 which means we use four IO lines.
163 /* Oprands for the LUT register. */
164 #define ADDR24BIT 0x18
165 #define ADDR32BIT 0x20
167 /* Macros for constructing the LUT register. */
168 #define LUT0(ins, pad, opr) \
169 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
170 ((LUT_##ins) << INSTR0_SHIFT))
172 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
174 /* other macros for LUT register. */
175 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
176 #define QUADSPI_LUT_NUM 64
178 /* SEQID -- we can have 16 seqids at most. */
179 #define SEQID_QUAD_READ 0
184 #define SEQID_CHIP_ERASE 5
189 #define SEQID_EN4B 10
190 #define SEQID_BRWR 11
192 enum fsl_qspi_devtype {
197 struct fsl_qspi_devtype_data {
198 enum fsl_qspi_devtype devtype;
203 static struct fsl_qspi_devtype_data vybrid_data = {
204 .devtype = FSL_QUADSPI_VYBRID,
209 static struct fsl_qspi_devtype_data imx6sx_data = {
210 .devtype = FSL_QUADSPI_IMX6SX,
215 #define FSL_QSPI_MAX_CHIP 4
217 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
218 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
219 void __iomem *iobase;
220 void __iomem *ahb_base; /* Used when read from AHB bus */
222 struct clk *clk, *clk_en;
225 struct fsl_qspi_devtype_data *devtype_data;
229 unsigned int chip_base_addr; /* We may support two chips. */
230 bool has_second_chip;
233 static inline int is_vybrid_qspi(struct fsl_qspi *q)
235 return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
238 static inline int is_imx6sx_qspi(struct fsl_qspi *q)
240 return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
244 * An IC bug makes us to re-arrange the 32-bit data.
245 * The following chips, such as IMX6SLX, have fixed this bug.
247 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
249 return is_vybrid_qspi(q) ? __swab32(a) : a;
252 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
254 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
255 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
258 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
260 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
261 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
264 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
266 struct fsl_qspi *q = dev_id;
269 /* clear interrupt */
270 reg = readl(q->iobase + QUADSPI_FR);
271 writel(reg, q->iobase + QUADSPI_FR);
273 if (reg & QUADSPI_FR_TFF_MASK)
276 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
280 static void fsl_qspi_init_lut(struct fsl_qspi *q)
282 void __iomem *base = q->iobase;
283 int rxfifo = q->devtype_data->rxfifo;
285 u8 cmd, addrlen, dummy;
288 fsl_qspi_unlock_lut(q);
290 /* Clear all the LUT table */
291 for (i = 0; i < QUADSPI_LUT_NUM; i++)
292 writel(0, base + QUADSPI_LUT_BASE + i * 4);
295 lut_base = SEQID_QUAD_READ * 4;
297 if (q->nor_size <= SZ_16M) {
298 cmd = SPINOR_OP_READ_1_1_4;
302 /* use the 4-byte address */
303 cmd = SPINOR_OP_READ_1_1_4;
308 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
309 base + QUADSPI_LUT(lut_base));
310 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
311 base + QUADSPI_LUT(lut_base + 1));
314 lut_base = SEQID_WREN * 4;
315 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
318 lut_base = SEQID_PP * 4;
320 if (q->nor_size <= SZ_16M) {
324 /* use the 4-byte address */
329 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
330 base + QUADSPI_LUT(lut_base));
331 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
334 lut_base = SEQID_RDSR * 4;
335 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
336 base + QUADSPI_LUT(lut_base));
339 lut_base = SEQID_SE * 4;
341 if (q->nor_size <= SZ_16M) {
345 /* use the 4-byte address */
350 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
351 base + QUADSPI_LUT(lut_base));
353 /* Erase the whole chip */
354 lut_base = SEQID_CHIP_ERASE * 4;
355 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
356 base + QUADSPI_LUT(lut_base));
359 lut_base = SEQID_RDID * 4;
360 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
361 base + QUADSPI_LUT(lut_base));
364 lut_base = SEQID_WRSR * 4;
365 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
366 base + QUADSPI_LUT(lut_base));
368 /* Read Configuration Register */
369 lut_base = SEQID_RDCR * 4;
370 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
371 base + QUADSPI_LUT(lut_base));
374 lut_base = SEQID_WRDI * 4;
375 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
377 /* Enter 4 Byte Mode (Micron) */
378 lut_base = SEQID_EN4B * 4;
379 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
381 /* Enter 4 Byte Mode (Spansion) */
382 lut_base = SEQID_BRWR * 4;
383 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
385 fsl_qspi_lock_lut(q);
388 /* Get the SEQID for the command */
389 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
392 case SPINOR_OP_READ_1_1_4:
393 return SEQID_QUAD_READ;
402 case SPINOR_OP_CHIP_ERASE:
403 return SEQID_CHIP_ERASE;
417 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
424 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
426 void __iomem *base = q->iobase;
431 init_completion(&q->c);
432 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
433 q->chip_base_addr, addr, len, cmd);
436 reg = readl(base + QUADSPI_MCR);
438 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
439 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
440 base + QUADSPI_RBCT);
441 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
444 reg2 = readl(base + QUADSPI_SR);
445 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
447 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
453 /* trigger the LUT now */
454 seqid = fsl_qspi_get_seqid(q, cmd);
455 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
457 /* Wait for the interrupt. */
458 err = wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000));
461 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
462 cmd, addr, readl(base + QUADSPI_FR),
463 readl(base + QUADSPI_SR));
469 /* restore the MCR */
470 writel(reg, base + QUADSPI_MCR);
475 /* Read out the data from the QUADSPI_RBDR buffer registers. */
476 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
482 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
483 tmp = fsl_qspi_endian_xchg(q, tmp);
484 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
485 q->chip_base_addr, tmp);
488 *((u32 *)rxbuf) = tmp;
491 memcpy(rxbuf, &tmp, len);
501 * If we have changed the content of the flash by writing or erasing,
502 * we need to invalidate the AHB buffer. If we do not do so, we may read out
503 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
504 * domain at the same time.
506 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
510 reg = readl(q->iobase + QUADSPI_MCR);
511 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
512 writel(reg, q->iobase + QUADSPI_MCR);
515 * The minimum delay : 1 AHB + 2 SFCK clocks.
516 * Delay 1 us is enough.
520 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
521 writel(reg, q->iobase + QUADSPI_MCR);
524 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
525 u8 opcode, unsigned int to, u32 *txbuf,
526 unsigned count, size_t *retlen)
531 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
532 q->chip_base_addr, to, count);
534 /* clear the TX FIFO. */
535 tmp = readl(q->iobase + QUADSPI_MCR);
536 writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
538 /* fill the TX data to the FIFO */
539 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
540 tmp = fsl_qspi_endian_xchg(q, *txbuf);
541 writel(tmp, q->iobase + QUADSPI_TBDR);
546 ret = fsl_qspi_runcmd(q, opcode, to, count);
548 if (ret == 0 && retlen)
554 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
556 int nor_size = q->nor_size;
557 void __iomem *base = q->iobase;
559 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
560 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
561 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
562 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
566 * There are two different ways to read out the data from the flash:
567 * the "IP Command Read" and the "AHB Command Read".
569 * The IC guy suggests we use the "AHB Command Read" which is faster
570 * then the "IP Command Read". (What's more is that there is a bug in
571 * the "IP Command Read" in the Vybrid.)
573 * After we set up the registers for the "AHB Command Read", we can use
574 * the memcpy to read the data directly. A "missed" access to the buffer
575 * causes the controller to clear the buffer, and use the sequence pointed
576 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
578 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
580 void __iomem *base = q->iobase;
583 /* AHB configuration for access buffer 0/1/2 .*/
584 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
585 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
586 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
587 writel(QUADSPI_BUF3CR_ALLMST, base + QUADSPI_BUF3CR);
589 /* We only use the buffer3 */
590 writel(0, base + QUADSPI_BUF0IND);
591 writel(0, base + QUADSPI_BUF1IND);
592 writel(0, base + QUADSPI_BUF2IND);
594 /* Set the default lut sequence for AHB Read. */
595 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
596 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
597 q->iobase + QUADSPI_BFGENCR);
600 /* We use this function to do some basic init for spi_nor_scan(). */
601 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
603 void __iomem *base = q->iobase;
607 /* the default frequency, we will change it in the future.*/
608 ret = clk_set_rate(q->clk, 66000000);
612 /* Init the LUT table. */
613 fsl_qspi_init_lut(q);
615 /* Disable the module */
616 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
619 reg = readl(base + QUADSPI_SMPR);
620 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
621 | QUADSPI_SMPR_FSPHS_MASK
622 | QUADSPI_SMPR_HSENA_MASK
623 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
625 /* Enable the module */
626 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
629 /* enable the interrupt */
630 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
635 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
637 unsigned long rate = q->clk_rate;
640 if (is_imx6sx_qspi(q))
643 ret = clk_set_rate(q->clk, rate);
647 /* Init the LUT table again. */
648 fsl_qspi_init_lut(q);
650 /* Init for AHB read */
651 fsl_qspi_init_abh_read(q);
656 static struct of_device_id fsl_qspi_dt_ids[] = {
657 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
658 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
661 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
663 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
665 q->chip_base_addr = q->nor_size * (nor - q->nor);
668 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
671 struct fsl_qspi *q = nor->priv;
673 ret = fsl_qspi_runcmd(q, opcode, 0, len);
677 fsl_qspi_read_data(q, len, buf);
681 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
684 struct fsl_qspi *q = nor->priv;
688 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
692 if (opcode == SPINOR_OP_CHIP_ERASE)
695 } else if (len > 0) {
696 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
697 (u32 *)buf, len, NULL);
699 dev_err(q->dev, "invalid cmd %d\n", opcode);
706 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
707 size_t len, size_t *retlen, const u_char *buf)
709 struct fsl_qspi *q = nor->priv;
711 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
712 (u32 *)buf, len, retlen);
714 /* invalid the data in the AHB buffer. */
718 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
719 size_t len, size_t *retlen, u_char *buf)
721 struct fsl_qspi *q = nor->priv;
722 u8 cmd = nor->read_opcode;
724 dev_dbg(q->dev, "cmd [%x],read from (0x%p, 0x%.8x, 0x%.8x),len:%d\n",
725 cmd, q->ahb_base, q->chip_base_addr, (unsigned int)from, len);
727 /* Read out the data directly from the AHB buffer.*/
728 memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
734 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
736 struct fsl_qspi *q = nor->priv;
739 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
740 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
742 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
750 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
752 struct fsl_qspi *q = nor->priv;
755 ret = clk_enable(q->clk_en);
759 ret = clk_enable(q->clk);
761 clk_disable(q->clk_en);
765 fsl_qspi_set_base_addr(q, nor);
769 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
771 struct fsl_qspi *q = nor->priv;
774 clk_disable(q->clk_en);
777 static int fsl_qspi_probe(struct platform_device *pdev)
779 struct device_node *np = pdev->dev.of_node;
780 struct mtd_part_parser_data ppdata;
781 struct device *dev = &pdev->dev;
783 struct resource *res;
785 struct mtd_info *mtd;
787 const struct of_device_id *of_id =
788 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
790 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
794 q->nor_num = of_get_child_count(dev->of_node);
795 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
798 /* find the resources */
799 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
800 q->iobase = devm_ioremap_resource(dev, res);
801 if (IS_ERR(q->iobase)) {
802 ret = PTR_ERR(q->iobase);
806 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
808 q->ahb_base = devm_ioremap_resource(dev, res);
809 if (IS_ERR(q->ahb_base)) {
810 ret = PTR_ERR(q->ahb_base);
813 q->memmap_phy = res->start;
815 /* find the clocks */
816 q->clk_en = devm_clk_get(dev, "qspi_en");
817 if (IS_ERR(q->clk_en)) {
818 ret = PTR_ERR(q->clk_en);
822 q->clk = devm_clk_get(dev, "qspi");
823 if (IS_ERR(q->clk)) {
824 ret = PTR_ERR(q->clk);
828 ret = clk_prepare_enable(q->clk_en);
830 dev_err(dev, "can not enable the qspi_en clock\n");
834 ret = clk_prepare_enable(q->clk);
836 dev_err(dev, "can not enable the qspi clock\n");
841 ret = platform_get_irq(pdev, 0);
843 dev_err(dev, "failed to get the irq\n");
847 ret = devm_request_irq(dev, ret,
848 fsl_qspi_irq_handler, 0, pdev->name, q);
850 dev_err(dev, "failed to request irq.\n");
855 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
856 platform_set_drvdata(pdev, q);
858 ret = fsl_qspi_nor_setup(q);
862 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
863 q->has_second_chip = true;
865 /* iterate the subnodes. */
866 for_each_available_child_of_node(dev->of_node, np) {
870 if (!q->has_second_chip)
882 nor->read_reg = fsl_qspi_read_reg;
883 nor->write_reg = fsl_qspi_write_reg;
884 nor->read = fsl_qspi_read;
885 nor->write = fsl_qspi_write;
886 nor->erase = fsl_qspi_erase;
888 nor->prepare = fsl_qspi_prep;
889 nor->unprepare = fsl_qspi_unprep;
891 ret = of_modalias_node(np, modalias, sizeof(modalias));
895 ret = of_property_read_u32(np, "spi-max-frequency",
900 /* set the chip address for READID */
901 fsl_qspi_set_base_addr(q, nor);
903 ret = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
908 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
912 /* Set the correct NOR size now. */
913 if (q->nor_size == 0) {
914 q->nor_size = mtd->size;
916 /* Map the SPI NOR to accessiable address */
917 fsl_qspi_set_map_addr(q);
921 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
922 * may writes 265 bytes per time. The write is working in the
923 * unit of the TX FIFO, not in the unit of the SPI NOR's page
926 * So shrink the spi_nor->page_size if it is larger then the
929 if (nor->page_size > q->devtype_data->txfifo)
930 nor->page_size = q->devtype_data->txfifo;
935 /* finish the rest init. */
936 ret = fsl_qspi_nor_setup_last(q);
938 goto last_init_failed;
941 clk_disable(q->clk_en);
945 for (i = 0; i < q->nor_num; i++) {
947 if (!q->has_second_chip)
949 mtd_device_unregister(&q->mtd[i]);
952 clk_disable_unprepare(q->clk);
954 clk_disable_unprepare(q->clk_en);
959 static int fsl_qspi_remove(struct platform_device *pdev)
961 struct fsl_qspi *q = platform_get_drvdata(pdev);
964 for (i = 0; i < q->nor_num; i++) {
966 if (!q->has_second_chip)
968 mtd_device_unregister(&q->mtd[i]);
971 /* disable the hardware */
972 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
973 writel(0x0, q->iobase + QUADSPI_RSER);
975 clk_unprepare(q->clk);
976 clk_unprepare(q->clk_en);
980 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
985 static int fsl_qspi_resume(struct platform_device *pdev)
987 struct fsl_qspi *q = platform_get_drvdata(pdev);
989 fsl_qspi_nor_setup(q);
990 fsl_qspi_set_map_addr(q);
991 fsl_qspi_nor_setup_last(q);
996 static struct platform_driver fsl_qspi_driver = {
998 .name = "fsl-quadspi",
999 .bus = &platform_bus_type,
1000 .of_match_table = fsl_qspi_dt_ids,
1002 .probe = fsl_qspi_probe,
1003 .remove = fsl_qspi_remove,
1004 .suspend = fsl_qspi_suspend,
1005 .resume = fsl_qspi_resume,
1007 module_platform_driver(fsl_qspi_driver);
1009 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1010 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1011 MODULE_LICENSE("GPL v2");