2 * Freescale QuadSPI driver.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
32 #define QUADSPI_MCR 0x00
33 #define QUADSPI_MCR_RESERVED_SHIFT 16
34 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
35 #define QUADSPI_MCR_MDIS_SHIFT 14
36 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
37 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
38 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
39 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
40 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
41 #define QUADSPI_MCR_DDR_EN_SHIFT 7
42 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
43 #define QUADSPI_MCR_END_CFG_SHIFT 2
44 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
45 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
46 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
47 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
48 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
50 #define QUADSPI_IPCR 0x08
51 #define QUADSPI_IPCR_SEQID_SHIFT 24
52 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
54 #define QUADSPI_BUF0CR 0x10
55 #define QUADSPI_BUF1CR 0x14
56 #define QUADSPI_BUF2CR 0x18
57 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
59 #define QUADSPI_BUF3CR 0x1c
60 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
61 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
62 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
63 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
65 #define QUADSPI_BFGENCR 0x20
66 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
67 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
68 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
69 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
71 #define QUADSPI_BUF0IND 0x30
72 #define QUADSPI_BUF1IND 0x34
73 #define QUADSPI_BUF2IND 0x38
74 #define QUADSPI_SFAR 0x100
76 #define QUADSPI_SMPR 0x108
77 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
78 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
79 #define QUADSPI_SMPR_FSDLY_SHIFT 6
80 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
81 #define QUADSPI_SMPR_FSPHS_SHIFT 5
82 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
83 #define QUADSPI_SMPR_HSENA_SHIFT 0
84 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
86 #define QUADSPI_RBSR 0x10c
87 #define QUADSPI_RBSR_RDBFL_SHIFT 8
88 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
90 #define QUADSPI_RBCT 0x110
91 #define QUADSPI_RBCT_WMRK_MASK 0x1F
92 #define QUADSPI_RBCT_RXBRD_SHIFT 8
93 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
95 #define QUADSPI_TBSR 0x150
96 #define QUADSPI_TBDR 0x154
97 #define QUADSPI_SR 0x15c
98 #define QUADSPI_SR_IP_ACC_SHIFT 1
99 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
100 #define QUADSPI_SR_AHB_ACC_SHIFT 2
101 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
103 #define QUADSPI_FR 0x160
104 #define QUADSPI_FR_TFF_MASK 0x1
106 #define QUADSPI_SFA1AD 0x180
107 #define QUADSPI_SFA2AD 0x184
108 #define QUADSPI_SFB1AD 0x188
109 #define QUADSPI_SFB2AD 0x18c
110 #define QUADSPI_RBDR 0x200
112 #define QUADSPI_LUTKEY 0x300
113 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
115 #define QUADSPI_LCKCR 0x304
116 #define QUADSPI_LCKER_LOCK 0x1
117 #define QUADSPI_LCKER_UNLOCK 0x2
119 #define QUADSPI_RSER 0x164
120 #define QUADSPI_RSER_TFIE (0x1 << 0)
122 #define QUADSPI_LUT_BASE 0x310
125 * The definition of the LUT register shows below:
127 * ---------------------------------------------------
128 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
129 * ---------------------------------------------------
131 #define OPRND0_SHIFT 0
133 #define INSTR0_SHIFT 10
134 #define OPRND1_SHIFT 16
136 /* Instruction set for the LUT register. */
146 #define LUT_JMP_ON_CS 9
147 #define LUT_ADDR_DDR 10
148 #define LUT_MODE_DDR 11
149 #define LUT_MODE2_DDR 12
150 #define LUT_MODE4_DDR 13
151 #define LUT_READ_DDR 14
152 #define LUT_WRITE_DDR 15
153 #define LUT_DATA_LEARN 16
156 * The PAD definitions for LUT register.
158 * The pad stands for the lines number of IO[0:3].
159 * For example, the Quad read need four IO lines, so you should
160 * set LUT_PAD4 which means we use four IO lines.
166 /* Oprands for the LUT register. */
167 #define ADDR24BIT 0x18
168 #define ADDR32BIT 0x20
170 /* Macros for constructing the LUT register. */
171 #define LUT0(ins, pad, opr) \
172 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
173 ((LUT_##ins) << INSTR0_SHIFT))
175 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
177 /* other macros for LUT register. */
178 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
179 #define QUADSPI_LUT_NUM 64
181 /* SEQID -- we can have 16 seqids at most. */
182 #define SEQID_QUAD_READ 0
187 #define SEQID_CHIP_ERASE 5
192 #define SEQID_EN4B 10
193 #define SEQID_BRWR 11
195 enum fsl_qspi_devtype {
200 struct fsl_qspi_devtype_data {
201 enum fsl_qspi_devtype devtype;
207 static struct fsl_qspi_devtype_data vybrid_data = {
208 .devtype = FSL_QUADSPI_VYBRID,
214 static struct fsl_qspi_devtype_data imx6sx_data = {
215 .devtype = FSL_QUADSPI_IMX6SX,
221 #define FSL_QSPI_MAX_CHIP 4
223 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
224 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
225 void __iomem *iobase;
226 void __iomem *ahb_base; /* Used when read from AHB bus */
228 struct clk *clk, *clk_en;
231 struct fsl_qspi_devtype_data *devtype_data;
235 unsigned int chip_base_addr; /* We may support two chips. */
236 bool has_second_chip;
240 static inline int is_vybrid_qspi(struct fsl_qspi *q)
242 return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
245 static inline int is_imx6sx_qspi(struct fsl_qspi *q)
247 return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
251 * An IC bug makes us to re-arrange the 32-bit data.
252 * The following chips, such as IMX6SLX, have fixed this bug.
254 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
256 return is_vybrid_qspi(q) ? __swab32(a) : a;
259 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
261 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
262 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
265 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
267 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
268 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
271 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
273 struct fsl_qspi *q = dev_id;
276 /* clear interrupt */
277 reg = readl(q->iobase + QUADSPI_FR);
278 writel(reg, q->iobase + QUADSPI_FR);
280 if (reg & QUADSPI_FR_TFF_MASK)
283 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
287 static void fsl_qspi_init_lut(struct fsl_qspi *q)
289 void __iomem *base = q->iobase;
290 int rxfifo = q->devtype_data->rxfifo;
292 u8 cmd, addrlen, dummy;
295 fsl_qspi_unlock_lut(q);
297 /* Clear all the LUT table */
298 for (i = 0; i < QUADSPI_LUT_NUM; i++)
299 writel(0, base + QUADSPI_LUT_BASE + i * 4);
302 lut_base = SEQID_QUAD_READ * 4;
304 if (q->nor_size <= SZ_16M) {
305 cmd = SPINOR_OP_READ_1_1_4;
309 /* use the 4-byte address */
310 cmd = SPINOR_OP_READ_1_1_4;
315 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
316 base + QUADSPI_LUT(lut_base));
317 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
318 base + QUADSPI_LUT(lut_base + 1));
321 lut_base = SEQID_WREN * 4;
322 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
325 lut_base = SEQID_PP * 4;
327 if (q->nor_size <= SZ_16M) {
331 /* use the 4-byte address */
336 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
337 base + QUADSPI_LUT(lut_base));
338 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
341 lut_base = SEQID_RDSR * 4;
342 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
343 base + QUADSPI_LUT(lut_base));
346 lut_base = SEQID_SE * 4;
348 if (q->nor_size <= SZ_16M) {
352 /* use the 4-byte address */
357 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
358 base + QUADSPI_LUT(lut_base));
360 /* Erase the whole chip */
361 lut_base = SEQID_CHIP_ERASE * 4;
362 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
363 base + QUADSPI_LUT(lut_base));
366 lut_base = SEQID_RDID * 4;
367 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
368 base + QUADSPI_LUT(lut_base));
371 lut_base = SEQID_WRSR * 4;
372 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
373 base + QUADSPI_LUT(lut_base));
375 /* Read Configuration Register */
376 lut_base = SEQID_RDCR * 4;
377 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
378 base + QUADSPI_LUT(lut_base));
381 lut_base = SEQID_WRDI * 4;
382 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
384 /* Enter 4 Byte Mode (Micron) */
385 lut_base = SEQID_EN4B * 4;
386 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
388 /* Enter 4 Byte Mode (Spansion) */
389 lut_base = SEQID_BRWR * 4;
390 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
392 fsl_qspi_lock_lut(q);
395 /* Get the SEQID for the command */
396 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
399 case SPINOR_OP_READ_1_1_4:
400 return SEQID_QUAD_READ;
409 case SPINOR_OP_CHIP_ERASE:
410 return SEQID_CHIP_ERASE;
424 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
431 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
433 void __iomem *base = q->iobase;
438 init_completion(&q->c);
439 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
440 q->chip_base_addr, addr, len, cmd);
443 reg = readl(base + QUADSPI_MCR);
445 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
446 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
447 base + QUADSPI_RBCT);
448 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
451 reg2 = readl(base + QUADSPI_SR);
452 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
454 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
460 /* trigger the LUT now */
461 seqid = fsl_qspi_get_seqid(q, cmd);
462 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
464 /* Wait for the interrupt. */
465 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
467 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
468 cmd, addr, readl(base + QUADSPI_FR),
469 readl(base + QUADSPI_SR));
475 /* restore the MCR */
476 writel(reg, base + QUADSPI_MCR);
481 /* Read out the data from the QUADSPI_RBDR buffer registers. */
482 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
488 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
489 tmp = fsl_qspi_endian_xchg(q, tmp);
490 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
491 q->chip_base_addr, tmp);
494 *((u32 *)rxbuf) = tmp;
497 memcpy(rxbuf, &tmp, len);
507 * If we have changed the content of the flash by writing or erasing,
508 * we need to invalidate the AHB buffer. If we do not do so, we may read out
509 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
510 * domain at the same time.
512 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
516 reg = readl(q->iobase + QUADSPI_MCR);
517 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
518 writel(reg, q->iobase + QUADSPI_MCR);
521 * The minimum delay : 1 AHB + 2 SFCK clocks.
522 * Delay 1 us is enough.
526 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
527 writel(reg, q->iobase + QUADSPI_MCR);
530 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
531 u8 opcode, unsigned int to, u32 *txbuf,
532 unsigned count, size_t *retlen)
537 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
538 q->chip_base_addr, to, count);
540 /* clear the TX FIFO. */
541 tmp = readl(q->iobase + QUADSPI_MCR);
542 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
544 /* fill the TX data to the FIFO */
545 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
546 tmp = fsl_qspi_endian_xchg(q, *txbuf);
547 writel(tmp, q->iobase + QUADSPI_TBDR);
552 ret = fsl_qspi_runcmd(q, opcode, to, count);
554 if (ret == 0 && retlen)
560 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
562 int nor_size = q->nor_size;
563 void __iomem *base = q->iobase;
565 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
566 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
567 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
568 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
572 * There are two different ways to read out the data from the flash:
573 * the "IP Command Read" and the "AHB Command Read".
575 * The IC guy suggests we use the "AHB Command Read" which is faster
576 * then the "IP Command Read". (What's more is that there is a bug in
577 * the "IP Command Read" in the Vybrid.)
579 * After we set up the registers for the "AHB Command Read", we can use
580 * the memcpy to read the data directly. A "missed" access to the buffer
581 * causes the controller to clear the buffer, and use the sequence pointed
582 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
584 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
586 void __iomem *base = q->iobase;
589 /* AHB configuration for access buffer 0/1/2 .*/
590 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
591 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
592 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
594 * Set ADATSZ with the maximum AHB buffer size to improve the
597 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
598 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
600 /* We only use the buffer3 */
601 writel(0, base + QUADSPI_BUF0IND);
602 writel(0, base + QUADSPI_BUF1IND);
603 writel(0, base + QUADSPI_BUF2IND);
605 /* Set the default lut sequence for AHB Read. */
606 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
607 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
608 q->iobase + QUADSPI_BFGENCR);
611 /* We use this function to do some basic init for spi_nor_scan(). */
612 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
614 void __iomem *base = q->iobase;
618 /* the default frequency, we will change it in the future.*/
619 ret = clk_set_rate(q->clk, 66000000);
623 /* Init the LUT table. */
624 fsl_qspi_init_lut(q);
626 /* Disable the module */
627 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
630 reg = readl(base + QUADSPI_SMPR);
631 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
632 | QUADSPI_SMPR_FSPHS_MASK
633 | QUADSPI_SMPR_HSENA_MASK
634 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
636 /* Enable the module */
637 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
640 /* enable the interrupt */
641 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
646 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
648 unsigned long rate = q->clk_rate;
651 if (is_imx6sx_qspi(q))
654 ret = clk_set_rate(q->clk, rate);
658 /* Init the LUT table again. */
659 fsl_qspi_init_lut(q);
661 /* Init for AHB read */
662 fsl_qspi_init_abh_read(q);
667 static const struct of_device_id fsl_qspi_dt_ids[] = {
668 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
669 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
672 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
674 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
676 q->chip_base_addr = q->nor_size * (nor - q->nor);
679 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
682 struct fsl_qspi *q = nor->priv;
684 ret = fsl_qspi_runcmd(q, opcode, 0, len);
688 fsl_qspi_read_data(q, len, buf);
692 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
695 struct fsl_qspi *q = nor->priv;
699 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
703 if (opcode == SPINOR_OP_CHIP_ERASE)
706 } else if (len > 0) {
707 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
708 (u32 *)buf, len, NULL);
710 dev_err(q->dev, "invalid cmd %d\n", opcode);
717 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
718 size_t len, size_t *retlen, const u_char *buf)
720 struct fsl_qspi *q = nor->priv;
722 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
723 (u32 *)buf, len, retlen);
725 /* invalid the data in the AHB buffer. */
729 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
730 size_t len, size_t *retlen, u_char *buf)
732 struct fsl_qspi *q = nor->priv;
733 u8 cmd = nor->read_opcode;
735 dev_dbg(q->dev, "cmd [%x],read from (0x%p, 0x%.8x, 0x%.8x),len:%d\n",
736 cmd, q->ahb_base, q->chip_base_addr, (unsigned int)from, len);
738 /* Read out the data directly from the AHB buffer.*/
739 memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
745 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
747 struct fsl_qspi *q = nor->priv;
750 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
751 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
753 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
761 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
763 struct fsl_qspi *q = nor->priv;
766 mutex_lock(&q->lock);
767 ret = clk_enable(q->clk_en);
771 ret = clk_enable(q->clk);
775 fsl_qspi_set_base_addr(q, nor);
779 clk_disable(q->clk_en);
781 mutex_unlock(&q->lock);
786 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
788 struct fsl_qspi *q = nor->priv;
791 clk_disable(q->clk_en);
792 mutex_unlock(&q->lock);
795 static int fsl_qspi_probe(struct platform_device *pdev)
797 struct device_node *np = pdev->dev.of_node;
798 struct mtd_part_parser_data ppdata;
799 struct device *dev = &pdev->dev;
801 struct resource *res;
803 struct mtd_info *mtd;
805 const struct of_device_id *of_id =
806 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
808 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
812 q->nor_num = of_get_child_count(dev->of_node);
813 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
816 /* find the resources */
817 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
818 q->iobase = devm_ioremap_resource(dev, res);
819 if (IS_ERR(q->iobase))
820 return PTR_ERR(q->iobase);
822 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
824 q->ahb_base = devm_ioremap_resource(dev, res);
825 if (IS_ERR(q->ahb_base))
826 return PTR_ERR(q->ahb_base);
828 q->memmap_phy = res->start;
830 /* find the clocks */
831 q->clk_en = devm_clk_get(dev, "qspi_en");
832 if (IS_ERR(q->clk_en))
833 return PTR_ERR(q->clk_en);
835 q->clk = devm_clk_get(dev, "qspi");
837 return PTR_ERR(q->clk);
839 ret = clk_prepare_enable(q->clk_en);
841 dev_err(dev, "cannot enable the qspi_en clock: %d\n", ret);
845 ret = clk_prepare_enable(q->clk);
847 dev_err(dev, "cannot enable the qspi clock: %d\n", ret);
852 ret = platform_get_irq(pdev, 0);
854 dev_err(dev, "failed to get the irq: %d\n", ret);
858 ret = devm_request_irq(dev, ret,
859 fsl_qspi_irq_handler, 0, pdev->name, q);
861 dev_err(dev, "failed to request irq: %d\n", ret);
866 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
867 platform_set_drvdata(pdev, q);
869 ret = fsl_qspi_nor_setup(q);
873 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
874 q->has_second_chip = true;
876 mutex_init(&q->lock);
878 /* iterate the subnodes. */
879 for_each_available_child_of_node(dev->of_node, np) {
883 if (!q->has_second_chip)
895 nor->read_reg = fsl_qspi_read_reg;
896 nor->write_reg = fsl_qspi_write_reg;
897 nor->read = fsl_qspi_read;
898 nor->write = fsl_qspi_write;
899 nor->erase = fsl_qspi_erase;
901 nor->prepare = fsl_qspi_prep;
902 nor->unprepare = fsl_qspi_unprep;
904 ret = of_modalias_node(np, modalias, sizeof(modalias));
908 ret = of_property_read_u32(np, "spi-max-frequency",
913 /* set the chip address for READID */
914 fsl_qspi_set_base_addr(q, nor);
916 ret = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
921 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
925 /* Set the correct NOR size now. */
926 if (q->nor_size == 0) {
927 q->nor_size = mtd->size;
929 /* Map the SPI NOR to accessiable address */
930 fsl_qspi_set_map_addr(q);
934 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
935 * may writes 265 bytes per time. The write is working in the
936 * unit of the TX FIFO, not in the unit of the SPI NOR's page
939 * So shrink the spi_nor->page_size if it is larger then the
942 if (nor->page_size > q->devtype_data->txfifo)
943 nor->page_size = q->devtype_data->txfifo;
948 /* finish the rest init. */
949 ret = fsl_qspi_nor_setup_last(q);
951 goto last_init_failed;
954 clk_disable(q->clk_en);
958 for (i = 0; i < q->nor_num; i++) {
960 if (!q->has_second_chip)
962 mtd_device_unregister(&q->mtd[i]);
965 mutex_destroy(&q->lock);
967 clk_disable_unprepare(q->clk);
969 clk_disable_unprepare(q->clk_en);
973 static int fsl_qspi_remove(struct platform_device *pdev)
975 struct fsl_qspi *q = platform_get_drvdata(pdev);
978 for (i = 0; i < q->nor_num; i++) {
980 if (!q->has_second_chip)
982 mtd_device_unregister(&q->mtd[i]);
985 /* disable the hardware */
986 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
987 writel(0x0, q->iobase + QUADSPI_RSER);
989 mutex_destroy(&q->lock);
990 clk_unprepare(q->clk);
991 clk_unprepare(q->clk_en);
995 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1000 static int fsl_qspi_resume(struct platform_device *pdev)
1002 struct fsl_qspi *q = platform_get_drvdata(pdev);
1004 fsl_qspi_nor_setup(q);
1005 fsl_qspi_set_map_addr(q);
1006 fsl_qspi_nor_setup_last(q);
1011 static struct platform_driver fsl_qspi_driver = {
1013 .name = "fsl-quadspi",
1014 .bus = &platform_bus_type,
1015 .of_match_table = fsl_qspi_dt_ids,
1017 .probe = fsl_qspi_probe,
1018 .remove = fsl_qspi_remove,
1019 .suspend = fsl_qspi_suspend,
1020 .resume = fsl_qspi_resume,
1022 module_platform_driver(fsl_qspi_driver);
1024 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1025 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1026 MODULE_LICENSE("GPL v2");