2 * Freescale QuadSPI driver.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
30 #include <linux/pm_qos.h>
32 /* Controller needs driver to swap endian */
33 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
34 /* Controller needs 4x internal clock */
35 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
37 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
38 * trigger data transfer even though extern data will not transferred.
40 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
41 /* Controller cannot wake up from wait mode, TKT245618 */
42 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
45 #define QUADSPI_MCR 0x00
46 #define QUADSPI_MCR_RESERVED_SHIFT 16
47 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
48 #define QUADSPI_MCR_MDIS_SHIFT 14
49 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
50 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
51 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
52 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
53 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
54 #define QUADSPI_MCR_DDR_EN_SHIFT 7
55 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
56 #define QUADSPI_MCR_END_CFG_SHIFT 2
57 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
58 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
59 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
60 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
61 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
63 #define QUADSPI_IPCR 0x08
64 #define QUADSPI_IPCR_SEQID_SHIFT 24
65 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
67 #define QUADSPI_BUF0CR 0x10
68 #define QUADSPI_BUF1CR 0x14
69 #define QUADSPI_BUF2CR 0x18
70 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
72 #define QUADSPI_BUF3CR 0x1c
73 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
74 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
75 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
76 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
78 #define QUADSPI_BFGENCR 0x20
79 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
80 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
81 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
82 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
84 #define QUADSPI_BUF0IND 0x30
85 #define QUADSPI_BUF1IND 0x34
86 #define QUADSPI_BUF2IND 0x38
87 #define QUADSPI_SFAR 0x100
89 #define QUADSPI_SMPR 0x108
90 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
91 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
92 #define QUADSPI_SMPR_FSDLY_SHIFT 6
93 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
94 #define QUADSPI_SMPR_FSPHS_SHIFT 5
95 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
96 #define QUADSPI_SMPR_HSENA_SHIFT 0
97 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
99 #define QUADSPI_RBSR 0x10c
100 #define QUADSPI_RBSR_RDBFL_SHIFT 8
101 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
103 #define QUADSPI_RBCT 0x110
104 #define QUADSPI_RBCT_WMRK_MASK 0x1F
105 #define QUADSPI_RBCT_RXBRD_SHIFT 8
106 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
108 #define QUADSPI_TBSR 0x150
109 #define QUADSPI_TBDR 0x154
110 #define QUADSPI_SR 0x15c
111 #define QUADSPI_SR_IP_ACC_SHIFT 1
112 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
113 #define QUADSPI_SR_AHB_ACC_SHIFT 2
114 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
116 #define QUADSPI_FR 0x160
117 #define QUADSPI_FR_TFF_MASK 0x1
119 #define QUADSPI_SFA1AD 0x180
120 #define QUADSPI_SFA2AD 0x184
121 #define QUADSPI_SFB1AD 0x188
122 #define QUADSPI_SFB2AD 0x18c
123 #define QUADSPI_RBDR 0x200
125 #define QUADSPI_LUTKEY 0x300
126 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
128 #define QUADSPI_LCKCR 0x304
129 #define QUADSPI_LCKER_LOCK 0x1
130 #define QUADSPI_LCKER_UNLOCK 0x2
132 #define QUADSPI_RSER 0x164
133 #define QUADSPI_RSER_TFIE (0x1 << 0)
135 #define QUADSPI_LUT_BASE 0x310
138 * The definition of the LUT register shows below:
140 * ---------------------------------------------------
141 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
142 * ---------------------------------------------------
144 #define OPRND0_SHIFT 0
146 #define INSTR0_SHIFT 10
147 #define OPRND1_SHIFT 16
149 /* Instruction set for the LUT register. */
159 #define LUT_JMP_ON_CS 9
160 #define LUT_ADDR_DDR 10
161 #define LUT_MODE_DDR 11
162 #define LUT_MODE2_DDR 12
163 #define LUT_MODE4_DDR 13
164 #define LUT_READ_DDR 14
165 #define LUT_WRITE_DDR 15
166 #define LUT_DATA_LEARN 16
169 * The PAD definitions for LUT register.
171 * The pad stands for the lines number of IO[0:3].
172 * For example, the Quad read need four IO lines, so you should
173 * set LUT_PAD4 which means we use four IO lines.
179 /* Oprands for the LUT register. */
180 #define ADDR24BIT 0x18
181 #define ADDR32BIT 0x20
183 /* Macros for constructing the LUT register. */
184 #define LUT0(ins, pad, opr) \
185 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
186 ((LUT_##ins) << INSTR0_SHIFT))
188 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
190 /* other macros for LUT register. */
191 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
192 #define QUADSPI_LUT_NUM 64
194 /* SEQID -- we can have 16 seqids at most. */
195 #define SEQID_QUAD_READ 0
200 #define SEQID_CHIP_ERASE 5
205 #define SEQID_EN4B 10
206 #define SEQID_BRWR 11
208 #define QUADSPI_MIN_IOMAP SZ_4M
210 enum fsl_qspi_devtype {
217 struct fsl_qspi_devtype_data {
218 enum fsl_qspi_devtype devtype;
225 static struct fsl_qspi_devtype_data vybrid_data = {
226 .devtype = FSL_QUADSPI_VYBRID,
229 .ahb_buf_size = 1024,
230 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
233 static struct fsl_qspi_devtype_data imx6sx_data = {
234 .devtype = FSL_QUADSPI_IMX6SX,
237 .ahb_buf_size = 1024,
238 .driver_data = QUADSPI_QUIRK_4X_INT_CLK
239 | QUADSPI_QUIRK_TKT245618,
242 static struct fsl_qspi_devtype_data imx7d_data = {
243 .devtype = FSL_QUADSPI_IMX7D,
246 .ahb_buf_size = 1024,
247 .driver_data = QUADSPI_QUIRK_TKT253890
248 | QUADSPI_QUIRK_4X_INT_CLK,
251 static struct fsl_qspi_devtype_data imx6ul_data = {
252 .devtype = FSL_QUADSPI_IMX6UL,
255 .ahb_buf_size = 1024,
256 .driver_data = QUADSPI_QUIRK_TKT253890
257 | QUADSPI_QUIRK_4X_INT_CLK,
260 #define FSL_QSPI_MAX_CHIP 4
262 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
263 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
264 void __iomem *iobase;
265 void __iomem *ahb_addr;
269 struct clk *clk, *clk_en;
272 struct fsl_qspi_devtype_data *devtype_data;
276 unsigned int chip_base_addr; /* We may support two chips. */
277 bool has_second_chip;
279 struct pm_qos_request pm_qos_req;
282 static inline int needs_swap_endian(struct fsl_qspi *q)
284 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
287 static inline int needs_4x_clock(struct fsl_qspi *q)
289 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
292 static inline int needs_fill_txfifo(struct fsl_qspi *q)
294 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
297 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
299 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
303 * An IC bug makes us to re-arrange the 32-bit data.
304 * The following chips, such as IMX6SLX, have fixed this bug.
306 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
308 return needs_swap_endian(q) ? __swab32(a) : a;
311 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
317 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
323 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
325 struct fsl_qspi *q = dev_id;
328 /* clear interrupt */
329 reg = readl(q->iobase + QUADSPI_FR);
330 writel(reg, q->iobase + QUADSPI_FR);
332 if (reg & QUADSPI_FR_TFF_MASK)
335 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
339 static void fsl_qspi_init_lut(struct fsl_qspi *q)
341 void __iomem *base = q->iobase;
342 int rxfifo = q->devtype_data->rxfifo;
344 u8 cmd, addrlen, dummy;
347 fsl_qspi_unlock_lut(q);
349 /* Clear all the LUT table */
350 for (i = 0; i < QUADSPI_LUT_NUM; i++)
351 writel(0, base + QUADSPI_LUT_BASE + i * 4);
354 lut_base = SEQID_QUAD_READ * 4;
356 if (q->nor_size <= SZ_16M) {
357 cmd = SPINOR_OP_READ_1_1_4;
361 /* use the 4-byte address */
362 cmd = SPINOR_OP_READ_1_1_4;
367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
368 base + QUADSPI_LUT(lut_base));
369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
370 base + QUADSPI_LUT(lut_base + 1));
373 lut_base = SEQID_WREN * 4;
374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
377 lut_base = SEQID_PP * 4;
379 if (q->nor_size <= SZ_16M) {
383 /* use the 4-byte address */
388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
389 base + QUADSPI_LUT(lut_base));
390 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
393 lut_base = SEQID_RDSR * 4;
394 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
395 base + QUADSPI_LUT(lut_base));
398 lut_base = SEQID_SE * 4;
400 if (q->nor_size <= SZ_16M) {
404 /* use the 4-byte address */
409 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
410 base + QUADSPI_LUT(lut_base));
412 /* Erase the whole chip */
413 lut_base = SEQID_CHIP_ERASE * 4;
414 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
415 base + QUADSPI_LUT(lut_base));
418 lut_base = SEQID_RDID * 4;
419 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
420 base + QUADSPI_LUT(lut_base));
423 lut_base = SEQID_WRSR * 4;
424 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
425 base + QUADSPI_LUT(lut_base));
427 /* Read Configuration Register */
428 lut_base = SEQID_RDCR * 4;
429 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
430 base + QUADSPI_LUT(lut_base));
433 lut_base = SEQID_WRDI * 4;
434 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
436 /* Enter 4 Byte Mode (Micron) */
437 lut_base = SEQID_EN4B * 4;
438 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
440 /* Enter 4 Byte Mode (Spansion) */
441 lut_base = SEQID_BRWR * 4;
442 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
444 fsl_qspi_lock_lut(q);
447 /* Get the SEQID for the command */
448 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
451 case SPINOR_OP_READ_1_1_4:
452 return SEQID_QUAD_READ;
461 case SPINOR_OP_CHIP_ERASE:
462 return SEQID_CHIP_ERASE;
476 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
483 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
485 void __iomem *base = q->iobase;
490 init_completion(&q->c);
491 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
492 q->chip_base_addr, addr, len, cmd);
495 reg = readl(base + QUADSPI_MCR);
497 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
498 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
499 base + QUADSPI_RBCT);
500 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
503 reg2 = readl(base + QUADSPI_SR);
504 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
506 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
512 /* trigger the LUT now */
513 seqid = fsl_qspi_get_seqid(q, cmd);
514 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
516 /* Wait for the interrupt. */
517 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
519 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
520 cmd, addr, readl(base + QUADSPI_FR),
521 readl(base + QUADSPI_SR));
527 /* restore the MCR */
528 writel(reg, base + QUADSPI_MCR);
533 /* Read out the data from the QUADSPI_RBDR buffer registers. */
534 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
540 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
541 tmp = fsl_qspi_endian_xchg(q, tmp);
542 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
543 q->chip_base_addr, tmp);
546 *((u32 *)rxbuf) = tmp;
549 memcpy(rxbuf, &tmp, len);
559 * If we have changed the content of the flash by writing or erasing,
560 * we need to invalidate the AHB buffer. If we do not do so, we may read out
561 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
562 * domain at the same time.
564 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
568 reg = readl(q->iobase + QUADSPI_MCR);
569 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
570 writel(reg, q->iobase + QUADSPI_MCR);
573 * The minimum delay : 1 AHB + 2 SFCK clocks.
574 * Delay 1 us is enough.
578 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
579 writel(reg, q->iobase + QUADSPI_MCR);
582 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
583 u8 opcode, unsigned int to, u32 *txbuf,
584 unsigned count, size_t *retlen)
589 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
590 q->chip_base_addr, to, count);
592 /* clear the TX FIFO. */
593 tmp = readl(q->iobase + QUADSPI_MCR);
594 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
596 /* fill the TX data to the FIFO */
597 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
598 tmp = fsl_qspi_endian_xchg(q, *txbuf);
599 writel(tmp, q->iobase + QUADSPI_TBDR);
603 /* fill the TXFIFO upto 16 bytes for i.MX7d */
604 if (needs_fill_txfifo(q))
606 writel(tmp, q->iobase + QUADSPI_TBDR);
609 ret = fsl_qspi_runcmd(q, opcode, to, count);
611 if (ret == 0 && retlen)
617 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
619 int nor_size = q->nor_size;
620 void __iomem *base = q->iobase;
622 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
623 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
624 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
625 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
629 * There are two different ways to read out the data from the flash:
630 * the "IP Command Read" and the "AHB Command Read".
632 * The IC guy suggests we use the "AHB Command Read" which is faster
633 * then the "IP Command Read". (What's more is that there is a bug in
634 * the "IP Command Read" in the Vybrid.)
636 * After we set up the registers for the "AHB Command Read", we can use
637 * the memcpy to read the data directly. A "missed" access to the buffer
638 * causes the controller to clear the buffer, and use the sequence pointed
639 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
641 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
643 void __iomem *base = q->iobase;
646 /* AHB configuration for access buffer 0/1/2 .*/
647 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
648 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
649 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
651 * Set ADATSZ with the maximum AHB buffer size to improve the
654 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
655 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
657 /* We only use the buffer3 */
658 writel(0, base + QUADSPI_BUF0IND);
659 writel(0, base + QUADSPI_BUF1IND);
660 writel(0, base + QUADSPI_BUF2IND);
662 /* Set the default lut sequence for AHB Read. */
663 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
664 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
665 q->iobase + QUADSPI_BFGENCR);
668 /* This function was used to prepare and enable QSPI clock */
669 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
673 ret = clk_prepare_enable(q->clk_en);
677 ret = clk_prepare_enable(q->clk);
679 clk_disable_unprepare(q->clk_en);
683 if (needs_wakeup_wait_mode(q))
684 pm_qos_add_request(&q->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, 0);
689 /* This function was used to disable and unprepare QSPI clock */
690 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
692 if (needs_wakeup_wait_mode(q))
693 pm_qos_remove_request(&q->pm_qos_req);
695 clk_disable_unprepare(q->clk);
696 clk_disable_unprepare(q->clk_en);
700 /* We use this function to do some basic init for spi_nor_scan(). */
701 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
703 void __iomem *base = q->iobase;
707 /* disable and unprepare clock to avoid glitch pass to controller */
708 fsl_qspi_clk_disable_unprep(q);
710 /* the default frequency, we will change it in the future. */
711 ret = clk_set_rate(q->clk, 66000000);
715 ret = fsl_qspi_clk_prep_enable(q);
719 /* Init the LUT table. */
720 fsl_qspi_init_lut(q);
722 /* Disable the module */
723 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
726 reg = readl(base + QUADSPI_SMPR);
727 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
728 | QUADSPI_SMPR_FSPHS_MASK
729 | QUADSPI_SMPR_HSENA_MASK
730 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
732 /* Enable the module */
733 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
736 /* enable the interrupt */
737 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
742 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
744 unsigned long rate = q->clk_rate;
747 if (needs_4x_clock(q))
750 /* disable and unprepare clock to avoid glitch pass to controller */
751 fsl_qspi_clk_disable_unprep(q);
753 ret = clk_set_rate(q->clk, rate);
757 ret = fsl_qspi_clk_prep_enable(q);
761 /* Init the LUT table again. */
762 fsl_qspi_init_lut(q);
764 /* Init for AHB read */
765 fsl_qspi_init_abh_read(q);
770 static const struct of_device_id fsl_qspi_dt_ids[] = {
771 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
772 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
773 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
774 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
777 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
779 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
781 q->chip_base_addr = q->nor_size * (nor - q->nor);
784 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
787 struct fsl_qspi *q = nor->priv;
789 ret = fsl_qspi_runcmd(q, opcode, 0, len);
793 fsl_qspi_read_data(q, len, buf);
797 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
800 struct fsl_qspi *q = nor->priv;
804 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
808 if (opcode == SPINOR_OP_CHIP_ERASE)
811 } else if (len > 0) {
812 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
813 (u32 *)buf, len, NULL);
815 dev_err(q->dev, "invalid cmd %d\n", opcode);
822 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
823 size_t len, size_t *retlen, const u_char *buf)
825 struct fsl_qspi *q = nor->priv;
827 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
828 (u32 *)buf, len, retlen);
830 /* invalid the data in the AHB buffer. */
834 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
835 size_t len, size_t *retlen, u_char *buf)
837 struct fsl_qspi *q = nor->priv;
838 u8 cmd = nor->read_opcode;
840 /* if necessary,ioremap buffer before AHB read, */
842 q->memmap_offs = q->chip_base_addr + from;
843 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
845 q->ahb_addr = ioremap_nocache(
846 q->memmap_phy + q->memmap_offs,
849 dev_err(q->dev, "ioremap failed\n");
852 /* ioremap if the data requested is out of range */
853 } else if (q->chip_base_addr + from < q->memmap_offs
854 || q->chip_base_addr + from + len >
855 q->memmap_offs + q->memmap_len) {
856 iounmap(q->ahb_addr);
858 q->memmap_offs = q->chip_base_addr + from;
859 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
860 q->ahb_addr = ioremap_nocache(
861 q->memmap_phy + q->memmap_offs,
864 dev_err(q->dev, "ioremap failed\n");
869 dev_dbg(q->dev, "cmd [%x],read from 0x%p, len:%d\n",
870 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
873 /* Read out the data directly from the AHB buffer.*/
874 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
881 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
883 struct fsl_qspi *q = nor->priv;
886 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
887 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
889 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
897 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
899 struct fsl_qspi *q = nor->priv;
902 mutex_lock(&q->lock);
904 ret = fsl_qspi_clk_prep_enable(q);
908 fsl_qspi_set_base_addr(q, nor);
912 mutex_unlock(&q->lock);
916 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
918 struct fsl_qspi *q = nor->priv;
920 fsl_qspi_clk_disable_unprep(q);
921 mutex_unlock(&q->lock);
924 static int fsl_qspi_probe(struct platform_device *pdev)
926 struct device_node *np = pdev->dev.of_node;
927 struct mtd_part_parser_data ppdata;
928 struct device *dev = &pdev->dev;
930 struct resource *res;
932 struct mtd_info *mtd;
934 const struct of_device_id *of_id =
935 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
937 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
941 q->nor_num = of_get_child_count(dev->of_node);
942 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
946 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
947 platform_set_drvdata(pdev, q);
949 /* find the resources */
950 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
951 q->iobase = devm_ioremap_resource(dev, res);
952 if (IS_ERR(q->iobase))
953 return PTR_ERR(q->iobase);
955 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
957 if (!devm_request_mem_region(dev, res->start, resource_size(res),
959 dev_err(dev, "can't request region for resource %pR\n", res);
963 q->memmap_phy = res->start;
965 /* find the clocks */
966 q->clk_en = devm_clk_get(dev, "qspi_en");
967 if (IS_ERR(q->clk_en))
968 return PTR_ERR(q->clk_en);
970 q->clk = devm_clk_get(dev, "qspi");
972 return PTR_ERR(q->clk);
974 ret = fsl_qspi_clk_prep_enable(q);
976 dev_err(dev, "can not enable the clock\n");
981 ret = platform_get_irq(pdev, 0);
983 dev_err(dev, "failed to get the irq: %d\n", ret);
987 ret = devm_request_irq(dev, ret,
988 fsl_qspi_irq_handler, 0, pdev->name, q);
990 dev_err(dev, "failed to request irq: %d\n", ret);
994 ret = fsl_qspi_nor_setup(q);
998 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
999 q->has_second_chip = true;
1001 mutex_init(&q->lock);
1003 /* iterate the subnodes. */
1004 for_each_available_child_of_node(dev->of_node, np) {
1007 /* skip the holes */
1008 if (!q->has_second_chip)
1019 /* fill the hooks */
1020 nor->read_reg = fsl_qspi_read_reg;
1021 nor->write_reg = fsl_qspi_write_reg;
1022 nor->read = fsl_qspi_read;
1023 nor->write = fsl_qspi_write;
1024 nor->erase = fsl_qspi_erase;
1026 nor->prepare = fsl_qspi_prep;
1027 nor->unprepare = fsl_qspi_unprep;
1029 ret = of_modalias_node(np, modalias, sizeof(modalias));
1033 ret = of_property_read_u32(np, "spi-max-frequency",
1038 /* set the chip address for READID */
1039 fsl_qspi_set_base_addr(q, nor);
1041 ret = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
1045 ppdata.of_node = np;
1046 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1050 /* Set the correct NOR size now. */
1051 if (q->nor_size == 0) {
1052 q->nor_size = mtd->size;
1054 /* Map the SPI NOR to accessiable address */
1055 fsl_qspi_set_map_addr(q);
1059 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1060 * may writes 265 bytes per time. The write is working in the
1061 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1064 * So shrink the spi_nor->page_size if it is larger then the
1067 if (nor->page_size > q->devtype_data->txfifo)
1068 nor->page_size = q->devtype_data->txfifo;
1073 /* finish the rest init. */
1074 ret = fsl_qspi_nor_setup_last(q);
1076 goto last_init_failed;
1078 fsl_qspi_clk_disable_unprep(q);
1082 for (i = 0; i < q->nor_num; i++) {
1083 /* skip the holes */
1084 if (!q->has_second_chip)
1086 mtd_device_unregister(&q->mtd[i]);
1089 mutex_destroy(&q->lock);
1091 fsl_qspi_clk_disable_unprep(q);
1093 dev_err(dev, "Freescale QuadSPI probe failed\n");
1097 static int fsl_qspi_remove(struct platform_device *pdev)
1099 struct fsl_qspi *q = platform_get_drvdata(pdev);
1102 for (i = 0; i < q->nor_num; i++) {
1103 /* skip the holes */
1104 if (!q->has_second_chip)
1106 mtd_device_unregister(&q->mtd[i]);
1109 /* disable the hardware */
1110 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1111 writel(0x0, q->iobase + QUADSPI_RSER);
1113 mutex_destroy(&q->lock);
1116 iounmap(q->ahb_addr);
1121 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1126 static int fsl_qspi_resume(struct platform_device *pdev)
1129 struct fsl_qspi *q = platform_get_drvdata(pdev);
1131 ret = fsl_qspi_clk_prep_enable(q);
1135 fsl_qspi_nor_setup(q);
1136 fsl_qspi_set_map_addr(q);
1137 fsl_qspi_nor_setup_last(q);
1139 fsl_qspi_clk_disable_unprep(q);
1144 static struct platform_driver fsl_qspi_driver = {
1146 .name = "fsl-quadspi",
1147 .bus = &platform_bus_type,
1148 .of_match_table = fsl_qspi_dt_ids,
1150 .probe = fsl_qspi_probe,
1151 .remove = fsl_qspi_remove,
1152 .suspend = fsl_qspi_suspend,
1153 .resume = fsl_qspi_resume,
1155 module_platform_driver(fsl_qspi_driver);
1157 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1158 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1159 MODULE_LICENSE("GPL v2");