2 * Freescale QuadSPI driver.
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/interrupt.h>
14 #include <linux/errno.h>
15 #include <linux/platform_device.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/of_device.h>
23 #include <linux/timer.h>
24 #include <linux/jiffies.h>
25 #include <linux/completion.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/partitions.h>
28 #include <linux/mtd/spi-nor.h>
29 #include <linux/mutex.h>
31 /* Controller needs driver to swap endian */
32 #define QUADSPI_QUIRK_SWAP_ENDIAN (1 << 0)
33 /* Controller needs 4x internal clock */
34 #define QUADSPI_QUIRK_4X_INT_CLK (1 << 1)
36 * TKT253890, Controller needs driver to fill txfifo till 16 byte to
37 * trigger data transfer even though extern data will not transferred.
39 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
42 #define QUADSPI_MCR 0x00
43 #define QUADSPI_MCR_RESERVED_SHIFT 16
44 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
45 #define QUADSPI_MCR_MDIS_SHIFT 14
46 #define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
47 #define QUADSPI_MCR_CLR_TXF_SHIFT 11
48 #define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
49 #define QUADSPI_MCR_CLR_RXF_SHIFT 10
50 #define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
51 #define QUADSPI_MCR_DDR_EN_SHIFT 7
52 #define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
53 #define QUADSPI_MCR_END_CFG_SHIFT 2
54 #define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
55 #define QUADSPI_MCR_SWRSTHD_SHIFT 1
56 #define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
57 #define QUADSPI_MCR_SWRSTSD_SHIFT 0
58 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
60 #define QUADSPI_IPCR 0x08
61 #define QUADSPI_IPCR_SEQID_SHIFT 24
62 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
64 #define QUADSPI_BUF0CR 0x10
65 #define QUADSPI_BUF1CR 0x14
66 #define QUADSPI_BUF2CR 0x18
67 #define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
69 #define QUADSPI_BUF3CR 0x1c
70 #define QUADSPI_BUF3CR_ALLMST_SHIFT 31
71 #define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
72 #define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
73 #define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
75 #define QUADSPI_BFGENCR 0x20
76 #define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
77 #define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
78 #define QUADSPI_BFGENCR_SEQID_SHIFT 12
79 #define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
81 #define QUADSPI_BUF0IND 0x30
82 #define QUADSPI_BUF1IND 0x34
83 #define QUADSPI_BUF2IND 0x38
84 #define QUADSPI_SFAR 0x100
86 #define QUADSPI_SMPR 0x108
87 #define QUADSPI_SMPR_DDRSMP_SHIFT 16
88 #define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
89 #define QUADSPI_SMPR_FSDLY_SHIFT 6
90 #define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
91 #define QUADSPI_SMPR_FSPHS_SHIFT 5
92 #define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
93 #define QUADSPI_SMPR_HSENA_SHIFT 0
94 #define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
96 #define QUADSPI_RBSR 0x10c
97 #define QUADSPI_RBSR_RDBFL_SHIFT 8
98 #define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
100 #define QUADSPI_RBCT 0x110
101 #define QUADSPI_RBCT_WMRK_MASK 0x1F
102 #define QUADSPI_RBCT_RXBRD_SHIFT 8
103 #define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
105 #define QUADSPI_TBSR 0x150
106 #define QUADSPI_TBDR 0x154
107 #define QUADSPI_SR 0x15c
108 #define QUADSPI_SR_IP_ACC_SHIFT 1
109 #define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
110 #define QUADSPI_SR_AHB_ACC_SHIFT 2
111 #define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
113 #define QUADSPI_FR 0x160
114 #define QUADSPI_FR_TFF_MASK 0x1
116 #define QUADSPI_SFA1AD 0x180
117 #define QUADSPI_SFA2AD 0x184
118 #define QUADSPI_SFB1AD 0x188
119 #define QUADSPI_SFB2AD 0x18c
120 #define QUADSPI_RBDR 0x200
122 #define QUADSPI_LUTKEY 0x300
123 #define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
125 #define QUADSPI_LCKCR 0x304
126 #define QUADSPI_LCKER_LOCK 0x1
127 #define QUADSPI_LCKER_UNLOCK 0x2
129 #define QUADSPI_RSER 0x164
130 #define QUADSPI_RSER_TFIE (0x1 << 0)
132 #define QUADSPI_LUT_BASE 0x310
135 * The definition of the LUT register shows below:
137 * ---------------------------------------------------
138 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
139 * ---------------------------------------------------
141 #define OPRND0_SHIFT 0
143 #define INSTR0_SHIFT 10
144 #define OPRND1_SHIFT 16
146 /* Instruction set for the LUT register. */
156 #define LUT_JMP_ON_CS 9
157 #define LUT_ADDR_DDR 10
158 #define LUT_MODE_DDR 11
159 #define LUT_MODE2_DDR 12
160 #define LUT_MODE4_DDR 13
161 #define LUT_READ_DDR 14
162 #define LUT_WRITE_DDR 15
163 #define LUT_DATA_LEARN 16
166 * The PAD definitions for LUT register.
168 * The pad stands for the lines number of IO[0:3].
169 * For example, the Quad read need four IO lines, so you should
170 * set LUT_PAD4 which means we use four IO lines.
176 /* Oprands for the LUT register. */
177 #define ADDR24BIT 0x18
178 #define ADDR32BIT 0x20
180 /* Macros for constructing the LUT register. */
181 #define LUT0(ins, pad, opr) \
182 (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
183 ((LUT_##ins) << INSTR0_SHIFT))
185 #define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
187 /* other macros for LUT register. */
188 #define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
189 #define QUADSPI_LUT_NUM 64
191 /* SEQID -- we can have 16 seqids at most. */
192 #define SEQID_QUAD_READ 0
197 #define SEQID_CHIP_ERASE 5
202 #define SEQID_EN4B 10
203 #define SEQID_BRWR 11
205 #define QUADSPI_MIN_IOMAP SZ_4M
207 enum fsl_qspi_devtype {
214 struct fsl_qspi_devtype_data {
215 enum fsl_qspi_devtype devtype;
222 static struct fsl_qspi_devtype_data vybrid_data = {
223 .devtype = FSL_QUADSPI_VYBRID,
226 .ahb_buf_size = 1024,
227 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
230 static struct fsl_qspi_devtype_data imx6sx_data = {
231 .devtype = FSL_QUADSPI_IMX6SX,
234 .ahb_buf_size = 1024,
235 .driver_data = QUADSPI_QUIRK_4X_INT_CLK,
238 static struct fsl_qspi_devtype_data imx7d_data = {
239 .devtype = FSL_QUADSPI_IMX7D,
242 .ahb_buf_size = 1024,
243 .driver_data = QUADSPI_QUIRK_TKT253890
244 | QUADSPI_QUIRK_4X_INT_CLK,
247 static struct fsl_qspi_devtype_data imx6ul_data = {
248 .devtype = FSL_QUADSPI_IMX6UL,
251 .ahb_buf_size = 1024,
252 .driver_data = QUADSPI_QUIRK_TKT253890
253 | QUADSPI_QUIRK_4X_INT_CLK,
256 #define FSL_QSPI_MAX_CHIP 4
258 struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
259 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
260 void __iomem *iobase;
261 void __iomem *ahb_addr;
265 struct clk *clk, *clk_en;
268 struct fsl_qspi_devtype_data *devtype_data;
272 unsigned int chip_base_addr; /* We may support two chips. */
273 bool has_second_chip;
277 static inline int needs_swap_endian(struct fsl_qspi *q)
279 return q->devtype_data->driver_data & QUADSPI_QUIRK_SWAP_ENDIAN;
282 static inline int needs_4x_clock(struct fsl_qspi *q)
284 return q->devtype_data->driver_data & QUADSPI_QUIRK_4X_INT_CLK;
287 static inline int needs_fill_txfifo(struct fsl_qspi *q)
289 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT253890;
293 * An IC bug makes us to re-arrange the 32-bit data.
294 * The following chips, such as IMX6SLX, have fixed this bug.
296 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
298 return needs_swap_endian(q) ? __swab32(a) : a;
301 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
303 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
304 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
307 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
309 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
310 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
313 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
315 struct fsl_qspi *q = dev_id;
318 /* clear interrupt */
319 reg = readl(q->iobase + QUADSPI_FR);
320 writel(reg, q->iobase + QUADSPI_FR);
322 if (reg & QUADSPI_FR_TFF_MASK)
325 dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
329 static void fsl_qspi_init_lut(struct fsl_qspi *q)
331 void __iomem *base = q->iobase;
332 int rxfifo = q->devtype_data->rxfifo;
334 u8 cmd, addrlen, dummy;
337 fsl_qspi_unlock_lut(q);
339 /* Clear all the LUT table */
340 for (i = 0; i < QUADSPI_LUT_NUM; i++)
341 writel(0, base + QUADSPI_LUT_BASE + i * 4);
344 lut_base = SEQID_QUAD_READ * 4;
346 if (q->nor_size <= SZ_16M) {
347 cmd = SPINOR_OP_READ_1_1_4;
351 /* use the 4-byte address */
352 cmd = SPINOR_OP_READ_1_1_4;
357 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
358 base + QUADSPI_LUT(lut_base));
359 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
360 base + QUADSPI_LUT(lut_base + 1));
363 lut_base = SEQID_WREN * 4;
364 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
367 lut_base = SEQID_PP * 4;
369 if (q->nor_size <= SZ_16M) {
373 /* use the 4-byte address */
378 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
379 base + QUADSPI_LUT(lut_base));
380 writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
383 lut_base = SEQID_RDSR * 4;
384 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
385 base + QUADSPI_LUT(lut_base));
388 lut_base = SEQID_SE * 4;
390 if (q->nor_size <= SZ_16M) {
394 /* use the 4-byte address */
399 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
400 base + QUADSPI_LUT(lut_base));
402 /* Erase the whole chip */
403 lut_base = SEQID_CHIP_ERASE * 4;
404 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
405 base + QUADSPI_LUT(lut_base));
408 lut_base = SEQID_RDID * 4;
409 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
410 base + QUADSPI_LUT(lut_base));
413 lut_base = SEQID_WRSR * 4;
414 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
415 base + QUADSPI_LUT(lut_base));
417 /* Read Configuration Register */
418 lut_base = SEQID_RDCR * 4;
419 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
420 base + QUADSPI_LUT(lut_base));
423 lut_base = SEQID_WRDI * 4;
424 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
426 /* Enter 4 Byte Mode (Micron) */
427 lut_base = SEQID_EN4B * 4;
428 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
430 /* Enter 4 Byte Mode (Spansion) */
431 lut_base = SEQID_BRWR * 4;
432 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
434 fsl_qspi_lock_lut(q);
437 /* Get the SEQID for the command */
438 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
441 case SPINOR_OP_READ_1_1_4:
442 return SEQID_QUAD_READ;
451 case SPINOR_OP_CHIP_ERASE:
452 return SEQID_CHIP_ERASE;
466 dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
473 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
475 void __iomem *base = q->iobase;
480 init_completion(&q->c);
481 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
482 q->chip_base_addr, addr, len, cmd);
485 reg = readl(base + QUADSPI_MCR);
487 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
488 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
489 base + QUADSPI_RBCT);
490 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
493 reg2 = readl(base + QUADSPI_SR);
494 if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
496 dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
502 /* trigger the LUT now */
503 seqid = fsl_qspi_get_seqid(q, cmd);
504 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
506 /* Wait for the interrupt. */
507 if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
509 "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
510 cmd, addr, readl(base + QUADSPI_FR),
511 readl(base + QUADSPI_SR));
517 /* restore the MCR */
518 writel(reg, base + QUADSPI_MCR);
523 /* Read out the data from the QUADSPI_RBDR buffer registers. */
524 static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
530 tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
531 tmp = fsl_qspi_endian_xchg(q, tmp);
532 dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
533 q->chip_base_addr, tmp);
536 *((u32 *)rxbuf) = tmp;
539 memcpy(rxbuf, &tmp, len);
549 * If we have changed the content of the flash by writing or erasing,
550 * we need to invalidate the AHB buffer. If we do not do so, we may read out
551 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
552 * domain at the same time.
554 static inline void fsl_qspi_invalid(struct fsl_qspi *q)
558 reg = readl(q->iobase + QUADSPI_MCR);
559 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
560 writel(reg, q->iobase + QUADSPI_MCR);
563 * The minimum delay : 1 AHB + 2 SFCK clocks.
564 * Delay 1 us is enough.
568 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
569 writel(reg, q->iobase + QUADSPI_MCR);
572 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
573 u8 opcode, unsigned int to, u32 *txbuf,
574 unsigned count, size_t *retlen)
579 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
580 q->chip_base_addr, to, count);
582 /* clear the TX FIFO. */
583 tmp = readl(q->iobase + QUADSPI_MCR);
584 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
586 /* fill the TX data to the FIFO */
587 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
588 tmp = fsl_qspi_endian_xchg(q, *txbuf);
589 writel(tmp, q->iobase + QUADSPI_TBDR);
593 /* fill the TXFIFO upto 16 bytes for i.MX7d */
594 if (needs_fill_txfifo(q))
596 writel(tmp, q->iobase + QUADSPI_TBDR);
599 ret = fsl_qspi_runcmd(q, opcode, to, count);
601 if (ret == 0 && retlen)
607 static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
609 int nor_size = q->nor_size;
610 void __iomem *base = q->iobase;
612 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
613 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
614 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
615 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
619 * There are two different ways to read out the data from the flash:
620 * the "IP Command Read" and the "AHB Command Read".
622 * The IC guy suggests we use the "AHB Command Read" which is faster
623 * then the "IP Command Read". (What's more is that there is a bug in
624 * the "IP Command Read" in the Vybrid.)
626 * After we set up the registers for the "AHB Command Read", we can use
627 * the memcpy to read the data directly. A "missed" access to the buffer
628 * causes the controller to clear the buffer, and use the sequence pointed
629 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
631 static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
633 void __iomem *base = q->iobase;
636 /* AHB configuration for access buffer 0/1/2 .*/
637 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
638 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
639 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
641 * Set ADATSZ with the maximum AHB buffer size to improve the
644 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
645 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
647 /* We only use the buffer3 */
648 writel(0, base + QUADSPI_BUF0IND);
649 writel(0, base + QUADSPI_BUF1IND);
650 writel(0, base + QUADSPI_BUF2IND);
652 /* Set the default lut sequence for AHB Read. */
653 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
654 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
655 q->iobase + QUADSPI_BFGENCR);
658 /* We use this function to do some basic init for spi_nor_scan(). */
659 static int fsl_qspi_nor_setup(struct fsl_qspi *q)
661 void __iomem *base = q->iobase;
665 /* the default frequency, we will change it in the future.*/
666 ret = clk_set_rate(q->clk, 66000000);
670 /* Init the LUT table. */
671 fsl_qspi_init_lut(q);
673 /* Disable the module */
674 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
677 reg = readl(base + QUADSPI_SMPR);
678 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
679 | QUADSPI_SMPR_FSPHS_MASK
680 | QUADSPI_SMPR_HSENA_MASK
681 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
683 /* Enable the module */
684 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
687 /* enable the interrupt */
688 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
693 static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
695 unsigned long rate = q->clk_rate;
698 if (needs_4x_clock(q))
701 ret = clk_set_rate(q->clk, rate);
705 /* Init the LUT table again. */
706 fsl_qspi_init_lut(q);
708 /* Init for AHB read */
709 fsl_qspi_init_abh_read(q);
714 static const struct of_device_id fsl_qspi_dt_ids[] = {
715 { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
716 { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
717 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
718 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
721 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
723 static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
725 q->chip_base_addr = q->nor_size * (nor - q->nor);
728 static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
731 struct fsl_qspi *q = nor->priv;
733 ret = fsl_qspi_runcmd(q, opcode, 0, len);
737 fsl_qspi_read_data(q, len, buf);
741 static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
744 struct fsl_qspi *q = nor->priv;
748 ret = fsl_qspi_runcmd(q, opcode, 0, 1);
752 if (opcode == SPINOR_OP_CHIP_ERASE)
755 } else if (len > 0) {
756 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
757 (u32 *)buf, len, NULL);
759 dev_err(q->dev, "invalid cmd %d\n", opcode);
766 static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
767 size_t len, size_t *retlen, const u_char *buf)
769 struct fsl_qspi *q = nor->priv;
771 fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
772 (u32 *)buf, len, retlen);
774 /* invalid the data in the AHB buffer. */
778 static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
779 size_t len, size_t *retlen, u_char *buf)
781 struct fsl_qspi *q = nor->priv;
782 u8 cmd = nor->read_opcode;
784 /* if necessary,ioremap buffer before AHB read, */
786 q->memmap_offs = q->chip_base_addr + from;
787 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
789 q->ahb_addr = ioremap_nocache(
790 q->memmap_phy + q->memmap_offs,
793 dev_err(q->dev, "ioremap failed\n");
796 /* ioremap if the data requested is out of range */
797 } else if (q->chip_base_addr + from < q->memmap_offs
798 || q->chip_base_addr + from + len >
799 q->memmap_offs + q->memmap_len) {
800 iounmap(q->ahb_addr);
802 q->memmap_offs = q->chip_base_addr + from;
803 q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
804 q->ahb_addr = ioremap_nocache(
805 q->memmap_phy + q->memmap_offs,
808 dev_err(q->dev, "ioremap failed\n");
813 dev_dbg(q->dev, "cmd [%x],read from 0x%p, len:%d\n",
814 cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
817 /* Read out the data directly from the AHB buffer.*/
818 memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
825 static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
827 struct fsl_qspi *q = nor->priv;
830 dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
831 nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
833 ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
841 static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
843 struct fsl_qspi *q = nor->priv;
846 mutex_lock(&q->lock);
847 ret = clk_enable(q->clk_en);
851 ret = clk_enable(q->clk);
855 fsl_qspi_set_base_addr(q, nor);
859 clk_disable(q->clk_en);
861 mutex_unlock(&q->lock);
866 static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
868 struct fsl_qspi *q = nor->priv;
871 clk_disable(q->clk_en);
872 mutex_unlock(&q->lock);
875 static int fsl_qspi_probe(struct platform_device *pdev)
877 struct device_node *np = pdev->dev.of_node;
878 struct mtd_part_parser_data ppdata;
879 struct device *dev = &pdev->dev;
881 struct resource *res;
883 struct mtd_info *mtd;
885 const struct of_device_id *of_id =
886 of_match_device(fsl_qspi_dt_ids, &pdev->dev);
888 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
892 q->nor_num = of_get_child_count(dev->of_node);
893 if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
896 /* find the resources */
897 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
898 q->iobase = devm_ioremap_resource(dev, res);
899 if (IS_ERR(q->iobase))
900 return PTR_ERR(q->iobase);
902 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
904 if (!devm_request_mem_region(dev, res->start, resource_size(res),
906 dev_err(dev, "can't request region for resource %pR\n", res);
910 q->memmap_phy = res->start;
912 /* find the clocks */
913 q->clk_en = devm_clk_get(dev, "qspi_en");
914 if (IS_ERR(q->clk_en))
915 return PTR_ERR(q->clk_en);
917 q->clk = devm_clk_get(dev, "qspi");
919 return PTR_ERR(q->clk);
921 ret = clk_prepare_enable(q->clk_en);
923 dev_err(dev, "cannot enable the qspi_en clock: %d\n", ret);
927 ret = clk_prepare_enable(q->clk);
929 dev_err(dev, "cannot enable the qspi clock: %d\n", ret);
934 ret = platform_get_irq(pdev, 0);
936 dev_err(dev, "failed to get the irq: %d\n", ret);
940 ret = devm_request_irq(dev, ret,
941 fsl_qspi_irq_handler, 0, pdev->name, q);
943 dev_err(dev, "failed to request irq: %d\n", ret);
948 q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
949 platform_set_drvdata(pdev, q);
951 ret = fsl_qspi_nor_setup(q);
955 if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
956 q->has_second_chip = true;
958 mutex_init(&q->lock);
960 /* iterate the subnodes. */
961 for_each_available_child_of_node(dev->of_node, np) {
965 if (!q->has_second_chip)
977 nor->read_reg = fsl_qspi_read_reg;
978 nor->write_reg = fsl_qspi_write_reg;
979 nor->read = fsl_qspi_read;
980 nor->write = fsl_qspi_write;
981 nor->erase = fsl_qspi_erase;
983 nor->prepare = fsl_qspi_prep;
984 nor->unprepare = fsl_qspi_unprep;
986 ret = of_modalias_node(np, modalias, sizeof(modalias));
990 ret = of_property_read_u32(np, "spi-max-frequency",
995 /* set the chip address for READID */
996 fsl_qspi_set_base_addr(q, nor);
998 ret = spi_nor_scan(nor, modalias, SPI_NOR_QUAD);
1002 ppdata.of_node = np;
1003 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1007 /* Set the correct NOR size now. */
1008 if (q->nor_size == 0) {
1009 q->nor_size = mtd->size;
1011 /* Map the SPI NOR to accessiable address */
1012 fsl_qspi_set_map_addr(q);
1016 * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
1017 * may writes 265 bytes per time. The write is working in the
1018 * unit of the TX FIFO, not in the unit of the SPI NOR's page
1021 * So shrink the spi_nor->page_size if it is larger then the
1024 if (nor->page_size > q->devtype_data->txfifo)
1025 nor->page_size = q->devtype_data->txfifo;
1030 /* finish the rest init. */
1031 ret = fsl_qspi_nor_setup_last(q);
1033 goto last_init_failed;
1035 clk_disable(q->clk);
1036 clk_disable(q->clk_en);
1040 for (i = 0; i < q->nor_num; i++) {
1041 /* skip the holes */
1042 if (!q->has_second_chip)
1044 mtd_device_unregister(&q->mtd[i]);
1047 mutex_destroy(&q->lock);
1049 clk_disable_unprepare(q->clk);
1051 clk_disable_unprepare(q->clk_en);
1055 static int fsl_qspi_remove(struct platform_device *pdev)
1057 struct fsl_qspi *q = platform_get_drvdata(pdev);
1060 for (i = 0; i < q->nor_num; i++) {
1061 /* skip the holes */
1062 if (!q->has_second_chip)
1064 mtd_device_unregister(&q->mtd[i]);
1067 /* disable the hardware */
1068 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1069 writel(0x0, q->iobase + QUADSPI_RSER);
1071 mutex_destroy(&q->lock);
1072 clk_unprepare(q->clk);
1073 clk_unprepare(q->clk_en);
1076 iounmap(q->ahb_addr);
1081 static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
1086 static int fsl_qspi_resume(struct platform_device *pdev)
1088 struct fsl_qspi *q = platform_get_drvdata(pdev);
1090 fsl_qspi_nor_setup(q);
1091 fsl_qspi_set_map_addr(q);
1092 fsl_qspi_nor_setup_last(q);
1097 static struct platform_driver fsl_qspi_driver = {
1099 .name = "fsl-quadspi",
1100 .bus = &platform_bus_type,
1101 .of_match_table = fsl_qspi_dt_ids,
1103 .probe = fsl_qspi_probe,
1104 .remove = fsl_qspi_remove,
1105 .suspend = fsl_qspi_suspend,
1106 .resume = fsl_qspi_resume,
1108 module_platform_driver(fsl_qspi_driver);
1110 MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1111 MODULE_AUTHOR("Freescale Semiconductor Inc.");
1112 MODULE_LICENSE("GPL v2");