2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
19 #include <linux/sizes.h>
21 #include <linux/mtd/cfi.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/of_platform.h>
24 #include <linux/spi/flash.h>
25 #include <linux/mtd/spi-nor.h>
27 /* Define max times to check status register before we give up. */
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
41 #define SPI_NOR_MAX_ID_LEN 6
47 * This array stores the ID bytes.
48 * The first three bytes are the JEDIC ID.
49 * JEDEC ID zero means "no ID" (mostly older chips).
51 u8 id[SPI_NOR_MAX_ID_LEN];
54 /* The size listed here is what works with SPINOR_OP_SE, which isn't
55 * necessarily called a "sector" by the vendor.
64 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
65 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
66 #define SST_WRITE 0x04 /* use SST byte programming */
67 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
68 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
69 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
70 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
71 #define USE_FSR 0x80 /* use flag status register */
74 #define JEDEC_MFR(info) ((info)->id[0])
76 static const struct flash_info *spi_nor_match_id(const char *name);
79 * Read the status register, returning its value in the location
80 * Return the status register value.
81 * Returns negative if error occurred.
83 static int read_sr(struct spi_nor *nor)
88 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
90 pr_err("error %d reading SR\n", (int) ret);
98 * Read the flag status register, returning its value in the location
99 * Return the status register value.
100 * Returns negative if error occurred.
102 static int read_fsr(struct spi_nor *nor)
107 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
109 pr_err("error %d reading FSR\n", ret);
117 * Read configuration register, returning its value in the
118 * location. Return the configuration register value.
119 * Returns negative if error occured.
121 static int read_cr(struct spi_nor *nor)
126 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
128 dev_err(nor->dev, "error %d reading CR\n", ret);
136 * Dummy Cycle calculation for different type of read.
137 * It can be used to support more commands with
138 * different dummy cycle requirements.
140 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
142 switch (nor->flash_read) {
154 * Write status register 1 byte
155 * Returns negative if error occurred.
157 static inline int write_sr(struct spi_nor *nor, u8 val)
159 nor->cmd_buf[0] = val;
160 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
164 * Set write enable latch with Write Enable command.
165 * Returns negative if error occurred.
167 static inline int write_enable(struct spi_nor *nor)
169 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
173 * Send write disble instruction to the chip.
175 static inline int write_disable(struct spi_nor *nor)
177 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
180 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
185 /* Enable/disable 4-byte addressing mode. */
186 static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
190 bool need_wren = false;
193 switch (JEDEC_MFR(info)) {
194 case CFI_MFR_ST: /* Micron, actually */
195 /* Some Micron need WREN command; all will accept it */
197 case CFI_MFR_MACRONIX:
198 case 0xEF /* winbond */:
202 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
203 status = nor->write_reg(nor, cmd, NULL, 0);
210 nor->cmd_buf[0] = enable << 7;
211 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
214 static inline int spi_nor_sr_ready(struct spi_nor *nor)
216 int sr = read_sr(nor);
220 return !(sr & SR_WIP);
223 static inline int spi_nor_fsr_ready(struct spi_nor *nor)
225 int fsr = read_fsr(nor);
229 return fsr & FSR_READY;
232 static int spi_nor_ready(struct spi_nor *nor)
235 sr = spi_nor_sr_ready(nor);
238 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
245 * Service routine to read status register until ready, or timeout occurs.
246 * Returns non-zero if error.
248 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
249 unsigned long timeout_jiffies)
251 unsigned long deadline;
252 int timeout = 0, ret;
254 deadline = jiffies + timeout_jiffies;
257 if (time_after_eq(jiffies, deadline))
260 ret = spi_nor_ready(nor);
269 dev_err(nor->dev, "flash operation timed out\n");
274 static int spi_nor_wait_till_ready(struct spi_nor *nor)
276 return spi_nor_wait_till_ready_with_timeout(nor,
277 DEFAULT_READY_WAIT_JIFFIES);
281 * Erase the whole flash memory
283 * Returns 0 if successful, non-zero otherwise.
285 static int erase_chip(struct spi_nor *nor)
287 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
289 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
292 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
296 mutex_lock(&nor->lock);
299 ret = nor->prepare(nor, ops);
301 dev_err(nor->dev, "failed in the preparation.\n");
302 mutex_unlock(&nor->lock);
309 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
312 nor->unprepare(nor, ops);
313 mutex_unlock(&nor->lock);
317 * Erase an address range on the nor chip. The address range may extend
318 * one or more erase sectors. Return an error is there is a problem erasing.
320 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
322 struct spi_nor *nor = mtd_to_spi_nor(mtd);
327 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
328 (long long)instr->len);
330 div_u64_rem(instr->len, mtd->erasesize, &rem);
337 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
341 /* whole-chip erase? */
342 if (len == mtd->size) {
343 unsigned long timeout;
347 if (erase_chip(nor)) {
353 * Scale the timeout linearly with the size of the flash, with
354 * a minimum calibrated to an old 2MB flash. We could try to
355 * pull these from CFI/SFDP, but these values should be good
358 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
359 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
360 (unsigned long)(mtd->size / SZ_2M));
361 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
365 /* REVISIT in some cases we could speed up erasing large regions
366 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
367 * to use "small sector erase", but that's not always optimal.
370 /* "sector"-at-a-time erase */
375 if (nor->erase(nor, addr)) {
380 addr += mtd->erasesize;
381 len -= mtd->erasesize;
383 ret = spi_nor_wait_till_ready(nor);
391 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
393 instr->state = MTD_ERASE_DONE;
394 mtd_erase_callback(instr);
399 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
400 instr->state = MTD_ERASE_FAILED;
404 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
406 struct mtd_info *mtd = &nor->mtd;
407 uint32_t offset = ofs;
408 uint8_t status_old, status_new;
411 status_old = read_sr(nor);
413 if (offset < mtd->size - (mtd->size / 2))
414 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
415 else if (offset < mtd->size - (mtd->size / 4))
416 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
417 else if (offset < mtd->size - (mtd->size / 8))
418 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
419 else if (offset < mtd->size - (mtd->size / 16))
420 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
421 else if (offset < mtd->size - (mtd->size / 32))
422 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
423 else if (offset < mtd->size - (mtd->size / 64))
424 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
426 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
428 /* Only modify protection if it will not unlock other areas */
429 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
430 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
432 ret = write_sr(nor, status_new);
438 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
440 struct mtd_info *mtd = &nor->mtd;
441 uint32_t offset = ofs;
442 uint8_t status_old, status_new;
445 status_old = read_sr(nor);
447 if (offset+len > mtd->size - (mtd->size / 64))
448 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
449 else if (offset+len > mtd->size - (mtd->size / 32))
450 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
451 else if (offset+len > mtd->size - (mtd->size / 16))
452 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
453 else if (offset+len > mtd->size - (mtd->size / 8))
454 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
455 else if (offset+len > mtd->size - (mtd->size / 4))
456 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
457 else if (offset+len > mtd->size - (mtd->size / 2))
458 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
460 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
462 /* Only modify protection if it will not lock other areas */
463 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
464 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
466 ret = write_sr(nor, status_new);
472 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
474 struct spi_nor *nor = mtd_to_spi_nor(mtd);
477 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
481 ret = nor->flash_lock(nor, ofs, len);
483 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
487 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
489 struct spi_nor *nor = mtd_to_spi_nor(mtd);
492 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
496 ret = nor->flash_unlock(nor, ofs, len);
498 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
502 /* Used when the "_ext_id" is two bytes at most */
503 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
505 ((_jedec_id) >> 16) & 0xff, \
506 ((_jedec_id) >> 8) & 0xff, \
507 (_jedec_id) & 0xff, \
508 ((_ext_id) >> 8) & 0xff, \
511 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
512 .sector_size = (_sector_size), \
513 .n_sectors = (_n_sectors), \
517 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
519 ((_jedec_id) >> 16) & 0xff, \
520 ((_jedec_id) >> 8) & 0xff, \
521 (_jedec_id) & 0xff, \
522 ((_ext_id) >> 16) & 0xff, \
523 ((_ext_id) >> 8) & 0xff, \
527 .sector_size = (_sector_size), \
528 .n_sectors = (_n_sectors), \
532 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
533 .sector_size = (_sector_size), \
534 .n_sectors = (_n_sectors), \
535 .page_size = (_page_size), \
536 .addr_width = (_addr_width), \
539 /* NOTE: double check command sets and memory organization when you add
540 * more nor chips. This current list focusses on newer chips, which
541 * have been converging on command sets which including JEDEC ID.
543 * All newly added entries should describe *hardware* and should use SECT_4K
544 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
545 * scenarios excluding small sectors there is config option that can be
546 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
547 * For historical (and compatibility) reasons (before we got above config) some
548 * old entries may be missing 4K flag.
550 static const struct flash_info spi_nor_ids[] = {
551 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
552 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
553 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
555 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
556 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
557 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
559 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
560 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
561 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
562 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
564 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
567 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
568 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
569 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
570 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
571 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
572 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
573 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
574 { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
577 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
580 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
581 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
584 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
587 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
588 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
589 { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
591 /* Intel/Numonyx -- xxxs33b */
592 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
593 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
594 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
597 { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
600 { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
601 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
602 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
603 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
604 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
605 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
606 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
607 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
608 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
609 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
610 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
611 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
612 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
613 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
614 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
617 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
618 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
619 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
620 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
621 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
622 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
623 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
624 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
625 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
628 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
629 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
630 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
632 /* Spansion -- single (large) sector size only, at least
633 * for the chips listed here (without boot sectors).
635 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
636 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
637 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
638 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
639 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
640 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
641 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
642 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
643 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
644 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
645 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
646 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
647 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
648 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
649 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
650 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
651 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
652 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
653 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
654 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
655 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
656 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K) },
658 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
659 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
660 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
661 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
662 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
663 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
664 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
665 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
666 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
667 { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
668 { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
669 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
670 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
672 /* ST Microelectronics -- newer production may have feature updates */
673 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
674 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
675 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
676 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
677 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
678 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
679 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
680 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
681 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
683 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
684 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
685 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
686 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
687 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
688 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
689 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
690 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
691 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
693 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
694 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
695 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
697 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
698 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
699 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
701 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
702 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
703 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
704 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
705 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
706 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
708 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
709 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
710 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
711 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
712 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
713 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
714 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
715 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
716 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
717 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
718 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
719 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
720 { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
721 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
722 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
723 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
724 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
726 /* Catalyst / On Semiconductor -- non-JEDEC */
727 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
728 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
729 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
730 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
731 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
735 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
738 u8 id[SPI_NOR_MAX_ID_LEN];
739 const struct flash_info *info;
741 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
743 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
747 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
748 info = &spi_nor_ids[tmp];
750 if (!memcmp(info->id, id, info->id_len))
751 return &spi_nor_ids[tmp];
754 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
755 id[0], id[1], id[2]);
756 return ERR_PTR(-ENODEV);
759 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
760 size_t *retlen, u_char *buf)
762 struct spi_nor *nor = mtd_to_spi_nor(mtd);
765 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
767 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
771 ret = nor->read(nor, from, len, retlen, buf);
773 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
777 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
778 size_t *retlen, const u_char *buf)
780 struct spi_nor *nor = mtd_to_spi_nor(mtd);
784 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
786 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
792 nor->sst_write_second = false;
795 /* Start write from odd address. */
797 nor->program_opcode = SPINOR_OP_BP;
799 /* write one byte. */
800 nor->write(nor, to, 1, retlen, buf);
801 ret = spi_nor_wait_till_ready(nor);
807 /* Write out most of the data here. */
808 for (; actual < len - 1; actual += 2) {
809 nor->program_opcode = SPINOR_OP_AAI_WP;
811 /* write two bytes. */
812 nor->write(nor, to, 2, retlen, buf + actual);
813 ret = spi_nor_wait_till_ready(nor);
817 nor->sst_write_second = true;
819 nor->sst_write_second = false;
822 ret = spi_nor_wait_till_ready(nor);
826 /* Write out trailing byte if it exists. */
830 nor->program_opcode = SPINOR_OP_BP;
831 nor->write(nor, to, 1, retlen, buf + actual);
833 ret = spi_nor_wait_till_ready(nor);
839 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
844 * Write an address range to the nor chip. Data must be written in
845 * FLASH_PAGESIZE chunks. The address range may be any size provided
846 * it is within the physical boundaries.
848 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
849 size_t *retlen, const u_char *buf)
851 struct spi_nor *nor = mtd_to_spi_nor(mtd);
852 u32 page_offset, page_size, i;
855 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
857 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
863 page_offset = to & (nor->page_size - 1);
865 /* do all the bytes fit onto one page? */
866 if (page_offset + len <= nor->page_size) {
867 nor->write(nor, to, len, retlen, buf);
869 /* the size of data remaining on the first page */
870 page_size = nor->page_size - page_offset;
871 nor->write(nor, to, page_size, retlen, buf);
873 /* write everything in nor->page_size chunks */
874 for (i = page_size; i < len; i += page_size) {
876 if (page_size > nor->page_size)
877 page_size = nor->page_size;
879 ret = spi_nor_wait_till_ready(nor);
885 nor->write(nor, to + i, page_size, retlen, buf + i);
889 ret = spi_nor_wait_till_ready(nor);
891 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
895 static int macronix_quad_enable(struct spi_nor *nor)
902 write_sr(nor, val | SR_QUAD_EN_MX);
904 if (spi_nor_wait_till_ready(nor))
908 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
909 dev_err(nor->dev, "Macronix Quad bit not set\n");
917 * Write status Register and configuration register with 2 bytes
918 * The first byte will be written to the status register, while the
919 * second byte will be written to the configuration register.
920 * Return negative if error occured.
922 static int write_sr_cr(struct spi_nor *nor, u16 val)
924 nor->cmd_buf[0] = val & 0xff;
925 nor->cmd_buf[1] = (val >> 8);
927 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
930 static int spansion_quad_enable(struct spi_nor *nor)
933 int quad_en = CR_QUAD_EN_SPAN << 8;
937 ret = write_sr_cr(nor, quad_en);
940 "error while writing configuration register\n");
944 /* read back and check it */
946 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
947 dev_err(nor->dev, "Spansion Quad bit not set\n");
954 static int micron_quad_enable(struct spi_nor *nor)
959 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
961 dev_err(nor->dev, "error %d reading EVCR\n", ret);
967 /* set EVCR, enable quad I/O */
968 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
969 ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
971 dev_err(nor->dev, "error while writing EVCR register\n");
975 ret = spi_nor_wait_till_ready(nor);
979 /* read EVCR and check it */
980 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
982 dev_err(nor->dev, "error %d reading EVCR\n", ret);
985 if (val & EVCR_QUAD_EN_MICRON) {
986 dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
993 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
997 switch (JEDEC_MFR(info)) {
998 case CFI_MFR_MACRONIX:
999 status = macronix_quad_enable(nor);
1001 dev_err(nor->dev, "Macronix quad-read not enabled\n");
1006 status = micron_quad_enable(nor);
1008 dev_err(nor->dev, "Micron quad-read not enabled\n");
1013 status = spansion_quad_enable(nor);
1015 dev_err(nor->dev, "Spansion quad-read not enabled\n");
1022 static int spi_nor_check(struct spi_nor *nor)
1024 if (!nor->dev || !nor->read || !nor->write ||
1025 !nor->read_reg || !nor->write_reg || !nor->erase) {
1026 pr_err("spi-nor: please fill all the necessary fields!\n");
1033 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
1035 const struct flash_info *info = NULL;
1036 struct device *dev = nor->dev;
1037 struct mtd_info *mtd = &nor->mtd;
1038 struct device_node *np = nor->flash_node;
1042 ret = spi_nor_check(nor);
1047 info = spi_nor_match_id(name);
1048 /* Try to auto-detect if chip name wasn't specified or not found */
1050 info = spi_nor_read_id(nor);
1051 if (IS_ERR_OR_NULL(info))
1055 * If caller has specified name of flash model that can normally be
1056 * detected using JEDEC, let's verify it.
1058 if (name && info->id_len) {
1059 const struct flash_info *jinfo;
1061 jinfo = spi_nor_read_id(nor);
1062 if (IS_ERR(jinfo)) {
1063 return PTR_ERR(jinfo);
1064 } else if (jinfo != info) {
1066 * JEDEC knows better, so overwrite platform ID. We
1067 * can't trust partitions any longer, but we'll let
1068 * mtd apply them anyway, since some partitions may be
1069 * marked read-only, and we don't want to lose that
1070 * information, even if it's not 100% accurate.
1072 dev_warn(dev, "found %s, expected %s\n",
1073 jinfo->name, info->name);
1078 mutex_init(&nor->lock);
1081 * Atmel, SST and Intel/Numonyx serial nor tend to power
1082 * up with the software protection bits set
1085 if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
1086 JEDEC_MFR(info) == CFI_MFR_INTEL ||
1087 JEDEC_MFR(info) == CFI_MFR_SST) {
1093 mtd->name = dev_name(dev);
1095 mtd->type = MTD_NORFLASH;
1097 mtd->flags = MTD_CAP_NORFLASH;
1098 mtd->size = info->sector_size * info->n_sectors;
1099 mtd->_erase = spi_nor_erase;
1100 mtd->_read = spi_nor_read;
1102 /* nor protection support for STmicro chips */
1103 if (JEDEC_MFR(info) == CFI_MFR_ST) {
1104 nor->flash_lock = stm_lock;
1105 nor->flash_unlock = stm_unlock;
1108 if (nor->flash_lock && nor->flash_unlock) {
1109 mtd->_lock = spi_nor_lock;
1110 mtd->_unlock = spi_nor_unlock;
1113 /* sst nor chips use AAI word program */
1114 if (info->flags & SST_WRITE)
1115 mtd->_write = sst_write;
1117 mtd->_write = spi_nor_write;
1119 if (info->flags & USE_FSR)
1120 nor->flags |= SNOR_F_USE_FSR;
1122 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
1123 /* prefer "small sector" erase if possible */
1124 if (info->flags & SECT_4K) {
1125 nor->erase_opcode = SPINOR_OP_BE_4K;
1126 mtd->erasesize = 4096;
1127 } else if (info->flags & SECT_4K_PMC) {
1128 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1129 mtd->erasesize = 4096;
1133 nor->erase_opcode = SPINOR_OP_SE;
1134 mtd->erasesize = info->sector_size;
1137 if (info->flags & SPI_NOR_NO_ERASE)
1138 mtd->flags |= MTD_NO_ERASE;
1140 mtd->dev.parent = dev;
1141 nor->page_size = info->page_size;
1142 mtd->writebufsize = nor->page_size;
1145 /* If we were instantiated by DT, use it */
1146 if (of_property_read_bool(np, "m25p,fast-read"))
1147 nor->flash_read = SPI_NOR_FAST;
1149 nor->flash_read = SPI_NOR_NORMAL;
1151 /* If we weren't instantiated by DT, default to fast-read */
1152 nor->flash_read = SPI_NOR_FAST;
1155 /* Some devices cannot do fast-read, no matter what DT tells us */
1156 if (info->flags & SPI_NOR_NO_FR)
1157 nor->flash_read = SPI_NOR_NORMAL;
1159 /* Quad/Dual-read mode takes precedence over fast/normal */
1160 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1161 ret = set_quad_mode(nor, info);
1163 dev_err(dev, "quad mode not supported\n");
1166 nor->flash_read = SPI_NOR_QUAD;
1167 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1168 nor->flash_read = SPI_NOR_DUAL;
1171 /* Default commands */
1172 switch (nor->flash_read) {
1174 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1177 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1180 nor->read_opcode = SPINOR_OP_READ_FAST;
1182 case SPI_NOR_NORMAL:
1183 nor->read_opcode = SPINOR_OP_READ;
1186 dev_err(dev, "No Read opcode defined\n");
1190 nor->program_opcode = SPINOR_OP_PP;
1192 if (info->addr_width)
1193 nor->addr_width = info->addr_width;
1194 else if (mtd->size > 0x1000000) {
1195 /* enable 4-byte addressing if the device exceeds 16MiB */
1196 nor->addr_width = 4;
1197 if (JEDEC_MFR(info) == CFI_MFR_AMD) {
1198 /* Dedicated 4-byte command set */
1199 switch (nor->flash_read) {
1201 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1204 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1207 nor->read_opcode = SPINOR_OP_READ4_FAST;
1209 case SPI_NOR_NORMAL:
1210 nor->read_opcode = SPINOR_OP_READ4;
1213 nor->program_opcode = SPINOR_OP_PP_4B;
1214 /* No small sector erase for 4-byte command set */
1215 nor->erase_opcode = SPINOR_OP_SE_4B;
1216 mtd->erasesize = info->sector_size;
1218 set_4byte(nor, info, 1);
1220 nor->addr_width = 3;
1223 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1225 dev_info(dev, "%s (%lld Kbytes)\n", info->name,
1226 (long long)mtd->size >> 10);
1229 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1230 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1231 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1232 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1234 if (mtd->numeraseregions)
1235 for (i = 0; i < mtd->numeraseregions; i++)
1237 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1238 ".erasesize = 0x%.8x (%uKiB), "
1239 ".numblocks = %d }\n",
1240 i, (long long)mtd->eraseregions[i].offset,
1241 mtd->eraseregions[i].erasesize,
1242 mtd->eraseregions[i].erasesize / 1024,
1243 mtd->eraseregions[i].numblocks);
1246 EXPORT_SYMBOL_GPL(spi_nor_scan);
1248 static const struct flash_info *spi_nor_match_id(const char *name)
1250 const struct flash_info *id = spi_nor_ids;
1253 if (!strcmp(name, id->name))
1260 MODULE_LICENSE("GPL");
1261 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1262 MODULE_AUTHOR("Mike Lavender");
1263 MODULE_DESCRIPTION("framework for SPI NOR");