2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/mutex.h>
18 #include <linux/math64.h>
20 #include <linux/mtd/cfi.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/of_platform.h>
23 #include <linux/spi/flash.h>
24 #include <linux/mtd/spi-nor.h>
26 /* Define max times to check status register before we give up. */
27 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
29 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
32 * Read the status register, returning its value in the location
33 * Return the status register value.
34 * Returns negative if error occurred.
36 static int read_sr(struct spi_nor *nor)
41 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
43 pr_err("error %d reading SR\n", (int) ret);
51 * Read the flag status register, returning its value in the location
52 * Return the status register value.
53 * Returns negative if error occurred.
55 static int read_fsr(struct spi_nor *nor)
60 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
62 pr_err("error %d reading FSR\n", ret);
70 * Read configuration register, returning its value in the
71 * location. Return the configuration register value.
72 * Returns negative if error occured.
74 static int read_cr(struct spi_nor *nor)
79 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
81 dev_err(nor->dev, "error %d reading CR\n", ret);
89 * Dummy Cycle calculation for different type of read.
90 * It can be used to support more commands with
91 * different dummy cycle requirements.
93 static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
95 switch (nor->flash_read) {
107 * Write status register 1 byte
108 * Returns negative if error occurred.
110 static inline int write_sr(struct spi_nor *nor, u8 val)
112 nor->cmd_buf[0] = val;
113 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
117 * Set write enable latch with Write Enable command.
118 * Returns negative if error occurred.
120 static inline int write_enable(struct spi_nor *nor)
122 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
126 * Send write disble instruction to the chip.
128 static inline int write_disable(struct spi_nor *nor)
130 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
133 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
138 /* Enable/disable 4-byte addressing mode. */
139 static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
142 bool need_wren = false;
145 switch (JEDEC_MFR(jedec_id)) {
146 case CFI_MFR_ST: /* Micron, actually */
147 /* Some Micron need WREN command; all will accept it */
149 case CFI_MFR_MACRONIX:
150 case 0xEF /* winbond */:
154 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
155 status = nor->write_reg(nor, cmd, NULL, 0, 0);
162 nor->cmd_buf[0] = enable << 7;
163 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
167 static int spi_nor_wait_till_ready(struct spi_nor *nor)
169 unsigned long deadline;
172 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
180 else if (!(sr & SR_WIP))
182 } while (!time_after_eq(jiffies, deadline));
187 static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
189 unsigned long deadline;
193 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
201 } else if (!(sr & SR_WIP)) {
208 } while (!time_after_eq(jiffies, deadline));
214 * Service routine to read status register until ready, or timeout occurs.
215 * Returns non-zero if error.
217 static int wait_till_ready(struct spi_nor *nor)
219 return nor->wait_till_ready(nor);
223 * Erase the whole flash memory
225 * Returns 0 if successful, non-zero otherwise.
227 static int erase_chip(struct spi_nor *nor)
231 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
233 /* Wait until finished previous write command. */
234 ret = wait_till_ready(nor);
238 /* Send write enable, then erase commands. */
241 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
244 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
248 mutex_lock(&nor->lock);
251 ret = nor->prepare(nor, ops);
253 dev_err(nor->dev, "failed in the preparation.\n");
254 mutex_unlock(&nor->lock);
261 static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
264 nor->unprepare(nor, ops);
265 mutex_unlock(&nor->lock);
269 * Erase an address range on the nor chip. The address range may extend
270 * one or more erase sectors. Return an error is there is a problem erasing.
272 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
274 struct spi_nor *nor = mtd_to_spi_nor(mtd);
279 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
280 (long long)instr->len);
282 div_u64_rem(instr->len, mtd->erasesize, &rem);
289 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
293 /* whole-chip erase? */
294 if (len == mtd->size) {
295 if (erase_chip(nor)) {
300 /* REVISIT in some cases we could speed up erasing large regions
301 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
302 * to use "small sector erase", but that's not always optimal.
305 /* "sector"-at-a-time erase */
308 if (nor->erase(nor, addr)) {
313 addr += mtd->erasesize;
314 len -= mtd->erasesize;
318 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
320 instr->state = MTD_ERASE_DONE;
321 mtd_erase_callback(instr);
326 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
327 instr->state = MTD_ERASE_FAILED;
331 static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
333 struct spi_nor *nor = mtd_to_spi_nor(mtd);
334 uint32_t offset = ofs;
335 uint8_t status_old, status_new;
338 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
342 /* Wait until finished previous command */
343 ret = wait_till_ready(nor);
347 status_old = read_sr(nor);
349 if (offset < mtd->size - (mtd->size / 2))
350 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
351 else if (offset < mtd->size - (mtd->size / 4))
352 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
353 else if (offset < mtd->size - (mtd->size / 8))
354 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
355 else if (offset < mtd->size - (mtd->size / 16))
356 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
357 else if (offset < mtd->size - (mtd->size / 32))
358 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
359 else if (offset < mtd->size - (mtd->size / 64))
360 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
362 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
364 /* Only modify protection if it will not unlock other areas */
365 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
366 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
368 ret = write_sr(nor, status_new);
374 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
378 static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
380 struct spi_nor *nor = mtd_to_spi_nor(mtd);
381 uint32_t offset = ofs;
382 uint8_t status_old, status_new;
385 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
389 /* Wait until finished previous command */
390 ret = wait_till_ready(nor);
394 status_old = read_sr(nor);
396 if (offset+len > mtd->size - (mtd->size / 64))
397 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
398 else if (offset+len > mtd->size - (mtd->size / 32))
399 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
400 else if (offset+len > mtd->size - (mtd->size / 16))
401 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
402 else if (offset+len > mtd->size - (mtd->size / 8))
403 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
404 else if (offset+len > mtd->size - (mtd->size / 4))
405 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
406 else if (offset+len > mtd->size - (mtd->size / 2))
407 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
409 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
411 /* Only modify protection if it will not lock other areas */
412 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
413 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
415 ret = write_sr(nor, status_new);
421 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
426 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
427 * a high byte of zero plus three data bytes: the manufacturer id,
428 * then a two byte device id.
433 /* The size listed here is what works with SPINOR_OP_SE, which isn't
434 * necessarily called a "sector" by the vendor.
436 unsigned sector_size;
443 #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
444 #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
445 #define SST_WRITE 0x04 /* use SST byte programming */
446 #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
447 #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
448 #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
449 #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
450 #define USE_FSR 0x80 /* use flag status register */
453 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
454 ((kernel_ulong_t)&(struct flash_info) { \
455 .jedec_id = (_jedec_id), \
456 .ext_id = (_ext_id), \
457 .sector_size = (_sector_size), \
458 .n_sectors = (_n_sectors), \
463 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
464 ((kernel_ulong_t)&(struct flash_info) { \
465 .sector_size = (_sector_size), \
466 .n_sectors = (_n_sectors), \
467 .page_size = (_page_size), \
468 .addr_width = (_addr_width), \
472 /* NOTE: double check command sets and memory organization when you add
473 * more nor chips. This current list focusses on newer chips, which
474 * have been converging on command sets which including JEDEC ID.
476 const struct spi_device_id spi_nor_ids[] = {
477 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
478 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
479 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
481 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
482 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
483 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
485 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
486 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
487 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
488 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
490 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
493 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
494 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
495 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
496 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
497 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
498 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
499 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
502 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
505 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
506 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
509 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
510 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
512 /* Intel/Numonyx -- xxxs33b */
513 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
514 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
515 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
518 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
519 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
520 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
521 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
522 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
523 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
524 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
525 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
526 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
527 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
528 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
529 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
530 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
533 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
534 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
535 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
536 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
537 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
538 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
539 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
542 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
543 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
544 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
546 /* Spansion -- single (large) sector size only, at least
547 * for the chips listed here (without boot sectors).
549 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
550 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
551 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
552 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
553 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
554 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
555 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
556 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
557 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
558 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
559 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
560 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
561 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
562 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
563 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
564 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
565 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
566 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
568 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
569 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
570 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
571 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
572 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
573 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
574 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
575 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
576 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
577 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
579 /* ST Microelectronics -- newer production may have feature updates */
580 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
581 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
582 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
583 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
584 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
585 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
586 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
587 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
588 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
589 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
591 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
592 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
593 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
594 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
595 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
596 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
597 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
598 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
599 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
601 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
602 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
603 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
605 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
606 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
607 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
609 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
610 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
611 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
612 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
613 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
615 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
616 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
617 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
618 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
619 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
620 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
621 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
622 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
623 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
624 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
625 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
626 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
627 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
628 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
629 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
630 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
632 /* Catalyst / On Semiconductor -- non-JEDEC */
633 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
634 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
635 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
636 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
637 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
640 EXPORT_SYMBOL_GPL(spi_nor_ids);
642 static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
648 struct flash_info *info;
650 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
652 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
661 ext_jedec = id[3] << 8 | id[4];
663 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
664 info = (void *)spi_nor_ids[tmp].driver_data;
665 if (info->jedec_id == jedec) {
666 if (info->ext_id == 0 || info->ext_id == ext_jedec)
667 return &spi_nor_ids[tmp];
670 dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
671 return ERR_PTR(-ENODEV);
674 static const struct spi_device_id *jedec_probe(struct spi_nor *nor)
676 return nor->read_id(nor);
679 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
680 size_t *retlen, u_char *buf)
682 struct spi_nor *nor = mtd_to_spi_nor(mtd);
685 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
687 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
691 ret = nor->read(nor, from, len, retlen, buf);
693 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
697 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
698 size_t *retlen, const u_char *buf)
700 struct spi_nor *nor = mtd_to_spi_nor(mtd);
704 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
706 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
710 /* Wait until finished previous write command. */
711 ret = wait_till_ready(nor);
717 nor->sst_write_second = false;
720 /* Start write from odd address. */
722 nor->program_opcode = SPINOR_OP_BP;
724 /* write one byte. */
725 nor->write(nor, to, 1, retlen, buf);
726 ret = wait_till_ready(nor);
732 /* Write out most of the data here. */
733 for (; actual < len - 1; actual += 2) {
734 nor->program_opcode = SPINOR_OP_AAI_WP;
736 /* write two bytes. */
737 nor->write(nor, to, 2, retlen, buf + actual);
738 ret = wait_till_ready(nor);
742 nor->sst_write_second = true;
744 nor->sst_write_second = false;
747 ret = wait_till_ready(nor);
751 /* Write out trailing byte if it exists. */
755 nor->program_opcode = SPINOR_OP_BP;
756 nor->write(nor, to, 1, retlen, buf + actual);
758 ret = wait_till_ready(nor);
764 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
769 * Write an address range to the nor chip. Data must be written in
770 * FLASH_PAGESIZE chunks. The address range may be any size provided
771 * it is within the physical boundaries.
773 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
774 size_t *retlen, const u_char *buf)
776 struct spi_nor *nor = mtd_to_spi_nor(mtd);
777 u32 page_offset, page_size, i;
780 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
782 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
786 /* Wait until finished previous write command. */
787 ret = wait_till_ready(nor);
793 page_offset = to & (nor->page_size - 1);
795 /* do all the bytes fit onto one page? */
796 if (page_offset + len <= nor->page_size) {
797 nor->write(nor, to, len, retlen, buf);
799 /* the size of data remaining on the first page */
800 page_size = nor->page_size - page_offset;
801 nor->write(nor, to, page_size, retlen, buf);
803 /* write everything in nor->page_size chunks */
804 for (i = page_size; i < len; i += page_size) {
806 if (page_size > nor->page_size)
807 page_size = nor->page_size;
809 wait_till_ready(nor);
812 nor->write(nor, to + i, page_size, retlen, buf + i);
817 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
821 static int macronix_quad_enable(struct spi_nor *nor)
828 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
829 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
831 if (wait_till_ready(nor))
835 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
836 dev_err(nor->dev, "Macronix Quad bit not set\n");
844 * Write status Register and configuration register with 2 bytes
845 * The first byte will be written to the status register, while the
846 * second byte will be written to the configuration register.
847 * Return negative if error occured.
849 static int write_sr_cr(struct spi_nor *nor, u16 val)
851 nor->cmd_buf[0] = val & 0xff;
852 nor->cmd_buf[1] = (val >> 8);
854 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
857 static int spansion_quad_enable(struct spi_nor *nor)
860 int quad_en = CR_QUAD_EN_SPAN << 8;
864 ret = write_sr_cr(nor, quad_en);
867 "error while writing configuration register\n");
871 /* read back and check it */
873 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
874 dev_err(nor->dev, "Spansion Quad bit not set\n");
881 static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
885 switch (JEDEC_MFR(jedec_id)) {
886 case CFI_MFR_MACRONIX:
887 status = macronix_quad_enable(nor);
889 dev_err(nor->dev, "Macronix quad-read not enabled\n");
894 status = spansion_quad_enable(nor);
896 dev_err(nor->dev, "Spansion quad-read not enabled\n");
903 static int spi_nor_check(struct spi_nor *nor)
905 if (!nor->dev || !nor->read || !nor->write ||
906 !nor->read_reg || !nor->write_reg || !nor->erase) {
907 pr_err("spi-nor: please fill all the necessary fields!\n");
912 nor->read_id = spi_nor_read_id;
913 if (!nor->wait_till_ready)
914 nor->wait_till_ready = spi_nor_wait_till_ready;
919 int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
922 struct flash_info *info;
923 struct flash_platform_data *data;
924 struct device *dev = nor->dev;
925 struct mtd_info *mtd = nor->mtd;
926 struct device_node *np = dev->of_node;
930 ret = spi_nor_check(nor);
934 /* Platform data helps sort out which chip type we have, as
935 * well as how this board partitions it. If we don't have
936 * a chip ID, try the JEDEC id commands; they'll work for most
937 * newer chips, even if we don't recognize the particular chip.
939 data = dev_get_platdata(dev);
940 if (data && data->type) {
941 const struct spi_device_id *plat_id;
943 for (i = 0; i < ARRAY_SIZE(spi_nor_ids) - 1; i++) {
944 plat_id = &spi_nor_ids[i];
945 if (strcmp(data->type, plat_id->name))
950 if (i < ARRAY_SIZE(spi_nor_ids) - 1)
953 dev_warn(dev, "unrecognized id %s\n", data->type);
956 info = (void *)id->driver_data;
958 if (info->jedec_id) {
959 const struct spi_device_id *jid;
961 jid = jedec_probe(nor);
964 } else if (jid != id) {
966 * JEDEC knows better, so overwrite platform ID. We
967 * can't trust partitions any longer, but we'll let
968 * mtd apply them anyway, since some partitions may be
969 * marked read-only, and we don't want to lose that
970 * information, even if it's not 100% accurate.
972 dev_warn(dev, "found %s, expected %s\n",
973 jid->name, id->name);
975 info = (void *)jid->driver_data;
979 mutex_init(&nor->lock);
982 * Atmel, SST and Intel/Numonyx serial nor tend to power
983 * up with the software protection bits set
986 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
987 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
988 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
993 if (data && data->name)
994 mtd->name = data->name;
996 mtd->name = dev_name(dev);
998 mtd->type = MTD_NORFLASH;
1000 mtd->flags = MTD_CAP_NORFLASH;
1001 mtd->size = info->sector_size * info->n_sectors;
1002 mtd->_erase = spi_nor_erase;
1003 mtd->_read = spi_nor_read;
1005 /* nor protection support for STmicro chips */
1006 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1007 mtd->_lock = spi_nor_lock;
1008 mtd->_unlock = spi_nor_unlock;
1011 /* sst nor chips use AAI word program */
1012 if (info->flags & SST_WRITE)
1013 mtd->_write = sst_write;
1015 mtd->_write = spi_nor_write;
1017 if ((info->flags & USE_FSR) &&
1018 nor->wait_till_ready == spi_nor_wait_till_ready)
1019 nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
1021 /* prefer "small sector" erase if possible */
1022 if (info->flags & SECT_4K) {
1023 nor->erase_opcode = SPINOR_OP_BE_4K;
1024 mtd->erasesize = 4096;
1025 } else if (info->flags & SECT_4K_PMC) {
1026 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
1027 mtd->erasesize = 4096;
1029 nor->erase_opcode = SPINOR_OP_SE;
1030 mtd->erasesize = info->sector_size;
1033 if (info->flags & SPI_NOR_NO_ERASE)
1034 mtd->flags |= MTD_NO_ERASE;
1036 mtd->dev.parent = dev;
1037 nor->page_size = info->page_size;
1038 mtd->writebufsize = nor->page_size;
1041 /* If we were instantiated by DT, use it */
1042 if (of_property_read_bool(np, "m25p,fast-read"))
1043 nor->flash_read = SPI_NOR_FAST;
1045 nor->flash_read = SPI_NOR_NORMAL;
1047 /* If we weren't instantiated by DT, default to fast-read */
1048 nor->flash_read = SPI_NOR_FAST;
1051 /* Some devices cannot do fast-read, no matter what DT tells us */
1052 if (info->flags & SPI_NOR_NO_FR)
1053 nor->flash_read = SPI_NOR_NORMAL;
1055 /* Quad/Dual-read mode takes precedence over fast/normal */
1056 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1057 ret = set_quad_mode(nor, info->jedec_id);
1059 dev_err(dev, "quad mode not supported\n");
1062 nor->flash_read = SPI_NOR_QUAD;
1063 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1064 nor->flash_read = SPI_NOR_DUAL;
1067 /* Default commands */
1068 switch (nor->flash_read) {
1070 nor->read_opcode = SPINOR_OP_READ_1_1_4;
1073 nor->read_opcode = SPINOR_OP_READ_1_1_2;
1076 nor->read_opcode = SPINOR_OP_READ_FAST;
1078 case SPI_NOR_NORMAL:
1079 nor->read_opcode = SPINOR_OP_READ;
1082 dev_err(dev, "No Read opcode defined\n");
1086 nor->program_opcode = SPINOR_OP_PP;
1088 if (info->addr_width)
1089 nor->addr_width = info->addr_width;
1090 else if (mtd->size > 0x1000000) {
1091 /* enable 4-byte addressing if the device exceeds 16MiB */
1092 nor->addr_width = 4;
1093 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1094 /* Dedicated 4-byte command set */
1095 switch (nor->flash_read) {
1097 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
1100 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
1103 nor->read_opcode = SPINOR_OP_READ4_FAST;
1105 case SPI_NOR_NORMAL:
1106 nor->read_opcode = SPINOR_OP_READ4;
1109 nor->program_opcode = SPINOR_OP_PP_4B;
1110 /* No small sector erase for 4-byte command set */
1111 nor->erase_opcode = SPINOR_OP_SE_4B;
1112 mtd->erasesize = info->sector_size;
1114 set_4byte(nor, info->jedec_id, 1);
1116 nor->addr_width = 3;
1119 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1121 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1122 (long long)mtd->size >> 10);
1125 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1126 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1127 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1128 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1130 if (mtd->numeraseregions)
1131 for (i = 0; i < mtd->numeraseregions; i++)
1133 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1134 ".erasesize = 0x%.8x (%uKiB), "
1135 ".numblocks = %d }\n",
1136 i, (long long)mtd->eraseregions[i].offset,
1137 mtd->eraseregions[i].erasesize,
1138 mtd->eraseregions[i].erasesize / 1024,
1139 mtd->eraseregions[i].numblocks);
1142 EXPORT_SYMBOL_GPL(spi_nor_scan);
1144 const struct spi_device_id *spi_nor_match_id(char *name)
1146 const struct spi_device_id *id = spi_nor_ids;
1148 while (id->name[0]) {
1149 if (!strcmp(name, id->name))
1155 EXPORT_SYMBOL_GPL(spi_nor_match_id);
1157 MODULE_LICENSE("GPL");
1158 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1159 MODULE_AUTHOR("Mike Lavender");
1160 MODULE_DESCRIPTION("framework for SPI NOR");