1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
79 #include <asm/uaccess.h>
81 /* VLAN tagging feature enable/disable */
82 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
83 #define CP_VLAN_TAG_USED 1
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
87 #define CP_VLAN_TAG_USED 0
88 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
89 do { (tx_desc)->opts2 = 0; } while (0)
92 /* These identify the driver base version and may not be removed. */
93 static char version[] =
94 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
96 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
97 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
98 MODULE_VERSION(DRV_VERSION);
99 MODULE_LICENSE("GPL");
101 static int debug = -1;
102 module_param(debug, int, 0);
103 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
105 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
106 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
107 static int multicast_filter_limit = 32;
108 module_param(multicast_filter_limit, int, 0);
109 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
111 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
114 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
115 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
116 #define CP_REGS_SIZE (0xff + 1)
117 #define CP_REGS_VER 1 /* version 1 */
118 #define CP_RX_RING_SIZE 64
119 #define CP_TX_RING_SIZE 64
120 #define CP_RING_BYTES \
121 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
122 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
124 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
125 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
126 #define TX_BUFFS_AVAIL(CP) \
127 (((CP)->tx_tail <= (CP)->tx_head) ? \
128 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
129 (CP)->tx_tail - (CP)->tx_head - 1)
131 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
132 #define CP_INTERNAL_PHY 32
134 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
135 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
136 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
137 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
138 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
140 /* Time in jiffies before concluding the transmitter is hung. */
141 #define TX_TIMEOUT (6*HZ)
143 /* hardware minimum and maximum for a single frame's data payload */
144 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
145 #define CP_MAX_MTU 4096
148 /* NIC register offsets */
149 MAC0 = 0x00, /* Ethernet hardware address. */
150 MAR0 = 0x08, /* Multicast filter. */
151 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
152 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
153 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
154 Cmd = 0x37, /* Command register */
155 IntrMask = 0x3C, /* Interrupt mask */
156 IntrStatus = 0x3E, /* Interrupt status */
157 TxConfig = 0x40, /* Tx configuration */
158 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
159 RxConfig = 0x44, /* Rx configuration */
160 RxMissed = 0x4C, /* 24 bits valid, write clears */
161 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
162 Config1 = 0x52, /* Config1 */
163 Config3 = 0x59, /* Config3 */
164 Config4 = 0x5A, /* Config4 */
165 MultiIntr = 0x5C, /* Multiple interrupt select */
166 BasicModeCtrl = 0x62, /* MII BMCR */
167 BasicModeStatus = 0x64, /* MII BMSR */
168 NWayAdvert = 0x66, /* MII ADVERTISE */
169 NWayLPAR = 0x68, /* MII LPA */
170 NWayExpansion = 0x6A, /* MII Expansion */
171 Config5 = 0xD8, /* Config5 */
172 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
173 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
174 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
175 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
176 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
177 TxThresh = 0xEC, /* Early Tx threshold */
178 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
179 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
181 /* Tx and Rx status descriptors */
182 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
183 RingEnd = (1 << 30), /* End of descriptor ring */
184 FirstFrag = (1 << 29), /* First segment of a packet */
185 LastFrag = (1 << 28), /* Final segment of a packet */
186 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
187 MSSShift = 16, /* MSS value position */
188 MSSMask = 0xfff, /* MSS value: 11 bits */
189 TxError = (1 << 23), /* Tx error summary */
190 RxError = (1 << 20), /* Rx error summary */
191 IPCS = (1 << 18), /* Calculate IP checksum */
192 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
193 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
194 TxVlanTag = (1 << 17), /* Add VLAN tag */
195 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
196 IPFail = (1 << 15), /* IP checksum failed */
197 UDPFail = (1 << 14), /* UDP/IP checksum failed */
198 TCPFail = (1 << 13), /* TCP/IP checksum failed */
199 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
200 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
201 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
205 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
206 TxOWC = (1 << 22), /* Tx Out-of-window collision */
207 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
208 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
209 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
210 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
211 RxErrFrame = (1 << 27), /* Rx frame alignment error */
212 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
213 RxErrCRC = (1 << 18), /* Rx CRC error */
214 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
215 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
216 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
218 /* StatsAddr register */
219 DumpStats = (1 << 3), /* Begin stats dump */
221 /* RxConfig register */
222 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
223 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
224 AcceptErr = 0x20, /* Accept packets with CRC errors */
225 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
226 AcceptBroadcast = 0x08, /* Accept broadcast packets */
227 AcceptMulticast = 0x04, /* Accept multicast packets */
228 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
229 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
231 /* IntrMask / IntrStatus registers */
232 PciErr = (1 << 15), /* System error on the PCI bus */
233 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
234 LenChg = (1 << 13), /* Cable length change */
235 SWInt = (1 << 8), /* Software-requested interrupt */
236 TxEmpty = (1 << 7), /* No Tx descriptors available */
237 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
238 LinkChg = (1 << 5), /* Packet underrun, or link change */
239 RxEmpty = (1 << 4), /* No Rx descriptors available */
240 TxErr = (1 << 3), /* Tx error */
241 TxOK = (1 << 2), /* Tx packet sent */
242 RxErr = (1 << 1), /* Rx error */
243 RxOK = (1 << 0), /* Rx packet received */
244 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
245 but hardware likes to raise it */
247 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
248 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
249 RxErr | RxOK | IntrResvd,
251 /* C mode command register */
252 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
253 RxOn = (1 << 3), /* Rx mode enable */
254 TxOn = (1 << 2), /* Tx mode enable */
256 /* C+ mode command register */
257 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
258 RxChkSum = (1 << 5), /* Rx checksum offload enable */
259 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
260 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
261 CpRxOn = (1 << 1), /* Rx mode enable */
262 CpTxOn = (1 << 0), /* Tx mode enable */
264 /* Cfg9436 EEPROM control register */
265 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
266 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
268 /* TxConfig register */
269 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
270 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
272 /* Early Tx Threshold register */
273 TxThreshMask = 0x3f, /* Mask bits 5-0 */
274 TxThreshMax = 2048, /* Max early Tx threshold */
276 /* Config1 register */
277 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
278 LWACT = (1 << 4), /* LWAKE active mode */
279 PMEnable = (1 << 0), /* Enable various PM features of chip */
281 /* Config3 register */
282 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
283 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
284 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
286 /* Config4 register */
287 LWPTN = (1 << 1), /* LWAKE Pattern */
288 LWPME = (1 << 4), /* LANWAKE vs PMEB */
290 /* Config5 register */
291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LANWake = (1 << 1), /* Enable LANWake signal */
295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
297 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
298 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
299 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
302 static const unsigned int cp_rx_config =
303 (RX_FIFO_THRESH << RxCfgFIFOShift) |
304 (RX_DMA_BURST << RxCfgDMAShift);
312 struct cp_dma_stats {
328 struct cp_extra_stats {
329 unsigned long rx_frags;
334 struct net_device *dev;
338 struct napi_struct napi;
340 struct pci_dev *pdev;
344 struct cp_extra_stats cp_stats;
346 unsigned rx_head ____cacheline_aligned;
348 struct cp_desc *rx_ring;
349 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
351 unsigned tx_head ____cacheline_aligned;
353 struct cp_desc *tx_ring;
354 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
357 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
360 struct vlan_group *vlgrp;
364 struct mii_if_info mii_if;
367 #define cpr8(reg) readb(cp->regs + (reg))
368 #define cpr16(reg) readw(cp->regs + (reg))
369 #define cpr32(reg) readl(cp->regs + (reg))
370 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
371 #define cpw16(reg,val) writew((val), cp->regs + (reg))
372 #define cpw32(reg,val) writel((val), cp->regs + (reg))
373 #define cpw8_f(reg,val) do { \
374 writeb((val), cp->regs + (reg)); \
375 readb(cp->regs + (reg)); \
377 #define cpw16_f(reg,val) do { \
378 writew((val), cp->regs + (reg)); \
379 readw(cp->regs + (reg)); \
381 #define cpw32_f(reg,val) do { \
382 writel((val), cp->regs + (reg)); \
383 readl(cp->regs + (reg)); \
387 static void __cp_set_rx_mode (struct net_device *dev);
388 static void cp_tx (struct cp_private *cp);
389 static void cp_clean_rings (struct cp_private *cp);
390 #ifdef CONFIG_NET_POLL_CONTROLLER
391 static void cp_poll_controller(struct net_device *dev);
393 static int cp_get_eeprom_len(struct net_device *dev);
394 static int cp_get_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396 static int cp_set_eeprom(struct net_device *dev,
397 struct ethtool_eeprom *eeprom, u8 *data);
399 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
400 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
401 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
404 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
407 const char str[ETH_GSTRING_LEN];
408 } ethtool_stats_keys[] = {
427 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
429 struct cp_private *cp = netdev_priv(dev);
432 spin_lock_irqsave(&cp->lock, flags);
435 cp->cpcmd |= RxVlanOn;
437 cp->cpcmd &= ~RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
442 #endif /* CP_VLAN_TAG_USED */
444 static inline void cp_set_rxbufsize (struct cp_private *cp)
446 unsigned int mtu = cp->dev->mtu;
448 if (mtu > ETH_DATA_LEN)
449 /* MTU + ethernet header + FCS + optional VLAN tag */
450 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
452 cp->rx_buf_sz = PKT_BUF_SZ;
455 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
456 struct cp_desc *desc)
458 skb->protocol = eth_type_trans (skb, cp->dev);
460 cp->dev->stats.rx_packets++;
461 cp->dev->stats.rx_bytes += skb->len;
464 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
465 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
466 swab16(le32_to_cpu(desc->opts2) & 0xffff));
469 netif_receive_skb(skb);
472 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
475 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
476 rx_tail, status, len);
477 cp->dev->stats.rx_errors++;
478 if (status & RxErrFrame)
479 cp->dev->stats.rx_frame_errors++;
480 if (status & RxErrCRC)
481 cp->dev->stats.rx_crc_errors++;
482 if ((status & RxErrRunt) || (status & RxErrLong))
483 cp->dev->stats.rx_length_errors++;
484 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
485 cp->dev->stats.rx_length_errors++;
486 if (status & RxErrFIFO)
487 cp->dev->stats.rx_fifo_errors++;
490 static inline unsigned int cp_rx_csum_ok (u32 status)
492 unsigned int protocol = (status >> 16) & 0x3;
494 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
495 ((protocol == RxProtoUDP) && !(status & UDPFail)))
501 static int cp_rx_poll(struct napi_struct *napi, int budget)
503 struct cp_private *cp = container_of(napi, struct cp_private, napi);
504 struct net_device *dev = cp->dev;
505 unsigned int rx_tail = cp->rx_tail;
510 cpw16(IntrStatus, cp_rx_intr_mask);
515 struct sk_buff *skb, *new_skb;
516 struct cp_desc *desc;
517 const unsigned buflen = cp->rx_buf_sz;
519 skb = cp->rx_skb[rx_tail];
522 desc = &cp->rx_ring[rx_tail];
523 status = le32_to_cpu(desc->opts1);
524 if (status & DescOwn)
527 len = (status & 0x1fff) - 4;
528 mapping = le64_to_cpu(desc->addr);
530 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
531 /* we don't support incoming fragmented frames.
532 * instead, we attempt to ensure that the
533 * pre-allocated RX skbs are properly sized such
534 * that RX fragments are never encountered
536 cp_rx_err_acct(cp, rx_tail, status, len);
537 dev->stats.rx_dropped++;
538 cp->cp_stats.rx_frags++;
542 if (status & (RxError | RxErrFIFO)) {
543 cp_rx_err_acct(cp, rx_tail, status, len);
547 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
548 rx_tail, status, len);
550 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
552 dev->stats.rx_dropped++;
556 dma_unmap_single(&cp->pdev->dev, mapping,
557 buflen, PCI_DMA_FROMDEVICE);
559 /* Handle checksum offloading for incoming packets. */
560 if (cp_rx_csum_ok(status))
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
563 skb_checksum_none_assert(skb);
567 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
569 cp->rx_skb[rx_tail] = new_skb;
571 cp_rx_skb(cp, skb, desc);
575 cp->rx_ring[rx_tail].opts2 = 0;
576 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
577 if (rx_tail == (CP_RX_RING_SIZE - 1))
578 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
581 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
582 rx_tail = NEXT_RX(rx_tail);
588 cp->rx_tail = rx_tail;
590 /* if we did not reach work limit, then we're done with
591 * this round of polling
596 if (cpr16(IntrStatus) & cp_rx_intr_mask)
599 spin_lock_irqsave(&cp->lock, flags);
600 __napi_complete(napi);
601 cpw16_f(IntrMask, cp_intr_mask);
602 spin_unlock_irqrestore(&cp->lock, flags);
608 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
610 struct net_device *dev = dev_instance;
611 struct cp_private *cp;
614 if (unlikely(dev == NULL))
616 cp = netdev_priv(dev);
618 status = cpr16(IntrStatus);
619 if (!status || (status == 0xFFFF))
622 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
623 status, cpr8(Cmd), cpr16(CpCmd));
625 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
627 spin_lock(&cp->lock);
629 /* close possible race's with dev_close */
630 if (unlikely(!netif_running(dev))) {
632 spin_unlock(&cp->lock);
636 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
637 if (napi_schedule_prep(&cp->napi)) {
638 cpw16_f(IntrMask, cp_norx_intr_mask);
639 __napi_schedule(&cp->napi);
642 if (status & (TxOK | TxErr | TxEmpty | SWInt))
644 if (status & LinkChg)
645 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
647 spin_unlock(&cp->lock);
649 if (status & PciErr) {
652 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
653 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
654 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
657 /* TODO: reset hardware */
663 #ifdef CONFIG_NET_POLL_CONTROLLER
665 * Polling receive - used by netconsole and other diagnostic tools
666 * to allow network i/o with interrupts disabled.
668 static void cp_poll_controller(struct net_device *dev)
670 disable_irq(dev->irq);
671 cp_interrupt(dev->irq, dev);
672 enable_irq(dev->irq);
676 static void cp_tx (struct cp_private *cp)
678 unsigned tx_head = cp->tx_head;
679 unsigned tx_tail = cp->tx_tail;
681 while (tx_tail != tx_head) {
682 struct cp_desc *txd = cp->tx_ring + tx_tail;
687 status = le32_to_cpu(txd->opts1);
688 if (status & DescOwn)
691 skb = cp->tx_skb[tx_tail];
694 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
695 le32_to_cpu(txd->opts1) & 0xffff,
698 if (status & LastFrag) {
699 if (status & (TxError | TxFIFOUnder)) {
700 netif_dbg(cp, tx_err, cp->dev,
701 "tx err, status 0x%x\n", status);
702 cp->dev->stats.tx_errors++;
704 cp->dev->stats.tx_window_errors++;
705 if (status & TxMaxCol)
706 cp->dev->stats.tx_aborted_errors++;
707 if (status & TxLinkFail)
708 cp->dev->stats.tx_carrier_errors++;
709 if (status & TxFIFOUnder)
710 cp->dev->stats.tx_fifo_errors++;
712 cp->dev->stats.collisions +=
713 ((status >> TxColCntShift) & TxColCntMask);
714 cp->dev->stats.tx_packets++;
715 cp->dev->stats.tx_bytes += skb->len;
716 netif_dbg(cp, tx_done, cp->dev,
717 "tx done, slot %d\n", tx_tail);
719 dev_kfree_skb_irq(skb);
722 cp->tx_skb[tx_tail] = NULL;
724 tx_tail = NEXT_TX(tx_tail);
727 cp->tx_tail = tx_tail;
729 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
730 netif_wake_queue(cp->dev);
733 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
734 struct net_device *dev)
736 struct cp_private *cp = netdev_priv(dev);
739 unsigned long intr_flags;
745 spin_lock_irqsave(&cp->lock, intr_flags);
747 /* This is a hard error, log it. */
748 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
749 netif_stop_queue(dev);
750 spin_unlock_irqrestore(&cp->lock, intr_flags);
751 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
752 return NETDEV_TX_BUSY;
756 if (vlan_tx_tag_present(skb))
757 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
761 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
762 mss = skb_shinfo(skb)->gso_size;
764 if (skb_shinfo(skb)->nr_frags == 0) {
765 struct cp_desc *txd = &cp->tx_ring[entry];
770 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
771 CP_VLAN_TX_TAG(txd, vlan_tag);
772 txd->addr = cpu_to_le64(mapping);
775 flags = eor | len | DescOwn | FirstFrag | LastFrag;
778 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
779 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
780 const struct iphdr *ip = ip_hdr(skb);
781 if (ip->protocol == IPPROTO_TCP)
782 flags |= IPCS | TCPCS;
783 else if (ip->protocol == IPPROTO_UDP)
784 flags |= IPCS | UDPCS;
786 WARN_ON(1); /* we need a WARN() */
789 txd->opts1 = cpu_to_le32(flags);
792 cp->tx_skb[entry] = skb;
793 entry = NEXT_TX(entry);
796 u32 first_len, first_eor;
797 dma_addr_t first_mapping;
798 int frag, first_entry = entry;
799 const struct iphdr *ip = ip_hdr(skb);
801 /* We must give this initial chunk to the device last.
802 * Otherwise we could race with the device.
805 first_len = skb_headlen(skb);
806 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
807 first_len, PCI_DMA_TODEVICE);
808 cp->tx_skb[entry] = skb;
809 entry = NEXT_TX(entry);
811 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
812 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
817 len = this_frag->size;
818 mapping = dma_map_single(&cp->pdev->dev,
819 ((void *) page_address(this_frag->page) +
820 this_frag->page_offset),
821 len, PCI_DMA_TODEVICE);
822 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
824 ctrl = eor | len | DescOwn;
828 ((mss & MSSMask) << MSSShift);
829 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
830 if (ip->protocol == IPPROTO_TCP)
831 ctrl |= IPCS | TCPCS;
832 else if (ip->protocol == IPPROTO_UDP)
833 ctrl |= IPCS | UDPCS;
838 if (frag == skb_shinfo(skb)->nr_frags - 1)
841 txd = &cp->tx_ring[entry];
842 CP_VLAN_TX_TAG(txd, vlan_tag);
843 txd->addr = cpu_to_le64(mapping);
846 txd->opts1 = cpu_to_le32(ctrl);
849 cp->tx_skb[entry] = skb;
850 entry = NEXT_TX(entry);
853 txd = &cp->tx_ring[first_entry];
854 CP_VLAN_TX_TAG(txd, vlan_tag);
855 txd->addr = cpu_to_le64(first_mapping);
858 if (skb->ip_summed == CHECKSUM_PARTIAL) {
859 if (ip->protocol == IPPROTO_TCP)
860 txd->opts1 = cpu_to_le32(first_eor | first_len |
861 FirstFrag | DescOwn |
863 else if (ip->protocol == IPPROTO_UDP)
864 txd->opts1 = cpu_to_le32(first_eor | first_len |
865 FirstFrag | DescOwn |
870 txd->opts1 = cpu_to_le32(first_eor | first_len |
871 FirstFrag | DescOwn);
875 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
877 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
878 netif_stop_queue(dev);
880 spin_unlock_irqrestore(&cp->lock, intr_flags);
882 cpw8(TxPoll, NormalTxPoll);
887 /* Set or clear the multicast filter for this adaptor.
888 This routine is not state sensitive and need not be SMP locked. */
890 static void __cp_set_rx_mode (struct net_device *dev)
892 struct cp_private *cp = netdev_priv(dev);
893 u32 mc_filter[2]; /* Multicast hash filter */
897 /* Note: do not reorder, GCC is clever about common statements. */
898 if (dev->flags & IFF_PROMISC) {
899 /* Unconditionally log net taps. */
901 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
903 mc_filter[1] = mc_filter[0] = 0xffffffff;
904 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
905 (dev->flags & IFF_ALLMULTI)) {
906 /* Too many to filter perfectly -- accept all multicasts. */
907 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
908 mc_filter[1] = mc_filter[0] = 0xffffffff;
910 struct netdev_hw_addr *ha;
911 rx_mode = AcceptBroadcast | AcceptMyPhys;
912 mc_filter[1] = mc_filter[0] = 0;
913 netdev_for_each_mc_addr(ha, dev) {
914 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
916 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
917 rx_mode |= AcceptMulticast;
921 /* We can safely update without stopping the chip. */
922 tmp = cp_rx_config | rx_mode;
923 if (cp->rx_config != tmp) {
924 cpw32_f (RxConfig, tmp);
927 cpw32_f (MAR0 + 0, mc_filter[0]);
928 cpw32_f (MAR0 + 4, mc_filter[1]);
931 static void cp_set_rx_mode (struct net_device *dev)
934 struct cp_private *cp = netdev_priv(dev);
936 spin_lock_irqsave (&cp->lock, flags);
937 __cp_set_rx_mode(dev);
938 spin_unlock_irqrestore (&cp->lock, flags);
941 static void __cp_get_stats(struct cp_private *cp)
943 /* only lower 24 bits valid; write any value to clear */
944 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
948 static struct net_device_stats *cp_get_stats(struct net_device *dev)
950 struct cp_private *cp = netdev_priv(dev);
953 /* The chip only need report frame silently dropped. */
954 spin_lock_irqsave(&cp->lock, flags);
955 if (netif_running(dev) && netif_device_present(dev))
957 spin_unlock_irqrestore(&cp->lock, flags);
962 static void cp_stop_hw (struct cp_private *cp)
964 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
965 cpw16_f(IntrMask, 0);
968 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
971 cp->tx_head = cp->tx_tail = 0;
974 static void cp_reset_hw (struct cp_private *cp)
976 unsigned work = 1000;
981 if (!(cpr8(Cmd) & CmdReset))
984 schedule_timeout_uninterruptible(10);
987 netdev_err(cp->dev, "hardware reset timeout\n");
990 static inline void cp_start_hw (struct cp_private *cp)
992 cpw16(CpCmd, cp->cpcmd);
993 cpw8(Cmd, RxOn | TxOn);
996 static void cp_init_hw (struct cp_private *cp)
998 struct net_device *dev = cp->dev;
1003 cpw8_f (Cfg9346, Cfg9346_Unlock);
1005 /* Restore our idea of the MAC address. */
1006 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1007 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1010 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1012 __cp_set_rx_mode(dev);
1013 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1015 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1016 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1017 cpw8(Config3, PARMEnable);
1018 cp->wol_enabled = 0;
1020 cpw8(Config5, cpr8(Config5) & PMEStatus);
1022 cpw32_f(HiTxRingAddr, 0);
1023 cpw32_f(HiTxRingAddr + 4, 0);
1025 ring_dma = cp->ring_dma;
1026 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1027 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1029 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1030 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1031 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1033 cpw16(MultiIntr, 0);
1035 cpw16_f(IntrMask, cp_intr_mask);
1037 cpw8_f(Cfg9346, Cfg9346_Lock);
1040 static int cp_refill_rx(struct cp_private *cp)
1042 struct net_device *dev = cp->dev;
1045 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1046 struct sk_buff *skb;
1049 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1053 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1054 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1055 cp->rx_skb[i] = skb;
1057 cp->rx_ring[i].opts2 = 0;
1058 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1059 if (i == (CP_RX_RING_SIZE - 1))
1060 cp->rx_ring[i].opts1 =
1061 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1063 cp->rx_ring[i].opts1 =
1064 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1074 static void cp_init_rings_index (struct cp_private *cp)
1077 cp->tx_head = cp->tx_tail = 0;
1080 static int cp_init_rings (struct cp_private *cp)
1082 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1083 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1085 cp_init_rings_index(cp);
1087 return cp_refill_rx (cp);
1090 static int cp_alloc_rings (struct cp_private *cp)
1094 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1095 &cp->ring_dma, GFP_KERNEL);
1100 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1102 return cp_init_rings(cp);
1105 static void cp_clean_rings (struct cp_private *cp)
1107 struct cp_desc *desc;
1110 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1111 if (cp->rx_skb[i]) {
1112 desc = cp->rx_ring + i;
1113 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1114 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1115 dev_kfree_skb(cp->rx_skb[i]);
1119 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1120 if (cp->tx_skb[i]) {
1121 struct sk_buff *skb = cp->tx_skb[i];
1123 desc = cp->tx_ring + i;
1124 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1125 le32_to_cpu(desc->opts1) & 0xffff,
1127 if (le32_to_cpu(desc->opts1) & LastFrag)
1129 cp->dev->stats.tx_dropped++;
1133 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1134 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1136 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1137 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1140 static void cp_free_rings (struct cp_private *cp)
1143 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1149 static int cp_open (struct net_device *dev)
1151 struct cp_private *cp = netdev_priv(dev);
1154 netif_dbg(cp, ifup, dev, "enabling interface\n");
1156 rc = cp_alloc_rings(cp);
1160 napi_enable(&cp->napi);
1164 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1168 netif_carrier_off(dev);
1169 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1170 netif_start_queue(dev);
1175 napi_disable(&cp->napi);
1181 static int cp_close (struct net_device *dev)
1183 struct cp_private *cp = netdev_priv(dev);
1184 unsigned long flags;
1186 napi_disable(&cp->napi);
1188 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1190 spin_lock_irqsave(&cp->lock, flags);
1192 netif_stop_queue(dev);
1193 netif_carrier_off(dev);
1197 spin_unlock_irqrestore(&cp->lock, flags);
1199 free_irq(dev->irq, dev);
1205 static void cp_tx_timeout(struct net_device *dev)
1207 struct cp_private *cp = netdev_priv(dev);
1208 unsigned long flags;
1211 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1212 cpr8(Cmd), cpr16(CpCmd),
1213 cpr16(IntrStatus), cpr16(IntrMask));
1215 spin_lock_irqsave(&cp->lock, flags);
1219 rc = cp_init_rings(cp);
1222 netif_wake_queue(dev);
1224 spin_unlock_irqrestore(&cp->lock, flags);
1228 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1230 struct cp_private *cp = netdev_priv(dev);
1232 unsigned long flags;
1234 /* check for invalid MTU, according to hardware limits */
1235 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1238 /* if network interface not up, no need for complexity */
1239 if (!netif_running(dev)) {
1241 cp_set_rxbufsize(cp); /* set new rx buf size */
1245 spin_lock_irqsave(&cp->lock, flags);
1247 cp_stop_hw(cp); /* stop h/w and free rings */
1251 cp_set_rxbufsize(cp); /* set new rx buf size */
1253 rc = cp_init_rings(cp); /* realloc and restart h/w */
1256 spin_unlock_irqrestore(&cp->lock, flags);
1262 static const char mii_2_8139_map[8] = {
1273 static int mdio_read(struct net_device *dev, int phy_id, int location)
1275 struct cp_private *cp = netdev_priv(dev);
1277 return location < 8 && mii_2_8139_map[location] ?
1278 readw(cp->regs + mii_2_8139_map[location]) : 0;
1282 static void mdio_write(struct net_device *dev, int phy_id, int location,
1285 struct cp_private *cp = netdev_priv(dev);
1287 if (location == 0) {
1288 cpw8(Cfg9346, Cfg9346_Unlock);
1289 cpw16(BasicModeCtrl, value);
1290 cpw8(Cfg9346, Cfg9346_Lock);
1291 } else if (location < 8 && mii_2_8139_map[location])
1292 cpw16(mii_2_8139_map[location], value);
1295 /* Set the ethtool Wake-on-LAN settings */
1296 static int netdev_set_wol (struct cp_private *cp,
1297 const struct ethtool_wolinfo *wol)
1301 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1302 /* If WOL is being disabled, no need for complexity */
1304 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1305 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1308 cpw8 (Cfg9346, Cfg9346_Unlock);
1309 cpw8 (Config3, options);
1310 cpw8 (Cfg9346, Cfg9346_Lock);
1312 options = 0; /* Paranoia setting */
1313 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1314 /* If WOL is being disabled, no need for complexity */
1316 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1317 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1318 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1321 cpw8 (Config5, options);
1323 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1328 /* Get the ethtool Wake-on-LAN settings */
1329 static void netdev_get_wol (struct cp_private *cp,
1330 struct ethtool_wolinfo *wol)
1334 wol->wolopts = 0; /* Start from scratch */
1335 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1336 WAKE_MCAST | WAKE_UCAST;
1337 /* We don't need to go on if WOL is disabled */
1338 if (!cp->wol_enabled) return;
1340 options = cpr8 (Config3);
1341 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1342 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1344 options = 0; /* Paranoia setting */
1345 options = cpr8 (Config5);
1346 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1347 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1348 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1351 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1353 struct cp_private *cp = netdev_priv(dev);
1355 strcpy (info->driver, DRV_NAME);
1356 strcpy (info->version, DRV_VERSION);
1357 strcpy (info->bus_info, pci_name(cp->pdev));
1360 static int cp_get_regs_len(struct net_device *dev)
1362 return CP_REGS_SIZE;
1365 static int cp_get_sset_count (struct net_device *dev, int sset)
1369 return CP_NUM_STATS;
1375 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1377 struct cp_private *cp = netdev_priv(dev);
1379 unsigned long flags;
1381 spin_lock_irqsave(&cp->lock, flags);
1382 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1383 spin_unlock_irqrestore(&cp->lock, flags);
1388 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1390 struct cp_private *cp = netdev_priv(dev);
1392 unsigned long flags;
1394 spin_lock_irqsave(&cp->lock, flags);
1395 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1396 spin_unlock_irqrestore(&cp->lock, flags);
1401 static int cp_nway_reset(struct net_device *dev)
1403 struct cp_private *cp = netdev_priv(dev);
1404 return mii_nway_restart(&cp->mii_if);
1407 static u32 cp_get_msglevel(struct net_device *dev)
1409 struct cp_private *cp = netdev_priv(dev);
1410 return cp->msg_enable;
1413 static void cp_set_msglevel(struct net_device *dev, u32 value)
1415 struct cp_private *cp = netdev_priv(dev);
1416 cp->msg_enable = value;
1419 static int cp_set_features(struct net_device *dev, u32 features)
1421 struct cp_private *cp = netdev_priv(dev);
1422 unsigned long flags;
1424 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1427 spin_lock_irqsave(&cp->lock, flags);
1429 if (features & NETIF_F_RXCSUM)
1430 cp->cpcmd |= RxChkSum;
1432 cp->cpcmd &= ~RxChkSum;
1434 cpw16_f(CpCmd, cp->cpcmd);
1435 spin_unlock_irqrestore(&cp->lock, flags);
1440 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1443 struct cp_private *cp = netdev_priv(dev);
1444 unsigned long flags;
1446 if (regs->len < CP_REGS_SIZE)
1447 return /* -EINVAL */;
1449 regs->version = CP_REGS_VER;
1451 spin_lock_irqsave(&cp->lock, flags);
1452 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1453 spin_unlock_irqrestore(&cp->lock, flags);
1456 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1458 struct cp_private *cp = netdev_priv(dev);
1459 unsigned long flags;
1461 spin_lock_irqsave (&cp->lock, flags);
1462 netdev_get_wol (cp, wol);
1463 spin_unlock_irqrestore (&cp->lock, flags);
1466 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1468 struct cp_private *cp = netdev_priv(dev);
1469 unsigned long flags;
1472 spin_lock_irqsave (&cp->lock, flags);
1473 rc = netdev_set_wol (cp, wol);
1474 spin_unlock_irqrestore (&cp->lock, flags);
1479 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1481 switch (stringset) {
1483 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1491 static void cp_get_ethtool_stats (struct net_device *dev,
1492 struct ethtool_stats *estats, u64 *tmp_stats)
1494 struct cp_private *cp = netdev_priv(dev);
1495 struct cp_dma_stats *nic_stats;
1499 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1504 /* begin NIC statistics dump */
1505 cpw32(StatsAddr + 4, (u64)dma >> 32);
1506 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1509 for (i = 0; i < 1000; i++) {
1510 if ((cpr32(StatsAddr) & DumpStats) == 0)
1514 cpw32(StatsAddr, 0);
1515 cpw32(StatsAddr + 4, 0);
1519 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1520 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1521 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1522 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1523 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1524 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1525 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1526 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1527 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1528 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1529 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1530 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1531 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1532 tmp_stats[i++] = cp->cp_stats.rx_frags;
1533 BUG_ON(i != CP_NUM_STATS);
1535 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1538 static const struct ethtool_ops cp_ethtool_ops = {
1539 .get_drvinfo = cp_get_drvinfo,
1540 .get_regs_len = cp_get_regs_len,
1541 .get_sset_count = cp_get_sset_count,
1542 .get_settings = cp_get_settings,
1543 .set_settings = cp_set_settings,
1544 .nway_reset = cp_nway_reset,
1545 .get_link = ethtool_op_get_link,
1546 .get_msglevel = cp_get_msglevel,
1547 .set_msglevel = cp_set_msglevel,
1548 .get_regs = cp_get_regs,
1549 .get_wol = cp_get_wol,
1550 .set_wol = cp_set_wol,
1551 .get_strings = cp_get_strings,
1552 .get_ethtool_stats = cp_get_ethtool_stats,
1553 .get_eeprom_len = cp_get_eeprom_len,
1554 .get_eeprom = cp_get_eeprom,
1555 .set_eeprom = cp_set_eeprom,
1558 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1560 struct cp_private *cp = netdev_priv(dev);
1562 unsigned long flags;
1564 if (!netif_running(dev))
1567 spin_lock_irqsave(&cp->lock, flags);
1568 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1569 spin_unlock_irqrestore(&cp->lock, flags);
1573 static int cp_set_mac_address(struct net_device *dev, void *p)
1575 struct cp_private *cp = netdev_priv(dev);
1576 struct sockaddr *addr = p;
1578 if (!is_valid_ether_addr(addr->sa_data))
1579 return -EADDRNOTAVAIL;
1581 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1583 spin_lock_irq(&cp->lock);
1585 cpw8_f(Cfg9346, Cfg9346_Unlock);
1586 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1587 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1588 cpw8_f(Cfg9346, Cfg9346_Lock);
1590 spin_unlock_irq(&cp->lock);
1595 /* Serial EEPROM section. */
1597 /* EEPROM_Ctrl bits. */
1598 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1599 #define EE_CS 0x08 /* EEPROM chip select. */
1600 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1601 #define EE_WRITE_0 0x00
1602 #define EE_WRITE_1 0x02
1603 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1604 #define EE_ENB (0x80 | EE_CS)
1606 /* Delay between EEPROM clock transitions.
1607 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1610 #define eeprom_delay() readl(ee_addr)
1612 /* The EEPROM commands include the alway-set leading bit. */
1613 #define EE_EXTEND_CMD (4)
1614 #define EE_WRITE_CMD (5)
1615 #define EE_READ_CMD (6)
1616 #define EE_ERASE_CMD (7)
1618 #define EE_EWDS_ADDR (0)
1619 #define EE_WRAL_ADDR (1)
1620 #define EE_ERAL_ADDR (2)
1621 #define EE_EWEN_ADDR (3)
1623 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1625 static void eeprom_cmd_start(void __iomem *ee_addr)
1627 writeb (EE_ENB & ~EE_CS, ee_addr);
1628 writeb (EE_ENB, ee_addr);
1632 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1636 /* Shift the command bits out. */
1637 for (i = cmd_len - 1; i >= 0; i--) {
1638 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1639 writeb (EE_ENB | dataval, ee_addr);
1641 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1644 writeb (EE_ENB, ee_addr);
1648 static void eeprom_cmd_end(void __iomem *ee_addr)
1650 writeb (~EE_CS, ee_addr);
1654 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1657 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1659 eeprom_cmd_start(ee_addr);
1660 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1661 eeprom_cmd_end(ee_addr);
1664 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1668 void __iomem *ee_addr = ioaddr + Cfg9346;
1669 int read_cmd = location | (EE_READ_CMD << addr_len);
1671 eeprom_cmd_start(ee_addr);
1672 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1674 for (i = 16; i > 0; i--) {
1675 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1678 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1680 writeb (EE_ENB, ee_addr);
1684 eeprom_cmd_end(ee_addr);
1689 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1693 void __iomem *ee_addr = ioaddr + Cfg9346;
1694 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1696 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1698 eeprom_cmd_start(ee_addr);
1699 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1700 eeprom_cmd(ee_addr, val, 16);
1701 eeprom_cmd_end(ee_addr);
1703 eeprom_cmd_start(ee_addr);
1704 for (i = 0; i < 20000; i++)
1705 if (readb(ee_addr) & EE_DATA_READ)
1707 eeprom_cmd_end(ee_addr);
1709 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1712 static int cp_get_eeprom_len(struct net_device *dev)
1714 struct cp_private *cp = netdev_priv(dev);
1717 spin_lock_irq(&cp->lock);
1718 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1719 spin_unlock_irq(&cp->lock);
1724 static int cp_get_eeprom(struct net_device *dev,
1725 struct ethtool_eeprom *eeprom, u8 *data)
1727 struct cp_private *cp = netdev_priv(dev);
1728 unsigned int addr_len;
1730 u32 offset = eeprom->offset >> 1;
1731 u32 len = eeprom->len;
1734 eeprom->magic = CP_EEPROM_MAGIC;
1736 spin_lock_irq(&cp->lock);
1738 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1740 if (eeprom->offset & 1) {
1741 val = read_eeprom(cp->regs, offset, addr_len);
1742 data[i++] = (u8)(val >> 8);
1746 while (i < len - 1) {
1747 val = read_eeprom(cp->regs, offset, addr_len);
1748 data[i++] = (u8)val;
1749 data[i++] = (u8)(val >> 8);
1754 val = read_eeprom(cp->regs, offset, addr_len);
1758 spin_unlock_irq(&cp->lock);
1762 static int cp_set_eeprom(struct net_device *dev,
1763 struct ethtool_eeprom *eeprom, u8 *data)
1765 struct cp_private *cp = netdev_priv(dev);
1766 unsigned int addr_len;
1768 u32 offset = eeprom->offset >> 1;
1769 u32 len = eeprom->len;
1772 if (eeprom->magic != CP_EEPROM_MAGIC)
1775 spin_lock_irq(&cp->lock);
1777 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1779 if (eeprom->offset & 1) {
1780 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1781 val |= (u16)data[i++] << 8;
1782 write_eeprom(cp->regs, offset, val, addr_len);
1786 while (i < len - 1) {
1787 val = (u16)data[i++];
1788 val |= (u16)data[i++] << 8;
1789 write_eeprom(cp->regs, offset, val, addr_len);
1794 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1795 val |= (u16)data[i];
1796 write_eeprom(cp->regs, offset, val, addr_len);
1799 spin_unlock_irq(&cp->lock);
1803 /* Put the board into D3cold state and wait for WakeUp signal */
1804 static void cp_set_d3_state (struct cp_private *cp)
1806 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1807 pci_set_power_state (cp->pdev, PCI_D3hot);
1810 static const struct net_device_ops cp_netdev_ops = {
1811 .ndo_open = cp_open,
1812 .ndo_stop = cp_close,
1813 .ndo_validate_addr = eth_validate_addr,
1814 .ndo_set_mac_address = cp_set_mac_address,
1815 .ndo_set_multicast_list = cp_set_rx_mode,
1816 .ndo_get_stats = cp_get_stats,
1817 .ndo_do_ioctl = cp_ioctl,
1818 .ndo_start_xmit = cp_start_xmit,
1819 .ndo_tx_timeout = cp_tx_timeout,
1820 .ndo_set_features = cp_set_features,
1821 #if CP_VLAN_TAG_USED
1822 .ndo_vlan_rx_register = cp_vlan_rx_register,
1825 .ndo_change_mtu = cp_change_mtu,
1828 #ifdef CONFIG_NET_POLL_CONTROLLER
1829 .ndo_poll_controller = cp_poll_controller,
1833 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1835 struct net_device *dev;
1836 struct cp_private *cp;
1839 resource_size_t pciaddr;
1840 unsigned int addr_len, i, pci_using_dac;
1843 static int version_printed;
1844 if (version_printed++ == 0)
1845 pr_info("%s", version);
1848 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1849 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1850 dev_info(&pdev->dev,
1851 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1852 pdev->vendor, pdev->device, pdev->revision);
1856 dev = alloc_etherdev(sizeof(struct cp_private));
1859 SET_NETDEV_DEV(dev, &pdev->dev);
1861 cp = netdev_priv(dev);
1864 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1865 spin_lock_init (&cp->lock);
1866 cp->mii_if.dev = dev;
1867 cp->mii_if.mdio_read = mdio_read;
1868 cp->mii_if.mdio_write = mdio_write;
1869 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1870 cp->mii_if.phy_id_mask = 0x1f;
1871 cp->mii_if.reg_num_mask = 0x1f;
1872 cp_set_rxbufsize(cp);
1874 rc = pci_enable_device(pdev);
1878 rc = pci_set_mwi(pdev);
1880 goto err_out_disable;
1882 rc = pci_request_regions(pdev, DRV_NAME);
1886 pciaddr = pci_resource_start(pdev, 1);
1889 dev_err(&pdev->dev, "no MMIO resource\n");
1892 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1894 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1895 (unsigned long long)pci_resource_len(pdev, 1));
1899 /* Configure DMA attributes. */
1900 if ((sizeof(dma_addr_t) > 4) &&
1901 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1902 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1907 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1910 "No usable DMA configuration, aborting\n");
1913 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1916 "No usable consistent DMA configuration, aborting\n");
1921 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1922 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1924 dev->features |= NETIF_F_RXCSUM;
1925 dev->hw_features |= NETIF_F_RXCSUM;
1927 regs = ioremap(pciaddr, CP_REGS_SIZE);
1930 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1931 (unsigned long long)pci_resource_len(pdev, 1),
1932 (unsigned long long)pciaddr);
1935 dev->base_addr = (unsigned long) regs;
1940 /* read MAC address from EEPROM */
1941 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1942 for (i = 0; i < 3; i++)
1943 ((__le16 *) (dev->dev_addr))[i] =
1944 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1945 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1947 dev->netdev_ops = &cp_netdev_ops;
1948 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1949 dev->ethtool_ops = &cp_ethtool_ops;
1950 dev->watchdog_timeo = TX_TIMEOUT;
1952 #if CP_VLAN_TAG_USED
1953 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1957 dev->features |= NETIF_F_HIGHDMA;
1959 /* disabled by default until verified */
1960 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
1962 dev->irq = pdev->irq;
1964 rc = register_netdev(dev);
1968 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1969 dev->base_addr, dev->dev_addr, dev->irq);
1971 pci_set_drvdata(pdev, dev);
1973 /* enable busmastering and memory-write-invalidate */
1974 pci_set_master(pdev);
1976 if (cp->wol_enabled)
1977 cp_set_d3_state (cp);
1984 pci_release_regions(pdev);
1986 pci_clear_mwi(pdev);
1988 pci_disable_device(pdev);
1994 static void cp_remove_one (struct pci_dev *pdev)
1996 struct net_device *dev = pci_get_drvdata(pdev);
1997 struct cp_private *cp = netdev_priv(dev);
1999 unregister_netdev(dev);
2001 if (cp->wol_enabled)
2002 pci_set_power_state (pdev, PCI_D0);
2003 pci_release_regions(pdev);
2004 pci_clear_mwi(pdev);
2005 pci_disable_device(pdev);
2006 pci_set_drvdata(pdev, NULL);
2011 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2013 struct net_device *dev = pci_get_drvdata(pdev);
2014 struct cp_private *cp = netdev_priv(dev);
2015 unsigned long flags;
2017 if (!netif_running(dev))
2020 netif_device_detach (dev);
2021 netif_stop_queue (dev);
2023 spin_lock_irqsave (&cp->lock, flags);
2025 /* Disable Rx and Tx */
2026 cpw16 (IntrMask, 0);
2027 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2029 spin_unlock_irqrestore (&cp->lock, flags);
2031 pci_save_state(pdev);
2032 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2033 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2038 static int cp_resume (struct pci_dev *pdev)
2040 struct net_device *dev = pci_get_drvdata (pdev);
2041 struct cp_private *cp = netdev_priv(dev);
2042 unsigned long flags;
2044 if (!netif_running(dev))
2047 netif_device_attach (dev);
2049 pci_set_power_state(pdev, PCI_D0);
2050 pci_restore_state(pdev);
2051 pci_enable_wake(pdev, PCI_D0, 0);
2053 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2054 cp_init_rings_index (cp);
2056 netif_start_queue (dev);
2058 spin_lock_irqsave (&cp->lock, flags);
2060 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2062 spin_unlock_irqrestore (&cp->lock, flags);
2066 #endif /* CONFIG_PM */
2068 static struct pci_driver cp_driver = {
2070 .id_table = cp_pci_tbl,
2071 .probe = cp_init_one,
2072 .remove = cp_remove_one,
2074 .resume = cp_resume,
2075 .suspend = cp_suspend,
2079 static int __init cp_init (void)
2082 pr_info("%s", version);
2084 return pci_register_driver(&cp_driver);
2087 static void __exit cp_exit (void)
2089 pci_unregister_driver (&cp_driver);
2092 module_init(cp_init);
2093 module_exit(cp_exit);