2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter *adapter)
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
30 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
33 /* To check if valid bit is set, check the entire word as we don't know
34 * the endianness of the data (old entry is host endian while a new entry is
36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
38 if (compl->flags != 0) {
39 compl->flags = le32_to_cpu(compl->flags);
40 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
47 /* Need to reset the entire word that houses the valid bit */
48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
53 static int be_mcc_compl_process(struct be_adapter *adapter,
54 struct be_mcc_compl *compl)
56 u16 compl_status, extd_status;
58 /* Just swap the status to host endian; mcc tag is opaquely copied
60 be_dws_le_to_cpu(compl, 4);
62 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
63 CQE_STATUS_COMPL_MASK;
65 if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
66 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
67 adapter->flash_status = compl_status;
68 complete(&adapter->flash_compl);
71 if (compl_status == MCC_STATUS_SUCCESS) {
72 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
73 struct be_cmd_resp_get_stats *resp =
74 adapter->stats_cmd.va;
75 be_dws_le_to_cpu(&resp->hw_stats,
76 sizeof(resp->hw_stats));
77 netdev_stats_update(adapter);
78 adapter->stats_ioctl_sent = false;
80 } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
81 (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
82 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
84 dev_warn(&adapter->pdev->dev,
85 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
86 compl->tag0, compl_status, extd_status);
91 /* Link state evt is a string of bytes; no need for endian swapping */
92 static void be_async_link_state_process(struct be_adapter *adapter,
93 struct be_async_event_link_state *evt)
95 be_link_status_update(adapter,
96 evt->port_link_status == ASYNC_EVENT_LINK_UP);
99 /* Grp5 CoS Priority evt */
100 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
101 struct be_async_event_grp5_cos_priority *evt)
104 adapter->vlan_prio_bmap = evt->available_priority_bmap;
105 adapter->recommended_prio =
106 evt->reco_default_priority << VLAN_PRIO_SHIFT;
110 /* Grp5 QOS Speed evt */
111 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
112 struct be_async_event_grp5_qos_link_speed *evt)
114 if (evt->physical_port == adapter->port_num) {
115 /* qos_link_speed is in units of 10 Mbps */
116 adapter->link_speed = evt->qos_link_speed * 10;
120 static void be_async_grp5_evt_process(struct be_adapter *adapter,
121 u32 trailer, struct be_mcc_compl *evt)
125 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
126 ASYNC_TRAILER_EVENT_TYPE_MASK;
128 switch (event_type) {
129 case ASYNC_EVENT_COS_PRIORITY:
130 be_async_grp5_cos_priority_process(adapter,
131 (struct be_async_event_grp5_cos_priority *)evt);
133 case ASYNC_EVENT_QOS_SPEED:
134 be_async_grp5_qos_speed_process(adapter,
135 (struct be_async_event_grp5_qos_link_speed *)evt);
138 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
143 static inline bool is_link_state_evt(u32 trailer)
145 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
146 ASYNC_TRAILER_EVENT_CODE_MASK) ==
147 ASYNC_EVENT_CODE_LINK_STATE;
150 static inline bool is_grp5_evt(u32 trailer)
152 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
153 ASYNC_TRAILER_EVENT_CODE_MASK) ==
154 ASYNC_EVENT_CODE_GRP_5);
157 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
159 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
160 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
162 if (be_mcc_compl_is_new(compl)) {
163 queue_tail_inc(mcc_cq);
169 void be_async_mcc_enable(struct be_adapter *adapter)
171 spin_lock_bh(&adapter->mcc_cq_lock);
173 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
174 adapter->mcc_obj.rearm_cq = true;
176 spin_unlock_bh(&adapter->mcc_cq_lock);
179 void be_async_mcc_disable(struct be_adapter *adapter)
181 adapter->mcc_obj.rearm_cq = false;
184 int be_process_mcc(struct be_adapter *adapter, int *status)
186 struct be_mcc_compl *compl;
188 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
190 spin_lock_bh(&adapter->mcc_cq_lock);
191 while ((compl = be_mcc_compl_get(adapter))) {
192 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
193 /* Interpret flags as an async trailer */
194 if (is_link_state_evt(compl->flags))
195 be_async_link_state_process(adapter,
196 (struct be_async_event_link_state *) compl);
197 else if (is_grp5_evt(compl->flags))
198 be_async_grp5_evt_process(adapter,
199 compl->flags, compl);
200 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
201 *status = be_mcc_compl_process(adapter, compl);
202 atomic_dec(&mcc_obj->q.used);
204 be_mcc_compl_use(compl);
208 spin_unlock_bh(&adapter->mcc_cq_lock);
212 /* Wait till no more pending mcc requests are present */
213 static int be_mcc_wait_compl(struct be_adapter *adapter)
215 #define mcc_timeout 120000 /* 12s timeout */
216 int i, num, status = 0;
217 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
219 for (i = 0; i < mcc_timeout; i++) {
220 num = be_process_mcc(adapter, &status);
222 be_cq_notify(adapter, mcc_obj->cq.id,
223 mcc_obj->rearm_cq, num);
225 if (atomic_read(&mcc_obj->q.used) == 0)
229 if (i == mcc_timeout) {
230 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
236 /* Notify MCC requests and wait for completion */
237 static int be_mcc_notify_wait(struct be_adapter *adapter)
239 be_mcc_notify(adapter);
240 return be_mcc_wait_compl(adapter);
243 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
249 ready = ioread32(db);
250 if (ready == 0xffffffff) {
251 dev_err(&adapter->pdev->dev,
252 "pci slot disconnected\n");
256 ready &= MPU_MAILBOX_DB_RDY_MASK;
261 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
262 be_detect_dump_ue(adapter);
266 set_current_state(TASK_INTERRUPTIBLE);
267 schedule_timeout(msecs_to_jiffies(1));
275 * Insert the mailbox address into the doorbell in two steps
276 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
278 static int be_mbox_notify_wait(struct be_adapter *adapter)
282 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
283 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
284 struct be_mcc_mailbox *mbox = mbox_mem->va;
285 struct be_mcc_compl *compl = &mbox->compl;
287 /* wait for ready to be set */
288 status = be_mbox_db_ready_wait(adapter, db);
292 val |= MPU_MAILBOX_DB_HI_MASK;
293 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
294 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
297 /* wait for ready to be set */
298 status = be_mbox_db_ready_wait(adapter, db);
303 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
304 val |= (u32)(mbox_mem->dma >> 4) << 2;
307 status = be_mbox_db_ready_wait(adapter, db);
311 /* A cq entry has been made now */
312 if (be_mcc_compl_is_new(compl)) {
313 status = be_mcc_compl_process(adapter, &mbox->compl);
314 be_mcc_compl_use(compl);
318 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
324 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
326 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
328 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
329 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
335 int be_cmd_POST(struct be_adapter *adapter)
338 int status, timeout = 0;
341 status = be_POST_stage_get(adapter, &stage);
343 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
346 } else if (stage != POST_STAGE_ARMFW_RDY) {
347 set_current_state(TASK_INTERRUPTIBLE);
348 schedule_timeout(2 * HZ);
353 } while (timeout < 40);
355 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
359 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
361 return wrb->payload.embedded_payload;
364 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
366 return &wrb->payload.sgl[0];
369 /* Don't touch the hdr after it's prepared */
370 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
371 bool embedded, u8 sge_cnt, u32 opcode)
374 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
376 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
377 MCC_WRB_SGE_CNT_SHIFT;
378 wrb->payload_length = payload_len;
380 be_dws_cpu_to_le(wrb, 8);
383 /* Don't touch the hdr after it's prepared */
384 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
385 u8 subsystem, u8 opcode, int cmd_len)
387 req_hdr->opcode = opcode;
388 req_hdr->subsystem = subsystem;
389 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
390 req_hdr->version = 0;
393 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
394 struct be_dma_mem *mem)
396 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
397 u64 dma = (u64)mem->dma;
399 for (i = 0; i < buf_pages; i++) {
400 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
401 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
406 /* Converts interrupt delay in microseconds to multiplier value */
407 static u32 eq_delay_to_mult(u32 usec_delay)
409 #define MAX_INTR_RATE 651042
410 const u32 round = 10;
416 u32 interrupt_rate = 1000000 / usec_delay;
417 /* Max delay, corresponding to the lowest interrupt rate */
418 if (interrupt_rate == 0)
421 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
422 multiplier /= interrupt_rate;
423 /* Round the multiplier to the closest value.*/
424 multiplier = (multiplier + round/2) / round;
425 multiplier = min(multiplier, (u32)1023);
431 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
433 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
434 struct be_mcc_wrb *wrb
435 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
436 memset(wrb, 0, sizeof(*wrb));
440 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
442 struct be_queue_info *mccq = &adapter->mcc_obj.q;
443 struct be_mcc_wrb *wrb;
445 if (atomic_read(&mccq->used) >= mccq->len) {
446 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
450 wrb = queue_head_node(mccq);
451 queue_head_inc(mccq);
452 atomic_inc(&mccq->used);
453 memset(wrb, 0, sizeof(*wrb));
457 /* Tell fw we're about to start firing cmds by writing a
458 * special pattern across the wrb hdr; uses mbox
460 int be_cmd_fw_init(struct be_adapter *adapter)
465 spin_lock(&adapter->mbox_lock);
467 wrb = (u8 *)wrb_from_mbox(adapter);
477 status = be_mbox_notify_wait(adapter);
479 spin_unlock(&adapter->mbox_lock);
483 /* Tell fw we're done with firing cmds by writing a
484 * special pattern across the wrb hdr; uses mbox
486 int be_cmd_fw_clean(struct be_adapter *adapter)
491 if (adapter->eeh_err)
494 spin_lock(&adapter->mbox_lock);
496 wrb = (u8 *)wrb_from_mbox(adapter);
506 status = be_mbox_notify_wait(adapter);
508 spin_unlock(&adapter->mbox_lock);
511 int be_cmd_eq_create(struct be_adapter *adapter,
512 struct be_queue_info *eq, int eq_delay)
514 struct be_mcc_wrb *wrb;
515 struct be_cmd_req_eq_create *req;
516 struct be_dma_mem *q_mem = &eq->dma_mem;
519 spin_lock(&adapter->mbox_lock);
521 wrb = wrb_from_mbox(adapter);
522 req = embedded_payload(wrb);
524 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
526 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
527 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
529 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
531 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
533 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
534 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
535 __ilog2_u32(eq->len/256));
536 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
537 eq_delay_to_mult(eq_delay));
538 be_dws_cpu_to_le(req->context, sizeof(req->context));
540 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
542 status = be_mbox_notify_wait(adapter);
544 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
545 eq->id = le16_to_cpu(resp->eq_id);
549 spin_unlock(&adapter->mbox_lock);
554 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
555 u8 type, bool permanent, u32 if_handle)
557 struct be_mcc_wrb *wrb;
558 struct be_cmd_req_mac_query *req;
561 spin_lock(&adapter->mbox_lock);
563 wrb = wrb_from_mbox(adapter);
564 req = embedded_payload(wrb);
566 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
567 OPCODE_COMMON_NTWK_MAC_QUERY);
569 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
570 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
576 req->if_id = cpu_to_le16((u16) if_handle);
580 status = be_mbox_notify_wait(adapter);
582 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
583 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
586 spin_unlock(&adapter->mbox_lock);
590 /* Uses synchronous MCCQ */
591 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
592 u32 if_id, u32 *pmac_id)
594 struct be_mcc_wrb *wrb;
595 struct be_cmd_req_pmac_add *req;
598 spin_lock_bh(&adapter->mcc_lock);
600 wrb = wrb_from_mccq(adapter);
605 req = embedded_payload(wrb);
607 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
608 OPCODE_COMMON_NTWK_PMAC_ADD);
610 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
611 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
613 req->if_id = cpu_to_le32(if_id);
614 memcpy(req->mac_address, mac_addr, ETH_ALEN);
616 status = be_mcc_notify_wait(adapter);
618 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
619 *pmac_id = le32_to_cpu(resp->pmac_id);
623 spin_unlock_bh(&adapter->mcc_lock);
627 /* Uses synchronous MCCQ */
628 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
630 struct be_mcc_wrb *wrb;
631 struct be_cmd_req_pmac_del *req;
634 spin_lock_bh(&adapter->mcc_lock);
636 wrb = wrb_from_mccq(adapter);
641 req = embedded_payload(wrb);
643 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
644 OPCODE_COMMON_NTWK_PMAC_DEL);
646 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
647 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
649 req->if_id = cpu_to_le32(if_id);
650 req->pmac_id = cpu_to_le32(pmac_id);
652 status = be_mcc_notify_wait(adapter);
655 spin_unlock_bh(&adapter->mcc_lock);
660 int be_cmd_cq_create(struct be_adapter *adapter,
661 struct be_queue_info *cq, struct be_queue_info *eq,
662 bool sol_evts, bool no_delay, int coalesce_wm)
664 struct be_mcc_wrb *wrb;
665 struct be_cmd_req_cq_create *req;
666 struct be_dma_mem *q_mem = &cq->dma_mem;
670 spin_lock(&adapter->mbox_lock);
672 wrb = wrb_from_mbox(adapter);
673 req = embedded_payload(wrb);
674 ctxt = &req->context;
676 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
677 OPCODE_COMMON_CQ_CREATE);
679 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
680 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
682 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
684 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
685 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
686 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
687 __ilog2_u32(cq->len/256));
688 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
689 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
690 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
691 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
692 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
693 be_dws_cpu_to_le(ctxt, sizeof(req->context));
695 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
697 status = be_mbox_notify_wait(adapter);
699 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
700 cq->id = le16_to_cpu(resp->cq_id);
704 spin_unlock(&adapter->mbox_lock);
709 static u32 be_encoded_q_len(int q_len)
711 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
712 if (len_encoded == 16)
717 int be_cmd_mccq_create(struct be_adapter *adapter,
718 struct be_queue_info *mccq,
719 struct be_queue_info *cq)
721 struct be_mcc_wrb *wrb;
722 struct be_cmd_req_mcc_create *req;
723 struct be_dma_mem *q_mem = &mccq->dma_mem;
727 spin_lock(&adapter->mbox_lock);
729 wrb = wrb_from_mbox(adapter);
730 req = embedded_payload(wrb);
731 ctxt = &req->context;
733 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
734 OPCODE_COMMON_MCC_CREATE_EXT);
736 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
737 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
739 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
741 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
742 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
743 be_encoded_q_len(mccq->len));
744 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
745 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
746 req->async_event_bitmap[0] |= 0x00000022;
747 be_dws_cpu_to_le(ctxt, sizeof(req->context));
749 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
751 status = be_mbox_notify_wait(adapter);
753 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
754 mccq->id = le16_to_cpu(resp->id);
755 mccq->created = true;
757 spin_unlock(&adapter->mbox_lock);
762 int be_cmd_txq_create(struct be_adapter *adapter,
763 struct be_queue_info *txq,
764 struct be_queue_info *cq)
766 struct be_mcc_wrb *wrb;
767 struct be_cmd_req_eth_tx_create *req;
768 struct be_dma_mem *q_mem = &txq->dma_mem;
772 spin_lock(&adapter->mbox_lock);
774 wrb = wrb_from_mbox(adapter);
775 req = embedded_payload(wrb);
776 ctxt = &req->context;
778 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
779 OPCODE_ETH_TX_CREATE);
781 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
784 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
785 req->ulp_num = BE_ULP1_NUM;
786 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
788 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
789 be_encoded_q_len(txq->len));
790 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
791 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
793 be_dws_cpu_to_le(ctxt, sizeof(req->context));
795 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
797 status = be_mbox_notify_wait(adapter);
799 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
800 txq->id = le16_to_cpu(resp->cid);
804 spin_unlock(&adapter->mbox_lock);
810 int be_cmd_rxq_create(struct be_adapter *adapter,
811 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
812 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
814 struct be_mcc_wrb *wrb;
815 struct be_cmd_req_eth_rx_create *req;
816 struct be_dma_mem *q_mem = &rxq->dma_mem;
819 spin_lock(&adapter->mbox_lock);
821 wrb = wrb_from_mbox(adapter);
822 req = embedded_payload(wrb);
824 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
825 OPCODE_ETH_RX_CREATE);
827 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
830 req->cq_id = cpu_to_le16(cq_id);
831 req->frag_size = fls(frag_size) - 1;
833 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
834 req->interface_id = cpu_to_le32(if_id);
835 req->max_frame_size = cpu_to_le16(max_frame_size);
836 req->rss_queue = cpu_to_le32(rss);
838 status = be_mbox_notify_wait(adapter);
840 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
841 rxq->id = le16_to_cpu(resp->id);
843 *rss_id = resp->rss_id;
846 spin_unlock(&adapter->mbox_lock);
851 /* Generic destroyer function for all types of queues
854 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
857 struct be_mcc_wrb *wrb;
858 struct be_cmd_req_q_destroy *req;
859 u8 subsys = 0, opcode = 0;
862 if (adapter->eeh_err)
865 spin_lock(&adapter->mbox_lock);
867 wrb = wrb_from_mbox(adapter);
868 req = embedded_payload(wrb);
870 switch (queue_type) {
872 subsys = CMD_SUBSYSTEM_COMMON;
873 opcode = OPCODE_COMMON_EQ_DESTROY;
876 subsys = CMD_SUBSYSTEM_COMMON;
877 opcode = OPCODE_COMMON_CQ_DESTROY;
880 subsys = CMD_SUBSYSTEM_ETH;
881 opcode = OPCODE_ETH_TX_DESTROY;
884 subsys = CMD_SUBSYSTEM_ETH;
885 opcode = OPCODE_ETH_RX_DESTROY;
888 subsys = CMD_SUBSYSTEM_COMMON;
889 opcode = OPCODE_COMMON_MCC_DESTROY;
895 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
897 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
898 req->id = cpu_to_le16(q->id);
900 status = be_mbox_notify_wait(adapter);
902 spin_unlock(&adapter->mbox_lock);
907 /* Create an rx filtering policy configuration on an i/f
910 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
911 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
914 struct be_mcc_wrb *wrb;
915 struct be_cmd_req_if_create *req;
918 spin_lock(&adapter->mbox_lock);
920 wrb = wrb_from_mbox(adapter);
921 req = embedded_payload(wrb);
923 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
924 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
926 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
927 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
929 req->hdr.domain = domain;
930 req->capability_flags = cpu_to_le32(cap_flags);
931 req->enable_flags = cpu_to_le32(en_flags);
932 req->pmac_invalid = pmac_invalid;
934 memcpy(req->mac_addr, mac, ETH_ALEN);
936 status = be_mbox_notify_wait(adapter);
938 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
939 *if_handle = le32_to_cpu(resp->interface_id);
941 *pmac_id = le32_to_cpu(resp->pmac_id);
944 spin_unlock(&adapter->mbox_lock);
949 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
951 struct be_mcc_wrb *wrb;
952 struct be_cmd_req_if_destroy *req;
955 if (adapter->eeh_err)
958 spin_lock(&adapter->mbox_lock);
960 wrb = wrb_from_mbox(adapter);
961 req = embedded_payload(wrb);
963 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
964 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
966 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
967 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
969 req->interface_id = cpu_to_le32(interface_id);
971 status = be_mbox_notify_wait(adapter);
973 spin_unlock(&adapter->mbox_lock);
978 /* Get stats is a non embedded command: the request is not embedded inside
979 * WRB but is a separate dma memory block
980 * Uses asynchronous MCC
982 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
984 struct be_mcc_wrb *wrb;
985 struct be_cmd_req_get_stats *req;
989 spin_lock_bh(&adapter->mcc_lock);
991 wrb = wrb_from_mccq(adapter);
996 req = nonemb_cmd->va;
997 sge = nonembedded_sgl(wrb);
999 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1000 OPCODE_ETH_GET_STATISTICS);
1002 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1003 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1004 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1005 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1006 sge->len = cpu_to_le32(nonemb_cmd->size);
1008 be_mcc_notify(adapter);
1009 adapter->stats_ioctl_sent = true;
1012 spin_unlock_bh(&adapter->mcc_lock);
1016 /* Uses synchronous mcc */
1017 int be_cmd_link_status_query(struct be_adapter *adapter,
1018 bool *link_up, u8 *mac_speed, u16 *link_speed)
1020 struct be_mcc_wrb *wrb;
1021 struct be_cmd_req_link_status *req;
1024 spin_lock_bh(&adapter->mcc_lock);
1026 wrb = wrb_from_mccq(adapter);
1031 req = embedded_payload(wrb);
1035 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1036 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1038 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1039 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1041 status = be_mcc_notify_wait(adapter);
1043 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1044 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1046 *link_speed = le16_to_cpu(resp->link_speed);
1047 *mac_speed = resp->mac_speed;
1052 spin_unlock_bh(&adapter->mcc_lock);
1057 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1059 struct be_mcc_wrb *wrb;
1060 struct be_cmd_req_get_fw_version *req;
1063 spin_lock(&adapter->mbox_lock);
1065 wrb = wrb_from_mbox(adapter);
1066 req = embedded_payload(wrb);
1068 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1069 OPCODE_COMMON_GET_FW_VERSION);
1071 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1072 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1074 status = be_mbox_notify_wait(adapter);
1076 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1077 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1080 spin_unlock(&adapter->mbox_lock);
1084 /* set the EQ delay interval of an EQ to specified value
1087 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1089 struct be_mcc_wrb *wrb;
1090 struct be_cmd_req_modify_eq_delay *req;
1093 spin_lock_bh(&adapter->mcc_lock);
1095 wrb = wrb_from_mccq(adapter);
1100 req = embedded_payload(wrb);
1102 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1103 OPCODE_COMMON_MODIFY_EQ_DELAY);
1105 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1106 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1108 req->num_eq = cpu_to_le32(1);
1109 req->delay[0].eq_id = cpu_to_le32(eq_id);
1110 req->delay[0].phase = 0;
1111 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1113 be_mcc_notify(adapter);
1116 spin_unlock_bh(&adapter->mcc_lock);
1120 /* Uses sycnhronous mcc */
1121 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1122 u32 num, bool untagged, bool promiscuous)
1124 struct be_mcc_wrb *wrb;
1125 struct be_cmd_req_vlan_config *req;
1128 spin_lock_bh(&adapter->mcc_lock);
1130 wrb = wrb_from_mccq(adapter);
1135 req = embedded_payload(wrb);
1137 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1138 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1140 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1141 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1143 req->interface_id = if_id;
1144 req->promiscuous = promiscuous;
1145 req->untagged = untagged;
1146 req->num_vlan = num;
1148 memcpy(req->normal_vlan, vtag_array,
1149 req->num_vlan * sizeof(vtag_array[0]));
1152 status = be_mcc_notify_wait(adapter);
1155 spin_unlock_bh(&adapter->mcc_lock);
1159 /* Uses MCC for this command as it may be called in BH context
1160 * Uses synchronous mcc
1162 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1164 struct be_mcc_wrb *wrb;
1165 struct be_cmd_req_promiscuous_config *req;
1168 spin_lock_bh(&adapter->mcc_lock);
1170 wrb = wrb_from_mccq(adapter);
1175 req = embedded_payload(wrb);
1177 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1179 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1180 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1182 /* In FW versions X.102.149/X.101.487 and later,
1183 * the port setting associated only with the
1184 * issuing pci function will take effect
1187 req->port1_promiscuous = en;
1189 req->port0_promiscuous = en;
1191 status = be_mcc_notify_wait(adapter);
1194 spin_unlock_bh(&adapter->mcc_lock);
1199 * Uses MCC for this command as it may be called in BH context
1200 * (mc == NULL) => multicast promiscous
1202 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1203 struct net_device *netdev, struct be_dma_mem *mem)
1205 struct be_mcc_wrb *wrb;
1206 struct be_cmd_req_mcast_mac_config *req = mem->va;
1210 spin_lock_bh(&adapter->mcc_lock);
1212 wrb = wrb_from_mccq(adapter);
1217 sge = nonembedded_sgl(wrb);
1218 memset(req, 0, sizeof(*req));
1220 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1221 OPCODE_COMMON_NTWK_MULTICAST_SET);
1222 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1223 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1224 sge->len = cpu_to_le32(mem->size);
1226 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1227 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1229 req->interface_id = if_id;
1232 struct netdev_hw_addr *ha;
1234 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1237 netdev_for_each_mc_addr(ha, netdev)
1238 memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1240 req->promiscuous = 1;
1243 status = be_mcc_notify_wait(adapter);
1246 spin_unlock_bh(&adapter->mcc_lock);
1250 /* Uses synchrounous mcc */
1251 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1253 struct be_mcc_wrb *wrb;
1254 struct be_cmd_req_set_flow_control *req;
1257 spin_lock_bh(&adapter->mcc_lock);
1259 wrb = wrb_from_mccq(adapter);
1264 req = embedded_payload(wrb);
1266 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1267 OPCODE_COMMON_SET_FLOW_CONTROL);
1269 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1270 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1272 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1273 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1275 status = be_mcc_notify_wait(adapter);
1278 spin_unlock_bh(&adapter->mcc_lock);
1283 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1285 struct be_mcc_wrb *wrb;
1286 struct be_cmd_req_get_flow_control *req;
1289 spin_lock_bh(&adapter->mcc_lock);
1291 wrb = wrb_from_mccq(adapter);
1296 req = embedded_payload(wrb);
1298 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1299 OPCODE_COMMON_GET_FLOW_CONTROL);
1301 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1302 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1304 status = be_mcc_notify_wait(adapter);
1306 struct be_cmd_resp_get_flow_control *resp =
1307 embedded_payload(wrb);
1308 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1309 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1313 spin_unlock_bh(&adapter->mcc_lock);
1318 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1319 u32 *mode, u32 *caps)
1321 struct be_mcc_wrb *wrb;
1322 struct be_cmd_req_query_fw_cfg *req;
1325 spin_lock(&adapter->mbox_lock);
1327 wrb = wrb_from_mbox(adapter);
1328 req = embedded_payload(wrb);
1330 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1331 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1333 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1334 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1336 status = be_mbox_notify_wait(adapter);
1338 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1339 *port_num = le32_to_cpu(resp->phys_port);
1340 *mode = le32_to_cpu(resp->function_mode);
1341 *caps = le32_to_cpu(resp->function_caps);
1344 spin_unlock(&adapter->mbox_lock);
1349 int be_cmd_reset_function(struct be_adapter *adapter)
1351 struct be_mcc_wrb *wrb;
1352 struct be_cmd_req_hdr *req;
1355 spin_lock(&adapter->mbox_lock);
1357 wrb = wrb_from_mbox(adapter);
1358 req = embedded_payload(wrb);
1360 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1361 OPCODE_COMMON_FUNCTION_RESET);
1363 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1364 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1366 status = be_mbox_notify_wait(adapter);
1368 spin_unlock(&adapter->mbox_lock);
1372 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1374 struct be_mcc_wrb *wrb;
1375 struct be_cmd_req_rss_config *req;
1379 spin_lock(&adapter->mbox_lock);
1381 wrb = wrb_from_mbox(adapter);
1382 req = embedded_payload(wrb);
1384 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1385 OPCODE_ETH_RSS_CONFIG);
1387 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1388 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1390 req->if_id = cpu_to_le32(adapter->if_handle);
1391 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1392 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1393 memcpy(req->cpu_table, rsstable, table_size);
1394 memcpy(req->hash, myhash, sizeof(myhash));
1395 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1397 status = be_mbox_notify_wait(adapter);
1399 spin_unlock(&adapter->mbox_lock);
1404 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1405 u8 bcn, u8 sts, u8 state)
1407 struct be_mcc_wrb *wrb;
1408 struct be_cmd_req_enable_disable_beacon *req;
1411 spin_lock_bh(&adapter->mcc_lock);
1413 wrb = wrb_from_mccq(adapter);
1418 req = embedded_payload(wrb);
1420 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1421 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1423 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1424 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1426 req->port_num = port_num;
1427 req->beacon_state = state;
1428 req->beacon_duration = bcn;
1429 req->status_duration = sts;
1431 status = be_mcc_notify_wait(adapter);
1434 spin_unlock_bh(&adapter->mcc_lock);
1439 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1441 struct be_mcc_wrb *wrb;
1442 struct be_cmd_req_get_beacon_state *req;
1445 spin_lock_bh(&adapter->mcc_lock);
1447 wrb = wrb_from_mccq(adapter);
1452 req = embedded_payload(wrb);
1454 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1455 OPCODE_COMMON_GET_BEACON_STATE);
1457 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1458 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1460 req->port_num = port_num;
1462 status = be_mcc_notify_wait(adapter);
1464 struct be_cmd_resp_get_beacon_state *resp =
1465 embedded_payload(wrb);
1466 *state = resp->beacon_state;
1470 spin_unlock_bh(&adapter->mcc_lock);
1474 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1475 u32 flash_type, u32 flash_opcode, u32 buf_size)
1477 struct be_mcc_wrb *wrb;
1478 struct be_cmd_write_flashrom *req;
1482 spin_lock_bh(&adapter->mcc_lock);
1483 adapter->flash_status = 0;
1485 wrb = wrb_from_mccq(adapter);
1491 sge = nonembedded_sgl(wrb);
1493 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1494 OPCODE_COMMON_WRITE_FLASHROM);
1495 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1497 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1498 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1499 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1500 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1501 sge->len = cpu_to_le32(cmd->size);
1503 req->params.op_type = cpu_to_le32(flash_type);
1504 req->params.op_code = cpu_to_le32(flash_opcode);
1505 req->params.data_buf_size = cpu_to_le32(buf_size);
1507 be_mcc_notify(adapter);
1508 spin_unlock_bh(&adapter->mcc_lock);
1510 if (!wait_for_completion_timeout(&adapter->flash_compl,
1511 msecs_to_jiffies(12000)))
1514 status = adapter->flash_status;
1519 spin_unlock_bh(&adapter->mcc_lock);
1523 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1526 struct be_mcc_wrb *wrb;
1527 struct be_cmd_write_flashrom *req;
1530 spin_lock_bh(&adapter->mcc_lock);
1532 wrb = wrb_from_mccq(adapter);
1537 req = embedded_payload(wrb);
1539 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1540 OPCODE_COMMON_READ_FLASHROM);
1542 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1543 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1545 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1546 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1547 req->params.offset = cpu_to_le32(offset);
1548 req->params.data_buf_size = cpu_to_le32(0x4);
1550 status = be_mcc_notify_wait(adapter);
1552 memcpy(flashed_crc, req->params.data_buf, 4);
1555 spin_unlock_bh(&adapter->mcc_lock);
1559 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1560 struct be_dma_mem *nonemb_cmd)
1562 struct be_mcc_wrb *wrb;
1563 struct be_cmd_req_acpi_wol_magic_config *req;
1567 spin_lock_bh(&adapter->mcc_lock);
1569 wrb = wrb_from_mccq(adapter);
1574 req = nonemb_cmd->va;
1575 sge = nonembedded_sgl(wrb);
1577 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1578 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1580 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1581 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1582 memcpy(req->magic_mac, mac, ETH_ALEN);
1584 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1585 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1586 sge->len = cpu_to_le32(nonemb_cmd->size);
1588 status = be_mcc_notify_wait(adapter);
1591 spin_unlock_bh(&adapter->mcc_lock);
1595 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1596 u8 loopback_type, u8 enable)
1598 struct be_mcc_wrb *wrb;
1599 struct be_cmd_req_set_lmode *req;
1602 spin_lock_bh(&adapter->mcc_lock);
1604 wrb = wrb_from_mccq(adapter);
1610 req = embedded_payload(wrb);
1612 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1613 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1615 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1616 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1619 req->src_port = port_num;
1620 req->dest_port = port_num;
1621 req->loopback_type = loopback_type;
1622 req->loopback_state = enable;
1624 status = be_mcc_notify_wait(adapter);
1626 spin_unlock_bh(&adapter->mcc_lock);
1630 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1631 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1633 struct be_mcc_wrb *wrb;
1634 struct be_cmd_req_loopback_test *req;
1637 spin_lock_bh(&adapter->mcc_lock);
1639 wrb = wrb_from_mccq(adapter);
1645 req = embedded_payload(wrb);
1647 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1648 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1650 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1651 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1652 req->hdr.timeout = cpu_to_le32(4);
1654 req->pattern = cpu_to_le64(pattern);
1655 req->src_port = cpu_to_le32(port_num);
1656 req->dest_port = cpu_to_le32(port_num);
1657 req->pkt_size = cpu_to_le32(pkt_size);
1658 req->num_pkts = cpu_to_le32(num_pkts);
1659 req->loopback_type = cpu_to_le32(loopback_type);
1661 status = be_mcc_notify_wait(adapter);
1663 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1664 status = le32_to_cpu(resp->status);
1668 spin_unlock_bh(&adapter->mcc_lock);
1672 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1673 u32 byte_cnt, struct be_dma_mem *cmd)
1675 struct be_mcc_wrb *wrb;
1676 struct be_cmd_req_ddrdma_test *req;
1681 spin_lock_bh(&adapter->mcc_lock);
1683 wrb = wrb_from_mccq(adapter);
1689 sge = nonembedded_sgl(wrb);
1690 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1691 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1692 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1693 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1695 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1696 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1697 sge->len = cpu_to_le32(cmd->size);
1699 req->pattern = cpu_to_le64(pattern);
1700 req->byte_count = cpu_to_le32(byte_cnt);
1701 for (i = 0; i < byte_cnt; i++) {
1702 req->snd_buff[i] = (u8)(pattern >> (j*8));
1708 status = be_mcc_notify_wait(adapter);
1711 struct be_cmd_resp_ddrdma_test *resp;
1713 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1720 spin_unlock_bh(&adapter->mcc_lock);
1724 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1725 struct be_dma_mem *nonemb_cmd)
1727 struct be_mcc_wrb *wrb;
1728 struct be_cmd_req_seeprom_read *req;
1732 spin_lock_bh(&adapter->mcc_lock);
1734 wrb = wrb_from_mccq(adapter);
1735 req = nonemb_cmd->va;
1736 sge = nonembedded_sgl(wrb);
1738 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1739 OPCODE_COMMON_SEEPROM_READ);
1741 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1742 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1744 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1745 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1746 sge->len = cpu_to_le32(nonemb_cmd->size);
1748 status = be_mcc_notify_wait(adapter);
1750 spin_unlock_bh(&adapter->mcc_lock);
1754 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1756 struct be_mcc_wrb *wrb;
1757 struct be_cmd_req_get_phy_info *req;
1761 spin_lock_bh(&adapter->mcc_lock);
1763 wrb = wrb_from_mccq(adapter);
1770 sge = nonembedded_sgl(wrb);
1772 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1773 OPCODE_COMMON_GET_PHY_DETAILS);
1775 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1776 OPCODE_COMMON_GET_PHY_DETAILS,
1779 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1780 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1781 sge->len = cpu_to_le32(cmd->size);
1783 status = be_mcc_notify_wait(adapter);
1785 spin_unlock_bh(&adapter->mcc_lock);
1789 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1791 struct be_mcc_wrb *wrb;
1792 struct be_cmd_req_set_qos *req;
1795 spin_lock_bh(&adapter->mcc_lock);
1797 wrb = wrb_from_mccq(adapter);
1803 req = embedded_payload(wrb);
1805 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1806 OPCODE_COMMON_SET_QOS);
1808 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1809 OPCODE_COMMON_SET_QOS, sizeof(*req));
1811 req->hdr.domain = domain;
1812 req->valid_bits = BE_QOS_BITS_NIC;
1813 req->max_bps_nic = bps;
1815 status = be_mcc_notify_wait(adapter);
1818 spin_unlock_bh(&adapter->mcc_lock);