drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 static void be_mcc_notify(struct be_adapter *adapter)
  22 {
  23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24         u32 val = 0;
  25
  26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  28
  29         wmb();
  30         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  31 }
  32
  33 /* To check if valid bit is set, check the entire word as we don't know
  34  * the endianness of the data (old entry is host endian while a new entry is
  35  * little endian) */
  36 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  37 {
  38         if (compl->flags != 0) {
  39                 compl->flags = le32_to_cpu(compl->flags);
  40                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  41                 return true;
  42         } else {
  43                 return false;
  44         }
  45 }
  46
  47 /* Need to reset the entire word that houses the valid bit */
  48 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  49 {
  50         compl->flags = 0;
  51 }
  52
  53 static int be_mcc_compl_process(struct be_adapter *adapter,
  54         struct be_mcc_compl *compl)
  55 {
  56         u16 compl_status, extd_status;
  57
  58         /* Just swap the status to host endian; mcc tag is opaquely copied
  59          * from mcc_wrb */
  60         be_dws_le_to_cpu(compl, 4);
  61
  62         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  63                                 CQE_STATUS_COMPL_MASK;
  64
  65         if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
  66                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  67                 adapter->flash_status = compl_status;
  68                 complete(&adapter->flash_compl);
  69         }
  70
  71         if (compl_status == MCC_STATUS_SUCCESS) {
  72                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
  73                         struct be_cmd_resp_get_stats *resp =
  74                                                 adapter->stats_cmd.va;
  75                         be_dws_le_to_cpu(&resp->hw_stats,
  76                                                 sizeof(resp->hw_stats));
  77                         netdev_stats_update(adapter);
  78                         adapter->stats_ioctl_sent = false;
  79                 }
  80         } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
  81                    (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
  82                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  83                                 CQE_STATUS_EXTD_MASK;
  84                 dev_warn(&adapter->pdev->dev,
  85                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  86                         compl->tag0, compl_status, extd_status);
  87         }
  88         return compl_status;
  89 }
  90
  91 /* Link state evt is a string of bytes; no need for endian swapping */
  92 static void be_async_link_state_process(struct be_adapter *adapter,
  93                 struct be_async_event_link_state *evt)
  94 {
  95         be_link_status_update(adapter,
  96                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
  97 }
  98
  99 /* Grp5 CoS Priority evt */
 100 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 101                 struct be_async_event_grp5_cos_priority *evt)
 102 {
 103         if (evt->valid) {
 104                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 105                 adapter->recommended_prio =
 106                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 107         }
 108 }
 109
 110 /* Grp5 QOS Speed evt */
 111 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 112                 struct be_async_event_grp5_qos_link_speed *evt)
 113 {
 114         if (evt->physical_port == adapter->port_num) {
 115                 /* qos_link_speed is in units of 10 Mbps */
 116                 adapter->link_speed = evt->qos_link_speed * 10;
 117         }
 118 }
 119
 120 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 121                 u32 trailer, struct be_mcc_compl *evt)
 122 {
 123         u8 event_type = 0;
 124
 125         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 126                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 127
 128         switch (event_type) {
 129         case ASYNC_EVENT_COS_PRIORITY:
 130                 be_async_grp5_cos_priority_process(adapter,
 131                 (struct be_async_event_grp5_cos_priority *)evt);
 132         break;
 133         case ASYNC_EVENT_QOS_SPEED:
 134                 be_async_grp5_qos_speed_process(adapter,
 135                 (struct be_async_event_grp5_qos_link_speed *)evt);
 136         break;
 137         default:
 138                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 139                 break;
 140         }
 141 }
 142
 143 static inline bool is_link_state_evt(u32 trailer)
 144 {
 145         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 146                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 147                                 ASYNC_EVENT_CODE_LINK_STATE;
 148 }
 149
 150 static inline bool is_grp5_evt(u32 trailer)
 151 {
 152         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 153                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 154                                 ASYNC_EVENT_CODE_GRP_5);
 155 }
 156
 157 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 158 {
 159         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 160         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 161
 162         if (be_mcc_compl_is_new(compl)) {
 163                 queue_tail_inc(mcc_cq);
 164                 return compl;
 165         }
 166         return NULL;
 167 }
 168
 169 void be_async_mcc_enable(struct be_adapter *adapter)
 170 {
 171         spin_lock_bh(&adapter->mcc_cq_lock);
 172
 173         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 174         adapter->mcc_obj.rearm_cq = true;
 175
 176         spin_unlock_bh(&adapter->mcc_cq_lock);
 177 }
 178
 179 void be_async_mcc_disable(struct be_adapter *adapter)
 180 {
 181         adapter->mcc_obj.rearm_cq = false;
 182 }
 183
 184 int be_process_mcc(struct be_adapter *adapter, int *status)
 185 {
 186         struct be_mcc_compl *compl;
 187         int num = 0;
 188         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 189
 190         spin_lock_bh(&adapter->mcc_cq_lock);
 191         while ((compl = be_mcc_compl_get(adapter))) {
 192                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 193                         /* Interpret flags as an async trailer */
 194                         if (is_link_state_evt(compl->flags))
 195                                 be_async_link_state_process(adapter,
 196                                 (struct be_async_event_link_state *) compl);
 197                         else if (is_grp5_evt(compl->flags))
 198                                 be_async_grp5_evt_process(adapter,
 199                                 compl->flags, compl);
 200                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 201                                 *status = be_mcc_compl_process(adapter, compl);
 202                                 atomic_dec(&mcc_obj->q.used);
 203                 }
 204                 be_mcc_compl_use(compl);
 205                 num++;
 206         }
 207
 208         spin_unlock_bh(&adapter->mcc_cq_lock);
 209         return num;
 210 }
 211
 212 /* Wait till no more pending mcc requests are present */
 213 static int be_mcc_wait_compl(struct be_adapter *adapter)
 214 {
 215 #define mcc_timeout             120000 /* 12s timeout */
 216         int i, num, status = 0;
 217         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 218
 219         for (i = 0; i < mcc_timeout; i++) {
 220                 num = be_process_mcc(adapter, &status);
 221                 if (num)
 222                         be_cq_notify(adapter, mcc_obj->cq.id,
 223                                 mcc_obj->rearm_cq, num);
 224
 225                 if (atomic_read(&mcc_obj->q.used) == 0)
 226                         break;
 227                 udelay(100);
 228         }
 229         if (i == mcc_timeout) {
 230                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 231                 return -1;
 232         }
 233         return status;
 234 }
 235
 236 /* Notify MCC requests and wait for completion */
 237 static int be_mcc_notify_wait(struct be_adapter *adapter)
 238 {
 239         be_mcc_notify(adapter);
 240         return be_mcc_wait_compl(adapter);
 241 }
 242
 243 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 244 {
 245         int msecs = 0;
 246         u32 ready;
 247
 248         do {
 249                 ready = ioread32(db);
 250                 if (ready == 0xffffffff) {
 251                         dev_err(&adapter->pdev->dev,
 252                                 "pci slot disconnected\n");
 253                         return -1;
 254                 }
 255
 256                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 257                 if (ready)
 258                         break;
 259
 260                 if (msecs > 4000) {
 261                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 262                         be_detect_dump_ue(adapter);
 263                         return -1;
 264                 }
 265
 266                 set_current_state(TASK_INTERRUPTIBLE);
 267                 schedule_timeout(msecs_to_jiffies(1));
 268                 msecs++;
 269         } while (true);
 270
 271         return 0;
 272 }
 273
 274 /*
 275  * Insert the mailbox address into the doorbell in two steps
 276  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 277  */
 278 static int be_mbox_notify_wait(struct be_adapter *adapter)
 279 {
 280         int status;
 281         u32 val = 0;
 282         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 283         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 284         struct be_mcc_mailbox *mbox = mbox_mem->va;
 285         struct be_mcc_compl *compl = &mbox->compl;
 286
 287         /* wait for ready to be set */
 288         status = be_mbox_db_ready_wait(adapter, db);
 289         if (status != 0)
 290                 return status;
 291
 292         val |= MPU_MAILBOX_DB_HI_MASK;
 293         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 294         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 295         iowrite32(val, db);
 296
 297         /* wait for ready to be set */
 298         status = be_mbox_db_ready_wait(adapter, db);
 299         if (status != 0)
 300                 return status;
 301
 302         val = 0;
 303         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 304         val |= (u32)(mbox_mem->dma >> 4) << 2;
 305         iowrite32(val, db);
 306
 307         status = be_mbox_db_ready_wait(adapter, db);
 308         if (status != 0)
 309                 return status;
 310
 311         /* A cq entry has been made now */
 312         if (be_mcc_compl_is_new(compl)) {
 313                 status = be_mcc_compl_process(adapter, &mbox->compl);
 314                 be_mcc_compl_use(compl);
 315                 if (status)
 316                         return status;
 317         } else {
 318                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 319                 return -1;
 320         }
 321         return 0;
 322 }
 323
 324 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 325 {
 326         u32 sem;
 327
 328         if (lancer_chip(adapter))
 329                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 330         else
 331                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 332
 333         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 334         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 335                 return -1;
 336         else
 337                 return 0;
 338 }
 339
 340 int be_cmd_POST(struct be_adapter *adapter)
 341 {
 342         u16 stage;
 343         int status, timeout = 0;
 344
 345         do {
 346                 status = be_POST_stage_get(adapter, &stage);
 347                 if (status) {
 348                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
 349                                 stage);
 350                         return -1;
 351                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 352                         set_current_state(TASK_INTERRUPTIBLE);
 353                         schedule_timeout(2 * HZ);
 354                         timeout += 2;
 355                 } else {
 356                         return 0;
 357                 }
 358         } while (timeout < 40);
 359
 360         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
 361         return -1;
 362 }
 363
 364 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 365 {
 366         return wrb->payload.embedded_payload;
 367 }
 368
 369 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 370 {
 371         return &wrb->payload.sgl[0];
 372 }
 373
 374 /* Don't touch the hdr after it's prepared */
 375 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 376                                 bool embedded, u8 sge_cnt, u32 opcode)
 377 {
 378         if (embedded)
 379                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 380         else
 381                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 382                                 MCC_WRB_SGE_CNT_SHIFT;
 383         wrb->payload_length = payload_len;
 384         wrb->tag0 = opcode;
 385         be_dws_cpu_to_le(wrb, 8);
 386 }
 387
 388 /* Don't touch the hdr after it's prepared */
 389 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 390                                 u8 subsystem, u8 opcode, int cmd_len)
 391 {
 392         req_hdr->opcode = opcode;
 393         req_hdr->subsystem = subsystem;
 394         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 395         req_hdr->version = 0;
 396 }
 397
 398 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 399                         struct be_dma_mem *mem)
 400 {
 401         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 402         u64 dma = (u64)mem->dma;
 403
 404         for (i = 0; i < buf_pages; i++) {
 405                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 406                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 407                 dma += PAGE_SIZE_4K;
 408         }
 409 }
 410
 411 /* Converts interrupt delay in microseconds to multiplier value */
 412 static u32 eq_delay_to_mult(u32 usec_delay)
 413 {
 414 #define MAX_INTR_RATE                   651042
 415         const u32 round = 10;
 416         u32 multiplier;
 417
 418         if (usec_delay == 0)
 419                 multiplier = 0;
 420         else {
 421                 u32 interrupt_rate = 1000000 / usec_delay;
 422                 /* Max delay, corresponding to the lowest interrupt rate */
 423                 if (interrupt_rate == 0)
 424                         multiplier = 1023;
 425                 else {
 426                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 427                         multiplier /= interrupt_rate;
 428                         /* Round the multiplier to the closest value.*/
 429                         multiplier = (multiplier + round/2) / round;
 430                         multiplier = min(multiplier, (u32)1023);
 431                 }
 432         }
 433         return multiplier;
 434 }
 435
 436 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 437 {
 438         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 439         struct be_mcc_wrb *wrb
 440                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 441         memset(wrb, 0, sizeof(*wrb));
 442         return wrb;
 443 }
 444
 445 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 446 {
 447         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 448         struct be_mcc_wrb *wrb;
 449
 450         if (atomic_read(&mccq->used) >= mccq->len) {
 451                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 452                 return NULL;
 453         }
 454
 455         wrb = queue_head_node(mccq);
 456         queue_head_inc(mccq);
 457         atomic_inc(&mccq->used);
 458         memset(wrb, 0, sizeof(*wrb));
 459         return wrb;
 460 }
 461
 462 /* Tell fw we're about to start firing cmds by writing a
 463  * special pattern across the wrb hdr; uses mbox
 464  */
 465 int be_cmd_fw_init(struct be_adapter *adapter)
 466 {
 467         u8 *wrb;
 468         int status;
 469
 470         spin_lock(&adapter->mbox_lock);
 471
 472         wrb = (u8 *)wrb_from_mbox(adapter);
 473         *wrb++ = 0xFF;
 474         *wrb++ = 0x12;
 475         *wrb++ = 0x34;
 476         *wrb++ = 0xFF;
 477         *wrb++ = 0xFF;
 478         *wrb++ = 0x56;
 479         *wrb++ = 0x78;
 480         *wrb = 0xFF;
 481
 482         status = be_mbox_notify_wait(adapter);
 483
 484         spin_unlock(&adapter->mbox_lock);
 485         return status;
 486 }
 487
 488 /* Tell fw we're done with firing cmds by writing a
 489  * special pattern across the wrb hdr; uses mbox
 490  */
 491 int be_cmd_fw_clean(struct be_adapter *adapter)
 492 {
 493         u8 *wrb;
 494         int status;
 495
 496         if (adapter->eeh_err)
 497                 return -EIO;
 498
 499         spin_lock(&adapter->mbox_lock);
 500
 501         wrb = (u8 *)wrb_from_mbox(adapter);
 502         *wrb++ = 0xFF;
 503         *wrb++ = 0xAA;
 504         *wrb++ = 0xBB;
 505         *wrb++ = 0xFF;
 506         *wrb++ = 0xFF;
 507         *wrb++ = 0xCC;
 508         *wrb++ = 0xDD;
 509         *wrb = 0xFF;
 510
 511         status = be_mbox_notify_wait(adapter);
 512
 513         spin_unlock(&adapter->mbox_lock);
 514         return status;
 515 }
 516 int be_cmd_eq_create(struct be_adapter *adapter,
 517                 struct be_queue_info *eq, int eq_delay)
 518 {
 519         struct be_mcc_wrb *wrb;
 520         struct be_cmd_req_eq_create *req;
 521         struct be_dma_mem *q_mem = &eq->dma_mem;
 522         int status;
 523
 524         spin_lock(&adapter->mbox_lock);
 525
 526         wrb = wrb_from_mbox(adapter);
 527         req = embedded_payload(wrb);
 528
 529         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 530
 531         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 532                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 533
 534         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 535
 536         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 537         /* 4byte eqe*/
 538         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 539         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 540                         __ilog2_u32(eq->len/256));
 541         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 542                         eq_delay_to_mult(eq_delay));
 543         be_dws_cpu_to_le(req->context, sizeof(req->context));
 544
 545         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 546
 547         status = be_mbox_notify_wait(adapter);
 548         if (!status) {
 549                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 550                 eq->id = le16_to_cpu(resp->eq_id);
 551                 eq->created = true;
 552         }
 553
 554         spin_unlock(&adapter->mbox_lock);
 555         return status;
 556 }
 557
 558 /* Uses mbox */
 559 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 560                         u8 type, bool permanent, u32 if_handle)
 561 {
 562         struct be_mcc_wrb *wrb;
 563         struct be_cmd_req_mac_query *req;
 564         int status;
 565
 566         spin_lock(&adapter->mbox_lock);
 567
 568         wrb = wrb_from_mbox(adapter);
 569         req = embedded_payload(wrb);
 570
 571         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 572                         OPCODE_COMMON_NTWK_MAC_QUERY);
 573
 574         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 575                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 576
 577         req->type = type;
 578         if (permanent) {
 579                 req->permanent = 1;
 580         } else {
 581                 req->if_id = cpu_to_le16((u16) if_handle);
 582                 req->permanent = 0;
 583         }
 584
 585         status = be_mbox_notify_wait(adapter);
 586         if (!status) {
 587                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 588                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 589         }
 590
 591         spin_unlock(&adapter->mbox_lock);
 592         return status;
 593 }
 594
 595 /* Uses synchronous MCCQ */
 596 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 597                 u32 if_id, u32 *pmac_id)
 598 {
 599         struct be_mcc_wrb *wrb;
 600         struct be_cmd_req_pmac_add *req;
 601         int status;
 602
 603         spin_lock_bh(&adapter->mcc_lock);
 604
 605         wrb = wrb_from_mccq(adapter);
 606         if (!wrb) {
 607                 status = -EBUSY;
 608                 goto err;
 609         }
 610         req = embedded_payload(wrb);
 611
 612         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 613                         OPCODE_COMMON_NTWK_PMAC_ADD);
 614
 615         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 616                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 617
 618         req->if_id = cpu_to_le32(if_id);
 619         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 620
 621         status = be_mcc_notify_wait(adapter);
 622         if (!status) {
 623                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 624                 *pmac_id = le32_to_cpu(resp->pmac_id);
 625         }
 626
 627 err:
 628         spin_unlock_bh(&adapter->mcc_lock);
 629         return status;
 630 }
 631
 632 /* Uses synchronous MCCQ */
 633 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
 634 {
 635         struct be_mcc_wrb *wrb;
 636         struct be_cmd_req_pmac_del *req;
 637         int status;
 638
 639         spin_lock_bh(&adapter->mcc_lock);
 640
 641         wrb = wrb_from_mccq(adapter);
 642         if (!wrb) {
 643                 status = -EBUSY;
 644                 goto err;
 645         }
 646         req = embedded_payload(wrb);
 647
 648         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 649                         OPCODE_COMMON_NTWK_PMAC_DEL);
 650
 651         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 652                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 653
 654         req->if_id = cpu_to_le32(if_id);
 655         req->pmac_id = cpu_to_le32(pmac_id);
 656
 657         status = be_mcc_notify_wait(adapter);
 658
 659 err:
 660         spin_unlock_bh(&adapter->mcc_lock);
 661         return status;
 662 }
 663
 664 /* Uses Mbox */
 665 int be_cmd_cq_create(struct be_adapter *adapter,
 666                 struct be_queue_info *cq, struct be_queue_info *eq,
 667                 bool sol_evts, bool no_delay, int coalesce_wm)
 668 {
 669         struct be_mcc_wrb *wrb;
 670         struct be_cmd_req_cq_create *req;
 671         struct be_dma_mem *q_mem = &cq->dma_mem;
 672         void *ctxt;
 673         int status;
 674
 675         spin_lock(&adapter->mbox_lock);
 676
 677         wrb = wrb_from_mbox(adapter);
 678         req = embedded_payload(wrb);
 679         ctxt = &req->context;
 680
 681         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 682                         OPCODE_COMMON_CQ_CREATE);
 683
 684         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 685                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 686
 687         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 688         if (lancer_chip(adapter)) {
 689                 req->hdr.version = 1;
 690                 req->page_size = 1; /* 1 for 4K */
 691                 AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
 692                                                                 coalesce_wm);
 693                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 694                                                                 no_delay);
 695                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 696                                                 __ilog2_u32(cq->len/256));
 697                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 698                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 699                                                                 ctxt, 1);
 700                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 701                                                                 ctxt, eq->id);
 702                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 703         } else {
 704                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 705                                                                 coalesce_wm);
 706                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 707                                                                 ctxt, no_delay);
 708                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 709                                                 __ilog2_u32(cq->len/256));
 710                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 711                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 712                                                                 ctxt, sol_evts);
 713                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 714                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 715                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 716         }
 717
 718         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 719
 720         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 721
 722         status = be_mbox_notify_wait(adapter);
 723         if (!status) {
 724                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 725                 cq->id = le16_to_cpu(resp->cq_id);
 726                 cq->created = true;
 727         }
 728
 729         spin_unlock(&adapter->mbox_lock);
 730
 731         return status;
 732 }
 733
 734 static u32 be_encoded_q_len(int q_len)
 735 {
 736         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 737         if (len_encoded == 16)
 738                 len_encoded = 0;
 739         return len_encoded;
 740 }
 741
 742 int be_cmd_mccq_create(struct be_adapter *adapter,
 743                         struct be_queue_info *mccq,
 744                         struct be_queue_info *cq)
 745 {
 746         struct be_mcc_wrb *wrb;
 747         struct be_cmd_req_mcc_create *req;
 748         struct be_dma_mem *q_mem = &mccq->dma_mem;
 749         void *ctxt;
 750         int status;
 751
 752         spin_lock(&adapter->mbox_lock);
 753
 754         wrb = wrb_from_mbox(adapter);
 755         req = embedded_payload(wrb);
 756         ctxt = &req->context;
 757
 758         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 759                         OPCODE_COMMON_MCC_CREATE_EXT);
 760
 761         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 762                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 763
 764         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 765         if (lancer_chip(adapter)) {
 766                 req->hdr.version = 1;
 767                 req->cq_id = cpu_to_le16(cq->id);
 768
 769                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 770                                                 be_encoded_q_len(mccq->len));
 771                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 772                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 773                                                                 ctxt, cq->id);
 774                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 775                                                                  ctxt, 1);
 776
 777         } else {
 778                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 779                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 780                                                 be_encoded_q_len(mccq->len));
 781                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 782         }
 783
 784         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 785         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 786         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 787
 788         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 789
 790         status = be_mbox_notify_wait(adapter);
 791         if (!status) {
 792                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 793                 mccq->id = le16_to_cpu(resp->id);
 794                 mccq->created = true;
 795         }
 796         spin_unlock(&adapter->mbox_lock);
 797
 798         return status;
 799 }
 800
 801 int be_cmd_txq_create(struct be_adapter *adapter,
 802                         struct be_queue_info *txq,
 803                         struct be_queue_info *cq)
 804 {
 805         struct be_mcc_wrb *wrb;
 806         struct be_cmd_req_eth_tx_create *req;
 807         struct be_dma_mem *q_mem = &txq->dma_mem;
 808         void *ctxt;
 809         int status;
 810
 811         spin_lock(&adapter->mbox_lock);
 812
 813         wrb = wrb_from_mbox(adapter);
 814         req = embedded_payload(wrb);
 815         ctxt = &req->context;
 816
 817         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 818                         OPCODE_ETH_TX_CREATE);
 819
 820         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 821                 sizeof(*req));
 822
 823         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 824         req->ulp_num = BE_ULP1_NUM;
 825         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 826
 827         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 828                 be_encoded_q_len(txq->len));
 829         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 830         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 831
 832         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 833
 834         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 835
 836         status = be_mbox_notify_wait(adapter);
 837         if (!status) {
 838                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 839                 txq->id = le16_to_cpu(resp->cid);
 840                 txq->created = true;
 841         }
 842
 843         spin_unlock(&adapter->mbox_lock);
 844
 845         return status;
 846 }
 847
 848 /* Uses mbox */
 849 int be_cmd_rxq_create(struct be_adapter *adapter,
 850                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 851                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 852 {
 853         struct be_mcc_wrb *wrb;
 854         struct be_cmd_req_eth_rx_create *req;
 855         struct be_dma_mem *q_mem = &rxq->dma_mem;
 856         int status;
 857
 858         spin_lock(&adapter->mbox_lock);
 859
 860         wrb = wrb_from_mbox(adapter);
 861         req = embedded_payload(wrb);
 862
 863         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 864                         OPCODE_ETH_RX_CREATE);
 865
 866         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 867                 sizeof(*req));
 868
 869         req->cq_id = cpu_to_le16(cq_id);
 870         req->frag_size = fls(frag_size) - 1;
 871         req->num_pages = 2;
 872         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 873         req->interface_id = cpu_to_le32(if_id);
 874         req->max_frame_size = cpu_to_le16(max_frame_size);
 875         req->rss_queue = cpu_to_le32(rss);
 876
 877         status = be_mbox_notify_wait(adapter);
 878         if (!status) {
 879                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 880                 rxq->id = le16_to_cpu(resp->id);
 881                 rxq->created = true;
 882                 *rss_id = resp->rss_id;
 883         }
 884
 885         spin_unlock(&adapter->mbox_lock);
 886
 887         return status;
 888 }
 889
 890 /* Generic destroyer function for all types of queues
 891  * Uses Mbox
 892  */
 893 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 894                 int queue_type)
 895 {
 896         struct be_mcc_wrb *wrb;
 897         struct be_cmd_req_q_destroy *req;
 898         u8 subsys = 0, opcode = 0;
 899         int status;
 900
 901         if (adapter->eeh_err)
 902                 return -EIO;
 903
 904         spin_lock(&adapter->mbox_lock);
 905
 906         wrb = wrb_from_mbox(adapter);
 907         req = embedded_payload(wrb);
 908
 909         switch (queue_type) {
 910         case QTYPE_EQ:
 911                 subsys = CMD_SUBSYSTEM_COMMON;
 912                 opcode = OPCODE_COMMON_EQ_DESTROY;
 913                 break;
 914         case QTYPE_CQ:
 915                 subsys = CMD_SUBSYSTEM_COMMON;
 916                 opcode = OPCODE_COMMON_CQ_DESTROY;
 917                 break;
 918         case QTYPE_TXQ:
 919                 subsys = CMD_SUBSYSTEM_ETH;
 920                 opcode = OPCODE_ETH_TX_DESTROY;
 921                 break;
 922         case QTYPE_RXQ:
 923                 subsys = CMD_SUBSYSTEM_ETH;
 924                 opcode = OPCODE_ETH_RX_DESTROY;
 925                 break;
 926         case QTYPE_MCCQ:
 927                 subsys = CMD_SUBSYSTEM_COMMON;
 928                 opcode = OPCODE_COMMON_MCC_DESTROY;
 929                 break;
 930         default:
 931                 BUG();
 932         }
 933
 934         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
 935
 936         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 937         req->id = cpu_to_le16(q->id);
 938
 939         status = be_mbox_notify_wait(adapter);
 940
 941         spin_unlock(&adapter->mbox_lock);
 942
 943         return status;
 944 }
 945
 946 /* Create an rx filtering policy configuration on an i/f
 947  * Uses mbox
 948  */
 949 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
 950                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
 951                 u32 domain)
 952 {
 953         struct be_mcc_wrb *wrb;
 954         struct be_cmd_req_if_create *req;
 955         int status;
 956
 957         spin_lock(&adapter->mbox_lock);
 958
 959         wrb = wrb_from_mbox(adapter);
 960         req = embedded_payload(wrb);
 961
 962         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 963                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
 964
 965         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 966                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
 967
 968         req->hdr.domain = domain;
 969         req->capability_flags = cpu_to_le32(cap_flags);
 970         req->enable_flags = cpu_to_le32(en_flags);
 971         req->pmac_invalid = pmac_invalid;
 972         if (!pmac_invalid)
 973                 memcpy(req->mac_addr, mac, ETH_ALEN);
 974
 975         status = be_mbox_notify_wait(adapter);
 976         if (!status) {
 977                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
 978                 *if_handle = le32_to_cpu(resp->interface_id);
 979                 if (!pmac_invalid)
 980                         *pmac_id = le32_to_cpu(resp->pmac_id);
 981         }
 982
 983         spin_unlock(&adapter->mbox_lock);
 984         return status;
 985 }
 986
 987 /* Uses mbox */
 988 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 989 {
 990         struct be_mcc_wrb *wrb;
 991         struct be_cmd_req_if_destroy *req;
 992         int status;
 993
 994         if (adapter->eeh_err)
 995                 return -EIO;
 996
 997         spin_lock(&adapter->mbox_lock);
 998
 999         wrb = wrb_from_mbox(adapter);
1000         req = embedded_payload(wrb);
1001
1002         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1003                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1004
1005         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1006                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1007
1008         req->interface_id = cpu_to_le32(interface_id);
1009
1010         status = be_mbox_notify_wait(adapter);
1011
1012         spin_unlock(&adapter->mbox_lock);
1013
1014         return status;
1015 }
1016
1017 /* Get stats is a non embedded command: the request is not embedded inside
1018  * WRB but is a separate dma memory block
1019  * Uses asynchronous MCC
1020  */
1021 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1022 {
1023         struct be_mcc_wrb *wrb;
1024         struct be_cmd_req_get_stats *req;
1025         struct be_sge *sge;
1026         int status = 0;
1027
1028         spin_lock_bh(&adapter->mcc_lock);
1029
1030         wrb = wrb_from_mccq(adapter);
1031         if (!wrb) {
1032                 status = -EBUSY;
1033                 goto err;
1034         }
1035         req = nonemb_cmd->va;
1036         sge = nonembedded_sgl(wrb);
1037
1038         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1039                         OPCODE_ETH_GET_STATISTICS);
1040
1041         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1042                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1043         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1044         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1045         sge->len = cpu_to_le32(nonemb_cmd->size);
1046
1047         be_mcc_notify(adapter);
1048         adapter->stats_ioctl_sent = true;
1049
1050 err:
1051         spin_unlock_bh(&adapter->mcc_lock);
1052         return status;
1053 }
1054
1055 /* Uses synchronous mcc */
1056 int be_cmd_link_status_query(struct be_adapter *adapter,
1057                         bool *link_up, u8 *mac_speed, u16 *link_speed)
1058 {
1059         struct be_mcc_wrb *wrb;
1060         struct be_cmd_req_link_status *req;
1061         int status;
1062
1063         spin_lock_bh(&adapter->mcc_lock);
1064
1065         wrb = wrb_from_mccq(adapter);
1066         if (!wrb) {
1067                 status = -EBUSY;
1068                 goto err;
1069         }
1070         req = embedded_payload(wrb);
1071
1072         *link_up = false;
1073
1074         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1075                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1076
1077         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1078                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1079
1080         status = be_mcc_notify_wait(adapter);
1081         if (!status) {
1082                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1083                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1084                         *link_up = true;
1085                         *link_speed = le16_to_cpu(resp->link_speed);
1086                         *mac_speed = resp->mac_speed;
1087                 }
1088         }
1089
1090 err:
1091         spin_unlock_bh(&adapter->mcc_lock);
1092         return status;
1093 }
1094
1095 /* Uses Mbox */
1096 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1097 {
1098         struct be_mcc_wrb *wrb;
1099         struct be_cmd_req_get_fw_version *req;
1100         int status;
1101
1102         spin_lock(&adapter->mbox_lock);
1103
1104         wrb = wrb_from_mbox(adapter);
1105         req = embedded_payload(wrb);
1106
1107         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1108                         OPCODE_COMMON_GET_FW_VERSION);
1109
1110         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1111                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1112
1113         status = be_mbox_notify_wait(adapter);
1114         if (!status) {
1115                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1116                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1117         }
1118
1119         spin_unlock(&adapter->mbox_lock);
1120         return status;
1121 }
1122
1123 /* set the EQ delay interval of an EQ to specified value
1124  * Uses async mcc
1125  */
1126 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1127 {
1128         struct be_mcc_wrb *wrb;
1129         struct be_cmd_req_modify_eq_delay *req;
1130         int status = 0;
1131
1132         spin_lock_bh(&adapter->mcc_lock);
1133
1134         wrb = wrb_from_mccq(adapter);
1135         if (!wrb) {
1136                 status = -EBUSY;
1137                 goto err;
1138         }
1139         req = embedded_payload(wrb);
1140
1141         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1142                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1143
1144         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1145                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1146
1147         req->num_eq = cpu_to_le32(1);
1148         req->delay[0].eq_id = cpu_to_le32(eq_id);
1149         req->delay[0].phase = 0;
1150         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1151
1152         be_mcc_notify(adapter);
1153
1154 err:
1155         spin_unlock_bh(&adapter->mcc_lock);
1156         return status;
1157 }
1158
1159 /* Uses sycnhronous mcc */
1160 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1161                         u32 num, bool untagged, bool promiscuous)
1162 {
1163         struct be_mcc_wrb *wrb;
1164         struct be_cmd_req_vlan_config *req;
1165         int status;
1166
1167         spin_lock_bh(&adapter->mcc_lock);
1168
1169         wrb = wrb_from_mccq(adapter);
1170         if (!wrb) {
1171                 status = -EBUSY;
1172                 goto err;
1173         }
1174         req = embedded_payload(wrb);
1175
1176         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1177                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1178
1179         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1180                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1181
1182         req->interface_id = if_id;
1183         req->promiscuous = promiscuous;
1184         req->untagged = untagged;
1185         req->num_vlan = num;
1186         if (!promiscuous) {
1187                 memcpy(req->normal_vlan, vtag_array,
1188                         req->num_vlan * sizeof(vtag_array[0]));
1189         }
1190
1191         status = be_mcc_notify_wait(adapter);
1192
1193 err:
1194         spin_unlock_bh(&adapter->mcc_lock);
1195         return status;
1196 }
1197
1198 /* Uses MCC for this command as it may be called in BH context
1199  * Uses synchronous mcc
1200  */
1201 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1202 {
1203         struct be_mcc_wrb *wrb;
1204         struct be_cmd_req_promiscuous_config *req;
1205         int status;
1206
1207         spin_lock_bh(&adapter->mcc_lock);
1208
1209         wrb = wrb_from_mccq(adapter);
1210         if (!wrb) {
1211                 status = -EBUSY;
1212                 goto err;
1213         }
1214         req = embedded_payload(wrb);
1215
1216         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1217
1218         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1219                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1220
1221         /* In FW versions X.102.149/X.101.487 and later,
1222          * the port setting associated only with the
1223          * issuing pci function will take effect
1224          */
1225         if (port_num)
1226                 req->port1_promiscuous = en;
1227         else
1228                 req->port0_promiscuous = en;
1229
1230         status = be_mcc_notify_wait(adapter);
1231
1232 err:
1233         spin_unlock_bh(&adapter->mcc_lock);
1234         return status;
1235 }
1236
1237 /*
1238  * Uses MCC for this command as it may be called in BH context
1239  * (mc == NULL) => multicast promiscous
1240  */
1241 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1242                 struct net_device *netdev, struct be_dma_mem *mem)
1243 {
1244         struct be_mcc_wrb *wrb;
1245         struct be_cmd_req_mcast_mac_config *req = mem->va;
1246         struct be_sge *sge;
1247         int status;
1248
1249         spin_lock_bh(&adapter->mcc_lock);
1250
1251         wrb = wrb_from_mccq(adapter);
1252         if (!wrb) {
1253                 status = -EBUSY;
1254                 goto err;
1255         }
1256         sge = nonembedded_sgl(wrb);
1257         memset(req, 0, sizeof(*req));
1258
1259         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1260                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1261         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1262         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1263         sge->len = cpu_to_le32(mem->size);
1264
1265         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1266                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1267
1268         req->interface_id = if_id;
1269         if (netdev) {
1270                 int i;
1271                 struct netdev_hw_addr *ha;
1272
1273                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1274
1275                 i = 0;
1276                 netdev_for_each_mc_addr(ha, netdev)
1277                         memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1278         } else {
1279                 req->promiscuous = 1;
1280         }
1281
1282         status = be_mcc_notify_wait(adapter);
1283
1284 err:
1285         spin_unlock_bh(&adapter->mcc_lock);
1286         return status;
1287 }
1288
1289 /* Uses synchrounous mcc */
1290 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1291 {
1292         struct be_mcc_wrb *wrb;
1293         struct be_cmd_req_set_flow_control *req;
1294         int status;
1295
1296         spin_lock_bh(&adapter->mcc_lock);
1297
1298         wrb = wrb_from_mccq(adapter);
1299         if (!wrb) {
1300                 status = -EBUSY;
1301                 goto err;
1302         }
1303         req = embedded_payload(wrb);
1304
1305         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1306                         OPCODE_COMMON_SET_FLOW_CONTROL);
1307
1308         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1309                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1310
1311         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1312         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1313
1314         status = be_mcc_notify_wait(adapter);
1315
1316 err:
1317         spin_unlock_bh(&adapter->mcc_lock);
1318         return status;
1319 }
1320
1321 /* Uses sycn mcc */
1322 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1323 {
1324         struct be_mcc_wrb *wrb;
1325         struct be_cmd_req_get_flow_control *req;
1326         int status;
1327
1328         spin_lock_bh(&adapter->mcc_lock);
1329
1330         wrb = wrb_from_mccq(adapter);
1331         if (!wrb) {
1332                 status = -EBUSY;
1333                 goto err;
1334         }
1335         req = embedded_payload(wrb);
1336
1337         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1338                         OPCODE_COMMON_GET_FLOW_CONTROL);
1339
1340         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1341                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1342
1343         status = be_mcc_notify_wait(adapter);
1344         if (!status) {
1345                 struct be_cmd_resp_get_flow_control *resp =
1346                                                 embedded_payload(wrb);
1347                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1348                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1349         }
1350
1351 err:
1352         spin_unlock_bh(&adapter->mcc_lock);
1353         return status;
1354 }
1355
1356 /* Uses mbox */
1357 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1358                 u32 *mode, u32 *caps)
1359 {
1360         struct be_mcc_wrb *wrb;
1361         struct be_cmd_req_query_fw_cfg *req;
1362         int status;
1363
1364         spin_lock(&adapter->mbox_lock);
1365
1366         wrb = wrb_from_mbox(adapter);
1367         req = embedded_payload(wrb);
1368
1369         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1370                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1371
1372         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1373                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1374
1375         status = be_mbox_notify_wait(adapter);
1376         if (!status) {
1377                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1378                 *port_num = le32_to_cpu(resp->phys_port);
1379                 *mode = le32_to_cpu(resp->function_mode);
1380                 *caps = le32_to_cpu(resp->function_caps);
1381         }
1382
1383         spin_unlock(&adapter->mbox_lock);
1384         return status;
1385 }
1386
1387 /* Uses mbox */
1388 int be_cmd_reset_function(struct be_adapter *adapter)
1389 {
1390         struct be_mcc_wrb *wrb;
1391         struct be_cmd_req_hdr *req;
1392         int status;
1393
1394         spin_lock(&adapter->mbox_lock);
1395
1396         wrb = wrb_from_mbox(adapter);
1397         req = embedded_payload(wrb);
1398
1399         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1400                         OPCODE_COMMON_FUNCTION_RESET);
1401
1402         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1403                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1404
1405         status = be_mbox_notify_wait(adapter);
1406
1407         spin_unlock(&adapter->mbox_lock);
1408         return status;
1409 }
1410
1411 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1412 {
1413         struct be_mcc_wrb *wrb;
1414         struct be_cmd_req_rss_config *req;
1415         u32 myhash[10];
1416         int status;
1417
1418         spin_lock(&adapter->mbox_lock);
1419
1420         wrb = wrb_from_mbox(adapter);
1421         req = embedded_payload(wrb);
1422
1423         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1424                 OPCODE_ETH_RSS_CONFIG);
1425
1426         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1427                 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1428
1429         req->if_id = cpu_to_le32(adapter->if_handle);
1430         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1431         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1432         memcpy(req->cpu_table, rsstable, table_size);
1433         memcpy(req->hash, myhash, sizeof(myhash));
1434         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1435
1436         status = be_mbox_notify_wait(adapter);
1437
1438         spin_unlock(&adapter->mbox_lock);
1439         return status;
1440 }
1441
1442 /* Uses sync mcc */
1443 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1444                         u8 bcn, u8 sts, u8 state)
1445 {
1446         struct be_mcc_wrb *wrb;
1447         struct be_cmd_req_enable_disable_beacon *req;
1448         int status;
1449
1450         spin_lock_bh(&adapter->mcc_lock);
1451
1452         wrb = wrb_from_mccq(adapter);
1453         if (!wrb) {
1454                 status = -EBUSY;
1455                 goto err;
1456         }
1457         req = embedded_payload(wrb);
1458
1459         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1460                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1461
1462         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1463                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1464
1465         req->port_num = port_num;
1466         req->beacon_state = state;
1467         req->beacon_duration = bcn;
1468         req->status_duration = sts;
1469
1470         status = be_mcc_notify_wait(adapter);
1471
1472 err:
1473         spin_unlock_bh(&adapter->mcc_lock);
1474         return status;
1475 }
1476
1477 /* Uses sync mcc */
1478 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1479 {
1480         struct be_mcc_wrb *wrb;
1481         struct be_cmd_req_get_beacon_state *req;
1482         int status;
1483
1484         spin_lock_bh(&adapter->mcc_lock);
1485
1486         wrb = wrb_from_mccq(adapter);
1487         if (!wrb) {
1488                 status = -EBUSY;
1489                 goto err;
1490         }
1491         req = embedded_payload(wrb);
1492
1493         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1494                         OPCODE_COMMON_GET_BEACON_STATE);
1495
1496         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1497                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1498
1499         req->port_num = port_num;
1500
1501         status = be_mcc_notify_wait(adapter);
1502         if (!status) {
1503                 struct be_cmd_resp_get_beacon_state *resp =
1504                                                 embedded_payload(wrb);
1505                 *state = resp->beacon_state;
1506         }
1507
1508 err:
1509         spin_unlock_bh(&adapter->mcc_lock);
1510         return status;
1511 }
1512
1513 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1514                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1515 {
1516         struct be_mcc_wrb *wrb;
1517         struct be_cmd_write_flashrom *req;
1518         struct be_sge *sge;
1519         int status;
1520
1521         spin_lock_bh(&adapter->mcc_lock);
1522         adapter->flash_status = 0;
1523
1524         wrb = wrb_from_mccq(adapter);
1525         if (!wrb) {
1526                 status = -EBUSY;
1527                 goto err_unlock;
1528         }
1529         req = cmd->va;
1530         sge = nonembedded_sgl(wrb);
1531
1532         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1533                         OPCODE_COMMON_WRITE_FLASHROM);
1534         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1535
1536         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1537                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1538         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1539         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1540         sge->len = cpu_to_le32(cmd->size);
1541
1542         req->params.op_type = cpu_to_le32(flash_type);
1543         req->params.op_code = cpu_to_le32(flash_opcode);
1544         req->params.data_buf_size = cpu_to_le32(buf_size);
1545
1546         be_mcc_notify(adapter);
1547         spin_unlock_bh(&adapter->mcc_lock);
1548
1549         if (!wait_for_completion_timeout(&adapter->flash_compl,
1550                         msecs_to_jiffies(12000)))
1551                 status = -1;
1552         else
1553                 status = adapter->flash_status;
1554
1555         return status;
1556
1557 err_unlock:
1558         spin_unlock_bh(&adapter->mcc_lock);
1559         return status;
1560 }
1561
1562 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1563                          int offset)
1564 {
1565         struct be_mcc_wrb *wrb;
1566         struct be_cmd_write_flashrom *req;
1567         int status;
1568
1569         spin_lock_bh(&adapter->mcc_lock);
1570
1571         wrb = wrb_from_mccq(adapter);
1572         if (!wrb) {
1573                 status = -EBUSY;
1574                 goto err;
1575         }
1576         req = embedded_payload(wrb);
1577
1578         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1579                         OPCODE_COMMON_READ_FLASHROM);
1580
1581         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1582                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1583
1584         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1585         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1586         req->params.offset = cpu_to_le32(offset);
1587         req->params.data_buf_size = cpu_to_le32(0x4);
1588
1589         status = be_mcc_notify_wait(adapter);
1590         if (!status)
1591                 memcpy(flashed_crc, req->params.data_buf, 4);
1592
1593 err:
1594         spin_unlock_bh(&adapter->mcc_lock);
1595         return status;
1596 }
1597
1598 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1599                                 struct be_dma_mem *nonemb_cmd)
1600 {
1601         struct be_mcc_wrb *wrb;
1602         struct be_cmd_req_acpi_wol_magic_config *req;
1603         struct be_sge *sge;
1604         int status;
1605
1606         spin_lock_bh(&adapter->mcc_lock);
1607
1608         wrb = wrb_from_mccq(adapter);
1609         if (!wrb) {
1610                 status = -EBUSY;
1611                 goto err;
1612         }
1613         req = nonemb_cmd->va;
1614         sge = nonembedded_sgl(wrb);
1615
1616         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1617                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1618
1619         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1620                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1621         memcpy(req->magic_mac, mac, ETH_ALEN);
1622
1623         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1624         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1625         sge->len = cpu_to_le32(nonemb_cmd->size);
1626
1627         status = be_mcc_notify_wait(adapter);
1628
1629 err:
1630         spin_unlock_bh(&adapter->mcc_lock);
1631         return status;
1632 }
1633
1634 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1635                         u8 loopback_type, u8 enable)
1636 {
1637         struct be_mcc_wrb *wrb;
1638         struct be_cmd_req_set_lmode *req;
1639         int status;
1640
1641         spin_lock_bh(&adapter->mcc_lock);
1642
1643         wrb = wrb_from_mccq(adapter);
1644         if (!wrb) {
1645                 status = -EBUSY;
1646                 goto err;
1647         }
1648
1649         req = embedded_payload(wrb);
1650
1651         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1652                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1653
1654         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1655                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1656                         sizeof(*req));
1657
1658         req->src_port = port_num;
1659         req->dest_port = port_num;
1660         req->loopback_type = loopback_type;
1661         req->loopback_state = enable;
1662
1663         status = be_mcc_notify_wait(adapter);
1664 err:
1665         spin_unlock_bh(&adapter->mcc_lock);
1666         return status;
1667 }
1668
1669 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1670                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1671 {
1672         struct be_mcc_wrb *wrb;
1673         struct be_cmd_req_loopback_test *req;
1674         int status;
1675
1676         spin_lock_bh(&adapter->mcc_lock);
1677
1678         wrb = wrb_from_mccq(adapter);
1679         if (!wrb) {
1680                 status = -EBUSY;
1681                 goto err;
1682         }
1683
1684         req = embedded_payload(wrb);
1685
1686         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1687                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1688
1689         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1690                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1691         req->hdr.timeout = cpu_to_le32(4);
1692
1693         req->pattern = cpu_to_le64(pattern);
1694         req->src_port = cpu_to_le32(port_num);
1695         req->dest_port = cpu_to_le32(port_num);
1696         req->pkt_size = cpu_to_le32(pkt_size);
1697         req->num_pkts = cpu_to_le32(num_pkts);
1698         req->loopback_type = cpu_to_le32(loopback_type);
1699
1700         status = be_mcc_notify_wait(adapter);
1701         if (!status) {
1702                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1703                 status = le32_to_cpu(resp->status);
1704         }
1705
1706 err:
1707         spin_unlock_bh(&adapter->mcc_lock);
1708         return status;
1709 }
1710
1711 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1712                                 u32 byte_cnt, struct be_dma_mem *cmd)
1713 {
1714         struct be_mcc_wrb *wrb;
1715         struct be_cmd_req_ddrdma_test *req;
1716         struct be_sge *sge;
1717         int status;
1718         int i, j = 0;
1719
1720         spin_lock_bh(&adapter->mcc_lock);
1721
1722         wrb = wrb_from_mccq(adapter);
1723         if (!wrb) {
1724                 status = -EBUSY;
1725                 goto err;
1726         }
1727         req = cmd->va;
1728         sge = nonembedded_sgl(wrb);
1729         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1730                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1731         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1732                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1733
1734         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1735         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1736         sge->len = cpu_to_le32(cmd->size);
1737
1738         req->pattern = cpu_to_le64(pattern);
1739         req->byte_count = cpu_to_le32(byte_cnt);
1740         for (i = 0; i < byte_cnt; i++) {
1741                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1742                 j++;
1743                 if (j > 7)
1744                         j = 0;
1745         }
1746
1747         status = be_mcc_notify_wait(adapter);
1748
1749         if (!status) {
1750                 struct be_cmd_resp_ddrdma_test *resp;
1751                 resp = cmd->va;
1752                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1753                                 resp->snd_err) {
1754                         status = -1;
1755                 }
1756         }
1757
1758 err:
1759         spin_unlock_bh(&adapter->mcc_lock);
1760         return status;
1761 }
1762
1763 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1764                                 struct be_dma_mem *nonemb_cmd)
1765 {
1766         struct be_mcc_wrb *wrb;
1767         struct be_cmd_req_seeprom_read *req;
1768         struct be_sge *sge;
1769         int status;
1770
1771         spin_lock_bh(&adapter->mcc_lock);
1772
1773         wrb = wrb_from_mccq(adapter);
1774         req = nonemb_cmd->va;
1775         sge = nonembedded_sgl(wrb);
1776
1777         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1778                         OPCODE_COMMON_SEEPROM_READ);
1779
1780         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1781                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1782
1783         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1784         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1785         sge->len = cpu_to_le32(nonemb_cmd->size);
1786
1787         status = be_mcc_notify_wait(adapter);
1788
1789         spin_unlock_bh(&adapter->mcc_lock);
1790         return status;
1791 }
1792
1793 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1794 {
1795         struct be_mcc_wrb *wrb;
1796         struct be_cmd_req_get_phy_info *req;
1797         struct be_sge *sge;
1798         int status;
1799
1800         spin_lock_bh(&adapter->mcc_lock);
1801
1802         wrb = wrb_from_mccq(adapter);
1803         if (!wrb) {
1804                 status = -EBUSY;
1805                 goto err;
1806         }
1807
1808         req = cmd->va;
1809         sge = nonembedded_sgl(wrb);
1810
1811         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1812                                 OPCODE_COMMON_GET_PHY_DETAILS);
1813
1814         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1815                         OPCODE_COMMON_GET_PHY_DETAILS,
1816                         sizeof(*req));
1817
1818         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1819         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1820         sge->len = cpu_to_le32(cmd->size);
1821
1822         status = be_mcc_notify_wait(adapter);
1823 err:
1824         spin_unlock_bh(&adapter->mcc_lock);
1825         return status;
1826 }
1827
1828 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1829 {
1830         struct be_mcc_wrb *wrb;
1831         struct be_cmd_req_set_qos *req;
1832         int status;
1833
1834         spin_lock_bh(&adapter->mcc_lock);
1835
1836         wrb = wrb_from_mccq(adapter);
1837         if (!wrb) {
1838                 status = -EBUSY;
1839                 goto err;
1840         }
1841
1842         req = embedded_payload(wrb);
1843
1844         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1845                                 OPCODE_COMMON_SET_QOS);
1846
1847         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1848                         OPCODE_COMMON_SET_QOS, sizeof(*req));
1849
1850         req->hdr.domain = domain;
1851         req->valid_bits = BE_QOS_BITS_NIC;
1852         req->max_bps_nic = bps;
1853
1854         status = be_mcc_notify_wait(adapter);
1855
1856 err:
1857         spin_unlock_bh(&adapter->mcc_lock);
1858         return status;
1859 }