2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 32;
24 static void be_mcc_notify(struct be_adapter *adapter)
26 struct be_queue_info *mccq = &adapter->mcc_obj.q;
29 if (adapter->eeh_err) {
30 dev_info(&adapter->pdev->dev,
31 "Error in Card Detected! Cannot issue commands\n");
35 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
36 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
39 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
42 /* To check if valid bit is set, check the entire word as we don't know
43 * the endianness of the data (old entry is host endian while a new entry is
45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
47 if (compl->flags != 0) {
48 compl->flags = le32_to_cpu(compl->flags);
49 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
56 /* Need to reset the entire word that houses the valid bit */
57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
62 static int be_mcc_compl_process(struct be_adapter *adapter,
63 struct be_mcc_compl *compl)
65 u16 compl_status, extd_status;
67 /* Just swap the status to host endian; mcc tag is opaquely copied
69 be_dws_le_to_cpu(compl, 4);
71 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
72 CQE_STATUS_COMPL_MASK;
74 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
75 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
76 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
77 adapter->flash_status = compl_status;
78 complete(&adapter->flash_compl);
81 if (compl_status == MCC_STATUS_SUCCESS) {
82 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
83 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
84 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
85 if (adapter->generation == BE_GEN3) {
86 if (lancer_chip(adapter)) {
87 struct lancer_cmd_resp_pport_stats
88 *resp = adapter->stats_cmd.va;
89 be_dws_le_to_cpu(&resp->pport_stats,
90 sizeof(resp->pport_stats));
92 struct be_cmd_resp_get_stats_v1 *resp =
93 adapter->stats_cmd.va;
95 be_dws_le_to_cpu(&resp->hw_stats,
96 sizeof(resp->hw_stats));
99 struct be_cmd_resp_get_stats_v0 *resp =
100 adapter->stats_cmd.va;
102 be_dws_le_to_cpu(&resp->hw_stats,
103 sizeof(resp->hw_stats));
105 be_parse_stats(adapter);
106 netdev_stats_update(adapter);
107 adapter->stats_cmd_sent = false;
110 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
111 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
114 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
115 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
116 "permitted to execute this cmd (opcode %d)\n",
119 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
120 CQE_STATUS_EXTD_MASK;
121 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
122 "status %d, extd-status %d\n",
123 compl->tag0, compl_status, extd_status);
130 /* Link state evt is a string of bytes; no need for endian swapping */
131 static void be_async_link_state_process(struct be_adapter *adapter,
132 struct be_async_event_link_state *evt)
134 be_link_status_update(adapter,
135 evt->port_link_status == ASYNC_EVENT_LINK_UP);
138 /* Grp5 CoS Priority evt */
139 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
140 struct be_async_event_grp5_cos_priority *evt)
143 adapter->vlan_prio_bmap = evt->available_priority_bmap;
144 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
145 adapter->recommended_prio =
146 evt->reco_default_priority << VLAN_PRIO_SHIFT;
150 /* Grp5 QOS Speed evt */
151 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
152 struct be_async_event_grp5_qos_link_speed *evt)
154 if (evt->physical_port == adapter->port_num) {
155 /* qos_link_speed is in units of 10 Mbps */
156 adapter->link_speed = evt->qos_link_speed * 10;
161 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
162 struct be_async_event_grp5_pvid_state *evt)
165 adapter->pvid = le16_to_cpu(evt->tag);
170 static void be_async_grp5_evt_process(struct be_adapter *adapter,
171 u32 trailer, struct be_mcc_compl *evt)
175 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
176 ASYNC_TRAILER_EVENT_TYPE_MASK;
178 switch (event_type) {
179 case ASYNC_EVENT_COS_PRIORITY:
180 be_async_grp5_cos_priority_process(adapter,
181 (struct be_async_event_grp5_cos_priority *)evt);
183 case ASYNC_EVENT_QOS_SPEED:
184 be_async_grp5_qos_speed_process(adapter,
185 (struct be_async_event_grp5_qos_link_speed *)evt);
187 case ASYNC_EVENT_PVID_STATE:
188 be_async_grp5_pvid_state_process(adapter,
189 (struct be_async_event_grp5_pvid_state *)evt);
192 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
197 static inline bool is_link_state_evt(u32 trailer)
199 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
200 ASYNC_TRAILER_EVENT_CODE_MASK) ==
201 ASYNC_EVENT_CODE_LINK_STATE;
204 static inline bool is_grp5_evt(u32 trailer)
206 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
207 ASYNC_TRAILER_EVENT_CODE_MASK) ==
208 ASYNC_EVENT_CODE_GRP_5);
211 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
213 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
214 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
216 if (be_mcc_compl_is_new(compl)) {
217 queue_tail_inc(mcc_cq);
223 void be_async_mcc_enable(struct be_adapter *adapter)
225 spin_lock_bh(&adapter->mcc_cq_lock);
227 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
228 adapter->mcc_obj.rearm_cq = true;
230 spin_unlock_bh(&adapter->mcc_cq_lock);
233 void be_async_mcc_disable(struct be_adapter *adapter)
235 adapter->mcc_obj.rearm_cq = false;
238 int be_process_mcc(struct be_adapter *adapter, int *status)
240 struct be_mcc_compl *compl;
242 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
244 spin_lock_bh(&adapter->mcc_cq_lock);
245 while ((compl = be_mcc_compl_get(adapter))) {
246 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
247 /* Interpret flags as an async trailer */
248 if (is_link_state_evt(compl->flags))
249 be_async_link_state_process(adapter,
250 (struct be_async_event_link_state *) compl);
251 else if (is_grp5_evt(compl->flags))
252 be_async_grp5_evt_process(adapter,
253 compl->flags, compl);
254 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
255 *status = be_mcc_compl_process(adapter, compl);
256 atomic_dec(&mcc_obj->q.used);
258 be_mcc_compl_use(compl);
262 spin_unlock_bh(&adapter->mcc_cq_lock);
266 /* Wait till no more pending mcc requests are present */
267 static int be_mcc_wait_compl(struct be_adapter *adapter)
269 #define mcc_timeout 120000 /* 12s timeout */
270 int i, num, status = 0;
271 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
273 if (adapter->eeh_err)
276 for (i = 0; i < mcc_timeout; i++) {
277 num = be_process_mcc(adapter, &status);
279 be_cq_notify(adapter, mcc_obj->cq.id,
280 mcc_obj->rearm_cq, num);
282 if (atomic_read(&mcc_obj->q.used) == 0)
286 if (i == mcc_timeout) {
287 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
293 /* Notify MCC requests and wait for completion */
294 static int be_mcc_notify_wait(struct be_adapter *adapter)
296 be_mcc_notify(adapter);
297 return be_mcc_wait_compl(adapter);
300 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
305 if (adapter->eeh_err) {
306 dev_err(&adapter->pdev->dev,
307 "Error detected in card.Cannot issue commands\n");
312 ready = ioread32(db);
313 if (ready == 0xffffffff) {
314 dev_err(&adapter->pdev->dev,
315 "pci slot disconnected\n");
319 ready &= MPU_MAILBOX_DB_RDY_MASK;
324 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
325 if (!lancer_chip(adapter))
326 be_detect_dump_ue(adapter);
338 * Insert the mailbox address into the doorbell in two steps
339 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
341 static int be_mbox_notify_wait(struct be_adapter *adapter)
345 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
346 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
347 struct be_mcc_mailbox *mbox = mbox_mem->va;
348 struct be_mcc_compl *compl = &mbox->compl;
350 /* wait for ready to be set */
351 status = be_mbox_db_ready_wait(adapter, db);
355 val |= MPU_MAILBOX_DB_HI_MASK;
356 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
357 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
360 /* wait for ready to be set */
361 status = be_mbox_db_ready_wait(adapter, db);
366 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
367 val |= (u32)(mbox_mem->dma >> 4) << 2;
370 status = be_mbox_db_ready_wait(adapter, db);
374 /* A cq entry has been made now */
375 if (be_mcc_compl_is_new(compl)) {
376 status = be_mcc_compl_process(adapter, &mbox->compl);
377 be_mcc_compl_use(compl);
381 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
387 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
391 if (lancer_chip(adapter))
392 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
394 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
396 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
397 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
403 int be_cmd_POST(struct be_adapter *adapter)
406 int status, timeout = 0;
407 struct device *dev = &adapter->pdev->dev;
410 status = be_POST_stage_get(adapter, &stage);
412 dev_err(dev, "POST error; stage=0x%x\n", stage);
414 } else if (stage != POST_STAGE_ARMFW_RDY) {
415 if (msleep_interruptible(2000)) {
416 dev_err(dev, "Waiting for POST aborted\n");
423 } while (timeout < 40);
425 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
429 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
431 return wrb->payload.embedded_payload;
434 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
436 return &wrb->payload.sgl[0];
439 /* Don't touch the hdr after it's prepared */
440 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
441 bool embedded, u8 sge_cnt, u32 opcode)
444 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
446 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
447 MCC_WRB_SGE_CNT_SHIFT;
448 wrb->payload_length = payload_len;
450 be_dws_cpu_to_le(wrb, 8);
453 /* Don't touch the hdr after it's prepared */
454 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
455 u8 subsystem, u8 opcode, int cmd_len)
457 req_hdr->opcode = opcode;
458 req_hdr->subsystem = subsystem;
459 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
460 req_hdr->version = 0;
463 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
464 struct be_dma_mem *mem)
466 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
467 u64 dma = (u64)mem->dma;
469 for (i = 0; i < buf_pages; i++) {
470 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
471 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
476 /* Converts interrupt delay in microseconds to multiplier value */
477 static u32 eq_delay_to_mult(u32 usec_delay)
479 #define MAX_INTR_RATE 651042
480 const u32 round = 10;
486 u32 interrupt_rate = 1000000 / usec_delay;
487 /* Max delay, corresponding to the lowest interrupt rate */
488 if (interrupt_rate == 0)
491 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
492 multiplier /= interrupt_rate;
493 /* Round the multiplier to the closest value.*/
494 multiplier = (multiplier + round/2) / round;
495 multiplier = min(multiplier, (u32)1023);
501 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
503 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
504 struct be_mcc_wrb *wrb
505 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
506 memset(wrb, 0, sizeof(*wrb));
510 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
512 struct be_queue_info *mccq = &adapter->mcc_obj.q;
513 struct be_mcc_wrb *wrb;
515 if (atomic_read(&mccq->used) >= mccq->len) {
516 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
520 wrb = queue_head_node(mccq);
521 queue_head_inc(mccq);
522 atomic_inc(&mccq->used);
523 memset(wrb, 0, sizeof(*wrb));
527 /* Tell fw we're about to start firing cmds by writing a
528 * special pattern across the wrb hdr; uses mbox
530 int be_cmd_fw_init(struct be_adapter *adapter)
535 if (mutex_lock_interruptible(&adapter->mbox_lock))
538 wrb = (u8 *)wrb_from_mbox(adapter);
548 status = be_mbox_notify_wait(adapter);
550 mutex_unlock(&adapter->mbox_lock);
554 /* Tell fw we're done with firing cmds by writing a
555 * special pattern across the wrb hdr; uses mbox
557 int be_cmd_fw_clean(struct be_adapter *adapter)
562 if (adapter->eeh_err)
565 if (mutex_lock_interruptible(&adapter->mbox_lock))
568 wrb = (u8 *)wrb_from_mbox(adapter);
578 status = be_mbox_notify_wait(adapter);
580 mutex_unlock(&adapter->mbox_lock);
583 int be_cmd_eq_create(struct be_adapter *adapter,
584 struct be_queue_info *eq, int eq_delay)
586 struct be_mcc_wrb *wrb;
587 struct be_cmd_req_eq_create *req;
588 struct be_dma_mem *q_mem = &eq->dma_mem;
591 if (mutex_lock_interruptible(&adapter->mbox_lock))
594 wrb = wrb_from_mbox(adapter);
595 req = embedded_payload(wrb);
597 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
599 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
600 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
602 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
604 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
606 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
607 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
608 __ilog2_u32(eq->len/256));
609 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
610 eq_delay_to_mult(eq_delay));
611 be_dws_cpu_to_le(req->context, sizeof(req->context));
613 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
615 status = be_mbox_notify_wait(adapter);
617 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
618 eq->id = le16_to_cpu(resp->eq_id);
622 mutex_unlock(&adapter->mbox_lock);
627 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
628 u8 type, bool permanent, u32 if_handle)
630 struct be_mcc_wrb *wrb;
631 struct be_cmd_req_mac_query *req;
634 if (mutex_lock_interruptible(&adapter->mbox_lock))
637 wrb = wrb_from_mbox(adapter);
638 req = embedded_payload(wrb);
640 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
641 OPCODE_COMMON_NTWK_MAC_QUERY);
643 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
644 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
650 req->if_id = cpu_to_le16((u16) if_handle);
654 status = be_mbox_notify_wait(adapter);
656 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
657 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
660 mutex_unlock(&adapter->mbox_lock);
664 /* Uses synchronous MCCQ */
665 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
666 u32 if_id, u32 *pmac_id, u32 domain)
668 struct be_mcc_wrb *wrb;
669 struct be_cmd_req_pmac_add *req;
672 spin_lock_bh(&adapter->mcc_lock);
674 wrb = wrb_from_mccq(adapter);
679 req = embedded_payload(wrb);
681 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
682 OPCODE_COMMON_NTWK_PMAC_ADD);
684 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
685 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
687 req->hdr.domain = domain;
688 req->if_id = cpu_to_le32(if_id);
689 memcpy(req->mac_address, mac_addr, ETH_ALEN);
691 status = be_mcc_notify_wait(adapter);
693 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
694 *pmac_id = le32_to_cpu(resp->pmac_id);
698 spin_unlock_bh(&adapter->mcc_lock);
702 /* Uses synchronous MCCQ */
703 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
705 struct be_mcc_wrb *wrb;
706 struct be_cmd_req_pmac_del *req;
709 spin_lock_bh(&adapter->mcc_lock);
711 wrb = wrb_from_mccq(adapter);
716 req = embedded_payload(wrb);
718 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
719 OPCODE_COMMON_NTWK_PMAC_DEL);
721 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
722 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
724 req->hdr.domain = dom;
725 req->if_id = cpu_to_le32(if_id);
726 req->pmac_id = cpu_to_le32(pmac_id);
728 status = be_mcc_notify_wait(adapter);
731 spin_unlock_bh(&adapter->mcc_lock);
736 int be_cmd_cq_create(struct be_adapter *adapter,
737 struct be_queue_info *cq, struct be_queue_info *eq,
738 bool sol_evts, bool no_delay, int coalesce_wm)
740 struct be_mcc_wrb *wrb;
741 struct be_cmd_req_cq_create *req;
742 struct be_dma_mem *q_mem = &cq->dma_mem;
746 if (mutex_lock_interruptible(&adapter->mbox_lock))
749 wrb = wrb_from_mbox(adapter);
750 req = embedded_payload(wrb);
751 ctxt = &req->context;
753 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
754 OPCODE_COMMON_CQ_CREATE);
756 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
757 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
759 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
760 if (lancer_chip(adapter)) {
761 req->hdr.version = 2;
762 req->page_size = 1; /* 1 for 4K */
763 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
765 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
766 __ilog2_u32(cq->len/256));
767 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
768 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
770 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
772 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
774 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
776 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
778 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
779 __ilog2_u32(cq->len/256));
780 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
781 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
783 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
784 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
785 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
788 be_dws_cpu_to_le(ctxt, sizeof(req->context));
790 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
792 status = be_mbox_notify_wait(adapter);
794 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
795 cq->id = le16_to_cpu(resp->cq_id);
799 mutex_unlock(&adapter->mbox_lock);
804 static u32 be_encoded_q_len(int q_len)
806 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
807 if (len_encoded == 16)
812 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
813 struct be_queue_info *mccq,
814 struct be_queue_info *cq)
816 struct be_mcc_wrb *wrb;
817 struct be_cmd_req_mcc_ext_create *req;
818 struct be_dma_mem *q_mem = &mccq->dma_mem;
822 if (mutex_lock_interruptible(&adapter->mbox_lock))
825 wrb = wrb_from_mbox(adapter);
826 req = embedded_payload(wrb);
827 ctxt = &req->context;
829 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
830 OPCODE_COMMON_MCC_CREATE_EXT);
832 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
833 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
835 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
836 if (lancer_chip(adapter)) {
837 req->hdr.version = 1;
838 req->cq_id = cpu_to_le16(cq->id);
840 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
841 be_encoded_q_len(mccq->len));
842 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
843 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
845 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
849 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
850 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
851 be_encoded_q_len(mccq->len));
852 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
855 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
856 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
857 be_dws_cpu_to_le(ctxt, sizeof(req->context));
859 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
861 status = be_mbox_notify_wait(adapter);
863 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
864 mccq->id = le16_to_cpu(resp->id);
865 mccq->created = true;
867 mutex_unlock(&adapter->mbox_lock);
872 int be_cmd_mccq_org_create(struct be_adapter *adapter,
873 struct be_queue_info *mccq,
874 struct be_queue_info *cq)
876 struct be_mcc_wrb *wrb;
877 struct be_cmd_req_mcc_create *req;
878 struct be_dma_mem *q_mem = &mccq->dma_mem;
882 if (mutex_lock_interruptible(&adapter->mbox_lock))
885 wrb = wrb_from_mbox(adapter);
886 req = embedded_payload(wrb);
887 ctxt = &req->context;
889 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
890 OPCODE_COMMON_MCC_CREATE);
892 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
893 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
895 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
897 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
898 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
899 be_encoded_q_len(mccq->len));
900 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
902 be_dws_cpu_to_le(ctxt, sizeof(req->context));
904 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
906 status = be_mbox_notify_wait(adapter);
908 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
909 mccq->id = le16_to_cpu(resp->id);
910 mccq->created = true;
913 mutex_unlock(&adapter->mbox_lock);
917 int be_cmd_mccq_create(struct be_adapter *adapter,
918 struct be_queue_info *mccq,
919 struct be_queue_info *cq)
923 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
924 if (status && !lancer_chip(adapter)) {
925 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
926 "or newer to avoid conflicting priorities between NIC "
928 status = be_cmd_mccq_org_create(adapter, mccq, cq);
933 int be_cmd_txq_create(struct be_adapter *adapter,
934 struct be_queue_info *txq,
935 struct be_queue_info *cq)
937 struct be_mcc_wrb *wrb;
938 struct be_cmd_req_eth_tx_create *req;
939 struct be_dma_mem *q_mem = &txq->dma_mem;
943 if (mutex_lock_interruptible(&adapter->mbox_lock))
946 wrb = wrb_from_mbox(adapter);
947 req = embedded_payload(wrb);
948 ctxt = &req->context;
950 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
951 OPCODE_ETH_TX_CREATE);
953 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
956 if (lancer_chip(adapter)) {
957 req->hdr.version = 1;
958 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
962 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
963 req->ulp_num = BE_ULP1_NUM;
964 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
966 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
967 be_encoded_q_len(txq->len));
968 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
969 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
971 be_dws_cpu_to_le(ctxt, sizeof(req->context));
973 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
975 status = be_mbox_notify_wait(adapter);
977 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
978 txq->id = le16_to_cpu(resp->cid);
982 mutex_unlock(&adapter->mbox_lock);
988 int be_cmd_rxq_create(struct be_adapter *adapter,
989 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
990 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
992 struct be_mcc_wrb *wrb;
993 struct be_cmd_req_eth_rx_create *req;
994 struct be_dma_mem *q_mem = &rxq->dma_mem;
997 if (mutex_lock_interruptible(&adapter->mbox_lock))
1000 wrb = wrb_from_mbox(adapter);
1001 req = embedded_payload(wrb);
1003 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1004 OPCODE_ETH_RX_CREATE);
1006 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
1009 req->cq_id = cpu_to_le16(cq_id);
1010 req->frag_size = fls(frag_size) - 1;
1012 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1013 req->interface_id = cpu_to_le32(if_id);
1014 req->max_frame_size = cpu_to_le16(max_frame_size);
1015 req->rss_queue = cpu_to_le32(rss);
1017 status = be_mbox_notify_wait(adapter);
1019 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1020 rxq->id = le16_to_cpu(resp->id);
1021 rxq->created = true;
1022 *rss_id = resp->rss_id;
1025 mutex_unlock(&adapter->mbox_lock);
1030 /* Generic destroyer function for all types of queues
1033 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1036 struct be_mcc_wrb *wrb;
1037 struct be_cmd_req_q_destroy *req;
1038 u8 subsys = 0, opcode = 0;
1041 if (adapter->eeh_err)
1044 if (mutex_lock_interruptible(&adapter->mbox_lock))
1047 wrb = wrb_from_mbox(adapter);
1048 req = embedded_payload(wrb);
1050 switch (queue_type) {
1052 subsys = CMD_SUBSYSTEM_COMMON;
1053 opcode = OPCODE_COMMON_EQ_DESTROY;
1056 subsys = CMD_SUBSYSTEM_COMMON;
1057 opcode = OPCODE_COMMON_CQ_DESTROY;
1060 subsys = CMD_SUBSYSTEM_ETH;
1061 opcode = OPCODE_ETH_TX_DESTROY;
1064 subsys = CMD_SUBSYSTEM_ETH;
1065 opcode = OPCODE_ETH_RX_DESTROY;
1068 subsys = CMD_SUBSYSTEM_COMMON;
1069 opcode = OPCODE_COMMON_MCC_DESTROY;
1075 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
1077 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1078 req->id = cpu_to_le16(q->id);
1080 status = be_mbox_notify_wait(adapter);
1082 mutex_unlock(&adapter->mbox_lock);
1087 /* Create an rx filtering policy configuration on an i/f
1090 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1091 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1094 struct be_mcc_wrb *wrb;
1095 struct be_cmd_req_if_create *req;
1098 if (mutex_lock_interruptible(&adapter->mbox_lock))
1101 wrb = wrb_from_mbox(adapter);
1102 req = embedded_payload(wrb);
1104 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1105 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1107 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1110 req->hdr.domain = domain;
1111 req->capability_flags = cpu_to_le32(cap_flags);
1112 req->enable_flags = cpu_to_le32(en_flags);
1113 req->pmac_invalid = pmac_invalid;
1115 memcpy(req->mac_addr, mac, ETH_ALEN);
1117 status = be_mbox_notify_wait(adapter);
1119 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1120 *if_handle = le32_to_cpu(resp->interface_id);
1122 *pmac_id = le32_to_cpu(resp->pmac_id);
1125 mutex_unlock(&adapter->mbox_lock);
1130 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1132 struct be_mcc_wrb *wrb;
1133 struct be_cmd_req_if_destroy *req;
1136 if (adapter->eeh_err)
1139 if (mutex_lock_interruptible(&adapter->mbox_lock))
1142 wrb = wrb_from_mbox(adapter);
1143 req = embedded_payload(wrb);
1145 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1146 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1148 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1149 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1151 req->hdr.domain = domain;
1152 req->interface_id = cpu_to_le32(interface_id);
1154 status = be_mbox_notify_wait(adapter);
1156 mutex_unlock(&adapter->mbox_lock);
1161 /* Get stats is a non embedded command: the request is not embedded inside
1162 * WRB but is a separate dma memory block
1163 * Uses asynchronous MCC
1165 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1167 struct be_mcc_wrb *wrb;
1168 struct be_cmd_req_hdr *hdr;
1172 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1173 be_cmd_get_die_temperature(adapter);
1175 spin_lock_bh(&adapter->mcc_lock);
1177 wrb = wrb_from_mccq(adapter);
1182 hdr = nonemb_cmd->va;
1183 sge = nonembedded_sgl(wrb);
1185 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1186 OPCODE_ETH_GET_STATISTICS);
1188 be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1189 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1191 if (adapter->generation == BE_GEN3)
1194 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1195 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1196 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1197 sge->len = cpu_to_le32(nonemb_cmd->size);
1199 be_mcc_notify(adapter);
1200 adapter->stats_cmd_sent = true;
1203 spin_unlock_bh(&adapter->mcc_lock);
1208 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209 struct be_dma_mem *nonemb_cmd)
1212 struct be_mcc_wrb *wrb;
1213 struct lancer_cmd_req_pport_stats *req;
1217 spin_lock_bh(&adapter->mcc_lock);
1219 wrb = wrb_from_mccq(adapter);
1224 req = nonemb_cmd->va;
1225 sge = nonembedded_sgl(wrb);
1227 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1228 OPCODE_ETH_GET_PPORT_STATS);
1230 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1231 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1234 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1235 req->cmd_params.params.reset_stats = 0;
1237 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1238 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1239 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1240 sge->len = cpu_to_le32(nonemb_cmd->size);
1242 be_mcc_notify(adapter);
1243 adapter->stats_cmd_sent = true;
1246 spin_unlock_bh(&adapter->mcc_lock);
1250 /* Uses synchronous mcc */
1251 int be_cmd_link_status_query(struct be_adapter *adapter,
1252 bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
1254 struct be_mcc_wrb *wrb;
1255 struct be_cmd_req_link_status *req;
1258 spin_lock_bh(&adapter->mcc_lock);
1260 wrb = wrb_from_mccq(adapter);
1265 req = embedded_payload(wrb);
1269 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1270 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1272 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1273 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1275 status = be_mcc_notify_wait(adapter);
1277 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1278 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1280 *link_speed = le16_to_cpu(resp->link_speed);
1281 *mac_speed = resp->mac_speed;
1286 spin_unlock_bh(&adapter->mcc_lock);
1290 /* Uses synchronous mcc */
1291 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1293 struct be_mcc_wrb *wrb;
1294 struct be_cmd_req_get_cntl_addnl_attribs *req;
1297 spin_lock_bh(&adapter->mcc_lock);
1299 wrb = wrb_from_mccq(adapter);
1304 req = embedded_payload(wrb);
1306 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1307 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1309 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1310 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1312 status = be_mcc_notify_wait(adapter);
1314 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1315 embedded_payload(wrb);
1316 adapter->drv_stats.be_on_die_temperature =
1317 resp->on_die_temperature;
1319 /* If IOCTL fails once, do not bother issuing it again */
1321 be_get_temp_freq = 0;
1324 spin_unlock_bh(&adapter->mcc_lock);
1328 /* Uses synchronous mcc */
1329 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1331 struct be_mcc_wrb *wrb;
1332 struct be_cmd_req_get_fat *req;
1335 spin_lock_bh(&adapter->mcc_lock);
1337 wrb = wrb_from_mccq(adapter);
1342 req = embedded_payload(wrb);
1344 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1345 OPCODE_COMMON_MANAGE_FAT);
1347 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1348 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1349 req->fat_operation = cpu_to_le32(QUERY_FAT);
1350 status = be_mcc_notify_wait(adapter);
1352 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1353 if (log_size && resp->log_size)
1354 *log_size = le32_to_cpu(resp->log_size) -
1358 spin_unlock_bh(&adapter->mcc_lock);
1362 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1364 struct be_dma_mem get_fat_cmd;
1365 struct be_mcc_wrb *wrb;
1366 struct be_cmd_req_get_fat *req;
1368 u32 offset = 0, total_size, buf_size,
1369 log_offset = sizeof(u32), payload_len;
1375 total_size = buf_len;
1377 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1378 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1381 if (!get_fat_cmd.va) {
1383 dev_err(&adapter->pdev->dev,
1384 "Memory allocation failure while retrieving FAT data\n");
1388 spin_lock_bh(&adapter->mcc_lock);
1390 while (total_size) {
1391 buf_size = min(total_size, (u32)60*1024);
1392 total_size -= buf_size;
1394 wrb = wrb_from_mccq(adapter);
1399 req = get_fat_cmd.va;
1400 sge = nonembedded_sgl(wrb);
1402 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1403 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1404 OPCODE_COMMON_MANAGE_FAT);
1406 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1407 OPCODE_COMMON_MANAGE_FAT, payload_len);
1409 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1410 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1411 sge->len = cpu_to_le32(get_fat_cmd.size);
1413 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1414 req->read_log_offset = cpu_to_le32(log_offset);
1415 req->read_log_length = cpu_to_le32(buf_size);
1416 req->data_buffer_size = cpu_to_le32(buf_size);
1418 status = be_mcc_notify_wait(adapter);
1420 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1421 memcpy(buf + offset,
1423 resp->read_log_length);
1425 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1429 log_offset += buf_size;
1432 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1435 spin_unlock_bh(&adapter->mcc_lock);
1439 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1441 struct be_mcc_wrb *wrb;
1442 struct be_cmd_req_get_fw_version *req;
1445 if (mutex_lock_interruptible(&adapter->mbox_lock))
1448 wrb = wrb_from_mbox(adapter);
1449 req = embedded_payload(wrb);
1451 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1452 OPCODE_COMMON_GET_FW_VERSION);
1454 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1455 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1457 status = be_mbox_notify_wait(adapter);
1459 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1460 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1463 mutex_unlock(&adapter->mbox_lock);
1467 /* set the EQ delay interval of an EQ to specified value
1470 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1472 struct be_mcc_wrb *wrb;
1473 struct be_cmd_req_modify_eq_delay *req;
1476 spin_lock_bh(&adapter->mcc_lock);
1478 wrb = wrb_from_mccq(adapter);
1483 req = embedded_payload(wrb);
1485 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1486 OPCODE_COMMON_MODIFY_EQ_DELAY);
1488 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1491 req->num_eq = cpu_to_le32(1);
1492 req->delay[0].eq_id = cpu_to_le32(eq_id);
1493 req->delay[0].phase = 0;
1494 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1496 be_mcc_notify(adapter);
1499 spin_unlock_bh(&adapter->mcc_lock);
1503 /* Uses sycnhronous mcc */
1504 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1505 u32 num, bool untagged, bool promiscuous)
1507 struct be_mcc_wrb *wrb;
1508 struct be_cmd_req_vlan_config *req;
1511 spin_lock_bh(&adapter->mcc_lock);
1513 wrb = wrb_from_mccq(adapter);
1518 req = embedded_payload(wrb);
1520 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1521 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1523 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1524 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1526 req->interface_id = if_id;
1527 req->promiscuous = promiscuous;
1528 req->untagged = untagged;
1529 req->num_vlan = num;
1531 memcpy(req->normal_vlan, vtag_array,
1532 req->num_vlan * sizeof(vtag_array[0]));
1535 status = be_mcc_notify_wait(adapter);
1538 spin_unlock_bh(&adapter->mcc_lock);
1542 /* Uses MCC for this command as it may be called in BH context
1543 * Uses synchronous mcc
1545 int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
1547 struct be_mcc_wrb *wrb;
1548 struct be_cmd_req_rx_filter *req;
1549 struct be_dma_mem promiscous_cmd;
1553 memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
1554 promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
1555 promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
1556 promiscous_cmd.size, &promiscous_cmd.dma);
1557 if (!promiscous_cmd.va) {
1558 dev_err(&adapter->pdev->dev,
1559 "Memory allocation failure\n");
1563 spin_lock_bh(&adapter->mcc_lock);
1565 wrb = wrb_from_mccq(adapter);
1571 req = promiscous_cmd.va;
1572 sge = nonembedded_sgl(wrb);
1574 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1575 OPCODE_COMMON_NTWK_RX_FILTER);
1576 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1577 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1579 req->if_id = cpu_to_le32(adapter->if_handle);
1580 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1582 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1584 sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
1585 sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
1586 sge->len = cpu_to_le32(promiscous_cmd.size);
1588 status = be_mcc_notify_wait(adapter);
1591 spin_unlock_bh(&adapter->mcc_lock);
1592 pci_free_consistent(adapter->pdev, promiscous_cmd.size,
1593 promiscous_cmd.va, promiscous_cmd.dma);
1598 * Uses MCC for this command as it may be called in BH context
1599 * (mc == NULL) => multicast promiscuous
1601 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1602 struct net_device *netdev, struct be_dma_mem *mem)
1604 struct be_mcc_wrb *wrb;
1605 struct be_cmd_req_mcast_mac_config *req = mem->va;
1609 spin_lock_bh(&adapter->mcc_lock);
1611 wrb = wrb_from_mccq(adapter);
1616 sge = nonembedded_sgl(wrb);
1617 memset(req, 0, sizeof(*req));
1619 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1620 OPCODE_COMMON_NTWK_MULTICAST_SET);
1621 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1622 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1623 sge->len = cpu_to_le32(mem->size);
1625 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1626 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1628 req->interface_id = if_id;
1631 struct netdev_hw_addr *ha;
1633 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1636 netdev_for_each_mc_addr(ha, netdev)
1637 memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1639 req->promiscuous = 1;
1642 status = be_mcc_notify_wait(adapter);
1645 spin_unlock_bh(&adapter->mcc_lock);
1649 /* Uses synchrounous mcc */
1650 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1652 struct be_mcc_wrb *wrb;
1653 struct be_cmd_req_set_flow_control *req;
1656 spin_lock_bh(&adapter->mcc_lock);
1658 wrb = wrb_from_mccq(adapter);
1663 req = embedded_payload(wrb);
1665 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1666 OPCODE_COMMON_SET_FLOW_CONTROL);
1668 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1669 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1671 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1672 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1674 status = be_mcc_notify_wait(adapter);
1677 spin_unlock_bh(&adapter->mcc_lock);
1682 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1684 struct be_mcc_wrb *wrb;
1685 struct be_cmd_req_get_flow_control *req;
1688 spin_lock_bh(&adapter->mcc_lock);
1690 wrb = wrb_from_mccq(adapter);
1695 req = embedded_payload(wrb);
1697 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1698 OPCODE_COMMON_GET_FLOW_CONTROL);
1700 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1701 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1703 status = be_mcc_notify_wait(adapter);
1705 struct be_cmd_resp_get_flow_control *resp =
1706 embedded_payload(wrb);
1707 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1708 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1712 spin_unlock_bh(&adapter->mcc_lock);
1717 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1718 u32 *mode, u32 *caps)
1720 struct be_mcc_wrb *wrb;
1721 struct be_cmd_req_query_fw_cfg *req;
1724 if (mutex_lock_interruptible(&adapter->mbox_lock))
1727 wrb = wrb_from_mbox(adapter);
1728 req = embedded_payload(wrb);
1730 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1731 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1733 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1734 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1736 status = be_mbox_notify_wait(adapter);
1738 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1739 *port_num = le32_to_cpu(resp->phys_port);
1740 *mode = le32_to_cpu(resp->function_mode);
1741 *caps = le32_to_cpu(resp->function_caps);
1744 mutex_unlock(&adapter->mbox_lock);
1749 int be_cmd_reset_function(struct be_adapter *adapter)
1751 struct be_mcc_wrb *wrb;
1752 struct be_cmd_req_hdr *req;
1755 if (mutex_lock_interruptible(&adapter->mbox_lock))
1758 wrb = wrb_from_mbox(adapter);
1759 req = embedded_payload(wrb);
1761 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1762 OPCODE_COMMON_FUNCTION_RESET);
1764 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1765 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1767 status = be_mbox_notify_wait(adapter);
1769 mutex_unlock(&adapter->mbox_lock);
1773 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1775 struct be_mcc_wrb *wrb;
1776 struct be_cmd_req_rss_config *req;
1777 u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1778 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
1781 if (mutex_lock_interruptible(&adapter->mbox_lock))
1784 wrb = wrb_from_mbox(adapter);
1785 req = embedded_payload(wrb);
1787 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1788 OPCODE_ETH_RSS_CONFIG);
1790 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1791 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1793 req->if_id = cpu_to_le32(adapter->if_handle);
1794 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1795 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1796 memcpy(req->cpu_table, rsstable, table_size);
1797 memcpy(req->hash, myhash, sizeof(myhash));
1798 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1800 status = be_mbox_notify_wait(adapter);
1802 mutex_unlock(&adapter->mbox_lock);
1807 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1808 u8 bcn, u8 sts, u8 state)
1810 struct be_mcc_wrb *wrb;
1811 struct be_cmd_req_enable_disable_beacon *req;
1814 spin_lock_bh(&adapter->mcc_lock);
1816 wrb = wrb_from_mccq(adapter);
1821 req = embedded_payload(wrb);
1823 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1824 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1826 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1827 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1829 req->port_num = port_num;
1830 req->beacon_state = state;
1831 req->beacon_duration = bcn;
1832 req->status_duration = sts;
1834 status = be_mcc_notify_wait(adapter);
1837 spin_unlock_bh(&adapter->mcc_lock);
1842 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1844 struct be_mcc_wrb *wrb;
1845 struct be_cmd_req_get_beacon_state *req;
1848 spin_lock_bh(&adapter->mcc_lock);
1850 wrb = wrb_from_mccq(adapter);
1855 req = embedded_payload(wrb);
1857 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1858 OPCODE_COMMON_GET_BEACON_STATE);
1860 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1861 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1863 req->port_num = port_num;
1865 status = be_mcc_notify_wait(adapter);
1867 struct be_cmd_resp_get_beacon_state *resp =
1868 embedded_payload(wrb);
1869 *state = resp->beacon_state;
1873 spin_unlock_bh(&adapter->mcc_lock);
1877 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1878 u32 data_size, u32 data_offset, const char *obj_name,
1879 u32 *data_written, u8 *addn_status)
1881 struct be_mcc_wrb *wrb;
1882 struct lancer_cmd_req_write_object *req;
1883 struct lancer_cmd_resp_write_object *resp;
1887 spin_lock_bh(&adapter->mcc_lock);
1888 adapter->flash_status = 0;
1890 wrb = wrb_from_mccq(adapter);
1896 req = embedded_payload(wrb);
1898 be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
1899 true, 1, OPCODE_COMMON_WRITE_OBJECT);
1900 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1902 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1903 OPCODE_COMMON_WRITE_OBJECT,
1904 sizeof(struct lancer_cmd_req_write_object));
1906 ctxt = &req->context;
1907 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1908 write_length, ctxt, data_size);
1911 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1914 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1917 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1918 req->write_offset = cpu_to_le32(data_offset);
1919 strcpy(req->object_name, obj_name);
1920 req->descriptor_count = cpu_to_le32(1);
1921 req->buf_len = cpu_to_le32(data_size);
1922 req->addr_low = cpu_to_le32((cmd->dma +
1923 sizeof(struct lancer_cmd_req_write_object))
1925 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1926 sizeof(struct lancer_cmd_req_write_object)));
1928 be_mcc_notify(adapter);
1929 spin_unlock_bh(&adapter->mcc_lock);
1931 if (!wait_for_completion_timeout(&adapter->flash_compl,
1932 msecs_to_jiffies(12000)))
1935 status = adapter->flash_status;
1937 resp = embedded_payload(wrb);
1939 *data_written = le32_to_cpu(resp->actual_write_len);
1941 *addn_status = resp->additional_status;
1942 status = resp->status;
1948 spin_unlock_bh(&adapter->mcc_lock);
1952 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1953 u32 flash_type, u32 flash_opcode, u32 buf_size)
1955 struct be_mcc_wrb *wrb;
1956 struct be_cmd_write_flashrom *req;
1960 spin_lock_bh(&adapter->mcc_lock);
1961 adapter->flash_status = 0;
1963 wrb = wrb_from_mccq(adapter);
1969 sge = nonembedded_sgl(wrb);
1971 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1972 OPCODE_COMMON_WRITE_FLASHROM);
1973 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1975 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1976 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1977 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1978 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1979 sge->len = cpu_to_le32(cmd->size);
1981 req->params.op_type = cpu_to_le32(flash_type);
1982 req->params.op_code = cpu_to_le32(flash_opcode);
1983 req->params.data_buf_size = cpu_to_le32(buf_size);
1985 be_mcc_notify(adapter);
1986 spin_unlock_bh(&adapter->mcc_lock);
1988 if (!wait_for_completion_timeout(&adapter->flash_compl,
1989 msecs_to_jiffies(12000)))
1992 status = adapter->flash_status;
1997 spin_unlock_bh(&adapter->mcc_lock);
2001 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2004 struct be_mcc_wrb *wrb;
2005 struct be_cmd_write_flashrom *req;
2008 spin_lock_bh(&adapter->mcc_lock);
2010 wrb = wrb_from_mccq(adapter);
2015 req = embedded_payload(wrb);
2017 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
2018 OPCODE_COMMON_READ_FLASHROM);
2020 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2021 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
2023 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
2024 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2025 req->params.offset = cpu_to_le32(offset);
2026 req->params.data_buf_size = cpu_to_le32(0x4);
2028 status = be_mcc_notify_wait(adapter);
2030 memcpy(flashed_crc, req->params.data_buf, 4);
2033 spin_unlock_bh(&adapter->mcc_lock);
2037 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2038 struct be_dma_mem *nonemb_cmd)
2040 struct be_mcc_wrb *wrb;
2041 struct be_cmd_req_acpi_wol_magic_config *req;
2045 spin_lock_bh(&adapter->mcc_lock);
2047 wrb = wrb_from_mccq(adapter);
2052 req = nonemb_cmd->va;
2053 sge = nonembedded_sgl(wrb);
2055 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2056 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
2058 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2059 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
2060 memcpy(req->magic_mac, mac, ETH_ALEN);
2062 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2063 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2064 sge->len = cpu_to_le32(nonemb_cmd->size);
2066 status = be_mcc_notify_wait(adapter);
2069 spin_unlock_bh(&adapter->mcc_lock);
2073 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2074 u8 loopback_type, u8 enable)
2076 struct be_mcc_wrb *wrb;
2077 struct be_cmd_req_set_lmode *req;
2080 spin_lock_bh(&adapter->mcc_lock);
2082 wrb = wrb_from_mccq(adapter);
2088 req = embedded_payload(wrb);
2090 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2091 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
2093 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2094 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2097 req->src_port = port_num;
2098 req->dest_port = port_num;
2099 req->loopback_type = loopback_type;
2100 req->loopback_state = enable;
2102 status = be_mcc_notify_wait(adapter);
2104 spin_unlock_bh(&adapter->mcc_lock);
2108 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2109 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2111 struct be_mcc_wrb *wrb;
2112 struct be_cmd_req_loopback_test *req;
2115 spin_lock_bh(&adapter->mcc_lock);
2117 wrb = wrb_from_mccq(adapter);
2123 req = embedded_payload(wrb);
2125 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2126 OPCODE_LOWLEVEL_LOOPBACK_TEST);
2128 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2129 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2130 req->hdr.timeout = cpu_to_le32(4);
2132 req->pattern = cpu_to_le64(pattern);
2133 req->src_port = cpu_to_le32(port_num);
2134 req->dest_port = cpu_to_le32(port_num);
2135 req->pkt_size = cpu_to_le32(pkt_size);
2136 req->num_pkts = cpu_to_le32(num_pkts);
2137 req->loopback_type = cpu_to_le32(loopback_type);
2139 status = be_mcc_notify_wait(adapter);
2141 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2142 status = le32_to_cpu(resp->status);
2146 spin_unlock_bh(&adapter->mcc_lock);
2150 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2151 u32 byte_cnt, struct be_dma_mem *cmd)
2153 struct be_mcc_wrb *wrb;
2154 struct be_cmd_req_ddrdma_test *req;
2159 spin_lock_bh(&adapter->mcc_lock);
2161 wrb = wrb_from_mccq(adapter);
2167 sge = nonembedded_sgl(wrb);
2168 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
2169 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2170 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2171 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2173 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2174 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2175 sge->len = cpu_to_le32(cmd->size);
2177 req->pattern = cpu_to_le64(pattern);
2178 req->byte_count = cpu_to_le32(byte_cnt);
2179 for (i = 0; i < byte_cnt; i++) {
2180 req->snd_buff[i] = (u8)(pattern >> (j*8));
2186 status = be_mcc_notify_wait(adapter);
2189 struct be_cmd_resp_ddrdma_test *resp;
2191 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2198 spin_unlock_bh(&adapter->mcc_lock);
2202 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2203 struct be_dma_mem *nonemb_cmd)
2205 struct be_mcc_wrb *wrb;
2206 struct be_cmd_req_seeprom_read *req;
2210 spin_lock_bh(&adapter->mcc_lock);
2212 wrb = wrb_from_mccq(adapter);
2217 req = nonemb_cmd->va;
2218 sge = nonembedded_sgl(wrb);
2220 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2221 OPCODE_COMMON_SEEPROM_READ);
2223 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2224 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2226 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2227 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2228 sge->len = cpu_to_le32(nonemb_cmd->size);
2230 status = be_mcc_notify_wait(adapter);
2233 spin_unlock_bh(&adapter->mcc_lock);
2237 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2239 struct be_mcc_wrb *wrb;
2240 struct be_cmd_req_get_phy_info *req;
2244 spin_lock_bh(&adapter->mcc_lock);
2246 wrb = wrb_from_mccq(adapter);
2253 sge = nonembedded_sgl(wrb);
2255 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2256 OPCODE_COMMON_GET_PHY_DETAILS);
2258 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2259 OPCODE_COMMON_GET_PHY_DETAILS,
2262 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2263 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2264 sge->len = cpu_to_le32(cmd->size);
2266 status = be_mcc_notify_wait(adapter);
2268 spin_unlock_bh(&adapter->mcc_lock);
2272 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2274 struct be_mcc_wrb *wrb;
2275 struct be_cmd_req_set_qos *req;
2278 spin_lock_bh(&adapter->mcc_lock);
2280 wrb = wrb_from_mccq(adapter);
2286 req = embedded_payload(wrb);
2288 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2289 OPCODE_COMMON_SET_QOS);
2291 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2292 OPCODE_COMMON_SET_QOS, sizeof(*req));
2294 req->hdr.domain = domain;
2295 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2296 req->max_bps_nic = cpu_to_le32(bps);
2298 status = be_mcc_notify_wait(adapter);
2301 spin_unlock_bh(&adapter->mcc_lock);
2305 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2307 struct be_mcc_wrb *wrb;
2308 struct be_cmd_req_cntl_attribs *req;
2309 struct be_cmd_resp_cntl_attribs *resp;
2312 int payload_len = max(sizeof(*req), sizeof(*resp));
2313 struct mgmt_controller_attrib *attribs;
2314 struct be_dma_mem attribs_cmd;
2316 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2317 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2318 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2320 if (!attribs_cmd.va) {
2321 dev_err(&adapter->pdev->dev,
2322 "Memory allocation failure\n");
2326 if (mutex_lock_interruptible(&adapter->mbox_lock))
2329 wrb = wrb_from_mbox(adapter);
2334 req = attribs_cmd.va;
2335 sge = nonembedded_sgl(wrb);
2337 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2338 OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2339 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2340 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2341 sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2342 sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2343 sge->len = cpu_to_le32(attribs_cmd.size);
2345 status = be_mbox_notify_wait(adapter);
2347 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2348 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2352 mutex_unlock(&adapter->mbox_lock);
2353 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2359 int be_cmd_check_native_mode(struct be_adapter *adapter)
2361 struct be_mcc_wrb *wrb;
2362 struct be_cmd_req_set_func_cap *req;
2365 if (mutex_lock_interruptible(&adapter->mbox_lock))
2368 wrb = wrb_from_mbox(adapter);
2374 req = embedded_payload(wrb);
2376 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2377 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2379 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2380 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2382 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2383 CAPABILITY_BE3_NATIVE_ERX_API);
2384 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2386 status = be_mbox_notify_wait(adapter);
2388 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2389 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2390 CAPABILITY_BE3_NATIVE_ERX_API;
2393 mutex_unlock(&adapter->mbox_lock);