drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 32;
  23
  24 static void be_mcc_notify(struct be_adapter *adapter)
  25 {
  26         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  27         u32 val = 0;
  28
  29         if (adapter->eeh_err) {
  30                 dev_info(&adapter->pdev->dev,
  31                         "Error in Card Detected! Cannot issue commands\n");
  32                 return;
  33         }
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static int be_mcc_compl_process(struct be_adapter *adapter,
  63         struct be_mcc_compl *compl)
  64 {
  65         u16 compl_status, extd_status;
  66
  67         /* Just swap the status to host endian; mcc tag is opaquely copied
  68          * from mcc_wrb */
  69         be_dws_le_to_cpu(compl, 4);
  70
  71         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  72                                 CQE_STATUS_COMPL_MASK;
  73
  74         if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  75                 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  76                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  77                 adapter->flash_status = compl_status;
  78                 complete(&adapter->flash_compl);
  79         }
  80
  81         if (compl_status == MCC_STATUS_SUCCESS) {
  82                 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  83                          (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  84                         (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  85                         if (adapter->generation == BE_GEN3) {
  86                                 if (lancer_chip(adapter)) {
  87                                         struct lancer_cmd_resp_pport_stats
  88                                                 *resp = adapter->stats_cmd.va;
  89                                         be_dws_le_to_cpu(&resp->pport_stats,
  90                                                 sizeof(resp->pport_stats));
  91                                 } else {
  92                                         struct be_cmd_resp_get_stats_v1 *resp =
  93                                                         adapter->stats_cmd.va;
  94
  95                                 be_dws_le_to_cpu(&resp->hw_stats,
  96                                                         sizeof(resp->hw_stats));
  97                                 }
  98                         } else {
  99                                 struct be_cmd_resp_get_stats_v0 *resp =
 100                                                         adapter->stats_cmd.va;
 101
 102                                 be_dws_le_to_cpu(&resp->hw_stats,
 103                                                         sizeof(resp->hw_stats));
 104                         }
 105                         be_parse_stats(adapter);
 106                         netdev_stats_update(adapter);
 107                         adapter->stats_cmd_sent = false;
 108                 }
 109         } else {
 110                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 111                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 112                         goto done;
 113
 114                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 115                         dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
 116                                 "permitted to execute this cmd (opcode %d)\n",
 117                                 compl->tag0);
 118                 } else {
 119                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 120                                         CQE_STATUS_EXTD_MASK;
 121                         dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
 122                                 "status %d, extd-status %d\n",
 123                                 compl->tag0, compl_status, extd_status);
 124                 }
 125         }
 126 done:
 127         return compl_status;
 128 }
 129
 130 /* Link state evt is a string of bytes; no need for endian swapping */
 131 static void be_async_link_state_process(struct be_adapter *adapter,
 132                 struct be_async_event_link_state *evt)
 133 {
 134         be_link_status_update(adapter,
 135                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
 136 }
 137
 138 /* Grp5 CoS Priority evt */
 139 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 140                 struct be_async_event_grp5_cos_priority *evt)
 141 {
 142         if (evt->valid) {
 143                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 144                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 145                 adapter->recommended_prio =
 146                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 147         }
 148 }
 149
 150 /* Grp5 QOS Speed evt */
 151 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 152                 struct be_async_event_grp5_qos_link_speed *evt)
 153 {
 154         if (evt->physical_port == adapter->port_num) {
 155                 /* qos_link_speed is in units of 10 Mbps */
 156                 adapter->link_speed = evt->qos_link_speed * 10;
 157         }
 158 }
 159
 160 /*Grp5 PVID evt*/
 161 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 162                 struct be_async_event_grp5_pvid_state *evt)
 163 {
 164         if (evt->enabled)
 165                 adapter->pvid = le16_to_cpu(evt->tag);
 166         else
 167                 adapter->pvid = 0;
 168 }
 169
 170 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 171                 u32 trailer, struct be_mcc_compl *evt)
 172 {
 173         u8 event_type = 0;
 174
 175         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 176                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 177
 178         switch (event_type) {
 179         case ASYNC_EVENT_COS_PRIORITY:
 180                 be_async_grp5_cos_priority_process(adapter,
 181                 (struct be_async_event_grp5_cos_priority *)evt);
 182         break;
 183         case ASYNC_EVENT_QOS_SPEED:
 184                 be_async_grp5_qos_speed_process(adapter,
 185                 (struct be_async_event_grp5_qos_link_speed *)evt);
 186         break;
 187         case ASYNC_EVENT_PVID_STATE:
 188                 be_async_grp5_pvid_state_process(adapter,
 189                 (struct be_async_event_grp5_pvid_state *)evt);
 190         break;
 191         default:
 192                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 193                 break;
 194         }
 195 }
 196
 197 static inline bool is_link_state_evt(u32 trailer)
 198 {
 199         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 200                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 201                                 ASYNC_EVENT_CODE_LINK_STATE;
 202 }
 203
 204 static inline bool is_grp5_evt(u32 trailer)
 205 {
 206         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 207                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 208                                 ASYNC_EVENT_CODE_GRP_5);
 209 }
 210
 211 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 212 {
 213         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 214         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 215
 216         if (be_mcc_compl_is_new(compl)) {
 217                 queue_tail_inc(mcc_cq);
 218                 return compl;
 219         }
 220         return NULL;
 221 }
 222
 223 void be_async_mcc_enable(struct be_adapter *adapter)
 224 {
 225         spin_lock_bh(&adapter->mcc_cq_lock);
 226
 227         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 228         adapter->mcc_obj.rearm_cq = true;
 229
 230         spin_unlock_bh(&adapter->mcc_cq_lock);
 231 }
 232
 233 void be_async_mcc_disable(struct be_adapter *adapter)
 234 {
 235         adapter->mcc_obj.rearm_cq = false;
 236 }
 237
 238 int be_process_mcc(struct be_adapter *adapter, int *status)
 239 {
 240         struct be_mcc_compl *compl;
 241         int num = 0;
 242         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 243
 244         spin_lock_bh(&adapter->mcc_cq_lock);
 245         while ((compl = be_mcc_compl_get(adapter))) {
 246                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 247                         /* Interpret flags as an async trailer */
 248                         if (is_link_state_evt(compl->flags))
 249                                 be_async_link_state_process(adapter,
 250                                 (struct be_async_event_link_state *) compl);
 251                         else if (is_grp5_evt(compl->flags))
 252                                 be_async_grp5_evt_process(adapter,
 253                                 compl->flags, compl);
 254                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 255                                 *status = be_mcc_compl_process(adapter, compl);
 256                                 atomic_dec(&mcc_obj->q.used);
 257                 }
 258                 be_mcc_compl_use(compl);
 259                 num++;
 260         }
 261
 262         spin_unlock_bh(&adapter->mcc_cq_lock);
 263         return num;
 264 }
 265
 266 /* Wait till no more pending mcc requests are present */
 267 static int be_mcc_wait_compl(struct be_adapter *adapter)
 268 {
 269 #define mcc_timeout             120000 /* 12s timeout */
 270         int i, num, status = 0;
 271         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 272
 273         if (adapter->eeh_err)
 274                 return -EIO;
 275
 276         for (i = 0; i < mcc_timeout; i++) {
 277                 num = be_process_mcc(adapter, &status);
 278                 if (num)
 279                         be_cq_notify(adapter, mcc_obj->cq.id,
 280                                 mcc_obj->rearm_cq, num);
 281
 282                 if (atomic_read(&mcc_obj->q.used) == 0)
 283                         break;
 284                 udelay(100);
 285         }
 286         if (i == mcc_timeout) {
 287                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 288                 return -1;
 289         }
 290         return status;
 291 }
 292
 293 /* Notify MCC requests and wait for completion */
 294 static int be_mcc_notify_wait(struct be_adapter *adapter)
 295 {
 296         be_mcc_notify(adapter);
 297         return be_mcc_wait_compl(adapter);
 298 }
 299
 300 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 301 {
 302         int msecs = 0;
 303         u32 ready;
 304
 305         if (adapter->eeh_err) {
 306                 dev_err(&adapter->pdev->dev,
 307                         "Error detected in card.Cannot issue commands\n");
 308                 return -EIO;
 309         }
 310
 311         do {
 312                 ready = ioread32(db);
 313                 if (ready == 0xffffffff) {
 314                         dev_err(&adapter->pdev->dev,
 315                                 "pci slot disconnected\n");
 316                         return -1;
 317                 }
 318
 319                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 320                 if (ready)
 321                         break;
 322
 323                 if (msecs > 4000) {
 324                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 325                         if (!lancer_chip(adapter))
 326                                 be_detect_dump_ue(adapter);
 327                         return -1;
 328                 }
 329
 330                 msleep(1);
 331                 msecs++;
 332         } while (true);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Insert the mailbox address into the doorbell in two steps
 339  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 340  */
 341 static int be_mbox_notify_wait(struct be_adapter *adapter)
 342 {
 343         int status;
 344         u32 val = 0;
 345         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 346         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 347         struct be_mcc_mailbox *mbox = mbox_mem->va;
 348         struct be_mcc_compl *compl = &mbox->compl;
 349
 350         /* wait for ready to be set */
 351         status = be_mbox_db_ready_wait(adapter, db);
 352         if (status != 0)
 353                 return status;
 354
 355         val |= MPU_MAILBOX_DB_HI_MASK;
 356         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 357         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 358         iowrite32(val, db);
 359
 360         /* wait for ready to be set */
 361         status = be_mbox_db_ready_wait(adapter, db);
 362         if (status != 0)
 363                 return status;
 364
 365         val = 0;
 366         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 367         val |= (u32)(mbox_mem->dma >> 4) << 2;
 368         iowrite32(val, db);
 369
 370         status = be_mbox_db_ready_wait(adapter, db);
 371         if (status != 0)
 372                 return status;
 373
 374         /* A cq entry has been made now */
 375         if (be_mcc_compl_is_new(compl)) {
 376                 status = be_mcc_compl_process(adapter, &mbox->compl);
 377                 be_mcc_compl_use(compl);
 378                 if (status)
 379                         return status;
 380         } else {
 381                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 382                 return -1;
 383         }
 384         return 0;
 385 }
 386
 387 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 388 {
 389         u32 sem;
 390
 391         if (lancer_chip(adapter))
 392                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 393         else
 394                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 395
 396         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 397         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 398                 return -1;
 399         else
 400                 return 0;
 401 }
 402
 403 int be_cmd_POST(struct be_adapter *adapter)
 404 {
 405         u16 stage;
 406         int status, timeout = 0;
 407         struct device *dev = &adapter->pdev->dev;
 408
 409         do {
 410                 status = be_POST_stage_get(adapter, &stage);
 411                 if (status) {
 412                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 413                         return -1;
 414                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 415                         if (msleep_interruptible(2000)) {
 416                                 dev_err(dev, "Waiting for POST aborted\n");
 417                                 return -EINTR;
 418                         }
 419                         timeout += 2;
 420                 } else {
 421                         return 0;
 422                 }
 423         } while (timeout < 40);
 424
 425         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 426         return -1;
 427 }
 428
 429 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 430 {
 431         return wrb->payload.embedded_payload;
 432 }
 433
 434 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 435 {
 436         return &wrb->payload.sgl[0];
 437 }
 438
 439 /* Don't touch the hdr after it's prepared */
 440 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 441                                 bool embedded, u8 sge_cnt, u32 opcode)
 442 {
 443         if (embedded)
 444                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 445         else
 446                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 447                                 MCC_WRB_SGE_CNT_SHIFT;
 448         wrb->payload_length = payload_len;
 449         wrb->tag0 = opcode;
 450         be_dws_cpu_to_le(wrb, 8);
 451 }
 452
 453 /* Don't touch the hdr after it's prepared */
 454 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 455                                 u8 subsystem, u8 opcode, int cmd_len)
 456 {
 457         req_hdr->opcode = opcode;
 458         req_hdr->subsystem = subsystem;
 459         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 460         req_hdr->version = 0;
 461 }
 462
 463 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 464                         struct be_dma_mem *mem)
 465 {
 466         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 467         u64 dma = (u64)mem->dma;
 468
 469         for (i = 0; i < buf_pages; i++) {
 470                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 471                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 472                 dma += PAGE_SIZE_4K;
 473         }
 474 }
 475
 476 /* Converts interrupt delay in microseconds to multiplier value */
 477 static u32 eq_delay_to_mult(u32 usec_delay)
 478 {
 479 #define MAX_INTR_RATE                   651042
 480         const u32 round = 10;
 481         u32 multiplier;
 482
 483         if (usec_delay == 0)
 484                 multiplier = 0;
 485         else {
 486                 u32 interrupt_rate = 1000000 / usec_delay;
 487                 /* Max delay, corresponding to the lowest interrupt rate */
 488                 if (interrupt_rate == 0)
 489                         multiplier = 1023;
 490                 else {
 491                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 492                         multiplier /= interrupt_rate;
 493                         /* Round the multiplier to the closest value.*/
 494                         multiplier = (multiplier + round/2) / round;
 495                         multiplier = min(multiplier, (u32)1023);
 496                 }
 497         }
 498         return multiplier;
 499 }
 500
 501 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 502 {
 503         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 504         struct be_mcc_wrb *wrb
 505                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 506         memset(wrb, 0, sizeof(*wrb));
 507         return wrb;
 508 }
 509
 510 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 511 {
 512         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 513         struct be_mcc_wrb *wrb;
 514
 515         if (atomic_read(&mccq->used) >= mccq->len) {
 516                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 517                 return NULL;
 518         }
 519
 520         wrb = queue_head_node(mccq);
 521         queue_head_inc(mccq);
 522         atomic_inc(&mccq->used);
 523         memset(wrb, 0, sizeof(*wrb));
 524         return wrb;
 525 }
 526
 527 /* Tell fw we're about to start firing cmds by writing a
 528  * special pattern across the wrb hdr; uses mbox
 529  */
 530 int be_cmd_fw_init(struct be_adapter *adapter)
 531 {
 532         u8 *wrb;
 533         int status;
 534
 535         if (mutex_lock_interruptible(&adapter->mbox_lock))
 536                 return -1;
 537
 538         wrb = (u8 *)wrb_from_mbox(adapter);
 539         *wrb++ = 0xFF;
 540         *wrb++ = 0x12;
 541         *wrb++ = 0x34;
 542         *wrb++ = 0xFF;
 543         *wrb++ = 0xFF;
 544         *wrb++ = 0x56;
 545         *wrb++ = 0x78;
 546         *wrb = 0xFF;
 547
 548         status = be_mbox_notify_wait(adapter);
 549
 550         mutex_unlock(&adapter->mbox_lock);
 551         return status;
 552 }
 553
 554 /* Tell fw we're done with firing cmds by writing a
 555  * special pattern across the wrb hdr; uses mbox
 556  */
 557 int be_cmd_fw_clean(struct be_adapter *adapter)
 558 {
 559         u8 *wrb;
 560         int status;
 561
 562         if (adapter->eeh_err)
 563                 return -EIO;
 564
 565         if (mutex_lock_interruptible(&adapter->mbox_lock))
 566                 return -1;
 567
 568         wrb = (u8 *)wrb_from_mbox(adapter);
 569         *wrb++ = 0xFF;
 570         *wrb++ = 0xAA;
 571         *wrb++ = 0xBB;
 572         *wrb++ = 0xFF;
 573         *wrb++ = 0xFF;
 574         *wrb++ = 0xCC;
 575         *wrb++ = 0xDD;
 576         *wrb = 0xFF;
 577
 578         status = be_mbox_notify_wait(adapter);
 579
 580         mutex_unlock(&adapter->mbox_lock);
 581         return status;
 582 }
 583 int be_cmd_eq_create(struct be_adapter *adapter,
 584                 struct be_queue_info *eq, int eq_delay)
 585 {
 586         struct be_mcc_wrb *wrb;
 587         struct be_cmd_req_eq_create *req;
 588         struct be_dma_mem *q_mem = &eq->dma_mem;
 589         int status;
 590
 591         if (mutex_lock_interruptible(&adapter->mbox_lock))
 592                 return -1;
 593
 594         wrb = wrb_from_mbox(adapter);
 595         req = embedded_payload(wrb);
 596
 597         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 598
 599         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 600                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 601
 602         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 603
 604         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 605         /* 4byte eqe*/
 606         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 607         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 608                         __ilog2_u32(eq->len/256));
 609         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 610                         eq_delay_to_mult(eq_delay));
 611         be_dws_cpu_to_le(req->context, sizeof(req->context));
 612
 613         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 614
 615         status = be_mbox_notify_wait(adapter);
 616         if (!status) {
 617                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 618                 eq->id = le16_to_cpu(resp->eq_id);
 619                 eq->created = true;
 620         }
 621
 622         mutex_unlock(&adapter->mbox_lock);
 623         return status;
 624 }
 625
 626 /* Uses mbox */
 627 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 628                         u8 type, bool permanent, u32 if_handle)
 629 {
 630         struct be_mcc_wrb *wrb;
 631         struct be_cmd_req_mac_query *req;
 632         int status;
 633
 634         if (mutex_lock_interruptible(&adapter->mbox_lock))
 635                 return -1;
 636
 637         wrb = wrb_from_mbox(adapter);
 638         req = embedded_payload(wrb);
 639
 640         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 641                         OPCODE_COMMON_NTWK_MAC_QUERY);
 642
 643         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 644                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 645
 646         req->type = type;
 647         if (permanent) {
 648                 req->permanent = 1;
 649         } else {
 650                 req->if_id = cpu_to_le16((u16) if_handle);
 651                 req->permanent = 0;
 652         }
 653
 654         status = be_mbox_notify_wait(adapter);
 655         if (!status) {
 656                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 657                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 658         }
 659
 660         mutex_unlock(&adapter->mbox_lock);
 661         return status;
 662 }
 663
 664 /* Uses synchronous MCCQ */
 665 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 666                 u32 if_id, u32 *pmac_id, u32 domain)
 667 {
 668         struct be_mcc_wrb *wrb;
 669         struct be_cmd_req_pmac_add *req;
 670         int status;
 671
 672         spin_lock_bh(&adapter->mcc_lock);
 673
 674         wrb = wrb_from_mccq(adapter);
 675         if (!wrb) {
 676                 status = -EBUSY;
 677                 goto err;
 678         }
 679         req = embedded_payload(wrb);
 680
 681         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 682                         OPCODE_COMMON_NTWK_PMAC_ADD);
 683
 684         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 685                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 686
 687         req->hdr.domain = domain;
 688         req->if_id = cpu_to_le32(if_id);
 689         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 690
 691         status = be_mcc_notify_wait(adapter);
 692         if (!status) {
 693                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 694                 *pmac_id = le32_to_cpu(resp->pmac_id);
 695         }
 696
 697 err:
 698         spin_unlock_bh(&adapter->mcc_lock);
 699         return status;
 700 }
 701
 702 /* Uses synchronous MCCQ */
 703 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
 704 {
 705         struct be_mcc_wrb *wrb;
 706         struct be_cmd_req_pmac_del *req;
 707         int status;
 708
 709         spin_lock_bh(&adapter->mcc_lock);
 710
 711         wrb = wrb_from_mccq(adapter);
 712         if (!wrb) {
 713                 status = -EBUSY;
 714                 goto err;
 715         }
 716         req = embedded_payload(wrb);
 717
 718         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 719                         OPCODE_COMMON_NTWK_PMAC_DEL);
 720
 721         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 722                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 723
 724         req->hdr.domain = dom;
 725         req->if_id = cpu_to_le32(if_id);
 726         req->pmac_id = cpu_to_le32(pmac_id);
 727
 728         status = be_mcc_notify_wait(adapter);
 729
 730 err:
 731         spin_unlock_bh(&adapter->mcc_lock);
 732         return status;
 733 }
 734
 735 /* Uses Mbox */
 736 int be_cmd_cq_create(struct be_adapter *adapter,
 737                 struct be_queue_info *cq, struct be_queue_info *eq,
 738                 bool sol_evts, bool no_delay, int coalesce_wm)
 739 {
 740         struct be_mcc_wrb *wrb;
 741         struct be_cmd_req_cq_create *req;
 742         struct be_dma_mem *q_mem = &cq->dma_mem;
 743         void *ctxt;
 744         int status;
 745
 746         if (mutex_lock_interruptible(&adapter->mbox_lock))
 747                 return -1;
 748
 749         wrb = wrb_from_mbox(adapter);
 750         req = embedded_payload(wrb);
 751         ctxt = &req->context;
 752
 753         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 754                         OPCODE_COMMON_CQ_CREATE);
 755
 756         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 757                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 758
 759         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 760         if (lancer_chip(adapter)) {
 761                 req->hdr.version = 2;
 762                 req->page_size = 1; /* 1 for 4K */
 763                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 764                                                                 no_delay);
 765                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 766                                                 __ilog2_u32(cq->len/256));
 767                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 768                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 769                                                                 ctxt, 1);
 770                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 771                                                                 ctxt, eq->id);
 772                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 773         } else {
 774                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 775                                                                 coalesce_wm);
 776                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 777                                                                 ctxt, no_delay);
 778                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 779                                                 __ilog2_u32(cq->len/256));
 780                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 781                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 782                                                                 ctxt, sol_evts);
 783                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 784                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 785                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 786         }
 787
 788         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 789
 790         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 791
 792         status = be_mbox_notify_wait(adapter);
 793         if (!status) {
 794                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 795                 cq->id = le16_to_cpu(resp->cq_id);
 796                 cq->created = true;
 797         }
 798
 799         mutex_unlock(&adapter->mbox_lock);
 800
 801         return status;
 802 }
 803
 804 static u32 be_encoded_q_len(int q_len)
 805 {
 806         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 807         if (len_encoded == 16)
 808                 len_encoded = 0;
 809         return len_encoded;
 810 }
 811
 812 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 813                         struct be_queue_info *mccq,
 814                         struct be_queue_info *cq)
 815 {
 816         struct be_mcc_wrb *wrb;
 817         struct be_cmd_req_mcc_ext_create *req;
 818         struct be_dma_mem *q_mem = &mccq->dma_mem;
 819         void *ctxt;
 820         int status;
 821
 822         if (mutex_lock_interruptible(&adapter->mbox_lock))
 823                 return -1;
 824
 825         wrb = wrb_from_mbox(adapter);
 826         req = embedded_payload(wrb);
 827         ctxt = &req->context;
 828
 829         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 830                         OPCODE_COMMON_MCC_CREATE_EXT);
 831
 832         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 833                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 834
 835         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 836         if (lancer_chip(adapter)) {
 837                 req->hdr.version = 1;
 838                 req->cq_id = cpu_to_le16(cq->id);
 839
 840                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 841                                                 be_encoded_q_len(mccq->len));
 842                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 843                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 844                                                                 ctxt, cq->id);
 845                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 846                                                                  ctxt, 1);
 847
 848         } else {
 849                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 850                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 851                                                 be_encoded_q_len(mccq->len));
 852                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 853         }
 854
 855         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 856         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 857         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 858
 859         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 860
 861         status = be_mbox_notify_wait(adapter);
 862         if (!status) {
 863                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 864                 mccq->id = le16_to_cpu(resp->id);
 865                 mccq->created = true;
 866         }
 867         mutex_unlock(&adapter->mbox_lock);
 868
 869         return status;
 870 }
 871
 872 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 873                         struct be_queue_info *mccq,
 874                         struct be_queue_info *cq)
 875 {
 876         struct be_mcc_wrb *wrb;
 877         struct be_cmd_req_mcc_create *req;
 878         struct be_dma_mem *q_mem = &mccq->dma_mem;
 879         void *ctxt;
 880         int status;
 881
 882         if (mutex_lock_interruptible(&adapter->mbox_lock))
 883                 return -1;
 884
 885         wrb = wrb_from_mbox(adapter);
 886         req = embedded_payload(wrb);
 887         ctxt = &req->context;
 888
 889         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 890                         OPCODE_COMMON_MCC_CREATE);
 891
 892         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 893                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 894
 895         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 896
 897         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 898         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 899                         be_encoded_q_len(mccq->len));
 900         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 901
 902         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 903
 904         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 905
 906         status = be_mbox_notify_wait(adapter);
 907         if (!status) {
 908                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 909                 mccq->id = le16_to_cpu(resp->id);
 910                 mccq->created = true;
 911         }
 912
 913         mutex_unlock(&adapter->mbox_lock);
 914         return status;
 915 }
 916
 917 int be_cmd_mccq_create(struct be_adapter *adapter,
 918                         struct be_queue_info *mccq,
 919                         struct be_queue_info *cq)
 920 {
 921         int status;
 922
 923         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
 924         if (status && !lancer_chip(adapter)) {
 925                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
 926                         "or newer to avoid conflicting priorities between NIC "
 927                         "and FCoE traffic");
 928                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
 929         }
 930         return status;
 931 }
 932
 933 int be_cmd_txq_create(struct be_adapter *adapter,
 934                         struct be_queue_info *txq,
 935                         struct be_queue_info *cq)
 936 {
 937         struct be_mcc_wrb *wrb;
 938         struct be_cmd_req_eth_tx_create *req;
 939         struct be_dma_mem *q_mem = &txq->dma_mem;
 940         void *ctxt;
 941         int status;
 942
 943         if (mutex_lock_interruptible(&adapter->mbox_lock))
 944                 return -1;
 945
 946         wrb = wrb_from_mbox(adapter);
 947         req = embedded_payload(wrb);
 948         ctxt = &req->context;
 949
 950         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 951                         OPCODE_ETH_TX_CREATE);
 952
 953         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 954                 sizeof(*req));
 955
 956         if (lancer_chip(adapter)) {
 957                 req->hdr.version = 1;
 958                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 959                                         adapter->if_handle);
 960         }
 961
 962         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 963         req->ulp_num = BE_ULP1_NUM;
 964         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 965
 966         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 967                 be_encoded_q_len(txq->len));
 968         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 969         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 970
 971         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 972
 973         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 974
 975         status = be_mbox_notify_wait(adapter);
 976         if (!status) {
 977                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 978                 txq->id = le16_to_cpu(resp->cid);
 979                 txq->created = true;
 980         }
 981
 982         mutex_unlock(&adapter->mbox_lock);
 983
 984         return status;
 985 }
 986
 987 /* Uses mbox */
 988 int be_cmd_rxq_create(struct be_adapter *adapter,
 989                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 990                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 991 {
 992         struct be_mcc_wrb *wrb;
 993         struct be_cmd_req_eth_rx_create *req;
 994         struct be_dma_mem *q_mem = &rxq->dma_mem;
 995         int status;
 996
 997         if (mutex_lock_interruptible(&adapter->mbox_lock))
 998                 return -1;
 999
1000         wrb = wrb_from_mbox(adapter);
1001         req = embedded_payload(wrb);
1002
1003         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1004                         OPCODE_ETH_RX_CREATE);
1005
1006         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
1007                 sizeof(*req));
1008
1009         req->cq_id = cpu_to_le16(cq_id);
1010         req->frag_size = fls(frag_size) - 1;
1011         req->num_pages = 2;
1012         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1013         req->interface_id = cpu_to_le32(if_id);
1014         req->max_frame_size = cpu_to_le16(max_frame_size);
1015         req->rss_queue = cpu_to_le32(rss);
1016
1017         status = be_mbox_notify_wait(adapter);
1018         if (!status) {
1019                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1020                 rxq->id = le16_to_cpu(resp->id);
1021                 rxq->created = true;
1022                 *rss_id = resp->rss_id;
1023         }
1024
1025         mutex_unlock(&adapter->mbox_lock);
1026
1027         return status;
1028 }
1029
1030 /* Generic destroyer function for all types of queues
1031  * Uses Mbox
1032  */
1033 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1034                 int queue_type)
1035 {
1036         struct be_mcc_wrb *wrb;
1037         struct be_cmd_req_q_destroy *req;
1038         u8 subsys = 0, opcode = 0;
1039         int status;
1040
1041         if (adapter->eeh_err)
1042                 return -EIO;
1043
1044         if (mutex_lock_interruptible(&adapter->mbox_lock))
1045                 return -1;
1046
1047         wrb = wrb_from_mbox(adapter);
1048         req = embedded_payload(wrb);
1049
1050         switch (queue_type) {
1051         case QTYPE_EQ:
1052                 subsys = CMD_SUBSYSTEM_COMMON;
1053                 opcode = OPCODE_COMMON_EQ_DESTROY;
1054                 break;
1055         case QTYPE_CQ:
1056                 subsys = CMD_SUBSYSTEM_COMMON;
1057                 opcode = OPCODE_COMMON_CQ_DESTROY;
1058                 break;
1059         case QTYPE_TXQ:
1060                 subsys = CMD_SUBSYSTEM_ETH;
1061                 opcode = OPCODE_ETH_TX_DESTROY;
1062                 break;
1063         case QTYPE_RXQ:
1064                 subsys = CMD_SUBSYSTEM_ETH;
1065                 opcode = OPCODE_ETH_RX_DESTROY;
1066                 break;
1067         case QTYPE_MCCQ:
1068                 subsys = CMD_SUBSYSTEM_COMMON;
1069                 opcode = OPCODE_COMMON_MCC_DESTROY;
1070                 break;
1071         default:
1072                 BUG();
1073         }
1074
1075         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
1076
1077         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1078         req->id = cpu_to_le16(q->id);
1079
1080         status = be_mbox_notify_wait(adapter);
1081
1082         mutex_unlock(&adapter->mbox_lock);
1083
1084         return status;
1085 }
1086
1087 /* Create an rx filtering policy configuration on an i/f
1088  * Uses mbox
1089  */
1090 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1091                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1092                 u32 domain)
1093 {
1094         struct be_mcc_wrb *wrb;
1095         struct be_cmd_req_if_create *req;
1096         int status;
1097
1098         if (mutex_lock_interruptible(&adapter->mbox_lock))
1099                 return -1;
1100
1101         wrb = wrb_from_mbox(adapter);
1102         req = embedded_payload(wrb);
1103
1104         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1105                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1106
1107         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1108                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1109
1110         req->hdr.domain = domain;
1111         req->capability_flags = cpu_to_le32(cap_flags);
1112         req->enable_flags = cpu_to_le32(en_flags);
1113         req->pmac_invalid = pmac_invalid;
1114         if (!pmac_invalid)
1115                 memcpy(req->mac_addr, mac, ETH_ALEN);
1116
1117         status = be_mbox_notify_wait(adapter);
1118         if (!status) {
1119                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1120                 *if_handle = le32_to_cpu(resp->interface_id);
1121                 if (!pmac_invalid)
1122                         *pmac_id = le32_to_cpu(resp->pmac_id);
1123         }
1124
1125         mutex_unlock(&adapter->mbox_lock);
1126         return status;
1127 }
1128
1129 /* Uses mbox */
1130 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1131 {
1132         struct be_mcc_wrb *wrb;
1133         struct be_cmd_req_if_destroy *req;
1134         int status;
1135
1136         if (adapter->eeh_err)
1137                 return -EIO;
1138
1139         if (mutex_lock_interruptible(&adapter->mbox_lock))
1140                 return -1;
1141
1142         wrb = wrb_from_mbox(adapter);
1143         req = embedded_payload(wrb);
1144
1145         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1146                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1147
1148         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1149                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1150
1151         req->hdr.domain = domain;
1152         req->interface_id = cpu_to_le32(interface_id);
1153
1154         status = be_mbox_notify_wait(adapter);
1155
1156         mutex_unlock(&adapter->mbox_lock);
1157
1158         return status;
1159 }
1160
1161 /* Get stats is a non embedded command: the request is not embedded inside
1162  * WRB but is a separate dma memory block
1163  * Uses asynchronous MCC
1164  */
1165 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1166 {
1167         struct be_mcc_wrb *wrb;
1168         struct be_cmd_req_hdr *hdr;
1169         struct be_sge *sge;
1170         int status = 0;
1171
1172         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1173                 be_cmd_get_die_temperature(adapter);
1174
1175         spin_lock_bh(&adapter->mcc_lock);
1176
1177         wrb = wrb_from_mccq(adapter);
1178         if (!wrb) {
1179                 status = -EBUSY;
1180                 goto err;
1181         }
1182         hdr = nonemb_cmd->va;
1183         sge = nonembedded_sgl(wrb);
1184
1185         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1186                         OPCODE_ETH_GET_STATISTICS);
1187
1188         be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1189                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1190
1191         if (adapter->generation == BE_GEN3)
1192                 hdr->version = 1;
1193
1194         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1195         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1196         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1197         sge->len = cpu_to_le32(nonemb_cmd->size);
1198
1199         be_mcc_notify(adapter);
1200         adapter->stats_cmd_sent = true;
1201
1202 err:
1203         spin_unlock_bh(&adapter->mcc_lock);
1204         return status;
1205 }
1206
1207 /* Lancer Stats */
1208 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1209                                 struct be_dma_mem *nonemb_cmd)
1210 {
1211
1212         struct be_mcc_wrb *wrb;
1213         struct lancer_cmd_req_pport_stats *req;
1214         struct be_sge *sge;
1215         int status = 0;
1216
1217         spin_lock_bh(&adapter->mcc_lock);
1218
1219         wrb = wrb_from_mccq(adapter);
1220         if (!wrb) {
1221                 status = -EBUSY;
1222                 goto err;
1223         }
1224         req = nonemb_cmd->va;
1225         sge = nonembedded_sgl(wrb);
1226
1227         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1228                         OPCODE_ETH_GET_PPORT_STATS);
1229
1230         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1231                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1232
1233
1234         req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1235         req->cmd_params.params.reset_stats = 0;
1236
1237         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1238         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1239         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1240         sge->len = cpu_to_le32(nonemb_cmd->size);
1241
1242         be_mcc_notify(adapter);
1243         adapter->stats_cmd_sent = true;
1244
1245 err:
1246         spin_unlock_bh(&adapter->mcc_lock);
1247         return status;
1248 }
1249
1250 /* Uses synchronous mcc */
1251 int be_cmd_link_status_query(struct be_adapter *adapter,
1252                         bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
1253 {
1254         struct be_mcc_wrb *wrb;
1255         struct be_cmd_req_link_status *req;
1256         int status;
1257
1258         spin_lock_bh(&adapter->mcc_lock);
1259
1260         wrb = wrb_from_mccq(adapter);
1261         if (!wrb) {
1262                 status = -EBUSY;
1263                 goto err;
1264         }
1265         req = embedded_payload(wrb);
1266
1267         *link_up = false;
1268
1269         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1270                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1271
1272         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1273                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1274
1275         status = be_mcc_notify_wait(adapter);
1276         if (!status) {
1277                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1278                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1279                         *link_up = true;
1280                         *link_speed = le16_to_cpu(resp->link_speed);
1281                         *mac_speed = resp->mac_speed;
1282                 }
1283         }
1284
1285 err:
1286         spin_unlock_bh(&adapter->mcc_lock);
1287         return status;
1288 }
1289
1290 /* Uses synchronous mcc */
1291 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1292 {
1293         struct be_mcc_wrb *wrb;
1294         struct be_cmd_req_get_cntl_addnl_attribs *req;
1295         int status;
1296
1297         spin_lock_bh(&adapter->mcc_lock);
1298
1299         wrb = wrb_from_mccq(adapter);
1300         if (!wrb) {
1301                 status = -EBUSY;
1302                 goto err;
1303         }
1304         req = embedded_payload(wrb);
1305
1306         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1307                         OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1308
1309         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1310                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1311
1312         status = be_mcc_notify_wait(adapter);
1313         if (!status) {
1314                 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1315                                                 embedded_payload(wrb);
1316                 adapter->drv_stats.be_on_die_temperature =
1317                                                 resp->on_die_temperature;
1318         }
1319         /* If IOCTL fails once, do not bother issuing it again */
1320         else
1321                 be_get_temp_freq = 0;
1322
1323 err:
1324         spin_unlock_bh(&adapter->mcc_lock);
1325         return status;
1326 }
1327
1328 /* Uses synchronous mcc */
1329 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1330 {
1331         struct be_mcc_wrb *wrb;
1332         struct be_cmd_req_get_fat *req;
1333         int status;
1334
1335         spin_lock_bh(&adapter->mcc_lock);
1336
1337         wrb = wrb_from_mccq(adapter);
1338         if (!wrb) {
1339                 status = -EBUSY;
1340                 goto err;
1341         }
1342         req = embedded_payload(wrb);
1343
1344         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1345                         OPCODE_COMMON_MANAGE_FAT);
1346
1347         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1348                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1349         req->fat_operation = cpu_to_le32(QUERY_FAT);
1350         status = be_mcc_notify_wait(adapter);
1351         if (!status) {
1352                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1353                 if (log_size && resp->log_size)
1354                         *log_size = le32_to_cpu(resp->log_size) -
1355                                         sizeof(u32);
1356         }
1357 err:
1358         spin_unlock_bh(&adapter->mcc_lock);
1359         return status;
1360 }
1361
1362 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1363 {
1364         struct be_dma_mem get_fat_cmd;
1365         struct be_mcc_wrb *wrb;
1366         struct be_cmd_req_get_fat *req;
1367         struct be_sge *sge;
1368         u32 offset = 0, total_size, buf_size,
1369                                 log_offset = sizeof(u32), payload_len;
1370         int status;
1371
1372         if (buf_len == 0)
1373                 return;
1374
1375         total_size = buf_len;
1376
1377         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1378         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1379                         get_fat_cmd.size,
1380                         &get_fat_cmd.dma);
1381         if (!get_fat_cmd.va) {
1382                 status = -ENOMEM;
1383                 dev_err(&adapter->pdev->dev,
1384                 "Memory allocation failure while retrieving FAT data\n");
1385                 return;
1386         }
1387
1388         spin_lock_bh(&adapter->mcc_lock);
1389
1390         while (total_size) {
1391                 buf_size = min(total_size, (u32)60*1024);
1392                 total_size -= buf_size;
1393
1394                 wrb = wrb_from_mccq(adapter);
1395                 if (!wrb) {
1396                         status = -EBUSY;
1397                         goto err;
1398                 }
1399                 req = get_fat_cmd.va;
1400                 sge = nonembedded_sgl(wrb);
1401
1402                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1403                 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1404                                 OPCODE_COMMON_MANAGE_FAT);
1405
1406                 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1407                                 OPCODE_COMMON_MANAGE_FAT, payload_len);
1408
1409                 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1410                 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1411                 sge->len = cpu_to_le32(get_fat_cmd.size);
1412
1413                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1414                 req->read_log_offset = cpu_to_le32(log_offset);
1415                 req->read_log_length = cpu_to_le32(buf_size);
1416                 req->data_buffer_size = cpu_to_le32(buf_size);
1417
1418                 status = be_mcc_notify_wait(adapter);
1419                 if (!status) {
1420                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1421                         memcpy(buf + offset,
1422                                 resp->data_buffer,
1423                                 resp->read_log_length);
1424                 } else {
1425                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1426                         goto err;
1427                 }
1428                 offset += buf_size;
1429                 log_offset += buf_size;
1430         }
1431 err:
1432         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1433                         get_fat_cmd.va,
1434                         get_fat_cmd.dma);
1435         spin_unlock_bh(&adapter->mcc_lock);
1436 }
1437
1438 /* Uses Mbox */
1439 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1440 {
1441         struct be_mcc_wrb *wrb;
1442         struct be_cmd_req_get_fw_version *req;
1443         int status;
1444
1445         if (mutex_lock_interruptible(&adapter->mbox_lock))
1446                 return -1;
1447
1448         wrb = wrb_from_mbox(adapter);
1449         req = embedded_payload(wrb);
1450
1451         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1452                         OPCODE_COMMON_GET_FW_VERSION);
1453
1454         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1455                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1456
1457         status = be_mbox_notify_wait(adapter);
1458         if (!status) {
1459                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1460                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1461         }
1462
1463         mutex_unlock(&adapter->mbox_lock);
1464         return status;
1465 }
1466
1467 /* set the EQ delay interval of an EQ to specified value
1468  * Uses async mcc
1469  */
1470 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1471 {
1472         struct be_mcc_wrb *wrb;
1473         struct be_cmd_req_modify_eq_delay *req;
1474         int status = 0;
1475
1476         spin_lock_bh(&adapter->mcc_lock);
1477
1478         wrb = wrb_from_mccq(adapter);
1479         if (!wrb) {
1480                 status = -EBUSY;
1481                 goto err;
1482         }
1483         req = embedded_payload(wrb);
1484
1485         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1486                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1487
1488         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1490
1491         req->num_eq = cpu_to_le32(1);
1492         req->delay[0].eq_id = cpu_to_le32(eq_id);
1493         req->delay[0].phase = 0;
1494         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1495
1496         be_mcc_notify(adapter);
1497
1498 err:
1499         spin_unlock_bh(&adapter->mcc_lock);
1500         return status;
1501 }
1502
1503 /* Uses sycnhronous mcc */
1504 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1505                         u32 num, bool untagged, bool promiscuous)
1506 {
1507         struct be_mcc_wrb *wrb;
1508         struct be_cmd_req_vlan_config *req;
1509         int status;
1510
1511         spin_lock_bh(&adapter->mcc_lock);
1512
1513         wrb = wrb_from_mccq(adapter);
1514         if (!wrb) {
1515                 status = -EBUSY;
1516                 goto err;
1517         }
1518         req = embedded_payload(wrb);
1519
1520         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1521                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1522
1523         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1524                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1525
1526         req->interface_id = if_id;
1527         req->promiscuous = promiscuous;
1528         req->untagged = untagged;
1529         req->num_vlan = num;
1530         if (!promiscuous) {
1531                 memcpy(req->normal_vlan, vtag_array,
1532                         req->num_vlan * sizeof(vtag_array[0]));
1533         }
1534
1535         status = be_mcc_notify_wait(adapter);
1536
1537 err:
1538         spin_unlock_bh(&adapter->mcc_lock);
1539         return status;
1540 }
1541
1542 /* Uses MCC for this command as it may be called in BH context
1543  * Uses synchronous mcc
1544  */
1545 int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
1546 {
1547         struct be_mcc_wrb *wrb;
1548         struct be_cmd_req_rx_filter *req;
1549         struct be_dma_mem promiscous_cmd;
1550         struct be_sge *sge;
1551         int status;
1552
1553         memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
1554         promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
1555         promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
1556                                 promiscous_cmd.size, &promiscous_cmd.dma);
1557         if (!promiscous_cmd.va) {
1558                 dev_err(&adapter->pdev->dev,
1559                                 "Memory allocation failure\n");
1560                 return -ENOMEM;
1561         }
1562
1563         spin_lock_bh(&adapter->mcc_lock);
1564
1565         wrb = wrb_from_mccq(adapter);
1566         if (!wrb) {
1567                 status = -EBUSY;
1568                 goto err;
1569         }
1570
1571         req = promiscous_cmd.va;
1572         sge = nonembedded_sgl(wrb);
1573
1574         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1575                                         OPCODE_COMMON_NTWK_RX_FILTER);
1576         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1577                         OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1578
1579         req->if_id = cpu_to_le32(adapter->if_handle);
1580         req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1581         if (en)
1582                 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1583
1584         sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
1585         sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
1586         sge->len = cpu_to_le32(promiscous_cmd.size);
1587
1588         status = be_mcc_notify_wait(adapter);
1589
1590 err:
1591         spin_unlock_bh(&adapter->mcc_lock);
1592         pci_free_consistent(adapter->pdev, promiscous_cmd.size,
1593                         promiscous_cmd.va, promiscous_cmd.dma);
1594         return status;
1595 }
1596
1597 /*
1598  * Uses MCC for this command as it may be called in BH context
1599  * (mc == NULL) => multicast promiscuous
1600  */
1601 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1602                 struct net_device *netdev, struct be_dma_mem *mem)
1603 {
1604         struct be_mcc_wrb *wrb;
1605         struct be_cmd_req_mcast_mac_config *req = mem->va;
1606         struct be_sge *sge;
1607         int status;
1608
1609         spin_lock_bh(&adapter->mcc_lock);
1610
1611         wrb = wrb_from_mccq(adapter);
1612         if (!wrb) {
1613                 status = -EBUSY;
1614                 goto err;
1615         }
1616         sge = nonembedded_sgl(wrb);
1617         memset(req, 0, sizeof(*req));
1618
1619         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1620                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1621         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1622         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1623         sge->len = cpu_to_le32(mem->size);
1624
1625         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1626                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1627
1628         req->interface_id = if_id;
1629         if (netdev) {
1630                 int i;
1631                 struct netdev_hw_addr *ha;
1632
1633                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1634
1635                 i = 0;
1636                 netdev_for_each_mc_addr(ha, netdev)
1637                         memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1638         } else {
1639                 req->promiscuous = 1;
1640         }
1641
1642         status = be_mcc_notify_wait(adapter);
1643
1644 err:
1645         spin_unlock_bh(&adapter->mcc_lock);
1646         return status;
1647 }
1648
1649 /* Uses synchrounous mcc */
1650 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1651 {
1652         struct be_mcc_wrb *wrb;
1653         struct be_cmd_req_set_flow_control *req;
1654         int status;
1655
1656         spin_lock_bh(&adapter->mcc_lock);
1657
1658         wrb = wrb_from_mccq(adapter);
1659         if (!wrb) {
1660                 status = -EBUSY;
1661                 goto err;
1662         }
1663         req = embedded_payload(wrb);
1664
1665         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1666                         OPCODE_COMMON_SET_FLOW_CONTROL);
1667
1668         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1669                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1670
1671         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1672         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1673
1674         status = be_mcc_notify_wait(adapter);
1675
1676 err:
1677         spin_unlock_bh(&adapter->mcc_lock);
1678         return status;
1679 }
1680
1681 /* Uses sycn mcc */
1682 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1683 {
1684         struct be_mcc_wrb *wrb;
1685         struct be_cmd_req_get_flow_control *req;
1686         int status;
1687
1688         spin_lock_bh(&adapter->mcc_lock);
1689
1690         wrb = wrb_from_mccq(adapter);
1691         if (!wrb) {
1692                 status = -EBUSY;
1693                 goto err;
1694         }
1695         req = embedded_payload(wrb);
1696
1697         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1698                         OPCODE_COMMON_GET_FLOW_CONTROL);
1699
1700         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1701                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1702
1703         status = be_mcc_notify_wait(adapter);
1704         if (!status) {
1705                 struct be_cmd_resp_get_flow_control *resp =
1706                                                 embedded_payload(wrb);
1707                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1708                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1709         }
1710
1711 err:
1712         spin_unlock_bh(&adapter->mcc_lock);
1713         return status;
1714 }
1715
1716 /* Uses mbox */
1717 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1718                 u32 *mode, u32 *caps)
1719 {
1720         struct be_mcc_wrb *wrb;
1721         struct be_cmd_req_query_fw_cfg *req;
1722         int status;
1723
1724         if (mutex_lock_interruptible(&adapter->mbox_lock))
1725                 return -1;
1726
1727         wrb = wrb_from_mbox(adapter);
1728         req = embedded_payload(wrb);
1729
1730         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1731                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1732
1733         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1734                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1735
1736         status = be_mbox_notify_wait(adapter);
1737         if (!status) {
1738                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1739                 *port_num = le32_to_cpu(resp->phys_port);
1740                 *mode = le32_to_cpu(resp->function_mode);
1741                 *caps = le32_to_cpu(resp->function_caps);
1742         }
1743
1744         mutex_unlock(&adapter->mbox_lock);
1745         return status;
1746 }
1747
1748 /* Uses mbox */
1749 int be_cmd_reset_function(struct be_adapter *adapter)
1750 {
1751         struct be_mcc_wrb *wrb;
1752         struct be_cmd_req_hdr *req;
1753         int status;
1754
1755         if (mutex_lock_interruptible(&adapter->mbox_lock))
1756                 return -1;
1757
1758         wrb = wrb_from_mbox(adapter);
1759         req = embedded_payload(wrb);
1760
1761         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1762                         OPCODE_COMMON_FUNCTION_RESET);
1763
1764         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1765                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1766
1767         status = be_mbox_notify_wait(adapter);
1768
1769         mutex_unlock(&adapter->mbox_lock);
1770         return status;
1771 }
1772
1773 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1774 {
1775         struct be_mcc_wrb *wrb;
1776         struct be_cmd_req_rss_config *req;
1777         u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1778                         0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
1779         int status;
1780
1781         if (mutex_lock_interruptible(&adapter->mbox_lock))
1782                 return -1;
1783
1784         wrb = wrb_from_mbox(adapter);
1785         req = embedded_payload(wrb);
1786
1787         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1788                 OPCODE_ETH_RSS_CONFIG);
1789
1790         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1791                 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1792
1793         req->if_id = cpu_to_le32(adapter->if_handle);
1794         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1795         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1796         memcpy(req->cpu_table, rsstable, table_size);
1797         memcpy(req->hash, myhash, sizeof(myhash));
1798         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1799
1800         status = be_mbox_notify_wait(adapter);
1801
1802         mutex_unlock(&adapter->mbox_lock);
1803         return status;
1804 }
1805
1806 /* Uses sync mcc */
1807 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1808                         u8 bcn, u8 sts, u8 state)
1809 {
1810         struct be_mcc_wrb *wrb;
1811         struct be_cmd_req_enable_disable_beacon *req;
1812         int status;
1813
1814         spin_lock_bh(&adapter->mcc_lock);
1815
1816         wrb = wrb_from_mccq(adapter);
1817         if (!wrb) {
1818                 status = -EBUSY;
1819                 goto err;
1820         }
1821         req = embedded_payload(wrb);
1822
1823         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1824                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1825
1826         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1827                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1828
1829         req->port_num = port_num;
1830         req->beacon_state = state;
1831         req->beacon_duration = bcn;
1832         req->status_duration = sts;
1833
1834         status = be_mcc_notify_wait(adapter);
1835
1836 err:
1837         spin_unlock_bh(&adapter->mcc_lock);
1838         return status;
1839 }
1840
1841 /* Uses sync mcc */
1842 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1843 {
1844         struct be_mcc_wrb *wrb;
1845         struct be_cmd_req_get_beacon_state *req;
1846         int status;
1847
1848         spin_lock_bh(&adapter->mcc_lock);
1849
1850         wrb = wrb_from_mccq(adapter);
1851         if (!wrb) {
1852                 status = -EBUSY;
1853                 goto err;
1854         }
1855         req = embedded_payload(wrb);
1856
1857         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1858                         OPCODE_COMMON_GET_BEACON_STATE);
1859
1860         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1861                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1862
1863         req->port_num = port_num;
1864
1865         status = be_mcc_notify_wait(adapter);
1866         if (!status) {
1867                 struct be_cmd_resp_get_beacon_state *resp =
1868                                                 embedded_payload(wrb);
1869                 *state = resp->beacon_state;
1870         }
1871
1872 err:
1873         spin_unlock_bh(&adapter->mcc_lock);
1874         return status;
1875 }
1876
1877 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1878                         u32 data_size, u32 data_offset, const char *obj_name,
1879                         u32 *data_written, u8 *addn_status)
1880 {
1881         struct be_mcc_wrb *wrb;
1882         struct lancer_cmd_req_write_object *req;
1883         struct lancer_cmd_resp_write_object *resp;
1884         void *ctxt = NULL;
1885         int status;
1886
1887         spin_lock_bh(&adapter->mcc_lock);
1888         adapter->flash_status = 0;
1889
1890         wrb = wrb_from_mccq(adapter);
1891         if (!wrb) {
1892                 status = -EBUSY;
1893                 goto err_unlock;
1894         }
1895
1896         req = embedded_payload(wrb);
1897
1898         be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
1899                         true, 1, OPCODE_COMMON_WRITE_OBJECT);
1900         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1901
1902         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1903                                 OPCODE_COMMON_WRITE_OBJECT,
1904                                 sizeof(struct lancer_cmd_req_write_object));
1905
1906         ctxt = &req->context;
1907         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1908                         write_length, ctxt, data_size);
1909
1910         if (data_size == 0)
1911                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1912                                 eof, ctxt, 1);
1913         else
1914                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1915                                 eof, ctxt, 0);
1916
1917         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1918         req->write_offset = cpu_to_le32(data_offset);
1919         strcpy(req->object_name, obj_name);
1920         req->descriptor_count = cpu_to_le32(1);
1921         req->buf_len = cpu_to_le32(data_size);
1922         req->addr_low = cpu_to_le32((cmd->dma +
1923                                 sizeof(struct lancer_cmd_req_write_object))
1924                                 & 0xFFFFFFFF);
1925         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1926                                 sizeof(struct lancer_cmd_req_write_object)));
1927
1928         be_mcc_notify(adapter);
1929         spin_unlock_bh(&adapter->mcc_lock);
1930
1931         if (!wait_for_completion_timeout(&adapter->flash_compl,
1932                         msecs_to_jiffies(12000)))
1933                 status = -1;
1934         else
1935                 status = adapter->flash_status;
1936
1937         resp = embedded_payload(wrb);
1938         if (!status) {
1939                 *data_written = le32_to_cpu(resp->actual_write_len);
1940         } else {
1941                 *addn_status = resp->additional_status;
1942                 status = resp->status;
1943         }
1944
1945         return status;
1946
1947 err_unlock:
1948         spin_unlock_bh(&adapter->mcc_lock);
1949         return status;
1950 }
1951
1952 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1953                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1954 {
1955         struct be_mcc_wrb *wrb;
1956         struct be_cmd_write_flashrom *req;
1957         struct be_sge *sge;
1958         int status;
1959
1960         spin_lock_bh(&adapter->mcc_lock);
1961         adapter->flash_status = 0;
1962
1963         wrb = wrb_from_mccq(adapter);
1964         if (!wrb) {
1965                 status = -EBUSY;
1966                 goto err_unlock;
1967         }
1968         req = cmd->va;
1969         sge = nonembedded_sgl(wrb);
1970
1971         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1972                         OPCODE_COMMON_WRITE_FLASHROM);
1973         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1974
1975         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1976                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1977         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1978         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1979         sge->len = cpu_to_le32(cmd->size);
1980
1981         req->params.op_type = cpu_to_le32(flash_type);
1982         req->params.op_code = cpu_to_le32(flash_opcode);
1983         req->params.data_buf_size = cpu_to_le32(buf_size);
1984
1985         be_mcc_notify(adapter);
1986         spin_unlock_bh(&adapter->mcc_lock);
1987
1988         if (!wait_for_completion_timeout(&adapter->flash_compl,
1989                         msecs_to_jiffies(12000)))
1990                 status = -1;
1991         else
1992                 status = adapter->flash_status;
1993
1994         return status;
1995
1996 err_unlock:
1997         spin_unlock_bh(&adapter->mcc_lock);
1998         return status;
1999 }
2000
2001 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2002                          int offset)
2003 {
2004         struct be_mcc_wrb *wrb;
2005         struct be_cmd_write_flashrom *req;
2006         int status;
2007
2008         spin_lock_bh(&adapter->mcc_lock);
2009
2010         wrb = wrb_from_mccq(adapter);
2011         if (!wrb) {
2012                 status = -EBUSY;
2013                 goto err;
2014         }
2015         req = embedded_payload(wrb);
2016
2017         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
2018                         OPCODE_COMMON_READ_FLASHROM);
2019
2020         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2021                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
2022
2023         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
2024         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2025         req->params.offset = cpu_to_le32(offset);
2026         req->params.data_buf_size = cpu_to_le32(0x4);
2027
2028         status = be_mcc_notify_wait(adapter);
2029         if (!status)
2030                 memcpy(flashed_crc, req->params.data_buf, 4);
2031
2032 err:
2033         spin_unlock_bh(&adapter->mcc_lock);
2034         return status;
2035 }
2036
2037 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2038                                 struct be_dma_mem *nonemb_cmd)
2039 {
2040         struct be_mcc_wrb *wrb;
2041         struct be_cmd_req_acpi_wol_magic_config *req;
2042         struct be_sge *sge;
2043         int status;
2044
2045         spin_lock_bh(&adapter->mcc_lock);
2046
2047         wrb = wrb_from_mccq(adapter);
2048         if (!wrb) {
2049                 status = -EBUSY;
2050                 goto err;
2051         }
2052         req = nonemb_cmd->va;
2053         sge = nonembedded_sgl(wrb);
2054
2055         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2056                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
2057
2058         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2059                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
2060         memcpy(req->magic_mac, mac, ETH_ALEN);
2061
2062         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2063         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2064         sge->len = cpu_to_le32(nonemb_cmd->size);
2065
2066         status = be_mcc_notify_wait(adapter);
2067
2068 err:
2069         spin_unlock_bh(&adapter->mcc_lock);
2070         return status;
2071 }
2072
2073 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2074                         u8 loopback_type, u8 enable)
2075 {
2076         struct be_mcc_wrb *wrb;
2077         struct be_cmd_req_set_lmode *req;
2078         int status;
2079
2080         spin_lock_bh(&adapter->mcc_lock);
2081
2082         wrb = wrb_from_mccq(adapter);
2083         if (!wrb) {
2084                 status = -EBUSY;
2085                 goto err;
2086         }
2087
2088         req = embedded_payload(wrb);
2089
2090         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2091                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
2092
2093         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2094                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2095                         sizeof(*req));
2096
2097         req->src_port = port_num;
2098         req->dest_port = port_num;
2099         req->loopback_type = loopback_type;
2100         req->loopback_state = enable;
2101
2102         status = be_mcc_notify_wait(adapter);
2103 err:
2104         spin_unlock_bh(&adapter->mcc_lock);
2105         return status;
2106 }
2107
2108 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2109                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2110 {
2111         struct be_mcc_wrb *wrb;
2112         struct be_cmd_req_loopback_test *req;
2113         int status;
2114
2115         spin_lock_bh(&adapter->mcc_lock);
2116
2117         wrb = wrb_from_mccq(adapter);
2118         if (!wrb) {
2119                 status = -EBUSY;
2120                 goto err;
2121         }
2122
2123         req = embedded_payload(wrb);
2124
2125         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2126                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
2127
2128         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2129                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2130         req->hdr.timeout = cpu_to_le32(4);
2131
2132         req->pattern = cpu_to_le64(pattern);
2133         req->src_port = cpu_to_le32(port_num);
2134         req->dest_port = cpu_to_le32(port_num);
2135         req->pkt_size = cpu_to_le32(pkt_size);
2136         req->num_pkts = cpu_to_le32(num_pkts);
2137         req->loopback_type = cpu_to_le32(loopback_type);
2138
2139         status = be_mcc_notify_wait(adapter);
2140         if (!status) {
2141                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2142                 status = le32_to_cpu(resp->status);
2143         }
2144
2145 err:
2146         spin_unlock_bh(&adapter->mcc_lock);
2147         return status;
2148 }
2149
2150 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2151                                 u32 byte_cnt, struct be_dma_mem *cmd)
2152 {
2153         struct be_mcc_wrb *wrb;
2154         struct be_cmd_req_ddrdma_test *req;
2155         struct be_sge *sge;
2156         int status;
2157         int i, j = 0;
2158
2159         spin_lock_bh(&adapter->mcc_lock);
2160
2161         wrb = wrb_from_mccq(adapter);
2162         if (!wrb) {
2163                 status = -EBUSY;
2164                 goto err;
2165         }
2166         req = cmd->va;
2167         sge = nonembedded_sgl(wrb);
2168         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
2169                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2170         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2171                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2172
2173         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2174         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2175         sge->len = cpu_to_le32(cmd->size);
2176
2177         req->pattern = cpu_to_le64(pattern);
2178         req->byte_count = cpu_to_le32(byte_cnt);
2179         for (i = 0; i < byte_cnt; i++) {
2180                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2181                 j++;
2182                 if (j > 7)
2183                         j = 0;
2184         }
2185
2186         status = be_mcc_notify_wait(adapter);
2187
2188         if (!status) {
2189                 struct be_cmd_resp_ddrdma_test *resp;
2190                 resp = cmd->va;
2191                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2192                                 resp->snd_err) {
2193                         status = -1;
2194                 }
2195         }
2196
2197 err:
2198         spin_unlock_bh(&adapter->mcc_lock);
2199         return status;
2200 }
2201
2202 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2203                                 struct be_dma_mem *nonemb_cmd)
2204 {
2205         struct be_mcc_wrb *wrb;
2206         struct be_cmd_req_seeprom_read *req;
2207         struct be_sge *sge;
2208         int status;
2209
2210         spin_lock_bh(&adapter->mcc_lock);
2211
2212         wrb = wrb_from_mccq(adapter);
2213         if (!wrb) {
2214                 status = -EBUSY;
2215                 goto err;
2216         }
2217         req = nonemb_cmd->va;
2218         sge = nonembedded_sgl(wrb);
2219
2220         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2221                         OPCODE_COMMON_SEEPROM_READ);
2222
2223         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2224                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2225
2226         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2227         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2228         sge->len = cpu_to_le32(nonemb_cmd->size);
2229
2230         status = be_mcc_notify_wait(adapter);
2231
2232 err:
2233         spin_unlock_bh(&adapter->mcc_lock);
2234         return status;
2235 }
2236
2237 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2238 {
2239         struct be_mcc_wrb *wrb;
2240         struct be_cmd_req_get_phy_info *req;
2241         struct be_sge *sge;
2242         int status;
2243
2244         spin_lock_bh(&adapter->mcc_lock);
2245
2246         wrb = wrb_from_mccq(adapter);
2247         if (!wrb) {
2248                 status = -EBUSY;
2249                 goto err;
2250         }
2251
2252         req = cmd->va;
2253         sge = nonembedded_sgl(wrb);
2254
2255         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2256                                 OPCODE_COMMON_GET_PHY_DETAILS);
2257
2258         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2259                         OPCODE_COMMON_GET_PHY_DETAILS,
2260                         sizeof(*req));
2261
2262         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2263         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2264         sge->len = cpu_to_le32(cmd->size);
2265
2266         status = be_mcc_notify_wait(adapter);
2267 err:
2268         spin_unlock_bh(&adapter->mcc_lock);
2269         return status;
2270 }
2271
2272 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2273 {
2274         struct be_mcc_wrb *wrb;
2275         struct be_cmd_req_set_qos *req;
2276         int status;
2277
2278         spin_lock_bh(&adapter->mcc_lock);
2279
2280         wrb = wrb_from_mccq(adapter);
2281         if (!wrb) {
2282                 status = -EBUSY;
2283                 goto err;
2284         }
2285
2286         req = embedded_payload(wrb);
2287
2288         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2289                                 OPCODE_COMMON_SET_QOS);
2290
2291         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2292                         OPCODE_COMMON_SET_QOS, sizeof(*req));
2293
2294         req->hdr.domain = domain;
2295         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2296         req->max_bps_nic = cpu_to_le32(bps);
2297
2298         status = be_mcc_notify_wait(adapter);
2299
2300 err:
2301         spin_unlock_bh(&adapter->mcc_lock);
2302         return status;
2303 }
2304
2305 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2306 {
2307         struct be_mcc_wrb *wrb;
2308         struct be_cmd_req_cntl_attribs *req;
2309         struct be_cmd_resp_cntl_attribs *resp;
2310         struct be_sge *sge;
2311         int status;
2312         int payload_len = max(sizeof(*req), sizeof(*resp));
2313         struct mgmt_controller_attrib *attribs;
2314         struct be_dma_mem attribs_cmd;
2315
2316         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2317         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2318         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2319                                                 &attribs_cmd.dma);
2320         if (!attribs_cmd.va) {
2321                 dev_err(&adapter->pdev->dev,
2322                                 "Memory allocation failure\n");
2323                 return -ENOMEM;
2324         }
2325
2326         if (mutex_lock_interruptible(&adapter->mbox_lock))
2327                 return -1;
2328
2329         wrb = wrb_from_mbox(adapter);
2330         if (!wrb) {
2331                 status = -EBUSY;
2332                 goto err;
2333         }
2334         req = attribs_cmd.va;
2335         sge = nonembedded_sgl(wrb);
2336
2337         be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2338                         OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2339         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2340                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2341         sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2342         sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2343         sge->len = cpu_to_le32(attribs_cmd.size);
2344
2345         status = be_mbox_notify_wait(adapter);
2346         if (!status) {
2347                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2348                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2349         }
2350
2351 err:
2352         mutex_unlock(&adapter->mbox_lock);
2353         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2354                                         attribs_cmd.dma);
2355         return status;
2356 }
2357
2358 /* Uses mbox */
2359 int be_cmd_check_native_mode(struct be_adapter *adapter)
2360 {
2361         struct be_mcc_wrb *wrb;
2362         struct be_cmd_req_set_func_cap *req;
2363         int status;
2364
2365         if (mutex_lock_interruptible(&adapter->mbox_lock))
2366                 return -1;
2367
2368         wrb = wrb_from_mbox(adapter);
2369         if (!wrb) {
2370                 status = -EBUSY;
2371                 goto err;
2372         }
2373
2374         req = embedded_payload(wrb);
2375
2376         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2377                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2378
2379         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2380                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2381
2382         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2383                                 CAPABILITY_BE3_NATIVE_ERX_API);
2384         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2385
2386         status = be_mbox_notify_wait(adapter);
2387         if (!status) {
2388                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2389                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2390                                         CAPABILITY_BE3_NATIVE_ERX_API;
2391         }
2392 err:
2393         mutex_unlock(&adapter->mbox_lock);
2394         return status;
2395 }