1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
40 /****************************************************************************
41 * Shared HW configuration *
42 ****************************************************************************/
43 struct shared_hw_cfg { /* NVRAM Offset */
44 /* Up to 16 bytes of NULL-terminated string */
45 u8 part_num[16]; /* 0x104 */
47 u32 config; /* 0x114 */
48 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
49 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
50 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
51 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
52 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
54 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
56 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
58 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
59 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
60 /* Whatever MFW found in NVM
61 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
62 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
63 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
64 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
65 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
66 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
67 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
68 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
69 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
70 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
71 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
72 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
73 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
74 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
76 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
77 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
78 #define SHARED_HW_CFG_LED_MAC1 0x00000000
79 #define SHARED_HW_CFG_LED_PHY1 0x00010000
80 #define SHARED_HW_CFG_LED_PHY2 0x00020000
81 #define SHARED_HW_CFG_LED_PHY3 0x00030000
82 #define SHARED_HW_CFG_LED_MAC2 0x00040000
83 #define SHARED_HW_CFG_LED_PHY4 0x00050000
84 #define SHARED_HW_CFG_LED_PHY5 0x00060000
85 #define SHARED_HW_CFG_LED_PHY6 0x00070000
86 #define SHARED_HW_CFG_LED_MAC3 0x00080000
87 #define SHARED_HW_CFG_LED_PHY7 0x00090000
88 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
89 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
90 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
91 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
92 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
95 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
96 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
97 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
98 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
99 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
100 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
101 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
102 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
104 u32 config2; /* 0x118 */
105 /* one time auto detect grace period (in sec) */
106 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
107 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
109 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
111 /* The default value for the core clock is 250MHz and it is
112 achieved by setting the clock change to 4 */
113 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
114 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
116 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
117 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
119 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
121 /* The fan failure mechanism is usually related to the PHY type
122 since the power consumption of the board is determined by the PHY.
123 Currently, fan is required for most designs with SFX7101, BCM8727
124 and BCM8481. If a fan is not required for a board which uses one
125 of those PHYs, this field should be set to "Disabled". If a fan is
126 required for a different PHY type, this option should be set to
128 The fan failure indication is expected on
130 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
131 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
132 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
133 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
134 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
136 /* Set the MDC/MDIO access for the first external phy */
137 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
138 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
145 /* Set the MDC/MDIO access for the second external phy */
146 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
147 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
148 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
149 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
150 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
151 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
152 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
153 u32 power_dissipated; /* 0x11c */
154 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
155 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
157 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
158 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
159 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
160 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
161 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
162 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
164 u32 ump_nc_si_config; /* 0x120 */
165 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
166 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
167 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
168 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
169 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
170 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
172 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
173 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
175 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
176 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
177 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
178 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
180 u32 board; /* 0x124 */
181 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
182 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
184 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
185 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
187 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
188 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
190 u32 reserved; /* 0x128 */
195 /****************************************************************************
196 * Port HW configuration *
197 ****************************************************************************/
198 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
201 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
202 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
205 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
206 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
208 u32 power_dissipated;
209 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
210 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
211 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
212 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
213 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
214 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
215 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
216 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
219 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
220 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
221 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
222 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
223 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
224 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
225 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
226 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
229 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
230 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
233 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
236 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
240 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
241 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
243 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
244 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
247 u32 Reserved0[3]; /* 0x158 */
248 /* Controls the TX laser of the SFP+ module */
249 u32 sfp_ctrl; /* 0x164 */
250 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
251 #define PORT_HW_CFG_TX_LASER_SHIFT 0
252 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
253 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
254 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
255 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
256 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
258 /* Controls the fault module LED of the SFP+ */
259 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
260 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
261 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
262 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
263 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
264 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
265 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
266 u32 Reserved01[11]; /* 0x158 */
268 u32 media_type; /* 0x194 */
269 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
270 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
272 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
273 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
275 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
276 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
277 /* for external PHY, or forced mode or during AN */
278 u16 xgxs_config_rx[4]; /* 0x198 */
280 u16 xgxs_config_tx[4]; /* 0x1A0 */
282 u32 Reserved1[56]; /* 0x1A8 */
283 u32 default_cfg; /* 0x288 */
284 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
285 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
286 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
287 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
288 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
289 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
291 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
292 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
293 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
294 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
295 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
296 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
298 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
299 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
300 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
301 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
302 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
303 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
305 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
306 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
307 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
308 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
309 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
310 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
313 * When KR link is required to be set to force which is not
314 * KR-compliant, this parameter determine what is the trigger for it.
315 * When GPIO is selected, low input will force the speed. Currently
316 * default speed is 1G. In the future, it may be widen to select the
317 * forced speed in with another parameter. Note when force-1G is
318 * enabled, it override option 56: Link Speed option.
320 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
321 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
322 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
323 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
324 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
325 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
326 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
327 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
328 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
329 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
330 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
331 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
332 /* Enable to determine with which GPIO to reset the external phy */
333 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
334 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
335 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
336 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
337 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
338 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
339 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
340 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
341 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
342 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
343 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
344 /* Enable BAM on KR */
345 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
346 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
347 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
348 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
350 /* Enable Common Mode Sense */
351 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
352 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
353 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
354 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
356 u32 speed_capability_mask2; /* 0x28C */
357 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
358 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
359 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
360 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
361 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
362 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
363 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
364 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
365 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
366 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
367 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
368 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
369 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
370 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
372 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
373 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
374 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
375 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
376 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
377 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
378 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
379 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
380 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
381 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
382 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
383 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
384 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
385 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
387 /* In the case where two media types (e.g. copper and fiber) are
388 present and electrically active at the same time, PHY Selection
389 will determine which of the two PHYs will be designated as the
390 Active PHY and used for a connection to the network. */
391 u32 multi_phy_config; /* 0x290 */
392 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
393 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
394 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
395 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
396 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
397 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
398 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
400 /* When enabled, all second phy nvram parameters will be swapped
401 with the first phy parameters */
402 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
403 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
404 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
405 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
408 /* Address of the second external phy */
409 u32 external_phy_config2; /* 0x294 */
410 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
411 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
413 /* The second XGXS external PHY type */
414 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
415 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
416 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
417 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
418 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
419 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
420 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
421 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
422 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
423 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
424 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
425 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
426 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
427 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
428 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
429 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
430 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
431 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
432 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
434 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
435 8706, 8726 and 8727) not all 4 values are needed. */
436 u16 xgxs_config2_rx[4]; /* 0x296 */
437 u16 xgxs_config2_tx[4]; /* 0x2A0 */
440 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
441 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
443 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
444 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
445 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
446 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
447 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
448 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
450 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
452 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
454 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
456 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
457 /* Indicate whether to swap the external phy polarity */
458 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
459 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
460 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
462 u32 external_phy_config;
463 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
464 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
465 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
466 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
467 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
469 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
470 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
472 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
473 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
474 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
475 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
476 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
477 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
478 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
479 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
480 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
481 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
482 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
483 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
484 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
485 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
486 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
487 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
488 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
489 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
491 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
492 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
494 u32 speed_capability_mask;
495 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
496 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
497 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
498 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
499 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
500 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
501 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
502 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
503 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
504 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
505 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
506 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
507 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
508 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
509 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
511 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
512 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
513 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
514 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
515 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
516 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
517 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
518 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
519 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
520 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
521 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
522 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
523 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
524 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
525 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
532 /****************************************************************************
533 * Shared Feature configuration *
534 ****************************************************************************/
535 struct shared_feat_cfg { /* NVRAM Offset */
537 u32 config; /* 0x450 */
538 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
540 /* Use the values from options 47 and 48 instead of the HW default
542 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
543 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
545 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
546 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
547 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
548 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
549 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
550 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
555 /****************************************************************************
556 * Port Feature configuration *
557 ****************************************************************************/
558 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
561 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
562 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
563 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
564 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
565 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
566 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
567 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
568 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
569 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
570 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
571 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
572 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
573 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
574 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
575 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
576 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
577 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
578 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
579 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
580 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
581 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
582 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
583 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
584 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
585 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
586 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
587 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
588 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
589 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
590 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
591 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
592 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
593 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
594 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
595 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
596 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
597 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
598 #define PORT_FEATURE_EN_SIZE_SHIFT 24
599 #define PORT_FEATURE_WOL_ENABLED 0x01000000
600 #define PORT_FEATURE_MBA_ENABLED 0x02000000
601 #define PORT_FEATURE_MFW_ENABLED 0x04000000
603 /* Reserved bits: 28-29 */
604 /* Check the optic vendor via i2c against a list of approved modules
605 in a separate nvram image */
606 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
607 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
608 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
609 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
610 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
611 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
615 /* Default is used when driver sets to "auto" mode */
616 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
617 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
618 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
619 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
620 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
621 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
622 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
623 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
624 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
627 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
628 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
629 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
630 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
631 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
632 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
633 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
634 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
635 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
636 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
637 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
638 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
639 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
640 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
641 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
642 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
643 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
644 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
645 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
646 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
647 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
648 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
649 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
650 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
651 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
652 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
653 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
654 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
655 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
656 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
657 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
658 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
659 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
660 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
661 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
662 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
663 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
664 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
665 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
666 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
667 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
668 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
669 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
670 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
671 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
672 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
673 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
674 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
675 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
676 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
677 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
678 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
679 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
680 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
683 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
684 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
687 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
688 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
689 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
692 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
693 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
694 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
695 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
696 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
700 #define PORT_FEATURE_SMBUS_EN 0x00000001
701 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
702 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
706 u32 link_config; /* Used as HW defaults for the driver */
707 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
708 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
709 /* (forced) low speed switch (< 10G) */
710 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
711 /* (forced) high speed switch (>= 10G) */
712 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
713 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
714 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
716 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
717 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
718 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
719 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
720 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
721 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
722 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
723 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
724 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
725 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
726 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
727 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
728 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
729 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
730 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
731 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
732 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
734 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
735 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
736 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
737 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
738 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
739 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
740 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
742 /* The default for MCP link configuration,
743 uses the same defines as link_config */
744 u32 mfw_wol_link_cfg;
745 /* The default for the driver of the second external phy,
746 uses the same defines as link_config */
747 u32 link_config2; /* 0x47C */
749 /* The default for MCP of the second external phy,
750 uses the same defines as link_config */
751 u32 mfw_wol_link_cfg2; /* 0x480 */
753 u32 Reserved2[17]; /* 0x484 */
758 /****************************************************************************
759 * Device Information *
760 ****************************************************************************/
761 struct shm_dev_info { /* size */
763 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
765 struct shared_hw_cfg shared_hw_config; /* 40 */
767 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
769 struct shared_feat_cfg shared_feature_config; /* 4 */
771 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
784 #define E1_FUNC_MAX 2
785 #define E1H_FUNC_MAX 8
786 #define E2_FUNC_MAX 4 /* per path */
796 /* This value (in milliseconds) determines the frequency of the driver
797 * issuing the PULSE message code. The firmware monitors this periodic
798 * pulse to determine when to switch to an OS-absent mode. */
799 #define DRV_PULSE_PERIOD_MS 250
801 /* This value (in milliseconds) determines how long the driver should
802 * wait for an acknowledgement from the firmware before timing out. Once
803 * the firmware has timed out, the driver will assume there is no firmware
804 * running and there won't be any firmware-driver synchronization during a
806 #define FW_ACK_TIME_OUT_MS 5000
808 #define FW_ACK_POLL_TIME_MS 1
810 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
812 /* LED Blink rate that will achieve ~15.9Hz */
813 #define LED_BLINK_RATE_VAL 480
815 /****************************************************************************
816 * Driver <-> FW Mailbox *
817 ****************************************************************************/
821 /* Driver should update this field on any link change event */
823 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
824 #define LINK_STATUS_LINK_UP 0x00000001
825 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
826 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
827 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
828 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
829 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
830 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
831 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
832 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
833 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
834 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
835 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
836 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
837 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
838 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
839 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
840 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
841 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
842 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
843 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
844 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
845 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
846 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
847 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
848 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
849 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
851 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
852 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
854 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
855 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
856 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
858 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
859 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
860 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
861 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
862 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
863 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
864 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
866 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
867 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
869 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
870 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
872 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
873 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
874 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
875 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
876 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
878 #define LINK_STATUS_SERDES_LINK 0x00100000
880 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
881 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
882 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
883 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
884 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
885 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
886 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
887 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
893 /* MCP firmware does not use this field */
894 u32 ext_phy_fw_version;
902 #define DRV_MSG_CODE_MASK 0xffff0000
903 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
904 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
905 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
906 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
907 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
908 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
909 #define DRV_MSG_CODE_DCC_OK 0x30000000
910 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
911 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
912 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
913 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
914 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
915 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
916 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
917 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
919 * The optic module verification commands require bootcode
922 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
923 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
925 * The specific optic module verification command requires bootcode
928 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
929 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
931 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
932 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
933 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
934 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
935 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
936 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
937 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
938 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
939 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
941 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
946 #define FW_MSG_CODE_MASK 0xffff0000
947 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
948 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
949 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
950 /* Load common chip is supported from bc 6.0.0 */
951 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
952 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
953 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
954 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
955 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
956 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
957 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
958 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
959 #define FW_MSG_CODE_DCC_DONE 0x30100000
960 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
961 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
962 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
963 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
964 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
965 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
966 #define FW_MSG_CODE_NO_KEY 0x80f00000
967 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
968 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
969 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
970 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
971 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
972 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
973 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
974 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
975 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
977 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
978 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
979 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
980 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
982 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
987 #define DRV_PULSE_SEQ_MASK 0x00007fff
988 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
989 /* The system time is in the format of
990 * (year-2001)*12*32 + month*32 + day. */
991 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
992 /* Indicate to the firmware not to go into the
993 * OS-absent when it is not getting driver pulse.
994 * This is used for debugging as well for PXE(MBA). */
997 #define MCP_PULSE_SEQ_MASK 0x00007fff
998 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
999 /* Indicates to the driver not to assert due to lack
1000 * of MCP response */
1001 #define MCP_EVENT_MASK 0xffff0000
1002 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1004 u32 iscsi_boot_signature;
1005 u32 iscsi_boot_block_offset;
1008 #define DRV_STATUS_PMF 0x00000001
1009 #define DRV_STATUS_SET_MF_BW 0x00000004
1011 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1012 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1013 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1014 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1015 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1016 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1017 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1018 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1019 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1022 #define VIRT_MAC_SIGN_MASK 0xffff0000
1023 #define VIRT_MAC_SIGNATURE 0x564d0000
1029 /****************************************************************************
1030 * Management firmware state *
1031 ****************************************************************************/
1032 /* Allocate 440 bytes for management firmware */
1033 #define MGMTFW_STATE_WORD_SIZE 110
1035 struct mgmtfw_state {
1036 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1040 /****************************************************************************
1041 * Multi-Function configuration *
1042 ****************************************************************************/
1043 struct shared_mf_cfg {
1046 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1048 #define SHARED_MF_CLP_EXIT 0x00000001
1050 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1054 struct port_mf_cfg {
1056 u32 dynamic_cfg; /* device control channel */
1057 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1058 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1059 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1065 struct func_mf_cfg {
1069 /* function 0 of each port cannot be hidden */
1070 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1072 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
1073 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1074 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1075 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1076 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
1077 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1079 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1082 /* 0 - low priority, 3 - high priority */
1083 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1084 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1085 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1088 /* value range - 0..100, increments in 100Mbps */
1089 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1090 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1091 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1092 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1093 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1094 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1096 u32 mac_upper; /* MAC */
1097 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1098 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1099 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1101 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1103 u32 e1hov_tag; /* VNI */
1104 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1105 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1106 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1112 /* This structure is not applicable and should not be accessed on 57711 */
1113 struct func_ext_cfg {
1115 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1116 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1117 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1118 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1119 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1120 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1122 u32 iscsi_mac_addr_upper;
1123 u32 iscsi_mac_addr_lower;
1125 u32 fcoe_mac_addr_upper;
1126 u32 fcoe_mac_addr_lower;
1128 u32 fcoe_wwn_port_name_upper;
1129 u32 fcoe_wwn_port_name_lower;
1131 u32 fcoe_wwn_node_name_upper;
1132 u32 fcoe_wwn_node_name_lower;
1135 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1136 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1137 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1138 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1139 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1144 struct shared_mf_cfg shared_mf_config;
1145 struct port_mf_cfg port_mf_config[PORT_MAX];
1146 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1148 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1152 /****************************************************************************
1153 * Shared Memory Region *
1154 ****************************************************************************/
1155 struct shmem_region { /* SharedMem Offset (size) */
1157 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1158 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1159 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1161 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1162 #define SHR_MEM_VALIDITY_MB 0x00200000
1163 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1164 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1165 /* One licensing bit should be set */
1166 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1167 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1168 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1169 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1171 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1172 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1173 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1174 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1175 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1176 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1178 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1180 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1182 /* FW information (for internal FW use) */
1183 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1184 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1186 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1187 struct drv_func_mb func_mb[]; /* 0x684
1188 (44*2/4/8=0x58/0xb0/0x160) */
1190 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1201 struct fw_flr_ack ack;
1204 /**** SUPPORT FOR SHMEM ARRRAYS ***
1205 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1206 * define arrays with storage types smaller then unsigned dwords.
1207 * The macros below add generic support for SHMEM arrays with numeric elements
1208 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1209 * array with individual bit-filed elements accessed using shifts and masks.
1213 /* eb is the bitwidth of a single element */
1214 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1215 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1217 /* the bit-position macro allows the used to flip the order of the arrays
1218 * elements on a per byte or word boundary.
1220 * example: an array with 8 entries each 4 bit wide. This array will fit into
1221 * a single dword. The diagrmas below show the array order of the nibbles.
1223 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1226 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1229 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1232 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1235 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1238 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1241 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1242 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1243 (((i)%((fb)/(eb))) * (eb)))
1245 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1246 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1247 SHMEM_ARRAY_MASK(eb))
1249 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1251 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1252 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1253 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1254 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1258 /****START OF DCBX STRUCTURES DECLARATIONS****/
1259 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1260 #define DCBX_PRI_PG_BITWIDTH 4
1261 #define DCBX_PRI_PG_FBITS 8
1262 #define DCBX_PRI_PG_GET(a, i) \
1263 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1264 #define DCBX_PRI_PG_SET(a, i, val) \
1265 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1266 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1267 #define DCBX_BW_PG_BITWIDTH 8
1268 #define DCBX_PG_BW_GET(a, i) \
1269 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1270 #define DCBX_PG_BW_SET(a, i, val) \
1271 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1272 #define DCBX_STRICT_PRI_PG 15
1273 #define DCBX_MAX_APP_PROTOCOL 16
1274 #define FCOE_APP_IDX 0
1275 #define ISCSI_APP_IDX 1
1276 #define PREDEFINED_APP_IDX_MAX 2
1278 struct dcbx_ets_feature {
1284 struct dcbx_pfc_feature {
1287 #define DCBX_PFC_PRI_0 0x01
1288 #define DCBX_PFC_PRI_1 0x02
1289 #define DCBX_PFC_PRI_2 0x04
1290 #define DCBX_PFC_PRI_3 0x08
1291 #define DCBX_PFC_PRI_4 0x10
1292 #define DCBX_PFC_PRI_5 0x20
1293 #define DCBX_PFC_PRI_6 0x40
1294 #define DCBX_PFC_PRI_7 0x80
1298 #elif defined(__LITTLE_ENDIAN)
1303 #define DCBX_PFC_PRI_0 0x01
1304 #define DCBX_PFC_PRI_1 0x02
1305 #define DCBX_PFC_PRI_2 0x04
1306 #define DCBX_PFC_PRI_3 0x08
1307 #define DCBX_PFC_PRI_4 0x10
1308 #define DCBX_PFC_PRI_5 0x20
1309 #define DCBX_PFC_PRI_6 0x40
1310 #define DCBX_PFC_PRI_7 0x80
1314 struct dcbx_app_priority_entry {
1319 #define DCBX_APP_ENTRY_VALID 0x01
1320 #define DCBX_APP_ENTRY_SF_MASK 0x30
1321 #define DCBX_APP_ENTRY_SF_SHIFT 4
1322 #define DCBX_APP_SF_ETH_TYPE 0x10
1323 #define DCBX_APP_SF_PORT 0x20
1324 #elif defined(__LITTLE_ENDIAN)
1326 #define DCBX_APP_ENTRY_VALID 0x01
1327 #define DCBX_APP_ENTRY_SF_MASK 0x30
1328 #define DCBX_APP_ENTRY_SF_SHIFT 4
1329 #define DCBX_APP_SF_ETH_TYPE 0x10
1330 #define DCBX_APP_SF_PORT 0x20
1336 struct dcbx_app_priority_feature {
1342 #elif defined(__LITTLE_ENDIAN)
1348 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1351 struct dcbx_features {
1352 struct dcbx_ets_feature ets;
1353 struct dcbx_pfc_feature pfc;
1354 struct dcbx_app_priority_feature app;
1357 struct lldp_params {
1359 u8 msg_fast_tx_interval;
1363 #define LLDP_TX_ONLY 0x01
1364 #define LLDP_RX_ONLY 0x02
1365 #define LLDP_TX_RX 0x03
1366 #define LLDP_DISABLED 0x04
1371 #elif defined(__LITTLE_ENDIAN)
1373 #define LLDP_TX_ONLY 0x01
1374 #define LLDP_RX_ONLY 0x02
1375 #define LLDP_TX_RX 0x03
1376 #define LLDP_DISABLED 0x04
1379 u8 msg_fast_tx_interval;
1385 #define REM_CHASSIS_ID_STAT_LEN 4
1386 #define REM_PORT_ID_STAT_LEN 4
1387 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1388 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1391 struct lldp_dcbx_stat {
1392 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1393 #define LOCAL_PORT_ID_STAT_LEN 2
1394 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1395 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1396 u32 num_tx_dcbx_pkts;
1397 u32 num_rx_dcbx_pkts;
1400 struct lldp_admin_mib {
1402 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1403 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1404 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1405 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1406 #define DCBX_ETS_RECO_VALID 0x00000010
1407 #define DCBX_ETS_WILLING 0x00000020
1408 #define DCBX_PFC_WILLING 0x00000040
1409 #define DCBX_APP_WILLING 0x00000080
1410 #define DCBX_VERSION_CEE 0x00000100
1411 #define DCBX_VERSION_IEEE 0x00000200
1412 #define DCBX_DCBX_ENABLED 0x00000400
1413 #define DCBX_CEE_VERSION_MASK 0x0000f000
1414 #define DCBX_CEE_VERSION_SHIFT 12
1415 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1416 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1417 struct dcbx_features features;
1420 struct lldp_remote_mib {
1423 #define DCBX_ETS_TLV_RX 0x00000001
1424 #define DCBX_PFC_TLV_RX 0x00000002
1425 #define DCBX_APP_TLV_RX 0x00000004
1426 #define DCBX_ETS_RX_ERROR 0x00000010
1427 #define DCBX_PFC_RX_ERROR 0x00000020
1428 #define DCBX_APP_RX_ERROR 0x00000040
1429 #define DCBX_ETS_REM_WILLING 0x00000100
1430 #define DCBX_PFC_REM_WILLING 0x00000200
1431 #define DCBX_APP_REM_WILLING 0x00000400
1432 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1433 struct dcbx_features features;
1437 struct lldp_local_mib {
1440 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1441 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1442 #define DCBX_LOCAL_APP_ERROR 0x00000004
1443 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1444 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1445 struct dcbx_features features;
1448 /***END OF DCBX STRUCTURES DECLARATIONS***/
1450 struct shmem2_region {
1455 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1456 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1457 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1458 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1459 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1460 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1461 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1462 u32 ext_phy_fw_version2[PORT_MAX];
1464 * For backwards compatibility, if the mf_cfg_addr does not exist
1465 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1466 * end of struct shmem_region
1469 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1471 struct fw_flr_mb flr_mb;
1472 u32 dcbx_lldp_params_offset;
1473 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1474 u32 dcbx_neg_res_offset;
1475 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1476 u32 dcbx_remote_mib_offset;
1477 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1479 * The other shmemX_base_addr holds the other path's shmem address
1480 * required for example in case of common phy init, or for path1 to know
1481 * the address of mcp debug trace which is located in offset from shmem
1484 u32 other_shmem_base_addr;
1485 u32 other_shmem2_base_addr;
1486 u32 reserved1[E2_VF_MAX / 32];
1487 u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
1488 u32 dcbx_lldp_dcbx_stat_offset;
1489 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1494 u32 rx_stat_ifhcinoctets;
1495 u32 rx_stat_ifhcinbadoctets;
1496 u32 rx_stat_etherstatsfragments;
1497 u32 rx_stat_ifhcinucastpkts;
1498 u32 rx_stat_ifhcinmulticastpkts;
1499 u32 rx_stat_ifhcinbroadcastpkts;
1500 u32 rx_stat_dot3statsfcserrors;
1501 u32 rx_stat_dot3statsalignmenterrors;
1502 u32 rx_stat_dot3statscarriersenseerrors;
1503 u32 rx_stat_xonpauseframesreceived;
1504 u32 rx_stat_xoffpauseframesreceived;
1505 u32 rx_stat_maccontrolframesreceived;
1506 u32 rx_stat_xoffstateentered;
1507 u32 rx_stat_dot3statsframestoolong;
1508 u32 rx_stat_etherstatsjabbers;
1509 u32 rx_stat_etherstatsundersizepkts;
1510 u32 rx_stat_etherstatspkts64octets;
1511 u32 rx_stat_etherstatspkts65octetsto127octets;
1512 u32 rx_stat_etherstatspkts128octetsto255octets;
1513 u32 rx_stat_etherstatspkts256octetsto511octets;
1514 u32 rx_stat_etherstatspkts512octetsto1023octets;
1515 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1516 u32 rx_stat_etherstatspktsover1522octets;
1518 u32 rx_stat_falsecarriererrors;
1520 u32 tx_stat_ifhcoutoctets;
1521 u32 tx_stat_ifhcoutbadoctets;
1522 u32 tx_stat_etherstatscollisions;
1523 u32 tx_stat_outxonsent;
1524 u32 tx_stat_outxoffsent;
1525 u32 tx_stat_flowcontroldone;
1526 u32 tx_stat_dot3statssinglecollisionframes;
1527 u32 tx_stat_dot3statsmultiplecollisionframes;
1528 u32 tx_stat_dot3statsdeferredtransmissions;
1529 u32 tx_stat_dot3statsexcessivecollisions;
1530 u32 tx_stat_dot3statslatecollisions;
1531 u32 tx_stat_ifhcoutucastpkts;
1532 u32 tx_stat_ifhcoutmulticastpkts;
1533 u32 tx_stat_ifhcoutbroadcastpkts;
1534 u32 tx_stat_etherstatspkts64octets;
1535 u32 tx_stat_etherstatspkts65octetsto127octets;
1536 u32 tx_stat_etherstatspkts128octetsto255octets;
1537 u32 tx_stat_etherstatspkts256octetsto511octets;
1538 u32 tx_stat_etherstatspkts512octetsto1023octets;
1539 u32 tx_stat_etherstatspkts1024octetsto1522octets;
1540 u32 tx_stat_etherstatspktsover1522octets;
1541 u32 tx_stat_dot3statsinternalmactransmiterrors;
1545 struct bmac1_stats {
1546 u32 tx_stat_gtpkt_lo;
1547 u32 tx_stat_gtpkt_hi;
1548 u32 tx_stat_gtxpf_lo;
1549 u32 tx_stat_gtxpf_hi;
1550 u32 tx_stat_gtfcs_lo;
1551 u32 tx_stat_gtfcs_hi;
1552 u32 tx_stat_gtmca_lo;
1553 u32 tx_stat_gtmca_hi;
1554 u32 tx_stat_gtbca_lo;
1555 u32 tx_stat_gtbca_hi;
1556 u32 tx_stat_gtfrg_lo;
1557 u32 tx_stat_gtfrg_hi;
1558 u32 tx_stat_gtovr_lo;
1559 u32 tx_stat_gtovr_hi;
1560 u32 tx_stat_gt64_lo;
1561 u32 tx_stat_gt64_hi;
1562 u32 tx_stat_gt127_lo;
1563 u32 tx_stat_gt127_hi;
1564 u32 tx_stat_gt255_lo;
1565 u32 tx_stat_gt255_hi;
1566 u32 tx_stat_gt511_lo;
1567 u32 tx_stat_gt511_hi;
1568 u32 tx_stat_gt1023_lo;
1569 u32 tx_stat_gt1023_hi;
1570 u32 tx_stat_gt1518_lo;
1571 u32 tx_stat_gt1518_hi;
1572 u32 tx_stat_gt2047_lo;
1573 u32 tx_stat_gt2047_hi;
1574 u32 tx_stat_gt4095_lo;
1575 u32 tx_stat_gt4095_hi;
1576 u32 tx_stat_gt9216_lo;
1577 u32 tx_stat_gt9216_hi;
1578 u32 tx_stat_gt16383_lo;
1579 u32 tx_stat_gt16383_hi;
1580 u32 tx_stat_gtmax_lo;
1581 u32 tx_stat_gtmax_hi;
1582 u32 tx_stat_gtufl_lo;
1583 u32 tx_stat_gtufl_hi;
1584 u32 tx_stat_gterr_lo;
1585 u32 tx_stat_gterr_hi;
1586 u32 tx_stat_gtbyt_lo;
1587 u32 tx_stat_gtbyt_hi;
1589 u32 rx_stat_gr64_lo;
1590 u32 rx_stat_gr64_hi;
1591 u32 rx_stat_gr127_lo;
1592 u32 rx_stat_gr127_hi;
1593 u32 rx_stat_gr255_lo;
1594 u32 rx_stat_gr255_hi;
1595 u32 rx_stat_gr511_lo;
1596 u32 rx_stat_gr511_hi;
1597 u32 rx_stat_gr1023_lo;
1598 u32 rx_stat_gr1023_hi;
1599 u32 rx_stat_gr1518_lo;
1600 u32 rx_stat_gr1518_hi;
1601 u32 rx_stat_gr2047_lo;
1602 u32 rx_stat_gr2047_hi;
1603 u32 rx_stat_gr4095_lo;
1604 u32 rx_stat_gr4095_hi;
1605 u32 rx_stat_gr9216_lo;
1606 u32 rx_stat_gr9216_hi;
1607 u32 rx_stat_gr16383_lo;
1608 u32 rx_stat_gr16383_hi;
1609 u32 rx_stat_grmax_lo;
1610 u32 rx_stat_grmax_hi;
1611 u32 rx_stat_grpkt_lo;
1612 u32 rx_stat_grpkt_hi;
1613 u32 rx_stat_grfcs_lo;
1614 u32 rx_stat_grfcs_hi;
1615 u32 rx_stat_grmca_lo;
1616 u32 rx_stat_grmca_hi;
1617 u32 rx_stat_grbca_lo;
1618 u32 rx_stat_grbca_hi;
1619 u32 rx_stat_grxcf_lo;
1620 u32 rx_stat_grxcf_hi;
1621 u32 rx_stat_grxpf_lo;
1622 u32 rx_stat_grxpf_hi;
1623 u32 rx_stat_grxuo_lo;
1624 u32 rx_stat_grxuo_hi;
1625 u32 rx_stat_grjbr_lo;
1626 u32 rx_stat_grjbr_hi;
1627 u32 rx_stat_grovr_lo;
1628 u32 rx_stat_grovr_hi;
1629 u32 rx_stat_grflr_lo;
1630 u32 rx_stat_grflr_hi;
1631 u32 rx_stat_grmeg_lo;
1632 u32 rx_stat_grmeg_hi;
1633 u32 rx_stat_grmeb_lo;
1634 u32 rx_stat_grmeb_hi;
1635 u32 rx_stat_grbyt_lo;
1636 u32 rx_stat_grbyt_hi;
1637 u32 rx_stat_grund_lo;
1638 u32 rx_stat_grund_hi;
1639 u32 rx_stat_grfrg_lo;
1640 u32 rx_stat_grfrg_hi;
1641 u32 rx_stat_grerb_lo;
1642 u32 rx_stat_grerb_hi;
1643 u32 rx_stat_grfre_lo;
1644 u32 rx_stat_grfre_hi;
1645 u32 rx_stat_gripj_lo;
1646 u32 rx_stat_gripj_hi;
1649 struct bmac2_stats {
1650 u32 tx_stat_gtpk_lo; /* gtpok */
1651 u32 tx_stat_gtpk_hi; /* gtpok */
1652 u32 tx_stat_gtxpf_lo; /* gtpf */
1653 u32 tx_stat_gtxpf_hi; /* gtpf */
1654 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
1655 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
1656 u32 tx_stat_gtfcs_lo;
1657 u32 tx_stat_gtfcs_hi;
1658 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
1659 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
1660 u32 tx_stat_gtmca_lo;
1661 u32 tx_stat_gtmca_hi;
1662 u32 tx_stat_gtbca_lo;
1663 u32 tx_stat_gtbca_hi;
1664 u32 tx_stat_gtovr_lo;
1665 u32 tx_stat_gtovr_hi;
1666 u32 tx_stat_gtfrg_lo;
1667 u32 tx_stat_gtfrg_hi;
1668 u32 tx_stat_gtpkt1_lo; /* gtpkt */
1669 u32 tx_stat_gtpkt1_hi; /* gtpkt */
1670 u32 tx_stat_gt64_lo;
1671 u32 tx_stat_gt64_hi;
1672 u32 tx_stat_gt127_lo;
1673 u32 tx_stat_gt127_hi;
1674 u32 tx_stat_gt255_lo;
1675 u32 tx_stat_gt255_hi;
1676 u32 tx_stat_gt511_lo;
1677 u32 tx_stat_gt511_hi;
1678 u32 tx_stat_gt1023_lo;
1679 u32 tx_stat_gt1023_hi;
1680 u32 tx_stat_gt1518_lo;
1681 u32 tx_stat_gt1518_hi;
1682 u32 tx_stat_gt2047_lo;
1683 u32 tx_stat_gt2047_hi;
1684 u32 tx_stat_gt4095_lo;
1685 u32 tx_stat_gt4095_hi;
1686 u32 tx_stat_gt9216_lo;
1687 u32 tx_stat_gt9216_hi;
1688 u32 tx_stat_gt16383_lo;
1689 u32 tx_stat_gt16383_hi;
1690 u32 tx_stat_gtmax_lo;
1691 u32 tx_stat_gtmax_hi;
1692 u32 tx_stat_gtufl_lo;
1693 u32 tx_stat_gtufl_hi;
1694 u32 tx_stat_gterr_lo;
1695 u32 tx_stat_gterr_hi;
1696 u32 tx_stat_gtbyt_lo;
1697 u32 tx_stat_gtbyt_hi;
1699 u32 rx_stat_gr64_lo;
1700 u32 rx_stat_gr64_hi;
1701 u32 rx_stat_gr127_lo;
1702 u32 rx_stat_gr127_hi;
1703 u32 rx_stat_gr255_lo;
1704 u32 rx_stat_gr255_hi;
1705 u32 rx_stat_gr511_lo;
1706 u32 rx_stat_gr511_hi;
1707 u32 rx_stat_gr1023_lo;
1708 u32 rx_stat_gr1023_hi;
1709 u32 rx_stat_gr1518_lo;
1710 u32 rx_stat_gr1518_hi;
1711 u32 rx_stat_gr2047_lo;
1712 u32 rx_stat_gr2047_hi;
1713 u32 rx_stat_gr4095_lo;
1714 u32 rx_stat_gr4095_hi;
1715 u32 rx_stat_gr9216_lo;
1716 u32 rx_stat_gr9216_hi;
1717 u32 rx_stat_gr16383_lo;
1718 u32 rx_stat_gr16383_hi;
1719 u32 rx_stat_grmax_lo;
1720 u32 rx_stat_grmax_hi;
1721 u32 rx_stat_grpkt_lo;
1722 u32 rx_stat_grpkt_hi;
1723 u32 rx_stat_grfcs_lo;
1724 u32 rx_stat_grfcs_hi;
1725 u32 rx_stat_gruca_lo;
1726 u32 rx_stat_gruca_hi;
1727 u32 rx_stat_grmca_lo;
1728 u32 rx_stat_grmca_hi;
1729 u32 rx_stat_grbca_lo;
1730 u32 rx_stat_grbca_hi;
1731 u32 rx_stat_grxpf_lo; /* grpf */
1732 u32 rx_stat_grxpf_hi; /* grpf */
1733 u32 rx_stat_grpp_lo;
1734 u32 rx_stat_grpp_hi;
1735 u32 rx_stat_grxuo_lo; /* gruo */
1736 u32 rx_stat_grxuo_hi; /* gruo */
1737 u32 rx_stat_grjbr_lo;
1738 u32 rx_stat_grjbr_hi;
1739 u32 rx_stat_grovr_lo;
1740 u32 rx_stat_grovr_hi;
1741 u32 rx_stat_grxcf_lo; /* grcf */
1742 u32 rx_stat_grxcf_hi; /* grcf */
1743 u32 rx_stat_grflr_lo;
1744 u32 rx_stat_grflr_hi;
1745 u32 rx_stat_grpok_lo;
1746 u32 rx_stat_grpok_hi;
1747 u32 rx_stat_grmeg_lo;
1748 u32 rx_stat_grmeg_hi;
1749 u32 rx_stat_grmeb_lo;
1750 u32 rx_stat_grmeb_hi;
1751 u32 rx_stat_grbyt_lo;
1752 u32 rx_stat_grbyt_hi;
1753 u32 rx_stat_grund_lo;
1754 u32 rx_stat_grund_hi;
1755 u32 rx_stat_grfrg_lo;
1756 u32 rx_stat_grfrg_hi;
1757 u32 rx_stat_grerb_lo; /* grerrbyt */
1758 u32 rx_stat_grerb_hi; /* grerrbyt */
1759 u32 rx_stat_grfre_lo; /* grfrerr */
1760 u32 rx_stat_grfre_hi; /* grfrerr */
1761 u32 rx_stat_gripj_lo;
1762 u32 rx_stat_gripj_hi;
1766 struct emac_stats emac_stats;
1767 struct bmac1_stats bmac1_stats;
1768 struct bmac2_stats bmac2_stats;
1774 u32 rx_stat_ifhcinbadoctets_hi;
1775 u32 rx_stat_ifhcinbadoctets_lo;
1777 /* out_bad_octets */
1778 u32 tx_stat_ifhcoutbadoctets_hi;
1779 u32 tx_stat_ifhcoutbadoctets_lo;
1781 /* crc_receive_errors */
1782 u32 rx_stat_dot3statsfcserrors_hi;
1783 u32 rx_stat_dot3statsfcserrors_lo;
1784 /* alignment_errors */
1785 u32 rx_stat_dot3statsalignmenterrors_hi;
1786 u32 rx_stat_dot3statsalignmenterrors_lo;
1787 /* carrier_sense_errors */
1788 u32 rx_stat_dot3statscarriersenseerrors_hi;
1789 u32 rx_stat_dot3statscarriersenseerrors_lo;
1790 /* false_carrier_detections */
1791 u32 rx_stat_falsecarriererrors_hi;
1792 u32 rx_stat_falsecarriererrors_lo;
1794 /* runt_packets_received */
1795 u32 rx_stat_etherstatsundersizepkts_hi;
1796 u32 rx_stat_etherstatsundersizepkts_lo;
1797 /* jabber_packets_received */
1798 u32 rx_stat_dot3statsframestoolong_hi;
1799 u32 rx_stat_dot3statsframestoolong_lo;
1801 /* error_runt_packets_received */
1802 u32 rx_stat_etherstatsfragments_hi;
1803 u32 rx_stat_etherstatsfragments_lo;
1804 /* error_jabber_packets_received */
1805 u32 rx_stat_etherstatsjabbers_hi;
1806 u32 rx_stat_etherstatsjabbers_lo;
1808 /* control_frames_received */
1809 u32 rx_stat_maccontrolframesreceived_hi;
1810 u32 rx_stat_maccontrolframesreceived_lo;
1811 u32 rx_stat_bmac_xpf_hi;
1812 u32 rx_stat_bmac_xpf_lo;
1813 u32 rx_stat_bmac_xcf_hi;
1814 u32 rx_stat_bmac_xcf_lo;
1816 /* xoff_state_entered */
1817 u32 rx_stat_xoffstateentered_hi;
1818 u32 rx_stat_xoffstateentered_lo;
1819 /* pause_xon_frames_received */
1820 u32 rx_stat_xonpauseframesreceived_hi;
1821 u32 rx_stat_xonpauseframesreceived_lo;
1822 /* pause_xoff_frames_received */
1823 u32 rx_stat_xoffpauseframesreceived_hi;
1824 u32 rx_stat_xoffpauseframesreceived_lo;
1825 /* pause_xon_frames_transmitted */
1826 u32 tx_stat_outxonsent_hi;
1827 u32 tx_stat_outxonsent_lo;
1828 /* pause_xoff_frames_transmitted */
1829 u32 tx_stat_outxoffsent_hi;
1830 u32 tx_stat_outxoffsent_lo;
1831 /* flow_control_done */
1832 u32 tx_stat_flowcontroldone_hi;
1833 u32 tx_stat_flowcontroldone_lo;
1835 /* ether_stats_collisions */
1836 u32 tx_stat_etherstatscollisions_hi;
1837 u32 tx_stat_etherstatscollisions_lo;
1838 /* single_collision_transmit_frames */
1839 u32 tx_stat_dot3statssinglecollisionframes_hi;
1840 u32 tx_stat_dot3statssinglecollisionframes_lo;
1841 /* multiple_collision_transmit_frames */
1842 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1843 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1844 /* deferred_transmissions */
1845 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1846 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1847 /* excessive_collision_frames */
1848 u32 tx_stat_dot3statsexcessivecollisions_hi;
1849 u32 tx_stat_dot3statsexcessivecollisions_lo;
1850 /* late_collision_frames */
1851 u32 tx_stat_dot3statslatecollisions_hi;
1852 u32 tx_stat_dot3statslatecollisions_lo;
1854 /* frames_transmitted_64_bytes */
1855 u32 tx_stat_etherstatspkts64octets_hi;
1856 u32 tx_stat_etherstatspkts64octets_lo;
1857 /* frames_transmitted_65_127_bytes */
1858 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1859 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1860 /* frames_transmitted_128_255_bytes */
1861 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1862 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1863 /* frames_transmitted_256_511_bytes */
1864 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1865 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1866 /* frames_transmitted_512_1023_bytes */
1867 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1868 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1869 /* frames_transmitted_1024_1522_bytes */
1870 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1871 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1872 /* frames_transmitted_1523_9022_bytes */
1873 u32 tx_stat_etherstatspktsover1522octets_hi;
1874 u32 tx_stat_etherstatspktsover1522octets_lo;
1875 u32 tx_stat_bmac_2047_hi;
1876 u32 tx_stat_bmac_2047_lo;
1877 u32 tx_stat_bmac_4095_hi;
1878 u32 tx_stat_bmac_4095_lo;
1879 u32 tx_stat_bmac_9216_hi;
1880 u32 tx_stat_bmac_9216_lo;
1881 u32 tx_stat_bmac_16383_hi;
1882 u32 tx_stat_bmac_16383_lo;
1884 /* internal_mac_transmit_errors */
1885 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1886 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1888 /* if_out_discards */
1889 u32 tx_stat_bmac_ufl_hi;
1890 u32 tx_stat_bmac_ufl_lo;
1894 #define MAC_STX_IDX_MAX 2
1896 struct host_port_stats {
1897 u32 host_port_stats_start;
1899 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1904 u32 host_port_stats_end;
1908 struct host_func_stats {
1909 u32 host_func_stats_start;
1911 u32 total_bytes_received_hi;
1912 u32 total_bytes_received_lo;
1914 u32 total_bytes_transmitted_hi;
1915 u32 total_bytes_transmitted_lo;
1917 u32 total_unicast_packets_received_hi;
1918 u32 total_unicast_packets_received_lo;
1920 u32 total_multicast_packets_received_hi;
1921 u32 total_multicast_packets_received_lo;
1923 u32 total_broadcast_packets_received_hi;
1924 u32 total_broadcast_packets_received_lo;
1926 u32 total_unicast_packets_transmitted_hi;
1927 u32 total_unicast_packets_transmitted_lo;
1929 u32 total_multicast_packets_transmitted_hi;
1930 u32 total_multicast_packets_transmitted_lo;
1932 u32 total_broadcast_packets_transmitted_hi;
1933 u32 total_broadcast_packets_transmitted_lo;
1935 u32 valid_bytes_received_hi;
1936 u32 valid_bytes_received_lo;
1938 u32 host_func_stats_end;
1942 #define BCM_5710_FW_MAJOR_VERSION 6
1943 #define BCM_5710_FW_MINOR_VERSION 2
1944 #define BCM_5710_FW_REVISION_VERSION 9
1945 #define BCM_5710_FW_ENGINEERING_VERSION 0
1946 #define BCM_5710_FW_COMPILE_FLAGS 1
1952 struct atten_sp_status_block {
1954 __le32 attn_bits_ack;
1957 __le16 attn_bits_index;
1963 * common data for all protocols
1965 struct doorbell_hdr {
1967 #define DOORBELL_HDR_RX (0x1<<0)
1968 #define DOORBELL_HDR_RX_SHIFT 0
1969 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1970 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1971 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1972 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1973 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1974 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1978 * doorbell message sent to the chip
1981 #if defined(__BIG_ENDIAN)
1984 struct doorbell_hdr header;
1985 #elif defined(__LITTLE_ENDIAN)
1986 struct doorbell_hdr header;
1994 * doorbell message sent to the chip
1996 struct doorbell_set_prod {
1997 #if defined(__BIG_ENDIAN)
2000 struct doorbell_hdr header;
2001 #elif defined(__LITTLE_ENDIAN)
2002 struct doorbell_hdr header;
2010 * 3 lines. status block
2012 struct hc_status_block_e1x {
2013 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2014 __le16 running_index[HC_SB_MAX_SM];
2021 struct host_hc_status_block_e1x {
2022 struct hc_status_block_e1x sb;
2027 * 3 lines. status block
2029 struct hc_status_block_e2 {
2030 __le16 index_values[HC_SB_MAX_INDICES_E2];
2031 __le16 running_index[HC_SB_MAX_SM];
2038 struct host_hc_status_block_e2 {
2039 struct hc_status_block_e2 sb;
2044 * 5 lines. slow-path status block
2046 struct hc_sp_status_block {
2047 __le16 index_values[HC_SP_SB_MAX_INDICES];
2048 __le16 running_index;
2056 struct host_sp_status_block {
2057 struct atten_sp_status_block atten_status_block;
2058 struct hc_sp_status_block sp_sb;
2063 * IGU driver acknowledgment register
2065 struct igu_ack_register {
2066 #if defined(__BIG_ENDIAN)
2067 u16 sb_id_and_flags;
2068 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2069 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2070 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2071 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2072 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2073 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2074 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2075 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2076 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2077 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2078 u16 status_block_index;
2079 #elif defined(__LITTLE_ENDIAN)
2080 u16 status_block_index;
2081 u16 sb_id_and_flags;
2082 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2083 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2084 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2085 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2086 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2087 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2088 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2089 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2090 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2091 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2097 * IGU driver acknowledgement register
2099 struct igu_backward_compatible {
2100 u32 sb_id_and_flags;
2101 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2102 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2103 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2104 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2105 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2106 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2107 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2108 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2109 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2110 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2111 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2112 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2118 * IGU driver acknowledgement register
2120 struct igu_regular {
2121 u32 sb_id_and_flags;
2122 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2123 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2124 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2125 #define IGU_REGULAR_RESERVED0_SHIFT 20
2126 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2127 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2128 #define IGU_REGULAR_BUPDATE (0x1<<24)
2129 #define IGU_REGULAR_BUPDATE_SHIFT 24
2130 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2131 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2132 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2133 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2134 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2135 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2136 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2137 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2138 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2139 #define IGU_REGULAR_BCLEANUP_SHIFT 31
2144 * IGU driver acknowledgement register
2146 union igu_consprod_reg {
2147 struct igu_regular regular;
2148 struct igu_backward_compatible backward_compatible;
2153 * Control register for the IGU command register
2155 struct igu_ctrl_reg {
2157 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2158 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
2159 #define IGU_CTRL_REG_FID (0x7F<<12)
2160 #define IGU_CTRL_REG_FID_SHIFT 12
2161 #define IGU_CTRL_REG_RESERVED (0x1<<19)
2162 #define IGU_CTRL_REG_RESERVED_SHIFT 19
2163 #define IGU_CTRL_REG_TYPE (0x1<<20)
2164 #define IGU_CTRL_REG_TYPE_SHIFT 20
2165 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2166 #define IGU_CTRL_REG_UNUSED_SHIFT 21
2171 * Parser parsing flags field
2173 struct parsing_flags {
2175 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2176 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2177 #define PARSING_FLAGS_VLAN (0x1<<1)
2178 #define PARSING_FLAGS_VLAN_SHIFT 1
2179 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2180 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2181 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2182 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2183 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2184 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2185 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2186 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2187 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2188 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2189 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2190 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2191 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2192 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2193 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2194 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2195 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2196 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2197 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2198 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2199 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
2200 #define PARSING_FLAGS_RESERVED0_SHIFT 14
2211 * dmae command structure
2213 struct dmae_command {
2215 #define DMAE_COMMAND_SRC (0x1<<0)
2216 #define DMAE_COMMAND_SRC_SHIFT 0
2217 #define DMAE_COMMAND_DST (0x3<<1)
2218 #define DMAE_COMMAND_DST_SHIFT 1
2219 #define DMAE_COMMAND_C_DST (0x1<<3)
2220 #define DMAE_COMMAND_C_DST_SHIFT 3
2221 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2222 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2223 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2224 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2225 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2226 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2227 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2228 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2229 #define DMAE_COMMAND_PORT (0x1<<11)
2230 #define DMAE_COMMAND_PORT_SHIFT 11
2231 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2232 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2233 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2234 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2235 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2236 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2237 #define DMAE_COMMAND_E1HVN (0x3<<15)
2238 #define DMAE_COMMAND_E1HVN_SHIFT 15
2239 #define DMAE_COMMAND_DST_VN (0x3<<17)
2240 #define DMAE_COMMAND_DST_VN_SHIFT 17
2241 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2242 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2243 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2244 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2245 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2246 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2251 #if defined(__BIG_ENDIAN)
2254 #elif defined(__LITTLE_ENDIAN)
2263 #if defined(__BIG_ENDIAN)
2266 #elif defined(__LITTLE_ENDIAN)
2270 #if defined(__BIG_ENDIAN)
2273 #elif defined(__LITTLE_ENDIAN)
2277 #if defined(__BIG_ENDIAN)
2280 #elif defined(__LITTLE_ENDIAN)
2287 struct double_regpair {
2296 * SDM operation gen command (generate aggregative interrupt)
2300 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
2301 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2302 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
2303 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
2304 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
2305 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
2306 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
2307 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
2308 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
2309 #define SDM_OP_GEN_RESERVED_SHIFT 17
2313 * The eth Rx Buffer Descriptor
2321 * The eth Rx SGE Descriptor
2331 * The eth storm context of Ustorm
2333 struct ustorm_eth_st_context {
2338 * The eth storm context of Tstorm
2340 struct tstorm_eth_st_context {
2341 u32 __reserved0[28];
2345 * The eth aggregative context of Xstorm
2347 struct xstorm_eth_ag_context {
2349 #if defined(__BIG_ENDIAN)
2353 #elif defined(__LITTLE_ENDIAN)
2362 * The eth aggregative context of Tstorm
2364 struct tstorm_eth_ag_context {
2365 u32 __reserved0[14];
2370 * The eth aggregative context of Cstorm
2372 struct cstorm_eth_ag_context {
2373 u32 __reserved0[10];
2378 * The eth aggregative context of Ustorm
2380 struct ustorm_eth_ag_context {
2382 #if defined(__BIG_ENDIAN)
2386 #elif defined(__LITTLE_ENDIAN)
2395 * Timers connection context
2397 struct timers_block_context {
2402 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2403 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2404 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2405 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2406 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2407 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2411 * structure for easy accessibility to assembler
2413 struct eth_tx_bd_flags {
2415 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2416 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2417 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2418 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2419 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2420 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2421 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2422 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2423 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2424 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2425 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2426 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2427 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2428 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2432 * The eth Tx Buffer Descriptor
2434 struct eth_tx_start_bd {
2439 __le16 vlan_or_ethertype;
2440 struct eth_tx_bd_flags bd_flags;
2442 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2443 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2444 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2445 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2449 * Tx regular BD structure
2454 __le16 total_pkt_bytes;
2460 * Tx parsing BD structure for ETH E1/E1h
2462 struct eth_tx_parse_bd_e1x {
2464 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2465 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2466 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2467 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2468 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2469 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2470 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2471 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2472 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2473 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2475 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2476 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2477 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2478 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2479 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2480 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2481 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2482 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2483 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2484 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2485 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2486 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2487 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2488 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2489 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2490 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2493 __le16 total_hlen_w;
2494 __le16 tcp_pseudo_csum;
2497 __le32 tcp_send_seq;
2501 * Tx parsing BD structure for ETH E2
2503 struct eth_tx_parse_bd_e2 {
2504 __le16 dst_mac_addr_lo;
2505 __le16 dst_mac_addr_mid;
2506 __le16 dst_mac_addr_hi;
2507 __le16 src_mac_addr_lo;
2508 __le16 src_mac_addr_mid;
2509 __le16 src_mac_addr_hi;
2510 __le32 parsing_data;
2511 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2512 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2513 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2514 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2515 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2516 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2517 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2518 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2522 * The last BD in the BD memory will hold a pointer to the next BD memory
2524 struct eth_tx_next_bd {
2531 * union for 4 Bd types
2533 union eth_tx_bd_types {
2534 struct eth_tx_start_bd start_bd;
2535 struct eth_tx_bd reg_bd;
2536 struct eth_tx_parse_bd_e1x parse_bd_e1x;
2537 struct eth_tx_parse_bd_e2 parse_bd_e2;
2538 struct eth_tx_next_bd next_bd;
2543 * The eth storm context of Xstorm
2545 struct xstorm_eth_st_context {
2550 * The eth storm context of Cstorm
2552 struct cstorm_eth_st_context {
2557 * Ethernet connection context
2559 struct eth_context {
2560 struct ustorm_eth_st_context ustorm_st_context;
2561 struct tstorm_eth_st_context tstorm_st_context;
2562 struct xstorm_eth_ag_context xstorm_ag_context;
2563 struct tstorm_eth_ag_context tstorm_ag_context;
2564 struct cstorm_eth_ag_context cstorm_ag_context;
2565 struct ustorm_eth_ag_context ustorm_ag_context;
2566 struct timers_block_context timers_context;
2567 struct xstorm_eth_st_context xstorm_st_context;
2568 struct cstorm_eth_st_context cstorm_st_context;
2575 struct eth_tx_doorbell {
2576 #if defined(__BIG_ENDIAN)
2579 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2580 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2581 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2582 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2583 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2584 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2585 struct doorbell_hdr hdr;
2586 #elif defined(__LITTLE_ENDIAN)
2587 struct doorbell_hdr hdr;
2589 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2590 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2591 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2592 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2593 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2594 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2601 * client init fc data
2603 struct client_init_fc_data {
2604 __le16 cqe_pause_thr_low;
2605 __le16 cqe_pause_thr_high;
2606 __le16 bd_pause_thr_low;
2607 __le16 bd_pause_thr_high;
2608 __le16 sge_pause_thr_low;
2609 __le16 sge_pause_thr_high;
2612 u8 safc_group_en_flg;
2621 * client init ramrod data
2623 struct client_init_general_data {
2625 u8 statistics_counter_id;
2626 u8 statistics_en_flg;
2631 __le32 reserved1[2];
2636 * client init rx data
2638 struct client_init_rx_data {
2640 u8 vmqueue_mode_en_flg;
2641 u8 extra_data_over_sgl_en_flg;
2642 u8 cache_line_alignment_log_size;
2643 u8 enable_dynamic_hc;
2644 u8 max_sges_for_packet;
2646 u8 drop_ip_cs_err_flg;
2647 u8 drop_tcp_cs_err_flg;
2649 u8 drop_udp_cs_err_flg;
2650 u8 inner_vlan_removal_enable_flg;
2651 u8 outer_vlan_removal_enable_flg;
2653 u8 rx_sb_index_number;
2655 __le16 bd_buff_size;
2656 __le16 sge_buff_size;
2658 struct regpair bd_page_base;
2659 struct regpair sge_page_base;
2660 struct regpair cqe_page_base;
2663 __le16 max_agg_size;
2664 __le32 reserved2[3];
2668 * client init tx data
2670 struct client_init_tx_data {
2671 u8 enforce_security_flg;
2672 u8 tx_status_block_id;
2673 u8 tx_sb_index_number;
2677 struct regpair tx_bd_page_base;
2678 __le32 reserved2[2];
2682 * client init ramrod data
2684 struct client_init_ramrod_data {
2685 struct client_init_general_data general;
2686 struct client_init_rx_data rx;
2687 struct client_init_tx_data tx;
2688 struct client_init_fc_data fc;
2693 * The data contain client ID need to the ramrod
2695 struct eth_common_ramrod_data {
2702 * union for sgl and raw data.
2704 union eth_sgl_or_raw_data {
2710 * regular eth FP CQE parameters struct
2712 struct eth_fast_path_rx_cqe {
2713 u8 type_error_flags;
2714 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2715 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2716 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2717 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2718 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2719 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2720 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2721 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2722 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2723 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2724 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2725 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2726 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2727 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2729 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2730 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2731 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2732 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2733 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2734 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2735 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2736 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2737 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2738 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2739 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2740 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2741 u8 placement_offset;
2743 __le32 rss_hash_result;
2747 struct parsing_flags pars_flags;
2748 union eth_sgl_or_raw_data sgl_or_raw_data;
2753 * The data for RSS setup ramrod
2755 struct eth_halt_ramrod_data {
2761 * The data for statistics query ramrod
2763 struct common_query_ramrod_data {
2764 #if defined(__BIG_ENDIAN)
2768 #elif defined(__LITTLE_ENDIAN)
2778 * Place holder for ramrods protocol specific data
2780 struct ramrod_data {
2786 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2788 union eth_ramrod_data {
2789 struct ramrod_data general;
2794 * Eth Rx Cqe structure- general structure for ramrods
2796 struct common_ramrod_eth_rx_cqe {
2798 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2799 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2800 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2801 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2802 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2803 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2806 __le32 conn_and_cmd_data;
2807 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2808 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2809 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2810 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2811 struct ramrod_data protocol_data;
2812 __le32 reserved2[4];
2816 * Rx Last CQE in page (in ETH)
2818 struct eth_rx_cqe_next_page {
2825 * union for all eth rx cqe types (fix their sizes)
2828 struct eth_fast_path_rx_cqe fast_path_cqe;
2829 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2830 struct eth_rx_cqe_next_page next_page_cqe;
2835 * common data for all protocols
2838 __le32 conn_and_cmd_data;
2839 #define SPE_HDR_CID (0xFFFFFF<<0)
2840 #define SPE_HDR_CID_SHIFT 0
2841 #define SPE_HDR_CMD_ID (0xFF<<24)
2842 #define SPE_HDR_CMD_ID_SHIFT 24
2844 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2845 #define SPE_HDR_CONN_TYPE_SHIFT 0
2846 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
2847 #define SPE_HDR_FUNCTION_ID_SHIFT 8
2852 * Ethernet slow path element
2854 union eth_specific_data {
2855 u8 protocol_data[8];
2856 struct regpair client_init_ramrod_init_data;
2857 struct eth_halt_ramrod_data halt_ramrod_data;
2858 struct regpair update_data_addr;
2859 struct eth_common_ramrod_data common_ramrod_data;
2863 * Ethernet slow path element
2867 union eth_specific_data data;
2872 * array of 13 bds as appears in the eth xstorm context
2874 struct eth_tx_bds_array {
2875 union eth_tx_bd_types bds[13];
2880 * Common configuration parameters per function in Tstorm
2882 struct tstorm_eth_function_common_config {
2883 #if defined(__BIG_ENDIAN)
2887 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2888 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2889 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2890 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2891 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2892 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2893 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2894 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2895 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2896 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2897 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2898 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2899 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2900 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2901 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2902 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2903 #elif defined(__LITTLE_ENDIAN)
2905 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2906 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2907 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2908 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2909 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2910 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2911 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2912 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2913 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2914 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2915 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2916 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2917 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2918 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2919 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2920 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2928 * RSS idirection table update configuration
2930 struct rss_update_config {
2931 #if defined(__BIG_ENDIAN)
2934 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2935 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2936 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2937 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2938 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2939 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2940 #elif defined(__LITTLE_ENDIAN)
2942 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2943 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2944 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2945 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2946 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2947 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2954 * parameters for eth update ramrod
2956 struct eth_update_ramrod_data {
2957 struct tstorm_eth_function_common_config func_config;
2958 u8 indirectionTable[128];
2959 struct rss_update_config rss_config;
2964 * MAC filtering configuration command header
2966 struct mac_configuration_hdr {
2975 * MAC address in list for ramrod
2977 struct mac_configuration_entry {
2978 __le16 lsb_mac_addr;
2979 __le16 middle_mac_addr;
2980 __le16 msb_mac_addr;
2984 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2985 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2986 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2987 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2988 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2989 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2990 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2991 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2992 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2993 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2994 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2995 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
2997 u32 clients_bit_vector;
3001 * MAC filtering configuration command
3003 struct mac_configuration_cmd {
3004 struct mac_configuration_hdr hdr;
3005 struct mac_configuration_entry config_table[64];
3010 * approximate-match multicast filtering for E1H per function in Tstorm
3012 struct tstorm_eth_approximate_match_multicast_filtering {
3013 u32 mcast_add_hash_bit_array[8];
3018 * MAC filtering configuration parameters per port in Tstorm
3020 struct tstorm_eth_mac_filter_config {
3022 u32 ucast_accept_all;
3024 u32 mcast_accept_all;
3026 u32 bcast_accept_all;
3028 u32 unmatched_unicast;
3034 * common flag to indicate existence of TPA.
3036 struct tstorm_eth_tpa_exist {
3037 #if defined(__BIG_ENDIAN)
3041 #elif defined(__LITTLE_ENDIAN)
3051 * Three RX producers for ETH
3053 struct ustorm_eth_rx_producers {
3054 #if defined(__BIG_ENDIAN)
3057 #elif defined(__LITTLE_ENDIAN)
3061 #if defined(__BIG_ENDIAN)
3064 #elif defined(__LITTLE_ENDIAN)
3072 * cfc delete event data
3074 struct cfc_del_event_data {
3084 * per-port SAFC demo variables
3086 struct cmng_flags_per_port {
3087 u8 con_number[NUM_OF_PROTOCOLS];
3089 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
3090 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
3091 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
3092 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
3093 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
3094 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
3095 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
3096 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
3097 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
3098 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
3099 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
3100 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
3101 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
3102 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
3107 * per-port rate shaping variables
3109 struct rate_shaping_vars_per_port {
3110 u32 rs_periodic_timeout;
3115 * per-port fairness variables
3117 struct fairness_vars_per_port {
3120 u32 fairness_timeout;
3124 * per-port SAFC variables
3126 struct safc_struct_per_port {
3127 #if defined(__BIG_ENDIAN)
3130 u8 safc_timeout_usec;
3131 #elif defined(__LITTLE_ENDIAN)
3132 u8 safc_timeout_usec;
3136 u8 cos_to_traffic_types[MAX_COS_NUMBER];
3138 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
3142 * per-port PFC variables
3144 struct pfc_struct_per_port {
3145 u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
3146 #if defined(__BIG_ENDIAN)
3147 u16 pfc_pause_quanta_in_nanosec;
3149 u8 priority_non_pausable_mask;
3150 #elif defined(__LITTLE_ENDIAN)
3151 u8 priority_non_pausable_mask;
3153 u16 pfc_pause_quanta_in_nanosec;
3160 struct priority_cos {
3161 #if defined(__BIG_ENDIAN)
3165 #elif defined(__LITTLE_ENDIAN)
3174 * Per-port congestion management variables
3176 struct cmng_struct_per_port {
3177 struct rate_shaping_vars_per_port rs_vars;
3178 struct fairness_vars_per_port fair_vars;
3179 struct safc_struct_per_port safc_vars;
3180 struct pfc_struct_per_port pfc_vars;
3181 #if defined(__BIG_ENDIAN)
3185 #elif defined(__LITTLE_ENDIAN)
3191 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3192 struct cmng_flags_per_port flags;
3198 * Dynamic HC counters set by the driver
3200 struct hc_dynamic_drv_counter {
3201 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
3205 * zone A per-queue data
3207 struct cstorm_queue_zone_data {
3208 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
3209 struct regpair reserved[2];
3213 * Dynamic host coalescing init parameters
3215 struct dynamic_hc_config {
3217 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
3218 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
3219 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
3220 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
3221 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
3226 * Protocol-common statistics collected by the Xstorm (per client)
3228 struct xstorm_per_client_stats {
3230 __le32 unicast_pkts_sent;
3231 struct regpair unicast_bytes_sent;
3232 struct regpair multicast_bytes_sent;
3233 __le32 multicast_pkts_sent;
3234 __le32 broadcast_pkts_sent;
3235 struct regpair broadcast_bytes_sent;
3236 __le16 stats_counter;
3242 * Common statistics collected by the Xstorm (per port)
3244 struct xstorm_common_stats {
3245 struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3249 * Protocol-common statistics collected by the Tstorm (per port)
3251 struct tstorm_per_port_stats {
3252 __le32 mac_filter_discard;
3253 __le32 xxoverflow_discard;
3254 __le32 brb_truncate_discard;
3259 * Protocol-common statistics collected by the Tstorm (per client)
3261 struct tstorm_per_client_stats {
3262 struct regpair rcv_unicast_bytes;
3263 struct regpair rcv_broadcast_bytes;
3264 struct regpair rcv_multicast_bytes;
3265 struct regpair rcv_error_bytes;
3266 __le32 checksum_discard;
3267 __le32 packets_too_big_discard;
3268 __le32 rcv_unicast_pkts;
3269 __le32 rcv_broadcast_pkts;
3270 __le32 rcv_multicast_pkts;
3271 __le32 no_buff_discard;
3272 __le32 ttl0_discard;
3273 __le16 stats_counter;
3278 * Protocol-common statistics collected by the Tstorm
3280 struct tstorm_common_stats {
3281 struct tstorm_per_port_stats port_statistics;
3282 struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3286 * Protocol-common statistics collected by the Ustorm (per client)
3288 struct ustorm_per_client_stats {
3289 struct regpair ucast_no_buff_bytes;
3290 struct regpair mcast_no_buff_bytes;
3291 struct regpair bcast_no_buff_bytes;
3292 __le32 ucast_no_buff_pkts;
3293 __le32 mcast_no_buff_pkts;
3294 __le32 bcast_no_buff_pkts;
3295 __le16 stats_counter;
3300 * Protocol-common statistics collected by the Ustorm
3302 struct ustorm_common_stats {
3303 struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3307 * Eth statistics query structure for the eth_stats_query ramrod
3309 struct eth_stats_query {
3310 struct xstorm_common_stats xstorm_common;
3311 struct tstorm_common_stats tstorm_common;
3312 struct ustorm_common_stats ustorm_common;
3317 * set mac event data
3319 struct set_mac_event_data {
3327 * union for all event ring message types
3330 struct set_mac_event_data set_mac_event;
3331 struct cfc_del_event_data cfc_del_event;
3336 * per PF event ring data
3338 struct event_ring_data {
3339 struct regpair base_addr;
3340 #if defined(__BIG_ENDIAN)
3344 #elif defined(__LITTLE_ENDIAN)
3354 * event ring message element (each element is 128 bits)
3356 struct event_ring_msg {
3360 union event_data data;
3364 * event ring next page element (128 bits)
3366 struct event_ring_next {
3367 struct regpair addr;
3372 * union for event ring element types (each element is 128 bits)
3374 union event_ring_elem {
3375 struct event_ring_msg message;
3376 struct event_ring_next next_page;
3381 * per-vnic fairness variables
3383 struct fairness_vars_per_vn {
3384 u32 cos_credit_delta[MAX_COS_NUMBER];
3385 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
3386 u32 vn_credit_delta;
3392 * The data for flow control configuration
3394 struct flow_control_configuration {
3396 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3397 #if defined(__BIG_ENDIAN)
3401 #elif defined(__LITTLE_ENDIAN)
3411 * FW version stored in the Xstorm RAM
3414 #if defined(__BIG_ENDIAN)
3419 #elif defined(__LITTLE_ENDIAN)
3426 #define FW_VERSION_OPTIMIZED (0x1<<0)
3427 #define FW_VERSION_OPTIMIZED_SHIFT 0
3428 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3429 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3430 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3431 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3432 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3433 #define __FW_VERSION_RESERVED_SHIFT 4
3438 * Dynamic Host-Coalescing - Driver(host) counters
3440 struct hc_dynamic_sb_drv_counters {
3441 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3446 * 2 bytes. configuration/state parameters for a single protocol index
3448 struct hc_index_data {
3449 #if defined(__BIG_ENDIAN)
3451 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3452 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3453 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3454 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3455 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3456 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3457 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3458 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3460 #elif defined(__LITTLE_ENDIAN)
3463 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3464 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3465 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3466 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3467 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3468 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3469 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3470 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3478 struct hc_status_block_sm {
3479 #if defined(__BIG_ENDIAN)
3484 #elif defined(__LITTLE_ENDIAN)
3494 * hold PCI identification variables- used in various places in firmware
3497 #if defined(__BIG_ENDIAN)
3502 #elif defined(__LITTLE_ENDIAN)
3511 * The fast-path status block meta-data, common to all chips
3514 struct regpair host_sb_addr;
3515 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3516 struct pci_entity p_func;
3517 #if defined(__BIG_ENDIAN)
3520 u8 __dynamic_hc_level;
3522 #elif defined(__LITTLE_ENDIAN)
3524 u8 __dynamic_hc_level;
3528 struct regpair rsrv1[2];
3533 * The fast-path status block meta-data
3535 struct hc_sp_status_block_data {
3536 struct regpair host_sb_addr;
3537 #if defined(__BIG_ENDIAN)
3541 #elif defined(__LITTLE_ENDIAN)
3546 struct pci_entity p_func;
3551 * The fast-path status block meta-data
3553 struct hc_status_block_data_e1x {
3554 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3555 struct hc_sb_data common;
3560 * The fast-path status block meta-data
3562 struct hc_status_block_data_e2 {
3563 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3564 struct hc_sb_data common;
3569 * FW version stored in first line of pram
3571 struct pram_fw_version {
3577 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3578 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3579 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3580 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3581 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3582 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3583 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3584 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3585 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3586 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3591 * Ethernet slow path element
3593 union protocol_common_specific_data {
3594 u8 protocol_data[8];
3595 struct regpair phy_address;
3596 struct regpair mac_config_addr;
3597 struct common_query_ramrod_data query_ramrod_data;
3601 * The send queue element
3603 struct protocol_common_spe {
3605 union protocol_common_specific_data data;
3610 * a single rate shaping counter. can be used as protocol or vnic counter
3612 struct rate_shaping_counter {
3614 #if defined(__BIG_ENDIAN)
3617 #elif defined(__LITTLE_ENDIAN)
3625 * per-vnic rate shaping variables
3627 struct rate_shaping_vars_per_vn {
3628 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3629 struct rate_shaping_counter vn_counter;
3634 * The send queue element
3636 struct slow_path_element {
3638 struct regpair protocol_data;
3643 * eth/toe flags that indicate if to query
3645 struct stats_indication_flags {
3652 * per-port PFC variables
3654 struct storm_pfc_struct_per_port {
3655 #if defined(__BIG_ENDIAN)
3658 #elif defined(__LITTLE_ENDIAN)
3662 #if defined(__BIG_ENDIAN)
3663 u16 pfc_pause_quanta_in_nanosec;
3665 #elif defined(__LITTLE_ENDIAN)
3667 u16 pfc_pause_quanta_in_nanosec;
3672 * Per-port congestion management variables
3674 struct storm_cmng_struct_per_port {
3675 struct storm_pfc_struct_per_port pfc_vars;
3680 * zone A per-queue data
3682 struct tstorm_queue_zone_data {
3683 struct regpair reserved[4];
3688 * zone B per-VF data
3690 struct tstorm_vf_zone_data {
3691 struct regpair reserved;
3696 * zone A per-queue data
3698 struct ustorm_queue_zone_data {
3699 struct ustorm_eth_rx_producers eth_rx_producers;
3700 struct regpair reserved[3];
3705 * zone B per-VF data
3707 struct ustorm_vf_zone_data {
3708 struct regpair reserved;
3713 * data per VF-PF channel
3715 struct vf_pf_channel_data {
3716 #if defined(__BIG_ENDIAN)
3720 #elif defined(__LITTLE_ENDIAN)
3730 * zone A per-queue data
3732 struct xstorm_queue_zone_data {
3733 struct regpair reserved[4];
3738 * zone B per-VF data
3740 struct xstorm_vf_zone_data {
3741 struct regpair reserved;
3744 #endif /* BNX2X_HSI_H */