drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28
  29 /********************************************************/
  30 #define ETH_HLEN                        14
  31 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  32 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  33 #define ETH_MIN_PACKET_SIZE             60
  34 #define ETH_MAX_PACKET_SIZE             1500
  35 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  36 #define MDIO_ACCESS_TIMEOUT             1000
  37 #define BMAC_CONTROL_RX_ENABLE          2
  38
  39 /***********************************************************/
  40 /*                      Shortcut definitions               */
  41 /***********************************************************/
  42
  43 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  44
  45 #define NIG_STATUS_EMAC0_MI_INT \
  46                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  47 #define NIG_STATUS_XGXS0_LINK10G \
  48                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  49 #define NIG_STATUS_XGXS0_LINK_STATUS \
  50                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  51 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  52                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  53 #define NIG_STATUS_SERDES0_LINK_STATUS \
  54                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  55 #define NIG_MASK_MI_INT \
  56                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  57 #define NIG_MASK_XGXS0_LINK10G \
  58                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  59 #define NIG_MASK_XGXS0_LINK_STATUS \
  60                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  61 #define NIG_MASK_SERDES0_LINK_STATUS \
  62                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  63
  64 #define MDIO_AN_CL73_OR_37_COMPLETE \
  65                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  66                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  67
  68 #define XGXS_RESET_BITS \
  69         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  73          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  74
  75 #define SERDES_RESET_BITS \
  76         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  80
  81 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  82 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  83 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  84 #define AUTONEG_PARALLEL \
  85                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  86 #define AUTONEG_SGMII_FIBER_AUTODET \
  87                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  88 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  89
  90 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  91                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  92 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  93                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  94 #define GP_STATUS_SPEED_MASK \
  95                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  96 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  97 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
  98 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
  99 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 100 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 101 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 102 #define GP_STATUS_10G_HIG \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 104 #define GP_STATUS_10G_CX4 \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 106 #define GP_STATUS_12G_HIG \
 107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 108 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 109 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 110 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 111 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 112 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 113 #define GP_STATUS_10G_KX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 115
 116 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 117 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 118 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 119 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 120 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 121 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 122 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 123 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 124 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 125 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 126 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 127 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 128 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 129 #define LINK_12GTFD             LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
 130 #define LINK_12GXFD             LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
 131 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
 132 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
 133 #define LINK_13GTFD             LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
 134 #define LINK_13GXFD             LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
 135 #define LINK_15GTFD             LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
 136 #define LINK_15GXFD             LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
 137 #define LINK_16GTFD             LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 138 #define LINK_16GXFD             LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 139
 140 #define PHY_XGXS_FLAG                   0x1
 141 #define PHY_SGMII_FLAG                  0x2
 142 #define PHY_SERDES_FLAG                 0x4
 143
 144 /* */
 145 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 146         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 147         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 148
 149
 150 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 151         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 152         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 153         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 154
 155 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 157         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 158
 159 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 160         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 161 #define SFP_EEPROM_OPTIONS_SIZE                 2
 162
 163 #define EDC_MODE_LINEAR                         0x0022
 164 #define EDC_MODE_LIMITING                               0x0044
 165 #define EDC_MODE_PASSIVE_DAC                    0x0055
 166
 167
 168 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 169 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 170 /**********************************************************/
 171 /*                     INTERFACE                          */
 172 /**********************************************************/
 173
 174 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 175         bnx2x_cl45_write(_bp, _phy, \
 176                 (_phy)->def_md_devad, \
 177                 (_bank + (_addr & 0xf)), \
 178                 _val)
 179
 180 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 181         bnx2x_cl45_read(_bp, _phy, \
 182                 (_phy)->def_md_devad, \
 183                 (_bank + (_addr & 0xf)), \
 184                 _val)
 185
 186 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 187 {
 188         u32 val = REG_RD(bp, reg);
 189
 190         val |= bits;
 191         REG_WR(bp, reg, val);
 192         return val;
 193 }
 194
 195 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 196 {
 197         u32 val = REG_RD(bp, reg);
 198
 199         val &= ~bits;
 200         REG_WR(bp, reg, val);
 201         return val;
 202 }
 203
 204 /******************************************************************/
 205 /*                              ETS section                       */
 206 /******************************************************************/
 207 void bnx2x_ets_disabled(struct link_params *params)
 208 {
 209         /* ETS disabled configuration*/
 210         struct bnx2x *bp = params->bp;
 211
 212         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 213
 214         /*
 215          * mapping between entry  priority to client number (0,1,2 -debug and
 216          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 217          * 3bits client num.
 218          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 219          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 220          */
 221
 222         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 223         /*
 224          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 225          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 226          * COS0 entry, 4 - COS1 entry.
 227          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 228          * bit4   bit3    bit2   bit1     bit0
 229          * MCP and debug are strict
 230          */
 231
 232         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 233         /* defines which entries (clients) are subjected to WFQ arbitration */
 234         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 235         /*
 236          * For strict priority entries defines the number of consecutive
 237          * slots for the highest priority.
 238          */
 239         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 240         /*
 241          * mapping between the CREDIT_WEIGHT registers and actual client
 242          * numbers
 243          */
 244         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 245         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 246         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 247
 248         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 249         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 250         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 251         /* ETS mode disable */
 252         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 253         /*
 254          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 255          * weight for COS0/COS1.
 256          */
 257         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 258         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 262         /* Defines the number of consecutive slots for the strict priority */
 263         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 264 }
 265
 266 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
 267 {
 268         /* ETS disabled configuration */
 269         struct bnx2x *bp = params->bp;
 270         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 271         /*
 272          * defines which entries (clients) are subjected to WFQ arbitration
 273          * COS0 0x8
 274          * COS1 0x10
 275          */
 276         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 277         /*
 278          * mapping between the ARB_CREDIT_WEIGHT registers and actual
 279          * client numbers (WEIGHT_0 does not actually have to represent
 280          * client 0)
 281          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 282          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 283          */
 284         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 285
 286         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 287                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 288         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 289                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 290
 291         /* ETS mode enabled*/
 292         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 293
 294         /* Defines the number of consecutive slots for the strict priority */
 295         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 296         /*
 297          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 298          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 299          * entry, 4 - COS1 entry.
 300          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 301          * bit4   bit3    bit2     bit1    bit0
 302          * MCP and debug are strict
 303          */
 304         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 305
 306         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 307         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 308                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 309         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 310                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 311 }
 312
 313 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 314                         const u32 cos1_bw)
 315 {
 316         /* ETS disabled configuration*/
 317         struct bnx2x *bp = params->bp;
 318         const u32 total_bw = cos0_bw + cos1_bw;
 319         u32 cos0_credit_weight = 0;
 320         u32 cos1_credit_weight = 0;
 321
 322         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 323
 324         if ((0 == total_bw) ||
 325             (0 == cos0_bw) ||
 326             (0 == cos1_bw)) {
 327                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
 328                 return;
 329         }
 330
 331         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 332                 total_bw;
 333         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 334                 total_bw;
 335
 336         bnx2x_ets_bw_limit_common(params);
 337
 338         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 339         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 340
 341         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 342         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 343 }
 344
 345 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 346 {
 347         /* ETS disabled configuration*/
 348         struct bnx2x *bp = params->bp;
 349         u32 val = 0;
 350
 351         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 352         /*
 353          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 354          * as strict.  Bits 0,1,2 - debug and management entries,
 355          * 3 - COS0 entry, 4 - COS1 entry.
 356          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 357          *  bit4   bit3   bit2      bit1     bit0
 358          * MCP and debug are strict
 359          */
 360         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 361         /*
 362          * For strict priority entries defines the number of consecutive slots
 363          * for the highest priority.
 364          */
 365         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 366         /* ETS mode disable */
 367         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 368         /* Defines the number of consecutive slots for the strict priority */
 369         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 370
 371         /* Defines the number of consecutive slots for the strict priority */
 372         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 373
 374         /*
 375          * mapping between entry  priority to client number (0,1,2 -debug and
 376          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 377          * 3bits client num.
 378          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 379          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 380          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 381          */
 382         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 383         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 384
 385         return 0;
 386 }
 387 /******************************************************************/
 388 /*                      PFC section                               */
 389 /******************************************************************/
 390
 391 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 392                                      u32 pfc_frames_sent[2],
 393                                      u32 pfc_frames_received[2])
 394 {
 395         /* Read pfc statistic */
 396         struct bnx2x *bp = params->bp;
 397         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 398                 NIG_REG_INGRESS_BMAC0_MEM;
 399
 400         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 401
 402         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 403                                         pfc_frames_sent, 2);
 404
 405         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 406                                         pfc_frames_received, 2);
 407
 408 }
 409 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 410                                     u32 pfc_frames_sent[2],
 411                                     u32 pfc_frames_received[2])
 412 {
 413         /* Read pfc statistic */
 414         struct bnx2x *bp = params->bp;
 415         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 416         u32 val_xon = 0;
 417         u32 val_xoff = 0;
 418
 419         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 420
 421         /* PFC received frames */
 422         val_xoff = REG_RD(bp, emac_base +
 423                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 424         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 425         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 426         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 427
 428         pfc_frames_received[0] = val_xon + val_xoff;
 429
 430         /* PFC received sent */
 431         val_xoff = REG_RD(bp, emac_base +
 432                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 433         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 434         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 435         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 436
 437         pfc_frames_sent[0] = val_xon + val_xoff;
 438 }
 439
 440 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 441                          u32 pfc_frames_sent[2],
 442                          u32 pfc_frames_received[2])
 443 {
 444         /* Read pfc statistic */
 445         struct bnx2x *bp = params->bp;
 446         u32 val = 0;
 447         DP(NETIF_MSG_LINK, "pfc statistic\n");
 448
 449         if (!vars->link_up)
 450                 return;
 451
 452         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 453         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 454             == 0) {
 455                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 456                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 457                                         pfc_frames_received);
 458         } else {
 459                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 460                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 461                                          pfc_frames_received);
 462         }
 463 }
 464 /******************************************************************/
 465 /*                      MAC/PBF section                           */
 466 /******************************************************************/
 467 static void bnx2x_emac_init(struct link_params *params,
 468                             struct link_vars *vars)
 469 {
 470         /* reset and unreset the emac core */
 471         struct bnx2x *bp = params->bp;
 472         u8 port = params->port;
 473         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 474         u32 val;
 475         u16 timeout;
 476
 477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 478                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 479         udelay(5);
 480         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 481                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 482
 483         /* init emac - use read-modify-write */
 484         /* self clear reset */
 485         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 486         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 487
 488         timeout = 200;
 489         do {
 490                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 491                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 492                 if (!timeout) {
 493                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 494                         return;
 495                 }
 496                 timeout--;
 497         } while (val & EMAC_MODE_RESET);
 498
 499         /* Set mac address */
 500         val = ((params->mac_addr[0] << 8) |
 501                 params->mac_addr[1]);
 502         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 503
 504         val = ((params->mac_addr[2] << 24) |
 505                (params->mac_addr[3] << 16) |
 506                (params->mac_addr[4] << 8) |
 507                 params->mac_addr[5]);
 508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 509 }
 510
 511 static int bnx2x_emac_enable(struct link_params *params,
 512                              struct link_vars *vars, u8 lb)
 513 {
 514         struct bnx2x *bp = params->bp;
 515         u8 port = params->port;
 516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 517         u32 val;
 518
 519         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 520
 521         /* enable emac and not bmac */
 522         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 523
 524         /* ASIC */
 525         if (vars->phy_flags & PHY_XGXS_FLAG) {
 526                 u32 ser_lane = ((params->lane_config &
 527                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 528                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 529
 530                 DP(NETIF_MSG_LINK, "XGXS\n");
 531                 /* select the master lanes (out of 0-3) */
 532                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
 533                 /* select XGXS */
 534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
 535
 536         } else { /* SerDes */
 537                 DP(NETIF_MSG_LINK, "SerDes\n");
 538                 /* select SerDes */
 539                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
 540         }
 541
 542         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 543                       EMAC_RX_MODE_RESET);
 544         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 545                       EMAC_TX_MODE_RESET);
 546
 547         if (CHIP_REV_IS_SLOW(bp)) {
 548                 /* config GMII mode */
 549                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 550                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
 551         } else { /* ASIC */
 552                 /* pause enable/disable */
 553                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 554                                EMAC_RX_MODE_FLOW_EN);
 555
 556                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 557                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 558                                 EMAC_TX_MODE_FLOW_EN));
 559                 if (!(params->feature_config_flags &
 560                       FEATURE_CONFIG_PFC_ENABLED)) {
 561                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 562                                 bnx2x_bits_en(bp, emac_base +
 563                                               EMAC_REG_EMAC_RX_MODE,
 564                                               EMAC_RX_MODE_FLOW_EN);
 565
 566                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 567                                 bnx2x_bits_en(bp, emac_base +
 568                                               EMAC_REG_EMAC_TX_MODE,
 569                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 570                                                EMAC_TX_MODE_FLOW_EN));
 571                 } else
 572                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 573                                       EMAC_TX_MODE_FLOW_EN);
 574         }
 575
 576         /* KEEP_VLAN_TAG, promiscuous */
 577         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 578         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 579
 580         /*
 581          * Setting this bit causes MAC control frames (except for pause
 582          * frames) to be passed on for processing. This setting has no
 583          * affect on the operation of the pause frames. This bit effects
 584          * all packets regardless of RX Parser packet sorting logic.
 585          * Turn the PFC off to make sure we are in Xon state before
 586          * enabling it.
 587          */
 588         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 589         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 590                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 591                 /* Enable PFC again */
 592                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 593                         EMAC_REG_RX_PFC_MODE_RX_EN |
 594                         EMAC_REG_RX_PFC_MODE_TX_EN |
 595                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 596
 597                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 598                         ((0x0101 <<
 599                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 600                          (0x00ff <<
 601                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 602                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 603         }
 604         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 605
 606         /* Set Loopback */
 607         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 608         if (lb)
 609                 val |= 0x810;
 610         else
 611                 val &= ~0x810;
 612         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 613
 614         /* enable emac */
 615         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 616
 617         /* enable emac for jumbo packets */
 618         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 619                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 620                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 621
 622         /* strip CRC */
 623         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
 624
 625         /* disable the NIG in/out to the bmac */
 626         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
 627         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
 628         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
 629
 630         /* enable the NIG in/out to the emac */
 631         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
 632         val = 0;
 633         if ((params->feature_config_flags &
 634               FEATURE_CONFIG_PFC_ENABLED) ||
 635             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 636                 val = 1;
 637
 638         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
 639         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
 640
 641         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
 642
 643         vars->mac_type = MAC_TYPE_EMAC;
 644         return 0;
 645 }
 646
 647 static void bnx2x_update_pfc_bmac1(struct link_params *params,
 648                                    struct link_vars *vars)
 649 {
 650         u32 wb_data[2];
 651         struct bnx2x *bp = params->bp;
 652         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 653                 NIG_REG_INGRESS_BMAC0_MEM;
 654
 655         u32 val = 0x14;
 656         if ((!(params->feature_config_flags &
 657               FEATURE_CONFIG_PFC_ENABLED)) &&
 658                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 659                 /* Enable BigMAC to react on received Pause packets */
 660                 val |= (1<<5);
 661         wb_data[0] = val;
 662         wb_data[1] = 0;
 663         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
 664
 665         /* tx control */
 666         val = 0xc0;
 667         if (!(params->feature_config_flags &
 668               FEATURE_CONFIG_PFC_ENABLED) &&
 669                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 670                 val |= 0x800000;
 671         wb_data[0] = val;
 672         wb_data[1] = 0;
 673         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
 674 }
 675
 676 static void bnx2x_update_pfc_bmac2(struct link_params *params,
 677                                    struct link_vars *vars,
 678                                    u8 is_lb)
 679 {
 680         /*
 681          * Set rx control: Strip CRC and enable BigMAC to relay
 682          * control packets to the system as well
 683          */
 684         u32 wb_data[2];
 685         struct bnx2x *bp = params->bp;
 686         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 687                 NIG_REG_INGRESS_BMAC0_MEM;
 688         u32 val = 0x14;
 689
 690         if ((!(params->feature_config_flags &
 691               FEATURE_CONFIG_PFC_ENABLED)) &&
 692                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 693                 /* Enable BigMAC to react on received Pause packets */
 694                 val |= (1<<5);
 695         wb_data[0] = val;
 696         wb_data[1] = 0;
 697         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
 698         udelay(30);
 699
 700         /* Tx control */
 701         val = 0xc0;
 702         if (!(params->feature_config_flags &
 703                                 FEATURE_CONFIG_PFC_ENABLED) &&
 704             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 705                 val |= 0x800000;
 706         wb_data[0] = val;
 707         wb_data[1] = 0;
 708         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
 709
 710         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 711                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 712                 /* Enable PFC RX & TX & STATS and set 8 COS  */
 713                 wb_data[0] = 0x0;
 714                 wb_data[0] |= (1<<0);  /* RX */
 715                 wb_data[0] |= (1<<1);  /* TX */
 716                 wb_data[0] |= (1<<2);  /* Force initial Xon */
 717                 wb_data[0] |= (1<<3);  /* 8 cos */
 718                 wb_data[0] |= (1<<5);  /* STATS */
 719                 wb_data[1] = 0;
 720                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
 721                             wb_data, 2);
 722                 /* Clear the force Xon */
 723                 wb_data[0] &= ~(1<<2);
 724         } else {
 725                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
 726                 /* disable PFC RX & TX & STATS and set 8 COS */
 727                 wb_data[0] = 0x8;
 728                 wb_data[1] = 0;
 729         }
 730
 731         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 732
 733         /*
 734          * Set Time (based unit is 512 bit time) between automatic
 735          * re-sending of PP packets amd enable automatic re-send of
 736          * Per-Priroity Packet as long as pp_gen is asserted and
 737          * pp_disable is low.
 738          */
 739         val = 0x8000;
 740         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 741                 val |= (1<<16); /* enable automatic re-send */
 742
 743         wb_data[0] = val;
 744         wb_data[1] = 0;
 745         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
 746                     wb_data, 2);
 747
 748         /* mac control */
 749         val = 0x3; /* Enable RX and TX */
 750         if (is_lb) {
 751                 val |= 0x4; /* Local loopback */
 752                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
 753         }
 754         /* When PFC enabled, Pass pause frames towards the NIG. */
 755         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 756                 val |= ((1<<6)|(1<<5));
 757
 758         wb_data[0] = val;
 759         wb_data[1] = 0;
 760         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
 761 }
 762
 763 static void bnx2x_update_pfc_brb(struct link_params *params,
 764                 struct link_vars *vars,
 765                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 766 {
 767         struct bnx2x *bp = params->bp;
 768         int set_pfc = params->feature_config_flags &
 769                 FEATURE_CONFIG_PFC_ENABLED;
 770
 771         /* default - pause configuration */
 772         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 773         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 774         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 775         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 776
 777         if (set_pfc && pfc_params)
 778                 /* First COS */
 779                 if (!pfc_params->cos0_pauseable) {
 780                         pause_xoff_th =
 781                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 782                         pause_xon_th =
 783                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 784                         full_xoff_th =
 785                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 786                         full_xon_th =
 787                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 788                 }
 789         /*
 790          * The number of free blocks below which the pause signal to class 0
 791          * of MAC #n is asserted. n=0,1
 792          */
 793         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
 794         /*
 795          * The number of free blocks above which the pause signal to class 0
 796          * of MAC #n is de-asserted. n=0,1
 797          */
 798         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
 799         /*
 800          * The number of free blocks below which the full signal to class 0
 801          * of MAC #n is asserted. n=0,1
 802          */
 803         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
 804         /*
 805          * The number of free blocks above which the full signal to class 0
 806          * of MAC #n is de-asserted. n=0,1
 807          */
 808         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
 809
 810         if (set_pfc && pfc_params) {
 811                 /* Second COS */
 812                 if (pfc_params->cos1_pauseable) {
 813                         pause_xoff_th =
 814                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 815                         pause_xon_th =
 816                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 817                         full_xoff_th =
 818                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 819                         full_xon_th =
 820                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 821                 } else {
 822                         pause_xoff_th =
 823                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 824                         pause_xon_th =
 825                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 826                         full_xoff_th =
 827                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 828                         full_xon_th =
 829                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 830                 }
 831                 /*
 832                  * The number of free blocks below which the pause signal to
 833                  * class 1 of MAC #n is asserted. n=0,1
 834                  */
 835                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
 836                 /*
 837                  * The number of free blocks above which the pause signal to
 838                  * class 1 of MAC #n is de-asserted. n=0,1
 839                  */
 840                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
 841                 /*
 842                  * The number of free blocks below which the full signal to
 843                  * class 1 of MAC #n is asserted. n=0,1
 844                  */
 845                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
 846                 /*
 847                  * The number of free blocks above which the full signal to
 848                  * class 1 of MAC #n is de-asserted. n=0,1
 849                  */
 850                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
 851         }
 852 }
 853
 854 static void bnx2x_update_pfc_nig(struct link_params *params,
 855                 struct link_vars *vars,
 856                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
 857 {
 858         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
 859         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
 860         u32 pkt_priority_to_cos = 0;
 861         u32 val;
 862         struct bnx2x *bp = params->bp;
 863         int port = params->port;
 864         int set_pfc = params->feature_config_flags &
 865                 FEATURE_CONFIG_PFC_ENABLED;
 866         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
 867
 868         /*
 869          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
 870          * MAC control frames (that are not pause packets)
 871          * will be forwarded to the XCM.
 872          */
 873         xcm_mask = REG_RD(bp,
 874                                 port ? NIG_REG_LLH1_XCM_MASK :
 875                                 NIG_REG_LLH0_XCM_MASK);
 876         /*
 877          * nig params will override non PFC params, since it's possible to
 878          * do transition from PFC to SAFC
 879          */
 880         if (set_pfc) {
 881                 pause_enable = 0;
 882                 llfc_out_en = 0;
 883                 llfc_enable = 0;
 884                 ppp_enable = 1;
 885                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 886                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 887                 xcm0_out_en = 0;
 888                 p0_hwpfc_enable = 1;
 889         } else  {
 890                 if (nig_params) {
 891                         llfc_out_en = nig_params->llfc_out_en;
 892                         llfc_enable = nig_params->llfc_enable;
 893                         pause_enable = nig_params->pause_enable;
 894                 } else  /*defaul non PFC mode - PAUSE */
 895                         pause_enable = 1;
 896
 897                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 898                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 899                 xcm0_out_en = 1;
 900         }
 901
 902         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
 903                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
 904         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
 905                NIG_REG_LLFC_ENABLE_0, llfc_enable);
 906         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
 907                NIG_REG_PAUSE_ENABLE_0, pause_enable);
 908
 909         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
 910                NIG_REG_PPP_ENABLE_0, ppp_enable);
 911
 912         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
 913                NIG_REG_LLH0_XCM_MASK, xcm_mask);
 914
 915         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
 916
 917         /* output enable for RX_XCM # IF */
 918         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
 919
 920         /* HW PFC TX enable */
 921         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
 922
 923         /* 0x2 = BMAC, 0x1= EMAC */
 924         switch (vars->mac_type) {
 925         case MAC_TYPE_EMAC:
 926                 val = 1;
 927                 break;
 928         case MAC_TYPE_BMAC:
 929                 val = 0;
 930                 break;
 931         default:
 932                 val = 0;
 933                 break;
 934         }
 935         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
 936
 937         if (nig_params) {
 938                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
 939
 940                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
 941                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
 942                        nig_params->rx_cos0_priority_mask);
 943
 944                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
 945                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
 946                        nig_params->rx_cos1_priority_mask);
 947
 948                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
 949                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
 950                        nig_params->llfc_high_priority_classes);
 951
 952                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
 953                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
 954                        nig_params->llfc_low_priority_classes);
 955         }
 956         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
 957                NIG_REG_P0_PKT_PRIORITY_TO_COS,
 958                pkt_priority_to_cos);
 959 }
 960
 961
 962 void bnx2x_update_pfc(struct link_params *params,
 963                       struct link_vars *vars,
 964                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 965 {
 966         /*
 967          * The PFC and pause are orthogonal to one another, meaning when
 968          * PFC is enabled, the pause are disabled, and when PFC is
 969          * disabled, pause are set according to the pause result.
 970          */
 971         u32 val;
 972         struct bnx2x *bp = params->bp;
 973
 974         /* update NIG params */
 975         bnx2x_update_pfc_nig(params, vars, pfc_params);
 976
 977         /* update BRB params */
 978         bnx2x_update_pfc_brb(params, vars, pfc_params);
 979
 980         if (!vars->link_up)
 981                 return;
 982
 983         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 984         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 985             == 0) {
 986                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
 987                 bnx2x_emac_enable(params, vars, 0);
 988                 return;
 989         }
 990
 991         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
 992         if (CHIP_IS_E2(bp))
 993                 bnx2x_update_pfc_bmac2(params, vars, 0);
 994         else
 995                 bnx2x_update_pfc_bmac1(params, vars);
 996
 997         val = 0;
 998         if ((params->feature_config_flags &
 999               FEATURE_CONFIG_PFC_ENABLED) ||
1000             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001                 val = 1;
1002         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003 }
1004
1005 static int bnx2x_bmac1_enable(struct link_params *params,
1006                               struct link_vars *vars,
1007                               u8 is_lb)
1008 {
1009         struct bnx2x *bp = params->bp;
1010         u8 port = params->port;
1011         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012                                NIG_REG_INGRESS_BMAC0_MEM;
1013         u32 wb_data[2];
1014         u32 val;
1015
1016         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1017
1018         /* XGXS control */
1019         wb_data[0] = 0x3c;
1020         wb_data[1] = 0;
1021         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022                     wb_data, 2);
1023
1024         /* tx MAC SA */
1025         wb_data[0] = ((params->mac_addr[2] << 24) |
1026                        (params->mac_addr[3] << 16) |
1027                        (params->mac_addr[4] << 8) |
1028                         params->mac_addr[5]);
1029         wb_data[1] = ((params->mac_addr[0] << 8) |
1030                         params->mac_addr[1]);
1031         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1032
1033         /* mac control */
1034         val = 0x3;
1035         if (is_lb) {
1036                 val |= 0x4;
1037                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038         }
1039         wb_data[0] = val;
1040         wb_data[1] = 0;
1041         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1042
1043         /* set rx mtu */
1044         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045         wb_data[1] = 0;
1046         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1047
1048         bnx2x_update_pfc_bmac1(params, vars);
1049
1050         /* set tx mtu */
1051         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052         wb_data[1] = 0;
1053         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1054
1055         /* set cnt max size */
1056         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057         wb_data[1] = 0;
1058         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1059
1060         /* configure safc */
1061         wb_data[0] = 0x1000200;
1062         wb_data[1] = 0;
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064                     wb_data, 2);
1065
1066         return 0;
1067 }
1068
1069 static int bnx2x_bmac2_enable(struct link_params *params,
1070                               struct link_vars *vars,
1071                               u8 is_lb)
1072 {
1073         struct bnx2x *bp = params->bp;
1074         u8 port = params->port;
1075         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076                                NIG_REG_INGRESS_BMAC0_MEM;
1077         u32 wb_data[2];
1078
1079         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081         wb_data[0] = 0;
1082         wb_data[1] = 0;
1083         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1084         udelay(30);
1085
1086         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087         wb_data[0] = 0x3c;
1088         wb_data[1] = 0;
1089         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090                     wb_data, 2);
1091
1092         udelay(30);
1093
1094         /* tx MAC SA */
1095         wb_data[0] = ((params->mac_addr[2] << 24) |
1096                        (params->mac_addr[3] << 16) |
1097                        (params->mac_addr[4] << 8) |
1098                         params->mac_addr[5]);
1099         wb_data[1] = ((params->mac_addr[0] << 8) |
1100                         params->mac_addr[1]);
1101         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1102                     wb_data, 2);
1103
1104         udelay(30);
1105
1106         /* Configure SAFC */
1107         wb_data[0] = 0x1000200;
1108         wb_data[1] = 0;
1109         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1110                     wb_data, 2);
1111         udelay(30);
1112
1113         /* set rx mtu */
1114         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115         wb_data[1] = 0;
1116         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1117         udelay(30);
1118
1119         /* set tx mtu */
1120         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121         wb_data[1] = 0;
1122         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1123         udelay(30);
1124         /* set cnt max size */
1125         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126         wb_data[1] = 0;
1127         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1128         udelay(30);
1129         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1130
1131         return 0;
1132 }
1133
1134 static int bnx2x_bmac_enable(struct link_params *params,
1135                              struct link_vars *vars,
1136                              u8 is_lb)
1137 {
1138         int rc = 0;
1139         u8 port = params->port;
1140         struct bnx2x *bp = params->bp;
1141         u32 val;
1142         /* reset and unreset the BigMac */
1143         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1144                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1145         msleep(1);
1146
1147         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1148                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1149
1150         /* enable access for bmac registers */
1151         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1152
1153         /* Enable BMAC according to BMAC type*/
1154         if (CHIP_IS_E2(bp))
1155                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1156         else
1157                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1158         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1159         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1160         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1161         val = 0;
1162         if ((params->feature_config_flags &
1163               FEATURE_CONFIG_PFC_ENABLED) ||
1164             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1165                 val = 1;
1166         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1167         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1168         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1169         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1170         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1171         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1172
1173         vars->mac_type = MAC_TYPE_BMAC;
1174         return rc;
1175 }
1176
1177
1178 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1179 {
1180         struct bnx2x *bp = params->bp;
1181
1182         REG_WR(bp, params->shmem_base +
1183                offsetof(struct shmem_region,
1184                         port_mb[params->port].link_status), link_status);
1185 }
1186
1187 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1188 {
1189         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1190                         NIG_REG_INGRESS_BMAC0_MEM;
1191         u32 wb_data[2];
1192         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1193
1194         /* Only if the bmac is out of reset */
1195         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1196                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1197             nig_bmac_enable) {
1198
1199                 if (CHIP_IS_E2(bp)) {
1200                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1201                         REG_RD_DMAE(bp, bmac_addr +
1202                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1203                                     wb_data, 2);
1204                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1205                         REG_WR_DMAE(bp, bmac_addr +
1206                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1207                                     wb_data, 2);
1208                 } else {
1209                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1210                         REG_RD_DMAE(bp, bmac_addr +
1211                                         BIGMAC_REGISTER_BMAC_CONTROL,
1212                                         wb_data, 2);
1213                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1214                         REG_WR_DMAE(bp, bmac_addr +
1215                                         BIGMAC_REGISTER_BMAC_CONTROL,
1216                                         wb_data, 2);
1217                 }
1218                 msleep(1);
1219         }
1220 }
1221
1222 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1223                             u32 line_speed)
1224 {
1225         struct bnx2x *bp = params->bp;
1226         u8 port = params->port;
1227         u32 init_crd, crd;
1228         u32 count = 1000;
1229
1230         /* disable port */
1231         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1232
1233         /* wait for init credit */
1234         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1235         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1236         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1237
1238         while ((init_crd != crd) && count) {
1239                 msleep(5);
1240
1241                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1242                 count--;
1243         }
1244         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1245         if (init_crd != crd) {
1246                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1247                           init_crd, crd);
1248                 return -EINVAL;
1249         }
1250
1251         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1252             line_speed == SPEED_10 ||
1253             line_speed == SPEED_100 ||
1254             line_speed == SPEED_1000 ||
1255             line_speed == SPEED_2500) {
1256                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1257                 /* update threshold */
1258                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1259                 /* update init credit */
1260                 init_crd = 778;         /* (800-18-4) */
1261
1262         } else {
1263                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1264                               ETH_OVREHEAD)/16;
1265                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1266                 /* update threshold */
1267                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1268                 /* update init credit */
1269                 switch (line_speed) {
1270                 case SPEED_10000:
1271                         init_crd = thresh + 553 - 22;
1272                         break;
1273
1274                 case SPEED_12000:
1275                         init_crd = thresh + 664 - 22;
1276                         break;
1277
1278                 case SPEED_13000:
1279                         init_crd = thresh + 742 - 22;
1280                         break;
1281
1282                 case SPEED_16000:
1283                         init_crd = thresh + 778 - 22;
1284                         break;
1285                 default:
1286                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1287                                   line_speed);
1288                         return -EINVAL;
1289                 }
1290         }
1291         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1292         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1293                  line_speed, init_crd);
1294
1295         /* probe the credit changes */
1296         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1297         msleep(5);
1298         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1299
1300         /* enable port */
1301         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1302         return 0;
1303 }
1304
1305 /**
1306  * bnx2x_get_emac_base - retrive emac base address
1307  *
1308  * @bp:                 driver handle
1309  * @mdc_mdio_access:    access type
1310  * @port:               port id
1311  *
1312  * This function selects the MDC/MDIO access (through emac0 or
1313  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1314  * phy has a default access mode, which could also be overridden
1315  * by nvram configuration. This parameter, whether this is the
1316  * default phy configuration, or the nvram overrun
1317  * configuration, is passed here as mdc_mdio_access and selects
1318  * the emac_base for the CL45 read/writes operations
1319  */
1320 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1321                                u32 mdc_mdio_access, u8 port)
1322 {
1323         u32 emac_base = 0;
1324         switch (mdc_mdio_access) {
1325         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1326                 break;
1327         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1328                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1329                         emac_base = GRCBASE_EMAC1;
1330                 else
1331                         emac_base = GRCBASE_EMAC0;
1332                 break;
1333         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1334                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1335                         emac_base = GRCBASE_EMAC0;
1336                 else
1337                         emac_base = GRCBASE_EMAC1;
1338                 break;
1339         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1340                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1341                 break;
1342         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1343                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1344                 break;
1345         default:
1346                 break;
1347         }
1348         return emac_base;
1349
1350 }
1351
1352 /******************************************************************/
1353 /*                      CL45 access functions                     */
1354 /******************************************************************/
1355 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1356                             u8 devad, u16 reg, u16 val)
1357 {
1358         u32 tmp, saved_mode;
1359         u8 i;
1360         int rc = 0;
1361         /*
1362          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1363          * (a value of 49==0x31) and make sure that the AUTO poll is off
1364          */
1365
1366         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1367         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1368                              EMAC_MDIO_MODE_CLOCK_CNT);
1369         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1370                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1371         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1372         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1373         udelay(40);
1374
1375         /* address */
1376
1377         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1378                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1379                EMAC_MDIO_COMM_START_BUSY);
1380         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1381
1382         for (i = 0; i < 50; i++) {
1383                 udelay(10);
1384
1385                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1386                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1387                         udelay(5);
1388                         break;
1389                 }
1390         }
1391         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1393                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1394                 rc = -EFAULT;
1395         } else {
1396                 /* data */
1397                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1398                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1399                        EMAC_MDIO_COMM_START_BUSY);
1400                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1401
1402                 for (i = 0; i < 50; i++) {
1403                         udelay(10);
1404
1405                         tmp = REG_RD(bp, phy->mdio_ctrl +
1406                                      EMAC_REG_EMAC_MDIO_COMM);
1407                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1408                                 udelay(5);
1409                                 break;
1410                         }
1411                 }
1412                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1413                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1414                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1415                         rc = -EFAULT;
1416                 }
1417         }
1418
1419         /* Restore the saved mode */
1420         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1421
1422         return rc;
1423 }
1424
1425 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1426                            u8 devad, u16 reg, u16 *ret_val)
1427 {
1428         u32 val, saved_mode;
1429         u16 i;
1430         int rc = 0;
1431         /*
1432          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1433          * (a value of 49==0x31) and make sure that the AUTO poll is off
1434          */
1435
1436         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1437         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1438                               EMAC_MDIO_MODE_CLOCK_CNT));
1439         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1440                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1441         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1442         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1443         udelay(40);
1444
1445         /* address */
1446         val = ((phy->addr << 21) | (devad << 16) | reg |
1447                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1448                EMAC_MDIO_COMM_START_BUSY);
1449         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1450
1451         for (i = 0; i < 50; i++) {
1452                 udelay(10);
1453
1454                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1455                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1456                         udelay(5);
1457                         break;
1458                 }
1459         }
1460         if (val & EMAC_MDIO_COMM_START_BUSY) {
1461                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1462                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1463                 *ret_val = 0;
1464                 rc = -EFAULT;
1465
1466         } else {
1467                 /* data */
1468                 val = ((phy->addr << 21) | (devad << 16) |
1469                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1470                        EMAC_MDIO_COMM_START_BUSY);
1471                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1472
1473                 for (i = 0; i < 50; i++) {
1474                         udelay(10);
1475
1476                         val = REG_RD(bp, phy->mdio_ctrl +
1477                                      EMAC_REG_EMAC_MDIO_COMM);
1478                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1479                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1480                                 break;
1481                         }
1482                 }
1483                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1484                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1485                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1486                         *ret_val = 0;
1487                         rc = -EFAULT;
1488                 }
1489         }
1490
1491         /* Restore the saved mode */
1492         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1493
1494         return rc;
1495 }
1496
1497 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1498                    u8 devad, u16 reg, u16 *ret_val)
1499 {
1500         u8 phy_index;
1501         /*
1502          * Probe for the phy according to the given phy_addr, and execute
1503          * the read request on it
1504          */
1505         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1506                 if (params->phy[phy_index].addr == phy_addr) {
1507                         return bnx2x_cl45_read(params->bp,
1508                                                &params->phy[phy_index], devad,
1509                                                reg, ret_val);
1510                 }
1511         }
1512         return -EINVAL;
1513 }
1514
1515 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1516                     u8 devad, u16 reg, u16 val)
1517 {
1518         u8 phy_index;
1519         /*
1520          * Probe for the phy according to the given phy_addr, and execute
1521          * the write request on it
1522          */
1523         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1524                 if (params->phy[phy_index].addr == phy_addr) {
1525                         return bnx2x_cl45_write(params->bp,
1526                                                 &params->phy[phy_index], devad,
1527                                                 reg, val);
1528                 }
1529         }
1530         return -EINVAL;
1531 }
1532
1533 static void bnx2x_set_aer_mmd(struct link_params *params,
1534                               struct bnx2x_phy *phy)
1535 {
1536         u32 ser_lane;
1537         u16 offset, aer_val;
1538         struct bnx2x *bp = params->bp;
1539         ser_lane = ((params->lane_config &
1540                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542
1543         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
1544                 (phy->addr + ser_lane) : 0;
1545
1546         if (CHIP_IS_E2(bp))
1547                 aer_val = 0x3800 + offset - 1;
1548         else
1549                 aer_val = 0x3800 + offset;
1550         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
1551         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1552                           MDIO_AER_BLOCK_AER_REG, aer_val);
1553
1554 }
1555
1556 /******************************************************************/
1557 /*                      Internal phy section                      */
1558 /******************************************************************/
1559
1560 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1561 {
1562         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1563
1564         /* Set Clause 22 */
1565         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1566         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1567         udelay(500);
1568         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1569         udelay(500);
1570          /* Set Clause 45 */
1571         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1572 }
1573
1574 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1575 {
1576         u32 val;
1577
1578         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1579
1580         val = SERDES_RESET_BITS << (port*16);
1581
1582         /* reset and unreset the SerDes/XGXS */
1583         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1584         udelay(500);
1585         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1586
1587         bnx2x_set_serdes_access(bp, port);
1588
1589         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1590                DEFAULT_PHY_DEV_ADDR);
1591 }
1592
1593 static void bnx2x_xgxs_deassert(struct link_params *params)
1594 {
1595         struct bnx2x *bp = params->bp;
1596         u8 port;
1597         u32 val;
1598         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1599         port = params->port;
1600
1601         val = XGXS_RESET_BITS << (port*16);
1602
1603         /* reset and unreset the SerDes/XGXS */
1604         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1605         udelay(500);
1606         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1607
1608         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1609         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1610                params->phy[INT_PHY].def_md_devad);
1611 }
1612
1613 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1614                                      struct link_params *params, u16 *ieee_fc)
1615 {
1616         struct bnx2x *bp = params->bp;
1617         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1618         /**
1619          * resolve pause mode and advertisement Please refer to Table
1620          * 28B-3 of the 802.3ab-1999 spec
1621          */
1622
1623         switch (phy->req_flow_ctrl) {
1624         case BNX2X_FLOW_CTRL_AUTO:
1625                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
1626                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1627                 else
1628                         *ieee_fc |=
1629                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1630                 break;
1631
1632         case BNX2X_FLOW_CTRL_TX:
1633                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1634                 break;
1635
1636         case BNX2X_FLOW_CTRL_RX:
1637         case BNX2X_FLOW_CTRL_BOTH:
1638                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1639                 break;
1640
1641         case BNX2X_FLOW_CTRL_NONE:
1642         default:
1643                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1644                 break;
1645         }
1646         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1647 }
1648
1649 static void set_phy_vars(struct link_params *params,
1650                          struct link_vars *vars)
1651 {
1652         struct bnx2x *bp = params->bp;
1653         u8 actual_phy_idx, phy_index, link_cfg_idx;
1654         u8 phy_config_swapped = params->multi_phy_config &
1655                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
1656         for (phy_index = INT_PHY; phy_index < params->num_phys;
1657               phy_index++) {
1658                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
1659                 actual_phy_idx = phy_index;
1660                 if (phy_config_swapped) {
1661                         if (phy_index == EXT_PHY1)
1662                                 actual_phy_idx = EXT_PHY2;
1663                         else if (phy_index == EXT_PHY2)
1664                                 actual_phy_idx = EXT_PHY1;
1665                 }
1666                 params->phy[actual_phy_idx].req_flow_ctrl =
1667                         params->req_flow_ctrl[link_cfg_idx];
1668
1669                 params->phy[actual_phy_idx].req_line_speed =
1670                         params->req_line_speed[link_cfg_idx];
1671
1672                 params->phy[actual_phy_idx].speed_cap_mask =
1673                         params->speed_cap_mask[link_cfg_idx];
1674
1675                 params->phy[actual_phy_idx].req_duplex =
1676                         params->req_duplex[link_cfg_idx];
1677
1678                 if (params->req_line_speed[link_cfg_idx] ==
1679                     SPEED_AUTO_NEG)
1680                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1681
1682                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
1683                            " speed_cap_mask %x\n",
1684                            params->phy[actual_phy_idx].req_flow_ctrl,
1685                            params->phy[actual_phy_idx].req_line_speed,
1686                            params->phy[actual_phy_idx].speed_cap_mask);
1687         }
1688 }
1689
1690 static void bnx2x_ext_phy_set_pause(struct link_params *params,
1691                                     struct bnx2x_phy *phy,
1692                                     struct link_vars *vars)
1693 {
1694         u16 val;
1695         struct bnx2x *bp = params->bp;
1696         /* read modify write pause advertizing */
1697         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
1698
1699         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
1700
1701         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
1702         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
1703         if ((vars->ieee_fc &
1704             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
1705             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
1706                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
1707         }
1708         if ((vars->ieee_fc &
1709             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
1710             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
1711                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
1712         }
1713         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
1714         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
1715 }
1716
1717 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1718 {                                               /*  LD      LP   */
1719         switch (pause_result) {                 /* ASYM P ASYM P */
1720         case 0xb:                               /*   1  0   1  1 */
1721                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1722                 break;
1723
1724         case 0xe:                               /*   1  1   1  0 */
1725                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1726                 break;
1727
1728         case 0x5:                               /*   0  1   0  1 */
1729         case 0x7:                               /*   0  1   1  1 */
1730         case 0xd:                               /*   1  1   0  1 */
1731         case 0xf:                               /*   1  1   1  1 */
1732                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1733                 break;
1734
1735         default:
1736                 break;
1737         }
1738         if (pause_result & (1<<0))
1739                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1740         if (pause_result & (1<<1))
1741                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1742 }
1743
1744 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
1745                                    struct link_params *params,
1746                                    struct link_vars *vars)
1747 {
1748         struct bnx2x *bp = params->bp;
1749         u16 ld_pause;           /* local */
1750         u16 lp_pause;           /* link partner */
1751         u16 pause_result;
1752         u8 ret = 0;
1753         /* read twice */
1754
1755         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1756
1757         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1758                 vars->flow_ctrl = phy->req_flow_ctrl;
1759         else if (phy->req_line_speed != SPEED_AUTO_NEG)
1760                 vars->flow_ctrl = params->req_fc_auto_adv;
1761         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
1762                 ret = 1;
1763                 bnx2x_cl45_read(bp, phy,
1764                                 MDIO_AN_DEVAD,
1765                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1766                 bnx2x_cl45_read(bp, phy,
1767                                 MDIO_AN_DEVAD,
1768                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1769                 pause_result = (ld_pause &
1770                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1771                 pause_result |= (lp_pause &
1772                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1773                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
1774                    pause_result);
1775                 bnx2x_pause_resolve(vars, pause_result);
1776         }
1777         return ret;
1778 }
1779 void bnx2x_link_status_update(struct link_params *params,
1780                               struct link_vars *vars)
1781 {
1782         struct bnx2x *bp = params->bp;
1783         u8 link_10g;
1784         u8 port = params->port;
1785         u32 sync_offset, media_types;
1786         /* Update PHY configuration */
1787         set_phy_vars(params, vars);
1788
1789         vars->link_status = REG_RD(bp, params->shmem_base +
1790                                    offsetof(struct shmem_region,
1791                                             port_mb[port].link_status));
1792
1793         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1794         vars->phy_flags = PHY_XGXS_FLAG;
1795         if (vars->link_up) {
1796                 DP(NETIF_MSG_LINK, "phy link up\n");
1797
1798                 vars->phy_link_up = 1;
1799                 vars->duplex = DUPLEX_FULL;
1800                 switch (vars->link_status &
1801                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1802                         case LINK_10THD:
1803                                 vars->duplex = DUPLEX_HALF;
1804                                 /* fall thru */
1805                         case LINK_10TFD:
1806                                 vars->line_speed = SPEED_10;
1807                                 break;
1808
1809                         case LINK_100TXHD:
1810                                 vars->duplex = DUPLEX_HALF;
1811                                 /* fall thru */
1812                         case LINK_100T4:
1813                         case LINK_100TXFD:
1814                                 vars->line_speed = SPEED_100;
1815                                 break;
1816
1817                         case LINK_1000THD:
1818                                 vars->duplex = DUPLEX_HALF;
1819                                 /* fall thru */
1820                         case LINK_1000TFD:
1821                                 vars->line_speed = SPEED_1000;
1822                                 break;
1823
1824                         case LINK_2500THD:
1825                                 vars->duplex = DUPLEX_HALF;
1826                                 /* fall thru */
1827                         case LINK_2500TFD:
1828                                 vars->line_speed = SPEED_2500;
1829                                 break;
1830
1831                         case LINK_10GTFD:
1832                                 vars->line_speed = SPEED_10000;
1833                                 break;
1834
1835                         case LINK_12GTFD:
1836                                 vars->line_speed = SPEED_12000;
1837                                 break;
1838
1839                         case LINK_12_5GTFD:
1840                                 vars->line_speed = SPEED_12500;
1841                                 break;
1842
1843                         case LINK_13GTFD:
1844                                 vars->line_speed = SPEED_13000;
1845                                 break;
1846
1847                         case LINK_15GTFD:
1848                                 vars->line_speed = SPEED_15000;
1849                                 break;
1850
1851                         case LINK_16GTFD:
1852                                 vars->line_speed = SPEED_16000;
1853                                 break;
1854
1855                         default:
1856                                 break;
1857                 }
1858                 vars->flow_ctrl = 0;
1859                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1860                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1861
1862                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1863                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1864
1865                 if (!vars->flow_ctrl)
1866                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1867
1868                 if (vars->line_speed &&
1869                     ((vars->line_speed == SPEED_10) ||
1870                      (vars->line_speed == SPEED_100))) {
1871                         vars->phy_flags |= PHY_SGMII_FLAG;
1872                 } else {
1873                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1874                 }
1875
1876                 /* anything 10 and over uses the bmac */
1877                 link_10g = ((vars->line_speed == SPEED_10000) ||
1878                             (vars->line_speed == SPEED_12000) ||
1879                             (vars->line_speed == SPEED_12500) ||
1880                             (vars->line_speed == SPEED_13000) ||
1881                             (vars->line_speed == SPEED_15000) ||
1882                             (vars->line_speed == SPEED_16000));
1883                 if (link_10g)
1884                         vars->mac_type = MAC_TYPE_BMAC;
1885                 else
1886                         vars->mac_type = MAC_TYPE_EMAC;
1887
1888         } else { /* link down */
1889                 DP(NETIF_MSG_LINK, "phy link down\n");
1890
1891                 vars->phy_link_up = 0;
1892
1893                 vars->line_speed = 0;
1894                 vars->duplex = DUPLEX_FULL;
1895                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1896
1897                 /* indicate no mac active */
1898                 vars->mac_type = MAC_TYPE_NONE;
1899         }
1900
1901         /* Sync media type */
1902         sync_offset = params->shmem_base +
1903                         offsetof(struct shmem_region,
1904                                  dev_info.port_hw_config[port].media_type);
1905         media_types = REG_RD(bp, sync_offset);
1906
1907         params->phy[INT_PHY].media_type =
1908                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
1909                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
1910         params->phy[EXT_PHY1].media_type =
1911                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
1912                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
1913         params->phy[EXT_PHY2].media_type =
1914                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
1915                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
1916         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
1917
1918         /* Sync AEU offset */
1919         sync_offset = params->shmem_base +
1920                         offsetof(struct shmem_region,
1921                                  dev_info.port_hw_config[port].aeu_int_mask);
1922
1923         vars->aeu_int_mask = REG_RD(bp, sync_offset);
1924
1925         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
1926                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
1927         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1928                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1929 }
1930
1931
1932 static void bnx2x_set_master_ln(struct link_params *params,
1933                                 struct bnx2x_phy *phy)
1934 {
1935         struct bnx2x *bp = params->bp;
1936         u16 new_master_ln, ser_lane;
1937         ser_lane = ((params->lane_config &
1938                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1939                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1940
1941         /* set the master_ln for AN */
1942         CL22_RD_OVER_CL45(bp, phy,
1943                           MDIO_REG_BANK_XGXS_BLOCK2,
1944                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1945                           &new_master_ln);
1946
1947         CL22_WR_OVER_CL45(bp, phy,
1948                           MDIO_REG_BANK_XGXS_BLOCK2 ,
1949                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1950                           (new_master_ln | ser_lane));
1951 }
1952
1953 static int bnx2x_reset_unicore(struct link_params *params,
1954                                struct bnx2x_phy *phy,
1955                                u8 set_serdes)
1956 {
1957         struct bnx2x *bp = params->bp;
1958         u16 mii_control;
1959         u16 i;
1960         CL22_RD_OVER_CL45(bp, phy,
1961                           MDIO_REG_BANK_COMBO_IEEE0,
1962                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1963
1964         /* reset the unicore */
1965         CL22_WR_OVER_CL45(bp, phy,
1966                           MDIO_REG_BANK_COMBO_IEEE0,
1967                           MDIO_COMBO_IEEE0_MII_CONTROL,
1968                           (mii_control |
1969                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1970         if (set_serdes)
1971                 bnx2x_set_serdes_access(bp, params->port);
1972
1973         /* wait for the reset to self clear */
1974         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1975                 udelay(5);
1976
1977                 /* the reset erased the previous bank value */
1978                 CL22_RD_OVER_CL45(bp, phy,
1979                                   MDIO_REG_BANK_COMBO_IEEE0,
1980                                   MDIO_COMBO_IEEE0_MII_CONTROL,
1981                                   &mii_control);
1982
1983                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1984                         udelay(5);
1985                         return 0;
1986                 }
1987         }
1988
1989         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
1990                               " Port %d\n",
1991                          params->port);
1992         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1993         return -EINVAL;
1994
1995 }
1996
1997 static void bnx2x_set_swap_lanes(struct link_params *params,
1998                                  struct bnx2x_phy *phy)
1999 {
2000         struct bnx2x *bp = params->bp;
2001         /*
2002          *  Each two bits represents a lane number:
2003          *  No swap is 0123 => 0x1b no need to enable the swap
2004          */
2005         u16 ser_lane, rx_lane_swap, tx_lane_swap;
2006
2007         ser_lane = ((params->lane_config &
2008                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2009                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2010         rx_lane_swap = ((params->lane_config &
2011                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
2012                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
2013         tx_lane_swap = ((params->lane_config &
2014                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
2015                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
2016
2017         if (rx_lane_swap != 0x1b) {
2018                 CL22_WR_OVER_CL45(bp, phy,
2019                                   MDIO_REG_BANK_XGXS_BLOCK2,
2020                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2021                                   (rx_lane_swap |
2022                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2023                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2024         } else {
2025                 CL22_WR_OVER_CL45(bp, phy,
2026                                   MDIO_REG_BANK_XGXS_BLOCK2,
2027                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2028         }
2029
2030         if (tx_lane_swap != 0x1b) {
2031                 CL22_WR_OVER_CL45(bp, phy,
2032                                   MDIO_REG_BANK_XGXS_BLOCK2,
2033                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2034                                   (tx_lane_swap |
2035                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2036         } else {
2037                 CL22_WR_OVER_CL45(bp, phy,
2038                                   MDIO_REG_BANK_XGXS_BLOCK2,
2039                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2040         }
2041 }
2042
2043 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
2044                                          struct link_params *params)
2045 {
2046         struct bnx2x *bp = params->bp;
2047         u16 control2;
2048         CL22_RD_OVER_CL45(bp, phy,
2049                           MDIO_REG_BANK_SERDES_DIGITAL,
2050                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2051                           &control2);
2052         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2053                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2054         else
2055                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2056         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
2057                 phy->speed_cap_mask, control2);
2058         CL22_WR_OVER_CL45(bp, phy,
2059                           MDIO_REG_BANK_SERDES_DIGITAL,
2060                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2061                           control2);
2062
2063         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2064              (phy->speed_cap_mask &
2065                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
2066                 DP(NETIF_MSG_LINK, "XGXS\n");
2067
2068                 CL22_WR_OVER_CL45(bp, phy,
2069                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
2070                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2071                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2072
2073                 CL22_RD_OVER_CL45(bp, phy,
2074                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2075                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2076                                   &control2);
2077
2078
2079                 control2 |=
2080                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2081
2082                 CL22_WR_OVER_CL45(bp, phy,
2083                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2084                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2085                                   control2);
2086
2087                 /* Disable parallel detection of HiG */
2088                 CL22_WR_OVER_CL45(bp, phy,
2089                                   MDIO_REG_BANK_XGXS_BLOCK2,
2090                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2091                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2092                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2093         }
2094 }
2095
2096 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2097                               struct link_params *params,
2098                               struct link_vars *vars,
2099                               u8 enable_cl73)
2100 {
2101         struct bnx2x *bp = params->bp;
2102         u16 reg_val;
2103
2104         /* CL37 Autoneg */
2105         CL22_RD_OVER_CL45(bp, phy,
2106                           MDIO_REG_BANK_COMBO_IEEE0,
2107                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2108
2109         /* CL37 Autoneg Enabled */
2110         if (vars->line_speed == SPEED_AUTO_NEG)
2111                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2112         else /* CL37 Autoneg Disabled */
2113                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2114                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2115
2116         CL22_WR_OVER_CL45(bp, phy,
2117                           MDIO_REG_BANK_COMBO_IEEE0,
2118                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2119
2120         /* Enable/Disable Autodetection */
2121
2122         CL22_RD_OVER_CL45(bp, phy,
2123                           MDIO_REG_BANK_SERDES_DIGITAL,
2124                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2125         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
2126                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
2127         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
2128         if (vars->line_speed == SPEED_AUTO_NEG)
2129                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2130         else
2131                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2132
2133         CL22_WR_OVER_CL45(bp, phy,
2134                           MDIO_REG_BANK_SERDES_DIGITAL,
2135                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2136
2137         /* Enable TetonII and BAM autoneg */
2138         CL22_RD_OVER_CL45(bp, phy,
2139                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2140                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2141                           &reg_val);
2142         if (vars->line_speed == SPEED_AUTO_NEG) {
2143                 /* Enable BAM aneg Mode and TetonII aneg Mode */
2144                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2145                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2146         } else {
2147                 /* TetonII and BAM Autoneg Disabled */
2148                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2149                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2150         }
2151         CL22_WR_OVER_CL45(bp, phy,
2152                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2153                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2154                           reg_val);
2155
2156         if (enable_cl73) {
2157                 /* Enable Cl73 FSM status bits */
2158                 CL22_WR_OVER_CL45(bp, phy,
2159                                   MDIO_REG_BANK_CL73_USERB0,
2160                                   MDIO_CL73_USERB0_CL73_UCTRL,
2161                                   0xe);
2162
2163                 /* Enable BAM Station Manager*/
2164                 CL22_WR_OVER_CL45(bp, phy,
2165                         MDIO_REG_BANK_CL73_USERB0,
2166                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2167                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2168                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2169                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2170
2171                 /* Advertise CL73 link speeds */
2172                 CL22_RD_OVER_CL45(bp, phy,
2173                                   MDIO_REG_BANK_CL73_IEEEB1,
2174                                   MDIO_CL73_IEEEB1_AN_ADV2,
2175                                   &reg_val);
2176                 if (phy->speed_cap_mask &
2177                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2178                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2179                 if (phy->speed_cap_mask &
2180                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2181                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2182
2183                 CL22_WR_OVER_CL45(bp, phy,
2184                                   MDIO_REG_BANK_CL73_IEEEB1,
2185                                   MDIO_CL73_IEEEB1_AN_ADV2,
2186                                   reg_val);
2187
2188                 /* CL73 Autoneg Enabled */
2189                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2190
2191         } else /* CL73 Autoneg Disabled */
2192                 reg_val = 0;
2193
2194         CL22_WR_OVER_CL45(bp, phy,
2195                           MDIO_REG_BANK_CL73_IEEEB0,
2196                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2197 }
2198
2199 /* program SerDes, forced speed */
2200 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2201                                  struct link_params *params,
2202                                  struct link_vars *vars)
2203 {
2204         struct bnx2x *bp = params->bp;
2205         u16 reg_val;
2206
2207         /* program duplex, disable autoneg and sgmii*/
2208         CL22_RD_OVER_CL45(bp, phy,
2209                           MDIO_REG_BANK_COMBO_IEEE0,
2210                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2211         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2212                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2213                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2214         if (phy->req_duplex == DUPLEX_FULL)
2215                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2216         CL22_WR_OVER_CL45(bp, phy,
2217                           MDIO_REG_BANK_COMBO_IEEE0,
2218                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2219
2220         /*
2221          * program speed
2222          *  - needed only if the speed is greater than 1G (2.5G or 10G)
2223          */
2224         CL22_RD_OVER_CL45(bp, phy,
2225                           MDIO_REG_BANK_SERDES_DIGITAL,
2226                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2227         /* clearing the speed value before setting the right speed */
2228         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2229
2230         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2231                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2232
2233         if (!((vars->line_speed == SPEED_1000) ||
2234               (vars->line_speed == SPEED_100) ||
2235               (vars->line_speed == SPEED_10))) {
2236
2237                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2238                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2239                 if (vars->line_speed == SPEED_10000)
2240                         reg_val |=
2241                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2242                 if (vars->line_speed == SPEED_13000)
2243                         reg_val |=
2244                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2245         }
2246
2247         CL22_WR_OVER_CL45(bp, phy,
2248                           MDIO_REG_BANK_SERDES_DIGITAL,
2249                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
2250
2251 }
2252
2253 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
2254                                               struct link_params *params)
2255 {
2256         struct bnx2x *bp = params->bp;
2257         u16 val = 0;
2258
2259         /* configure the 48 bits for BAM AN */
2260
2261         /* set extended capabilities */
2262         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2263                 val |= MDIO_OVER_1G_UP1_2_5G;
2264         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2265                 val |= MDIO_OVER_1G_UP1_10G;
2266         CL22_WR_OVER_CL45(bp, phy,
2267                           MDIO_REG_BANK_OVER_1G,
2268                           MDIO_OVER_1G_UP1, val);
2269
2270         CL22_WR_OVER_CL45(bp, phy,
2271                           MDIO_REG_BANK_OVER_1G,
2272                           MDIO_OVER_1G_UP3, 0x400);
2273 }
2274
2275 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
2276                                               struct link_params *params,
2277                                               u16 ieee_fc)
2278 {
2279         struct bnx2x *bp = params->bp;
2280         u16 val;
2281         /* for AN, we are always publishing full duplex */
2282
2283         CL22_WR_OVER_CL45(bp, phy,
2284                           MDIO_REG_BANK_COMBO_IEEE0,
2285                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2286         CL22_RD_OVER_CL45(bp, phy,
2287                           MDIO_REG_BANK_CL73_IEEEB1,
2288                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
2289         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2290         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2291         CL22_WR_OVER_CL45(bp, phy,
2292                           MDIO_REG_BANK_CL73_IEEEB1,
2293                           MDIO_CL73_IEEEB1_AN_ADV1, val);
2294 }
2295
2296 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2297                                   struct link_params *params,
2298                                   u8 enable_cl73)
2299 {
2300         struct bnx2x *bp = params->bp;
2301         u16 mii_control;
2302
2303         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2304         /* Enable and restart BAM/CL37 aneg */
2305
2306         if (enable_cl73) {
2307                 CL22_RD_OVER_CL45(bp, phy,
2308                                   MDIO_REG_BANK_CL73_IEEEB0,
2309                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2310                                   &mii_control);
2311
2312                 CL22_WR_OVER_CL45(bp, phy,
2313                                   MDIO_REG_BANK_CL73_IEEEB0,
2314                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2315                                   (mii_control |
2316                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2317                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2318         } else {
2319
2320                 CL22_RD_OVER_CL45(bp, phy,
2321                                   MDIO_REG_BANK_COMBO_IEEE0,
2322                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2323                                   &mii_control);
2324                 DP(NETIF_MSG_LINK,
2325                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2326                          mii_control);
2327                 CL22_WR_OVER_CL45(bp, phy,
2328                                   MDIO_REG_BANK_COMBO_IEEE0,
2329                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2330                                   (mii_control |
2331                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2332                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2333         }
2334 }
2335
2336 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2337                                            struct link_params *params,
2338                                            struct link_vars *vars)
2339 {
2340         struct bnx2x *bp = params->bp;
2341         u16 control1;
2342
2343         /* in SGMII mode, the unicore is always slave */
2344
2345         CL22_RD_OVER_CL45(bp, phy,
2346                           MDIO_REG_BANK_SERDES_DIGITAL,
2347                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2348                           &control1);
2349         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2350         /* set sgmii mode (and not fiber) */
2351         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2352                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2353                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2354         CL22_WR_OVER_CL45(bp, phy,
2355                           MDIO_REG_BANK_SERDES_DIGITAL,
2356                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2357                           control1);
2358
2359         /* if forced speed */
2360         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2361                 /* set speed, disable autoneg */
2362                 u16 mii_control;
2363
2364                 CL22_RD_OVER_CL45(bp, phy,
2365                                   MDIO_REG_BANK_COMBO_IEEE0,
2366                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2367                                   &mii_control);
2368                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2369                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2370                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2371
2372                 switch (vars->line_speed) {
2373                 case SPEED_100:
2374                         mii_control |=
2375                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2376                         break;
2377                 case SPEED_1000:
2378                         mii_control |=
2379                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2380                         break;
2381                 case SPEED_10:
2382                         /* there is nothing to set for 10M */
2383                         break;
2384                 default:
2385                         /* invalid speed for SGMII */
2386                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2387                                   vars->line_speed);
2388                         break;
2389                 }
2390
2391                 /* setting the full duplex */
2392                 if (phy->req_duplex == DUPLEX_FULL)
2393                         mii_control |=
2394                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2395                 CL22_WR_OVER_CL45(bp, phy,
2396                                   MDIO_REG_BANK_COMBO_IEEE0,
2397                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2398                                   mii_control);
2399
2400         } else { /* AN mode */
2401                 /* enable and restart AN */
2402                 bnx2x_restart_autoneg(phy, params, 0);
2403         }
2404 }
2405
2406
2407 /*
2408  * link management
2409  */
2410
2411 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2412                                              struct link_params *params)
2413 {
2414         struct bnx2x *bp = params->bp;
2415         u16 pd_10g, status2_1000x;
2416         if (phy->req_line_speed != SPEED_AUTO_NEG)
2417                 return 0;
2418         CL22_RD_OVER_CL45(bp, phy,
2419                           MDIO_REG_BANK_SERDES_DIGITAL,
2420                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2421                           &status2_1000x);
2422         CL22_RD_OVER_CL45(bp, phy,
2423                           MDIO_REG_BANK_SERDES_DIGITAL,
2424                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2425                           &status2_1000x);
2426         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2427                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2428                          params->port);
2429                 return 1;
2430         }
2431
2432         CL22_RD_OVER_CL45(bp, phy,
2433                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
2434                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2435                           &pd_10g);
2436
2437         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2438                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2439                          params->port);
2440                 return 1;
2441         }
2442         return 0;
2443 }
2444
2445 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2446                                     struct link_params *params,
2447                                     struct link_vars *vars,
2448                                     u32 gp_status)
2449 {
2450         struct bnx2x *bp = params->bp;
2451         u16 ld_pause;   /* local driver */
2452         u16 lp_pause;   /* link partner */
2453         u16 pause_result;
2454
2455         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2456
2457         /* resolve from gp_status in case of AN complete and not sgmii */
2458         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2459                 vars->flow_ctrl = phy->req_flow_ctrl;
2460         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2461                 vars->flow_ctrl = params->req_fc_auto_adv;
2462         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2463                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2464                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2465                         vars->flow_ctrl = params->req_fc_auto_adv;
2466                         return;
2467                 }
2468                 if ((gp_status &
2469                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2470                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2471                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2472                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2473
2474                         CL22_RD_OVER_CL45(bp, phy,
2475                                           MDIO_REG_BANK_CL73_IEEEB1,
2476                                           MDIO_CL73_IEEEB1_AN_ADV1,
2477                                           &ld_pause);
2478                         CL22_RD_OVER_CL45(bp, phy,
2479                                           MDIO_REG_BANK_CL73_IEEEB1,
2480                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
2481                                           &lp_pause);
2482                         pause_result = (ld_pause &
2483                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2484                                         >> 8;
2485                         pause_result |= (lp_pause &
2486                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2487                                         >> 10;
2488                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2489                                  pause_result);
2490                 } else {
2491                         CL22_RD_OVER_CL45(bp, phy,
2492                                           MDIO_REG_BANK_COMBO_IEEE0,
2493                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2494                                           &ld_pause);
2495                         CL22_RD_OVER_CL45(bp, phy,
2496                                 MDIO_REG_BANK_COMBO_IEEE0,
2497                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2498                                 &lp_pause);
2499                         pause_result = (ld_pause &
2500                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2501                         pause_result |= (lp_pause &
2502                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2503                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2504                                  pause_result);
2505                 }
2506                 bnx2x_pause_resolve(vars, pause_result);
2507         }
2508         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2509 }
2510
2511 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2512                                          struct link_params *params)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u16 rx_status, ustat_val, cl37_fsm_received;
2516         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2517         /* Step 1: Make sure signal is detected */
2518         CL22_RD_OVER_CL45(bp, phy,
2519                           MDIO_REG_BANK_RX0,
2520                           MDIO_RX0_RX_STATUS,
2521                           &rx_status);
2522         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2523             (MDIO_RX0_RX_STATUS_SIGDET)) {
2524                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2525                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2526                 CL22_WR_OVER_CL45(bp, phy,
2527                                   MDIO_REG_BANK_CL73_IEEEB0,
2528                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2529                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2530                 return;
2531         }
2532         /* Step 2: Check CL73 state machine */
2533         CL22_RD_OVER_CL45(bp, phy,
2534                           MDIO_REG_BANK_CL73_USERB0,
2535                           MDIO_CL73_USERB0_CL73_USTAT1,
2536                           &ustat_val);
2537         if ((ustat_val &
2538              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2539               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2540             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2541               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2542                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2543                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2544                 return;
2545         }
2546         /*
2547          * Step 3: Check CL37 Message Pages received to indicate LP
2548          * supports only CL37
2549          */
2550         CL22_RD_OVER_CL45(bp, phy,
2551                           MDIO_REG_BANK_REMOTE_PHY,
2552                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
2553                           &cl37_fsm_received);
2554         if ((cl37_fsm_received &
2555              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2556              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2557             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2558               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2559                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2560                              "misc_rx_status(0x8330) = 0x%x\n",
2561                          cl37_fsm_received);
2562                 return;
2563         }
2564         /*
2565          * The combined cl37/cl73 fsm state information indicating that
2566          * we are connected to a device which does not support cl73, but
2567          * does support cl37 BAM. In this case we disable cl73 and
2568          * restart cl37 auto-neg
2569          */
2570
2571         /* Disable CL73 */
2572         CL22_WR_OVER_CL45(bp, phy,
2573                           MDIO_REG_BANK_CL73_IEEEB0,
2574                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2575                           0);
2576         /* Restart CL37 autoneg */
2577         bnx2x_restart_autoneg(phy, params, 0);
2578         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2579 }
2580
2581 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2582                                   struct link_params *params,
2583                                   struct link_vars *vars,
2584                                   u32 gp_status)
2585 {
2586         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2587                 vars->link_status |=
2588                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2589
2590         if (bnx2x_direct_parallel_detect_used(phy, params))
2591                 vars->link_status |=
2592                         LINK_STATUS_PARALLEL_DETECTION_USED;
2593 }
2594
2595 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
2596                                       struct link_params *params,
2597                                       struct link_vars *vars)
2598 {
2599         struct bnx2x *bp = params->bp;
2600         u16 new_line_speed, gp_status;
2601         int rc = 0;
2602
2603         /* Read gp_status */
2604         CL22_RD_OVER_CL45(bp, phy,
2605                           MDIO_REG_BANK_GP_STATUS,
2606                           MDIO_GP_STATUS_TOP_AN_STATUS1,
2607                           &gp_status);
2608
2609         if (phy->req_line_speed == SPEED_AUTO_NEG)
2610                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2611         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2612                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2613                          gp_status);
2614
2615                 vars->phy_link_up = 1;
2616                 vars->link_status |= LINK_STATUS_LINK_UP;
2617
2618                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2619                         vars->duplex = DUPLEX_FULL;
2620                 else
2621                         vars->duplex = DUPLEX_HALF;
2622
2623                 if (SINGLE_MEDIA_DIRECT(params)) {
2624                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2625                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2626                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2627                                                       gp_status);
2628                 }
2629
2630                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2631                 case GP_STATUS_10M:
2632                         new_line_speed = SPEED_10;
2633                         if (vars->duplex == DUPLEX_FULL)
2634                                 vars->link_status |= LINK_10TFD;
2635                         else
2636                                 vars->link_status |= LINK_10THD;
2637                         break;
2638
2639                 case GP_STATUS_100M:
2640                         new_line_speed = SPEED_100;
2641                         if (vars->duplex == DUPLEX_FULL)
2642                                 vars->link_status |= LINK_100TXFD;
2643                         else
2644                                 vars->link_status |= LINK_100TXHD;
2645                         break;
2646
2647                 case GP_STATUS_1G:
2648                 case GP_STATUS_1G_KX:
2649                         new_line_speed = SPEED_1000;
2650                         if (vars->duplex == DUPLEX_FULL)
2651                                 vars->link_status |= LINK_1000TFD;
2652                         else
2653                                 vars->link_status |= LINK_1000THD;
2654                         break;
2655
2656                 case GP_STATUS_2_5G:
2657                         new_line_speed = SPEED_2500;
2658                         if (vars->duplex == DUPLEX_FULL)
2659                                 vars->link_status |= LINK_2500TFD;
2660                         else
2661                                 vars->link_status |= LINK_2500THD;
2662                         break;
2663
2664                 case GP_STATUS_5G:
2665                 case GP_STATUS_6G:
2666                         DP(NETIF_MSG_LINK,
2667                                  "link speed unsupported  gp_status 0x%x\n",
2668                                   gp_status);
2669                         return -EINVAL;
2670
2671                 case GP_STATUS_10G_KX4:
2672                 case GP_STATUS_10G_HIG:
2673                 case GP_STATUS_10G_CX4:
2674                         new_line_speed = SPEED_10000;
2675                         vars->link_status |= LINK_10GTFD;
2676                         break;
2677
2678                 case GP_STATUS_12G_HIG:
2679                         new_line_speed = SPEED_12000;
2680                         vars->link_status |= LINK_12GTFD;
2681                         break;
2682
2683                 case GP_STATUS_12_5G:
2684                         new_line_speed = SPEED_12500;
2685                         vars->link_status |= LINK_12_5GTFD;
2686                         break;
2687
2688                 case GP_STATUS_13G:
2689                         new_line_speed = SPEED_13000;
2690                         vars->link_status |= LINK_13GTFD;
2691                         break;
2692
2693                 case GP_STATUS_15G:
2694                         new_line_speed = SPEED_15000;
2695                         vars->link_status |= LINK_15GTFD;
2696                         break;
2697
2698                 case GP_STATUS_16G:
2699                         new_line_speed = SPEED_16000;
2700                         vars->link_status |= LINK_16GTFD;
2701                         break;
2702
2703                 default:
2704                         DP(NETIF_MSG_LINK,
2705                                   "link speed unsupported gp_status 0x%x\n",
2706                                   gp_status);
2707                         return -EINVAL;
2708                 }
2709
2710                 vars->line_speed = new_line_speed;
2711
2712         } else { /* link_down */
2713                 DP(NETIF_MSG_LINK, "phy link down\n");
2714
2715                 vars->phy_link_up = 0;
2716
2717                 vars->duplex = DUPLEX_FULL;
2718                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2719                 vars->mac_type = MAC_TYPE_NONE;
2720
2721                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2722                     SINGLE_MEDIA_DIRECT(params)) {
2723                         /* Check signal is detected */
2724                         bnx2x_check_fallback_to_cl37(phy, params);
2725                 }
2726         }
2727
2728         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2729                  gp_status, vars->phy_link_up, vars->line_speed);
2730         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2731                    vars->duplex, vars->flow_ctrl, vars->link_status);
2732         return rc;
2733 }
2734
2735 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2736 {
2737         struct bnx2x *bp = params->bp;
2738         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2739         u16 lp_up2;
2740         u16 tx_driver;
2741         u16 bank;
2742
2743         /* read precomp */
2744         CL22_RD_OVER_CL45(bp, phy,
2745                           MDIO_REG_BANK_OVER_1G,
2746                           MDIO_OVER_1G_LP_UP2, &lp_up2);
2747
2748         /* bits [10:7] at lp_up2, positioned at [15:12] */
2749         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2750                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2751                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2752
2753         if (lp_up2 == 0)
2754                 return;
2755
2756         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2757               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2758                 CL22_RD_OVER_CL45(bp, phy,
2759                                   bank,
2760                                   MDIO_TX0_TX_DRIVER, &tx_driver);
2761
2762                 /* replace tx_driver bits [15:12] */
2763                 if (lp_up2 !=
2764                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2765                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2766                         tx_driver |= lp_up2;
2767                         CL22_WR_OVER_CL45(bp, phy,
2768                                           bank,
2769                                           MDIO_TX0_TX_DRIVER, tx_driver);
2770                 }
2771         }
2772 }
2773
2774 static int bnx2x_emac_program(struct link_params *params,
2775                               struct link_vars *vars)
2776 {
2777         struct bnx2x *bp = params->bp;
2778         u8 port = params->port;
2779         u16 mode = 0;
2780
2781         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2782         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2783                        EMAC_REG_EMAC_MODE,
2784                        (EMAC_MODE_25G_MODE |
2785                         EMAC_MODE_PORT_MII_10M |
2786                         EMAC_MODE_HALF_DUPLEX));
2787         switch (vars->line_speed) {
2788         case SPEED_10:
2789                 mode |= EMAC_MODE_PORT_MII_10M;
2790                 break;
2791
2792         case SPEED_100:
2793                 mode |= EMAC_MODE_PORT_MII;
2794                 break;
2795
2796         case SPEED_1000:
2797                 mode |= EMAC_MODE_PORT_GMII;
2798                 break;
2799
2800         case SPEED_2500:
2801                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2802                 break;
2803
2804         default:
2805                 /* 10G not valid for EMAC */
2806                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2807                            vars->line_speed);
2808                 return -EINVAL;
2809         }
2810
2811         if (vars->duplex == DUPLEX_HALF)
2812                 mode |= EMAC_MODE_HALF_DUPLEX;
2813         bnx2x_bits_en(bp,
2814                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2815                       mode);
2816
2817         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2818         return 0;
2819 }
2820
2821 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2822                                   struct link_params *params)
2823 {
2824
2825         u16 bank, i = 0;
2826         struct bnx2x *bp = params->bp;
2827
2828         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2829               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2830                         CL22_WR_OVER_CL45(bp, phy,
2831                                           bank,
2832                                           MDIO_RX0_RX_EQ_BOOST,
2833                                           phy->rx_preemphasis[i]);
2834         }
2835
2836         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2837                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2838                         CL22_WR_OVER_CL45(bp, phy,
2839                                           bank,
2840                                           MDIO_TX0_TX_DRIVER,
2841                                           phy->tx_preemphasis[i]);
2842         }
2843 }
2844
2845 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
2846                                    struct link_params *params,
2847                                    struct link_vars *vars)
2848 {
2849         struct bnx2x *bp = params->bp;
2850         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2851                           (params->loopback_mode == LOOPBACK_XGXS));
2852         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2853                 if (SINGLE_MEDIA_DIRECT(params) &&
2854                     (params->feature_config_flags &
2855                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2856                         bnx2x_set_preemphasis(phy, params);
2857
2858                 /* forced speed requested? */
2859                 if (vars->line_speed != SPEED_AUTO_NEG ||
2860                     (SINGLE_MEDIA_DIRECT(params) &&
2861                      params->loopback_mode == LOOPBACK_EXT)) {
2862                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2863
2864                         /* disable autoneg */
2865                         bnx2x_set_autoneg(phy, params, vars, 0);
2866
2867                         /* program speed and duplex */
2868                         bnx2x_program_serdes(phy, params, vars);
2869
2870                 } else { /* AN_mode */
2871                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2872
2873                         /* AN enabled */
2874                         bnx2x_set_brcm_cl37_advertisement(phy, params);
2875
2876                         /* program duplex & pause advertisement (for aneg) */
2877                         bnx2x_set_ieee_aneg_advertisement(phy, params,
2878                                                           vars->ieee_fc);
2879
2880                         /* enable autoneg */
2881                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2882
2883                         /* enable and restart AN */
2884                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2885                 }
2886
2887         } else { /* SGMII mode */
2888                 DP(NETIF_MSG_LINK, "SGMII\n");
2889
2890                 bnx2x_initialize_sgmii_process(phy, params, vars);
2891         }
2892 }
2893
2894 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
2895                           struct link_params *params,
2896                           struct link_vars *vars)
2897 {
2898         int rc;
2899         vars->phy_flags |= PHY_XGXS_FLAG;
2900         if ((phy->req_line_speed &&
2901              ((phy->req_line_speed == SPEED_100) ||
2902               (phy->req_line_speed == SPEED_10))) ||
2903             (!phy->req_line_speed &&
2904              (phy->speed_cap_mask >=
2905               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2906              (phy->speed_cap_mask <
2907               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
2908             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
2909                 vars->phy_flags |= PHY_SGMII_FLAG;
2910         else
2911                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2912
2913         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2914         bnx2x_set_aer_mmd(params, phy);
2915         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
2916                 bnx2x_set_master_ln(params, phy);
2917
2918         rc = bnx2x_reset_unicore(params, phy, 0);
2919         /* reset the SerDes and wait for reset bit return low */
2920         if (rc != 0)
2921                 return rc;
2922
2923         bnx2x_set_aer_mmd(params, phy);
2924         /* setting the masterLn_def again after the reset */
2925         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
2926                 bnx2x_set_master_ln(params, phy);
2927                 bnx2x_set_swap_lanes(params, phy);
2928         }
2929
2930         return rc;
2931 }
2932
2933 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2934                                      struct bnx2x_phy *phy,
2935                                      struct link_params *params)
2936 {
2937         u16 cnt, ctrl;
2938         /* Wait for soft reset to get cleared up to 1 sec */
2939         for (cnt = 0; cnt < 1000; cnt++) {
2940                 bnx2x_cl45_read(bp, phy,
2941                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2942                 if (!(ctrl & (1<<15)))
2943                         break;
2944                 msleep(1);
2945         }
2946
2947         if (cnt == 1000)
2948                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
2949                                       " Port %d\n",
2950                          params->port);
2951         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2952         return cnt;
2953 }
2954
2955 static void bnx2x_link_int_enable(struct link_params *params)
2956 {
2957         u8 port = params->port;
2958         u32 mask;
2959         struct bnx2x *bp = params->bp;
2960
2961         /* Setting the status to report on link up for either XGXS or SerDes */
2962         if (params->switch_cfg == SWITCH_CFG_10G) {
2963                 mask = (NIG_MASK_XGXS0_LINK10G |
2964                         NIG_MASK_XGXS0_LINK_STATUS);
2965                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2966                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2967                         params->phy[INT_PHY].type !=
2968                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2969                         mask |= NIG_MASK_MI_INT;
2970                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2971                 }
2972
2973         } else { /* SerDes */
2974                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2975                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2976                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2977                         params->phy[INT_PHY].type !=
2978                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2979                         mask |= NIG_MASK_MI_INT;
2980                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2981                 }
2982         }
2983         bnx2x_bits_en(bp,
2984                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2985                       mask);
2986
2987         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2988                  (params->switch_cfg == SWITCH_CFG_10G),
2989                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2990         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2991                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2992                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2993                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2994         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2995            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2996            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2997 }
2998
2999 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
3000                                      u8 exp_mi_int)
3001 {
3002         u32 latch_status = 0;
3003
3004         /*
3005          * Disable the MI INT ( external phy int ) by writing 1 to the
3006          * status register. Link down indication is high-active-signal,
3007          * so in this case we need to write the status to clear the XOR
3008          */
3009         /* Read Latched signals */
3010         latch_status = REG_RD(bp,
3011                                     NIG_REG_LATCH_STATUS_0 + port*8);
3012         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
3013         /* Handle only those with latched-signal=up.*/
3014         if (exp_mi_int)
3015                 bnx2x_bits_en(bp,
3016                               NIG_REG_STATUS_INTERRUPT_PORT0
3017                               + port*4,
3018                               NIG_STATUS_EMAC0_MI_INT);
3019         else
3020                 bnx2x_bits_dis(bp,
3021                                NIG_REG_STATUS_INTERRUPT_PORT0
3022                                + port*4,
3023                                NIG_STATUS_EMAC0_MI_INT);
3024
3025         if (latch_status & 1) {
3026
3027                 /* For all latched-signal=up : Re-Arm Latch signals */
3028                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
3029                        (latch_status & 0xfffe) | (latch_status & 1));
3030         }
3031         /* For all latched-signal=up,Write original_signal to status */
3032 }
3033
3034 static void bnx2x_link_int_ack(struct link_params *params,
3035                                struct link_vars *vars, u8 is_10g)
3036 {
3037         struct bnx2x *bp = params->bp;
3038         u8 port = params->port;
3039
3040         /*
3041          * First reset all status we assume only one line will be
3042          * change at a time
3043          */
3044         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3045                        (NIG_STATUS_XGXS0_LINK10G |
3046                         NIG_STATUS_XGXS0_LINK_STATUS |
3047                         NIG_STATUS_SERDES0_LINK_STATUS));
3048         if (vars->phy_link_up) {
3049                 if (is_10g) {
3050                         /*
3051                          * Disable the 10G link interrupt by writing 1 to the
3052                          * status register
3053                          */
3054                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
3055                         bnx2x_bits_en(bp,
3056                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3057                                       NIG_STATUS_XGXS0_LINK10G);
3058
3059                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
3060                         /*
3061                          * Disable the link interrupt by writing 1 to the
3062                          * relevant lane in the status register
3063                          */
3064                         u32 ser_lane = ((params->lane_config &
3065                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3066                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3067
3068                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
3069                                  vars->line_speed);
3070                         bnx2x_bits_en(bp,
3071                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3072                                       ((1 << ser_lane) <<
3073                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
3074
3075                 } else { /* SerDes */
3076                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
3077                         /*
3078                          * Disable the link interrupt by writing 1 to the status
3079                          * register
3080                          */
3081                         bnx2x_bits_en(bp,
3082                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3083                                       NIG_STATUS_SERDES0_LINK_STATUS);
3084                 }
3085
3086         }
3087 }
3088
3089 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
3090 {
3091         u8 *str_ptr = str;
3092         u32 mask = 0xf0000000;
3093         u8 shift = 8*4;
3094         u8 digit;
3095         u8 remove_leading_zeros = 1;
3096         if (*len < 10) {
3097                 /* Need more than 10chars for this format */
3098                 *str_ptr = '\0';
3099                 (*len)--;
3100                 return -EINVAL;
3101         }
3102         while (shift > 0) {
3103
3104                 shift -= 4;
3105                 digit = ((num & mask) >> shift);
3106                 if (digit == 0 && remove_leading_zeros) {
3107                         mask = mask >> 4;
3108                         continue;
3109                 } else if (digit < 0xa)
3110                         *str_ptr = digit + '0';
3111                 else
3112                         *str_ptr = digit - 0xa + 'a';
3113                 remove_leading_zeros = 0;
3114                 str_ptr++;
3115                 (*len)--;
3116                 mask = mask >> 4;
3117                 if (shift == 4*4) {
3118                         *str_ptr = '.';
3119                         str_ptr++;
3120                         (*len)--;
3121                         remove_leading_zeros = 1;
3122                 }
3123         }
3124         return 0;
3125 }
3126
3127
3128 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3129 {
3130         str[0] = '\0';
3131         (*len)--;
3132         return 0;
3133 }
3134
3135 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3136                                  u8 *version, u16 len)
3137 {
3138         struct bnx2x *bp;
3139         u32 spirom_ver = 0;
3140         int status = 0;
3141         u8 *ver_p = version;
3142         u16 remain_len = len;
3143         if (version == NULL || params == NULL)
3144                 return -EINVAL;
3145         bp = params->bp;
3146
3147         /* Extract first external phy*/
3148         version[0] = '\0';
3149         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3150
3151         if (params->phy[EXT_PHY1].format_fw_ver) {
3152                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3153                                                               ver_p,
3154                                                               &remain_len);
3155                 ver_p += (len - remain_len);
3156         }
3157         if ((params->num_phys == MAX_PHYS) &&
3158             (params->phy[EXT_PHY2].ver_addr != 0)) {
3159                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3160                 if (params->phy[EXT_PHY2].format_fw_ver) {
3161                         *ver_p = '/';
3162                         ver_p++;
3163                         remain_len--;
3164                         status |= params->phy[EXT_PHY2].format_fw_ver(
3165                                 spirom_ver,
3166                                 ver_p,
3167                                 &remain_len);
3168                         ver_p = version + (len - remain_len);
3169                 }
3170         }
3171         *ver_p = '\0';
3172         return status;
3173 }
3174
3175 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3176                                     struct link_params *params)
3177 {
3178         u8 port = params->port;
3179         struct bnx2x *bp = params->bp;
3180
3181         if (phy->req_line_speed != SPEED_1000) {
3182                 u32 md_devad;
3183
3184                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3185
3186                 /* change the uni_phy_addr in the nig */
3187                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3188                                        port*0x18));
3189
3190                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3191
3192                 bnx2x_cl45_write(bp, phy,
3193                                  5,
3194                                  (MDIO_REG_BANK_AER_BLOCK +
3195                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
3196                                  0x2800);
3197
3198                 bnx2x_cl45_write(bp, phy,
3199                                  5,
3200                                  (MDIO_REG_BANK_CL73_IEEEB0 +
3201                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3202                                  0x6041);
3203                 msleep(200);
3204                 /* set aer mmd back */
3205                 bnx2x_set_aer_mmd(params, phy);
3206
3207                 /* and md_devad */
3208                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3209         } else {
3210                 u16 mii_ctrl;
3211                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3212                 bnx2x_cl45_read(bp, phy, 5,
3213                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3214                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3215                                 &mii_ctrl);
3216                 bnx2x_cl45_write(bp, phy, 5,
3217                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3218                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3219                                  mii_ctrl |
3220                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3221         }
3222 }
3223
3224 int bnx2x_set_led(struct link_params *params,
3225                   struct link_vars *vars, u8 mode, u32 speed)
3226 {
3227         u8 port = params->port;
3228         u16 hw_led_mode = params->hw_led_mode;
3229         int rc = 0;
3230         u8 phy_idx;
3231         u32 tmp;
3232         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3233         struct bnx2x *bp = params->bp;
3234         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3235         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3236                  speed, hw_led_mode);
3237         /* In case */
3238         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3239                 if (params->phy[phy_idx].set_link_led) {
3240                         params->phy[phy_idx].set_link_led(
3241                                 &params->phy[phy_idx], params, mode);
3242                 }
3243         }
3244
3245         switch (mode) {
3246         case LED_MODE_FRONT_PANEL_OFF:
3247         case LED_MODE_OFF:
3248                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3249                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3250                        SHARED_HW_CFG_LED_MAC1);
3251
3252                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3253                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3254                 break;
3255
3256         case LED_MODE_OPER:
3257                 /*
3258                  * For all other phys, OPER mode is same as ON, so in case
3259                  * link is down, do nothing
3260                  */
3261                 if (!vars->link_up)
3262                         break;
3263         case LED_MODE_ON:
3264                 if (((params->phy[EXT_PHY1].type ==
3265                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3266                          (params->phy[EXT_PHY1].type ==
3267                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
3268                     CHIP_IS_E2(bp) && params->num_phys == 2) {
3269                         /*
3270                          * This is a work-around for E2+8727 Configurations
3271                          */
3272                         if (mode == LED_MODE_ON ||
3273                                 speed == SPEED_10000){
3274                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3275                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3276
3277                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3278                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3279                                         (tmp | EMAC_LED_OVERRIDE));
3280                                 return rc;
3281                         }
3282                 } else if (SINGLE_MEDIA_DIRECT(params)) {
3283                         /*
3284                          * This is a work-around for HW issue found when link
3285                          * is up in CL73
3286                          */
3287                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3288                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3289                 } else {
3290                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3291                 }
3292
3293                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3294                 /* Set blinking rate to ~15.9Hz */
3295                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3296                        LED_BLINK_RATE_VAL);
3297                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3298                        port*4, 1);
3299                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3300                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3301
3302                 if (CHIP_IS_E1(bp) &&
3303                     ((speed == SPEED_2500) ||
3304                      (speed == SPEED_1000) ||
3305                      (speed == SPEED_100) ||
3306                      (speed == SPEED_10))) {
3307                         /*
3308                          * On Everest 1 Ax chip versions for speeds less than
3309                          * 10G LED scheme is different
3310                          */
3311                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3312                                + port*4, 1);
3313                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3314                                port*4, 0);
3315                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3316                                port*4, 1);
3317                 }
3318                 break;
3319
3320         default:
3321                 rc = -EINVAL;
3322                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3323                          mode);
3324                 break;
3325         }
3326         return rc;
3327
3328 }
3329
3330 /*
3331  * This function comes to reflect the actual link state read DIRECTLY from the
3332  * HW
3333  */
3334 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3335                     u8 is_serdes)
3336 {
3337         struct bnx2x *bp = params->bp;
3338         u16 gp_status = 0, phy_index = 0;
3339         u8 ext_phy_link_up = 0, serdes_phy_type;
3340         struct link_vars temp_vars;
3341
3342         CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3343                           MDIO_REG_BANK_GP_STATUS,
3344                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3345                           &gp_status);
3346         /* link is up only if both local phy and external phy are up */
3347         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3348                 return -ESRCH;
3349
3350         switch (params->num_phys) {
3351         case 1:
3352                 /* No external PHY */
3353                 return 0;
3354         case 2:
3355                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3356                         &params->phy[EXT_PHY1],
3357                         params, &temp_vars);
3358                 break;
3359         case 3: /* Dual Media */
3360                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3361                       phy_index++) {
3362                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3363                                             ETH_PHY_SFP_FIBER) ||
3364                                            (params->phy[phy_index].media_type ==
3365                                             ETH_PHY_XFP_FIBER) ||
3366                                            (params->phy[phy_index].media_type ==
3367                                             ETH_PHY_DA_TWINAX));
3368
3369                         if (is_serdes != serdes_phy_type)
3370                                 continue;
3371                         if (params->phy[phy_index].read_status) {
3372                                 ext_phy_link_up |=
3373                                         params->phy[phy_index].read_status(
3374                                                 &params->phy[phy_index],
3375                                                 params, &temp_vars);
3376                         }
3377                 }
3378                 break;
3379         }
3380         if (ext_phy_link_up)
3381                 return 0;
3382         return -ESRCH;
3383 }
3384
3385 static int bnx2x_link_initialize(struct link_params *params,
3386                                  struct link_vars *vars)
3387 {
3388         int rc = 0;
3389         u8 phy_index, non_ext_phy;
3390         struct bnx2x *bp = params->bp;
3391         /*
3392          * In case of external phy existence, the line speed would be the
3393          * line speed linked up by the external phy. In case it is direct
3394          * only, then the line_speed during initialization will be
3395          * equal to the req_line_speed
3396          */
3397         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3398
3399         /*
3400          * Initialize the internal phy in case this is a direct board
3401          * (no external phys), or this board has external phy which requires
3402          * to first.
3403          */
3404
3405         bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
3406         /* init ext phy and enable link state int */
3407         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3408                        (params->loopback_mode == LOOPBACK_XGXS));
3409
3410         if (non_ext_phy ||
3411             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3412             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3413                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3414                 if (vars->line_speed == SPEED_AUTO_NEG)
3415                         bnx2x_set_parallel_detection(phy, params);
3416                         if (params->phy[INT_PHY].config_init)
3417                                 params->phy[INT_PHY].config_init(phy,
3418                                                                  params,
3419                                                                  vars);
3420         }
3421
3422         /* Init external phy*/
3423         if (non_ext_phy) {
3424                 if (params->phy[INT_PHY].supported &
3425                     SUPPORTED_FIBRE)
3426                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3427         } else {
3428                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3429                       phy_index++) {
3430                         /*
3431                          * No need to initialize second phy in case of first
3432                          * phy only selection. In case of second phy, we do
3433                          * need to initialize the first phy, since they are
3434                          * connected.
3435                          */
3436                         if (params->phy[phy_index].supported &
3437                             SUPPORTED_FIBRE)
3438                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
3439
3440                         if (phy_index == EXT_PHY2 &&
3441                             (bnx2x_phy_selection(params) ==
3442                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3443                                 DP(NETIF_MSG_LINK, "Not initializing"
3444                                                 " second phy\n");
3445                                 continue;
3446                         }
3447                         params->phy[phy_index].config_init(
3448                                 &params->phy[phy_index],
3449                                 params, vars);
3450                 }
3451         }
3452         /* Reset the interrupt indication after phy was initialized */
3453         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3454                        params->port*4,
3455                        (NIG_STATUS_XGXS0_LINK10G |
3456                         NIG_STATUS_XGXS0_LINK_STATUS |
3457                         NIG_STATUS_SERDES0_LINK_STATUS |
3458                         NIG_MASK_MI_INT));
3459         bnx2x_update_mng(params, vars->link_status);
3460         return rc;
3461 }
3462
3463 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3464                                  struct link_params *params)
3465 {
3466         /* reset the SerDes/XGXS */
3467         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3468                (0x1ff << (params->port*16)));
3469 }
3470
3471 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3472                                         struct link_params *params)
3473 {
3474         struct bnx2x *bp = params->bp;
3475         u8 gpio_port;
3476         /* HW reset */
3477         if (CHIP_IS_E2(bp))
3478                 gpio_port = BP_PATH(bp);
3479         else
3480                 gpio_port = params->port;
3481         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3482                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3483                        gpio_port);
3484         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3485                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3486                        gpio_port);
3487         DP(NETIF_MSG_LINK, "reset external PHY\n");
3488 }
3489
3490 static int bnx2x_update_link_down(struct link_params *params,
3491                                   struct link_vars *vars)
3492 {
3493         struct bnx2x *bp = params->bp;
3494         u8 port = params->port;
3495
3496         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3497         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3498
3499         /* indicate no mac active */
3500         vars->mac_type = MAC_TYPE_NONE;
3501
3502         /* update shared memory */
3503         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
3504                                LINK_STATUS_LINK_UP |
3505                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
3506                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
3507                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
3508                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
3509         vars->line_speed = 0;
3510         bnx2x_update_mng(params, vars->link_status);
3511
3512         /* activate nig drain */
3513         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3514
3515         /* disable emac */
3516         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3517
3518         msleep(10);
3519
3520         /* reset BigMac */
3521         bnx2x_bmac_rx_disable(bp, params->port);
3522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3523                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3524         return 0;
3525 }
3526
3527 static int bnx2x_update_link_up(struct link_params *params,
3528                                 struct link_vars *vars,
3529                                 u8 link_10g)
3530 {
3531         struct bnx2x *bp = params->bp;
3532         u8 port = params->port;
3533         int rc = 0;
3534
3535         vars->link_status |= LINK_STATUS_LINK_UP;
3536
3537         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3538                 vars->link_status |=
3539                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3540
3541         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3542                 vars->link_status |=
3543                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3544
3545         if (link_10g) {
3546                 bnx2x_bmac_enable(params, vars, 0);
3547                 bnx2x_set_led(params, vars,
3548                               LED_MODE_OPER, SPEED_10000);
3549         } else {
3550                 rc = bnx2x_emac_program(params, vars);
3551
3552                 bnx2x_emac_enable(params, vars, 0);
3553
3554                 /* AN complete? */
3555                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3556                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3557                     SINGLE_MEDIA_DIRECT(params))
3558                         bnx2x_set_gmii_tx_driver(params);
3559         }
3560
3561         /* PBF - link up */
3562         if (!(CHIP_IS_E2(bp)))
3563                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3564                                        vars->line_speed);
3565
3566         /* disable drain */
3567         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3568
3569         /* update shared memory */
3570         bnx2x_update_mng(params, vars->link_status);
3571         msleep(20);
3572         return rc;
3573 }
3574 /*
3575  * The bnx2x_link_update function should be called upon link
3576  * interrupt.
3577  * Link is considered up as follows:
3578  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3579  *   to be up
3580  * - SINGLE_MEDIA - The link between the 577xx and the external
3581  *   phy (XGXS) need to up as well as the external link of the
3582  *   phy (PHY_EXT1)
3583  * - DUAL_MEDIA - The link between the 577xx and the first
3584  *   external phy needs to be up, and at least one of the 2
3585  *   external phy link must be up.
3586  */
3587 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3588 {
3589         struct bnx2x *bp = params->bp;
3590         struct link_vars phy_vars[MAX_PHYS];
3591         u8 port = params->port;
3592         u8 link_10g, phy_index;
3593         u8 ext_phy_link_up = 0, cur_link_up;
3594         int rc = 0;
3595         u8 is_mi_int = 0;
3596         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3597         u8 active_external_phy = INT_PHY;
3598
3599         for (phy_index = INT_PHY; phy_index < params->num_phys;
3600               phy_index++) {
3601                 phy_vars[phy_index].flow_ctrl = 0;
3602                 phy_vars[phy_index].link_status = 0;
3603                 phy_vars[phy_index].line_speed = 0;
3604                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3605                 phy_vars[phy_index].phy_link_up = 0;
3606                 phy_vars[phy_index].link_up = 0;
3607                 phy_vars[phy_index].fault_detected = 0;
3608         }
3609
3610         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3611                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3612                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3613
3614         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3615                                 port*0x18) > 0);
3616         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3617                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3618                  is_mi_int,
3619                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3620
3621         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3622           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3623           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3624
3625         /* disable emac */
3626         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3627
3628         /*
3629          * Step 1:
3630          * Check external link change only for external phys, and apply
3631          * priority selection between them in case the link on both phys
3632          * is up. Note that instead of the common vars, a temporary
3633          * vars argument is used since each phy may have different link/
3634          * speed/duplex result
3635          */
3636         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3637               phy_index++) {
3638                 struct bnx2x_phy *phy = &params->phy[phy_index];
3639                 if (!phy->read_status)
3640                         continue;
3641                 /* Read link status and params of this ext phy */
3642                 cur_link_up = phy->read_status(phy, params,
3643                                                &phy_vars[phy_index]);
3644                 if (cur_link_up) {
3645                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3646                                    phy_index);
3647                 } else {
3648                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3649                                    phy_index);
3650                         continue;
3651                 }
3652
3653                 if (!ext_phy_link_up) {
3654                         ext_phy_link_up = 1;
3655                         active_external_phy = phy_index;
3656                 } else {
3657                         switch (bnx2x_phy_selection(params)) {
3658                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3659                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3660                         /*
3661                          * In this option, the first PHY makes sure to pass the
3662                          * traffic through itself only.
3663                          * Its not clear how to reset the link on the second phy
3664                          */
3665                                 active_external_phy = EXT_PHY1;
3666                                 break;
3667                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3668                         /*
3669                          * In this option, the first PHY makes sure to pass the
3670                          * traffic through the second PHY.
3671                          */
3672                                 active_external_phy = EXT_PHY2;
3673                                 break;
3674                         default:
3675                         /*
3676                          * Link indication on both PHYs with the following cases
3677                          * is invalid:
3678                          * - FIRST_PHY means that second phy wasn't initialized,
3679                          * hence its link is expected to be down
3680                          * - SECOND_PHY means that first phy should not be able
3681                          * to link up by itself (using configuration)
3682                          * - DEFAULT should be overriden during initialiazation
3683                          */
3684                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3685                                            "mpc=0x%x. DISABLING LINK !!!\n",
3686                                            params->multi_phy_config);
3687                                 ext_phy_link_up = 0;
3688                                 break;
3689                         }
3690                 }
3691         }
3692         prev_line_speed = vars->line_speed;
3693         /*
3694          * Step 2:
3695          * Read the status of the internal phy. In case of
3696          * DIRECT_SINGLE_MEDIA board, this link is the external link,
3697          * otherwise this is the link between the 577xx and the first
3698          * external phy
3699          */
3700         if (params->phy[INT_PHY].read_status)
3701                 params->phy[INT_PHY].read_status(
3702                         &params->phy[INT_PHY],
3703                         params, vars);
3704         /*
3705          * The INT_PHY flow control reside in the vars. This include the
3706          * case where the speed or flow control are not set to AUTO.
3707          * Otherwise, the active external phy flow control result is set
3708          * to the vars. The ext_phy_line_speed is needed to check if the
3709          * speed is different between the internal phy and external phy.
3710          * This case may be result of intermediate link speed change.
3711          */
3712         if (active_external_phy > INT_PHY) {
3713                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3714                 /*
3715                  * Link speed is taken from the XGXS. AN and FC result from
3716                  * the external phy.
3717                  */
3718                 vars->link_status |= phy_vars[active_external_phy].link_status;
3719
3720                 /*
3721                  * if active_external_phy is first PHY and link is up - disable
3722                  * disable TX on second external PHY
3723                  */
3724                 if (active_external_phy == EXT_PHY1) {
3725                         if (params->phy[EXT_PHY2].phy_specific_func) {
3726                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3727                                                    " EXT_PHY2\n");
3728                                 params->phy[EXT_PHY2].phy_specific_func(
3729                                         &params->phy[EXT_PHY2],
3730                                         params, DISABLE_TX);
3731                         }
3732                 }
3733
3734                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3735                 vars->duplex = phy_vars[active_external_phy].duplex;
3736                 if (params->phy[active_external_phy].supported &
3737                     SUPPORTED_FIBRE)
3738                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3739                 else
3740                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
3741                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3742                            active_external_phy);
3743         }
3744
3745         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3746               phy_index++) {
3747                 if (params->phy[phy_index].flags &
3748                     FLAGS_REARM_LATCH_SIGNAL) {
3749                         bnx2x_rearm_latch_signal(bp, port,
3750                                                  phy_index ==
3751                                                  active_external_phy);
3752                         break;
3753                 }
3754         }
3755         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3756                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3757                    vars->link_status, ext_phy_line_speed);
3758         /*
3759          * Upon link speed change set the NIG into drain mode. Comes to
3760          * deals with possible FIFO glitch due to clk change when speed
3761          * is decreased without link down indicator
3762          */
3763
3764         if (vars->phy_link_up) {
3765                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3766                     (ext_phy_line_speed != vars->line_speed)) {
3767                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3768                                    " different than the external"
3769                                    " link speed %d\n", vars->line_speed,
3770                                    ext_phy_line_speed);
3771                         vars->phy_link_up = 0;
3772                 } else if (prev_line_speed != vars->line_speed) {
3773                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3774                                0);
3775                         msleep(1);
3776                 }
3777         }
3778
3779         /* anything 10 and over uses the bmac */
3780         link_10g = ((vars->line_speed == SPEED_10000) ||
3781                     (vars->line_speed == SPEED_12000) ||
3782                     (vars->line_speed == SPEED_12500) ||
3783                     (vars->line_speed == SPEED_13000) ||
3784                     (vars->line_speed == SPEED_15000) ||
3785                     (vars->line_speed == SPEED_16000));
3786
3787         bnx2x_link_int_ack(params, vars, link_10g);
3788
3789         /*
3790          * In case external phy link is up, and internal link is down
3791          * (not initialized yet probably after link initialization, it
3792          * needs to be initialized.
3793          * Note that after link down-up as result of cable plug, the xgxs
3794          * link would probably become up again without the need
3795          * initialize it
3796          */
3797         if (!(SINGLE_MEDIA_DIRECT(params))) {
3798                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3799                            " init_preceding = %d\n", ext_phy_link_up,
3800                            vars->phy_link_up,
3801                            params->phy[EXT_PHY1].flags &
3802                            FLAGS_INIT_XGXS_FIRST);
3803                 if (!(params->phy[EXT_PHY1].flags &
3804                       FLAGS_INIT_XGXS_FIRST)
3805                     && ext_phy_link_up && !vars->phy_link_up) {
3806                         vars->line_speed = ext_phy_line_speed;
3807                         if (vars->line_speed < SPEED_1000)
3808                                 vars->phy_flags |= PHY_SGMII_FLAG;
3809                         else
3810                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3811
3812                         if (params->phy[INT_PHY].config_init)
3813                                 params->phy[INT_PHY].config_init(
3814                                         &params->phy[INT_PHY], params,
3815                                                 vars);
3816                 }
3817         }
3818         /*
3819          * Link is up only if both local phy and external phy (in case of
3820          * non-direct board) are up and no fault detected on active PHY.
3821          */
3822         vars->link_up = (vars->phy_link_up &&
3823                          (ext_phy_link_up ||
3824                           SINGLE_MEDIA_DIRECT(params)) &&
3825                          (phy_vars[active_external_phy].fault_detected == 0));
3826
3827         if (vars->link_up)
3828                 rc = bnx2x_update_link_up(params, vars, link_10g);
3829         else
3830                 rc = bnx2x_update_link_down(params, vars);
3831
3832         return rc;
3833 }
3834
3835
3836 /*****************************************************************************/
3837 /*                          External Phy section                             */
3838 /*****************************************************************************/
3839 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3840 {
3841         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3842                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3843         msleep(1);
3844         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3845                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3846 }
3847
3848 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3849                                       u32 spirom_ver, u32 ver_addr)
3850 {
3851         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3852                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3853
3854         if (ver_addr)
3855                 REG_WR(bp, ver_addr, spirom_ver);
3856 }
3857
3858 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3859                                       struct bnx2x_phy *phy,
3860                                       u8 port)
3861 {
3862         u16 fw_ver1, fw_ver2;
3863
3864         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3865                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3866         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3867                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3868         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3869                                   phy->ver_addr);
3870 }
3871
3872 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3873                                        struct bnx2x_phy *phy,
3874                                        struct link_vars *vars)
3875 {
3876         u16 val;
3877         bnx2x_cl45_read(bp, phy,
3878                         MDIO_AN_DEVAD,
3879                         MDIO_AN_REG_STATUS, &val);
3880         bnx2x_cl45_read(bp, phy,
3881                         MDIO_AN_DEVAD,
3882                         MDIO_AN_REG_STATUS, &val);
3883         if (val & (1<<5))
3884                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3885         if ((val & (1<<0)) == 0)
3886                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3887 }
3888
3889 /******************************************************************/
3890 /*              common BCM8073/BCM8727 PHY SECTION                */
3891 /******************************************************************/
3892 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3893                                   struct link_params *params,
3894                                   struct link_vars *vars)
3895 {
3896         struct bnx2x *bp = params->bp;
3897         if (phy->req_line_speed == SPEED_10 ||
3898             phy->req_line_speed == SPEED_100) {
3899                 vars->flow_ctrl = phy->req_flow_ctrl;
3900                 return;
3901         }
3902
3903         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3904             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3905                 u16 pause_result;
3906                 u16 ld_pause;           /* local */
3907                 u16 lp_pause;           /* link partner */
3908                 bnx2x_cl45_read(bp, phy,
3909                                 MDIO_AN_DEVAD,
3910                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3911
3912                 bnx2x_cl45_read(bp, phy,
3913                                 MDIO_AN_DEVAD,
3914                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3915                 pause_result = (ld_pause &
3916                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3917                 pause_result |= (lp_pause &
3918                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3919
3920                 bnx2x_pause_resolve(vars, pause_result);
3921                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3922                            pause_result);
3923         }
3924 }
3925 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3926                                              struct bnx2x_phy *phy,
3927                                              u8 port)
3928 {
3929         u32 count = 0;
3930         u16 fw_ver1, fw_msgout;
3931         int rc = 0;
3932
3933         /* Boot port from external ROM  */
3934         /* EDC grst */
3935         bnx2x_cl45_write(bp, phy,
3936                          MDIO_PMA_DEVAD,
3937                          MDIO_PMA_REG_GEN_CTRL,
3938                          0x0001);
3939
3940         /* ucode reboot and rst */
3941         bnx2x_cl45_write(bp, phy,
3942                          MDIO_PMA_DEVAD,
3943                          MDIO_PMA_REG_GEN_CTRL,
3944                          0x008c);
3945
3946         bnx2x_cl45_write(bp, phy,
3947                          MDIO_PMA_DEVAD,
3948                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3949
3950         /* Reset internal microprocessor */
3951         bnx2x_cl45_write(bp, phy,
3952                          MDIO_PMA_DEVAD,
3953                          MDIO_PMA_REG_GEN_CTRL,
3954                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3955
3956         /* Release srst bit */
3957         bnx2x_cl45_write(bp, phy,
3958                          MDIO_PMA_DEVAD,
3959                          MDIO_PMA_REG_GEN_CTRL,
3960                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3961
3962         /* Delay 100ms per the PHY specifications */
3963         msleep(100);
3964
3965         /* 8073 sometimes taking longer to download */
3966         do {
3967                 count++;
3968                 if (count > 300) {
3969                         DP(NETIF_MSG_LINK,
3970                                  "bnx2x_8073_8727_external_rom_boot port %x:"
3971                                  "Download failed. fw version = 0x%x\n",
3972                                  port, fw_ver1);
3973                         rc = -EINVAL;
3974                         break;
3975                 }
3976
3977                 bnx2x_cl45_read(bp, phy,
3978                                 MDIO_PMA_DEVAD,
3979                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3980                 bnx2x_cl45_read(bp, phy,
3981                                 MDIO_PMA_DEVAD,
3982                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3983
3984                 msleep(1);
3985         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3986                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3987                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3988
3989         /* Clear ser_boot_ctl bit */
3990         bnx2x_cl45_write(bp, phy,
3991                          MDIO_PMA_DEVAD,
3992                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3993         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3994
3995         DP(NETIF_MSG_LINK,
3996                  "bnx2x_8073_8727_external_rom_boot port %x:"
3997                  "Download complete. fw version = 0x%x\n",
3998                  port, fw_ver1);
3999
4000         return rc;
4001 }
4002
4003 /******************************************************************/
4004 /*                      BCM8073 PHY SECTION                       */
4005 /******************************************************************/
4006 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
4007 {
4008         /* This is only required for 8073A1, version 102 only */
4009         u16 val;
4010
4011         /* Read 8073 HW revision*/
4012         bnx2x_cl45_read(bp, phy,
4013                         MDIO_PMA_DEVAD,
4014                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4015
4016         if (val != 1) {
4017                 /* No need to workaround in 8073 A1 */
4018                 return 0;
4019         }
4020
4021         bnx2x_cl45_read(bp, phy,
4022                         MDIO_PMA_DEVAD,
4023                         MDIO_PMA_REG_ROM_VER2, &val);
4024
4025         /* SNR should be applied only for version 0x102 */
4026         if (val != 0x102)
4027                 return 0;
4028
4029         return 1;
4030 }
4031
4032 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
4033 {
4034         u16 val, cnt, cnt1 ;
4035
4036         bnx2x_cl45_read(bp, phy,
4037                         MDIO_PMA_DEVAD,
4038                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4039
4040         if (val > 0) {
4041                 /* No need to workaround in 8073 A1 */
4042                 return 0;
4043         }
4044         /* XAUI workaround in 8073 A0: */
4045
4046         /*
4047          * After loading the boot ROM and restarting Autoneg, poll
4048          * Dev1, Reg $C820:
4049          */
4050
4051         for (cnt = 0; cnt < 1000; cnt++) {
4052                 bnx2x_cl45_read(bp, phy,
4053                                 MDIO_PMA_DEVAD,
4054                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4055                                 &val);
4056                   /*
4057                    * If bit [14] = 0 or bit [13] = 0, continue on with
4058                    * system initialization (XAUI work-around not required, as
4059                    * these bits indicate 2.5G or 1G link up).
4060                    */
4061                 if (!(val & (1<<14)) || !(val & (1<<13))) {
4062                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4063                         return 0;
4064                 } else if (!(val & (1<<15))) {
4065                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
4066                         /*
4067                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
4068                          * MSB (bit15) goes to 1 (indicating that the XAUI
4069                          * workaround has completed), then continue on with
4070                          * system initialization.
4071                          */
4072                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4073                                 bnx2x_cl45_read(bp, phy,
4074                                         MDIO_PMA_DEVAD,
4075                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4076                                 if (val & (1<<15)) {
4077                                         DP(NETIF_MSG_LINK,
4078                                           "XAUI workaround has completed\n");
4079                                         return 0;
4080                                  }
4081                                  msleep(3);
4082                         }
4083                         break;
4084                 }
4085                 msleep(3);
4086         }
4087         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4088         return -EINVAL;
4089 }
4090
4091 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4092 {
4093         /* Force KR or KX */
4094         bnx2x_cl45_write(bp, phy,
4095                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4096         bnx2x_cl45_write(bp, phy,
4097                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4098         bnx2x_cl45_write(bp, phy,
4099                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4100         bnx2x_cl45_write(bp, phy,
4101                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4102 }
4103
4104 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4105                                       struct bnx2x_phy *phy,
4106                                       struct link_vars *vars)
4107 {
4108         u16 cl37_val;
4109         struct bnx2x *bp = params->bp;
4110         bnx2x_cl45_read(bp, phy,
4111                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4112
4113         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4114         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4115         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4116         if ((vars->ieee_fc &
4117             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4118             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4119                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4120         }
4121         if ((vars->ieee_fc &
4122             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4123             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4124                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4125         }
4126         if ((vars->ieee_fc &
4127             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4128             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4129                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4130         }
4131         DP(NETIF_MSG_LINK,
4132                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4133
4134         bnx2x_cl45_write(bp, phy,
4135                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4136         msleep(500);
4137 }
4138
4139 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
4140                                   struct link_params *params,
4141                                   struct link_vars *vars)
4142 {
4143         struct bnx2x *bp = params->bp;
4144         u16 val = 0, tmp1;
4145         u8 gpio_port;
4146         DP(NETIF_MSG_LINK, "Init 8073\n");
4147
4148         if (CHIP_IS_E2(bp))
4149                 gpio_port = BP_PATH(bp);
4150         else
4151                 gpio_port = params->port;
4152         /* Restore normal power mode*/
4153         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4154                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4155
4156         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4157                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4158
4159         /* enable LASI */
4160         bnx2x_cl45_write(bp, phy,
4161                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4162         bnx2x_cl45_write(bp, phy,
4163                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4164
4165         bnx2x_8073_set_pause_cl37(params, phy, vars);
4166
4167         bnx2x_cl45_read(bp, phy,
4168                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4169
4170         bnx2x_cl45_read(bp, phy,
4171                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4172
4173         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4174
4175         /* Swap polarity if required - Must be done only in non-1G mode */
4176         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4177                 /* Configure the 8073 to swap _P and _N of the KR lines */
4178                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4179                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4180                 bnx2x_cl45_read(bp, phy,
4181                                 MDIO_PMA_DEVAD,
4182                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4183                 bnx2x_cl45_write(bp, phy,
4184                                  MDIO_PMA_DEVAD,
4185                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4186                                  (val | (3<<9)));
4187         }
4188
4189
4190         /* Enable CL37 BAM */
4191         if (REG_RD(bp, params->shmem_base +
4192                          offsetof(struct shmem_region, dev_info.
4193                                   port_hw_config[params->port].default_cfg)) &
4194             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4195
4196                 bnx2x_cl45_read(bp, phy,
4197                                 MDIO_AN_DEVAD,
4198                                 MDIO_AN_REG_8073_BAM, &val);
4199                 bnx2x_cl45_write(bp, phy,
4200                                  MDIO_AN_DEVAD,
4201                                  MDIO_AN_REG_8073_BAM, val | 1);
4202                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4203         }
4204         if (params->loopback_mode == LOOPBACK_EXT) {
4205                 bnx2x_807x_force_10G(bp, phy);
4206                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4207                 return 0;
4208         } else {
4209                 bnx2x_cl45_write(bp, phy,
4210                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4211         }
4212         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4213                 if (phy->req_line_speed == SPEED_10000) {
4214                         val = (1<<7);
4215                 } else if (phy->req_line_speed ==  SPEED_2500) {
4216                         val = (1<<5);
4217                         /*
4218                          * Note that 2.5G works only when used with 1G
4219                          * advertisement
4220                          */
4221                 } else
4222                         val = (1<<5);
4223         } else {
4224                 val = 0;
4225                 if (phy->speed_cap_mask &
4226                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4227                         val |= (1<<7);
4228
4229                 /* Note that 2.5G works only when used with 1G advertisement */
4230                 if (phy->speed_cap_mask &
4231                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4232                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4233                         val |= (1<<5);
4234                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4235         }
4236
4237         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4238         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4239
4240         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4241              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4242             (phy->req_line_speed == SPEED_2500)) {
4243                 u16 phy_ver;
4244                 /* Allow 2.5G for A1 and above */
4245                 bnx2x_cl45_read(bp, phy,
4246                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4247                                 &phy_ver);
4248                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4249                 if (phy_ver > 0)
4250                         tmp1 |= 1;
4251                 else
4252                         tmp1 &= 0xfffe;
4253         } else {
4254                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4255                 tmp1 &= 0xfffe;
4256         }
4257
4258         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4259         /* Add support for CL37 (passive mode) II */
4260
4261         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4262         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4263                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4264                                   0x20 : 0x40)));
4265
4266         /* Add support for CL37 (passive mode) III */
4267         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4268
4269         /*
4270          * The SNR will improve about 2db by changing BW and FEE main
4271          * tap. Rest commands are executed after link is up
4272          * Change FFE main cursor to 5 in EDC register
4273          */
4274         if (bnx2x_8073_is_snr_needed(bp, phy))
4275                 bnx2x_cl45_write(bp, phy,
4276                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4277                                  0xFB0C);
4278
4279         /* Enable FEC (Forware Error Correction) Request in the AN */
4280         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4281         tmp1 |= (1<<15);
4282         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4283
4284         bnx2x_ext_phy_set_pause(params, phy, vars);
4285
4286         /* Restart autoneg */
4287         msleep(500);
4288         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4289         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4290                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4291         return 0;
4292 }
4293
4294 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4295                                  struct link_params *params,
4296                                  struct link_vars *vars)
4297 {
4298         struct bnx2x *bp = params->bp;
4299         u8 link_up = 0;
4300         u16 val1, val2;
4301         u16 link_status = 0;
4302         u16 an1000_status = 0;
4303
4304         bnx2x_cl45_read(bp, phy,
4305                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4306
4307         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4308
4309         /* clear the interrupt LASI status register */
4310         bnx2x_cl45_read(bp, phy,
4311                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4312         bnx2x_cl45_read(bp, phy,
4313                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4314         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4315         /* Clear MSG-OUT */
4316         bnx2x_cl45_read(bp, phy,
4317                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4318
4319         /* Check the LASI */
4320         bnx2x_cl45_read(bp, phy,
4321                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4322
4323         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4324
4325         /* Check the link status */
4326         bnx2x_cl45_read(bp, phy,
4327                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4328         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4329
4330         bnx2x_cl45_read(bp, phy,
4331                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4332         bnx2x_cl45_read(bp, phy,
4333                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4334         link_up = ((val1 & 4) == 4);
4335         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4336
4337         if (link_up &&
4338              ((phy->req_line_speed != SPEED_10000))) {
4339                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4340                         return 0;
4341         }
4342         bnx2x_cl45_read(bp, phy,
4343                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4344         bnx2x_cl45_read(bp, phy,
4345                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4346
4347         /* Check the link status on 1.1.2 */
4348         bnx2x_cl45_read(bp, phy,
4349                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4350         bnx2x_cl45_read(bp, phy,
4351                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4352         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4353                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4354
4355         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4356         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4357                 /*
4358                  * The SNR will improve about 2dbby changing the BW and FEE main
4359                  * tap. The 1st write to change FFE main tap is set before
4360                  * restart AN. Change PLL Bandwidth in EDC register
4361                  */
4362                 bnx2x_cl45_write(bp, phy,
4363                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4364                                  0x26BC);
4365
4366                 /* Change CDR Bandwidth in EDC register */
4367                 bnx2x_cl45_write(bp, phy,
4368                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4369                                  0x0333);
4370         }
4371         bnx2x_cl45_read(bp, phy,
4372                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4373                         &link_status);
4374
4375         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4376         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4377                 link_up = 1;
4378                 vars->line_speed = SPEED_10000;
4379                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4380                            params->port);
4381         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4382                 link_up = 1;
4383                 vars->line_speed = SPEED_2500;
4384                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4385                            params->port);
4386         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4387                 link_up = 1;
4388                 vars->line_speed = SPEED_1000;
4389                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4390                            params->port);
4391         } else {
4392                 link_up = 0;
4393                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4394                            params->port);
4395         }
4396
4397         if (link_up) {
4398                 /* Swap polarity if required */
4399                 if (params->lane_config &
4400                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4401                         /* Configure the 8073 to swap P and N of the KR lines */
4402                         bnx2x_cl45_read(bp, phy,
4403                                         MDIO_XS_DEVAD,
4404                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4405                         /*
4406                          * Set bit 3 to invert Rx in 1G mode and clear this bit
4407                          * when it`s in 10G mode.
4408                          */
4409                         if (vars->line_speed == SPEED_1000) {
4410                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4411                                               "the 8073\n");
4412                                 val1 |= (1<<3);
4413                         } else
4414                                 val1 &= ~(1<<3);
4415
4416                         bnx2x_cl45_write(bp, phy,
4417                                          MDIO_XS_DEVAD,
4418                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
4419                                          val1);
4420                 }
4421                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4422                 bnx2x_8073_resolve_fc(phy, params, vars);
4423                 vars->duplex = DUPLEX_FULL;
4424         }
4425         return link_up;
4426 }
4427
4428 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4429                                   struct link_params *params)
4430 {
4431         struct bnx2x *bp = params->bp;
4432         u8 gpio_port;
4433         if (CHIP_IS_E2(bp))
4434                 gpio_port = BP_PATH(bp);
4435         else
4436                 gpio_port = params->port;
4437         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4438            gpio_port);
4439         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4440                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4441                        gpio_port);
4442 }
4443
4444 /******************************************************************/
4445 /*                      BCM8705 PHY SECTION                       */
4446 /******************************************************************/
4447 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
4448                                   struct link_params *params,
4449                                   struct link_vars *vars)
4450 {
4451         struct bnx2x *bp = params->bp;
4452         DP(NETIF_MSG_LINK, "init 8705\n");
4453         /* Restore normal power mode*/
4454         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4455                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4456         /* HW reset */
4457         bnx2x_ext_phy_hw_reset(bp, params->port);
4458         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4459         bnx2x_wait_reset_complete(bp, phy, params);
4460
4461         bnx2x_cl45_write(bp, phy,
4462                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4463         bnx2x_cl45_write(bp, phy,
4464                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4465         bnx2x_cl45_write(bp, phy,
4466                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4467         bnx2x_cl45_write(bp, phy,
4468                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4469         /* BCM8705 doesn't have microcode, hence the 0 */
4470         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4471         return 0;
4472 }
4473
4474 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4475                                  struct link_params *params,
4476                                  struct link_vars *vars)
4477 {
4478         u8 link_up = 0;
4479         u16 val1, rx_sd;
4480         struct bnx2x *bp = params->bp;
4481         DP(NETIF_MSG_LINK, "read status 8705\n");
4482         bnx2x_cl45_read(bp, phy,
4483                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4484         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4485
4486         bnx2x_cl45_read(bp, phy,
4487                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4488         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4489
4490         bnx2x_cl45_read(bp, phy,
4491                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4492
4493         bnx2x_cl45_read(bp, phy,
4494                       MDIO_PMA_DEVAD, 0xc809, &val1);
4495         bnx2x_cl45_read(bp, phy,
4496                       MDIO_PMA_DEVAD, 0xc809, &val1);
4497
4498         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4499         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4500         if (link_up) {
4501                 vars->line_speed = SPEED_10000;
4502                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4503         }
4504         return link_up;
4505 }
4506
4507 /******************************************************************/
4508 /*                      SFP+ module Section                       */
4509 /******************************************************************/
4510 static u8 bnx2x_get_gpio_port(struct link_params *params)
4511 {
4512         u8 gpio_port;
4513         u32 swap_val, swap_override;
4514         struct bnx2x *bp = params->bp;
4515         if (CHIP_IS_E2(bp))
4516                 gpio_port = BP_PATH(bp);
4517         else
4518                 gpio_port = params->port;
4519         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4520         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4521         return gpio_port ^ (swap_val && swap_override);
4522 }
4523 static void bnx2x_sfp_set_transmitter(struct link_params *params,
4524                                       struct bnx2x_phy *phy,
4525                                       u8 tx_en)
4526 {
4527         u16 val;
4528         u8 port = params->port;
4529         struct bnx2x *bp = params->bp;
4530         u32 tx_en_mode;
4531
4532         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4533         tx_en_mode = REG_RD(bp, params->shmem_base +
4534                             offsetof(struct shmem_region,
4535                                      dev_info.port_hw_config[port].sfp_ctrl)) &
4536                 PORT_HW_CFG_TX_LASER_MASK;
4537         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4538                            "mode = %x\n", tx_en, port, tx_en_mode);
4539         switch (tx_en_mode) {
4540         case PORT_HW_CFG_TX_LASER_MDIO:
4541
4542                 bnx2x_cl45_read(bp, phy,
4543                                 MDIO_PMA_DEVAD,
4544                                 MDIO_PMA_REG_PHY_IDENTIFIER,
4545                                 &val);
4546
4547                 if (tx_en)
4548                         val &= ~(1<<15);
4549                 else
4550                         val |= (1<<15);
4551
4552                 bnx2x_cl45_write(bp, phy,
4553                                  MDIO_PMA_DEVAD,
4554                                  MDIO_PMA_REG_PHY_IDENTIFIER,
4555                                  val);
4556         break;
4557         case PORT_HW_CFG_TX_LASER_GPIO0:
4558         case PORT_HW_CFG_TX_LASER_GPIO1:
4559         case PORT_HW_CFG_TX_LASER_GPIO2:
4560         case PORT_HW_CFG_TX_LASER_GPIO3:
4561         {
4562                 u16 gpio_pin;
4563                 u8 gpio_port, gpio_mode;
4564                 if (tx_en)
4565                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4566                 else
4567                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4568
4569                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4570                 gpio_port = bnx2x_get_gpio_port(params);
4571                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4572                 break;
4573         }
4574         default:
4575                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4576                 break;
4577         }
4578 }
4579
4580 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4581                                              struct link_params *params,
4582                                              u16 addr, u8 byte_cnt, u8 *o_buf)
4583 {
4584         struct bnx2x *bp = params->bp;
4585         u16 val = 0;
4586         u16 i;
4587         if (byte_cnt > 16) {
4588                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4589                             " is limited to 0xf\n");
4590                 return -EINVAL;
4591         }
4592         /* Set the read command byte count */
4593         bnx2x_cl45_write(bp, phy,
4594                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4595                          (byte_cnt | 0xa000));
4596
4597         /* Set the read command address */
4598         bnx2x_cl45_write(bp, phy,
4599                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4600                          addr);
4601
4602         /* Activate read command */
4603         bnx2x_cl45_write(bp, phy,
4604                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4605                          0x2c0f);
4606
4607         /* Wait up to 500us for command complete status */
4608         for (i = 0; i < 100; i++) {
4609                 bnx2x_cl45_read(bp, phy,
4610                                 MDIO_PMA_DEVAD,
4611                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4612                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4613                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4614                         break;
4615                 udelay(5);
4616         }
4617
4618         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4619                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4620                 DP(NETIF_MSG_LINK,
4621                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4622                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4623                 return -EINVAL;
4624         }
4625
4626         /* Read the buffer */
4627         for (i = 0; i < byte_cnt; i++) {
4628                 bnx2x_cl45_read(bp, phy,
4629                                 MDIO_PMA_DEVAD,
4630                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4631                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4632         }
4633
4634         for (i = 0; i < 100; i++) {
4635                 bnx2x_cl45_read(bp, phy,
4636                                 MDIO_PMA_DEVAD,
4637                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4638                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4639                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4640                         return 0;
4641                 msleep(1);
4642         }
4643         return -EINVAL;
4644 }
4645
4646 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4647                                              struct link_params *params,
4648                                              u16 addr, u8 byte_cnt, u8 *o_buf)
4649 {
4650         struct bnx2x *bp = params->bp;
4651         u16 val, i;
4652
4653         if (byte_cnt > 16) {
4654                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4655                             " is limited to 0xf\n");
4656                 return -EINVAL;
4657         }
4658
4659         /* Need to read from 1.8000 to clear it */
4660         bnx2x_cl45_read(bp, phy,
4661                         MDIO_PMA_DEVAD,
4662                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4663                         &val);
4664
4665         /* Set the read command byte count */
4666         bnx2x_cl45_write(bp, phy,
4667                          MDIO_PMA_DEVAD,
4668                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4669                          ((byte_cnt < 2) ? 2 : byte_cnt));
4670
4671         /* Set the read command address */
4672         bnx2x_cl45_write(bp, phy,
4673                          MDIO_PMA_DEVAD,
4674                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4675                          addr);
4676         /* Set the destination address */
4677         bnx2x_cl45_write(bp, phy,
4678                          MDIO_PMA_DEVAD,
4679                          0x8004,
4680                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4681
4682         /* Activate read command */
4683         bnx2x_cl45_write(bp, phy,
4684                          MDIO_PMA_DEVAD,
4685                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4686                          0x8002);
4687         /*
4688          * Wait appropriate time for two-wire command to finish before
4689          * polling the status register
4690          */
4691         msleep(1);
4692
4693         /* Wait up to 500us for command complete status */
4694         for (i = 0; i < 100; i++) {
4695                 bnx2x_cl45_read(bp, phy,
4696                                 MDIO_PMA_DEVAD,
4697                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4698                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4699                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4700                         break;
4701                 udelay(5);
4702         }
4703
4704         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4705                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4706                 DP(NETIF_MSG_LINK,
4707                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4708                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4709                 return -EFAULT;
4710         }
4711
4712         /* Read the buffer */
4713         for (i = 0; i < byte_cnt; i++) {
4714                 bnx2x_cl45_read(bp, phy,
4715                                 MDIO_PMA_DEVAD,
4716                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4717                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4718         }
4719
4720         for (i = 0; i < 100; i++) {
4721                 bnx2x_cl45_read(bp, phy,
4722                                 MDIO_PMA_DEVAD,
4723                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4724                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4725                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4726                         return 0;
4727                 msleep(1);
4728         }
4729
4730         return -EINVAL;
4731 }
4732
4733 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4734                                  struct link_params *params, u16 addr,
4735                                  u8 byte_cnt, u8 *o_buf)
4736 {
4737         int rc = -EINVAL;
4738         switch (phy->type) {
4739         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4740                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4741                                                        byte_cnt, o_buf);
4742         break;
4743         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4744         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4745                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4746                                                        byte_cnt, o_buf);
4747         break;
4748         }
4749         return rc;
4750 }
4751
4752 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4753                               struct link_params *params,
4754                               u16 *edc_mode)
4755 {
4756         struct bnx2x *bp = params->bp;
4757         u32 sync_offset = 0, phy_idx, media_types;
4758         u8 val, check_limiting_mode = 0;
4759         *edc_mode = EDC_MODE_LIMITING;
4760
4761         phy->media_type = ETH_PHY_UNSPECIFIED;
4762         /* First check for copper cable */
4763         if (bnx2x_read_sfp_module_eeprom(phy,
4764                                          params,
4765                                          SFP_EEPROM_CON_TYPE_ADDR,
4766                                          1,
4767                                          &val) != 0) {
4768                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4769                 return -EINVAL;
4770         }
4771
4772         switch (val) {
4773         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4774         {
4775                 u8 copper_module_type;
4776                 phy->media_type = ETH_PHY_DA_TWINAX;
4777                 /*
4778                  * Check if its active cable (includes SFP+ module)
4779                  * of passive cable
4780                  */
4781                 if (bnx2x_read_sfp_module_eeprom(phy,
4782                                                params,
4783                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4784                                                1,
4785                                                &copper_module_type) != 0) {
4786                         DP(NETIF_MSG_LINK,
4787                                 "Failed to read copper-cable-type"
4788                                 " from SFP+ EEPROM\n");
4789                         return -EINVAL;
4790                 }
4791
4792                 if (copper_module_type &
4793                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4794                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4795                         check_limiting_mode = 1;
4796                 } else if (copper_module_type &
4797                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4798                                 DP(NETIF_MSG_LINK, "Passive Copper"
4799                                             " cable detected\n");
4800                                 *edc_mode =
4801                                       EDC_MODE_PASSIVE_DAC;
4802                 } else {
4803                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4804                                      "type 0x%x !!!\n", copper_module_type);
4805                         return -EINVAL;
4806                 }
4807                 break;
4808         }
4809         case SFP_EEPROM_CON_TYPE_VAL_LC:
4810                 phy->media_type = ETH_PHY_SFP_FIBER;
4811                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4812                 check_limiting_mode = 1;
4813                 break;
4814         default:
4815                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4816                          val);
4817                 return -EINVAL;
4818         }
4819         sync_offset = params->shmem_base +
4820                 offsetof(struct shmem_region,
4821                          dev_info.port_hw_config[params->port].media_type);
4822         media_types = REG_RD(bp, sync_offset);
4823         /* Update media type for non-PMF sync */
4824         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
4825                 if (&(params->phy[phy_idx]) == phy) {
4826                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
4827                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4828                         media_types |= ((phy->media_type &
4829                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
4830                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4831                         break;
4832                 }
4833         }
4834         REG_WR(bp, sync_offset, media_types);
4835         if (check_limiting_mode) {
4836                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4837                 if (bnx2x_read_sfp_module_eeprom(phy,
4838                                                  params,
4839                                                  SFP_EEPROM_OPTIONS_ADDR,
4840                                                  SFP_EEPROM_OPTIONS_SIZE,
4841                                                  options) != 0) {
4842                         DP(NETIF_MSG_LINK, "Failed to read Option"
4843                                 " field from module EEPROM\n");
4844                         return -EINVAL;
4845                 }
4846                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4847                         *edc_mode = EDC_MODE_LINEAR;
4848                 else
4849                         *edc_mode = EDC_MODE_LIMITING;
4850         }
4851         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4852         return 0;
4853 }
4854 /*
4855  * This function read the relevant field from the module (SFP+), and verify it
4856  * is compliant with this board
4857  */
4858 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4859                                    struct link_params *params)
4860 {
4861         struct bnx2x *bp = params->bp;
4862         u32 val, cmd;
4863         u32 fw_resp, fw_cmd_param;
4864         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4865         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4866         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4867         val = REG_RD(bp, params->shmem_base +
4868                          offsetof(struct shmem_region, dev_info.
4869                                   port_feature_config[params->port].config));
4870         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4871             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4872                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4873                 return 0;
4874         }
4875
4876         if (params->feature_config_flags &
4877             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4878                 /* Use specific phy request */
4879                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4880         } else if (params->feature_config_flags &
4881                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4882                 /* Use first phy request only in case of non-dual media*/
4883                 if (DUAL_MEDIA(params)) {
4884                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4885                            "verification\n");
4886                         return -EINVAL;
4887                 }
4888                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4889         } else {
4890                 /* No support in OPT MDL detection */
4891                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4892                           "verification\n");
4893                 return -EINVAL;
4894         }
4895
4896         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4897         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4898         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4899                 DP(NETIF_MSG_LINK, "Approved module\n");
4900                 return 0;
4901         }
4902
4903         /* format the warning message */
4904         if (bnx2x_read_sfp_module_eeprom(phy,
4905                                          params,
4906                                          SFP_EEPROM_VENDOR_NAME_ADDR,
4907                                          SFP_EEPROM_VENDOR_NAME_SIZE,
4908                                          (u8 *)vendor_name))
4909                 vendor_name[0] = '\0';
4910         else
4911                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4912         if (bnx2x_read_sfp_module_eeprom(phy,
4913                                          params,
4914                                          SFP_EEPROM_PART_NO_ADDR,
4915                                          SFP_EEPROM_PART_NO_SIZE,
4916                                          (u8 *)vendor_pn))
4917                 vendor_pn[0] = '\0';
4918         else
4919                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4920
4921         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
4922                               " Port %d from %s part number %s\n",
4923                          params->port, vendor_name, vendor_pn);
4924         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4925         return -EINVAL;
4926 }
4927
4928 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4929                                                  struct link_params *params)
4930
4931 {
4932         u8 val;
4933         struct bnx2x *bp = params->bp;
4934         u16 timeout;
4935         /*
4936          * Initialization time after hot-plug may take up to 300ms for
4937          * some phys type ( e.g. JDSU )
4938          */
4939
4940         for (timeout = 0; timeout < 60; timeout++) {
4941                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4942                     == 0) {
4943                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4944                                      "took %d ms\n", timeout * 5);
4945                         return 0;
4946                 }
4947                 msleep(5);
4948         }
4949         return -EINVAL;
4950 }
4951
4952 static void bnx2x_8727_power_module(struct bnx2x *bp,
4953                                     struct bnx2x_phy *phy,
4954                                     u8 is_power_up) {
4955         /* Make sure GPIOs are not using for LED mode */
4956         u16 val;
4957         /*
4958          * In the GPIO register, bit 4 is use to determine if the GPIOs are
4959          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4960          * output
4961          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4962          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4963          * where the 1st bit is the over-current(only input), and 2nd bit is
4964          * for power( only output )
4965          *
4966          * In case of NOC feature is disabled and power is up, set GPIO control
4967          *  as input to enable listening of over-current indication
4968          */
4969         if (phy->flags & FLAGS_NOC)
4970                 return;
4971         if (is_power_up)
4972                 val = (1<<4);
4973         else
4974                 /*
4975                  * Set GPIO control to OUTPUT, and set the power bit
4976                  * to according to the is_power_up
4977                  */
4978                 val = (1<<1);
4979
4980         bnx2x_cl45_write(bp, phy,
4981                          MDIO_PMA_DEVAD,
4982                          MDIO_PMA_REG_8727_GPIO_CTRL,
4983                          val);
4984 }
4985
4986 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4987                                         struct bnx2x_phy *phy,
4988                                         u16 edc_mode)
4989 {
4990         u16 cur_limiting_mode;
4991
4992         bnx2x_cl45_read(bp, phy,
4993                         MDIO_PMA_DEVAD,
4994                         MDIO_PMA_REG_ROM_VER2,
4995                         &cur_limiting_mode);
4996         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4997                  cur_limiting_mode);
4998
4999         if (edc_mode == EDC_MODE_LIMITING) {
5000                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
5001                 bnx2x_cl45_write(bp, phy,
5002                                  MDIO_PMA_DEVAD,
5003                                  MDIO_PMA_REG_ROM_VER2,
5004                                  EDC_MODE_LIMITING);
5005         } else { /* LRM mode ( default )*/
5006
5007                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
5008
5009                 /*
5010                  * Changing to LRM mode takes quite few seconds. So do it only
5011                  * if current mode is limiting (default is LRM)
5012                  */
5013                 if (cur_limiting_mode != EDC_MODE_LIMITING)
5014                         return 0;
5015
5016                 bnx2x_cl45_write(bp, phy,
5017                                  MDIO_PMA_DEVAD,
5018                                  MDIO_PMA_REG_LRM_MODE,
5019                                  0);
5020                 bnx2x_cl45_write(bp, phy,
5021                                  MDIO_PMA_DEVAD,
5022                                  MDIO_PMA_REG_ROM_VER2,
5023                                  0x128);
5024                 bnx2x_cl45_write(bp, phy,
5025                                  MDIO_PMA_DEVAD,
5026                                  MDIO_PMA_REG_MISC_CTRL0,
5027                                  0x4008);
5028                 bnx2x_cl45_write(bp, phy,
5029                                  MDIO_PMA_DEVAD,
5030                                  MDIO_PMA_REG_LRM_MODE,
5031                                  0xaaaa);
5032         }
5033         return 0;
5034 }
5035
5036 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
5037                                         struct bnx2x_phy *phy,
5038                                         u16 edc_mode)
5039 {
5040         u16 phy_identifier;
5041         u16 rom_ver2_val;
5042         bnx2x_cl45_read(bp, phy,
5043                         MDIO_PMA_DEVAD,
5044                         MDIO_PMA_REG_PHY_IDENTIFIER,
5045                         &phy_identifier);
5046
5047         bnx2x_cl45_write(bp, phy,
5048                          MDIO_PMA_DEVAD,
5049                          MDIO_PMA_REG_PHY_IDENTIFIER,
5050                          (phy_identifier & ~(1<<9)));
5051
5052         bnx2x_cl45_read(bp, phy,
5053                         MDIO_PMA_DEVAD,
5054                         MDIO_PMA_REG_ROM_VER2,
5055                         &rom_ver2_val);
5056         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
5057         bnx2x_cl45_write(bp, phy,
5058                          MDIO_PMA_DEVAD,
5059                          MDIO_PMA_REG_ROM_VER2,
5060                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
5061
5062         bnx2x_cl45_write(bp, phy,
5063                          MDIO_PMA_DEVAD,
5064                          MDIO_PMA_REG_PHY_IDENTIFIER,
5065                          (phy_identifier | (1<<9)));
5066
5067         return 0;
5068 }
5069
5070 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
5071                                      struct link_params *params,
5072                                      u32 action)
5073 {
5074         struct bnx2x *bp = params->bp;
5075
5076         switch (action) {
5077         case DISABLE_TX:
5078                 bnx2x_sfp_set_transmitter(params, phy, 0);
5079                 break;
5080         case ENABLE_TX:
5081                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
5082                         bnx2x_sfp_set_transmitter(params, phy, 1);
5083                 break;
5084         default:
5085                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5086                    action);
5087                 return;
5088         }
5089 }
5090
5091 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5092                                            u8 gpio_mode)
5093 {
5094         struct bnx2x *bp = params->bp;
5095
5096         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5097                             offsetof(struct shmem_region,
5098                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
5099                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5100         switch (fault_led_gpio) {
5101         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5102                 return;
5103         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5104         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5105         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5106         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5107         {
5108                 u8 gpio_port = bnx2x_get_gpio_port(params);
5109                 u16 gpio_pin = fault_led_gpio -
5110                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5111                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5112                                    "pin %x port %x mode %x\n",
5113                                gpio_pin, gpio_port, gpio_mode);
5114                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5115         }
5116         break;
5117         default:
5118                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5119                                fault_led_gpio);
5120         }
5121 }
5122
5123 static void bnx2x_power_sfp_module(struct link_params *params,
5124                                    struct bnx2x_phy *phy,
5125                                    u8 power)
5126 {
5127         struct bnx2x *bp = params->bp;
5128         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5129
5130         switch (phy->type) {
5131         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5132         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5133                 bnx2x_8727_power_module(params->bp, phy, power);
5134                 break;
5135         default:
5136                 break;
5137         }
5138 }
5139
5140 static void bnx2x_set_limiting_mode(struct link_params *params,
5141                                     struct bnx2x_phy *phy,
5142                                     u16 edc_mode)
5143 {
5144         switch (phy->type) {
5145         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5146                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5147                 break;
5148         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5149         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5150                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5151                 break;
5152         }
5153 }
5154
5155 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5156                                struct link_params *params)
5157 {
5158         struct bnx2x *bp = params->bp;
5159         u16 edc_mode;
5160         int rc = 0;
5161
5162         u32 val = REG_RD(bp, params->shmem_base +
5163                              offsetof(struct shmem_region, dev_info.
5164                                      port_feature_config[params->port].config));
5165
5166         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5167                  params->port);
5168         /* Power up module */
5169         bnx2x_power_sfp_module(params, phy, 1);
5170         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5171                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5172                 return -EINVAL;
5173         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5174                 /* check SFP+ module compatibility */
5175                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5176                 rc = -EINVAL;
5177                 /* Turn on fault module-detected led */
5178                 bnx2x_set_sfp_module_fault_led(params,
5179                                                MISC_REGISTERS_GPIO_HIGH);
5180
5181                 /* Check if need to power down the SFP+ module */
5182                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5183                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
5184                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5185                         bnx2x_power_sfp_module(params, phy, 0);
5186                         return rc;
5187                 }
5188         } else {
5189                 /* Turn off fault module-detected led */
5190                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5191         }
5192
5193         /*
5194          * Check and set limiting mode / LRM mode on 8726. On 8727 it
5195          * is done automatically
5196          */
5197         bnx2x_set_limiting_mode(params, phy, edc_mode);
5198
5199         /*
5200          * Enable transmit for this module if the module is approved, or
5201          * if unapproved modules should also enable the Tx laser
5202          */
5203         if (rc == 0 ||
5204             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5205             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5206                 bnx2x_sfp_set_transmitter(params, phy, 1);
5207         else
5208                 bnx2x_sfp_set_transmitter(params, phy, 0);
5209
5210         return rc;
5211 }
5212
5213 void bnx2x_handle_module_detect_int(struct link_params *params)
5214 {
5215         struct bnx2x *bp = params->bp;
5216         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5217         u32 gpio_val;
5218         u8 port = params->port;
5219
5220         /* Set valid module led off */
5221         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5222
5223         /* Get current gpio val reflecting module plugged in / out*/
5224         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5225
5226         /* Call the handling function in case module is detected */
5227         if (gpio_val == 0) {
5228                 bnx2x_power_sfp_module(params, phy, 1);
5229                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5230                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5231                                    port);
5232
5233                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5234                         bnx2x_sfp_module_detection(phy, params);
5235                 else
5236                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5237         } else {
5238                 u32 val = REG_RD(bp, params->shmem_base +
5239                                  offsetof(struct shmem_region, dev_info.
5240                                           port_feature_config[params->port].
5241                                           config));
5242
5243                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5244                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5245                                    port);
5246                 /*
5247                  * Module was plugged out.
5248                  * Disable transmit for this module
5249                  */
5250                 phy->media_type = ETH_PHY_NOT_PRESENT;
5251                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5252                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5253                         bnx2x_sfp_set_transmitter(params, phy, 0);
5254         }
5255 }
5256
5257 /******************************************************************/
5258 /*              Used by 8706 and 8727                             */
5259 /******************************************************************/
5260 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
5261                                  struct bnx2x_phy *phy,
5262                                  u16 alarm_status_offset,
5263                                  u16 alarm_ctrl_offset)
5264 {
5265         u16 alarm_status, val;
5266         bnx2x_cl45_read(bp, phy,
5267                         MDIO_PMA_DEVAD, alarm_status_offset,
5268                         &alarm_status);
5269         bnx2x_cl45_read(bp, phy,
5270                         MDIO_PMA_DEVAD, alarm_status_offset,
5271                         &alarm_status);
5272         /* Mask or enable the fault event. */
5273         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
5274         if (alarm_status & (1<<0))
5275                 val &= ~(1<<0);
5276         else
5277                 val |= (1<<0);
5278         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
5279 }
5280 /******************************************************************/
5281 /*              common BCM8706/BCM8726 PHY SECTION                */
5282 /******************************************************************/
5283 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5284                                       struct link_params *params,
5285                                       struct link_vars *vars)
5286 {
5287         u8 link_up = 0;
5288         u16 val1, val2, rx_sd, pcs_status;
5289         struct bnx2x *bp = params->bp;
5290         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5291         /* Clear RX Alarm*/
5292         bnx2x_cl45_read(bp, phy,
5293                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5294
5295         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5296                              MDIO_PMA_REG_TX_ALARM_CTRL);
5297
5298         /* clear LASI indication*/
5299         bnx2x_cl45_read(bp, phy,
5300                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5301         bnx2x_cl45_read(bp, phy,
5302                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5303         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5304
5305         bnx2x_cl45_read(bp, phy,
5306                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5307         bnx2x_cl45_read(bp, phy,
5308                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5309         bnx2x_cl45_read(bp, phy,
5310                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5311         bnx2x_cl45_read(bp, phy,
5312                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5313
5314         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5315                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5316         /*
5317          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5318          * are set, or if the autoneg bit 1 is set
5319          */
5320         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5321         if (link_up) {
5322                 if (val2 & (1<<1))
5323                         vars->line_speed = SPEED_1000;
5324                 else
5325                         vars->line_speed = SPEED_10000;
5326                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5327                 vars->duplex = DUPLEX_FULL;
5328         }
5329
5330         /* Capture 10G link fault. Read twice to clear stale value. */
5331         if (vars->line_speed == SPEED_10000) {
5332                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5333                             MDIO_PMA_REG_TX_ALARM, &val1);
5334                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5335                             MDIO_PMA_REG_TX_ALARM, &val1);
5336                 if (val1 & (1<<0))
5337                         vars->fault_detected = 1;
5338         }
5339
5340         return link_up;
5341 }
5342
5343 /******************************************************************/
5344 /*                      BCM8706 PHY SECTION                       */
5345 /******************************************************************/
5346 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5347                                  struct link_params *params,
5348                                  struct link_vars *vars)
5349 {
5350         u32 tx_en_mode;
5351         u16 cnt, val, tmp1;
5352         struct bnx2x *bp = params->bp;
5353         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5354                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5355         /* HW reset */
5356         bnx2x_ext_phy_hw_reset(bp, params->port);
5357         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5358         bnx2x_wait_reset_complete(bp, phy, params);
5359
5360         /* Wait until fw is loaded */
5361         for (cnt = 0; cnt < 100; cnt++) {
5362                 bnx2x_cl45_read(bp, phy,
5363                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5364                 if (val)
5365                         break;
5366                 msleep(10);
5367         }
5368         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5369         if ((params->feature_config_flags &
5370              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5371                 u8 i;
5372                 u16 reg;
5373                 for (i = 0; i < 4; i++) {
5374                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5375                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5376                                    MDIO_XS_8706_REG_BANK_RX0);
5377                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5378                         /* Clear first 3 bits of the control */
5379                         val &= ~0x7;
5380                         /* Set control bits according to configuration */
5381                         val |= (phy->rx_preemphasis[i] & 0x7);
5382                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5383                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5384                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5385                 }
5386         }
5387         /* Force speed */
5388         if (phy->req_line_speed == SPEED_10000) {
5389                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5390
5391                 bnx2x_cl45_write(bp, phy,
5392                                  MDIO_PMA_DEVAD,
5393                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5394                 bnx2x_cl45_write(bp, phy,
5395                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5396                                  0);
5397                 /* Arm LASI for link and Tx fault. */
5398                 bnx2x_cl45_write(bp, phy,
5399                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 3);
5400         } else {
5401                 /* Force 1Gbps using autoneg with 1G advertisement */
5402
5403                 /* Allow CL37 through CL73 */
5404                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5405                 bnx2x_cl45_write(bp, phy,
5406                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5407
5408                 /* Enable Full-Duplex advertisement on CL37 */
5409                 bnx2x_cl45_write(bp, phy,
5410                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5411                 /* Enable CL37 AN */
5412                 bnx2x_cl45_write(bp, phy,
5413                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5414                 /* 1G support */
5415                 bnx2x_cl45_write(bp, phy,
5416                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5417
5418                 /* Enable clause 73 AN */
5419                 bnx2x_cl45_write(bp, phy,
5420                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5421                 bnx2x_cl45_write(bp, phy,
5422                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5423                                  0x0400);
5424                 bnx2x_cl45_write(bp, phy,
5425                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5426                                  0x0004);
5427         }
5428         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5429
5430         /*
5431          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5432          * power mode, if TX Laser is disabled
5433          */
5434
5435         tx_en_mode = REG_RD(bp, params->shmem_base +
5436                             offsetof(struct shmem_region,
5437                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5438                         & PORT_HW_CFG_TX_LASER_MASK;
5439
5440         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5441                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5442                 bnx2x_cl45_read(bp, phy,
5443                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5444                 tmp1 |= 0x1;
5445                 bnx2x_cl45_write(bp, phy,
5446                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5447         }
5448
5449         return 0;
5450 }
5451
5452 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
5453                                   struct link_params *params,
5454                                   struct link_vars *vars)
5455 {
5456         return bnx2x_8706_8726_read_status(phy, params, vars);
5457 }
5458
5459 /******************************************************************/
5460 /*                      BCM8726 PHY SECTION                       */
5461 /******************************************************************/
5462 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5463                                        struct link_params *params)
5464 {
5465         struct bnx2x *bp = params->bp;
5466         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5467         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5468 }
5469
5470 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5471                                          struct link_params *params)
5472 {
5473         struct bnx2x *bp = params->bp;
5474         /* Need to wait 100ms after reset */
5475         msleep(100);
5476
5477         /* Micro controller re-boot */
5478         bnx2x_cl45_write(bp, phy,
5479                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5480
5481         /* Set soft reset */
5482         bnx2x_cl45_write(bp, phy,
5483                          MDIO_PMA_DEVAD,
5484                          MDIO_PMA_REG_GEN_CTRL,
5485                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5486
5487         bnx2x_cl45_write(bp, phy,
5488                          MDIO_PMA_DEVAD,
5489                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5490
5491         bnx2x_cl45_write(bp, phy,
5492                          MDIO_PMA_DEVAD,
5493                          MDIO_PMA_REG_GEN_CTRL,
5494                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5495
5496         /* wait for 150ms for microcode load */
5497         msleep(150);
5498
5499         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5500         bnx2x_cl45_write(bp, phy,
5501                          MDIO_PMA_DEVAD,
5502                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5503
5504         msleep(200);
5505         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5506 }
5507
5508 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5509                                  struct link_params *params,
5510                                  struct link_vars *vars)
5511 {
5512         struct bnx2x *bp = params->bp;
5513         u16 val1;
5514         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5515         if (link_up) {
5516                 bnx2x_cl45_read(bp, phy,
5517                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5518                                 &val1);
5519                 if (val1 & (1<<15)) {
5520                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5521                         link_up = 0;
5522                         vars->line_speed = 0;
5523                 }
5524         }
5525         return link_up;
5526 }
5527
5528
5529 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
5530                                   struct link_params *params,
5531                                   struct link_vars *vars)
5532 {
5533         struct bnx2x *bp = params->bp;
5534         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5535
5536         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5537         bnx2x_wait_reset_complete(bp, phy, params);
5538
5539         bnx2x_8726_external_rom_boot(phy, params);
5540
5541         /*
5542          * Need to call module detected on initialization since the module
5543          * detection triggered by actual module insertion might occur before
5544          * driver is loaded, and when driver is loaded, it reset all
5545          * registers, including the transmitter
5546          */
5547         bnx2x_sfp_module_detection(phy, params);
5548
5549         if (phy->req_line_speed == SPEED_1000) {
5550                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5551                 bnx2x_cl45_write(bp, phy,
5552                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5553                 bnx2x_cl45_write(bp, phy,
5554                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5555                 bnx2x_cl45_write(bp, phy,
5556                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5557                 bnx2x_cl45_write(bp, phy,
5558                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5559                                  0x400);
5560         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5561                    (phy->speed_cap_mask &
5562                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5563                    ((phy->speed_cap_mask &
5564                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5565                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5566                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5567                 /* Set Flow control */
5568                 bnx2x_ext_phy_set_pause(params, phy, vars);
5569                 bnx2x_cl45_write(bp, phy,
5570                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5571                 bnx2x_cl45_write(bp, phy,
5572                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5573                 bnx2x_cl45_write(bp, phy,
5574                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5575                 bnx2x_cl45_write(bp, phy,
5576                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5577                 bnx2x_cl45_write(bp, phy,
5578                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5579                 /*
5580                  * Enable RX-ALARM control to receive interrupt for 1G speed
5581                  * change
5582                  */
5583                 bnx2x_cl45_write(bp, phy,
5584                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5585                 bnx2x_cl45_write(bp, phy,
5586                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5587                                  0x400);
5588
5589         } else { /* Default 10G. Set only LASI control */
5590                 bnx2x_cl45_write(bp, phy,
5591                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5592         }
5593
5594         /* Set TX PreEmphasis if needed */
5595         if ((params->feature_config_flags &
5596              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5597                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5598                          "TX_CTRL2 0x%x\n",
5599                          phy->tx_preemphasis[0],
5600                          phy->tx_preemphasis[1]);
5601                 bnx2x_cl45_write(bp, phy,
5602                                  MDIO_PMA_DEVAD,
5603                                  MDIO_PMA_REG_8726_TX_CTRL1,
5604                                  phy->tx_preemphasis[0]);
5605
5606                 bnx2x_cl45_write(bp, phy,
5607                                  MDIO_PMA_DEVAD,
5608                                  MDIO_PMA_REG_8726_TX_CTRL2,
5609                                  phy->tx_preemphasis[1]);
5610         }
5611
5612         return 0;
5613
5614 }
5615
5616 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5617                                   struct link_params *params)
5618 {
5619         struct bnx2x *bp = params->bp;
5620         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5621         /* Set serial boot control for external load */
5622         bnx2x_cl45_write(bp, phy,
5623                          MDIO_PMA_DEVAD,
5624                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
5625 }
5626
5627 /******************************************************************/
5628 /*                      BCM8727 PHY SECTION                       */
5629 /******************************************************************/
5630
5631 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5632                                     struct link_params *params, u8 mode)
5633 {
5634         struct bnx2x *bp = params->bp;
5635         u16 led_mode_bitmask = 0;
5636         u16 gpio_pins_bitmask = 0;
5637         u16 val;
5638         /* Only NOC flavor requires to set the LED specifically */
5639         if (!(phy->flags & FLAGS_NOC))
5640                 return;
5641         switch (mode) {
5642         case LED_MODE_FRONT_PANEL_OFF:
5643         case LED_MODE_OFF:
5644                 led_mode_bitmask = 0;
5645                 gpio_pins_bitmask = 0x03;
5646                 break;
5647         case LED_MODE_ON:
5648                 led_mode_bitmask = 0;
5649                 gpio_pins_bitmask = 0x02;
5650                 break;
5651         case LED_MODE_OPER:
5652                 led_mode_bitmask = 0x60;
5653                 gpio_pins_bitmask = 0x11;
5654                 break;
5655         }
5656         bnx2x_cl45_read(bp, phy,
5657                         MDIO_PMA_DEVAD,
5658                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5659                         &val);
5660         val &= 0xff8f;
5661         val |= led_mode_bitmask;
5662         bnx2x_cl45_write(bp, phy,
5663                          MDIO_PMA_DEVAD,
5664                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5665                          val);
5666         bnx2x_cl45_read(bp, phy,
5667                         MDIO_PMA_DEVAD,
5668                         MDIO_PMA_REG_8727_GPIO_CTRL,
5669                         &val);
5670         val &= 0xffe0;
5671         val |= gpio_pins_bitmask;
5672         bnx2x_cl45_write(bp, phy,
5673                          MDIO_PMA_DEVAD,
5674                          MDIO_PMA_REG_8727_GPIO_CTRL,
5675                          val);
5676 }
5677 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5678                                 struct link_params *params) {
5679         u32 swap_val, swap_override;
5680         u8 port;
5681         /*
5682          * The PHY reset is controlled by GPIO 1. Fake the port number
5683          * to cancel the swap done in set_gpio()
5684          */
5685         struct bnx2x *bp = params->bp;
5686         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5687         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5688         port = (swap_val && swap_override) ^ 1;
5689         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5690                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5691 }
5692
5693 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
5694                                   struct link_params *params,
5695                                   struct link_vars *vars)
5696 {
5697         u32 tx_en_mode;
5698         u16 tmp1, val, mod_abs, tmp2;
5699         u16 rx_alarm_ctrl_val;
5700         u16 lasi_ctrl_val;
5701         struct bnx2x *bp = params->bp;
5702         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5703
5704         bnx2x_wait_reset_complete(bp, phy, params);
5705         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5706         /* Should be 0x6 to enable XS on Tx side. */
5707         lasi_ctrl_val = 0x0006;
5708
5709         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5710         /* enable LASI */
5711         bnx2x_cl45_write(bp, phy,
5712                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5713                          rx_alarm_ctrl_val);
5714         bnx2x_cl45_write(bp, phy,
5715                          MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5716                          0);
5717         bnx2x_cl45_write(bp, phy,
5718                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5719
5720         /*
5721          * Initially configure MOD_ABS to interrupt when module is
5722          * presence( bit 8)
5723          */
5724         bnx2x_cl45_read(bp, phy,
5725                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5726         /*
5727          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5728          * When the EDC is off it locks onto a reference clock and avoids
5729          * becoming 'lost'
5730          */
5731         mod_abs &= ~(1<<8);
5732         if (!(phy->flags & FLAGS_NOC))
5733                 mod_abs &= ~(1<<9);
5734         bnx2x_cl45_write(bp, phy,
5735                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5736
5737
5738         /* Make MOD_ABS give interrupt on change */
5739         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5740                         &val);
5741         val |= (1<<12);
5742         if (phy->flags & FLAGS_NOC)
5743                 val |= (3<<5);
5744
5745         /*
5746          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5747          * status which reflect SFP+ module over-current
5748          */
5749         if (!(phy->flags & FLAGS_NOC))
5750                 val &= 0xff8f; /* Reset bits 4-6 */
5751         bnx2x_cl45_write(bp, phy,
5752                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5753
5754         bnx2x_8727_power_module(bp, phy, 1);
5755
5756         bnx2x_cl45_read(bp, phy,
5757                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5758
5759         bnx2x_cl45_read(bp, phy,
5760                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5761
5762         /* Set option 1G speed */
5763         if (phy->req_line_speed == SPEED_1000) {
5764                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5765                 bnx2x_cl45_write(bp, phy,
5766                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5767                 bnx2x_cl45_write(bp, phy,
5768                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5769                 bnx2x_cl45_read(bp, phy,
5770                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5771                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5772                 /*
5773                  * Power down the XAUI until link is up in case of dual-media
5774                  * and 1G
5775                  */
5776                 if (DUAL_MEDIA(params)) {
5777                         bnx2x_cl45_read(bp, phy,
5778                                         MDIO_PMA_DEVAD,
5779                                         MDIO_PMA_REG_8727_PCS_GP, &val);
5780                         val |= (3<<10);
5781                         bnx2x_cl45_write(bp, phy,
5782                                          MDIO_PMA_DEVAD,
5783                                          MDIO_PMA_REG_8727_PCS_GP, val);
5784                 }
5785         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5786                    ((phy->speed_cap_mask &
5787                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5788                    ((phy->speed_cap_mask &
5789                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5790                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5791
5792                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5793                 bnx2x_cl45_write(bp, phy,
5794                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5795                 bnx2x_cl45_write(bp, phy,
5796                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5797         } else {
5798                 /*
5799                  * Since the 8727 has only single reset pin, need to set the 10G
5800                  * registers although it is default
5801                  */
5802                 bnx2x_cl45_write(bp, phy,
5803                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5804                                  0x0020);
5805                 bnx2x_cl45_write(bp, phy,
5806                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5807                 bnx2x_cl45_write(bp, phy,
5808                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5809                 bnx2x_cl45_write(bp, phy,
5810                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5811                                  0x0008);
5812         }
5813
5814         /*
5815          * Set 2-wire transfer rate of SFP+ module EEPROM
5816          * to 100Khz since some DACs(direct attached cables) do
5817          * not work at 400Khz.
5818          */
5819         bnx2x_cl45_write(bp, phy,
5820                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5821                          0xa001);
5822
5823         /* Set TX PreEmphasis if needed */
5824         if ((params->feature_config_flags &
5825              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5826                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5827                            phy->tx_preemphasis[0],
5828                            phy->tx_preemphasis[1]);
5829                 bnx2x_cl45_write(bp, phy,
5830                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5831                                  phy->tx_preemphasis[0]);
5832
5833                 bnx2x_cl45_write(bp, phy,
5834                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5835                                  phy->tx_preemphasis[1]);
5836         }
5837
5838         /*
5839          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5840          * power mode, if TX Laser is disabled
5841          */
5842         tx_en_mode = REG_RD(bp, params->shmem_base +
5843                             offsetof(struct shmem_region,
5844                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5845                         & PORT_HW_CFG_TX_LASER_MASK;
5846
5847         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5848
5849                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5850                 bnx2x_cl45_read(bp, phy,
5851                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5852                 tmp2 |= 0x1000;
5853                 tmp2 &= 0xFFEF;
5854                 bnx2x_cl45_write(bp, phy,
5855                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5856         }
5857
5858         return 0;
5859 }
5860
5861 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5862                                       struct link_params *params)
5863 {
5864         struct bnx2x *bp = params->bp;
5865         u16 mod_abs, rx_alarm_status;
5866         u32 val = REG_RD(bp, params->shmem_base +
5867                              offsetof(struct shmem_region, dev_info.
5868                                       port_feature_config[params->port].
5869                                       config));
5870         bnx2x_cl45_read(bp, phy,
5871                         MDIO_PMA_DEVAD,
5872                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5873         if (mod_abs & (1<<8)) {
5874
5875                 /* Module is absent */
5876                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5877                             "show module is absent\n");
5878                 phy->media_type = ETH_PHY_NOT_PRESENT;
5879                 /*
5880                  * 1. Set mod_abs to detect next module
5881                  *    presence event
5882                  * 2. Set EDC off by setting OPTXLOS signal input to low
5883                  *    (bit 9).
5884                  *    When the EDC is off it locks onto a reference clock and
5885                  *    avoids becoming 'lost'.
5886                  */
5887                 mod_abs &= ~(1<<8);
5888                 if (!(phy->flags & FLAGS_NOC))
5889                         mod_abs &= ~(1<<9);
5890                 bnx2x_cl45_write(bp, phy,
5891                                  MDIO_PMA_DEVAD,
5892                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5893
5894                 /*
5895                  * Clear RX alarm since it stays up as long as
5896                  * the mod_abs wasn't changed
5897                  */
5898                 bnx2x_cl45_read(bp, phy,
5899                                 MDIO_PMA_DEVAD,
5900                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5901
5902         } else {
5903                 /* Module is present */
5904                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5905                             "show module is present\n");
5906                 /*
5907                  * First disable transmitter, and if the module is ok, the
5908                  * module_detection will enable it
5909                  * 1. Set mod_abs to detect next module absent event ( bit 8)
5910                  * 2. Restore the default polarity of the OPRXLOS signal and
5911                  * this signal will then correctly indicate the presence or
5912                  * absence of the Rx signal. (bit 9)
5913                  */
5914                 mod_abs |= (1<<8);
5915                 if (!(phy->flags & FLAGS_NOC))
5916                         mod_abs |= (1<<9);
5917                 bnx2x_cl45_write(bp, phy,
5918                                  MDIO_PMA_DEVAD,
5919                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5920
5921                 /*
5922                  * Clear RX alarm since it stays up as long as the mod_abs
5923                  * wasn't changed. This is need to be done before calling the
5924                  * module detection, otherwise it will clear* the link update
5925                  * alarm
5926                  */
5927                 bnx2x_cl45_read(bp, phy,
5928                                 MDIO_PMA_DEVAD,
5929                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5930
5931
5932                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5933                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5934                         bnx2x_sfp_set_transmitter(params, phy, 0);
5935
5936                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5937                         bnx2x_sfp_module_detection(phy, params);
5938                 else
5939                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5940         }
5941
5942         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5943                    rx_alarm_status);
5944         /* No need to check link status in case of module plugged in/out */
5945 }
5946
5947 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5948                                  struct link_params *params,
5949                                  struct link_vars *vars)
5950
5951 {
5952         struct bnx2x *bp = params->bp;
5953         u8 link_up = 0, oc_port = params->port;
5954         u16 link_status = 0;
5955         u16 rx_alarm_status, lasi_ctrl, val1;
5956
5957         /* If PHY is not initialized, do not check link status */
5958         bnx2x_cl45_read(bp, phy,
5959                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5960                         &lasi_ctrl);
5961         if (!lasi_ctrl)
5962                 return 0;
5963
5964         /* Check the LASI on Rx */
5965         bnx2x_cl45_read(bp, phy,
5966                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5967                         &rx_alarm_status);
5968         vars->line_speed = 0;
5969         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
5970
5971         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5972                              MDIO_PMA_REG_TX_ALARM_CTRL);
5973
5974         bnx2x_cl45_read(bp, phy,
5975                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5976
5977         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5978
5979         /* Clear MSG-OUT */
5980         bnx2x_cl45_read(bp, phy,
5981                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5982
5983         /*
5984          * If a module is present and there is need to check
5985          * for over current
5986          */
5987         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5988                 /* Check over-current using 8727 GPIO0 input*/
5989                 bnx2x_cl45_read(bp, phy,
5990                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5991                                 &val1);
5992
5993                 if ((val1 & (1<<8)) == 0) {
5994                         if (!CHIP_IS_E1x(bp))
5995                                 oc_port = BP_PATH(bp) + (params->port << 1);
5996                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5997                                        " on port %d\n", oc_port);
5998                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
5999                                             " been detected and the power to "
6000                                             "that SFP+ module has been removed"
6001                                             " to prevent failure of the card."
6002                                             " Please remove the SFP+ module and"
6003                                             " restart the system to clear this"
6004                                             " error.\n",
6005                          oc_port);
6006                         /* Disable all RX_ALARMs except for mod_abs */
6007                         bnx2x_cl45_write(bp, phy,
6008                                          MDIO_PMA_DEVAD,
6009                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
6010
6011                         bnx2x_cl45_read(bp, phy,
6012                                         MDIO_PMA_DEVAD,
6013                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6014                         /* Wait for module_absent_event */
6015                         val1 |= (1<<8);
6016                         bnx2x_cl45_write(bp, phy,
6017                                          MDIO_PMA_DEVAD,
6018                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
6019                         /* Clear RX alarm */
6020                         bnx2x_cl45_read(bp, phy,
6021                                 MDIO_PMA_DEVAD,
6022                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
6023                         return 0;
6024                 }
6025         } /* Over current check */
6026
6027         /* When module absent bit is set, check module */
6028         if (rx_alarm_status & (1<<5)) {
6029                 bnx2x_8727_handle_mod_abs(phy, params);
6030                 /* Enable all mod_abs and link detection bits */
6031                 bnx2x_cl45_write(bp, phy,
6032                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6033                                  ((1<<5) | (1<<2)));
6034         }
6035         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
6036         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
6037         /* If transmitter is disabled, ignore false link up indication */
6038         bnx2x_cl45_read(bp, phy,
6039                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6040         if (val1 & (1<<15)) {
6041                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
6042                 return 0;
6043         }
6044
6045         bnx2x_cl45_read(bp, phy,
6046                         MDIO_PMA_DEVAD,
6047                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
6048
6049         /*
6050          * Bits 0..2 --> speed detected,
6051          * Bits 13..15--> link is down
6052          */
6053         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
6054                 link_up = 1;
6055                 vars->line_speed = SPEED_10000;
6056                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
6057                            params->port);
6058         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
6059                 link_up = 1;
6060                 vars->line_speed = SPEED_1000;
6061                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
6062                            params->port);
6063         } else {
6064                 link_up = 0;
6065                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
6066                            params->port);
6067         }
6068
6069         /* Capture 10G link fault. */
6070         if (vars->line_speed == SPEED_10000) {
6071                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6072                             MDIO_PMA_REG_TX_ALARM, &val1);
6073
6074                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6075                             MDIO_PMA_REG_TX_ALARM, &val1);
6076
6077                 if (val1 & (1<<0)) {
6078                         vars->fault_detected = 1;
6079                 }
6080         }
6081
6082         if (link_up) {
6083                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6084                 vars->duplex = DUPLEX_FULL;
6085                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
6086         }
6087
6088         if ((DUAL_MEDIA(params)) &&
6089             (phy->req_line_speed == SPEED_1000)) {
6090                 bnx2x_cl45_read(bp, phy,
6091                                 MDIO_PMA_DEVAD,
6092                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
6093                 /*
6094                  * In case of dual-media board and 1G, power up the XAUI side,
6095                  * otherwise power it down. For 10G it is done automatically
6096                  */
6097                 if (link_up)
6098                         val1 &= ~(3<<10);
6099                 else
6100                         val1 |= (3<<10);
6101                 bnx2x_cl45_write(bp, phy,
6102                                  MDIO_PMA_DEVAD,
6103                                  MDIO_PMA_REG_8727_PCS_GP, val1);
6104         }
6105         return link_up;
6106 }
6107
6108 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
6109                                   struct link_params *params)
6110 {
6111         struct bnx2x *bp = params->bp;
6112         /* Disable Transmitter */
6113         bnx2x_sfp_set_transmitter(params, phy, 0);
6114         /* Clear LASI */
6115         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
6116
6117 }
6118
6119 /******************************************************************/
6120 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
6121 /******************************************************************/
6122 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
6123                                            struct link_params *params)
6124 {
6125         u16 val, fw_ver1, fw_ver2, cnt;
6126         u8 port;
6127         struct bnx2x *bp = params->bp;
6128
6129         port = params->port;
6130
6131         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6132         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
6133         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
6134         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6135         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
6136         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
6137         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
6138
6139         for (cnt = 0; cnt < 100; cnt++) {
6140                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6141                 if (val & 1)
6142                         break;
6143                 udelay(5);
6144         }
6145         if (cnt == 100) {
6146                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6147                 bnx2x_save_spirom_version(bp, port, 0,
6148                                           phy->ver_addr);
6149                 return;
6150         }
6151
6152
6153         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
6154         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
6155         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6156         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
6157         for (cnt = 0; cnt < 100; cnt++) {
6158                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6159                 if (val & 1)
6160                         break;
6161                 udelay(5);
6162         }
6163         if (cnt == 100) {
6164                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6165                 bnx2x_save_spirom_version(bp, port, 0,
6166                                           phy->ver_addr);
6167                 return;
6168         }
6169
6170         /* lower 16 bits of the register SPI_FW_STATUS */
6171         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
6172         /* upper 16 bits of register SPI_FW_STATUS */
6173         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
6174
6175         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
6176                                   phy->ver_addr);
6177 }
6178
6179 static void bnx2x_848xx_set_led(struct bnx2x *bp,
6180                                 struct bnx2x_phy *phy)
6181 {
6182         u16 val;
6183
6184         /* PHYC_CTL_LED_CTL */
6185         bnx2x_cl45_read(bp, phy,
6186                         MDIO_PMA_DEVAD,
6187                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
6188         val &= 0xFE00;
6189         val |= 0x0092;
6190
6191         bnx2x_cl45_write(bp, phy,
6192                          MDIO_PMA_DEVAD,
6193                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
6194
6195         bnx2x_cl45_write(bp, phy,
6196                          MDIO_PMA_DEVAD,
6197                          MDIO_PMA_REG_8481_LED1_MASK,
6198                          0x80);
6199
6200         bnx2x_cl45_write(bp, phy,
6201                          MDIO_PMA_DEVAD,
6202                          MDIO_PMA_REG_8481_LED2_MASK,
6203                          0x18);
6204
6205         /* Select activity source by Tx and Rx, as suggested by PHY AE */
6206         bnx2x_cl45_write(bp, phy,
6207                          MDIO_PMA_DEVAD,
6208                          MDIO_PMA_REG_8481_LED3_MASK,
6209                          0x0006);
6210
6211         /* Select the closest activity blink rate to that in 10/100/1000 */
6212         bnx2x_cl45_write(bp, phy,
6213                         MDIO_PMA_DEVAD,
6214                         MDIO_PMA_REG_8481_LED3_BLINK,
6215                         0);
6216
6217         bnx2x_cl45_read(bp, phy,
6218                         MDIO_PMA_DEVAD,
6219                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
6220         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6221
6222         bnx2x_cl45_write(bp, phy,
6223                          MDIO_PMA_DEVAD,
6224                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
6225
6226         /* 'Interrupt Mask' */
6227         bnx2x_cl45_write(bp, phy,
6228                          MDIO_AN_DEVAD,
6229                          0xFFFB, 0xFFFD);
6230 }
6231
6232 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
6233                                        struct link_params *params,
6234                                        struct link_vars *vars)
6235 {
6236         struct bnx2x *bp = params->bp;
6237         u16 autoneg_val, an_1000_val, an_10_100_val;
6238         u16 tmp_req_line_speed;
6239
6240         tmp_req_line_speed = phy->req_line_speed;
6241         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6242                 if (phy->req_line_speed == SPEED_10000)
6243                         phy->req_line_speed = SPEED_AUTO_NEG;
6244
6245         /*
6246          * This phy uses the NIG latch mechanism since link indication
6247          * arrives through its LED4 and not via its LASI signal, so we
6248          * get steady signal instead of clear on read
6249          */
6250         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6251                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
6252
6253         bnx2x_cl45_write(bp, phy,
6254                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6255
6256         bnx2x_848xx_set_led(bp, phy);
6257
6258         /* set 1000 speed advertisement */
6259         bnx2x_cl45_read(bp, phy,
6260                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6261                         &an_1000_val);
6262
6263         bnx2x_ext_phy_set_pause(params, phy, vars);
6264         bnx2x_cl45_read(bp, phy,
6265                         MDIO_AN_DEVAD,
6266                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
6267                         &an_10_100_val);
6268         bnx2x_cl45_read(bp, phy,
6269                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6270                         &autoneg_val);
6271         /* Disable forced speed */
6272         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6273         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6274
6275         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6276              (phy->speed_cap_mask &
6277              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6278             (phy->req_line_speed == SPEED_1000)) {
6279                 an_1000_val |= (1<<8);
6280                 autoneg_val |= (1<<9 | 1<<12);
6281                 if (phy->req_duplex == DUPLEX_FULL)
6282                         an_1000_val |= (1<<9);
6283                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6284         } else
6285                 an_1000_val &= ~((1<<8) | (1<<9));
6286
6287         bnx2x_cl45_write(bp, phy,
6288                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6289                          an_1000_val);
6290
6291         /* set 10 speed advertisement */
6292         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6293              (phy->speed_cap_mask &
6294              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6295               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6296                 an_10_100_val |= (1<<7);
6297                 /* Enable autoneg and restart autoneg for legacy speeds */
6298                 autoneg_val |= (1<<9 | 1<<12);
6299
6300                 if (phy->req_duplex == DUPLEX_FULL)
6301                         an_10_100_val |= (1<<8);
6302                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6303         }
6304         /* set 10 speed advertisement */
6305         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6306             (phy->speed_cap_mask &
6307           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6308            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6309                 an_10_100_val |= (1<<5);
6310                 autoneg_val |= (1<<9 | 1<<12);
6311                 if (phy->req_duplex == DUPLEX_FULL)
6312                         an_10_100_val |= (1<<6);
6313                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6314         }
6315
6316         /* Only 10/100 are allowed to work in FORCE mode */
6317         if (phy->req_line_speed == SPEED_100) {
6318                 autoneg_val |= (1<<13);
6319                 /* Enabled AUTO-MDIX when autoneg is disabled */
6320                 bnx2x_cl45_write(bp, phy,
6321                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6322                                  (1<<15 | 1<<9 | 7<<0));
6323                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6324         }
6325         if (phy->req_line_speed == SPEED_10) {
6326                 /* Enabled AUTO-MDIX when autoneg is disabled */
6327                 bnx2x_cl45_write(bp, phy,
6328                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6329                                  (1<<15 | 1<<9 | 7<<0));
6330                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6331         }
6332
6333         bnx2x_cl45_write(bp, phy,
6334                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6335                          an_10_100_val);
6336
6337         if (phy->req_duplex == DUPLEX_FULL)
6338                 autoneg_val |= (1<<8);
6339
6340         bnx2x_cl45_write(bp, phy,
6341                          MDIO_AN_DEVAD,
6342                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6343
6344         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6345             (phy->speed_cap_mask &
6346              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6347                 (phy->req_line_speed == SPEED_10000)) {
6348                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
6349                         /* Restart autoneg for 10G*/
6350
6351                         bnx2x_cl45_write(bp, phy,
6352                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6353                                  0x3200);
6354         } else if (phy->req_line_speed != SPEED_10 &&
6355                    phy->req_line_speed != SPEED_100) {
6356                 bnx2x_cl45_write(bp, phy,
6357                                  MDIO_AN_DEVAD,
6358                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6359                                  1);
6360         }
6361         /* Save spirom version */
6362         bnx2x_save_848xx_spirom_version(phy, params);
6363
6364         phy->req_line_speed = tmp_req_line_speed;
6365
6366         return 0;
6367 }
6368
6369 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
6370                                   struct link_params *params,
6371                                   struct link_vars *vars)
6372 {
6373         struct bnx2x *bp = params->bp;
6374         /* Restore normal power mode*/
6375         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6376                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6377
6378         /* HW reset */
6379         bnx2x_ext_phy_hw_reset(bp, params->port);
6380         bnx2x_wait_reset_complete(bp, phy, params);
6381
6382         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6383         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6384 }
6385
6386
6387 #define PHY84833_HDSHK_WAIT 300
6388 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
6389                                    struct link_params *params,
6390                                    struct link_vars *vars)
6391 {
6392         u32 idx;
6393         u16 val;
6394         u16 data = 0x01b1;
6395         struct bnx2x *bp = params->bp;
6396         /* Do pair swap */
6397
6398
6399         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
6400         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6401                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
6402                         PHY84833_CMD_OPEN_OVERRIDE);
6403         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
6404                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6405                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
6406                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
6407                         break;
6408                 msleep(1);
6409         }
6410         if (idx >= PHY84833_HDSHK_WAIT) {
6411                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
6412                 return -EINVAL;
6413         }
6414
6415         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6416                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
6417                         data);
6418         /* Issue pair swap command */
6419         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6420                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
6421                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
6422         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
6423                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6424                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
6425                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
6426                         (val == PHY84833_CMD_COMPLETE_ERROR))
6427                         break;
6428                 msleep(1);
6429         }
6430         if ((idx >= PHY84833_HDSHK_WAIT) ||
6431                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
6432                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
6433                 return -EINVAL;
6434         }
6435         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6436                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
6437                         PHY84833_CMD_CLEAR_COMPLETE);
6438         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
6439         return 0;
6440 }
6441
6442 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6443                                    struct link_params *params,
6444                                    struct link_vars *vars)
6445 {
6446         struct bnx2x *bp = params->bp;
6447         u8 port, initialize = 1;
6448         u16 val;
6449         u16 temp;
6450         u32 actual_phy_selection, cms_enable;
6451         int rc = 0;
6452
6453         msleep(1);
6454
6455         if (!(CHIP_IS_E1(bp)))
6456                 port = BP_PATH(bp);
6457         else
6458                 port = params->port;
6459
6460         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
6461                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6462                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6463                                port);
6464         } else {
6465                 bnx2x_cl45_write(bp, phy,
6466                                 MDIO_PMA_DEVAD,
6467                                 MDIO_PMA_REG_CTRL, 0x8000);
6468         }
6469
6470         bnx2x_wait_reset_complete(bp, phy, params);
6471         /* Wait for GPHY to come out of reset */
6472         msleep(50);
6473
6474         /* Bring PHY out of super isolate mode */
6475         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
6476                 bnx2x_cl45_read(bp, phy,
6477                                 MDIO_CTL_DEVAD,
6478                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
6479                 val &= ~MDIO_84833_SUPER_ISOLATE;
6480                 bnx2x_cl45_write(bp, phy,
6481                                 MDIO_CTL_DEVAD,
6482                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
6483                 bnx2x_wait_reset_complete(bp, phy, params);
6484         }
6485
6486         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6487                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
6488
6489         /*
6490          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6491          */
6492         temp = vars->line_speed;
6493         vars->line_speed = SPEED_10000;
6494         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6495         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6496         vars->line_speed = temp;
6497
6498         /* Set dual-media configuration according to configuration */
6499
6500         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6501                         MDIO_CTL_REG_84823_MEDIA, &val);
6502         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6503                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6504                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6505                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6506                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6507         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6508                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6509
6510         actual_phy_selection = bnx2x_phy_selection(params);
6511
6512         switch (actual_phy_selection) {
6513         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6514                 /* Do nothing. Essentially this is like the priority copper */
6515                 break;
6516         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6517                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6518                 break;
6519         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6520                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6521                 break;
6522         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6523                 /* Do nothing here. The first PHY won't be initialized at all */
6524                 break;
6525         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6526                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6527                 initialize = 0;
6528                 break;
6529         }
6530         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6531                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6532
6533         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6534                          MDIO_CTL_REG_84823_MEDIA, val);
6535         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6536                    params->multi_phy_config, val);
6537
6538         if (initialize)
6539                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6540         else
6541                 bnx2x_save_848xx_spirom_version(phy, params);
6542         cms_enable = REG_RD(bp, params->shmem_base +
6543                         offsetof(struct shmem_region,
6544                         dev_info.port_hw_config[params->port].default_cfg)) &
6545                         PORT_HW_CFG_ENABLE_CMS_MASK;
6546
6547         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6548                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6549         if (cms_enable)
6550                 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6551         else
6552                 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6553         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6554                 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6555
6556
6557         return rc;
6558 }
6559
6560 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6561                                   struct link_params *params,
6562                                   struct link_vars *vars)
6563 {
6564         struct bnx2x *bp = params->bp;
6565         u16 val, val1, val2;
6566         u8 link_up = 0;
6567
6568
6569         /* Check 10G-BaseT link status */
6570         /* Check PMD signal ok */
6571         bnx2x_cl45_read(bp, phy,
6572                         MDIO_AN_DEVAD, 0xFFFA, &val1);
6573         bnx2x_cl45_read(bp, phy,
6574                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6575                         &val2);
6576         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6577
6578         /* Check link 10G */
6579         if (val2 & (1<<11)) {
6580                 vars->line_speed = SPEED_10000;
6581                 vars->duplex = DUPLEX_FULL;
6582                 link_up = 1;
6583                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6584         } else { /* Check Legacy speed link */
6585                 u16 legacy_status, legacy_speed;
6586
6587                 /* Enable expansion register 0x42 (Operation mode status) */
6588                 bnx2x_cl45_write(bp, phy,
6589                                  MDIO_AN_DEVAD,
6590                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6591
6592                 /* Get legacy speed operation status */
6593                 bnx2x_cl45_read(bp, phy,
6594                                 MDIO_AN_DEVAD,
6595                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6596                                 &legacy_status);
6597
6598                 DP(NETIF_MSG_LINK, "Legacy speed status"
6599                              " = 0x%x\n", legacy_status);
6600                 link_up = ((legacy_status & (1<<11)) == (1<<11));
6601                 if (link_up) {
6602                         legacy_speed = (legacy_status & (3<<9));
6603                         if (legacy_speed == (0<<9))
6604                                 vars->line_speed = SPEED_10;
6605                         else if (legacy_speed == (1<<9))
6606                                 vars->line_speed = SPEED_100;
6607                         else if (legacy_speed == (2<<9))
6608                                 vars->line_speed = SPEED_1000;
6609                         else /* Should not happen */
6610                                 vars->line_speed = 0;
6611
6612                         if (legacy_status & (1<<8))
6613                                 vars->duplex = DUPLEX_FULL;
6614                         else
6615                                 vars->duplex = DUPLEX_HALF;
6616
6617                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6618                                    " is_duplex_full= %d\n", vars->line_speed,
6619                                    (vars->duplex == DUPLEX_FULL));
6620                         /* Check legacy speed AN resolution */
6621                         bnx2x_cl45_read(bp, phy,
6622                                         MDIO_AN_DEVAD,
6623                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6624                                         &val);
6625                         if (val & (1<<5))
6626                                 vars->link_status |=
6627                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6628                         bnx2x_cl45_read(bp, phy,
6629                                         MDIO_AN_DEVAD,
6630                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6631                                         &val);
6632                         if ((val & (1<<0)) == 0)
6633                                 vars->link_status |=
6634                                         LINK_STATUS_PARALLEL_DETECTION_USED;
6635                 }
6636         }
6637         if (link_up) {
6638                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6639                            vars->line_speed);
6640                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6641         }
6642
6643         return link_up;
6644 }
6645
6646
6647 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6648 {
6649         int status = 0;
6650         u32 spirom_ver;
6651         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6652         status = bnx2x_format_ver(spirom_ver, str, len);
6653         return status;
6654 }
6655
6656 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6657                                 struct link_params *params)
6658 {
6659         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6660                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6661         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6662                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6663 }
6664
6665 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6666                                         struct link_params *params)
6667 {
6668         bnx2x_cl45_write(params->bp, phy,
6669                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6670         bnx2x_cl45_write(params->bp, phy,
6671                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6672 }
6673
6674 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6675                                    struct link_params *params)
6676 {
6677         struct bnx2x *bp = params->bp;
6678         u8 port;
6679
6680         if (!(CHIP_IS_E1(bp)))
6681                 port = BP_PATH(bp);
6682         else
6683                 port = params->port;
6684
6685         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
6686                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6687                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
6688                                port);
6689         } else {
6690                 bnx2x_cl45_write(bp, phy,
6691                                 MDIO_PMA_DEVAD,
6692                                 MDIO_PMA_REG_CTRL, 0x800);
6693         }
6694 }
6695
6696 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6697                                      struct link_params *params, u8 mode)
6698 {
6699         struct bnx2x *bp = params->bp;
6700         u16 val;
6701         u8 port;
6702
6703         if (!(CHIP_IS_E1(bp)))
6704                 port = BP_PATH(bp);
6705         else
6706                 port = params->port;
6707
6708         switch (mode) {
6709         case LED_MODE_OFF:
6710
6711                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
6712
6713                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6714                     SHARED_HW_CFG_LED_EXTPHY1) {
6715
6716                         /* Set LED masks */
6717                         bnx2x_cl45_write(bp, phy,
6718                                         MDIO_PMA_DEVAD,
6719                                         MDIO_PMA_REG_8481_LED1_MASK,
6720                                         0x0);
6721
6722                         bnx2x_cl45_write(bp, phy,
6723                                         MDIO_PMA_DEVAD,
6724                                         MDIO_PMA_REG_8481_LED2_MASK,
6725                                         0x0);
6726
6727                         bnx2x_cl45_write(bp, phy,
6728                                         MDIO_PMA_DEVAD,
6729                                         MDIO_PMA_REG_8481_LED3_MASK,
6730                                         0x0);
6731
6732                         bnx2x_cl45_write(bp, phy,
6733                                         MDIO_PMA_DEVAD,
6734                                         MDIO_PMA_REG_8481_LED5_MASK,
6735                                         0x0);
6736
6737                 } else {
6738                         bnx2x_cl45_write(bp, phy,
6739                                          MDIO_PMA_DEVAD,
6740                                          MDIO_PMA_REG_8481_LED1_MASK,
6741                                          0x0);
6742                 }
6743                 break;
6744         case LED_MODE_FRONT_PANEL_OFF:
6745
6746                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6747                    port);
6748
6749                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6750                     SHARED_HW_CFG_LED_EXTPHY1) {
6751
6752                         /* Set LED masks */
6753                         bnx2x_cl45_write(bp, phy,
6754                                          MDIO_PMA_DEVAD,
6755                                          MDIO_PMA_REG_8481_LED1_MASK,
6756                                          0x0);
6757
6758                         bnx2x_cl45_write(bp, phy,
6759                                          MDIO_PMA_DEVAD,
6760                                          MDIO_PMA_REG_8481_LED2_MASK,
6761                                          0x0);
6762
6763                         bnx2x_cl45_write(bp, phy,
6764                                          MDIO_PMA_DEVAD,
6765                                          MDIO_PMA_REG_8481_LED3_MASK,
6766                                          0x0);
6767
6768                         bnx2x_cl45_write(bp, phy,
6769                                          MDIO_PMA_DEVAD,
6770                                          MDIO_PMA_REG_8481_LED5_MASK,
6771                                          0x20);
6772
6773                 } else {
6774                         bnx2x_cl45_write(bp, phy,
6775                                          MDIO_PMA_DEVAD,
6776                                          MDIO_PMA_REG_8481_LED1_MASK,
6777                                          0x0);
6778                 }
6779                 break;
6780         case LED_MODE_ON:
6781
6782                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
6783
6784                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6785                     SHARED_HW_CFG_LED_EXTPHY1) {
6786                         /* Set control reg */
6787                         bnx2x_cl45_read(bp, phy,
6788                                         MDIO_PMA_DEVAD,
6789                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6790                                         &val);
6791                         val &= 0x8000;
6792                         val |= 0x2492;
6793
6794                         bnx2x_cl45_write(bp, phy,
6795                                          MDIO_PMA_DEVAD,
6796                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6797                                          val);
6798
6799                         /* Set LED masks */
6800                         bnx2x_cl45_write(bp, phy,
6801                                          MDIO_PMA_DEVAD,
6802                                          MDIO_PMA_REG_8481_LED1_MASK,
6803                                          0x0);
6804
6805                         bnx2x_cl45_write(bp, phy,
6806                                          MDIO_PMA_DEVAD,
6807                                          MDIO_PMA_REG_8481_LED2_MASK,
6808                                          0x20);
6809
6810                         bnx2x_cl45_write(bp, phy,
6811                                          MDIO_PMA_DEVAD,
6812                                          MDIO_PMA_REG_8481_LED3_MASK,
6813                                          0x20);
6814
6815                         bnx2x_cl45_write(bp, phy,
6816                                          MDIO_PMA_DEVAD,
6817                                          MDIO_PMA_REG_8481_LED5_MASK,
6818                                          0x0);
6819                 } else {
6820                         bnx2x_cl45_write(bp, phy,
6821                                          MDIO_PMA_DEVAD,
6822                                          MDIO_PMA_REG_8481_LED1_MASK,
6823                                          0x20);
6824                 }
6825                 break;
6826
6827         case LED_MODE_OPER:
6828
6829                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
6830
6831                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6832                     SHARED_HW_CFG_LED_EXTPHY1) {
6833
6834                         /* Set control reg */
6835                         bnx2x_cl45_read(bp, phy,
6836                                         MDIO_PMA_DEVAD,
6837                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6838                                         &val);
6839
6840                         if (!((val &
6841                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6842                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
6843                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
6844                                 bnx2x_cl45_write(bp, phy,
6845                                                  MDIO_PMA_DEVAD,
6846                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
6847                                                  0xa492);
6848                         }
6849
6850                         /* Set LED masks */
6851                         bnx2x_cl45_write(bp, phy,
6852                                          MDIO_PMA_DEVAD,
6853                                          MDIO_PMA_REG_8481_LED1_MASK,
6854                                          0x10);
6855
6856                         bnx2x_cl45_write(bp, phy,
6857                                          MDIO_PMA_DEVAD,
6858                                          MDIO_PMA_REG_8481_LED2_MASK,
6859                                          0x80);
6860
6861                         bnx2x_cl45_write(bp, phy,
6862                                          MDIO_PMA_DEVAD,
6863                                          MDIO_PMA_REG_8481_LED3_MASK,
6864                                          0x98);
6865
6866                         bnx2x_cl45_write(bp, phy,
6867                                          MDIO_PMA_DEVAD,
6868                                          MDIO_PMA_REG_8481_LED5_MASK,
6869                                          0x40);
6870
6871                 } else {
6872                         bnx2x_cl45_write(bp, phy,
6873                                          MDIO_PMA_DEVAD,
6874                                          MDIO_PMA_REG_8481_LED1_MASK,
6875                                          0x80);
6876
6877                         /* Tell LED3 to blink on source */
6878                         bnx2x_cl45_read(bp, phy,
6879                                         MDIO_PMA_DEVAD,
6880                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6881                                         &val);
6882                         val &= ~(7<<6);
6883                         val |= (1<<6); /* A83B[8:6]= 1 */
6884                         bnx2x_cl45_write(bp, phy,
6885                                          MDIO_PMA_DEVAD,
6886                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6887                                          val);
6888                 }
6889                 break;
6890         }
6891 }
6892 /******************************************************************/
6893 /*                      SFX7101 PHY SECTION                       */
6894 /******************************************************************/
6895 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6896                                        struct link_params *params)
6897 {
6898         struct bnx2x *bp = params->bp;
6899         /* SFX7101_XGXS_TEST1 */
6900         bnx2x_cl45_write(bp, phy,
6901                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6902 }
6903
6904 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
6905                                   struct link_params *params,
6906                                   struct link_vars *vars)
6907 {
6908         u16 fw_ver1, fw_ver2, val;
6909         struct bnx2x *bp = params->bp;
6910         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6911
6912         /* Restore normal power mode*/
6913         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6914                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6915         /* HW reset */
6916         bnx2x_ext_phy_hw_reset(bp, params->port);
6917         bnx2x_wait_reset_complete(bp, phy, params);
6918
6919         bnx2x_cl45_write(bp, phy,
6920                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6921         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6922         bnx2x_cl45_write(bp, phy,
6923                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6924
6925         bnx2x_ext_phy_set_pause(params, phy, vars);
6926         /* Restart autoneg */
6927         bnx2x_cl45_read(bp, phy,
6928                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6929         val |= 0x200;
6930         bnx2x_cl45_write(bp, phy,
6931                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6932
6933         /* Save spirom version */
6934         bnx2x_cl45_read(bp, phy,
6935                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6936
6937         bnx2x_cl45_read(bp, phy,
6938                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6939         bnx2x_save_spirom_version(bp, params->port,
6940                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6941         return 0;
6942 }
6943
6944 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6945                                  struct link_params *params,
6946                                  struct link_vars *vars)
6947 {
6948         struct bnx2x *bp = params->bp;
6949         u8 link_up;
6950         u16 val1, val2;
6951         bnx2x_cl45_read(bp, phy,
6952                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6953         bnx2x_cl45_read(bp, phy,
6954                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6955         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6956                    val2, val1);
6957         bnx2x_cl45_read(bp, phy,
6958                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6959         bnx2x_cl45_read(bp, phy,
6960                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6961         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6962                    val2, val1);
6963         link_up = ((val1 & 4) == 4);
6964         /* if link is up print the AN outcome of the SFX7101 PHY */
6965         if (link_up) {
6966                 bnx2x_cl45_read(bp, phy,
6967                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6968                                 &val2);
6969                 vars->line_speed = SPEED_10000;
6970                 vars->duplex = DUPLEX_FULL;
6971                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6972                            val2, (val2 & (1<<14)));
6973                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6974                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6975         }
6976         return link_up;
6977 }
6978
6979 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6980 {
6981         if (*len < 5)
6982                 return -EINVAL;
6983         str[0] = (spirom_ver & 0xFF);
6984         str[1] = (spirom_ver & 0xFF00) >> 8;
6985         str[2] = (spirom_ver & 0xFF0000) >> 16;
6986         str[3] = (spirom_ver & 0xFF000000) >> 24;
6987         str[4] = '\0';
6988         *len -= 5;
6989         return 0;
6990 }
6991
6992 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6993 {
6994         u16 val, cnt;
6995
6996         bnx2x_cl45_read(bp, phy,
6997                         MDIO_PMA_DEVAD,
6998                         MDIO_PMA_REG_7101_RESET, &val);
6999
7000         for (cnt = 0; cnt < 10; cnt++) {
7001                 msleep(50);
7002                 /* Writes a self-clearing reset */
7003                 bnx2x_cl45_write(bp, phy,
7004                                  MDIO_PMA_DEVAD,
7005                                  MDIO_PMA_REG_7101_RESET,
7006                                  (val | (1<<15)));
7007                 /* Wait for clear */
7008                 bnx2x_cl45_read(bp, phy,
7009                                 MDIO_PMA_DEVAD,
7010                                 MDIO_PMA_REG_7101_RESET, &val);
7011
7012                 if ((val & (1<<15)) == 0)
7013                         break;
7014         }
7015 }
7016
7017 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
7018                                 struct link_params *params) {
7019         /* Low power mode is controlled by GPIO 2 */
7020         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
7021                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7022         /* The PHY reset is controlled by GPIO 1 */
7023         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
7024                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7025 }
7026
7027 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
7028                                     struct link_params *params, u8 mode)
7029 {
7030         u16 val = 0;
7031         struct bnx2x *bp = params->bp;
7032         switch (mode) {
7033         case LED_MODE_FRONT_PANEL_OFF:
7034         case LED_MODE_OFF:
7035                 val = 2;
7036                 break;
7037         case LED_MODE_ON:
7038                 val = 1;
7039                 break;
7040         case LED_MODE_OPER:
7041                 val = 0;
7042                 break;
7043         }
7044         bnx2x_cl45_write(bp, phy,
7045                          MDIO_PMA_DEVAD,
7046                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
7047                          val);
7048 }
7049
7050 /******************************************************************/
7051 /*                      STATIC PHY DECLARATION                    */
7052 /******************************************************************/
7053
7054 static struct bnx2x_phy phy_null = {
7055         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
7056         .addr           = 0,
7057         .def_md_devad   = 0,
7058         .flags          = FLAGS_INIT_XGXS_FIRST,
7059         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7060         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7061         .mdio_ctrl      = 0,
7062         .supported      = 0,
7063         .media_type     = ETH_PHY_NOT_PRESENT,
7064         .ver_addr       = 0,
7065         .req_flow_ctrl  = 0,
7066         .req_line_speed = 0,
7067         .speed_cap_mask = 0,
7068         .req_duplex     = 0,
7069         .rsrv           = 0,
7070         .config_init    = (config_init_t)NULL,
7071         .read_status    = (read_status_t)NULL,
7072         .link_reset     = (link_reset_t)NULL,
7073         .config_loopback = (config_loopback_t)NULL,
7074         .format_fw_ver  = (format_fw_ver_t)NULL,
7075         .hw_reset       = (hw_reset_t)NULL,
7076         .set_link_led   = (set_link_led_t)NULL,
7077         .phy_specific_func = (phy_specific_func_t)NULL
7078 };
7079
7080 static struct bnx2x_phy phy_serdes = {
7081         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
7082         .addr           = 0xff,
7083         .def_md_devad   = 0,
7084         .flags          = 0,
7085         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7086         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7087         .mdio_ctrl      = 0,
7088         .supported      = (SUPPORTED_10baseT_Half |
7089                            SUPPORTED_10baseT_Full |
7090                            SUPPORTED_100baseT_Half |
7091                            SUPPORTED_100baseT_Full |
7092                            SUPPORTED_1000baseT_Full |
7093                            SUPPORTED_2500baseX_Full |
7094                            SUPPORTED_TP |
7095                            SUPPORTED_Autoneg |
7096                            SUPPORTED_Pause |
7097                            SUPPORTED_Asym_Pause),
7098         .media_type     = ETH_PHY_BASE_T,
7099         .ver_addr       = 0,
7100         .req_flow_ctrl  = 0,
7101         .req_line_speed = 0,
7102         .speed_cap_mask = 0,
7103         .req_duplex     = 0,
7104         .rsrv           = 0,
7105         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
7106         .read_status    = (read_status_t)bnx2x_link_settings_status,
7107         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7108         .config_loopback = (config_loopback_t)NULL,
7109         .format_fw_ver  = (format_fw_ver_t)NULL,
7110         .hw_reset       = (hw_reset_t)NULL,
7111         .set_link_led   = (set_link_led_t)NULL,
7112         .phy_specific_func = (phy_specific_func_t)NULL
7113 };
7114
7115 static struct bnx2x_phy phy_xgxs = {
7116         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
7117         .addr           = 0xff,
7118         .def_md_devad   = 0,
7119         .flags          = 0,
7120         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7121         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7122         .mdio_ctrl      = 0,
7123         .supported      = (SUPPORTED_10baseT_Half |
7124                            SUPPORTED_10baseT_Full |
7125                            SUPPORTED_100baseT_Half |
7126                            SUPPORTED_100baseT_Full |
7127                            SUPPORTED_1000baseT_Full |
7128                            SUPPORTED_2500baseX_Full |
7129                            SUPPORTED_10000baseT_Full |
7130                            SUPPORTED_FIBRE |
7131                            SUPPORTED_Autoneg |
7132                            SUPPORTED_Pause |
7133                            SUPPORTED_Asym_Pause),
7134         .media_type     = ETH_PHY_CX4,
7135         .ver_addr       = 0,
7136         .req_flow_ctrl  = 0,
7137         .req_line_speed = 0,
7138         .speed_cap_mask = 0,
7139         .req_duplex     = 0,
7140         .rsrv           = 0,
7141         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
7142         .read_status    = (read_status_t)bnx2x_link_settings_status,
7143         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7144         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
7145         .format_fw_ver  = (format_fw_ver_t)NULL,
7146         .hw_reset       = (hw_reset_t)NULL,
7147         .set_link_led   = (set_link_led_t)NULL,
7148         .phy_specific_func = (phy_specific_func_t)NULL
7149 };
7150
7151 static struct bnx2x_phy phy_7101 = {
7152         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7153         .addr           = 0xff,
7154         .def_md_devad   = 0,
7155         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7156         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7157         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7158         .mdio_ctrl      = 0,
7159         .supported      = (SUPPORTED_10000baseT_Full |
7160                            SUPPORTED_TP |
7161                            SUPPORTED_Autoneg |
7162                            SUPPORTED_Pause |
7163                            SUPPORTED_Asym_Pause),
7164         .media_type     = ETH_PHY_BASE_T,
7165         .ver_addr       = 0,
7166         .req_flow_ctrl  = 0,
7167         .req_line_speed = 0,
7168         .speed_cap_mask = 0,
7169         .req_duplex     = 0,
7170         .rsrv           = 0,
7171         .config_init    = (config_init_t)bnx2x_7101_config_init,
7172         .read_status    = (read_status_t)bnx2x_7101_read_status,
7173         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7174         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
7175         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
7176         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
7177         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
7178         .phy_specific_func = (phy_specific_func_t)NULL
7179 };
7180 static struct bnx2x_phy phy_8073 = {
7181         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
7182         .addr           = 0xff,
7183         .def_md_devad   = 0,
7184         .flags          = FLAGS_HW_LOCK_REQUIRED,
7185         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7186         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7187         .mdio_ctrl      = 0,
7188         .supported      = (SUPPORTED_10000baseT_Full |
7189                            SUPPORTED_2500baseX_Full |
7190                            SUPPORTED_1000baseT_Full |
7191                            SUPPORTED_FIBRE |
7192                            SUPPORTED_Autoneg |
7193                            SUPPORTED_Pause |
7194                            SUPPORTED_Asym_Pause),
7195         .media_type     = ETH_PHY_KR,
7196         .ver_addr       = 0,
7197         .req_flow_ctrl  = 0,
7198         .req_line_speed = 0,
7199         .speed_cap_mask = 0,
7200         .req_duplex     = 0,
7201         .rsrv           = 0,
7202         .config_init    = (config_init_t)bnx2x_8073_config_init,
7203         .read_status    = (read_status_t)bnx2x_8073_read_status,
7204         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
7205         .config_loopback = (config_loopback_t)NULL,
7206         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7207         .hw_reset       = (hw_reset_t)NULL,
7208         .set_link_led   = (set_link_led_t)NULL,
7209         .phy_specific_func = (phy_specific_func_t)NULL
7210 };
7211 static struct bnx2x_phy phy_8705 = {
7212         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
7213         .addr           = 0xff,
7214         .def_md_devad   = 0,
7215         .flags          = FLAGS_INIT_XGXS_FIRST,
7216         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7217         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7218         .mdio_ctrl      = 0,
7219         .supported      = (SUPPORTED_10000baseT_Full |
7220                            SUPPORTED_FIBRE |
7221                            SUPPORTED_Pause |
7222                            SUPPORTED_Asym_Pause),
7223         .media_type     = ETH_PHY_XFP_FIBER,
7224         .ver_addr       = 0,
7225         .req_flow_ctrl  = 0,
7226         .req_line_speed = 0,
7227         .speed_cap_mask = 0,
7228         .req_duplex     = 0,
7229         .rsrv           = 0,
7230         .config_init    = (config_init_t)bnx2x_8705_config_init,
7231         .read_status    = (read_status_t)bnx2x_8705_read_status,
7232         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7233         .config_loopback = (config_loopback_t)NULL,
7234         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
7235         .hw_reset       = (hw_reset_t)NULL,
7236         .set_link_led   = (set_link_led_t)NULL,
7237         .phy_specific_func = (phy_specific_func_t)NULL
7238 };
7239 static struct bnx2x_phy phy_8706 = {
7240         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7241         .addr           = 0xff,
7242         .def_md_devad   = 0,
7243         .flags          = FLAGS_INIT_XGXS_FIRST,
7244         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7245         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7246         .mdio_ctrl      = 0,
7247         .supported      = (SUPPORTED_10000baseT_Full |
7248                            SUPPORTED_1000baseT_Full |
7249                            SUPPORTED_FIBRE |
7250                            SUPPORTED_Pause |
7251                            SUPPORTED_Asym_Pause),
7252         .media_type     = ETH_PHY_SFP_FIBER,
7253         .ver_addr       = 0,
7254         .req_flow_ctrl  = 0,
7255         .req_line_speed = 0,
7256         .speed_cap_mask = 0,
7257         .req_duplex     = 0,
7258         .rsrv           = 0,
7259         .config_init    = (config_init_t)bnx2x_8706_config_init,
7260         .read_status    = (read_status_t)bnx2x_8706_read_status,
7261         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7262         .config_loopback = (config_loopback_t)NULL,
7263         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7264         .hw_reset       = (hw_reset_t)NULL,
7265         .set_link_led   = (set_link_led_t)NULL,
7266         .phy_specific_func = (phy_specific_func_t)NULL
7267 };
7268
7269 static struct bnx2x_phy phy_8726 = {
7270         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7271         .addr           = 0xff,
7272         .def_md_devad   = 0,
7273         .flags          = (FLAGS_HW_LOCK_REQUIRED |
7274                            FLAGS_INIT_XGXS_FIRST),
7275         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7276         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7277         .mdio_ctrl      = 0,
7278         .supported      = (SUPPORTED_10000baseT_Full |
7279                            SUPPORTED_1000baseT_Full |
7280                            SUPPORTED_Autoneg |
7281                            SUPPORTED_FIBRE |
7282                            SUPPORTED_Pause |
7283                            SUPPORTED_Asym_Pause),
7284         .media_type     = ETH_PHY_NOT_PRESENT,
7285         .ver_addr       = 0,
7286         .req_flow_ctrl  = 0,
7287         .req_line_speed = 0,
7288         .speed_cap_mask = 0,
7289         .req_duplex     = 0,
7290         .rsrv           = 0,
7291         .config_init    = (config_init_t)bnx2x_8726_config_init,
7292         .read_status    = (read_status_t)bnx2x_8726_read_status,
7293         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
7294         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7295         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7296         .hw_reset       = (hw_reset_t)NULL,
7297         .set_link_led   = (set_link_led_t)NULL,
7298         .phy_specific_func = (phy_specific_func_t)NULL
7299 };
7300
7301 static struct bnx2x_phy phy_8727 = {
7302         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7303         .addr           = 0xff,
7304         .def_md_devad   = 0,
7305         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7306         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7307         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7308         .mdio_ctrl      = 0,
7309         .supported      = (SUPPORTED_10000baseT_Full |
7310                            SUPPORTED_1000baseT_Full |
7311                            SUPPORTED_FIBRE |
7312                            SUPPORTED_Pause |
7313                            SUPPORTED_Asym_Pause),
7314         .media_type     = ETH_PHY_NOT_PRESENT,
7315         .ver_addr       = 0,
7316         .req_flow_ctrl  = 0,
7317         .req_line_speed = 0,
7318         .speed_cap_mask = 0,
7319         .req_duplex     = 0,
7320         .rsrv           = 0,
7321         .config_init    = (config_init_t)bnx2x_8727_config_init,
7322         .read_status    = (read_status_t)bnx2x_8727_read_status,
7323         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
7324         .config_loopback = (config_loopback_t)NULL,
7325         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7326         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
7327         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
7328         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
7329 };
7330 static struct bnx2x_phy phy_8481 = {
7331         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7332         .addr           = 0xff,
7333         .def_md_devad   = 0,
7334         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7335                           FLAGS_REARM_LATCH_SIGNAL,
7336         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7337         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7338         .mdio_ctrl      = 0,
7339         .supported      = (SUPPORTED_10baseT_Half |
7340                            SUPPORTED_10baseT_Full |
7341                            SUPPORTED_100baseT_Half |
7342                            SUPPORTED_100baseT_Full |
7343                            SUPPORTED_1000baseT_Full |
7344                            SUPPORTED_10000baseT_Full |
7345                            SUPPORTED_TP |
7346                            SUPPORTED_Autoneg |
7347                            SUPPORTED_Pause |
7348                            SUPPORTED_Asym_Pause),
7349         .media_type     = ETH_PHY_BASE_T,
7350         .ver_addr       = 0,
7351         .req_flow_ctrl  = 0,
7352         .req_line_speed = 0,
7353         .speed_cap_mask = 0,
7354         .req_duplex     = 0,
7355         .rsrv           = 0,
7356         .config_init    = (config_init_t)bnx2x_8481_config_init,
7357         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7358         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
7359         .config_loopback = (config_loopback_t)NULL,
7360         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7361         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
7362         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7363         .phy_specific_func = (phy_specific_func_t)NULL
7364 };
7365
7366 static struct bnx2x_phy phy_84823 = {
7367         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7368         .addr           = 0xff,
7369         .def_md_devad   = 0,
7370         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7371                           FLAGS_REARM_LATCH_SIGNAL,
7372         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7373         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7374         .mdio_ctrl      = 0,
7375         .supported      = (SUPPORTED_10baseT_Half |
7376                            SUPPORTED_10baseT_Full |
7377                            SUPPORTED_100baseT_Half |
7378                            SUPPORTED_100baseT_Full |
7379                            SUPPORTED_1000baseT_Full |
7380                            SUPPORTED_10000baseT_Full |
7381                            SUPPORTED_TP |
7382                            SUPPORTED_Autoneg |
7383                            SUPPORTED_Pause |
7384                            SUPPORTED_Asym_Pause),
7385         .media_type     = ETH_PHY_BASE_T,
7386         .ver_addr       = 0,
7387         .req_flow_ctrl  = 0,
7388         .req_line_speed = 0,
7389         .speed_cap_mask = 0,
7390         .req_duplex     = 0,
7391         .rsrv           = 0,
7392         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7393         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7394         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7395         .config_loopback = (config_loopback_t)NULL,
7396         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7397         .hw_reset       = (hw_reset_t)NULL,
7398         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7399         .phy_specific_func = (phy_specific_func_t)NULL
7400 };
7401
7402 static struct bnx2x_phy phy_84833 = {
7403         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7404         .addr           = 0xff,
7405         .def_md_devad   = 0,
7406         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7407                             FLAGS_REARM_LATCH_SIGNAL,
7408         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7409         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7410         .mdio_ctrl      = 0,
7411         .supported      = (SUPPORTED_10baseT_Half |
7412                            SUPPORTED_10baseT_Full |
7413                            SUPPORTED_100baseT_Half |
7414                            SUPPORTED_100baseT_Full |
7415                            SUPPORTED_1000baseT_Full |
7416                            SUPPORTED_10000baseT_Full |
7417                            SUPPORTED_TP |
7418                            SUPPORTED_Autoneg |
7419                            SUPPORTED_Pause |
7420                            SUPPORTED_Asym_Pause),
7421         .media_type     = ETH_PHY_BASE_T,
7422         .ver_addr       = 0,
7423         .req_flow_ctrl  = 0,
7424         .req_line_speed = 0,
7425         .speed_cap_mask = 0,
7426         .req_duplex     = 0,
7427         .rsrv           = 0,
7428         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7429         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7430         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7431         .config_loopback = (config_loopback_t)NULL,
7432         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7433         .hw_reset       = (hw_reset_t)NULL,
7434         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7435         .phy_specific_func = (phy_specific_func_t)NULL
7436 };
7437
7438 /*****************************************************************/
7439 /*                                                               */
7440 /* Populate the phy according. Main function: bnx2x_populate_phy   */
7441 /*                                                               */
7442 /*****************************************************************/
7443
7444 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7445                                      struct bnx2x_phy *phy, u8 port,
7446                                      u8 phy_index)
7447 {
7448         /* Get the 4 lanes xgxs config rx and tx */
7449         u32 rx = 0, tx = 0, i;
7450         for (i = 0; i < 2; i++) {
7451                 /*
7452                  * INT_PHY and EXT_PHY1 share the same value location in the
7453                  * shmem. When num_phys is greater than 1, than this value
7454                  * applies only to EXT_PHY1
7455                  */
7456                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7457                         rx = REG_RD(bp, shmem_base +
7458                                     offsetof(struct shmem_region,
7459                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7460
7461                         tx = REG_RD(bp, shmem_base +
7462                                     offsetof(struct shmem_region,
7463                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7464                 } else {
7465                         rx = REG_RD(bp, shmem_base +
7466                                     offsetof(struct shmem_region,
7467                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7468
7469                         tx = REG_RD(bp, shmem_base +
7470                                     offsetof(struct shmem_region,
7471                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7472                 }
7473
7474                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7475                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7476
7477                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7478                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7479         }
7480 }
7481
7482 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7483                                     u8 phy_index, u8 port)
7484 {
7485         u32 ext_phy_config = 0;
7486         switch (phy_index) {
7487         case EXT_PHY1:
7488                 ext_phy_config = REG_RD(bp, shmem_base +
7489                                               offsetof(struct shmem_region,
7490                         dev_info.port_hw_config[port].external_phy_config));
7491                 break;
7492         case EXT_PHY2:
7493                 ext_phy_config = REG_RD(bp, shmem_base +
7494                                               offsetof(struct shmem_region,
7495                         dev_info.port_hw_config[port].external_phy_config2));
7496                 break;
7497         default:
7498                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7499                 return -EINVAL;
7500         }
7501
7502         return ext_phy_config;
7503 }
7504 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7505                                   struct bnx2x_phy *phy)
7506 {
7507         u32 phy_addr;
7508         u32 chip_id;
7509         u32 switch_cfg = (REG_RD(bp, shmem_base +
7510                                        offsetof(struct shmem_region,
7511                         dev_info.port_feature_config[port].link_config)) &
7512                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
7513         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7514         switch (switch_cfg) {
7515         case SWITCH_CFG_1G:
7516                 phy_addr = REG_RD(bp,
7517                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
7518                                         port * 0x10);
7519                 *phy = phy_serdes;
7520                 break;
7521         case SWITCH_CFG_10G:
7522                 phy_addr = REG_RD(bp,
7523                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
7524                                         port * 0x18);
7525                 *phy = phy_xgxs;
7526                 break;
7527         default:
7528                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7529                 return -EINVAL;
7530         }
7531         phy->addr = (u8)phy_addr;
7532         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7533                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7534                                             port);
7535         if (CHIP_IS_E2(bp))
7536                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7537         else
7538                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7539
7540         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7541                    port, phy->addr, phy->mdio_ctrl);
7542
7543         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7544         return 0;
7545 }
7546
7547 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
7548                                   u8 phy_index,
7549                                   u32 shmem_base,
7550                                   u32 shmem2_base,
7551                                   u8 port,
7552                                   struct bnx2x_phy *phy)
7553 {
7554         u32 ext_phy_config, phy_type, config2;
7555         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7556         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7557                                                   phy_index, port);
7558         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7559         /* Select the phy type */
7560         switch (phy_type) {
7561         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7562                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7563                 *phy = phy_8073;
7564                 break;
7565         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7566                 *phy = phy_8705;
7567                 break;
7568         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7569                 *phy = phy_8706;
7570                 break;
7571         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7572                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7573                 *phy = phy_8726;
7574                 break;
7575         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7576                 /* BCM8727_NOC => BCM8727 no over current */
7577                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7578                 *phy = phy_8727;
7579                 phy->flags |= FLAGS_NOC;
7580                 break;
7581         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7582         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7583                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7584                 *phy = phy_8727;
7585                 break;
7586         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7587                 *phy = phy_8481;
7588                 break;
7589         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7590                 *phy = phy_84823;
7591                 break;
7592         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7593                 *phy = phy_84833;
7594                 break;
7595         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7596                 *phy = phy_7101;
7597                 break;
7598         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7599                 *phy = phy_null;
7600                 return -EINVAL;
7601         default:
7602                 *phy = phy_null;
7603                 return 0;
7604         }
7605
7606         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7607         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7608
7609         /*
7610          * The shmem address of the phy version is located on different
7611          * structures. In case this structure is too old, do not set
7612          * the address
7613          */
7614         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7615                                         dev_info.shared_hw_config.config2));
7616         if (phy_index == EXT_PHY1) {
7617                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7618                                 port_mb[port].ext_phy_fw_version);
7619
7620                 /* Check specific mdc mdio settings */
7621                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7622                         mdc_mdio_access = config2 &
7623                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7624         } else {
7625                 u32 size = REG_RD(bp, shmem2_base);
7626
7627                 if (size >
7628                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7629                         phy->ver_addr = shmem2_base +
7630                             offsetof(struct shmem2_region,
7631                                      ext_phy_fw_version2[port]);
7632                 }
7633                 /* Check specific mdc mdio settings */
7634                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7635                         mdc_mdio_access = (config2 &
7636                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7637                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7638                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7639         }
7640         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7641
7642         /*
7643          * In case mdc/mdio_access of the external phy is different than the
7644          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7645          * to prevent one port interfere with another port's CL45 operations.
7646          */
7647         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7648                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7649         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7650                    phy_type, port, phy_index);
7651         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
7652                    phy->addr, phy->mdio_ctrl);
7653         return 0;
7654 }
7655
7656 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7657                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7658 {
7659         int status = 0;
7660         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7661         if (phy_index == INT_PHY)
7662                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7663         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7664                                         port, phy);
7665         return status;
7666 }
7667
7668 static void bnx2x_phy_def_cfg(struct link_params *params,
7669                               struct bnx2x_phy *phy,
7670                               u8 phy_index)
7671 {
7672         struct bnx2x *bp = params->bp;
7673         u32 link_config;
7674         /* Populate the default phy configuration for MF mode */
7675         if (phy_index == EXT_PHY2) {
7676                 link_config = REG_RD(bp, params->shmem_base +
7677                                      offsetof(struct shmem_region, dev_info.
7678                         port_feature_config[params->port].link_config2));
7679                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7680                                              offsetof(struct shmem_region,
7681                                                       dev_info.
7682                         port_hw_config[params->port].speed_capability_mask2));
7683         } else {
7684                 link_config = REG_RD(bp, params->shmem_base +
7685                                      offsetof(struct shmem_region, dev_info.
7686                                 port_feature_config[params->port].link_config));
7687                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7688                                              offsetof(struct shmem_region,
7689                                                       dev_info.
7690                         port_hw_config[params->port].speed_capability_mask));
7691         }
7692         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7693                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7694
7695         phy->req_duplex = DUPLEX_FULL;
7696         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
7697         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7698                 phy->req_duplex = DUPLEX_HALF;
7699         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7700                 phy->req_line_speed = SPEED_10;
7701                 break;
7702         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7703                 phy->req_duplex = DUPLEX_HALF;
7704         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7705                 phy->req_line_speed = SPEED_100;
7706                 break;
7707         case PORT_FEATURE_LINK_SPEED_1G:
7708                 phy->req_line_speed = SPEED_1000;
7709                 break;
7710         case PORT_FEATURE_LINK_SPEED_2_5G:
7711                 phy->req_line_speed = SPEED_2500;
7712                 break;
7713         case PORT_FEATURE_LINK_SPEED_10G_CX4:
7714                 phy->req_line_speed = SPEED_10000;
7715                 break;
7716         default:
7717                 phy->req_line_speed = SPEED_AUTO_NEG;
7718                 break;
7719         }
7720
7721         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
7722         case PORT_FEATURE_FLOW_CONTROL_AUTO:
7723                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7724                 break;
7725         case PORT_FEATURE_FLOW_CONTROL_TX:
7726                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7727                 break;
7728         case PORT_FEATURE_FLOW_CONTROL_RX:
7729                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7730                 break;
7731         case PORT_FEATURE_FLOW_CONTROL_BOTH:
7732                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7733                 break;
7734         default:
7735                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7736                 break;
7737         }
7738 }
7739
7740 u32 bnx2x_phy_selection(struct link_params *params)
7741 {
7742         u32 phy_config_swapped, prio_cfg;
7743         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7744
7745         phy_config_swapped = params->multi_phy_config &
7746                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7747
7748         prio_cfg = params->multi_phy_config &
7749                         PORT_HW_CFG_PHY_SELECTION_MASK;
7750
7751         if (phy_config_swapped) {
7752                 switch (prio_cfg) {
7753                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7754                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7755                      break;
7756                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7757                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7758                      break;
7759                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7760                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7761                      break;
7762                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7763                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7764                      break;
7765                 }
7766         } else
7767                 return_cfg = prio_cfg;
7768
7769         return return_cfg;
7770 }
7771
7772
7773 int bnx2x_phy_probe(struct link_params *params)
7774 {
7775         u8 phy_index, actual_phy_idx, link_cfg_idx;
7776         u32 phy_config_swapped, sync_offset, media_types;
7777         struct bnx2x *bp = params->bp;
7778         struct bnx2x_phy *phy;
7779         params->num_phys = 0;
7780         DP(NETIF_MSG_LINK, "Begin phy probe\n");
7781         phy_config_swapped = params->multi_phy_config &
7782                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7783
7784         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7785               phy_index++) {
7786                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7787                 actual_phy_idx = phy_index;
7788                 if (phy_config_swapped) {
7789                         if (phy_index == EXT_PHY1)
7790                                 actual_phy_idx = EXT_PHY2;
7791                         else if (phy_index == EXT_PHY2)
7792                                 actual_phy_idx = EXT_PHY1;
7793                 }
7794                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7795                                " actual_phy_idx %x\n", phy_config_swapped,
7796                            phy_index, actual_phy_idx);
7797                 phy = &params->phy[actual_phy_idx];
7798                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7799                                        params->shmem2_base, params->port,
7800                                        phy) != 0) {
7801                         params->num_phys = 0;
7802                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7803                                    phy_index);
7804                         for (phy_index = INT_PHY;
7805                               phy_index < MAX_PHYS;
7806                               phy_index++)
7807                                 *phy = phy_null;
7808                         return -EINVAL;
7809                 }
7810                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7811                         break;
7812
7813                 sync_offset = params->shmem_base +
7814                         offsetof(struct shmem_region,
7815                         dev_info.port_hw_config[params->port].media_type);
7816                 media_types = REG_RD(bp, sync_offset);
7817
7818                 /*
7819                  * Update media type for non-PMF sync only for the first time
7820                  * In case the media type changes afterwards, it will be updated
7821                  * using the update_status function
7822                  */
7823                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7824                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7825                                      actual_phy_idx))) == 0) {
7826                         media_types |= ((phy->media_type &
7827                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7828                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7829                                  actual_phy_idx));
7830                 }
7831                 REG_WR(bp, sync_offset, media_types);
7832
7833                 bnx2x_phy_def_cfg(params, phy, phy_index);
7834                 params->num_phys++;
7835         }
7836
7837         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7838         return 0;
7839 }
7840
7841 void bnx2x_init_bmac_loopback(struct link_params *params,
7842                               struct link_vars *vars)
7843 {
7844         struct bnx2x *bp = params->bp;
7845                 vars->link_up = 1;
7846                 vars->line_speed = SPEED_10000;
7847                 vars->duplex = DUPLEX_FULL;
7848                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7849                 vars->mac_type = MAC_TYPE_BMAC;
7850
7851                 vars->phy_flags = PHY_XGXS_FLAG;
7852
7853                 bnx2x_xgxs_deassert(params);
7854
7855                 /* set bmac loopback */
7856                 bnx2x_bmac_enable(params, vars, 1);
7857
7858                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7859 }
7860
7861 void bnx2x_init_emac_loopback(struct link_params *params,
7862                               struct link_vars *vars)
7863 {
7864         struct bnx2x *bp = params->bp;
7865                 vars->link_up = 1;
7866                 vars->line_speed = SPEED_1000;
7867                 vars->duplex = DUPLEX_FULL;
7868                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7869                 vars->mac_type = MAC_TYPE_EMAC;
7870
7871                 vars->phy_flags = PHY_XGXS_FLAG;
7872
7873                 bnx2x_xgxs_deassert(params);
7874                 /* set bmac loopback */
7875                 bnx2x_emac_enable(params, vars, 1);
7876                 bnx2x_emac_program(params, vars);
7877                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7878 }
7879
7880 void bnx2x_init_xgxs_loopback(struct link_params *params,
7881                               struct link_vars *vars)
7882 {
7883         struct bnx2x *bp = params->bp;
7884                 vars->link_up = 1;
7885                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7886                 vars->duplex = DUPLEX_FULL;
7887         if (params->req_line_speed[0] == SPEED_1000)
7888                         vars->line_speed = SPEED_1000;
7889         else
7890                         vars->line_speed = SPEED_10000;
7891
7892
7893         bnx2x_xgxs_deassert(params);
7894         bnx2x_link_initialize(params, vars);
7895
7896         if (params->req_line_speed[0] == SPEED_1000) {
7897                 bnx2x_emac_program(params, vars);
7898                 bnx2x_emac_enable(params, vars, 0);
7899
7900         } else
7901                 bnx2x_bmac_enable(params, vars, 0);
7902
7903
7904                 if (params->loopback_mode == LOOPBACK_XGXS) {
7905                         /* set 10G XGXS loopback */
7906                         params->phy[INT_PHY].config_loopback(
7907                                 &params->phy[INT_PHY],
7908                                 params);
7909
7910                 } else {
7911                         /* set external phy loopback */
7912                         u8 phy_index;
7913                         for (phy_index = EXT_PHY1;
7914                               phy_index < params->num_phys; phy_index++) {
7915                                 if (params->phy[phy_index].config_loopback)
7916                                         params->phy[phy_index].config_loopback(
7917                                                 &params->phy[phy_index],
7918                                                 params);
7919                         }
7920                 }
7921                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7922
7923         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
7924 }
7925
7926 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7927 {
7928         struct bnx2x *bp = params->bp;
7929         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7930         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7931                    params->req_line_speed[0], params->req_flow_ctrl[0]);
7932         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7933                    params->req_line_speed[1], params->req_flow_ctrl[1]);
7934         vars->link_status = 0;
7935         vars->phy_link_up = 0;
7936         vars->link_up = 0;
7937         vars->line_speed = 0;
7938         vars->duplex = DUPLEX_FULL;
7939         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7940         vars->mac_type = MAC_TYPE_NONE;
7941         vars->phy_flags = 0;
7942
7943         /* disable attentions */
7944         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7945                        (NIG_MASK_XGXS0_LINK_STATUS |
7946                         NIG_MASK_XGXS0_LINK10G |
7947                         NIG_MASK_SERDES0_LINK_STATUS |
7948                         NIG_MASK_MI_INT));
7949
7950         bnx2x_emac_init(params, vars);
7951
7952         if (params->num_phys == 0) {
7953                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7954                 return -EINVAL;
7955         }
7956         set_phy_vars(params, vars);
7957
7958         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7959         switch (params->loopback_mode) {
7960         case LOOPBACK_BMAC:
7961                 bnx2x_init_bmac_loopback(params, vars);
7962                 break;
7963         case LOOPBACK_EMAC:
7964                 bnx2x_init_emac_loopback(params, vars);
7965                 break;
7966         case LOOPBACK_XGXS:
7967         case LOOPBACK_EXT_PHY:
7968                 bnx2x_init_xgxs_loopback(params, vars);
7969                 break;
7970         default:
7971                 /* No loopback */
7972                 if (params->switch_cfg == SWITCH_CFG_10G)
7973                         bnx2x_xgxs_deassert(params);
7974                 else
7975                         bnx2x_serdes_deassert(bp, params->port);
7976
7977                 bnx2x_link_initialize(params, vars);
7978                 msleep(30);
7979                 bnx2x_link_int_enable(params);
7980                 break;
7981         }
7982         return 0;
7983 }
7984
7985 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7986                      u8 reset_ext_phy)
7987 {
7988         struct bnx2x *bp = params->bp;
7989         u8 phy_index, port = params->port, clear_latch_ind = 0;
7990         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7991         /* disable attentions */
7992         vars->link_status = 0;
7993         bnx2x_update_mng(params, vars->link_status);
7994         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7995                        (NIG_MASK_XGXS0_LINK_STATUS |
7996                         NIG_MASK_XGXS0_LINK10G |
7997                         NIG_MASK_SERDES0_LINK_STATUS |
7998                         NIG_MASK_MI_INT));
7999
8000         /* activate nig drain */
8001         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
8002
8003         /* disable nig egress interface */
8004         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8005         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8006
8007         /* Stop BigMac rx */
8008         bnx2x_bmac_rx_disable(bp, port);
8009
8010         /* disable emac */
8011         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
8012
8013         msleep(10);
8014         /* The PHY reset is controlled by GPIO 1
8015          * Hold it as vars low
8016          */
8017          /* clear link led */
8018         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
8019
8020         if (reset_ext_phy) {
8021                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
8022                       phy_index++) {
8023                         if (params->phy[phy_index].link_reset)
8024                                 params->phy[phy_index].link_reset(
8025                                         &params->phy[phy_index],
8026                                         params);
8027                         if (params->phy[phy_index].flags &
8028                             FLAGS_REARM_LATCH_SIGNAL)
8029                                 clear_latch_ind = 1;
8030                 }
8031         }
8032
8033         if (clear_latch_ind) {
8034                 /* Clear latching indication */
8035                 bnx2x_rearm_latch_signal(bp, port, 0);
8036                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
8037                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
8038         }
8039         if (params->phy[INT_PHY].link_reset)
8040                 params->phy[INT_PHY].link_reset(
8041                         &params->phy[INT_PHY], params);
8042         /* reset BigMac */
8043         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8044                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
8045
8046         /* disable nig ingress interface */
8047         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
8048         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
8049         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8050         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8051         vars->link_up = 0;
8052         return 0;
8053 }
8054
8055 /****************************************************************************/
8056 /*                              Common function                             */
8057 /****************************************************************************/
8058 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
8059                                       u32 shmem_base_path[],
8060                                       u32 shmem2_base_path[], u8 phy_index,
8061                                       u32 chip_id)
8062 {
8063         struct bnx2x_phy phy[PORT_MAX];
8064         struct bnx2x_phy *phy_blk[PORT_MAX];
8065         u16 val;
8066         s8 port = 0;
8067         s8 port_of_path = 0;
8068         u32 swap_val, swap_override;
8069         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
8070         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
8071         port ^= (swap_val && swap_override);
8072         bnx2x_ext_phy_hw_reset(bp, port);
8073         /* PART1 - Reset both phys */
8074         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8075                 u32 shmem_base, shmem2_base;
8076                 /* In E2, same phy is using for port0 of the two paths */
8077                 if (CHIP_IS_E2(bp)) {
8078                         shmem_base = shmem_base_path[port];
8079                         shmem2_base = shmem2_base_path[port];
8080                         port_of_path = 0;
8081                 } else {
8082                         shmem_base = shmem_base_path[0];
8083                         shmem2_base = shmem2_base_path[0];
8084                         port_of_path = port;
8085                 }
8086
8087                 /* Extract the ext phy address for the port */
8088                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8089                                        port_of_path, &phy[port]) !=
8090                     0) {
8091                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
8092                         return -EINVAL;
8093                 }
8094                 /* disable attentions */
8095                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8096                                port_of_path*4,
8097                                (NIG_MASK_XGXS0_LINK_STATUS |
8098                                 NIG_MASK_XGXS0_LINK10G |
8099                                 NIG_MASK_SERDES0_LINK_STATUS |
8100                                 NIG_MASK_MI_INT));
8101
8102                 /* Need to take the phy out of low power mode in order
8103                         to write to access its registers */
8104                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8105                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8106                                port);
8107
8108                 /* Reset the phy */
8109                 bnx2x_cl45_write(bp, &phy[port],
8110                                  MDIO_PMA_DEVAD,
8111                                  MDIO_PMA_REG_CTRL,
8112                                  1<<15);
8113         }
8114
8115         /* Add delay of 150ms after reset */
8116         msleep(150);
8117
8118         if (phy[PORT_0].addr & 0x1) {
8119                 phy_blk[PORT_0] = &(phy[PORT_1]);
8120                 phy_blk[PORT_1] = &(phy[PORT_0]);
8121         } else {
8122                 phy_blk[PORT_0] = &(phy[PORT_0]);
8123                 phy_blk[PORT_1] = &(phy[PORT_1]);
8124         }
8125
8126         /* PART2 - Download firmware to both phys */
8127         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8128                 if (CHIP_IS_E2(bp))
8129                         port_of_path = 0;
8130                 else
8131                         port_of_path = port;
8132
8133                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8134                            phy_blk[port]->addr);
8135                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8136                                                       port_of_path))
8137                         return -EINVAL;
8138
8139                 /* Only set bit 10 = 1 (Tx power down) */
8140                 bnx2x_cl45_read(bp, phy_blk[port],
8141                                 MDIO_PMA_DEVAD,
8142                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8143
8144                 /* Phase1 of TX_POWER_DOWN reset */
8145                 bnx2x_cl45_write(bp, phy_blk[port],
8146                                  MDIO_PMA_DEVAD,
8147                                  MDIO_PMA_REG_TX_POWER_DOWN,
8148                                  (val | 1<<10));
8149         }
8150
8151         /*
8152          * Toggle Transmitter: Power down and then up with 600ms delay
8153          * between
8154          */
8155         msleep(600);
8156
8157         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
8158         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8159                 /* Phase2 of POWER_DOWN_RESET */
8160                 /* Release bit 10 (Release Tx power down) */
8161                 bnx2x_cl45_read(bp, phy_blk[port],
8162                                 MDIO_PMA_DEVAD,
8163                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8164
8165                 bnx2x_cl45_write(bp, phy_blk[port],
8166                                 MDIO_PMA_DEVAD,
8167                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
8168                 msleep(15);
8169
8170                 /* Read modify write the SPI-ROM version select register */
8171                 bnx2x_cl45_read(bp, phy_blk[port],
8172                                 MDIO_PMA_DEVAD,
8173                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
8174                 bnx2x_cl45_write(bp, phy_blk[port],
8175                                  MDIO_PMA_DEVAD,
8176                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
8177
8178                 /* set GPIO2 back to LOW */
8179                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8180                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8181         }
8182         return 0;
8183 }
8184 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
8185                                       u32 shmem_base_path[],
8186                                       u32 shmem2_base_path[], u8 phy_index,
8187                                       u32 chip_id)
8188 {
8189         u32 val;
8190         s8 port;
8191         struct bnx2x_phy phy;
8192         /* Use port1 because of the static port-swap */
8193         /* Enable the module detection interrupt */
8194         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8195         val |= ((1<<MISC_REGISTERS_GPIO_3)|
8196                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
8197         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8198
8199         bnx2x_ext_phy_hw_reset(bp, 0);
8200         msleep(5);
8201         for (port = 0; port < PORT_MAX; port++) {
8202                 u32 shmem_base, shmem2_base;
8203
8204                 /* In E2, same phy is using for port0 of the two paths */
8205                 if (CHIP_IS_E2(bp)) {
8206                         shmem_base = shmem_base_path[port];
8207                         shmem2_base = shmem2_base_path[port];
8208                 } else {
8209                         shmem_base = shmem_base_path[0];
8210                         shmem2_base = shmem2_base_path[0];
8211                 }
8212                 /* Extract the ext phy address for the port */
8213                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8214                                        port, &phy) !=
8215                     0) {
8216                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8217                         return -EINVAL;
8218                 }
8219
8220                 /* Reset phy*/
8221                 bnx2x_cl45_write(bp, &phy,
8222                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8223
8224
8225                 /* Set fault module detected LED on */
8226                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8227                                MISC_REGISTERS_GPIO_HIGH,
8228                                port);
8229         }
8230
8231         return 0;
8232 }
8233 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8234                                          u8 *io_gpio, u8 *io_port)
8235 {
8236
8237         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8238                                           offsetof(struct shmem_region,
8239                                 dev_info.port_hw_config[PORT_0].default_cfg));
8240         switch (phy_gpio_reset) {
8241         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8242                 *io_gpio = 0;
8243                 *io_port = 0;
8244                 break;
8245         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8246                 *io_gpio = 1;
8247                 *io_port = 0;
8248                 break;
8249         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8250                 *io_gpio = 2;
8251                 *io_port = 0;
8252                 break;
8253         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8254                 *io_gpio = 3;
8255                 *io_port = 0;
8256                 break;
8257         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8258                 *io_gpio = 0;
8259                 *io_port = 1;
8260                 break;
8261         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8262                 *io_gpio = 1;
8263                 *io_port = 1;
8264                 break;
8265         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8266                 *io_gpio = 2;
8267                 *io_port = 1;
8268                 break;
8269         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8270                 *io_gpio = 3;
8271                 *io_port = 1;
8272                 break;
8273         default:
8274                 /* Don't override the io_gpio and io_port */
8275                 break;
8276         }
8277 }
8278
8279 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
8280                                       u32 shmem_base_path[],
8281                                       u32 shmem2_base_path[], u8 phy_index,
8282                                       u32 chip_id)
8283 {
8284         s8 port, reset_gpio;
8285         u32 swap_val, swap_override;
8286         struct bnx2x_phy phy[PORT_MAX];
8287         struct bnx2x_phy *phy_blk[PORT_MAX];
8288         s8 port_of_path;
8289         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8290         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8291
8292         reset_gpio = MISC_REGISTERS_GPIO_1;
8293         port = 1;
8294
8295         /*
8296          * Retrieve the reset gpio/port which control the reset.
8297          * Default is GPIO1, PORT1
8298          */
8299         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8300                                      (u8 *)&reset_gpio, (u8 *)&port);
8301
8302         /* Calculate the port based on port swap */
8303         port ^= (swap_val && swap_override);
8304
8305         /* Initiate PHY reset*/
8306         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8307                        port);
8308         msleep(1);
8309         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8310                        port);
8311
8312         msleep(5);
8313
8314         /* PART1 - Reset both phys */
8315         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8316                 u32 shmem_base, shmem2_base;
8317
8318                 /* In E2, same phy is using for port0 of the two paths */
8319                 if (CHIP_IS_E2(bp)) {
8320                         shmem_base = shmem_base_path[port];
8321                         shmem2_base = shmem2_base_path[port];
8322                         port_of_path = 0;
8323                 } else {
8324                         shmem_base = shmem_base_path[0];
8325                         shmem2_base = shmem2_base_path[0];
8326                         port_of_path = port;
8327                 }
8328
8329                 /* Extract the ext phy address for the port */
8330                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8331                                        port_of_path, &phy[port]) !=
8332                                        0) {
8333                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8334                         return -EINVAL;
8335                 }
8336                 /* disable attentions */
8337                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8338                                port_of_path*4,
8339                                (NIG_MASK_XGXS0_LINK_STATUS |
8340                                 NIG_MASK_XGXS0_LINK10G |
8341                                 NIG_MASK_SERDES0_LINK_STATUS |
8342                                 NIG_MASK_MI_INT));
8343
8344
8345                 /* Reset the phy */
8346                 bnx2x_cl45_write(bp, &phy[port],
8347                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8348         }
8349
8350         /* Add delay of 150ms after reset */
8351         msleep(150);
8352         if (phy[PORT_0].addr & 0x1) {
8353                 phy_blk[PORT_0] = &(phy[PORT_1]);
8354                 phy_blk[PORT_1] = &(phy[PORT_0]);
8355         } else {
8356                 phy_blk[PORT_0] = &(phy[PORT_0]);
8357                 phy_blk[PORT_1] = &(phy[PORT_1]);
8358         }
8359         /* PART2 - Download firmware to both phys */
8360         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8361                 if (CHIP_IS_E2(bp))
8362                         port_of_path = 0;
8363                 else
8364                         port_of_path = port;
8365                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8366                            phy_blk[port]->addr);
8367                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8368                                                       port_of_path))
8369                         return -EINVAL;
8370
8371         }
8372         return 0;
8373 }
8374
8375 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8376                                      u32 shmem2_base_path[], u8 phy_index,
8377                                      u32 ext_phy_type, u32 chip_id)
8378 {
8379         int rc = 0;
8380
8381         switch (ext_phy_type) {
8382         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8383                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8384                                                 shmem2_base_path,
8385                                                 phy_index, chip_id);
8386                 break;
8387         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8388         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8389         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
8390                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8391                                                 shmem2_base_path,
8392                                                 phy_index, chip_id);
8393                 break;
8394
8395         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8396                 /*
8397                  * GPIO1 affects both ports, so there's need to pull
8398                  * it for single port alone
8399                  */
8400                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8401                                                 shmem2_base_path,
8402                                                 phy_index, chip_id);
8403                 break;
8404         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8405                 rc = -EINVAL;
8406                 break;
8407         default:
8408                 DP(NETIF_MSG_LINK,
8409                            "ext_phy 0x%x common init not required\n",
8410                            ext_phy_type);
8411                 break;
8412         }
8413
8414         if (rc != 0)
8415                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
8416                                       " Port %d\n",
8417                          0);
8418         return rc;
8419 }
8420
8421 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8422                           u32 shmem2_base_path[], u32 chip_id)
8423 {
8424         int rc = 0;
8425         u32 phy_ver;
8426         u8 phy_index;
8427         u32 ext_phy_type, ext_phy_config;
8428         DP(NETIF_MSG_LINK, "Begin common phy init\n");
8429
8430         /* Check if common init was already done */
8431         phy_ver = REG_RD(bp, shmem_base_path[0] +
8432                          offsetof(struct shmem_region,
8433                                   port_mb[PORT_0].ext_phy_fw_version));
8434         if (phy_ver) {
8435                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8436                                phy_ver);
8437                 return 0;
8438         }
8439
8440         /* Read the ext_phy_type for arbitrary port(0) */
8441         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8442               phy_index++) {
8443                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
8444                                                           shmem_base_path[0],
8445                                                           phy_index, 0);
8446                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8447                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8448                                                 shmem2_base_path,
8449                                                 phy_index, ext_phy_type,
8450                                                 chip_id);
8451         }
8452         return rc;
8453 }
8454
8455 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
8456 {
8457         u8 phy_index;
8458         struct bnx2x_phy phy;
8459         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8460               phy_index++) {
8461                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8462                                        0, &phy) != 0) {
8463                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8464                         return 0;
8465                 }
8466
8467                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8468                         return 1;
8469         }
8470         return 0;
8471 }
8472
8473 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8474                              u32 shmem_base,
8475                              u32 shmem2_base,
8476                              u8 port)
8477 {
8478         u8 phy_index, fan_failure_det_req = 0;
8479         struct bnx2x_phy phy;
8480         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8481               phy_index++) {
8482                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8483                                        port, &phy)
8484                     != 0) {
8485                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8486                         return 0;
8487                 }
8488                 fan_failure_det_req |= (phy.flags &
8489                                         FLAGS_FAN_FAILURE_DET_REQ);
8490         }
8491         return fan_failure_det_req;
8492 }
8493
8494 void bnx2x_hw_reset_phy(struct link_params *params)
8495 {
8496         u8 phy_index;
8497         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8498               phy_index++) {
8499                 if (params->phy[phy_index].hw_reset) {
8500                         params->phy[phy_index].hw_reset(
8501                                 &params->phy[phy_index],
8502                                 params);
8503                         params->phy[phy_index] = phy_null;
8504                 }
8505         }
8506 }
8507
8508 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
8509                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
8510                             u8 port)
8511 {
8512         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
8513         u32 val;
8514         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
8515
8516         {
8517                 struct bnx2x_phy phy;
8518                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8519                       phy_index++) {
8520                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
8521                                                shmem2_base, port, &phy)
8522                             != 0) {
8523                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
8524                                 return;
8525                         }
8526                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
8527                                 gpio_num = MISC_REGISTERS_GPIO_3;
8528                                 gpio_port = port;
8529                                 break;
8530                         }
8531                 }
8532         }
8533
8534         if (gpio_num == 0xff)
8535                 return;
8536
8537         /* Set GPIO3 to trigger SFP+ module insertion/removal */
8538         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
8539
8540         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8541         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8542         gpio_port ^= (swap_val && swap_override);
8543
8544         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
8545                 (gpio_num + (gpio_port << 2));
8546
8547         sync_offset = shmem_base +
8548                 offsetof(struct shmem_region,
8549                          dev_info.port_hw_config[port].aeu_int_mask);
8550         REG_WR(bp, sync_offset, vars->aeu_int_mask);
8551
8552         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
8553                        gpio_num, gpio_port, vars->aeu_int_mask);
8554
8555         if (port == 0)
8556                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8557         else
8558                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
8559
8560         /* Open appropriate AEU for interrupts */
8561         aeu_mask = REG_RD(bp, offset);
8562         aeu_mask |= vars->aeu_int_mask;
8563         REG_WR(bp, offset, aeu_mask);
8564
8565         /* Enable the GPIO to trigger interrupt */
8566         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8567         val |= 1 << (gpio_num + (gpio_port << 2));
8568         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8569 }