1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
31 /********************************************************/
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
41 #define I2C_SWITCH_WIDTH 2
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
48 /***********************************************************/
49 /* Shortcut definitions */
50 /***********************************************************/
52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
54 #define NIG_STATUS_EMAC0_MI_INT \
55 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
56 #define NIG_STATUS_XGXS0_LINK10G \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
58 #define NIG_STATUS_XGXS0_LINK_STATUS \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
62 #define NIG_STATUS_SERDES0_LINK_STATUS \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
64 #define NIG_MASK_MI_INT \
65 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
66 #define NIG_MASK_XGXS0_LINK10G \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
68 #define NIG_MASK_XGXS0_LINK_STATUS \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
70 #define NIG_MASK_SERDES0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
73 #define MDIO_AN_CL73_OR_37_COMPLETE \
74 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
75 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
77 #define XGXS_RESET_BITS \
78 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
84 #define SERDES_RESET_BITS \
85 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
90 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
91 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
92 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
93 #define AUTONEG_PARALLEL \
94 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
95 #define AUTONEG_SGMII_FIBER_AUTODET \
96 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
97 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
103 #define GP_STATUS_SPEED_MASK \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
105 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
106 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
107 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
108 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
109 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
110 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
111 #define GP_STATUS_10G_HIG \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
113 #define GP_STATUS_10G_CX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
116 #define GP_STATUS_10G_KX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
119 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
121 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
122 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
123 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
124 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
125 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
126 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
127 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
128 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
129 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
130 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
131 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
132 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
133 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
134 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
135 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
136 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB thresholds for E2*/
165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
177 /* BRB thresholds for E3A0 */
178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
191 /* BRB thresholds for E3B0 2 port mode*/
192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
208 /* Lossy +Lossless GUARANTIED == GUART */
209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
210 /* Lossless +Lossless*/
211 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
217 /* Lossless +Lossless*/
218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
226 /* BRB thresholds for E3B0 4 port mode */
227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
243 #define PFC_E3B0_4P_LB_GUART 120
245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
251 #define DCBX_INVALID_COS (0xFF)
253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
254 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
257 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
259 #define MAX_PACKET_SIZE (9700)
260 #define WC_UC_TIMEOUT 100
262 /**********************************************************/
264 /**********************************************************/
266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
267 bnx2x_cl45_write(_bp, _phy, \
268 (_phy)->def_md_devad, \
269 (_bank + (_addr & 0xf)), \
272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
273 bnx2x_cl45_read(_bp, _phy, \
274 (_phy)->def_md_devad, \
275 (_bank + (_addr & 0xf)), \
278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
280 u32 val = REG_RD(bp, reg);
283 REG_WR(bp, reg, val);
287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
289 u32 val = REG_RD(bp, reg);
292 REG_WR(bp, reg, val);
296 /******************************************************************/
297 /* EPIO/GPIO section */
298 /******************************************************************/
299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
301 u32 epio_mask, gp_oenable;
305 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
309 epio_mask = 1 << epio_pin;
310 /* Set this EPIO to output */
311 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
312 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
314 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
318 u32 epio_mask, gp_output, gp_oenable;
322 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
325 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
326 epio_mask = 1 << epio_pin;
327 /* Set this EPIO to output */
328 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
330 gp_output |= epio_mask;
332 gp_output &= ~epio_mask;
334 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
336 /* Set the value for this EPIO */
337 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
338 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
343 if (pin_cfg == PIN_CFG_NA)
345 if (pin_cfg >= PIN_CFG_EPIO0) {
346 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
348 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
349 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
350 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
356 if (pin_cfg == PIN_CFG_NA)
358 if (pin_cfg >= PIN_CFG_EPIO0) {
359 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
361 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
362 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
363 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
368 /******************************************************************/
370 /******************************************************************/
371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
373 /* ETS disabled configuration*/
374 struct bnx2x *bp = params->bp;
376 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
379 * mapping between entry priority to client number (0,1,2 -debug and
380 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
382 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
383 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
386 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
388 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
389 * as strict. Bits 0,1,2 - debug and management entries, 3 -
390 * COS0 entry, 4 - COS1 entry.
391 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
392 * bit4 bit3 bit2 bit1 bit0
393 * MCP and debug are strict
396 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
397 /* defines which entries (clients) are subjected to WFQ arbitration */
398 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
400 * For strict priority entries defines the number of consecutive
401 * slots for the highest priority.
403 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
405 * mapping between the CREDIT_WEIGHT registers and actual client
408 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
409 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
410 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
412 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
413 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
414 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
415 /* ETS mode disable */
416 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
418 * If ETS mode is enabled (there is no strict priority) defines a WFQ
419 * weight for COS0/COS1.
421 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
422 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
423 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
424 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
425 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
426 /* Defines the number of consecutive slots for the strict priority */
427 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
429 /******************************************************************************
431 * Getting min_w_val will be set according to line speed .
433 ******************************************************************************/
434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
437 /* Calculate min_w_val.*/
439 if (SPEED_20000 == vars->line_speed)
440 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
442 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
444 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
446 * If the link isn't up (static configuration for example ) The
447 * link will be according to 20GBPS.
451 /******************************************************************************
453 * Getting credit upper bound form min_w_val.
455 ******************************************************************************/
456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
458 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
460 return credit_upper_bound;
462 /******************************************************************************
464 * Set credit upper bound for NIG.
466 ******************************************************************************/
467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
468 const struct link_params *params,
471 struct bnx2x *bp = params->bp;
472 const u8 port = params->port;
473 const u32 credit_upper_bound =
474 bnx2x_ets_get_credit_upper_bound(min_w_val);
476 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
477 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
478 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
479 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
480 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
481 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
482 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
483 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
484 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
485 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
486 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
487 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
490 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
492 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
494 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
498 /******************************************************************************
500 * Will return the NIG ETS registers to init values.Except
501 * credit_upper_bound.
502 * That isn't used in this configuration (No WFQ is enabled) and will be
503 * configured acording to spec
505 ******************************************************************************/
506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
507 const struct link_vars *vars)
509 struct bnx2x *bp = params->bp;
510 const u8 port = params->port;
511 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
513 * mapping between entry priority to client number (0,1,2 -debug and
514 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
515 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
516 * reset value or init tool
519 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
520 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
522 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
526 * For strict priority entries defines the number of consecutive
527 * slots for the highest priority.
529 /* TODO_ETS - Should be done by reset value or init tool */
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
531 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
533 * mapping between the CREDIT_WEIGHT registers and actual client
536 /* TODO_ETS - Should be done by reset value or init tool */
539 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
540 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
549 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
550 * as strict. Bits 0,1,2 - debug and management entries, 3 -
551 * COS0 entry, 4 - COS1 entry.
552 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
553 * bit4 bit3 bit2 bit1 bit0
554 * MCP and debug are strict
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
560 /* defines which entries (clients) are subjected to WFQ arbitration */
561 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
562 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
565 * Please notice the register address are note continuous and a
566 * for here is note appropriate.In 2 port mode port0 only COS0-5
567 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
568 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
569 * are never used for WFQ
571 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
572 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
573 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
574 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
575 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
578 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
579 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
581 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
582 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
584 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
586 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
589 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
591 /******************************************************************************
593 * Set credit upper bound for PBF.
595 ******************************************************************************/
596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
597 const struct link_params *params,
600 struct bnx2x *bp = params->bp;
601 const u32 credit_upper_bound =
602 bnx2x_ets_get_credit_upper_bound(min_w_val);
603 const u8 port = params->port;
604 u32 base_upper_bound = 0;
608 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
609 * port mode port1 has COS0-2 that can be used for WFQ.
612 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
613 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
615 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
616 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
619 for (i = 0; i < max_cos; i++)
620 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
623 /******************************************************************************
625 * Will return the PBF ETS registers to init values.Except
626 * credit_upper_bound.
627 * That isn't used in this configuration (No WFQ is enabled) and will be
628 * configured acording to spec
630 ******************************************************************************/
631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
633 struct bnx2x *bp = params->bp;
634 const u8 port = params->port;
635 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
641 * mapping between entry priority to client number 0 - COS0
642 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
643 * TODO_ETS - Should be done by reset value or init tool
646 /* 0x688 (|011|0 10|00 1|000) */
647 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
649 /* (10 1|100 |011|0 10|00 1|000) */
650 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
652 /* TODO_ETS - Should be done by reset value or init tool */
654 /* 0x688 (|011|0 10|00 1|000)*/
655 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
657 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
658 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
660 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
661 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
664 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
665 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
667 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
668 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
670 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
671 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
674 base_weight = PBF_REG_COS0_WEIGHT_P0;
675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
677 base_weight = PBF_REG_COS0_WEIGHT_P1;
678 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
681 for (i = 0; i < max_cos; i++)
682 REG_WR(bp, base_weight + (0x4 * i), 0);
684 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
686 /******************************************************************************
688 * E3B0 disable will return basicly the values to init values.
690 ******************************************************************************/
691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
692 const struct link_vars *vars)
694 struct bnx2x *bp = params->bp;
696 if (!CHIP_IS_E3B0(bp)) {
697 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
702 bnx2x_ets_e3b0_nig_disabled(params, vars);
704 bnx2x_ets_e3b0_pbf_disabled(params);
709 /******************************************************************************
711 * Disable will return basicly the values to init values.
713 ******************************************************************************/
714 int bnx2x_ets_disabled(struct link_params *params,
715 struct link_vars *vars)
717 struct bnx2x *bp = params->bp;
718 int bnx2x_status = 0;
720 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
721 bnx2x_ets_e2e3a0_disabled(params);
722 else if (CHIP_IS_E3B0(bp))
723 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
725 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
732 /******************************************************************************
734 * Set the COS mappimg to SP and BW until this point all the COS are not
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
738 const struct bnx2x_ets_params *ets_params,
739 const u8 cos_sp_bitmap,
740 const u8 cos_bw_bitmap)
742 struct bnx2x *bp = params->bp;
743 const u8 port = params->port;
744 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
745 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
746 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
747 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
749 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
750 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
752 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
753 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
755 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
756 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
757 nig_cli_subject2wfq_bitmap);
759 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
760 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
761 pbf_cli_subject2wfq_bitmap);
766 /******************************************************************************
768 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
769 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
770 ******************************************************************************/
771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
773 const u32 min_w_val_nig,
774 const u32 min_w_val_pbf,
779 u32 nig_reg_adress_crd_weight = 0;
780 u32 pbf_reg_adress_crd_weight = 0;
781 /* Calculate and set BW for this COS*/
782 const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
783 const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
787 nig_reg_adress_crd_weight =
788 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
789 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
790 pbf_reg_adress_crd_weight = (port) ?
791 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
794 nig_reg_adress_crd_weight = (port) ?
795 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
796 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
797 pbf_reg_adress_crd_weight = (port) ?
798 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
801 nig_reg_adress_crd_weight = (port) ?
802 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
803 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
805 pbf_reg_adress_crd_weight = (port) ?
806 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
811 nig_reg_adress_crd_weight =
812 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
813 pbf_reg_adress_crd_weight =
814 PBF_REG_COS3_WEIGHT_P0;
819 nig_reg_adress_crd_weight =
820 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
821 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
826 nig_reg_adress_crd_weight =
827 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
828 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
832 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
834 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
838 /******************************************************************************
840 * Calculate the total BW.A value of 0 isn't legal.
842 ******************************************************************************/
843 static int bnx2x_ets_e3b0_get_total_bw(
844 const struct link_params *params,
845 const struct bnx2x_ets_params *ets_params,
848 struct bnx2x *bp = params->bp;
852 /* Calculate total BW requested */
853 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
854 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
856 if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
857 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
862 ets_params->cos[cos_idx].params.bw_params.bw;
866 /*Check taotl BW is valid */
867 if ((100 != *total_bw) || (0 == *total_bw)) {
868 if (0 == *total_bw) {
869 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
873 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
876 * We can handle a case whre the BW isn't 100 this can happen
877 * if the TC are joined.
883 /******************************************************************************
885 * Invalidate all the sp_pri_to_cos.
887 ******************************************************************************/
888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
891 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
892 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
894 /******************************************************************************
896 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
897 * according to sp_pri_to_cos.
899 ******************************************************************************/
900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
901 u8 *sp_pri_to_cos, const u8 pri,
904 struct bnx2x *bp = params->bp;
905 const u8 port = params->port;
906 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
907 DCBX_E3B0_MAX_NUM_COS_PORT0;
909 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
910 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
911 "parameter There can't be two COS's with"
912 "the same strict pri\n");
916 if (pri > max_num_of_cos) {
917 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
918 "parameter Illegal strict priority\n");
922 sp_pri_to_cos[pri] = cos_entry;
927 /******************************************************************************
929 * Returns the correct value according to COS and priority in
930 * the sp_pri_cli register.
932 ******************************************************************************/
933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
939 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
940 (pri_set + pri_offset));
944 /******************************************************************************
946 * Returns the correct value according to COS and priority in the
947 * sp_pri_cli register for NIG.
949 ******************************************************************************/
950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
952 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
953 const u8 nig_cos_offset = 3;
954 const u8 nig_pri_offset = 3;
956 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
960 /******************************************************************************
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for PBF.
965 ******************************************************************************/
966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
968 const u8 pbf_cos_offset = 0;
969 const u8 pbf_pri_offset = 0;
971 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
976 /******************************************************************************
978 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
979 * according to sp_pri_to_cos.(which COS has higher priority)
981 ******************************************************************************/
982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
985 struct bnx2x *bp = params->bp;
987 const u8 port = params->port;
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
989 u64 pri_cli_nig = 0x210;
990 u32 pri_cli_pbf = 0x0;
993 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
994 DCBX_E3B0_MAX_NUM_COS_PORT0;
996 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
998 /* Set all the strict priority first */
999 for (i = 0; i < max_num_of_cos; i++) {
1000 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1003 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004 "invalid cos entry\n");
1008 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009 sp_pri_to_cos[i], pri_set);
1011 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012 sp_pri_to_cos[i], pri_set);
1013 pri_bitmask = 1 << sp_pri_to_cos[i];
1014 /* COS is used remove it from bitmap.*/
1015 if (0 == (pri_bitmask & cos_bit_to_set)) {
1017 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018 "invalid There can't be two COS's with"
1019 " the same strict pri\n");
1022 cos_bit_to_set &= ~pri_bitmask;
1027 /* Set all the Non strict priority i= COS*/
1028 for (i = 0; i < max_num_of_cos; i++) {
1029 pri_bitmask = 1 << i;
1030 /* Check if COS was already used for SP */
1031 if (pri_bitmask & cos_bit_to_set) {
1032 /* COS wasn't used for SP */
1033 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1036 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1038 /* COS is used remove it from bitmap.*/
1039 cos_bit_to_set &= ~pri_bitmask;
1044 if (pri_set != max_num_of_cos) {
1045 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046 "entries were set\n");
1051 /* Only 6 usable clients*/
1052 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1055 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1057 /* Only 9 usable clients*/
1058 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1061 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1063 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1066 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1071 /******************************************************************************
1073 * Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076 const struct link_vars *vars,
1077 const struct bnx2x_ets_params *ets_params)
1079 struct bnx2x *bp = params->bp;
1080 int bnx2x_status = 0;
1081 const u8 port = params->port;
1083 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085 u8 cos_bw_bitmap = 0;
1086 u8 cos_sp_bitmap = 0;
1087 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089 DCBX_E3B0_MAX_NUM_COS_PORT0;
1092 if (!CHIP_IS_E3B0(bp)) {
1093 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1098 if ((ets_params->num_of_cos > max_num_of_cos)) {
1099 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100 "isn't supported\n");
1104 /* Prepare sp strict priority parameters*/
1105 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1107 /* Prepare BW parameters*/
1108 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1110 if (0 != bnx2x_status) {
1111 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1117 * Upper bound is set according to current link speed (min_w_val
1118 * should be the same for upper bound and COS credit val).
1120 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1124 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126 cos_bw_bitmap |= (1 << cos_entry);
1128 * The function also sets the BW in HW(not the mappin
1131 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1134 ets_params->cos[cos_entry].params.bw_params.bw,
1136 } else if (bnx2x_cos_state_strict ==
1137 ets_params->cos[cos_entry].state){
1138 cos_sp_bitmap |= (1 << cos_entry);
1140 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1143 ets_params->cos[cos_entry].params.sp_params.pri,
1147 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1151 if (0 != bnx2x_status) {
1152 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1154 return bnx2x_status;
1158 /* Set SP register (which COS has higher priority) */
1159 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1162 if (0 != bnx2x_status) {
1163 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1165 return bnx2x_status;
1168 /* Set client mapping of BW and strict */
1169 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1173 if (0 != bnx2x_status) {
1174 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175 return bnx2x_status;
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1181 /* ETS disabled configuration */
1182 struct bnx2x *bp = params->bp;
1183 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1185 * defines which entries (clients) are subjected to WFQ arbitration
1189 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1191 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192 * client numbers (WEIGHT_0 does not actually have to represent
1194 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1195 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1197 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1199 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1204 /* ETS mode enabled*/
1205 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1207 /* Defines the number of consecutive slots for the strict priority */
1208 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1210 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1212 * entry, 4 - COS1 entry.
1213 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214 * bit4 bit3 bit2 bit1 bit0
1215 * MCP and debug are strict
1217 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1219 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1229 /* ETS disabled configuration*/
1230 struct bnx2x *bp = params->bp;
1231 const u32 total_bw = cos0_bw + cos1_bw;
1232 u32 cos0_credit_weight = 0;
1233 u32 cos1_credit_weight = 0;
1235 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1237 if ((0 == total_bw) ||
1240 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1244 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1246 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1249 bnx2x_ets_bw_limit_common(params);
1251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1254 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1260 /* ETS disabled configuration*/
1261 struct bnx2x *bp = params->bp;
1264 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1266 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267 * as strict. Bits 0,1,2 - debug and management entries,
1268 * 3 - COS0 entry, 4 - COS1 entry.
1269 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270 * bit4 bit3 bit2 bit1 bit0
1271 * MCP and debug are strict
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1275 * For strict priority entries defines the number of consecutive slots
1276 * for the highest priority.
1278 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279 /* ETS mode disable */
1280 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281 /* Defines the number of consecutive slots for the strict priority */
1282 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1284 /* Defines the number of consecutive slots for the strict priority */
1285 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1288 * mapping between entry priority to client number (0,1,2 -debug and
1289 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1291 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1292 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1293 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1295 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1300 /******************************************************************/
1302 /******************************************************************/
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305 struct link_vars *vars,
1308 struct bnx2x *bp = params->bp;
1310 u32 pause_val, pfc0_val, pfc1_val;
1312 /* XMAC base adrr */
1313 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1315 /* Initialize pause and pfc registers */
1316 pause_val = 0x18000;
1317 pfc0_val = 0xFFFF8000;
1320 /* No PFC support */
1321 if (!(params->feature_config_flags &
1322 FEATURE_CONFIG_PFC_ENABLED)) {
1325 * RX flow control - Process pause frame in receive direction
1327 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1331 * TX flow control - Send pause packet when buffer is full
1333 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335 } else {/* PFC support */
1336 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1342 /* Write pause and PFC registers */
1343 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1351 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
1352 u32 pfc_frames_sent[2],
1353 u32 pfc_frames_received[2])
1355 /* Read pfc statistic */
1356 struct bnx2x *bp = params->bp;
1357 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1358 NIG_REG_INGRESS_BMAC0_MEM;
1360 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
1362 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
1363 pfc_frames_sent, 2);
1365 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
1366 pfc_frames_received, 2);
1369 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1370 u32 pfc_frames_sent[2],
1371 u32 pfc_frames_received[2])
1373 /* Read pfc statistic */
1374 struct bnx2x *bp = params->bp;
1375 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1379 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1381 /* PFC received frames */
1382 val_xoff = REG_RD(bp, emac_base +
1383 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1384 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1385 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1386 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1388 pfc_frames_received[0] = val_xon + val_xoff;
1390 /* PFC received sent */
1391 val_xoff = REG_RD(bp, emac_base +
1392 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1393 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1394 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1395 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1397 pfc_frames_sent[0] = val_xon + val_xoff;
1400 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1401 u32 pfc_frames_sent[2],
1402 u32 pfc_frames_received[2])
1404 /* Read pfc statistic */
1405 struct bnx2x *bp = params->bp;
1407 DP(NETIF_MSG_LINK, "pfc statistic\n");
1412 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1413 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1415 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
1416 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1417 pfc_frames_received);
1419 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
1420 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
1421 pfc_frames_received);
1424 /******************************************************************/
1425 /* MAC/PBF section */
1426 /******************************************************************/
1427 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1429 u32 mode, emac_base;
1431 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1432 * (a value of 49==0x31) and make sure that the AUTO poll is off
1436 emac_base = GRCBASE_EMAC0;
1438 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1439 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1440 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1441 EMAC_MDIO_MODE_CLOCK_CNT);
1442 if (USES_WARPCORE(bp))
1443 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1445 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1447 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1448 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1453 static void bnx2x_emac_init(struct link_params *params,
1454 struct link_vars *vars)
1456 /* reset and unreset the emac core */
1457 struct bnx2x *bp = params->bp;
1458 u8 port = params->port;
1459 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1463 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1464 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1466 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1467 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1469 /* init emac - use read-modify-write */
1470 /* self clear reset */
1471 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1472 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1476 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1477 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1479 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1483 } while (val & EMAC_MODE_RESET);
1484 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1485 /* Set mac address */
1486 val = ((params->mac_addr[0] << 8) |
1487 params->mac_addr[1]);
1488 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1490 val = ((params->mac_addr[2] << 24) |
1491 (params->mac_addr[3] << 16) |
1492 (params->mac_addr[4] << 8) |
1493 params->mac_addr[5]);
1494 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1497 static void bnx2x_set_xumac_nig(struct link_params *params,
1501 struct bnx2x *bp = params->bp;
1503 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1505 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1507 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1508 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1511 static void bnx2x_umac_enable(struct link_params *params,
1512 struct link_vars *vars, u8 lb)
1515 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1516 struct bnx2x *bp = params->bp;
1518 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1519 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1520 usleep_range(1000, 1000);
1522 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1525 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1528 * This register determines on which events the MAC will assert
1529 * error on the i/f to the NIG along w/ EOP.
1533 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1534 * params->port*0x14, 0xfffff.
1536 /* This register opens the gate for the UMAC despite its name */
1537 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1539 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1540 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1541 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1542 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1543 switch (vars->line_speed) {
1557 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1561 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1564 /* Enable RX and TX */
1565 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1566 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1567 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1568 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1571 /* Remove SW Reset */
1572 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1574 /* Check loopback mode */
1576 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1577 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1580 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1581 * length used by the MAC receive logic to check frames.
1583 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1584 bnx2x_set_xumac_nig(params,
1585 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1586 vars->mac_type = MAC_TYPE_UMAC;
1590 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1592 u32 port4mode_ovwr_val;
1593 /* Check 4-port override enabled */
1594 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1595 if (port4mode_ovwr_val & (1<<0)) {
1596 /* Return 4-port mode override value */
1597 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1599 /* Return 4-port mode from input pin */
1600 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1603 /* Define the XMAC mode */
1604 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1606 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1609 * In 4-port mode, need to set the mode only once, so if XMAC is
1610 * already out of reset, it means the mode has already been set,
1611 * and it must not* reset the XMAC again, since it controls both
1615 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1616 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1617 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1618 " in 4-port mode\n");
1623 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1624 MISC_REGISTERS_RESET_REG_2_XMAC);
1625 usleep_range(1000, 1000);
1627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1628 MISC_REGISTERS_RESET_REG_2_XMAC);
1630 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1632 /* Set the number of ports on the system side to up to 2 */
1633 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1635 /* Set the number of ports on the Warp Core to 10G */
1636 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1638 /* Set the number of ports on the system side to 1 */
1639 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1640 if (max_speed == SPEED_10000) {
1641 DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1642 " port per path\n");
1643 /* Set the number of ports on the Warp Core to 10G */
1644 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1646 DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1648 /* Set the number of ports on the Warp Core to 20G */
1649 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1653 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1654 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1655 usleep_range(1000, 1000);
1657 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1658 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1662 static void bnx2x_xmac_disable(struct link_params *params)
1664 u8 port = params->port;
1665 struct bnx2x *bp = params->bp;
1666 u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1668 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1669 MISC_REGISTERS_RESET_REG_2_XMAC) {
1670 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1671 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1672 usleep_range(1000, 1000);
1673 bnx2x_set_xumac_nig(params, 0, 0);
1674 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1675 XMAC_CTRL_REG_SOFT_RESET);
1679 static int bnx2x_xmac_enable(struct link_params *params,
1680 struct link_vars *vars, u8 lb)
1683 struct bnx2x *bp = params->bp;
1684 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1686 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1688 bnx2x_xmac_init(bp, vars->line_speed);
1691 * This register determines on which events the MAC will assert
1692 * error on the i/f to the NIG along w/ EOP.
1696 * This register tells the NIG whether to send traffic to UMAC
1699 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1701 /* Set Max packet size */
1702 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1704 /* CRC append for Tx packets */
1705 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1708 bnx2x_update_pfc_xmac(params, vars, 0);
1710 /* Enable TX and RX */
1711 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1713 /* Check loopback mode */
1715 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1716 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1717 bnx2x_set_xumac_nig(params,
1718 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1720 vars->mac_type = MAC_TYPE_XMAC;
1724 static int bnx2x_emac_enable(struct link_params *params,
1725 struct link_vars *vars, u8 lb)
1727 struct bnx2x *bp = params->bp;
1728 u8 port = params->port;
1729 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1732 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1734 /* enable emac and not bmac */
1735 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1738 if (vars->phy_flags & PHY_XGXS_FLAG) {
1739 u32 ser_lane = ((params->lane_config &
1740 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1741 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1743 DP(NETIF_MSG_LINK, "XGXS\n");
1744 /* select the master lanes (out of 0-3) */
1745 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1747 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1749 } else { /* SerDes */
1750 DP(NETIF_MSG_LINK, "SerDes\n");
1752 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1755 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1756 EMAC_RX_MODE_RESET);
1757 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1758 EMAC_TX_MODE_RESET);
1760 if (CHIP_REV_IS_SLOW(bp)) {
1761 /* config GMII mode */
1762 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1763 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1765 /* pause enable/disable */
1766 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1767 EMAC_RX_MODE_FLOW_EN);
1769 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1770 (EMAC_TX_MODE_EXT_PAUSE_EN |
1771 EMAC_TX_MODE_FLOW_EN));
1772 if (!(params->feature_config_flags &
1773 FEATURE_CONFIG_PFC_ENABLED)) {
1774 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1775 bnx2x_bits_en(bp, emac_base +
1776 EMAC_REG_EMAC_RX_MODE,
1777 EMAC_RX_MODE_FLOW_EN);
1779 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1780 bnx2x_bits_en(bp, emac_base +
1781 EMAC_REG_EMAC_TX_MODE,
1782 (EMAC_TX_MODE_EXT_PAUSE_EN |
1783 EMAC_TX_MODE_FLOW_EN));
1785 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1786 EMAC_TX_MODE_FLOW_EN);
1789 /* KEEP_VLAN_TAG, promiscuous */
1790 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1791 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1794 * Setting this bit causes MAC control frames (except for pause
1795 * frames) to be passed on for processing. This setting has no
1796 * affect on the operation of the pause frames. This bit effects
1797 * all packets regardless of RX Parser packet sorting logic.
1798 * Turn the PFC off to make sure we are in Xon state before
1801 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1802 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1803 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1804 /* Enable PFC again */
1805 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1806 EMAC_REG_RX_PFC_MODE_RX_EN |
1807 EMAC_REG_RX_PFC_MODE_TX_EN |
1808 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1810 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1812 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1814 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1815 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1817 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1820 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1825 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1828 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1830 /* enable emac for jumbo packets */
1831 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1832 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1833 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1836 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1838 /* disable the NIG in/out to the bmac */
1839 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1840 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1841 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1843 /* enable the NIG in/out to the emac */
1844 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1846 if ((params->feature_config_flags &
1847 FEATURE_CONFIG_PFC_ENABLED) ||
1848 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1851 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1852 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1854 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1856 vars->mac_type = MAC_TYPE_EMAC;
1860 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1861 struct link_vars *vars)
1864 struct bnx2x *bp = params->bp;
1865 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1866 NIG_REG_INGRESS_BMAC0_MEM;
1869 if ((!(params->feature_config_flags &
1870 FEATURE_CONFIG_PFC_ENABLED)) &&
1871 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1872 /* Enable BigMAC to react on received Pause packets */
1876 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1880 if (!(params->feature_config_flags &
1881 FEATURE_CONFIG_PFC_ENABLED) &&
1882 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1886 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1889 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1890 struct link_vars *vars,
1894 * Set rx control: Strip CRC and enable BigMAC to relay
1895 * control packets to the system as well
1898 struct bnx2x *bp = params->bp;
1899 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1900 NIG_REG_INGRESS_BMAC0_MEM;
1903 if ((!(params->feature_config_flags &
1904 FEATURE_CONFIG_PFC_ENABLED)) &&
1905 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1906 /* Enable BigMAC to react on received Pause packets */
1910 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1915 if (!(params->feature_config_flags &
1916 FEATURE_CONFIG_PFC_ENABLED) &&
1917 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1921 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1923 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1924 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1925 /* Enable PFC RX & TX & STATS and set 8 COS */
1927 wb_data[0] |= (1<<0); /* RX */
1928 wb_data[0] |= (1<<1); /* TX */
1929 wb_data[0] |= (1<<2); /* Force initial Xon */
1930 wb_data[0] |= (1<<3); /* 8 cos */
1931 wb_data[0] |= (1<<5); /* STATS */
1933 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1935 /* Clear the force Xon */
1936 wb_data[0] &= ~(1<<2);
1938 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1939 /* disable PFC RX & TX & STATS and set 8 COS */
1944 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1947 * Set Time (based unit is 512 bit time) between automatic
1948 * re-sending of PP packets amd enable automatic re-send of
1949 * Per-Priroity Packet as long as pp_gen is asserted and
1950 * pp_disable is low.
1953 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1954 val |= (1<<16); /* enable automatic re-send */
1958 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1962 val = 0x3; /* Enable RX and TX */
1964 val |= 0x4; /* Local loopback */
1965 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1967 /* When PFC enabled, Pass pause frames towards the NIG. */
1968 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1969 val |= ((1<<6)|(1<<5));
1973 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1977 /* PFC BRB internal port configuration params */
1978 struct bnx2x_pfc_brb_threshold_val {
1985 struct bnx2x_pfc_brb_e3b0_val {
1986 u32 full_lb_xoff_th;
1987 u32 full_lb_xon_threshold;
1989 u32 mac_0_class_t_guarantied;
1990 u32 mac_0_class_t_guarantied_hyst;
1991 u32 mac_1_class_t_guarantied;
1992 u32 mac_1_class_t_guarantied_hyst;
1995 struct bnx2x_pfc_brb_th_val {
1996 struct bnx2x_pfc_brb_threshold_val pauseable_th;
1997 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1999 static int bnx2x_pfc_brb_get_config_params(
2000 struct link_params *params,
2001 struct bnx2x_pfc_brb_th_val *config_val)
2003 struct bnx2x *bp = params->bp;
2004 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2005 if (CHIP_IS_E2(bp)) {
2006 config_val->pauseable_th.pause_xoff =
2007 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2008 config_val->pauseable_th.pause_xon =
2009 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2010 config_val->pauseable_th.full_xoff =
2011 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2012 config_val->pauseable_th.full_xon =
2013 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2015 config_val->non_pauseable_th.pause_xoff =
2016 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2017 config_val->non_pauseable_th.pause_xon =
2018 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2019 config_val->non_pauseable_th.full_xoff =
2020 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2021 config_val->non_pauseable_th.full_xon =
2022 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2023 } else if (CHIP_IS_E3A0(bp)) {
2024 config_val->pauseable_th.pause_xoff =
2025 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2026 config_val->pauseable_th.pause_xon =
2027 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2028 config_val->pauseable_th.full_xoff =
2029 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2030 config_val->pauseable_th.full_xon =
2031 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2033 config_val->non_pauseable_th.pause_xoff =
2034 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2035 config_val->non_pauseable_th.pause_xon =
2036 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2037 config_val->non_pauseable_th.full_xoff =
2038 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2039 config_val->non_pauseable_th.full_xon =
2040 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2041 } else if (CHIP_IS_E3B0(bp)) {
2042 if (params->phy[INT_PHY].flags &
2043 FLAGS_4_PORT_MODE) {
2044 config_val->pauseable_th.pause_xoff =
2045 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2046 config_val->pauseable_th.pause_xon =
2047 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2048 config_val->pauseable_th.full_xoff =
2049 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2050 config_val->pauseable_th.full_xon =
2051 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2053 config_val->non_pauseable_th.pause_xoff =
2054 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2055 config_val->non_pauseable_th.pause_xon =
2056 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2057 config_val->non_pauseable_th.full_xoff =
2058 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2059 config_val->non_pauseable_th.full_xon =
2060 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2062 config_val->pauseable_th.pause_xoff =
2063 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2064 config_val->pauseable_th.pause_xon =
2065 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2066 config_val->pauseable_th.full_xoff =
2067 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2068 config_val->pauseable_th.full_xon =
2069 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2071 config_val->non_pauseable_th.pause_xoff =
2072 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2073 config_val->non_pauseable_th.pause_xon =
2074 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2075 config_val->non_pauseable_th.full_xoff =
2076 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2077 config_val->non_pauseable_th.full_xon =
2078 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2087 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2088 struct bnx2x_pfc_brb_e3b0_val
2093 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2094 e3b0_val->full_lb_xoff_th =
2095 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2096 e3b0_val->full_lb_xon_threshold =
2097 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2098 e3b0_val->lb_guarantied =
2099 PFC_E3B0_4P_LB_GUART;
2100 e3b0_val->mac_0_class_t_guarantied =
2101 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2102 e3b0_val->mac_0_class_t_guarantied_hyst =
2103 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2104 e3b0_val->mac_1_class_t_guarantied =
2105 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2106 e3b0_val->mac_1_class_t_guarantied_hyst =
2107 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2109 e3b0_val->full_lb_xoff_th =
2110 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2111 e3b0_val->full_lb_xon_threshold =
2112 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2113 e3b0_val->mac_0_class_t_guarantied_hyst =
2114 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2115 e3b0_val->mac_1_class_t_guarantied =
2116 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2117 e3b0_val->mac_1_class_t_guarantied_hyst =
2118 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2120 if (cos0_pauseable != cos1_pauseable) {
2121 /* nonpauseable= Lossy + pauseable = Lossless*/
2122 e3b0_val->lb_guarantied =
2123 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2124 e3b0_val->mac_0_class_t_guarantied =
2125 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2126 } else if (cos0_pauseable) {
2127 /* Lossless +Lossless*/
2128 e3b0_val->lb_guarantied =
2129 PFC_E3B0_2P_PAUSE_LB_GUART;
2130 e3b0_val->mac_0_class_t_guarantied =
2131 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2134 e3b0_val->lb_guarantied =
2135 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2136 e3b0_val->mac_0_class_t_guarantied =
2137 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2141 static int bnx2x_update_pfc_brb(struct link_params *params,
2142 struct link_vars *vars,
2143 struct bnx2x_nig_brb_pfc_port_params
2146 struct bnx2x *bp = params->bp;
2147 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2148 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2149 &config_val.pauseable_th;
2150 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2151 int set_pfc = params->feature_config_flags &
2152 FEATURE_CONFIG_PFC_ENABLED;
2153 int bnx2x_status = 0;
2154 u8 port = params->port;
2156 /* default - pause configuration */
2157 reg_th_config = &config_val.pauseable_th;
2158 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2159 if (0 != bnx2x_status)
2160 return bnx2x_status;
2162 if (set_pfc && pfc_params)
2164 if (!pfc_params->cos0_pauseable)
2165 reg_th_config = &config_val.non_pauseable_th;
2167 * The number of free blocks below which the pause signal to class 0
2168 * of MAC #n is asserted. n=0,1
2170 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2171 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2172 reg_th_config->pause_xoff);
2174 * The number of free blocks above which the pause signal to class 0
2175 * of MAC #n is de-asserted. n=0,1
2177 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2178 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2180 * The number of free blocks below which the full signal to class 0
2181 * of MAC #n is asserted. n=0,1
2183 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2184 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2186 * The number of free blocks above which the full signal to class 0
2187 * of MAC #n is de-asserted. n=0,1
2189 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2190 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2192 if (set_pfc && pfc_params) {
2194 if (pfc_params->cos1_pauseable)
2195 reg_th_config = &config_val.pauseable_th;
2197 reg_th_config = &config_val.non_pauseable_th;
2199 * The number of free blocks below which the pause signal to
2200 * class 1 of MAC #n is asserted. n=0,1
2202 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2203 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2204 reg_th_config->pause_xoff);
2206 * The number of free blocks above which the pause signal to
2207 * class 1 of MAC #n is de-asserted. n=0,1
2209 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2210 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2211 reg_th_config->pause_xon);
2213 * The number of free blocks below which the full signal to
2214 * class 1 of MAC #n is asserted. n=0,1
2216 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2217 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2218 reg_th_config->full_xoff);
2220 * The number of free blocks above which the full signal to
2221 * class 1 of MAC #n is de-asserted. n=0,1
2223 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2224 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2225 reg_th_config->full_xon);
2228 if (CHIP_IS_E3B0(bp)) {
2229 /*Should be done by init tool */
2231 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2237 * The hysteresis on the guarantied buffer space for the Lb port
2238 * before signaling XON.
2240 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2242 bnx2x_pfc_brb_get_e3b0_config_params(
2245 pfc_params->cos0_pauseable,
2246 pfc_params->cos1_pauseable);
2248 * The number of free blocks below which the full signal to the
2249 * LB port is asserted.
2251 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2252 e3b0_val.full_lb_xoff_th);
2254 * The number of free blocks above which the full signal to the
2255 * LB port is de-asserted.
2257 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2258 e3b0_val.full_lb_xon_threshold);
2260 * The number of blocks guarantied for the MAC #n port. n=0,1
2263 /*The number of blocks guarantied for the LB port.*/
2264 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2265 e3b0_val.lb_guarantied);
2268 * The number of blocks guarantied for the MAC #n port.
2270 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2271 2 * e3b0_val.mac_0_class_t_guarantied);
2272 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2273 2 * e3b0_val.mac_1_class_t_guarantied);
2275 * The number of blocks guarantied for class #t in MAC0. t=0,1
2277 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2278 e3b0_val.mac_0_class_t_guarantied);
2279 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2280 e3b0_val.mac_0_class_t_guarantied);
2282 * The hysteresis on the guarantied buffer space for class in
2285 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2286 e3b0_val.mac_0_class_t_guarantied_hyst);
2287 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2288 e3b0_val.mac_0_class_t_guarantied_hyst);
2291 * The number of blocks guarantied for class #t in MAC1.t=0,1
2293 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2294 e3b0_val.mac_1_class_t_guarantied);
2295 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2296 e3b0_val.mac_1_class_t_guarantied);
2298 * The hysteresis on the guarantied buffer space for class #t
2301 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2302 e3b0_val.mac_1_class_t_guarantied_hyst);
2303 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2304 e3b0_val.mac_1_class_t_guarantied_hyst);
2310 return bnx2x_status;
2313 /******************************************************************************
2315 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2316 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2317 ******************************************************************************/
2318 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2320 u32 priority_mask, u8 port)
2322 u32 nig_reg_rx_priority_mask_add = 0;
2324 switch (cos_entry) {
2326 nig_reg_rx_priority_mask_add = (port) ?
2327 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2328 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2331 nig_reg_rx_priority_mask_add = (port) ?
2332 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2333 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2336 nig_reg_rx_priority_mask_add = (port) ?
2337 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2338 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2343 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2348 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2353 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2357 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2361 static void bnx2x_update_pfc_nig(struct link_params *params,
2362 struct link_vars *vars,
2363 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2365 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2366 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2367 u32 pkt_priority_to_cos = 0;
2368 struct bnx2x *bp = params->bp;
2369 u8 port = params->port;
2371 int set_pfc = params->feature_config_flags &
2372 FEATURE_CONFIG_PFC_ENABLED;
2373 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2376 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2377 * MAC control frames (that are not pause packets)
2378 * will be forwarded to the XCM.
2380 xcm_mask = REG_RD(bp,
2381 port ? NIG_REG_LLH1_XCM_MASK :
2382 NIG_REG_LLH0_XCM_MASK);
2384 * nig params will override non PFC params, since it's possible to
2385 * do transition from PFC to SAFC
2395 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2396 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2398 p0_hwpfc_enable = 1;
2401 llfc_out_en = nig_params->llfc_out_en;
2402 llfc_enable = nig_params->llfc_enable;
2403 pause_enable = nig_params->pause_enable;
2404 } else /*defaul non PFC mode - PAUSE */
2407 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2408 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2413 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2414 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2415 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2416 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2417 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2418 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2419 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2420 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2422 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2423 NIG_REG_PPP_ENABLE_0, ppp_enable);
2425 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2426 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2428 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2430 /* output enable for RX_XCM # IF */
2431 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2433 /* HW PFC TX enable */
2434 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2438 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2440 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2441 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2442 nig_params->rx_cos_priority_mask[i], port);
2444 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2445 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2446 nig_params->llfc_high_priority_classes);
2448 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2449 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2450 nig_params->llfc_low_priority_classes);
2452 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2453 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2454 pkt_priority_to_cos);
2457 int bnx2x_update_pfc(struct link_params *params,
2458 struct link_vars *vars,
2459 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2462 * The PFC and pause are orthogonal to one another, meaning when
2463 * PFC is enabled, the pause are disabled, and when PFC is
2464 * disabled, pause are set according to the pause result.
2467 struct bnx2x *bp = params->bp;
2468 int bnx2x_status = 0;
2469 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2470 /* update NIG params */
2471 bnx2x_update_pfc_nig(params, vars, pfc_params);
2473 /* update BRB params */
2474 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2475 if (0 != bnx2x_status)
2476 return bnx2x_status;
2479 return bnx2x_status;
2481 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2483 bnx2x_update_pfc_xmac(params, vars, 0);
2485 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2487 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2489 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2490 bnx2x_emac_enable(params, vars, 0);
2491 return bnx2x_status;
2495 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2497 bnx2x_update_pfc_bmac1(params, vars);
2500 if ((params->feature_config_flags &
2501 FEATURE_CONFIG_PFC_ENABLED) ||
2502 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2504 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2506 return bnx2x_status;
2510 static int bnx2x_bmac1_enable(struct link_params *params,
2511 struct link_vars *vars,
2514 struct bnx2x *bp = params->bp;
2515 u8 port = params->port;
2516 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2517 NIG_REG_INGRESS_BMAC0_MEM;
2521 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2526 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2530 wb_data[0] = ((params->mac_addr[2] << 24) |
2531 (params->mac_addr[3] << 16) |
2532 (params->mac_addr[4] << 8) |
2533 params->mac_addr[5]);
2534 wb_data[1] = ((params->mac_addr[0] << 8) |
2535 params->mac_addr[1]);
2536 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2542 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2546 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2549 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2551 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2553 bnx2x_update_pfc_bmac1(params, vars);
2556 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2558 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2560 /* set cnt max size */
2561 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2563 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2565 /* configure safc */
2566 wb_data[0] = 0x1000200;
2568 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2571 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2572 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2580 static int bnx2x_bmac2_enable(struct link_params *params,
2581 struct link_vars *vars,
2584 struct bnx2x *bp = params->bp;
2585 u8 port = params->port;
2586 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2587 NIG_REG_INGRESS_BMAC0_MEM;
2590 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2594 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2597 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2600 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2606 wb_data[0] = ((params->mac_addr[2] << 24) |
2607 (params->mac_addr[3] << 16) |
2608 (params->mac_addr[4] << 8) |
2609 params->mac_addr[5]);
2610 wb_data[1] = ((params->mac_addr[0] << 8) |
2611 params->mac_addr[1]);
2612 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2617 /* Configure SAFC */
2618 wb_data[0] = 0x1000200;
2620 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2625 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2627 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2631 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2633 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2635 /* set cnt max size */
2636 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2638 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2640 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2642 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2643 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2645 if (wb_data[0] > 0) {
2646 DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2655 static int bnx2x_bmac_enable(struct link_params *params,
2656 struct link_vars *vars,
2660 u8 port = params->port;
2661 struct bnx2x *bp = params->bp;
2663 /* reset and unreset the BigMac */
2664 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2665 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2668 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2669 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2671 /* enable access for bmac registers */
2672 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2674 /* Enable BMAC according to BMAC type*/
2676 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2678 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2679 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2680 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2681 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2683 if ((params->feature_config_flags &
2684 FEATURE_CONFIG_PFC_ENABLED) ||
2685 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2687 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2688 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2689 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2690 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2691 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2692 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2694 vars->mac_type = MAC_TYPE_BMAC;
2699 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2701 struct bnx2x *bp = params->bp;
2703 REG_WR(bp, params->shmem_base +
2704 offsetof(struct shmem_region,
2705 port_mb[params->port].link_status), link_status);
2708 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2710 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2711 NIG_REG_INGRESS_BMAC0_MEM;
2713 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2715 /* Only if the bmac is out of reset */
2716 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2717 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2720 if (CHIP_IS_E2(bp)) {
2721 /* Clear Rx Enable bit in BMAC_CONTROL register */
2722 REG_RD_DMAE(bp, bmac_addr +
2723 BIGMAC2_REGISTER_BMAC_CONTROL,
2725 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2726 REG_WR_DMAE(bp, bmac_addr +
2727 BIGMAC2_REGISTER_BMAC_CONTROL,
2730 /* Clear Rx Enable bit in BMAC_CONTROL register */
2731 REG_RD_DMAE(bp, bmac_addr +
2732 BIGMAC_REGISTER_BMAC_CONTROL,
2734 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2735 REG_WR_DMAE(bp, bmac_addr +
2736 BIGMAC_REGISTER_BMAC_CONTROL,
2743 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2746 struct bnx2x *bp = params->bp;
2747 u8 port = params->port;
2752 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2754 /* wait for init credit */
2755 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2756 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2757 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2759 while ((init_crd != crd) && count) {
2762 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2765 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766 if (init_crd != crd) {
2767 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2772 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2773 line_speed == SPEED_10 ||
2774 line_speed == SPEED_100 ||
2775 line_speed == SPEED_1000 ||
2776 line_speed == SPEED_2500) {
2777 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2778 /* update threshold */
2779 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2780 /* update init credit */
2781 init_crd = 778; /* (800-18-4) */
2784 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2786 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2787 /* update threshold */
2788 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2789 /* update init credit */
2790 switch (line_speed) {
2792 init_crd = thresh + 553 - 22;
2795 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2800 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2801 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2802 line_speed, init_crd);
2804 /* probe the credit changes */
2805 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2807 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2810 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2815 * bnx2x_get_emac_base - retrive emac base address
2817 * @bp: driver handle
2818 * @mdc_mdio_access: access type
2821 * This function selects the MDC/MDIO access (through emac0 or
2822 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2823 * phy has a default access mode, which could also be overridden
2824 * by nvram configuration. This parameter, whether this is the
2825 * default phy configuration, or the nvram overrun
2826 * configuration, is passed here as mdc_mdio_access and selects
2827 * the emac_base for the CL45 read/writes operations
2829 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2830 u32 mdc_mdio_access, u8 port)
2833 switch (mdc_mdio_access) {
2834 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2836 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2837 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2838 emac_base = GRCBASE_EMAC1;
2840 emac_base = GRCBASE_EMAC0;
2842 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2843 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2844 emac_base = GRCBASE_EMAC0;
2846 emac_base = GRCBASE_EMAC1;
2848 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2849 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2851 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2852 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2861 /******************************************************************/
2862 /* CL22 access functions */
2863 /******************************************************************/
2864 static int bnx2x_cl22_write(struct bnx2x *bp,
2865 struct bnx2x_phy *phy,
2871 /* Switch to CL22 */
2872 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2873 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2874 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2877 tmp = ((phy->addr << 21) | (reg << 16) | val |
2878 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2879 EMAC_MDIO_COMM_START_BUSY);
2880 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2882 for (i = 0; i < 50; i++) {
2885 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2886 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2891 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2892 DP(NETIF_MSG_LINK, "write phy register failed\n");
2895 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2899 static int bnx2x_cl22_read(struct bnx2x *bp,
2900 struct bnx2x_phy *phy,
2901 u16 reg, u16 *ret_val)
2907 /* Switch to CL22 */
2908 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2909 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2910 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2913 val = ((phy->addr << 21) | (reg << 16) |
2914 EMAC_MDIO_COMM_COMMAND_READ_22 |
2915 EMAC_MDIO_COMM_START_BUSY);
2916 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2918 for (i = 0; i < 50; i++) {
2921 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2922 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2923 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2928 if (val & EMAC_MDIO_COMM_START_BUSY) {
2929 DP(NETIF_MSG_LINK, "read phy register failed\n");
2934 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2938 /******************************************************************/
2939 /* CL45 access functions */
2940 /******************************************************************/
2941 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2942 u8 devad, u16 reg, u16 *ret_val)
2949 val = ((phy->addr << 21) | (devad << 16) | reg |
2950 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2951 EMAC_MDIO_COMM_START_BUSY);
2952 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2954 for (i = 0; i < 50; i++) {
2957 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2958 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2963 if (val & EMAC_MDIO_COMM_START_BUSY) {
2964 DP(NETIF_MSG_LINK, "read phy register failed\n");
2965 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2970 val = ((phy->addr << 21) | (devad << 16) |
2971 EMAC_MDIO_COMM_COMMAND_READ_45 |
2972 EMAC_MDIO_COMM_START_BUSY);
2973 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2975 for (i = 0; i < 50; i++) {
2978 val = REG_RD(bp, phy->mdio_ctrl +
2979 EMAC_REG_EMAC_MDIO_COMM);
2980 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2981 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2985 if (val & EMAC_MDIO_COMM_START_BUSY) {
2986 DP(NETIF_MSG_LINK, "read phy register failed\n");
2987 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2992 /* Work around for E3 A0 */
2993 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2994 phy->flags ^= FLAGS_DUMMY_READ;
2995 if (phy->flags & FLAGS_DUMMY_READ) {
2997 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3004 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3005 u8 devad, u16 reg, u16 val)
3013 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3014 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3015 EMAC_MDIO_COMM_START_BUSY);
3016 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3018 for (i = 0; i < 50; i++) {
3021 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3022 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3027 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3028 DP(NETIF_MSG_LINK, "write phy register failed\n");
3029 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3034 tmp = ((phy->addr << 21) | (devad << 16) | val |
3035 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3036 EMAC_MDIO_COMM_START_BUSY);
3037 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3039 for (i = 0; i < 50; i++) {
3042 tmp = REG_RD(bp, phy->mdio_ctrl +
3043 EMAC_REG_EMAC_MDIO_COMM);
3044 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3049 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3050 DP(NETIF_MSG_LINK, "write phy register failed\n");
3051 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3055 /* Work around for E3 A0 */
3056 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3057 phy->flags ^= FLAGS_DUMMY_READ;
3058 if (phy->flags & FLAGS_DUMMY_READ) {
3060 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3068 /******************************************************************/
3069 /* BSC access functions from E3 */
3070 /******************************************************************/
3071 static void bnx2x_bsc_module_sel(struct link_params *params)
3074 u32 board_cfg, sfp_ctrl;
3075 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3076 struct bnx2x *bp = params->bp;
3077 u8 port = params->port;
3078 /* Read I2C output PINs */
3079 board_cfg = REG_RD(bp, params->shmem_base +
3080 offsetof(struct shmem_region,
3081 dev_info.shared_hw_config.board));
3082 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3083 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3084 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3086 /* Read I2C output value */
3087 sfp_ctrl = REG_RD(bp, params->shmem_base +
3088 offsetof(struct shmem_region,
3089 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3090 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3091 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3092 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3093 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3094 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3097 static int bnx2x_bsc_read(struct link_params *params,
3098 struct bnx2x_phy *phy,
3107 struct bnx2x *bp = params->bp;
3109 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3110 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3114 if (xfer_cnt > 16) {
3115 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3119 bnx2x_bsc_module_sel(params);
3121 xfer_cnt = 16 - lc_addr;
3123 /* enable the engine */
3124 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3125 val |= MCPR_IMC_COMMAND_ENABLE;
3126 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3128 /* program slave device ID */
3129 val = (sl_devid << 16) | sl_addr;
3130 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3132 /* start xfer with 0 byte to update the address pointer ???*/
3133 val = (MCPR_IMC_COMMAND_ENABLE) |
3134 (MCPR_IMC_COMMAND_WRITE_OP <<
3135 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3136 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3137 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3139 /* poll for completion */
3141 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3142 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3144 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3155 /* start xfer with read op */
3156 val = (MCPR_IMC_COMMAND_ENABLE) |
3157 (MCPR_IMC_COMMAND_READ_OP <<
3158 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3159 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3161 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3163 /* poll for completion */
3165 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3168 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3170 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3178 for (i = (lc_addr >> 2); i < 4; i++) {
3179 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3181 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3182 ((data_array[i] & 0x0000ff00) << 8) |
3183 ((data_array[i] & 0x00ff0000) >> 8) |
3184 ((data_array[i] & 0xff000000) >> 24);
3190 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3191 u8 devad, u16 reg, u16 or_val)
3194 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3195 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3198 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3199 u8 devad, u16 reg, u16 *ret_val)
3203 * Probe for the phy according to the given phy_addr, and execute
3204 * the read request on it
3206 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3207 if (params->phy[phy_index].addr == phy_addr) {
3208 return bnx2x_cl45_read(params->bp,
3209 ¶ms->phy[phy_index], devad,
3216 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3217 u8 devad, u16 reg, u16 val)
3221 * Probe for the phy according to the given phy_addr, and execute
3222 * the write request on it
3224 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3225 if (params->phy[phy_index].addr == phy_addr) {
3226 return bnx2x_cl45_write(params->bp,
3227 ¶ms->phy[phy_index], devad,
3233 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3234 struct link_params *params)
3237 struct bnx2x *bp = params->bp;
3238 u32 path_swap, path_swap_ovr;
3242 port = params->port;
3244 if (bnx2x_is_4_port_mode(bp)) {
3245 u32 port_swap, port_swap_ovr;
3247 /*figure out path swap value */
3248 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3249 if (path_swap_ovr & 0x1)
3250 path_swap = (path_swap_ovr & 0x2);
3252 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3257 /*figure out port swap value */
3258 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3259 if (port_swap_ovr & 0x1)
3260 port_swap = (port_swap_ovr & 0x2);
3262 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3267 lane = (port<<1) + path;
3268 } else { /* two port mode - no port swap */
3270 /*figure out path swap value */
3272 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3273 if (path_swap_ovr & 0x1) {
3274 path_swap = (path_swap_ovr & 0x2);
3277 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3287 static void bnx2x_set_aer_mmd(struct link_params *params,
3288 struct bnx2x_phy *phy)
3291 u16 offset, aer_val;
3292 struct bnx2x *bp = params->bp;
3293 ser_lane = ((params->lane_config &
3294 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3295 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3297 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3298 (phy->addr + ser_lane) : 0;
3300 if (USES_WARPCORE(bp)) {
3301 aer_val = bnx2x_get_warpcore_lane(phy, params);
3303 * In Dual-lane mode, two lanes are joined together,
3304 * so in order to configure them, the AER broadcast method is
3306 * 0x200 is the broadcast address for lanes 0,1
3307 * 0x201 is the broadcast address for lanes 2,3
3309 if (phy->flags & FLAGS_WC_DUAL_MODE)
3310 aer_val = (aer_val >> 1) | 0x200;
3311 } else if (CHIP_IS_E2(bp))
3312 aer_val = 0x3800 + offset - 1;
3314 aer_val = 0x3800 + offset;
3315 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3316 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3317 MDIO_AER_BLOCK_AER_REG, aer_val);
3321 /******************************************************************/
3322 /* Internal phy section */
3323 /******************************************************************/
3325 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3327 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3330 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3331 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3333 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3336 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3339 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3343 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3345 val = SERDES_RESET_BITS << (port*16);
3347 /* reset and unreset the SerDes/XGXS */
3348 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3350 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3352 bnx2x_set_serdes_access(bp, port);
3354 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3355 DEFAULT_PHY_DEV_ADDR);
3358 static void bnx2x_xgxs_deassert(struct link_params *params)
3360 struct bnx2x *bp = params->bp;
3363 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3364 port = params->port;
3366 val = XGXS_RESET_BITS << (port*16);
3368 /* reset and unreset the SerDes/XGXS */
3369 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3373 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3374 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3375 params->phy[INT_PHY].def_md_devad);
3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3379 struct link_params *params, u16 *ieee_fc)
3381 struct bnx2x *bp = params->bp;
3382 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3384 * resolve pause mode and advertisement Please refer to Table
3385 * 28B-3 of the 802.3ab-1999 spec
3388 switch (phy->req_flow_ctrl) {
3389 case BNX2X_FLOW_CTRL_AUTO:
3390 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3391 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3394 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3397 case BNX2X_FLOW_CTRL_TX:
3398 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3401 case BNX2X_FLOW_CTRL_RX:
3402 case BNX2X_FLOW_CTRL_BOTH:
3403 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3406 case BNX2X_FLOW_CTRL_NONE:
3408 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3411 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3414 static void set_phy_vars(struct link_params *params,
3415 struct link_vars *vars)
3417 struct bnx2x *bp = params->bp;
3418 u8 actual_phy_idx, phy_index, link_cfg_idx;
3419 u8 phy_config_swapped = params->multi_phy_config &
3420 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3421 for (phy_index = INT_PHY; phy_index < params->num_phys;
3423 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3424 actual_phy_idx = phy_index;
3425 if (phy_config_swapped) {
3426 if (phy_index == EXT_PHY1)
3427 actual_phy_idx = EXT_PHY2;
3428 else if (phy_index == EXT_PHY2)
3429 actual_phy_idx = EXT_PHY1;
3431 params->phy[actual_phy_idx].req_flow_ctrl =
3432 params->req_flow_ctrl[link_cfg_idx];
3434 params->phy[actual_phy_idx].req_line_speed =
3435 params->req_line_speed[link_cfg_idx];
3437 params->phy[actual_phy_idx].speed_cap_mask =
3438 params->speed_cap_mask[link_cfg_idx];
3440 params->phy[actual_phy_idx].req_duplex =
3441 params->req_duplex[link_cfg_idx];
3443 if (params->req_line_speed[link_cfg_idx] ==
3445 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3447 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3448 " speed_cap_mask %x\n",
3449 params->phy[actual_phy_idx].req_flow_ctrl,
3450 params->phy[actual_phy_idx].req_line_speed,
3451 params->phy[actual_phy_idx].speed_cap_mask);
3455 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3456 struct bnx2x_phy *phy,
3457 struct link_vars *vars)
3460 struct bnx2x *bp = params->bp;
3461 /* read modify write pause advertizing */
3462 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3464 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3466 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3467 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3468 if ((vars->ieee_fc &
3469 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3470 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3471 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3473 if ((vars->ieee_fc &
3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3476 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3478 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3479 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3482 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3484 switch (pause_result) { /* ASYM P ASYM P */
3485 case 0xb: /* 1 0 1 1 */
3486 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3489 case 0xe: /* 1 1 1 0 */
3490 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3493 case 0x5: /* 0 1 0 1 */
3494 case 0x7: /* 0 1 1 1 */
3495 case 0xd: /* 1 1 0 1 */
3496 case 0xf: /* 1 1 1 1 */
3497 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3503 if (pause_result & (1<<0))
3504 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3505 if (pause_result & (1<<1))
3506 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3509 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3510 struct link_params *params,
3511 struct link_vars *vars)
3513 struct bnx2x *bp = params->bp;
3514 u16 ld_pause; /* local */
3515 u16 lp_pause; /* link partner */
3520 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3522 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3523 vars->flow_ctrl = phy->req_flow_ctrl;
3524 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3525 vars->flow_ctrl = params->req_fc_auto_adv;
3526 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3528 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616) {
3529 bnx2x_cl22_read(bp, phy,
3531 bnx2x_cl22_read(bp, phy,
3534 bnx2x_cl45_read(bp, phy,
3536 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3537 bnx2x_cl45_read(bp, phy,
3539 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3541 pause_result = (ld_pause &
3542 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3543 pause_result |= (lp_pause &
3544 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3545 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3547 bnx2x_pause_resolve(vars, pause_result);
3551 /******************************************************************/
3552 /* Warpcore section */
3553 /******************************************************************/
3554 /* The init_internal_warpcore should mirror the xgxs,
3555 * i.e. reset the lane (if needed), set aer for the
3556 * init configuration, and set/clear SGMII flag. Internal
3557 * phy init is done purely in phy_init stage.
3559 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3560 struct link_params *params,
3561 struct link_vars *vars) {
3562 u16 val16 = 0, lane;
3563 struct bnx2x *bp = params->bp;
3564 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3565 /* Check adding advertisement for 1G KX */
3566 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3567 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3568 (vars->line_speed == SPEED_1000)) {
3572 /* Enable CL37 1G Parallel Detect */
3573 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3574 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3575 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3576 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3577 (sd_digital | 0x1));
3579 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3581 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3582 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3583 (vars->line_speed == SPEED_10000)) {
3584 /* Check adding advertisement for 10G KR */
3586 /* Enable 10G Parallel Detect */
3587 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3588 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3590 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3593 /* Set Transmit PMD settings */
3594 lane = bnx2x_get_warpcore_lane(phy, params);
3595 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3596 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3597 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3598 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3599 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3600 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3601 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3603 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3604 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3606 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3607 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3610 /* Advertised speeds */
3611 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3612 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3614 /* Advertise pause */
3615 bnx2x_ext_phy_set_pause(params, phy, vars);
3617 /* Enable Autoneg */
3618 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3619 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3621 /* Over 1G - AN local device user page 1 */
3622 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3623 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3625 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3626 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3628 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3629 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3632 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3633 struct link_params *params,
3634 struct link_vars *vars)
3636 struct bnx2x *bp = params->bp;
3639 /* Disable Autoneg */
3640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3643 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3644 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3646 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3647 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3649 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3652 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3653 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3655 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3656 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3658 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3659 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3661 /* Disable CL36 PCS Tx */
3662 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3663 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3665 /* Double Wide Single Data Rate @ pll rate */
3666 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3667 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3669 /* Leave cl72 training enable, needed for KR */
3670 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3671 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3674 /* Leave CL72 enabled */
3675 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3676 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3678 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3679 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3682 /* Set speed via PMA/PMD register */
3683 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3684 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3686 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3687 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3689 /*Enable encoded forced speed */
3690 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3691 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3693 /* Turn TX scramble payload only the 64/66 scrambler */
3694 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3695 MDIO_WC_REG_TX66_CONTROL, 0x9);
3697 /* Turn RX scramble payload only the 64/66 scrambler */
3698 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3699 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3701 /* set and clear loopback to cause a reset to 64/66 decoder */
3702 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3703 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3704 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3705 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3709 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3710 struct link_params *params,
3713 struct bnx2x *bp = params->bp;
3714 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3715 /* Hold rxSeqStart */
3716 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3717 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3718 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3719 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3721 /* Hold tx_fifo_reset */
3722 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3723 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3724 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3725 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3727 /* Disable CL73 AN */
3728 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3730 /* Disable 100FX Enable and Auto-Detect */
3731 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3732 MDIO_WC_REG_FX100_CTRL1, &val);
3733 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3736 /* Disable 100FX Idle detect */
3737 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3738 MDIO_WC_REG_FX100_CTRL3, &val);
3739 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3740 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3742 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3743 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3744 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3745 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3746 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3748 /* Turn off auto-detect & fiber mode */
3749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3750 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3751 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3752 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3755 /* Set filter_force_link, disable_false_link and parallel_detect */
3756 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3757 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3758 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3759 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3760 ((val | 0x0006) & 0xFFFE));
3763 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3764 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3766 misc1_val &= ~(0x1f);
3770 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3771 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3772 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3774 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3775 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3776 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3780 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3781 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3782 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3784 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3785 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3786 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3788 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3789 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3791 /* Set Transmit PMD settings */
3792 lane = bnx2x_get_warpcore_lane(phy, params);
3793 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3794 MDIO_WC_REG_TX_FIR_TAP,
3795 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3796 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3797 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3800 /* Enable fiber mode, enable and invert sig_det */
3801 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3802 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3803 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3806 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3807 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3808 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3809 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3810 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3812 /* 10G XFI Full Duplex */
3813 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3816 /* Release tx_fifo_reset */
3817 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3818 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3819 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3822 /* Release rxSeqStart */
3823 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3824 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3825 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3826 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3829 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3830 struct bnx2x_phy *phy)
3832 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3835 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3836 struct bnx2x_phy *phy,
3839 /* Rx0 anaRxControl1G */
3840 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3843 /* Rx2 anaRxControl1G */
3844 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3847 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3848 MDIO_WC_REG_RX66_SCW0, 0xE070);
3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3853 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3854 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857 MDIO_WC_REG_RX66_SCW3, 0x8090);
3859 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3860 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3862 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3865 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3866 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3868 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3869 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3871 /* Serdes Digital Misc1 */
3872 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3875 /* Serdes Digital4 Misc3 */
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3879 /* Set Transmit PMD settings */
3880 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3881 MDIO_WC_REG_TX_FIR_TAP,
3882 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3883 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3884 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3885 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3886 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3887 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3888 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3889 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3890 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3893 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3894 struct link_params *params,
3897 struct bnx2x *bp = params->bp;
3898 u16 val16, digctrl_kx1, digctrl_kx2;
3901 lane = bnx2x_get_warpcore_lane(phy, params);
3903 /* Clear XFI clock comp in non-10G single lane mode. */
3904 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3905 MDIO_WC_REG_RX66_CONTROL, &val16);
3906 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3907 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3909 if (phy->req_line_speed == SPEED_AUTO_NEG) {
3911 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3913 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3916 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3918 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3919 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3921 switch (phy->req_line_speed) {
3931 DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3932 "\n", phy->req_line_speed);
3936 if (phy->req_duplex == DUPLEX_FULL)
3939 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3940 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3942 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3943 phy->req_line_speed);
3944 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3945 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3946 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
3949 /* SGMII Slave mode and disable signal detect */
3950 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3951 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3955 digctrl_kx1 &= 0xff4a;
3957 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3958 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3961 /* Turn off parallel detect */
3962 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3963 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3964 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3965 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3966 (digctrl_kx2 & ~(1<<2)));
3968 /* Re-enable parallel detect */
3969 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3970 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3971 (digctrl_kx2 | (1<<2)));
3973 /* Enable autodet */
3974 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3975 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3976 (digctrl_kx1 | 0x10));
3979 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
3980 struct bnx2x_phy *phy,
3984 /* Take lane out of reset after configuration is finished */
3985 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3986 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3991 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3992 MDIO_WC_REG_DIGITAL5_MISC6, val);
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3998 /* Clear SFI/XFI link settings registers */
3999 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4000 struct link_params *params,
4003 struct bnx2x *bp = params->bp;
4006 /* Set XFI clock comp as default. */
4007 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4008 MDIO_WC_REG_RX66_CONTROL, &val16);
4009 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4010 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4012 bnx2x_warpcore_reset_lane(bp, phy, 1);
4013 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4014 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4016 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4018 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4019 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4020 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4021 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4024 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4025 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4026 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4027 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4028 lane = bnx2x_get_warpcore_lane(phy, params);
4029 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4030 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4031 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4033 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4034 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4035 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4037 bnx2x_warpcore_reset_lane(bp, phy, 0);
4040 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4042 u32 shmem_base, u8 port,
4043 u8 *gpio_num, u8 *gpio_port)
4048 if (CHIP_IS_E3(bp)) {
4049 cfg_pin = (REG_RD(bp, shmem_base +
4050 offsetof(struct shmem_region,
4051 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4052 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4053 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4056 * Should not happen. This function called upon interrupt
4057 * triggered by GPIO ( since EPIO can only generate interrupts
4059 * So if this function was called and none of the GPIOs was set,
4060 * it means the shit hit the fan.
4062 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4063 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4064 DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4065 "module detect indication\n",
4070 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4071 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4073 *gpio_num = MISC_REGISTERS_GPIO_3;
4076 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4080 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4081 struct link_params *params)
4083 struct bnx2x *bp = params->bp;
4084 u8 gpio_num, gpio_port;
4086 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4087 params->shmem_base, params->port,
4088 &gpio_num, &gpio_port) != 0)
4090 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4092 /* Call the handling function in case module is detected */
4099 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4100 struct link_params *params,
4101 struct link_vars *vars)
4103 struct bnx2x *bp = params->bp;
4106 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4107 serdes_net_if = (REG_RD(bp, params->shmem_base +
4108 offsetof(struct shmem_region, dev_info.
4109 port_hw_config[params->port].default_cfg)) &
4110 PORT_HW_CFG_NET_SERDES_IF_MASK);
4111 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4112 "serdes_net_if = 0x%x\n",
4113 vars->line_speed, serdes_net_if);
4114 bnx2x_set_aer_mmd(params, phy);
4116 vars->phy_flags |= PHY_XGXS_FLAG;
4117 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4118 (phy->req_line_speed &&
4119 ((phy->req_line_speed == SPEED_100) ||
4120 (phy->req_line_speed == SPEED_10)))) {
4121 vars->phy_flags |= PHY_SGMII_FLAG;
4122 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4123 bnx2x_warpcore_clear_regs(phy, params, lane);
4124 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4126 switch (serdes_net_if) {
4127 case PORT_HW_CFG_NET_SERDES_IF_KR:
4128 /* Enable KR Auto Neg */
4129 if (params->loopback_mode == LOOPBACK_NONE)
4130 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4132 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4133 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4137 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4138 bnx2x_warpcore_clear_regs(phy, params, lane);
4139 if (vars->line_speed == SPEED_10000) {
4140 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4141 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4143 if (SINGLE_MEDIA_DIRECT(params)) {
4144 DP(NETIF_MSG_LINK, "1G Fiber\n");
4147 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4150 bnx2x_warpcore_set_sgmii_speed(phy,
4157 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4159 bnx2x_warpcore_clear_regs(phy, params, lane);
4160 if (vars->line_speed == SPEED_10000) {
4161 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4162 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4163 } else if (vars->line_speed == SPEED_1000) {
4164 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4165 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4167 /* Issue Module detection */
4168 if (bnx2x_is_sfp_module_plugged(phy, params))
4169 bnx2x_sfp_module_detection(phy, params);
4172 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4173 if (vars->line_speed != SPEED_20000) {
4174 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4177 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4178 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4179 /* Issue Module detection */
4181 bnx2x_sfp_module_detection(phy, params);
4184 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4185 if (vars->line_speed != SPEED_20000) {
4186 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4189 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4190 bnx2x_warpcore_set_20G_KR2(bp, phy);
4194 DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4195 "0x%x\n", serdes_net_if);
4200 /* Take lane out of reset after configuration is finished */
4201 bnx2x_warpcore_reset_lane(bp, phy, 0);
4202 DP(NETIF_MSG_LINK, "Exit config init\n");
4205 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4206 struct bnx2x_phy *phy,
4209 struct bnx2x *bp = params->bp;
4211 u8 port = params->port;
4213 cfg_pin = REG_RD(bp, params->shmem_base +
4214 offsetof(struct shmem_region,
4215 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4216 PORT_HW_CFG_TX_LASER_MASK;
4217 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4218 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4219 /* For 20G, the expected pin to be used is 3 pins after the current */
4221 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4222 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4223 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4226 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4227 struct link_params *params)
4229 struct bnx2x *bp = params->bp;
4231 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4232 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4233 bnx2x_set_aer_mmd(params, phy);
4234 /* Global register */
4235 bnx2x_warpcore_reset_lane(bp, phy, 1);
4237 /* Clear loopback settings (if any) */
4239 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4240 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4241 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4242 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4245 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4247 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4248 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4250 /* Update those 1-copy registers */
4251 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4252 MDIO_AER_BLOCK_AER_REG, 0);
4253 /* Enable 1G MDIO (1-copy) */
4254 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4255 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4257 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4258 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4261 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4262 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4263 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4264 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4269 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4270 struct link_params *params)
4272 struct bnx2x *bp = params->bp;
4275 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4276 params->loopback_mode, phy->req_line_speed);
4278 if (phy->req_line_speed < SPEED_10000) {
4281 /* Update those 1-copy registers */
4282 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4283 MDIO_AER_BLOCK_AER_REG, 0);
4284 /* Enable 1G MDIO (1-copy) */
4285 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4286 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4288 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4289 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4291 /* Set 1G loopback based on lane (1-copy) */
4292 lane = bnx2x_get_warpcore_lane(phy, params);
4293 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4294 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4295 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4299 /* Switch back to 4-copy registers */
4300 bnx2x_set_aer_mmd(params, phy);
4301 /* Global loopback, not recommended. */
4302 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4303 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4304 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4305 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4309 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4310 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4311 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4312 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4315 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4316 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4317 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4318 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4323 void bnx2x_link_status_update(struct link_params *params,
4324 struct link_vars *vars)
4326 struct bnx2x *bp = params->bp;
4328 u8 port = params->port;
4329 u32 sync_offset, media_types;
4330 /* Update PHY configuration */
4331 set_phy_vars(params, vars);
4333 vars->link_status = REG_RD(bp, params->shmem_base +
4334 offsetof(struct shmem_region,
4335 port_mb[port].link_status));
4337 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4338 vars->phy_flags = PHY_XGXS_FLAG;
4339 if (vars->link_up) {
4340 DP(NETIF_MSG_LINK, "phy link up\n");
4342 vars->phy_link_up = 1;
4343 vars->duplex = DUPLEX_FULL;
4344 switch (vars->link_status &
4345 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4347 vars->duplex = DUPLEX_HALF;
4350 vars->line_speed = SPEED_10;
4354 vars->duplex = DUPLEX_HALF;
4358 vars->line_speed = SPEED_100;
4362 vars->duplex = DUPLEX_HALF;
4365 vars->line_speed = SPEED_1000;
4369 vars->duplex = DUPLEX_HALF;
4372 vars->line_speed = SPEED_2500;
4376 vars->line_speed = SPEED_10000;
4379 vars->line_speed = SPEED_20000;
4384 vars->flow_ctrl = 0;
4385 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4386 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4388 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4389 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4391 if (!vars->flow_ctrl)
4392 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4394 if (vars->line_speed &&
4395 ((vars->line_speed == SPEED_10) ||
4396 (vars->line_speed == SPEED_100))) {
4397 vars->phy_flags |= PHY_SGMII_FLAG;
4399 vars->phy_flags &= ~PHY_SGMII_FLAG;
4401 if (vars->line_speed &&
4402 USES_WARPCORE(bp) &&
4403 (vars->line_speed == SPEED_1000))
4404 vars->phy_flags |= PHY_SGMII_FLAG;
4405 /* anything 10 and over uses the bmac */
4406 link_10g_plus = (vars->line_speed >= SPEED_10000);
4408 if (link_10g_plus) {
4409 if (USES_WARPCORE(bp))
4410 vars->mac_type = MAC_TYPE_XMAC;
4412 vars->mac_type = MAC_TYPE_BMAC;
4414 if (USES_WARPCORE(bp))
4415 vars->mac_type = MAC_TYPE_UMAC;
4417 vars->mac_type = MAC_TYPE_EMAC;
4419 } else { /* link down */
4420 DP(NETIF_MSG_LINK, "phy link down\n");
4422 vars->phy_link_up = 0;
4424 vars->line_speed = 0;
4425 vars->duplex = DUPLEX_FULL;
4426 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4428 /* indicate no mac active */
4429 vars->mac_type = MAC_TYPE_NONE;
4432 /* Sync media type */
4433 sync_offset = params->shmem_base +
4434 offsetof(struct shmem_region,
4435 dev_info.port_hw_config[port].media_type);
4436 media_types = REG_RD(bp, sync_offset);
4438 params->phy[INT_PHY].media_type =
4439 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4440 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4441 params->phy[EXT_PHY1].media_type =
4442 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4443 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4444 params->phy[EXT_PHY2].media_type =
4445 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4446 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4447 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4449 /* Sync AEU offset */
4450 sync_offset = params->shmem_base +
4451 offsetof(struct shmem_region,
4452 dev_info.port_hw_config[port].aeu_int_mask);
4454 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4456 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4457 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4458 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4459 vars->line_speed, vars->duplex, vars->flow_ctrl);
4463 static void bnx2x_set_master_ln(struct link_params *params,
4464 struct bnx2x_phy *phy)
4466 struct bnx2x *bp = params->bp;
4467 u16 new_master_ln, ser_lane;
4468 ser_lane = ((params->lane_config &
4469 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4470 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4472 /* set the master_ln for AN */
4473 CL22_RD_OVER_CL45(bp, phy,
4474 MDIO_REG_BANK_XGXS_BLOCK2,
4475 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4478 CL22_WR_OVER_CL45(bp, phy,
4479 MDIO_REG_BANK_XGXS_BLOCK2 ,
4480 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4481 (new_master_ln | ser_lane));
4484 static int bnx2x_reset_unicore(struct link_params *params,
4485 struct bnx2x_phy *phy,
4488 struct bnx2x *bp = params->bp;
4491 CL22_RD_OVER_CL45(bp, phy,
4492 MDIO_REG_BANK_COMBO_IEEE0,
4493 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4495 /* reset the unicore */
4496 CL22_WR_OVER_CL45(bp, phy,
4497 MDIO_REG_BANK_COMBO_IEEE0,
4498 MDIO_COMBO_IEEE0_MII_CONTROL,
4500 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4502 bnx2x_set_serdes_access(bp, params->port);
4504 /* wait for the reset to self clear */
4505 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4508 /* the reset erased the previous bank value */
4509 CL22_RD_OVER_CL45(bp, phy,
4510 MDIO_REG_BANK_COMBO_IEEE0,
4511 MDIO_COMBO_IEEE0_MII_CONTROL,
4514 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4520 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4523 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4528 static void bnx2x_set_swap_lanes(struct link_params *params,
4529 struct bnx2x_phy *phy)
4531 struct bnx2x *bp = params->bp;
4533 * Each two bits represents a lane number:
4534 * No swap is 0123 => 0x1b no need to enable the swap
4536 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4538 ser_lane = ((params->lane_config &
4539 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4540 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4541 rx_lane_swap = ((params->lane_config &
4542 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4543 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4544 tx_lane_swap = ((params->lane_config &
4545 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4546 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4548 if (rx_lane_swap != 0x1b) {
4549 CL22_WR_OVER_CL45(bp, phy,
4550 MDIO_REG_BANK_XGXS_BLOCK2,
4551 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4553 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4554 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4556 CL22_WR_OVER_CL45(bp, phy,
4557 MDIO_REG_BANK_XGXS_BLOCK2,
4558 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4561 if (tx_lane_swap != 0x1b) {
4562 CL22_WR_OVER_CL45(bp, phy,
4563 MDIO_REG_BANK_XGXS_BLOCK2,
4564 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4566 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4568 CL22_WR_OVER_CL45(bp, phy,
4569 MDIO_REG_BANK_XGXS_BLOCK2,
4570 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4574 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4575 struct link_params *params)
4577 struct bnx2x *bp = params->bp;
4579 CL22_RD_OVER_CL45(bp, phy,
4580 MDIO_REG_BANK_SERDES_DIGITAL,
4581 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4583 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4584 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4586 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4587 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4588 phy->speed_cap_mask, control2);
4589 CL22_WR_OVER_CL45(bp, phy,
4590 MDIO_REG_BANK_SERDES_DIGITAL,
4591 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4594 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4595 (phy->speed_cap_mask &
4596 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4597 DP(NETIF_MSG_LINK, "XGXS\n");
4599 CL22_WR_OVER_CL45(bp, phy,
4600 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4601 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4602 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4604 CL22_RD_OVER_CL45(bp, phy,
4605 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4606 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4611 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4613 CL22_WR_OVER_CL45(bp, phy,
4614 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4615 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4618 /* Disable parallel detection of HiG */
4619 CL22_WR_OVER_CL45(bp, phy,
4620 MDIO_REG_BANK_XGXS_BLOCK2,
4621 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4622 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4623 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4627 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4628 struct link_params *params,
4629 struct link_vars *vars,
4632 struct bnx2x *bp = params->bp;
4636 CL22_RD_OVER_CL45(bp, phy,
4637 MDIO_REG_BANK_COMBO_IEEE0,
4638 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4640 /* CL37 Autoneg Enabled */
4641 if (vars->line_speed == SPEED_AUTO_NEG)
4642 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4643 else /* CL37 Autoneg Disabled */
4644 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4645 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4647 CL22_WR_OVER_CL45(bp, phy,
4648 MDIO_REG_BANK_COMBO_IEEE0,
4649 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4651 /* Enable/Disable Autodetection */
4653 CL22_RD_OVER_CL45(bp, phy,
4654 MDIO_REG_BANK_SERDES_DIGITAL,
4655 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4656 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4657 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4658 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4659 if (vars->line_speed == SPEED_AUTO_NEG)
4660 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4662 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4664 CL22_WR_OVER_CL45(bp, phy,
4665 MDIO_REG_BANK_SERDES_DIGITAL,
4666 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4668 /* Enable TetonII and BAM autoneg */
4669 CL22_RD_OVER_CL45(bp, phy,
4670 MDIO_REG_BANK_BAM_NEXT_PAGE,
4671 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4673 if (vars->line_speed == SPEED_AUTO_NEG) {
4674 /* Enable BAM aneg Mode and TetonII aneg Mode */
4675 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4676 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4678 /* TetonII and BAM Autoneg Disabled */
4679 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4680 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4682 CL22_WR_OVER_CL45(bp, phy,
4683 MDIO_REG_BANK_BAM_NEXT_PAGE,
4684 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4688 /* Enable Cl73 FSM status bits */
4689 CL22_WR_OVER_CL45(bp, phy,
4690 MDIO_REG_BANK_CL73_USERB0,
4691 MDIO_CL73_USERB0_CL73_UCTRL,
4694 /* Enable BAM Station Manager*/
4695 CL22_WR_OVER_CL45(bp, phy,
4696 MDIO_REG_BANK_CL73_USERB0,
4697 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4698 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4699 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4700 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4702 /* Advertise CL73 link speeds */
4703 CL22_RD_OVER_CL45(bp, phy,
4704 MDIO_REG_BANK_CL73_IEEEB1,
4705 MDIO_CL73_IEEEB1_AN_ADV2,
4707 if (phy->speed_cap_mask &
4708 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4709 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4710 if (phy->speed_cap_mask &
4711 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4712 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4714 CL22_WR_OVER_CL45(bp, phy,
4715 MDIO_REG_BANK_CL73_IEEEB1,
4716 MDIO_CL73_IEEEB1_AN_ADV2,
4719 /* CL73 Autoneg Enabled */
4720 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4722 } else /* CL73 Autoneg Disabled */
4725 CL22_WR_OVER_CL45(bp, phy,
4726 MDIO_REG_BANK_CL73_IEEEB0,
4727 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4730 /* program SerDes, forced speed */
4731 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4732 struct link_params *params,
4733 struct link_vars *vars)
4735 struct bnx2x *bp = params->bp;
4738 /* program duplex, disable autoneg and sgmii*/
4739 CL22_RD_OVER_CL45(bp, phy,
4740 MDIO_REG_BANK_COMBO_IEEE0,
4741 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4742 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4743 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4744 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4745 if (phy->req_duplex == DUPLEX_FULL)
4746 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4747 CL22_WR_OVER_CL45(bp, phy,
4748 MDIO_REG_BANK_COMBO_IEEE0,
4749 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4753 * - needed only if the speed is greater than 1G (2.5G or 10G)
4755 CL22_RD_OVER_CL45(bp, phy,
4756 MDIO_REG_BANK_SERDES_DIGITAL,
4757 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4758 /* clearing the speed value before setting the right speed */
4759 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4761 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4762 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4764 if (!((vars->line_speed == SPEED_1000) ||
4765 (vars->line_speed == SPEED_100) ||
4766 (vars->line_speed == SPEED_10))) {
4768 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4769 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4770 if (vars->line_speed == SPEED_10000)
4772 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4775 CL22_WR_OVER_CL45(bp, phy,
4776 MDIO_REG_BANK_SERDES_DIGITAL,
4777 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4781 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4782 struct link_params *params)
4784 struct bnx2x *bp = params->bp;
4787 /* configure the 48 bits for BAM AN */
4789 /* set extended capabilities */
4790 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4791 val |= MDIO_OVER_1G_UP1_2_5G;
4792 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4793 val |= MDIO_OVER_1G_UP1_10G;
4794 CL22_WR_OVER_CL45(bp, phy,
4795 MDIO_REG_BANK_OVER_1G,
4796 MDIO_OVER_1G_UP1, val);
4798 CL22_WR_OVER_CL45(bp, phy,
4799 MDIO_REG_BANK_OVER_1G,
4800 MDIO_OVER_1G_UP3, 0x400);
4803 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4804 struct link_params *params,
4807 struct bnx2x *bp = params->bp;
4809 /* for AN, we are always publishing full duplex */
4811 CL22_WR_OVER_CL45(bp, phy,
4812 MDIO_REG_BANK_COMBO_IEEE0,
4813 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4814 CL22_RD_OVER_CL45(bp, phy,
4815 MDIO_REG_BANK_CL73_IEEEB1,
4816 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4817 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4818 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4819 CL22_WR_OVER_CL45(bp, phy,
4820 MDIO_REG_BANK_CL73_IEEEB1,
4821 MDIO_CL73_IEEEB1_AN_ADV1, val);
4824 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4825 struct link_params *params,
4828 struct bnx2x *bp = params->bp;
4831 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4832 /* Enable and restart BAM/CL37 aneg */
4835 CL22_RD_OVER_CL45(bp, phy,
4836 MDIO_REG_BANK_CL73_IEEEB0,
4837 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4840 CL22_WR_OVER_CL45(bp, phy,
4841 MDIO_REG_BANK_CL73_IEEEB0,
4842 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4844 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4845 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4848 CL22_RD_OVER_CL45(bp, phy,
4849 MDIO_REG_BANK_COMBO_IEEE0,
4850 MDIO_COMBO_IEEE0_MII_CONTROL,
4853 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4855 CL22_WR_OVER_CL45(bp, phy,
4856 MDIO_REG_BANK_COMBO_IEEE0,
4857 MDIO_COMBO_IEEE0_MII_CONTROL,
4859 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4860 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4864 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4865 struct link_params *params,
4866 struct link_vars *vars)
4868 struct bnx2x *bp = params->bp;
4871 /* in SGMII mode, the unicore is always slave */
4873 CL22_RD_OVER_CL45(bp, phy,
4874 MDIO_REG_BANK_SERDES_DIGITAL,
4875 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4877 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4878 /* set sgmii mode (and not fiber) */
4879 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4880 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4881 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4882 CL22_WR_OVER_CL45(bp, phy,
4883 MDIO_REG_BANK_SERDES_DIGITAL,
4884 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4887 /* if forced speed */
4888 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4889 /* set speed, disable autoneg */
4892 CL22_RD_OVER_CL45(bp, phy,
4893 MDIO_REG_BANK_COMBO_IEEE0,
4894 MDIO_COMBO_IEEE0_MII_CONTROL,
4896 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4897 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4898 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4900 switch (vars->line_speed) {
4903 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4907 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4910 /* there is nothing to set for 10M */
4913 /* invalid speed for SGMII */
4914 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4919 /* setting the full duplex */
4920 if (phy->req_duplex == DUPLEX_FULL)
4922 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4923 CL22_WR_OVER_CL45(bp, phy,
4924 MDIO_REG_BANK_COMBO_IEEE0,
4925 MDIO_COMBO_IEEE0_MII_CONTROL,
4928 } else { /* AN mode */
4929 /* enable and restart AN */
4930 bnx2x_restart_autoneg(phy, params, 0);
4939 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4940 struct link_params *params)
4942 struct bnx2x *bp = params->bp;
4943 u16 pd_10g, status2_1000x;
4944 if (phy->req_line_speed != SPEED_AUTO_NEG)
4946 CL22_RD_OVER_CL45(bp, phy,
4947 MDIO_REG_BANK_SERDES_DIGITAL,
4948 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4950 CL22_RD_OVER_CL45(bp, phy,
4951 MDIO_REG_BANK_SERDES_DIGITAL,
4952 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4954 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4955 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4960 CL22_RD_OVER_CL45(bp, phy,
4961 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4962 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4965 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4966 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
4973 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
4974 struct link_params *params,
4975 struct link_vars *vars,
4978 struct bnx2x *bp = params->bp;
4979 u16 ld_pause; /* local driver */
4980 u16 lp_pause; /* link partner */
4983 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4985 /* resolve from gp_status in case of AN complete and not sgmii */
4986 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
4987 vars->flow_ctrl = phy->req_flow_ctrl;
4988 else if (phy->req_line_speed != SPEED_AUTO_NEG)
4989 vars->flow_ctrl = params->req_fc_auto_adv;
4990 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
4991 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
4992 if (bnx2x_direct_parallel_detect_used(phy, params)) {
4993 vars->flow_ctrl = params->req_fc_auto_adv;
4997 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
4998 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
4999 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5000 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5002 CL22_RD_OVER_CL45(bp, phy,
5003 MDIO_REG_BANK_CL73_IEEEB1,
5004 MDIO_CL73_IEEEB1_AN_ADV1,
5006 CL22_RD_OVER_CL45(bp, phy,
5007 MDIO_REG_BANK_CL73_IEEEB1,
5008 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5010 pause_result = (ld_pause &
5011 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5013 pause_result |= (lp_pause &
5014 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5016 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5019 CL22_RD_OVER_CL45(bp, phy,
5020 MDIO_REG_BANK_COMBO_IEEE0,
5021 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5023 CL22_RD_OVER_CL45(bp, phy,
5024 MDIO_REG_BANK_COMBO_IEEE0,
5025 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5027 pause_result = (ld_pause &
5028 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5029 pause_result |= (lp_pause &
5030 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5031 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5034 bnx2x_pause_resolve(vars, pause_result);
5036 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5039 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5040 struct link_params *params)
5042 struct bnx2x *bp = params->bp;
5043 u16 rx_status, ustat_val, cl37_fsm_received;
5044 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5045 /* Step 1: Make sure signal is detected */
5046 CL22_RD_OVER_CL45(bp, phy,
5050 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5051 (MDIO_RX0_RX_STATUS_SIGDET)) {
5052 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5053 "rx_status(0x80b0) = 0x%x\n", rx_status);
5054 CL22_WR_OVER_CL45(bp, phy,
5055 MDIO_REG_BANK_CL73_IEEEB0,
5056 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5057 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5060 /* Step 2: Check CL73 state machine */
5061 CL22_RD_OVER_CL45(bp, phy,
5062 MDIO_REG_BANK_CL73_USERB0,
5063 MDIO_CL73_USERB0_CL73_USTAT1,
5066 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5067 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5068 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5069 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5070 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5071 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5075 * Step 3: Check CL37 Message Pages received to indicate LP
5076 * supports only CL37
5078 CL22_RD_OVER_CL45(bp, phy,
5079 MDIO_REG_BANK_REMOTE_PHY,
5080 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5081 &cl37_fsm_received);
5082 if ((cl37_fsm_received &
5083 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5084 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5085 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5086 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5087 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5088 "misc_rx_status(0x8330) = 0x%x\n",
5093 * The combined cl37/cl73 fsm state information indicating that
5094 * we are connected to a device which does not support cl73, but
5095 * does support cl37 BAM. In this case we disable cl73 and
5096 * restart cl37 auto-neg
5100 CL22_WR_OVER_CL45(bp, phy,
5101 MDIO_REG_BANK_CL73_IEEEB0,
5102 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5104 /* Restart CL37 autoneg */
5105 bnx2x_restart_autoneg(phy, params, 0);
5106 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5109 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5110 struct link_params *params,
5111 struct link_vars *vars,
5114 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5115 vars->link_status |=
5116 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5118 if (bnx2x_direct_parallel_detect_used(phy, params))
5119 vars->link_status |=
5120 LINK_STATUS_PARALLEL_DETECTION_USED;
5122 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5123 struct link_params *params,
5124 struct link_vars *vars,
5129 struct bnx2x *bp = params->bp;
5130 if (phy->req_line_speed == SPEED_AUTO_NEG)
5131 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5133 DP(NETIF_MSG_LINK, "phy link up\n");
5135 vars->phy_link_up = 1;
5136 vars->link_status |= LINK_STATUS_LINK_UP;
5138 switch (speed_mask) {
5140 vars->line_speed = SPEED_10;
5141 if (vars->duplex == DUPLEX_FULL)
5142 vars->link_status |= LINK_10TFD;
5144 vars->link_status |= LINK_10THD;
5147 case GP_STATUS_100M:
5148 vars->line_speed = SPEED_100;
5149 if (vars->duplex == DUPLEX_FULL)
5150 vars->link_status |= LINK_100TXFD;
5152 vars->link_status |= LINK_100TXHD;
5156 case GP_STATUS_1G_KX:
5157 vars->line_speed = SPEED_1000;
5158 if (vars->duplex == DUPLEX_FULL)
5159 vars->link_status |= LINK_1000TFD;
5161 vars->link_status |= LINK_1000THD;
5164 case GP_STATUS_2_5G:
5165 vars->line_speed = SPEED_2500;
5166 if (vars->duplex == DUPLEX_FULL)
5167 vars->link_status |= LINK_2500TFD;
5169 vars->link_status |= LINK_2500THD;
5175 "link speed unsupported gp_status 0x%x\n",
5179 case GP_STATUS_10G_KX4:
5180 case GP_STATUS_10G_HIG:
5181 case GP_STATUS_10G_CX4:
5182 case GP_STATUS_10G_KR:
5183 case GP_STATUS_10G_SFI:
5184 case GP_STATUS_10G_XFI:
5185 vars->line_speed = SPEED_10000;
5186 vars->link_status |= LINK_10GTFD;
5188 case GP_STATUS_20G_DXGXS:
5189 vars->line_speed = SPEED_20000;
5190 vars->link_status |= LINK_20GTFD;
5194 "link speed unsupported gp_status 0x%x\n",
5198 } else { /* link_down */
5199 DP(NETIF_MSG_LINK, "phy link down\n");
5201 vars->phy_link_up = 0;
5203 vars->duplex = DUPLEX_FULL;
5204 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5205 vars->mac_type = MAC_TYPE_NONE;
5207 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5208 vars->phy_link_up, vars->line_speed);
5212 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5213 struct link_params *params,
5214 struct link_vars *vars)
5217 struct bnx2x *bp = params->bp;
5219 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5222 /* Read gp_status */
5223 CL22_RD_OVER_CL45(bp, phy,
5224 MDIO_REG_BANK_GP_STATUS,
5225 MDIO_GP_STATUS_TOP_AN_STATUS1,
5227 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5228 duplex = DUPLEX_FULL;
5229 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5231 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5232 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5233 gp_status, link_up, speed_mask);
5234 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5239 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5240 if (SINGLE_MEDIA_DIRECT(params)) {
5241 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5242 if (phy->req_line_speed == SPEED_AUTO_NEG)
5243 bnx2x_xgxs_an_resolve(phy, params, vars,
5246 } else { /* link_down */
5247 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5248 SINGLE_MEDIA_DIRECT(params)) {
5249 /* Check signal is detected */
5250 bnx2x_check_fallback_to_cl37(phy, params);
5254 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5255 vars->duplex, vars->flow_ctrl, vars->link_status);
5259 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5260 struct link_params *params,
5261 struct link_vars *vars)
5264 struct bnx2x *bp = params->bp;
5267 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5269 lane = bnx2x_get_warpcore_lane(phy, params);
5270 /* Read gp_status */
5271 if (phy->req_line_speed > SPEED_10000) {
5273 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5275 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5277 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5278 temp_link_up, link_up);
5281 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5283 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5284 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5285 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5286 /* Check for either KR or generic link up. */
5287 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5288 ((gp_status1 >> 12) & 0xf);
5289 link_up = gp_status1 & (1 << lane);
5290 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5292 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5293 /* Check Autoneg complete */
5294 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5295 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5297 if (gp_status4 & ((1<<12)<<lane))
5298 vars->link_status |=
5299 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5301 /* Check parallel detect used */
5302 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5303 MDIO_WC_REG_PAR_DET_10G_STATUS,
5306 vars->link_status |=
5307 LINK_STATUS_PARALLEL_DETECTION_USED;
5309 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5314 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5315 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5317 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5318 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5320 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5322 if ((lane & 1) == 0)
5327 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5330 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5331 vars->duplex, vars->flow_ctrl, vars->link_status);
5334 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5336 struct bnx2x *bp = params->bp;
5337 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5343 CL22_RD_OVER_CL45(bp, phy,
5344 MDIO_REG_BANK_OVER_1G,
5345 MDIO_OVER_1G_LP_UP2, &lp_up2);
5347 /* bits [10:7] at lp_up2, positioned at [15:12] */
5348 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5349 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5350 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5355 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5356 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5357 CL22_RD_OVER_CL45(bp, phy,
5359 MDIO_TX0_TX_DRIVER, &tx_driver);
5361 /* replace tx_driver bits [15:12] */
5363 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5364 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5365 tx_driver |= lp_up2;
5366 CL22_WR_OVER_CL45(bp, phy,
5368 MDIO_TX0_TX_DRIVER, tx_driver);
5373 static int bnx2x_emac_program(struct link_params *params,
5374 struct link_vars *vars)
5376 struct bnx2x *bp = params->bp;
5377 u8 port = params->port;
5380 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5381 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5383 (EMAC_MODE_25G_MODE |
5384 EMAC_MODE_PORT_MII_10M |
5385 EMAC_MODE_HALF_DUPLEX));
5386 switch (vars->line_speed) {
5388 mode |= EMAC_MODE_PORT_MII_10M;
5392 mode |= EMAC_MODE_PORT_MII;
5396 mode |= EMAC_MODE_PORT_GMII;
5400 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5404 /* 10G not valid for EMAC */
5405 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5410 if (vars->duplex == DUPLEX_HALF)
5411 mode |= EMAC_MODE_HALF_DUPLEX;
5413 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5416 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5420 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5421 struct link_params *params)
5425 struct bnx2x *bp = params->bp;
5427 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5428 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5429 CL22_WR_OVER_CL45(bp, phy,
5431 MDIO_RX0_RX_EQ_BOOST,
5432 phy->rx_preemphasis[i]);
5435 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5436 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5437 CL22_WR_OVER_CL45(bp, phy,
5440 phy->tx_preemphasis[i]);
5444 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5445 struct link_params *params,
5446 struct link_vars *vars)
5448 struct bnx2x *bp = params->bp;
5449 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5450 (params->loopback_mode == LOOPBACK_XGXS));
5451 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5452 if (SINGLE_MEDIA_DIRECT(params) &&
5453 (params->feature_config_flags &
5454 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5455 bnx2x_set_preemphasis(phy, params);
5457 /* forced speed requested? */
5458 if (vars->line_speed != SPEED_AUTO_NEG ||
5459 (SINGLE_MEDIA_DIRECT(params) &&
5460 params->loopback_mode == LOOPBACK_EXT)) {
5461 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5463 /* disable autoneg */
5464 bnx2x_set_autoneg(phy, params, vars, 0);
5466 /* program speed and duplex */
5467 bnx2x_program_serdes(phy, params, vars);
5469 } else { /* AN_mode */
5470 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5473 bnx2x_set_brcm_cl37_advertisement(phy, params);
5475 /* program duplex & pause advertisement (for aneg) */
5476 bnx2x_set_ieee_aneg_advertisement(phy, params,
5479 /* enable autoneg */
5480 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5482 /* enable and restart AN */
5483 bnx2x_restart_autoneg(phy, params, enable_cl73);
5486 } else { /* SGMII mode */
5487 DP(NETIF_MSG_LINK, "SGMII\n");
5489 bnx2x_initialize_sgmii_process(phy, params, vars);
5493 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5494 struct link_params *params,
5495 struct link_vars *vars)
5498 vars->phy_flags |= PHY_XGXS_FLAG;
5499 if ((phy->req_line_speed &&
5500 ((phy->req_line_speed == SPEED_100) ||
5501 (phy->req_line_speed == SPEED_10))) ||
5502 (!phy->req_line_speed &&
5503 (phy->speed_cap_mask >=
5504 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5505 (phy->speed_cap_mask <
5506 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5507 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5508 vars->phy_flags |= PHY_SGMII_FLAG;
5510 vars->phy_flags &= ~PHY_SGMII_FLAG;
5512 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5513 bnx2x_set_aer_mmd(params, phy);
5514 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5515 bnx2x_set_master_ln(params, phy);
5517 rc = bnx2x_reset_unicore(params, phy, 0);
5518 /* reset the SerDes and wait for reset bit return low */
5522 bnx2x_set_aer_mmd(params, phy);
5523 /* setting the masterLn_def again after the reset */
5524 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5525 bnx2x_set_master_ln(params, phy);
5526 bnx2x_set_swap_lanes(params, phy);
5532 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5533 struct bnx2x_phy *phy,
5534 struct link_params *params)
5537 /* Wait for soft reset to get cleared up to 1 sec */
5538 for (cnt = 0; cnt < 1000; cnt++) {
5539 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616)
5540 bnx2x_cl22_read(bp, phy,
5541 MDIO_PMA_REG_CTRL, &ctrl);
5543 bnx2x_cl45_read(bp, phy,
5545 MDIO_PMA_REG_CTRL, &ctrl);
5546 if (!(ctrl & (1<<15)))
5552 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5555 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5559 static void bnx2x_link_int_enable(struct link_params *params)
5561 u8 port = params->port;
5563 struct bnx2x *bp = params->bp;
5565 /* Setting the status to report on link up for either XGXS or SerDes */
5566 if (CHIP_IS_E3(bp)) {
5567 mask = NIG_MASK_XGXS0_LINK_STATUS;
5568 if (!(SINGLE_MEDIA_DIRECT(params)))
5569 mask |= NIG_MASK_MI_INT;
5570 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5571 mask = (NIG_MASK_XGXS0_LINK10G |
5572 NIG_MASK_XGXS0_LINK_STATUS);
5573 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5574 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5575 params->phy[INT_PHY].type !=
5576 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5577 mask |= NIG_MASK_MI_INT;
5578 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5581 } else { /* SerDes */
5582 mask = NIG_MASK_SERDES0_LINK_STATUS;
5583 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5584 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5585 params->phy[INT_PHY].type !=
5586 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5587 mask |= NIG_MASK_MI_INT;
5588 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5592 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5595 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5596 (params->switch_cfg == SWITCH_CFG_10G),
5597 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5598 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5599 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5600 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5601 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5602 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5603 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5604 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5607 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5610 u32 latch_status = 0;
5613 * Disable the MI INT ( external phy int ) by writing 1 to the
5614 * status register. Link down indication is high-active-signal,
5615 * so in this case we need to write the status to clear the XOR
5617 /* Read Latched signals */
5618 latch_status = REG_RD(bp,
5619 NIG_REG_LATCH_STATUS_0 + port*8);
5620 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5621 /* Handle only those with latched-signal=up.*/
5624 NIG_REG_STATUS_INTERRUPT_PORT0
5626 NIG_STATUS_EMAC0_MI_INT);
5629 NIG_REG_STATUS_INTERRUPT_PORT0
5631 NIG_STATUS_EMAC0_MI_INT);
5633 if (latch_status & 1) {
5635 /* For all latched-signal=up : Re-Arm Latch signals */
5636 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5637 (latch_status & 0xfffe) | (latch_status & 1));
5639 /* For all latched-signal=up,Write original_signal to status */
5642 static void bnx2x_link_int_ack(struct link_params *params,
5643 struct link_vars *vars, u8 is_10g_plus)
5645 struct bnx2x *bp = params->bp;
5646 u8 port = params->port;
5649 * First reset all status we assume only one line will be
5652 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5653 (NIG_STATUS_XGXS0_LINK10G |
5654 NIG_STATUS_XGXS0_LINK_STATUS |
5655 NIG_STATUS_SERDES0_LINK_STATUS));
5656 if (vars->phy_link_up) {
5657 if (USES_WARPCORE(bp))
5658 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5661 mask = NIG_STATUS_XGXS0_LINK10G;
5662 else if (params->switch_cfg == SWITCH_CFG_10G) {
5664 * Disable the link interrupt by writing 1 to
5665 * the relevant lane in the status register
5668 ((params->lane_config &
5669 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5670 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5671 mask = ((1 << ser_lane) <<
5672 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5674 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5676 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5679 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5684 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5687 u32 mask = 0xf0000000;
5690 u8 remove_leading_zeros = 1;
5692 /* Need more than 10chars for this format */
5700 digit = ((num & mask) >> shift);
5701 if (digit == 0 && remove_leading_zeros) {
5704 } else if (digit < 0xa)
5705 *str_ptr = digit + '0';
5707 *str_ptr = digit - 0xa + 'a';
5708 remove_leading_zeros = 0;
5716 remove_leading_zeros = 1;
5723 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5730 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5731 u8 *version, u16 len)
5736 u8 *ver_p = version;
5737 u16 remain_len = len;
5738 if (version == NULL || params == NULL)
5742 /* Extract first external phy*/
5744 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5746 if (params->phy[EXT_PHY1].format_fw_ver) {
5747 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5750 ver_p += (len - remain_len);
5752 if ((params->num_phys == MAX_PHYS) &&
5753 (params->phy[EXT_PHY2].ver_addr != 0)) {
5754 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5755 if (params->phy[EXT_PHY2].format_fw_ver) {
5759 status |= params->phy[EXT_PHY2].format_fw_ver(
5763 ver_p = version + (len - remain_len);
5770 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5771 struct link_params *params)
5773 u8 port = params->port;
5774 struct bnx2x *bp = params->bp;
5776 if (phy->req_line_speed != SPEED_1000) {
5779 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5781 if (!CHIP_IS_E3(bp)) {
5782 /* change the uni_phy_addr in the nig */
5783 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5786 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5790 bnx2x_cl45_write(bp, phy,
5792 (MDIO_REG_BANK_AER_BLOCK +
5793 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5796 bnx2x_cl45_write(bp, phy,
5798 (MDIO_REG_BANK_CL73_IEEEB0 +
5799 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5802 /* set aer mmd back */
5803 bnx2x_set_aer_mmd(params, phy);
5805 if (!CHIP_IS_E3(bp)) {
5807 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5812 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5813 bnx2x_cl45_read(bp, phy, 5,
5814 (MDIO_REG_BANK_COMBO_IEEE0 +
5815 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5817 bnx2x_cl45_write(bp, phy, 5,
5818 (MDIO_REG_BANK_COMBO_IEEE0 +
5819 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5821 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5825 int bnx2x_set_led(struct link_params *params,
5826 struct link_vars *vars, u8 mode, u32 speed)
5828 u8 port = params->port;
5829 u16 hw_led_mode = params->hw_led_mode;
5833 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5834 struct bnx2x *bp = params->bp;
5835 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5836 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5837 speed, hw_led_mode);
5839 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5840 if (params->phy[phy_idx].set_link_led) {
5841 params->phy[phy_idx].set_link_led(
5842 ¶ms->phy[phy_idx], params, mode);
5847 case LED_MODE_FRONT_PANEL_OFF:
5849 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5850 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5851 SHARED_HW_CFG_LED_MAC1);
5853 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5854 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5859 * For all other phys, OPER mode is same as ON, so in case
5860 * link is down, do nothing
5865 if (((params->phy[EXT_PHY1].type ==
5866 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5867 (params->phy[EXT_PHY1].type ==
5868 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5869 CHIP_IS_E2(bp) && params->num_phys == 2) {
5871 * This is a work-around for E2+8727 Configurations
5873 if (mode == LED_MODE_ON ||
5874 speed == SPEED_10000){
5875 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5876 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5878 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5879 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5880 (tmp | EMAC_LED_OVERRIDE));
5883 } else if (SINGLE_MEDIA_DIRECT(params) &&
5887 * This is a work-around for HW issue found when link
5890 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5891 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5893 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5896 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5897 /* Set blinking rate to ~15.9Hz */
5898 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5899 LED_BLINK_RATE_VAL);
5900 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5902 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5903 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5905 if (CHIP_IS_E1(bp) &&
5906 ((speed == SPEED_2500) ||
5907 (speed == SPEED_1000) ||
5908 (speed == SPEED_100) ||
5909 (speed == SPEED_10))) {
5911 * On Everest 1 Ax chip versions for speeds less than
5912 * 10G LED scheme is different
5914 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5916 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5918 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5925 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5934 * This function comes to reflect the actual link state read DIRECTLY from the
5937 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5940 struct bnx2x *bp = params->bp;
5941 u16 gp_status = 0, phy_index = 0;
5942 u8 ext_phy_link_up = 0, serdes_phy_type;
5943 struct link_vars temp_vars;
5944 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
5946 if (CHIP_IS_E3(bp)) {
5948 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5950 /* Check 20G link */
5951 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5953 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5957 /* Check 10G link and below*/
5958 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5959 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5960 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5962 gp_status = ((gp_status >> 8) & 0xf) |
5963 ((gp_status >> 12) & 0xf);
5964 link_up = gp_status & (1 << lane);
5969 CL22_RD_OVER_CL45(bp, int_phy,
5970 MDIO_REG_BANK_GP_STATUS,
5971 MDIO_GP_STATUS_TOP_AN_STATUS1,
5973 /* link is up only if both local phy and external phy are up */
5974 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
5977 /* In XGXS loopback mode, do not check external PHY */
5978 if (params->loopback_mode == LOOPBACK_XGXS)
5981 switch (params->num_phys) {
5983 /* No external PHY */
5986 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
5987 ¶ms->phy[EXT_PHY1],
5988 params, &temp_vars);
5990 case 3: /* Dual Media */
5991 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
5993 serdes_phy_type = ((params->phy[phy_index].media_type ==
5994 ETH_PHY_SFP_FIBER) ||
5995 (params->phy[phy_index].media_type ==
5996 ETH_PHY_XFP_FIBER) ||
5997 (params->phy[phy_index].media_type ==
5998 ETH_PHY_DA_TWINAX));
6000 if (is_serdes != serdes_phy_type)
6002 if (params->phy[phy_index].read_status) {
6004 params->phy[phy_index].read_status(
6005 ¶ms->phy[phy_index],
6006 params, &temp_vars);
6011 if (ext_phy_link_up)
6016 static int bnx2x_link_initialize(struct link_params *params,
6017 struct link_vars *vars)
6020 u8 phy_index, non_ext_phy;
6021 struct bnx2x *bp = params->bp;
6023 * In case of external phy existence, the line speed would be the
6024 * line speed linked up by the external phy. In case it is direct
6025 * only, then the line_speed during initialization will be
6026 * equal to the req_line_speed
6028 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6031 * Initialize the internal phy in case this is a direct board
6032 * (no external phys), or this board has external phy which requires
6035 if (!USES_WARPCORE(bp))
6036 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6037 /* init ext phy and enable link state int */
6038 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6039 (params->loopback_mode == LOOPBACK_XGXS));
6042 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6043 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6044 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6045 if (vars->line_speed == SPEED_AUTO_NEG &&
6048 bnx2x_set_parallel_detection(phy, params);
6049 if (params->phy[INT_PHY].config_init)
6050 params->phy[INT_PHY].config_init(phy,
6055 /* Init external phy*/
6057 if (params->phy[INT_PHY].supported &
6059 vars->link_status |= LINK_STATUS_SERDES_LINK;
6061 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6064 * No need to initialize second phy in case of first
6065 * phy only selection. In case of second phy, we do
6066 * need to initialize the first phy, since they are
6069 if (params->phy[phy_index].supported &
6071 vars->link_status |= LINK_STATUS_SERDES_LINK;
6073 if (phy_index == EXT_PHY2 &&
6074 (bnx2x_phy_selection(params) ==
6075 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6076 DP(NETIF_MSG_LINK, "Not initializing"
6080 params->phy[phy_index].config_init(
6081 ¶ms->phy[phy_index],
6085 /* Reset the interrupt indication after phy was initialized */
6086 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6088 (NIG_STATUS_XGXS0_LINK10G |
6089 NIG_STATUS_XGXS0_LINK_STATUS |
6090 NIG_STATUS_SERDES0_LINK_STATUS |
6092 bnx2x_update_mng(params, vars->link_status);
6096 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6097 struct link_params *params)
6099 /* reset the SerDes/XGXS */
6100 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6101 (0x1ff << (params->port*16)));
6104 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6105 struct link_params *params)
6107 struct bnx2x *bp = params->bp;
6111 gpio_port = BP_PATH(bp);
6113 gpio_port = params->port;
6114 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6115 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6117 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6118 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6120 DP(NETIF_MSG_LINK, "reset external PHY\n");
6123 static int bnx2x_update_link_down(struct link_params *params,
6124 struct link_vars *vars)
6126 struct bnx2x *bp = params->bp;
6127 u8 port = params->port;
6129 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6130 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6131 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6132 /* indicate no mac active */
6133 vars->mac_type = MAC_TYPE_NONE;
6135 /* update shared memory */
6136 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6137 LINK_STATUS_LINK_UP |
6138 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6139 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6140 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6141 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6142 vars->line_speed = 0;
6143 bnx2x_update_mng(params, vars->link_status);
6145 /* activate nig drain */
6146 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6149 if (!CHIP_IS_E3(bp))
6150 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6153 /* reset BigMac/Xmac */
6154 if (CHIP_IS_E1x(bp) ||
6156 bnx2x_bmac_rx_disable(bp, params->port);
6157 REG_WR(bp, GRCBASE_MISC +
6158 MISC_REGISTERS_RESET_REG_2_CLEAR,
6159 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6162 bnx2x_xmac_disable(params);
6167 static int bnx2x_update_link_up(struct link_params *params,
6168 struct link_vars *vars,
6171 struct bnx2x *bp = params->bp;
6172 u8 port = params->port;
6175 vars->link_status |= LINK_STATUS_LINK_UP;
6176 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6178 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6179 vars->link_status |=
6180 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6182 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6183 vars->link_status |=
6184 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6185 if (USES_WARPCORE(bp)) {
6187 if (bnx2x_xmac_enable(params, vars, 0) ==
6189 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6191 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6192 vars->link_status &= ~LINK_STATUS_LINK_UP;
6195 bnx2x_umac_enable(params, vars, 0);
6196 bnx2x_set_led(params, vars,
6197 LED_MODE_OPER, vars->line_speed);
6199 if ((CHIP_IS_E1x(bp) ||
6202 if (bnx2x_bmac_enable(params, vars, 0) ==
6204 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6206 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6207 vars->link_status &= ~LINK_STATUS_LINK_UP;
6210 bnx2x_set_led(params, vars,
6211 LED_MODE_OPER, SPEED_10000);
6213 rc = bnx2x_emac_program(params, vars);
6214 bnx2x_emac_enable(params, vars, 0);
6217 if ((vars->link_status &
6218 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6219 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6220 SINGLE_MEDIA_DIRECT(params))
6221 bnx2x_set_gmii_tx_driver(params);
6226 if (CHIP_IS_E1x(bp))
6227 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6231 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6233 /* update shared memory */
6234 bnx2x_update_mng(params, vars->link_status);
6239 * The bnx2x_link_update function should be called upon link
6241 * Link is considered up as follows:
6242 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6244 * - SINGLE_MEDIA - The link between the 577xx and the external
6245 * phy (XGXS) need to up as well as the external link of the
6247 * - DUAL_MEDIA - The link between the 577xx and the first
6248 * external phy needs to be up, and at least one of the 2
6249 * external phy link must be up.
6251 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6253 struct bnx2x *bp = params->bp;
6254 struct link_vars phy_vars[MAX_PHYS];
6255 u8 port = params->port;
6256 u8 link_10g_plus, phy_index;
6257 u8 ext_phy_link_up = 0, cur_link_up;
6260 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6261 u8 active_external_phy = INT_PHY;
6262 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6263 for (phy_index = INT_PHY; phy_index < params->num_phys;
6265 phy_vars[phy_index].flow_ctrl = 0;
6266 phy_vars[phy_index].link_status = 0;
6267 phy_vars[phy_index].line_speed = 0;
6268 phy_vars[phy_index].duplex = DUPLEX_FULL;
6269 phy_vars[phy_index].phy_link_up = 0;
6270 phy_vars[phy_index].link_up = 0;
6271 phy_vars[phy_index].fault_detected = 0;
6274 if (USES_WARPCORE(bp))
6275 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6277 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6278 port, (vars->phy_flags & PHY_XGXS_FLAG),
6279 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6281 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6283 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6284 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6286 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6288 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6289 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6290 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6293 if (!CHIP_IS_E3(bp))
6294 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6298 * Check external link change only for external phys, and apply
6299 * priority selection between them in case the link on both phys
6300 * is up. Note that instead of the common vars, a temporary
6301 * vars argument is used since each phy may have different link/
6302 * speed/duplex result
6304 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6306 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6307 if (!phy->read_status)
6309 /* Read link status and params of this ext phy */
6310 cur_link_up = phy->read_status(phy, params,
6311 &phy_vars[phy_index]);
6313 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6316 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6321 if (!ext_phy_link_up) {
6322 ext_phy_link_up = 1;
6323 active_external_phy = phy_index;
6325 switch (bnx2x_phy_selection(params)) {
6326 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6327 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6329 * In this option, the first PHY makes sure to pass the
6330 * traffic through itself only.
6331 * Its not clear how to reset the link on the second phy
6333 active_external_phy = EXT_PHY1;
6335 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6337 * In this option, the first PHY makes sure to pass the
6338 * traffic through the second PHY.
6340 active_external_phy = EXT_PHY2;
6344 * Link indication on both PHYs with the following cases
6346 * - FIRST_PHY means that second phy wasn't initialized,
6347 * hence its link is expected to be down
6348 * - SECOND_PHY means that first phy should not be able
6349 * to link up by itself (using configuration)
6350 * - DEFAULT should be overriden during initialiazation
6352 DP(NETIF_MSG_LINK, "Invalid link indication"
6353 "mpc=0x%x. DISABLING LINK !!!\n",
6354 params->multi_phy_config);
6355 ext_phy_link_up = 0;
6360 prev_line_speed = vars->line_speed;
6363 * Read the status of the internal phy. In case of
6364 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6365 * otherwise this is the link between the 577xx and the first
6368 if (params->phy[INT_PHY].read_status)
6369 params->phy[INT_PHY].read_status(
6370 ¶ms->phy[INT_PHY],
6373 * The INT_PHY flow control reside in the vars. This include the
6374 * case where the speed or flow control are not set to AUTO.
6375 * Otherwise, the active external phy flow control result is set
6376 * to the vars. The ext_phy_line_speed is needed to check if the
6377 * speed is different between the internal phy and external phy.
6378 * This case may be result of intermediate link speed change.
6380 if (active_external_phy > INT_PHY) {
6381 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6383 * Link speed is taken from the XGXS. AN and FC result from
6386 vars->link_status |= phy_vars[active_external_phy].link_status;
6389 * if active_external_phy is first PHY and link is up - disable
6390 * disable TX on second external PHY
6392 if (active_external_phy == EXT_PHY1) {
6393 if (params->phy[EXT_PHY2].phy_specific_func) {
6394 DP(NETIF_MSG_LINK, "Disabling TX on"
6396 params->phy[EXT_PHY2].phy_specific_func(
6397 ¶ms->phy[EXT_PHY2],
6398 params, DISABLE_TX);
6402 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6403 vars->duplex = phy_vars[active_external_phy].duplex;
6404 if (params->phy[active_external_phy].supported &
6406 vars->link_status |= LINK_STATUS_SERDES_LINK;
6408 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6409 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6410 active_external_phy);
6413 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6415 if (params->phy[phy_index].flags &
6416 FLAGS_REARM_LATCH_SIGNAL) {
6417 bnx2x_rearm_latch_signal(bp, port,
6419 active_external_phy);
6423 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6424 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6425 vars->link_status, ext_phy_line_speed);
6427 * Upon link speed change set the NIG into drain mode. Comes to
6428 * deals with possible FIFO glitch due to clk change when speed
6429 * is decreased without link down indicator
6432 if (vars->phy_link_up) {
6433 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6434 (ext_phy_line_speed != vars->line_speed)) {
6435 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6436 " different than the external"
6437 " link speed %d\n", vars->line_speed,
6438 ext_phy_line_speed);
6439 vars->phy_link_up = 0;
6440 } else if (prev_line_speed != vars->line_speed) {
6441 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6447 /* anything 10 and over uses the bmac */
6448 link_10g_plus = (vars->line_speed >= SPEED_10000);
6450 bnx2x_link_int_ack(params, vars, link_10g_plus);
6453 * In case external phy link is up, and internal link is down
6454 * (not initialized yet probably after link initialization, it
6455 * needs to be initialized.
6456 * Note that after link down-up as result of cable plug, the xgxs
6457 * link would probably become up again without the need
6460 if (!(SINGLE_MEDIA_DIRECT(params))) {
6461 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6462 " init_preceding = %d\n", ext_phy_link_up,
6464 params->phy[EXT_PHY1].flags &
6465 FLAGS_INIT_XGXS_FIRST);
6466 if (!(params->phy[EXT_PHY1].flags &
6467 FLAGS_INIT_XGXS_FIRST)
6468 && ext_phy_link_up && !vars->phy_link_up) {
6469 vars->line_speed = ext_phy_line_speed;
6470 if (vars->line_speed < SPEED_1000)
6471 vars->phy_flags |= PHY_SGMII_FLAG;
6473 vars->phy_flags &= ~PHY_SGMII_FLAG;
6475 if (params->phy[INT_PHY].config_init)
6476 params->phy[INT_PHY].config_init(
6477 ¶ms->phy[INT_PHY], params,
6482 * Link is up only if both local phy and external phy (in case of
6483 * non-direct board) are up and no fault detected on active PHY.
6485 vars->link_up = (vars->phy_link_up &&
6487 SINGLE_MEDIA_DIRECT(params)) &&
6488 (phy_vars[active_external_phy].fault_detected == 0));
6491 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6493 rc = bnx2x_update_link_down(params, vars);
6499 /*****************************************************************************/
6500 /* External Phy section */
6501 /*****************************************************************************/
6502 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6504 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6505 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6507 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6508 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6511 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6512 u32 spirom_ver, u32 ver_addr)
6514 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6515 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6518 REG_WR(bp, ver_addr, spirom_ver);
6521 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6522 struct bnx2x_phy *phy,
6525 u16 fw_ver1, fw_ver2;
6527 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6528 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6529 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6530 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6531 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6535 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6536 struct bnx2x_phy *phy,
6537 struct link_vars *vars)
6540 bnx2x_cl45_read(bp, phy,
6542 MDIO_AN_REG_STATUS, &val);
6543 bnx2x_cl45_read(bp, phy,
6545 MDIO_AN_REG_STATUS, &val);
6547 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6548 if ((val & (1<<0)) == 0)
6549 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6552 /******************************************************************/
6553 /* common BCM8073/BCM8727 PHY SECTION */
6554 /******************************************************************/
6555 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6556 struct link_params *params,
6557 struct link_vars *vars)
6559 struct bnx2x *bp = params->bp;
6560 if (phy->req_line_speed == SPEED_10 ||
6561 phy->req_line_speed == SPEED_100) {
6562 vars->flow_ctrl = phy->req_flow_ctrl;
6566 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6567 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6569 u16 ld_pause; /* local */
6570 u16 lp_pause; /* link partner */
6571 bnx2x_cl45_read(bp, phy,
6573 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6575 bnx2x_cl45_read(bp, phy,
6577 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6578 pause_result = (ld_pause &
6579 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6580 pause_result |= (lp_pause &
6581 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6583 bnx2x_pause_resolve(vars, pause_result);
6584 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6588 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6589 struct bnx2x_phy *phy,
6593 u16 fw_ver1, fw_msgout;
6596 /* Boot port from external ROM */
6598 bnx2x_cl45_write(bp, phy,
6600 MDIO_PMA_REG_GEN_CTRL,
6603 /* ucode reboot and rst */
6604 bnx2x_cl45_write(bp, phy,
6606 MDIO_PMA_REG_GEN_CTRL,
6609 bnx2x_cl45_write(bp, phy,
6611 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6613 /* Reset internal microprocessor */
6614 bnx2x_cl45_write(bp, phy,
6616 MDIO_PMA_REG_GEN_CTRL,
6617 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6619 /* Release srst bit */
6620 bnx2x_cl45_write(bp, phy,
6622 MDIO_PMA_REG_GEN_CTRL,
6623 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6625 /* Delay 100ms per the PHY specifications */
6628 /* 8073 sometimes taking longer to download */
6633 "bnx2x_8073_8727_external_rom_boot port %x:"
6634 "Download failed. fw version = 0x%x\n",
6640 bnx2x_cl45_read(bp, phy,
6642 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6643 bnx2x_cl45_read(bp, phy,
6645 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6648 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6649 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6650 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6652 /* Clear ser_boot_ctl bit */
6653 bnx2x_cl45_write(bp, phy,
6655 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6656 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6659 "bnx2x_8073_8727_external_rom_boot port %x:"
6660 "Download complete. fw version = 0x%x\n",
6666 /******************************************************************/
6667 /* BCM8073 PHY SECTION */
6668 /******************************************************************/
6669 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6671 /* This is only required for 8073A1, version 102 only */
6674 /* Read 8073 HW revision*/
6675 bnx2x_cl45_read(bp, phy,
6677 MDIO_PMA_REG_8073_CHIP_REV, &val);
6680 /* No need to workaround in 8073 A1 */
6684 bnx2x_cl45_read(bp, phy,
6686 MDIO_PMA_REG_ROM_VER2, &val);
6688 /* SNR should be applied only for version 0x102 */
6695 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6697 u16 val, cnt, cnt1 ;
6699 bnx2x_cl45_read(bp, phy,
6701 MDIO_PMA_REG_8073_CHIP_REV, &val);
6704 /* No need to workaround in 8073 A1 */
6707 /* XAUI workaround in 8073 A0: */
6710 * After loading the boot ROM and restarting Autoneg, poll
6714 for (cnt = 0; cnt < 1000; cnt++) {
6715 bnx2x_cl45_read(bp, phy,
6717 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6720 * If bit [14] = 0 or bit [13] = 0, continue on with
6721 * system initialization (XAUI work-around not required, as
6722 * these bits indicate 2.5G or 1G link up).
6724 if (!(val & (1<<14)) || !(val & (1<<13))) {
6725 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6727 } else if (!(val & (1<<15))) {
6728 DP(NETIF_MSG_LINK, "bit 15 went off\n");
6730 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6731 * MSB (bit15) goes to 1 (indicating that the XAUI
6732 * workaround has completed), then continue on with
6733 * system initialization.
6735 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6736 bnx2x_cl45_read(bp, phy,
6738 MDIO_PMA_REG_8073_XAUI_WA, &val);
6739 if (val & (1<<15)) {
6741 "XAUI workaround has completed\n");
6750 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6754 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6756 /* Force KR or KX */
6757 bnx2x_cl45_write(bp, phy,
6758 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6759 bnx2x_cl45_write(bp, phy,
6760 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6761 bnx2x_cl45_write(bp, phy,
6762 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6763 bnx2x_cl45_write(bp, phy,
6764 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6767 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6768 struct bnx2x_phy *phy,
6769 struct link_vars *vars)
6772 struct bnx2x *bp = params->bp;
6773 bnx2x_cl45_read(bp, phy,
6774 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6776 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6777 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6778 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6779 if ((vars->ieee_fc &
6780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6781 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6782 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6784 if ((vars->ieee_fc &
6785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6786 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6787 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6789 if ((vars->ieee_fc &
6790 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6791 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6792 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6795 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6797 bnx2x_cl45_write(bp, phy,
6798 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6802 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6803 struct link_params *params,
6804 struct link_vars *vars)
6806 struct bnx2x *bp = params->bp;
6809 DP(NETIF_MSG_LINK, "Init 8073\n");
6812 gpio_port = BP_PATH(bp);
6814 gpio_port = params->port;
6815 /* Restore normal power mode*/
6816 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6817 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6819 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6820 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6823 bnx2x_cl45_write(bp, phy,
6824 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
6825 bnx2x_cl45_write(bp, phy,
6826 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
6828 bnx2x_8073_set_pause_cl37(params, phy, vars);
6830 bnx2x_cl45_read(bp, phy,
6831 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6833 bnx2x_cl45_read(bp, phy,
6834 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
6836 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6838 /* Swap polarity if required - Must be done only in non-1G mode */
6839 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6840 /* Configure the 8073 to swap _P and _N of the KR lines */
6841 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6842 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6843 bnx2x_cl45_read(bp, phy,
6845 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6846 bnx2x_cl45_write(bp, phy,
6848 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6853 /* Enable CL37 BAM */
6854 if (REG_RD(bp, params->shmem_base +
6855 offsetof(struct shmem_region, dev_info.
6856 port_hw_config[params->port].default_cfg)) &
6857 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6859 bnx2x_cl45_read(bp, phy,
6861 MDIO_AN_REG_8073_BAM, &val);
6862 bnx2x_cl45_write(bp, phy,
6864 MDIO_AN_REG_8073_BAM, val | 1);
6865 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6867 if (params->loopback_mode == LOOPBACK_EXT) {
6868 bnx2x_807x_force_10G(bp, phy);
6869 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6872 bnx2x_cl45_write(bp, phy,
6873 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6875 if (phy->req_line_speed != SPEED_AUTO_NEG) {
6876 if (phy->req_line_speed == SPEED_10000) {
6878 } else if (phy->req_line_speed == SPEED_2500) {
6881 * Note that 2.5G works only when used with 1G
6888 if (phy->speed_cap_mask &
6889 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6892 /* Note that 2.5G works only when used with 1G advertisement */
6893 if (phy->speed_cap_mask &
6894 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6895 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6897 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6900 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6901 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6903 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6904 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6905 (phy->req_line_speed == SPEED_2500)) {
6907 /* Allow 2.5G for A1 and above */
6908 bnx2x_cl45_read(bp, phy,
6909 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6911 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6917 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6921 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6922 /* Add support for CL37 (passive mode) II */
6924 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6925 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6926 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6929 /* Add support for CL37 (passive mode) III */
6930 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6933 * The SNR will improve about 2db by changing BW and FEE main
6934 * tap. Rest commands are executed after link is up
6935 * Change FFE main cursor to 5 in EDC register
6937 if (bnx2x_8073_is_snr_needed(bp, phy))
6938 bnx2x_cl45_write(bp, phy,
6939 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6942 /* Enable FEC (Forware Error Correction) Request in the AN */
6943 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6945 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6947 bnx2x_ext_phy_set_pause(params, phy, vars);
6949 /* Restart autoneg */
6951 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6952 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6953 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6957 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6958 struct link_params *params,
6959 struct link_vars *vars)
6961 struct bnx2x *bp = params->bp;
6964 u16 link_status = 0;
6965 u16 an1000_status = 0;
6967 bnx2x_cl45_read(bp, phy,
6968 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6970 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
6972 /* clear the interrupt LASI status register */
6973 bnx2x_cl45_read(bp, phy,
6974 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6975 bnx2x_cl45_read(bp, phy,
6976 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6977 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
6979 bnx2x_cl45_read(bp, phy,
6980 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6982 /* Check the LASI */
6983 bnx2x_cl45_read(bp, phy,
6984 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
6986 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
6988 /* Check the link status */
6989 bnx2x_cl45_read(bp, phy,
6990 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6991 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
6993 bnx2x_cl45_read(bp, phy,
6994 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6995 bnx2x_cl45_read(bp, phy,
6996 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6997 link_up = ((val1 & 4) == 4);
6998 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7001 ((phy->req_line_speed != SPEED_10000))) {
7002 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7005 bnx2x_cl45_read(bp, phy,
7006 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7007 bnx2x_cl45_read(bp, phy,
7008 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7010 /* Check the link status on 1.1.2 */
7011 bnx2x_cl45_read(bp, phy,
7012 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7013 bnx2x_cl45_read(bp, phy,
7014 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7015 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7016 "an_link_status=0x%x\n", val2, val1, an1000_status);
7018 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7019 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7021 * The SNR will improve about 2dbby changing the BW and FEE main
7022 * tap. The 1st write to change FFE main tap is set before
7023 * restart AN. Change PLL Bandwidth in EDC register
7025 bnx2x_cl45_write(bp, phy,
7026 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7029 /* Change CDR Bandwidth in EDC register */
7030 bnx2x_cl45_write(bp, phy,
7031 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7034 bnx2x_cl45_read(bp, phy,
7035 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7038 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7039 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7041 vars->line_speed = SPEED_10000;
7042 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7044 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7046 vars->line_speed = SPEED_2500;
7047 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7049 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7051 vars->line_speed = SPEED_1000;
7052 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7056 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7061 /* Swap polarity if required */
7062 if (params->lane_config &
7063 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7064 /* Configure the 8073 to swap P and N of the KR lines */
7065 bnx2x_cl45_read(bp, phy,
7067 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7069 * Set bit 3 to invert Rx in 1G mode and clear this bit
7070 * when it`s in 10G mode.
7072 if (vars->line_speed == SPEED_1000) {
7073 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7079 bnx2x_cl45_write(bp, phy,
7081 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7084 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7085 bnx2x_8073_resolve_fc(phy, params, vars);
7086 vars->duplex = DUPLEX_FULL;
7091 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7092 struct link_params *params)
7094 struct bnx2x *bp = params->bp;
7097 gpio_port = BP_PATH(bp);
7099 gpio_port = params->port;
7100 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7102 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7103 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7107 /******************************************************************/
7108 /* BCM8705 PHY SECTION */
7109 /******************************************************************/
7110 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7111 struct link_params *params,
7112 struct link_vars *vars)
7114 struct bnx2x *bp = params->bp;
7115 DP(NETIF_MSG_LINK, "init 8705\n");
7116 /* Restore normal power mode*/
7117 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7118 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7120 bnx2x_ext_phy_hw_reset(bp, params->port);
7121 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7122 bnx2x_wait_reset_complete(bp, phy, params);
7124 bnx2x_cl45_write(bp, phy,
7125 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7126 bnx2x_cl45_write(bp, phy,
7127 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7128 bnx2x_cl45_write(bp, phy,
7129 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7130 bnx2x_cl45_write(bp, phy,
7131 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7132 /* BCM8705 doesn't have microcode, hence the 0 */
7133 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7137 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7138 struct link_params *params,
7139 struct link_vars *vars)
7143 struct bnx2x *bp = params->bp;
7144 DP(NETIF_MSG_LINK, "read status 8705\n");
7145 bnx2x_cl45_read(bp, phy,
7146 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7147 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7149 bnx2x_cl45_read(bp, phy,
7150 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7151 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7153 bnx2x_cl45_read(bp, phy,
7154 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7156 bnx2x_cl45_read(bp, phy,
7157 MDIO_PMA_DEVAD, 0xc809, &val1);
7158 bnx2x_cl45_read(bp, phy,
7159 MDIO_PMA_DEVAD, 0xc809, &val1);
7161 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7162 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7164 vars->line_speed = SPEED_10000;
7165 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7170 /******************************************************************/
7171 /* SFP+ module Section */
7172 /******************************************************************/
7173 static u8 bnx2x_get_gpio_port(struct link_params *params)
7176 u32 swap_val, swap_override;
7177 struct bnx2x *bp = params->bp;
7179 gpio_port = BP_PATH(bp);
7181 gpio_port = params->port;
7182 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7183 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7184 return gpio_port ^ (swap_val && swap_override);
7187 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7188 struct bnx2x_phy *phy,
7192 u8 port = params->port;
7193 struct bnx2x *bp = params->bp;
7196 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7197 tx_en_mode = REG_RD(bp, params->shmem_base +
7198 offsetof(struct shmem_region,
7199 dev_info.port_hw_config[port].sfp_ctrl)) &
7200 PORT_HW_CFG_TX_LASER_MASK;
7201 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7202 "mode = %x\n", tx_en, port, tx_en_mode);
7203 switch (tx_en_mode) {
7204 case PORT_HW_CFG_TX_LASER_MDIO:
7206 bnx2x_cl45_read(bp, phy,
7208 MDIO_PMA_REG_PHY_IDENTIFIER,
7216 bnx2x_cl45_write(bp, phy,
7218 MDIO_PMA_REG_PHY_IDENTIFIER,
7221 case PORT_HW_CFG_TX_LASER_GPIO0:
7222 case PORT_HW_CFG_TX_LASER_GPIO1:
7223 case PORT_HW_CFG_TX_LASER_GPIO2:
7224 case PORT_HW_CFG_TX_LASER_GPIO3:
7227 u8 gpio_port, gpio_mode;
7229 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7231 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7233 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7234 gpio_port = bnx2x_get_gpio_port(params);
7235 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7239 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7244 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7245 struct bnx2x_phy *phy,
7248 struct bnx2x *bp = params->bp;
7249 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7251 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7253 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7256 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7257 struct link_params *params,
7258 u16 addr, u8 byte_cnt, u8 *o_buf)
7260 struct bnx2x *bp = params->bp;
7263 if (byte_cnt > 16) {
7264 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7265 " is limited to 0xf\n");
7268 /* Set the read command byte count */
7269 bnx2x_cl45_write(bp, phy,
7270 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7271 (byte_cnt | 0xa000));
7273 /* Set the read command address */
7274 bnx2x_cl45_write(bp, phy,
7275 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7278 /* Activate read command */
7279 bnx2x_cl45_write(bp, phy,
7280 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7283 /* Wait up to 500us for command complete status */
7284 for (i = 0; i < 100; i++) {
7285 bnx2x_cl45_read(bp, phy,
7287 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7288 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7289 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7294 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7295 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7297 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7298 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7302 /* Read the buffer */
7303 for (i = 0; i < byte_cnt; i++) {
7304 bnx2x_cl45_read(bp, phy,
7306 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7307 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7310 for (i = 0; i < 100; i++) {
7311 bnx2x_cl45_read(bp, phy,
7313 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7314 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7315 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7322 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7323 struct link_params *params,
7324 u16 addr, u8 byte_cnt,
7328 u8 i, j = 0, cnt = 0;
7331 struct bnx2x *bp = params->bp;
7332 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7333 " addr %d, cnt %d\n",
7335 if (byte_cnt > 16) {
7336 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7337 " is limited to 16 bytes\n");
7341 /* 4 byte aligned address */
7342 addr32 = addr & (~0x3);
7344 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7346 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7349 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7350 o_buf[j] = *((u8 *)data_array + i);
7358 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7359 struct link_params *params,
7360 u16 addr, u8 byte_cnt, u8 *o_buf)
7362 struct bnx2x *bp = params->bp;
7365 if (byte_cnt > 16) {
7366 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7367 " is limited to 0xf\n");
7371 /* Need to read from 1.8000 to clear it */
7372 bnx2x_cl45_read(bp, phy,
7374 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7377 /* Set the read command byte count */
7378 bnx2x_cl45_write(bp, phy,
7380 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7381 ((byte_cnt < 2) ? 2 : byte_cnt));
7383 /* Set the read command address */
7384 bnx2x_cl45_write(bp, phy,
7386 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7388 /* Set the destination address */
7389 bnx2x_cl45_write(bp, phy,
7392 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7394 /* Activate read command */
7395 bnx2x_cl45_write(bp, phy,
7397 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7400 * Wait appropriate time for two-wire command to finish before
7401 * polling the status register
7405 /* Wait up to 500us for command complete status */
7406 for (i = 0; i < 100; i++) {
7407 bnx2x_cl45_read(bp, phy,
7409 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7410 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7411 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7416 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7417 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7419 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7420 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7424 /* Read the buffer */
7425 for (i = 0; i < byte_cnt; i++) {
7426 bnx2x_cl45_read(bp, phy,
7428 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7429 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7432 for (i = 0; i < 100; i++) {
7433 bnx2x_cl45_read(bp, phy,
7435 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7436 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7437 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7445 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7446 struct link_params *params, u16 addr,
7447 u8 byte_cnt, u8 *o_buf)
7450 switch (phy->type) {
7451 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7452 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7455 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7456 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7457 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7460 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7461 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7468 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7469 struct link_params *params,
7472 struct bnx2x *bp = params->bp;
7473 u32 sync_offset = 0, phy_idx, media_types;
7474 u8 val, check_limiting_mode = 0;
7475 *edc_mode = EDC_MODE_LIMITING;
7477 phy->media_type = ETH_PHY_UNSPECIFIED;
7478 /* First check for copper cable */
7479 if (bnx2x_read_sfp_module_eeprom(phy,
7481 SFP_EEPROM_CON_TYPE_ADDR,
7484 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7489 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7491 u8 copper_module_type;
7492 phy->media_type = ETH_PHY_DA_TWINAX;
7494 * Check if its active cable (includes SFP+ module)
7497 if (bnx2x_read_sfp_module_eeprom(phy,
7499 SFP_EEPROM_FC_TX_TECH_ADDR,
7501 &copper_module_type) != 0) {
7503 "Failed to read copper-cable-type"
7504 " from SFP+ EEPROM\n");
7508 if (copper_module_type &
7509 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7510 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7511 check_limiting_mode = 1;
7512 } else if (copper_module_type &
7513 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7514 DP(NETIF_MSG_LINK, "Passive Copper"
7515 " cable detected\n");
7517 EDC_MODE_PASSIVE_DAC;
7519 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7520 "type 0x%x !!!\n", copper_module_type);
7525 case SFP_EEPROM_CON_TYPE_VAL_LC:
7526 phy->media_type = ETH_PHY_SFP_FIBER;
7527 DP(NETIF_MSG_LINK, "Optic module detected\n");
7528 check_limiting_mode = 1;
7531 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7535 sync_offset = params->shmem_base +
7536 offsetof(struct shmem_region,
7537 dev_info.port_hw_config[params->port].media_type);
7538 media_types = REG_RD(bp, sync_offset);
7539 /* Update media type for non-PMF sync */
7540 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7541 if (&(params->phy[phy_idx]) == phy) {
7542 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7543 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7544 media_types |= ((phy->media_type &
7545 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7546 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7550 REG_WR(bp, sync_offset, media_types);
7551 if (check_limiting_mode) {
7552 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7553 if (bnx2x_read_sfp_module_eeprom(phy,
7555 SFP_EEPROM_OPTIONS_ADDR,
7556 SFP_EEPROM_OPTIONS_SIZE,
7558 DP(NETIF_MSG_LINK, "Failed to read Option"
7559 " field from module EEPROM\n");
7562 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7563 *edc_mode = EDC_MODE_LINEAR;
7565 *edc_mode = EDC_MODE_LIMITING;
7567 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7571 * This function read the relevant field from the module (SFP+), and verify it
7572 * is compliant with this board
7574 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7575 struct link_params *params)
7577 struct bnx2x *bp = params->bp;
7579 u32 fw_resp, fw_cmd_param;
7580 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7581 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7582 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7583 val = REG_RD(bp, params->shmem_base +
7584 offsetof(struct shmem_region, dev_info.
7585 port_feature_config[params->port].config));
7586 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7587 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7588 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7592 if (params->feature_config_flags &
7593 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7594 /* Use specific phy request */
7595 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7596 } else if (params->feature_config_flags &
7597 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7598 /* Use first phy request only in case of non-dual media*/
7599 if (DUAL_MEDIA(params)) {
7600 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7604 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7606 /* No support in OPT MDL detection */
7607 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7612 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7613 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7614 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7615 DP(NETIF_MSG_LINK, "Approved module\n");
7619 /* format the warning message */
7620 if (bnx2x_read_sfp_module_eeprom(phy,
7622 SFP_EEPROM_VENDOR_NAME_ADDR,
7623 SFP_EEPROM_VENDOR_NAME_SIZE,
7625 vendor_name[0] = '\0';
7627 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7628 if (bnx2x_read_sfp_module_eeprom(phy,
7630 SFP_EEPROM_PART_NO_ADDR,
7631 SFP_EEPROM_PART_NO_SIZE,
7633 vendor_pn[0] = '\0';
7635 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7637 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7638 " Port %d from %s part number %s\n",
7639 params->port, vendor_name, vendor_pn);
7640 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7644 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7645 struct link_params *params)
7649 struct bnx2x *bp = params->bp;
7652 * Initialization time after hot-plug may take up to 300ms for
7653 * some phys type ( e.g. JDSU )
7656 for (timeout = 0; timeout < 60; timeout++) {
7657 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7659 DP(NETIF_MSG_LINK, "SFP+ module initialization "
7660 "took %d ms\n", timeout * 5);
7668 static void bnx2x_8727_power_module(struct bnx2x *bp,
7669 struct bnx2x_phy *phy,
7671 /* Make sure GPIOs are not using for LED mode */
7674 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7675 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7677 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7678 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7679 * where the 1st bit is the over-current(only input), and 2nd bit is
7680 * for power( only output )
7682 * In case of NOC feature is disabled and power is up, set GPIO control
7683 * as input to enable listening of over-current indication
7685 if (phy->flags & FLAGS_NOC)
7691 * Set GPIO control to OUTPUT, and set the power bit
7692 * to according to the is_power_up
7696 bnx2x_cl45_write(bp, phy,
7698 MDIO_PMA_REG_8727_GPIO_CTRL,
7702 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7703 struct bnx2x_phy *phy,
7706 u16 cur_limiting_mode;
7708 bnx2x_cl45_read(bp, phy,
7710 MDIO_PMA_REG_ROM_VER2,
7711 &cur_limiting_mode);
7712 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7715 if (edc_mode == EDC_MODE_LIMITING) {
7716 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7717 bnx2x_cl45_write(bp, phy,
7719 MDIO_PMA_REG_ROM_VER2,
7721 } else { /* LRM mode ( default )*/
7723 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7726 * Changing to LRM mode takes quite few seconds. So do it only
7727 * if current mode is limiting (default is LRM)
7729 if (cur_limiting_mode != EDC_MODE_LIMITING)
7732 bnx2x_cl45_write(bp, phy,
7734 MDIO_PMA_REG_LRM_MODE,
7736 bnx2x_cl45_write(bp, phy,
7738 MDIO_PMA_REG_ROM_VER2,
7740 bnx2x_cl45_write(bp, phy,
7742 MDIO_PMA_REG_MISC_CTRL0,
7744 bnx2x_cl45_write(bp, phy,
7746 MDIO_PMA_REG_LRM_MODE,
7752 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7753 struct bnx2x_phy *phy,
7758 bnx2x_cl45_read(bp, phy,
7760 MDIO_PMA_REG_PHY_IDENTIFIER,
7763 bnx2x_cl45_write(bp, phy,
7765 MDIO_PMA_REG_PHY_IDENTIFIER,
7766 (phy_identifier & ~(1<<9)));
7768 bnx2x_cl45_read(bp, phy,
7770 MDIO_PMA_REG_ROM_VER2,
7772 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7773 bnx2x_cl45_write(bp, phy,
7775 MDIO_PMA_REG_ROM_VER2,
7776 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7778 bnx2x_cl45_write(bp, phy,
7780 MDIO_PMA_REG_PHY_IDENTIFIER,
7781 (phy_identifier | (1<<9)));
7786 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7787 struct link_params *params,
7790 struct bnx2x *bp = params->bp;
7794 bnx2x_sfp_set_transmitter(params, phy, 0);
7797 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7798 bnx2x_sfp_set_transmitter(params, phy, 1);
7801 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7807 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7810 struct bnx2x *bp = params->bp;
7812 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7813 offsetof(struct shmem_region,
7814 dev_info.port_hw_config[params->port].sfp_ctrl)) &
7815 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7816 switch (fault_led_gpio) {
7817 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7819 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7820 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7821 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7822 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7824 u8 gpio_port = bnx2x_get_gpio_port(params);
7825 u16 gpio_pin = fault_led_gpio -
7826 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7827 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7828 "pin %x port %x mode %x\n",
7829 gpio_pin, gpio_port, gpio_mode);
7830 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7834 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7839 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7843 u8 port = params->port;
7844 struct bnx2x *bp = params->bp;
7845 pin_cfg = (REG_RD(bp, params->shmem_base +
7846 offsetof(struct shmem_region,
7847 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7848 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7849 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7850 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7851 gpio_mode, pin_cfg);
7852 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7855 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7858 struct bnx2x *bp = params->bp;
7859 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7860 if (CHIP_IS_E3(bp)) {
7862 * Low ==> if SFP+ module is supported otherwise
7863 * High ==> if SFP+ module is not on the approved vendor list
7865 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7867 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7870 static void bnx2x_warpcore_power_module(struct link_params *params,
7871 struct bnx2x_phy *phy,
7875 struct bnx2x *bp = params->bp;
7877 pin_cfg = (REG_RD(bp, params->shmem_base +
7878 offsetof(struct shmem_region,
7879 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7880 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7881 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7882 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7885 * Low ==> corresponding SFP+ module is powered
7886 * high ==> the SFP+ module is powered down
7888 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7891 static void bnx2x_power_sfp_module(struct link_params *params,
7892 struct bnx2x_phy *phy,
7895 struct bnx2x *bp = params->bp;
7896 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7898 switch (phy->type) {
7899 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7900 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7901 bnx2x_8727_power_module(params->bp, phy, power);
7903 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7904 bnx2x_warpcore_power_module(params, phy, power);
7910 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7911 struct bnx2x_phy *phy,
7915 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7916 struct bnx2x *bp = params->bp;
7918 u8 lane = bnx2x_get_warpcore_lane(phy, params);
7919 /* This is a global register which controls all lanes */
7920 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7921 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7922 val &= ~(0xf << (lane << 2));
7925 case EDC_MODE_LINEAR:
7926 case EDC_MODE_LIMITING:
7927 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7929 case EDC_MODE_PASSIVE_DAC:
7930 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
7936 val |= (mode << (lane << 2));
7937 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
7938 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
7940 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7941 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7946 static void bnx2x_set_limiting_mode(struct link_params *params,
7947 struct bnx2x_phy *phy,
7950 switch (phy->type) {
7951 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7952 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
7954 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7955 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7956 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
7958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7959 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
7964 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
7965 struct link_params *params)
7967 struct bnx2x *bp = params->bp;
7971 u32 val = REG_RD(bp, params->shmem_base +
7972 offsetof(struct shmem_region, dev_info.
7973 port_feature_config[params->port].config));
7975 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
7977 /* Power up module */
7978 bnx2x_power_sfp_module(params, phy, 1);
7979 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
7980 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
7982 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
7983 /* check SFP+ module compatibility */
7984 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
7986 /* Turn on fault module-detected led */
7987 bnx2x_set_sfp_module_fault_led(params,
7988 MISC_REGISTERS_GPIO_HIGH);
7990 /* Check if need to power down the SFP+ module */
7991 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7992 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
7993 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
7994 bnx2x_power_sfp_module(params, phy, 0);
7998 /* Turn off fault module-detected led */
7999 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8003 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8004 * is done automatically
8006 bnx2x_set_limiting_mode(params, phy, edc_mode);
8009 * Enable transmit for this module if the module is approved, or
8010 * if unapproved modules should also enable the Tx laser
8013 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8014 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8015 bnx2x_sfp_set_transmitter(params, phy, 1);
8017 bnx2x_sfp_set_transmitter(params, phy, 0);
8022 void bnx2x_handle_module_detect_int(struct link_params *params)
8024 struct bnx2x *bp = params->bp;
8025 struct bnx2x_phy *phy;
8027 u8 gpio_num, gpio_port;
8029 phy = ¶ms->phy[INT_PHY];
8031 phy = ¶ms->phy[EXT_PHY1];
8033 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8034 params->port, &gpio_num, &gpio_port) ==
8036 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8040 /* Set valid module led off */
8041 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8043 /* Get current gpio val reflecting module plugged in / out*/
8044 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8046 /* Call the handling function in case module is detected */
8047 if (gpio_val == 0) {
8048 bnx2x_power_sfp_module(params, phy, 1);
8049 bnx2x_set_gpio_int(bp, gpio_num,
8050 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8052 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8053 bnx2x_sfp_module_detection(phy, params);
8055 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8057 u32 val = REG_RD(bp, params->shmem_base +
8058 offsetof(struct shmem_region, dev_info.
8059 port_feature_config[params->port].
8062 bnx2x_set_gpio_int(bp, gpio_num,
8063 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8066 * Module was plugged out.
8067 * Disable transmit for this module
8069 phy->media_type = ETH_PHY_NOT_PRESENT;
8070 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8071 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8072 bnx2x_sfp_set_transmitter(params, phy, 0);
8076 /******************************************************************/
8077 /* Used by 8706 and 8727 */
8078 /******************************************************************/
8079 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8080 struct bnx2x_phy *phy,
8081 u16 alarm_status_offset,
8082 u16 alarm_ctrl_offset)
8084 u16 alarm_status, val;
8085 bnx2x_cl45_read(bp, phy,
8086 MDIO_PMA_DEVAD, alarm_status_offset,
8088 bnx2x_cl45_read(bp, phy,
8089 MDIO_PMA_DEVAD, alarm_status_offset,
8091 /* Mask or enable the fault event. */
8092 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8093 if (alarm_status & (1<<0))
8097 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8099 /******************************************************************/
8100 /* common BCM8706/BCM8726 PHY SECTION */
8101 /******************************************************************/
8102 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8103 struct link_params *params,
8104 struct link_vars *vars)
8107 u16 val1, val2, rx_sd, pcs_status;
8108 struct bnx2x *bp = params->bp;
8109 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8111 bnx2x_cl45_read(bp, phy,
8112 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
8114 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
8115 MDIO_PMA_REG_TX_ALARM_CTRL);
8117 /* clear LASI indication*/
8118 bnx2x_cl45_read(bp, phy,
8119 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
8120 bnx2x_cl45_read(bp, phy,
8121 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
8122 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8124 bnx2x_cl45_read(bp, phy,
8125 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8126 bnx2x_cl45_read(bp, phy,
8127 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8128 bnx2x_cl45_read(bp, phy,
8129 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8130 bnx2x_cl45_read(bp, phy,
8131 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8133 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8134 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8136 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8137 * are set, or if the autoneg bit 1 is set
8139 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8142 vars->line_speed = SPEED_1000;
8144 vars->line_speed = SPEED_10000;
8145 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8146 vars->duplex = DUPLEX_FULL;
8149 /* Capture 10G link fault. Read twice to clear stale value. */
8150 if (vars->line_speed == SPEED_10000) {
8151 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8152 MDIO_PMA_REG_TX_ALARM, &val1);
8153 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8154 MDIO_PMA_REG_TX_ALARM, &val1);
8156 vars->fault_detected = 1;
8162 /******************************************************************/
8163 /* BCM8706 PHY SECTION */
8164 /******************************************************************/
8165 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8166 struct link_params *params,
8167 struct link_vars *vars)
8171 struct bnx2x *bp = params->bp;
8173 /* SPF+ PHY: Set flag to check for Tx error */
8174 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8176 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8177 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8179 bnx2x_ext_phy_hw_reset(bp, params->port);
8180 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8181 bnx2x_wait_reset_complete(bp, phy, params);
8183 /* Wait until fw is loaded */
8184 for (cnt = 0; cnt < 100; cnt++) {
8185 bnx2x_cl45_read(bp, phy,
8186 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8191 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8192 if ((params->feature_config_flags &
8193 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8196 for (i = 0; i < 4; i++) {
8197 reg = MDIO_XS_8706_REG_BANK_RX0 +
8198 i*(MDIO_XS_8706_REG_BANK_RX1 -
8199 MDIO_XS_8706_REG_BANK_RX0);
8200 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8201 /* Clear first 3 bits of the control */
8203 /* Set control bits according to configuration */
8204 val |= (phy->rx_preemphasis[i] & 0x7);
8205 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8206 " reg 0x%x <-- val 0x%x\n", reg, val);
8207 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8211 if (phy->req_line_speed == SPEED_10000) {
8212 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8214 bnx2x_cl45_write(bp, phy,
8216 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8217 bnx2x_cl45_write(bp, phy,
8218 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
8220 /* Arm LASI for link and Tx fault. */
8221 bnx2x_cl45_write(bp, phy,
8222 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 3);
8224 /* Force 1Gbps using autoneg with 1G advertisement */
8226 /* Allow CL37 through CL73 */
8227 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8228 bnx2x_cl45_write(bp, phy,
8229 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8231 /* Enable Full-Duplex advertisement on CL37 */
8232 bnx2x_cl45_write(bp, phy,
8233 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8234 /* Enable CL37 AN */
8235 bnx2x_cl45_write(bp, phy,
8236 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8238 bnx2x_cl45_write(bp, phy,
8239 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8241 /* Enable clause 73 AN */
8242 bnx2x_cl45_write(bp, phy,
8243 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8244 bnx2x_cl45_write(bp, phy,
8245 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
8247 bnx2x_cl45_write(bp, phy,
8248 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
8251 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8254 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8255 * power mode, if TX Laser is disabled
8258 tx_en_mode = REG_RD(bp, params->shmem_base +
8259 offsetof(struct shmem_region,
8260 dev_info.port_hw_config[params->port].sfp_ctrl))
8261 & PORT_HW_CFG_TX_LASER_MASK;
8263 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8264 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8265 bnx2x_cl45_read(bp, phy,
8266 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8268 bnx2x_cl45_write(bp, phy,
8269 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8275 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8276 struct link_params *params,
8277 struct link_vars *vars)
8279 return bnx2x_8706_8726_read_status(phy, params, vars);
8282 /******************************************************************/
8283 /* BCM8726 PHY SECTION */
8284 /******************************************************************/
8285 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8286 struct link_params *params)
8288 struct bnx2x *bp = params->bp;
8289 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8290 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8293 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8294 struct link_params *params)
8296 struct bnx2x *bp = params->bp;
8297 /* Need to wait 100ms after reset */
8300 /* Micro controller re-boot */
8301 bnx2x_cl45_write(bp, phy,
8302 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8304 /* Set soft reset */
8305 bnx2x_cl45_write(bp, phy,
8307 MDIO_PMA_REG_GEN_CTRL,
8308 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8310 bnx2x_cl45_write(bp, phy,
8312 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8314 bnx2x_cl45_write(bp, phy,
8316 MDIO_PMA_REG_GEN_CTRL,
8317 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8319 /* wait for 150ms for microcode load */
8322 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8323 bnx2x_cl45_write(bp, phy,
8325 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8328 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8331 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8332 struct link_params *params,
8333 struct link_vars *vars)
8335 struct bnx2x *bp = params->bp;
8337 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8339 bnx2x_cl45_read(bp, phy,
8340 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8342 if (val1 & (1<<15)) {
8343 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8345 vars->line_speed = 0;
8352 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8353 struct link_params *params,
8354 struct link_vars *vars)
8356 struct bnx2x *bp = params->bp;
8357 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8359 /* SPF+ PHY: Set flag to check for Tx error */
8360 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8362 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8363 bnx2x_wait_reset_complete(bp, phy, params);
8365 bnx2x_8726_external_rom_boot(phy, params);
8368 * Need to call module detected on initialization since the module
8369 * detection triggered by actual module insertion might occur before
8370 * driver is loaded, and when driver is loaded, it reset all
8371 * registers, including the transmitter
8373 bnx2x_sfp_module_detection(phy, params);
8375 if (phy->req_line_speed == SPEED_1000) {
8376 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8377 bnx2x_cl45_write(bp, phy,
8378 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8379 bnx2x_cl45_write(bp, phy,
8380 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8381 bnx2x_cl45_write(bp, phy,
8382 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
8383 bnx2x_cl45_write(bp, phy,
8384 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
8386 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8387 (phy->speed_cap_mask &
8388 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8389 ((phy->speed_cap_mask &
8390 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8391 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8392 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8393 /* Set Flow control */
8394 bnx2x_ext_phy_set_pause(params, phy, vars);
8395 bnx2x_cl45_write(bp, phy,
8396 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8397 bnx2x_cl45_write(bp, phy,
8398 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8399 bnx2x_cl45_write(bp, phy,
8400 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8401 bnx2x_cl45_write(bp, phy,
8402 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8403 bnx2x_cl45_write(bp, phy,
8404 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8406 * Enable RX-ALARM control to receive interrupt for 1G speed
8409 bnx2x_cl45_write(bp, phy,
8410 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
8411 bnx2x_cl45_write(bp, phy,
8412 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
8415 } else { /* Default 10G. Set only LASI control */
8416 bnx2x_cl45_write(bp, phy,
8417 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
8420 /* Set TX PreEmphasis if needed */
8421 if ((params->feature_config_flags &
8422 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8423 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8425 phy->tx_preemphasis[0],
8426 phy->tx_preemphasis[1]);
8427 bnx2x_cl45_write(bp, phy,
8429 MDIO_PMA_REG_8726_TX_CTRL1,
8430 phy->tx_preemphasis[0]);
8432 bnx2x_cl45_write(bp, phy,
8434 MDIO_PMA_REG_8726_TX_CTRL2,
8435 phy->tx_preemphasis[1]);
8442 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8443 struct link_params *params)
8445 struct bnx2x *bp = params->bp;
8446 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8447 /* Set serial boot control for external load */
8448 bnx2x_cl45_write(bp, phy,
8450 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8453 /******************************************************************/
8454 /* BCM8727 PHY SECTION */
8455 /******************************************************************/
8457 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8458 struct link_params *params, u8 mode)
8460 struct bnx2x *bp = params->bp;
8461 u16 led_mode_bitmask = 0;
8462 u16 gpio_pins_bitmask = 0;
8464 /* Only NOC flavor requires to set the LED specifically */
8465 if (!(phy->flags & FLAGS_NOC))
8468 case LED_MODE_FRONT_PANEL_OFF:
8470 led_mode_bitmask = 0;
8471 gpio_pins_bitmask = 0x03;
8474 led_mode_bitmask = 0;
8475 gpio_pins_bitmask = 0x02;
8478 led_mode_bitmask = 0x60;
8479 gpio_pins_bitmask = 0x11;
8482 bnx2x_cl45_read(bp, phy,
8484 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8487 val |= led_mode_bitmask;
8488 bnx2x_cl45_write(bp, phy,
8490 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8492 bnx2x_cl45_read(bp, phy,
8494 MDIO_PMA_REG_8727_GPIO_CTRL,
8497 val |= gpio_pins_bitmask;
8498 bnx2x_cl45_write(bp, phy,
8500 MDIO_PMA_REG_8727_GPIO_CTRL,
8503 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8504 struct link_params *params) {
8505 u32 swap_val, swap_override;
8508 * The PHY reset is controlled by GPIO 1. Fake the port number
8509 * to cancel the swap done in set_gpio()
8511 struct bnx2x *bp = params->bp;
8512 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8513 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8514 port = (swap_val && swap_override) ^ 1;
8515 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8516 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8519 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8520 struct link_params *params,
8521 struct link_vars *vars)
8524 u16 tmp1, val, mod_abs, tmp2;
8525 u16 rx_alarm_ctrl_val;
8527 struct bnx2x *bp = params->bp;
8528 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8530 /* SPF+ PHY: Set flag to check for Tx error */
8531 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8533 bnx2x_wait_reset_complete(bp, phy, params);
8534 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8535 /* Should be 0x6 to enable XS on Tx side. */
8536 lasi_ctrl_val = 0x0006;
8538 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8540 bnx2x_cl45_write(bp, phy,
8541 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
8543 bnx2x_cl45_write(bp, phy,
8544 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
8546 bnx2x_cl45_write(bp, phy,
8547 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
8550 * Initially configure MOD_ABS to interrupt when module is
8553 bnx2x_cl45_read(bp, phy,
8554 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8556 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8557 * When the EDC is off it locks onto a reference clock and avoids
8561 if (!(phy->flags & FLAGS_NOC))
8563 bnx2x_cl45_write(bp, phy,
8564 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8567 /* Make MOD_ABS give interrupt on change */
8568 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8571 if (phy->flags & FLAGS_NOC)
8575 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8576 * status which reflect SFP+ module over-current
8578 if (!(phy->flags & FLAGS_NOC))
8579 val &= 0xff8f; /* Reset bits 4-6 */
8580 bnx2x_cl45_write(bp, phy,
8581 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8583 bnx2x_8727_power_module(bp, phy, 1);
8585 bnx2x_cl45_read(bp, phy,
8586 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8588 bnx2x_cl45_read(bp, phy,
8589 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
8591 /* Set option 1G speed */
8592 if (phy->req_line_speed == SPEED_1000) {
8593 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8594 bnx2x_cl45_write(bp, phy,
8595 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8596 bnx2x_cl45_write(bp, phy,
8597 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8598 bnx2x_cl45_read(bp, phy,
8599 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8600 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8602 * Power down the XAUI until link is up in case of dual-media
8605 if (DUAL_MEDIA(params)) {
8606 bnx2x_cl45_read(bp, phy,
8608 MDIO_PMA_REG_8727_PCS_GP, &val);
8610 bnx2x_cl45_write(bp, phy,
8612 MDIO_PMA_REG_8727_PCS_GP, val);
8614 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8615 ((phy->speed_cap_mask &
8616 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8617 ((phy->speed_cap_mask &
8618 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8619 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8621 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8622 bnx2x_cl45_write(bp, phy,
8623 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8624 bnx2x_cl45_write(bp, phy,
8625 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8628 * Since the 8727 has only single reset pin, need to set the 10G
8629 * registers although it is default
8631 bnx2x_cl45_write(bp, phy,
8632 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8634 bnx2x_cl45_write(bp, phy,
8635 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8636 bnx2x_cl45_write(bp, phy,
8637 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8638 bnx2x_cl45_write(bp, phy,
8639 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8644 * Set 2-wire transfer rate of SFP+ module EEPROM
8645 * to 100Khz since some DACs(direct attached cables) do
8646 * not work at 400Khz.
8648 bnx2x_cl45_write(bp, phy,
8649 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8652 /* Set TX PreEmphasis if needed */
8653 if ((params->feature_config_flags &
8654 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8655 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8656 phy->tx_preemphasis[0],
8657 phy->tx_preemphasis[1]);
8658 bnx2x_cl45_write(bp, phy,
8659 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8660 phy->tx_preemphasis[0]);
8662 bnx2x_cl45_write(bp, phy,
8663 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8664 phy->tx_preemphasis[1]);
8668 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8669 * power mode, if TX Laser is disabled
8671 tx_en_mode = REG_RD(bp, params->shmem_base +
8672 offsetof(struct shmem_region,
8673 dev_info.port_hw_config[params->port].sfp_ctrl))
8674 & PORT_HW_CFG_TX_LASER_MASK;
8676 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8678 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8679 bnx2x_cl45_read(bp, phy,
8680 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8683 bnx2x_cl45_write(bp, phy,
8684 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8690 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8691 struct link_params *params)
8693 struct bnx2x *bp = params->bp;
8694 u16 mod_abs, rx_alarm_status;
8695 u32 val = REG_RD(bp, params->shmem_base +
8696 offsetof(struct shmem_region, dev_info.
8697 port_feature_config[params->port].
8699 bnx2x_cl45_read(bp, phy,
8701 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8702 if (mod_abs & (1<<8)) {
8704 /* Module is absent */
8705 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8706 "show module is absent\n");
8707 phy->media_type = ETH_PHY_NOT_PRESENT;
8709 * 1. Set mod_abs to detect next module
8711 * 2. Set EDC off by setting OPTXLOS signal input to low
8713 * When the EDC is off it locks onto a reference clock and
8714 * avoids becoming 'lost'.
8717 if (!(phy->flags & FLAGS_NOC))
8719 bnx2x_cl45_write(bp, phy,
8721 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8724 * Clear RX alarm since it stays up as long as
8725 * the mod_abs wasn't changed
8727 bnx2x_cl45_read(bp, phy,
8729 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
8732 /* Module is present */
8733 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8734 "show module is present\n");
8736 * First disable transmitter, and if the module is ok, the
8737 * module_detection will enable it
8738 * 1. Set mod_abs to detect next module absent event ( bit 8)
8739 * 2. Restore the default polarity of the OPRXLOS signal and
8740 * this signal will then correctly indicate the presence or
8741 * absence of the Rx signal. (bit 9)
8744 if (!(phy->flags & FLAGS_NOC))
8746 bnx2x_cl45_write(bp, phy,
8748 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8751 * Clear RX alarm since it stays up as long as the mod_abs
8752 * wasn't changed. This is need to be done before calling the
8753 * module detection, otherwise it will clear* the link update
8756 bnx2x_cl45_read(bp, phy,
8758 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
8761 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8762 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8763 bnx2x_sfp_set_transmitter(params, phy, 0);
8765 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8766 bnx2x_sfp_module_detection(phy, params);
8768 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8771 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8773 /* No need to check link status in case of module plugged in/out */
8776 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8777 struct link_params *params,
8778 struct link_vars *vars)
8781 struct bnx2x *bp = params->bp;
8782 u8 link_up = 0, oc_port = params->port;
8783 u16 link_status = 0;
8784 u16 rx_alarm_status, lasi_ctrl, val1;
8786 /* If PHY is not initialized, do not check link status */
8787 bnx2x_cl45_read(bp, phy,
8788 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
8793 /* Check the LASI on Rx */
8794 bnx2x_cl45_read(bp, phy,
8795 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
8797 vars->line_speed = 0;
8798 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
8800 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
8801 MDIO_PMA_REG_TX_ALARM_CTRL);
8803 bnx2x_cl45_read(bp, phy,
8804 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
8806 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8809 bnx2x_cl45_read(bp, phy,
8810 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8813 * If a module is present and there is need to check
8816 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8817 /* Check over-current using 8727 GPIO0 input*/
8818 bnx2x_cl45_read(bp, phy,
8819 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8822 if ((val1 & (1<<8)) == 0) {
8823 if (!CHIP_IS_E1x(bp))
8824 oc_port = BP_PATH(bp) + (params->port << 1);
8825 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8826 " on port %d\n", oc_port);
8827 netdev_err(bp->dev, "Error: Power fault on Port %d has"
8828 " been detected and the power to "
8829 "that SFP+ module has been removed"
8830 " to prevent failure of the card."
8831 " Please remove the SFP+ module and"
8832 " restart the system to clear this"
8835 /* Disable all RX_ALARMs except for mod_abs */
8836 bnx2x_cl45_write(bp, phy,
8838 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
8840 bnx2x_cl45_read(bp, phy,
8842 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8843 /* Wait for module_absent_event */
8845 bnx2x_cl45_write(bp, phy,
8847 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8848 /* Clear RX alarm */
8849 bnx2x_cl45_read(bp, phy,
8851 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
8854 } /* Over current check */
8856 /* When module absent bit is set, check module */
8857 if (rx_alarm_status & (1<<5)) {
8858 bnx2x_8727_handle_mod_abs(phy, params);
8859 /* Enable all mod_abs and link detection bits */
8860 bnx2x_cl45_write(bp, phy,
8861 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
8864 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8865 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8866 /* If transmitter is disabled, ignore false link up indication */
8867 bnx2x_cl45_read(bp, phy,
8868 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8869 if (val1 & (1<<15)) {
8870 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8874 bnx2x_cl45_read(bp, phy,
8876 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8879 * Bits 0..2 --> speed detected,
8880 * Bits 13..15--> link is down
8882 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8884 vars->line_speed = SPEED_10000;
8885 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8887 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8889 vars->line_speed = SPEED_1000;
8890 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8894 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8898 /* Capture 10G link fault. */
8899 if (vars->line_speed == SPEED_10000) {
8900 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8901 MDIO_PMA_REG_TX_ALARM, &val1);
8903 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8904 MDIO_PMA_REG_TX_ALARM, &val1);
8906 if (val1 & (1<<0)) {
8907 vars->fault_detected = 1;
8912 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8913 vars->duplex = DUPLEX_FULL;
8914 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8917 if ((DUAL_MEDIA(params)) &&
8918 (phy->req_line_speed == SPEED_1000)) {
8919 bnx2x_cl45_read(bp, phy,
8921 MDIO_PMA_REG_8727_PCS_GP, &val1);
8923 * In case of dual-media board and 1G, power up the XAUI side,
8924 * otherwise power it down. For 10G it is done automatically
8930 bnx2x_cl45_write(bp, phy,
8932 MDIO_PMA_REG_8727_PCS_GP, val1);
8937 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
8938 struct link_params *params)
8940 struct bnx2x *bp = params->bp;
8941 /* Disable Transmitter */
8942 bnx2x_sfp_set_transmitter(params, phy, 0);
8944 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
8948 /******************************************************************/
8949 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
8950 /******************************************************************/
8951 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
8952 struct link_params *params)
8954 u16 val, fw_ver1, fw_ver2, cnt;
8956 struct bnx2x *bp = params->bp;
8958 port = params->port;
8960 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
8961 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
8962 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
8963 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
8964 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
8965 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
8966 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
8968 for (cnt = 0; cnt < 100; cnt++) {
8969 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
8975 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
8976 bnx2x_save_spirom_version(bp, port, 0,
8982 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
8983 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
8984 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
8985 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
8986 for (cnt = 0; cnt < 100; cnt++) {
8987 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
8993 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
8994 bnx2x_save_spirom_version(bp, port, 0,
8999 /* lower 16 bits of the register SPI_FW_STATUS */
9000 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9001 /* upper 16 bits of register SPI_FW_STATUS */
9002 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9004 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9008 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9009 struct bnx2x_phy *phy)
9013 /* PHYC_CTL_LED_CTL */
9014 bnx2x_cl45_read(bp, phy,
9016 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9020 bnx2x_cl45_write(bp, phy,
9022 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9024 bnx2x_cl45_write(bp, phy,
9026 MDIO_PMA_REG_8481_LED1_MASK,
9029 bnx2x_cl45_write(bp, phy,
9031 MDIO_PMA_REG_8481_LED2_MASK,
9034 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9035 bnx2x_cl45_write(bp, phy,
9037 MDIO_PMA_REG_8481_LED3_MASK,
9040 /* Select the closest activity blink rate to that in 10/100/1000 */
9041 bnx2x_cl45_write(bp, phy,
9043 MDIO_PMA_REG_8481_LED3_BLINK,
9046 bnx2x_cl45_read(bp, phy,
9048 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9049 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9051 bnx2x_cl45_write(bp, phy,
9053 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9055 /* 'Interrupt Mask' */
9056 bnx2x_cl45_write(bp, phy,
9061 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9062 struct link_params *params,
9063 struct link_vars *vars)
9065 struct bnx2x *bp = params->bp;
9066 u16 autoneg_val, an_1000_val, an_10_100_val;
9067 u16 tmp_req_line_speed;
9069 tmp_req_line_speed = phy->req_line_speed;
9070 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9071 if (phy->req_line_speed == SPEED_10000)
9072 phy->req_line_speed = SPEED_AUTO_NEG;
9075 * This phy uses the NIG latch mechanism since link indication
9076 * arrives through its LED4 and not via its LASI signal, so we
9077 * get steady signal instead of clear on read
9079 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9080 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9082 bnx2x_cl45_write(bp, phy,
9083 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9085 bnx2x_848xx_set_led(bp, phy);
9087 /* set 1000 speed advertisement */
9088 bnx2x_cl45_read(bp, phy,
9089 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9092 bnx2x_ext_phy_set_pause(params, phy, vars);
9093 bnx2x_cl45_read(bp, phy,
9095 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9097 bnx2x_cl45_read(bp, phy,
9098 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9100 /* Disable forced speed */
9101 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9102 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9104 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9105 (phy->speed_cap_mask &
9106 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9107 (phy->req_line_speed == SPEED_1000)) {
9108 an_1000_val |= (1<<8);
9109 autoneg_val |= (1<<9 | 1<<12);
9110 if (phy->req_duplex == DUPLEX_FULL)
9111 an_1000_val |= (1<<9);
9112 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9114 an_1000_val &= ~((1<<8) | (1<<9));
9116 bnx2x_cl45_write(bp, phy,
9117 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9120 /* set 10 speed advertisement */
9121 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9122 (phy->speed_cap_mask &
9123 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9124 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
9125 an_10_100_val |= (1<<7);
9126 /* Enable autoneg and restart autoneg for legacy speeds */
9127 autoneg_val |= (1<<9 | 1<<12);
9129 if (phy->req_duplex == DUPLEX_FULL)
9130 an_10_100_val |= (1<<8);
9131 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9133 /* set 10 speed advertisement */
9134 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9135 (phy->speed_cap_mask &
9136 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9137 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
9138 an_10_100_val |= (1<<5);
9139 autoneg_val |= (1<<9 | 1<<12);
9140 if (phy->req_duplex == DUPLEX_FULL)
9141 an_10_100_val |= (1<<6);
9142 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9145 /* Only 10/100 are allowed to work in FORCE mode */
9146 if (phy->req_line_speed == SPEED_100) {
9147 autoneg_val |= (1<<13);
9148 /* Enabled AUTO-MDIX when autoneg is disabled */
9149 bnx2x_cl45_write(bp, phy,
9150 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9151 (1<<15 | 1<<9 | 7<<0));
9152 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9154 if (phy->req_line_speed == SPEED_10) {
9155 /* Enabled AUTO-MDIX when autoneg is disabled */
9156 bnx2x_cl45_write(bp, phy,
9157 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9158 (1<<15 | 1<<9 | 7<<0));
9159 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9162 bnx2x_cl45_write(bp, phy,
9163 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9166 if (phy->req_duplex == DUPLEX_FULL)
9167 autoneg_val |= (1<<8);
9169 bnx2x_cl45_write(bp, phy,
9171 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9173 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9174 (phy->speed_cap_mask &
9175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9176 (phy->req_line_speed == SPEED_10000)) {
9177 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9178 /* Restart autoneg for 10G*/
9180 bnx2x_cl45_write(bp, phy,
9181 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9183 } else if (phy->req_line_speed != SPEED_10 &&
9184 phy->req_line_speed != SPEED_100) {
9185 bnx2x_cl45_write(bp, phy,
9187 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9190 /* Save spirom version */
9191 bnx2x_save_848xx_spirom_version(phy, params);
9193 phy->req_line_speed = tmp_req_line_speed;
9198 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9199 struct link_params *params,
9200 struct link_vars *vars)
9202 struct bnx2x *bp = params->bp;
9203 /* Restore normal power mode*/
9204 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9205 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9208 bnx2x_ext_phy_hw_reset(bp, params->port);
9209 bnx2x_wait_reset_complete(bp, phy, params);
9211 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9212 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9216 #define PHY84833_HDSHK_WAIT 300
9217 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9218 struct link_params *params,
9219 struct link_vars *vars)
9224 struct bnx2x *bp = params->bp;
9228 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9229 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9230 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9231 PHY84833_CMD_OPEN_OVERRIDE);
9232 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9233 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9234 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9235 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9239 if (idx >= PHY84833_HDSHK_WAIT) {
9240 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9244 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9245 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9247 /* Issue pair swap command */
9248 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9249 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9250 PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9251 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9252 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9253 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9254 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9255 (val == PHY84833_CMD_COMPLETE_ERROR))
9259 if ((idx >= PHY84833_HDSHK_WAIT) ||
9260 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9261 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9264 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9265 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9266 PHY84833_CMD_CLEAR_COMPLETE);
9267 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9272 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9273 u32 shmem_base_path[],
9279 if (CHIP_IS_E3(bp)) {
9280 /* Assume that these will be GPIOs, not EPIOs. */
9281 for (idx = 0; idx < 2; idx++) {
9282 /* Map config param to register bit. */
9283 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9284 offsetof(struct shmem_region,
9285 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9286 reset_pin[idx] = (reset_pin[idx] &
9287 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9288 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9289 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9290 reset_pin[idx] = (1 << reset_pin[idx]);
9292 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9294 /* E2, look from diff place of shmem. */
9295 for (idx = 0; idx < 2; idx++) {
9296 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9297 offsetof(struct shmem_region,
9298 dev_info.port_hw_config[0].default_cfg));
9299 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9300 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9301 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9302 reset_pin[idx] = (1 << reset_pin[idx]);
9304 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9307 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9309 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9311 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9317 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9318 struct link_params *params,
9319 struct link_vars *vars)
9321 struct bnx2x *bp = params->bp;
9322 u8 port, initialize = 1;
9325 u32 actual_phy_selection, cms_enable;
9330 if (!(CHIP_IS_E1(bp)))
9333 port = params->port;
9335 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9336 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9337 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9340 bnx2x_cl45_write(bp, phy,
9342 MDIO_PMA_REG_CTRL, 0x8000);
9345 bnx2x_wait_reset_complete(bp, phy, params);
9346 /* Wait for GPHY to come out of reset */
9349 /* Bring PHY out of super isolate mode */
9350 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9351 bnx2x_cl45_read(bp, phy,
9353 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9354 val &= ~MDIO_84833_SUPER_ISOLATE;
9355 bnx2x_cl45_write(bp, phy,
9357 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9358 bnx2x_wait_reset_complete(bp, phy, params);
9361 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9362 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9365 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9367 temp = vars->line_speed;
9368 vars->line_speed = SPEED_10000;
9369 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
9370 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
9371 vars->line_speed = temp;
9373 /* Set dual-media configuration according to configuration */
9375 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9376 MDIO_CTL_REG_84823_MEDIA, &val);
9377 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9378 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9379 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9380 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9381 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9383 if (CHIP_IS_E3(bp)) {
9384 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9385 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9387 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9388 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9391 actual_phy_selection = bnx2x_phy_selection(params);
9393 switch (actual_phy_selection) {
9394 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9395 /* Do nothing. Essentially this is like the priority copper */
9397 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9398 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9400 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9401 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9403 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9404 /* Do nothing here. The first PHY won't be initialized at all */
9406 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9407 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9411 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9412 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9414 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9415 MDIO_CTL_REG_84823_MEDIA, val);
9416 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9417 params->multi_phy_config, val);
9420 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9422 bnx2x_save_848xx_spirom_version(phy, params);
9423 cms_enable = REG_RD(bp, params->shmem_base +
9424 offsetof(struct shmem_region,
9425 dev_info.port_hw_config[params->port].default_cfg)) &
9426 PORT_HW_CFG_ENABLE_CMS_MASK;
9428 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9429 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9431 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9433 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9434 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9435 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9441 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9442 struct link_params *params,
9443 struct link_vars *vars)
9445 struct bnx2x *bp = params->bp;
9446 u16 val, val1, val2;
9450 /* Check 10G-BaseT link status */
9451 /* Check PMD signal ok */
9452 bnx2x_cl45_read(bp, phy,
9453 MDIO_AN_DEVAD, 0xFFFA, &val1);
9454 bnx2x_cl45_read(bp, phy,
9455 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9457 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9459 /* Check link 10G */
9460 if (val2 & (1<<11)) {
9461 vars->line_speed = SPEED_10000;
9462 vars->duplex = DUPLEX_FULL;
9464 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9465 } else { /* Check Legacy speed link */
9466 u16 legacy_status, legacy_speed;
9468 /* Enable expansion register 0x42 (Operation mode status) */
9469 bnx2x_cl45_write(bp, phy,
9471 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9473 /* Get legacy speed operation status */
9474 bnx2x_cl45_read(bp, phy,
9476 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9479 DP(NETIF_MSG_LINK, "Legacy speed status"
9480 " = 0x%x\n", legacy_status);
9481 link_up = ((legacy_status & (1<<11)) == (1<<11));
9483 legacy_speed = (legacy_status & (3<<9));
9484 if (legacy_speed == (0<<9))
9485 vars->line_speed = SPEED_10;
9486 else if (legacy_speed == (1<<9))
9487 vars->line_speed = SPEED_100;
9488 else if (legacy_speed == (2<<9))
9489 vars->line_speed = SPEED_1000;
9490 else /* Should not happen */
9491 vars->line_speed = 0;
9493 if (legacy_status & (1<<8))
9494 vars->duplex = DUPLEX_FULL;
9496 vars->duplex = DUPLEX_HALF;
9498 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9499 " is_duplex_full= %d\n", vars->line_speed,
9500 (vars->duplex == DUPLEX_FULL));
9501 /* Check legacy speed AN resolution */
9502 bnx2x_cl45_read(bp, phy,
9504 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9507 vars->link_status |=
9508 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9509 bnx2x_cl45_read(bp, phy,
9511 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9513 if ((val & (1<<0)) == 0)
9514 vars->link_status |=
9515 LINK_STATUS_PARALLEL_DETECTION_USED;
9519 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9521 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9528 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9532 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9533 status = bnx2x_format_ver(spirom_ver, str, len);
9537 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9538 struct link_params *params)
9540 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9541 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9542 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9543 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9546 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9547 struct link_params *params)
9549 bnx2x_cl45_write(params->bp, phy,
9550 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9551 bnx2x_cl45_write(params->bp, phy,
9552 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9555 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9556 struct link_params *params)
9558 struct bnx2x *bp = params->bp;
9562 if (!(CHIP_IS_E1(bp)))
9565 port = params->port;
9567 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9568 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9569 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9572 bnx2x_cl45_read(bp, phy,
9575 /* Put to low power mode on newer FW */
9576 if ((val16 & 0x303f) > 0x1009)
9577 bnx2x_cl45_write(bp, phy,
9579 MDIO_PMA_REG_CTRL, 0x800);
9583 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9584 struct link_params *params, u8 mode)
9586 struct bnx2x *bp = params->bp;
9590 if (!(CHIP_IS_E1(bp)))
9593 port = params->port;
9598 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9600 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9601 SHARED_HW_CFG_LED_EXTPHY1) {
9604 bnx2x_cl45_write(bp, phy,
9606 MDIO_PMA_REG_8481_LED1_MASK,
9609 bnx2x_cl45_write(bp, phy,
9611 MDIO_PMA_REG_8481_LED2_MASK,
9614 bnx2x_cl45_write(bp, phy,
9616 MDIO_PMA_REG_8481_LED3_MASK,
9619 bnx2x_cl45_write(bp, phy,
9621 MDIO_PMA_REG_8481_LED5_MASK,
9625 bnx2x_cl45_write(bp, phy,
9627 MDIO_PMA_REG_8481_LED1_MASK,
9631 case LED_MODE_FRONT_PANEL_OFF:
9633 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9636 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9637 SHARED_HW_CFG_LED_EXTPHY1) {
9640 bnx2x_cl45_write(bp, phy,
9642 MDIO_PMA_REG_8481_LED1_MASK,
9645 bnx2x_cl45_write(bp, phy,
9647 MDIO_PMA_REG_8481_LED2_MASK,
9650 bnx2x_cl45_write(bp, phy,
9652 MDIO_PMA_REG_8481_LED3_MASK,
9655 bnx2x_cl45_write(bp, phy,
9657 MDIO_PMA_REG_8481_LED5_MASK,
9661 bnx2x_cl45_write(bp, phy,
9663 MDIO_PMA_REG_8481_LED1_MASK,
9669 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9671 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9672 SHARED_HW_CFG_LED_EXTPHY1) {
9673 /* Set control reg */
9674 bnx2x_cl45_read(bp, phy,
9676 MDIO_PMA_REG_8481_LINK_SIGNAL,
9681 bnx2x_cl45_write(bp, phy,
9683 MDIO_PMA_REG_8481_LINK_SIGNAL,
9687 bnx2x_cl45_write(bp, phy,
9689 MDIO_PMA_REG_8481_LED1_MASK,
9692 bnx2x_cl45_write(bp, phy,
9694 MDIO_PMA_REG_8481_LED2_MASK,
9697 bnx2x_cl45_write(bp, phy,
9699 MDIO_PMA_REG_8481_LED3_MASK,
9702 bnx2x_cl45_write(bp, phy,
9704 MDIO_PMA_REG_8481_LED5_MASK,
9707 bnx2x_cl45_write(bp, phy,
9709 MDIO_PMA_REG_8481_LED1_MASK,
9716 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9718 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9719 SHARED_HW_CFG_LED_EXTPHY1) {
9721 /* Set control reg */
9722 bnx2x_cl45_read(bp, phy,
9724 MDIO_PMA_REG_8481_LINK_SIGNAL,
9728 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9729 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9730 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9731 bnx2x_cl45_write(bp, phy,
9733 MDIO_PMA_REG_8481_LINK_SIGNAL,
9738 bnx2x_cl45_write(bp, phy,
9740 MDIO_PMA_REG_8481_LED1_MASK,
9743 bnx2x_cl45_write(bp, phy,
9745 MDIO_PMA_REG_8481_LED2_MASK,
9748 bnx2x_cl45_write(bp, phy,
9750 MDIO_PMA_REG_8481_LED3_MASK,
9753 bnx2x_cl45_write(bp, phy,
9755 MDIO_PMA_REG_8481_LED5_MASK,
9759 bnx2x_cl45_write(bp, phy,
9761 MDIO_PMA_REG_8481_LED1_MASK,
9764 /* Tell LED3 to blink on source */
9765 bnx2x_cl45_read(bp, phy,
9767 MDIO_PMA_REG_8481_LINK_SIGNAL,
9770 val |= (1<<6); /* A83B[8:6]= 1 */
9771 bnx2x_cl45_write(bp, phy,
9773 MDIO_PMA_REG_8481_LINK_SIGNAL,
9780 * This is a workaround for E3+84833 until autoneg
9781 * restart is fixed in f/w
9783 if (CHIP_IS_E3(bp)) {
9784 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9785 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9789 /******************************************************************/
9790 /* 54616S PHY SECTION */
9791 /******************************************************************/
9792 static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
9793 struct link_params *params,
9794 struct link_vars *vars)
9796 struct bnx2x *bp = params->bp;
9798 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9801 DP(NETIF_MSG_LINK, "54616S cfg init\n");
9802 usleep_range(1000, 1000);
9804 /* This works with E3 only, no need to check the chip
9805 before determining the port. */
9806 port = params->port;
9808 cfg_pin = (REG_RD(bp, params->shmem_base +
9809 offsetof(struct shmem_region,
9810 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9811 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9812 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9814 /* Drive pin high to bring the GPHY out of reset. */
9815 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
9817 /* wait for GPHY to reset */
9821 bnx2x_cl22_write(bp, phy,
9822 MDIO_PMA_REG_CTRL, 0x8000);
9823 bnx2x_wait_reset_complete(bp, phy, params);
9825 /*wait for GPHY to reset */
9828 /* Configure LED4: set to INTR (0x6). */
9829 /* Accessing shadow register 0xe. */
9830 bnx2x_cl22_write(bp, phy,
9831 MDIO_REG_GPHY_SHADOW,
9832 MDIO_REG_GPHY_SHADOW_LED_SEL2);
9833 bnx2x_cl22_read(bp, phy,
9834 MDIO_REG_GPHY_SHADOW,
9836 temp &= ~(0xf << 4);
9838 bnx2x_cl22_write(bp, phy,
9839 MDIO_REG_GPHY_SHADOW,
9840 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
9841 /* Configure INTR based on link status change. */
9842 bnx2x_cl22_write(bp, phy,
9844 ~MDIO_REG_INTR_MASK_LINK_STATUS);
9846 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
9847 bnx2x_cl22_write(bp, phy,
9848 MDIO_REG_GPHY_SHADOW,
9849 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
9850 bnx2x_cl22_read(bp, phy,
9851 MDIO_REG_GPHY_SHADOW,
9853 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
9854 bnx2x_cl22_write(bp, phy,
9855 MDIO_REG_GPHY_SHADOW,
9856 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
9859 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
9860 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
9862 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
9863 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
9864 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
9866 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
9867 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
9868 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
9870 /* read all advertisement */
9871 bnx2x_cl22_read(bp, phy,
9875 bnx2x_cl22_read(bp, phy,
9879 bnx2x_cl22_read(bp, phy,
9883 /* Disable forced speed */
9884 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9885 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
9888 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9889 (phy->speed_cap_mask &
9890 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9891 (phy->req_line_speed == SPEED_1000)) {
9892 an_1000_val |= (1<<8);
9893 autoneg_val |= (1<<9 | 1<<12);
9894 if (phy->req_duplex == DUPLEX_FULL)
9895 an_1000_val |= (1<<9);
9896 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9898 an_1000_val &= ~((1<<8) | (1<<9));
9900 bnx2x_cl22_write(bp, phy,
9903 bnx2x_cl22_read(bp, phy,
9907 /* set 100 speed advertisement */
9908 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9909 (phy->speed_cap_mask &
9910 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9911 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
9912 an_10_100_val |= (1<<7);
9913 /* Enable autoneg and restart autoneg for legacy speeds */
9914 autoneg_val |= (1<<9 | 1<<12);
9916 if (phy->req_duplex == DUPLEX_FULL)
9917 an_10_100_val |= (1<<8);
9918 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9921 /* set 10 speed advertisement */
9922 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9923 (phy->speed_cap_mask &
9924 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9925 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
9926 an_10_100_val |= (1<<5);
9927 autoneg_val |= (1<<9 | 1<<12);
9928 if (phy->req_duplex == DUPLEX_FULL)
9929 an_10_100_val |= (1<<6);
9930 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9933 /* Only 10/100 are allowed to work in FORCE mode */
9934 if (phy->req_line_speed == SPEED_100) {
9935 autoneg_val |= (1<<13);
9936 /* Enabled AUTO-MDIX when autoneg is disabled */
9937 bnx2x_cl22_write(bp, phy,
9939 (1<<15 | 1<<9 | 7<<0));
9940 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9942 if (phy->req_line_speed == SPEED_10) {
9943 /* Enabled AUTO-MDIX when autoneg is disabled */
9944 bnx2x_cl22_write(bp, phy,
9946 (1<<15 | 1<<9 | 7<<0));
9947 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9950 bnx2x_cl22_write(bp, phy,
9952 an_10_100_val | fc_val);
9954 if (phy->req_duplex == DUPLEX_FULL)
9955 autoneg_val |= (1<<8);
9957 bnx2x_cl22_write(bp, phy,
9958 MDIO_PMA_REG_CTRL, autoneg_val);
9963 static void bnx2x_54616s_set_link_led(struct bnx2x_phy *phy,
9964 struct link_params *params, u8 mode)
9966 struct bnx2x *bp = params->bp;
9967 DP(NETIF_MSG_LINK, "54616S set link led (mode=%x)\n", mode);
9969 case LED_MODE_FRONT_PANEL_OFF:
9979 static void bnx2x_54616s_link_reset(struct bnx2x_phy *phy,
9980 struct link_params *params)
9982 struct bnx2x *bp = params->bp;
9986 /* This works with E3 only, no need to check the chip
9987 before determining the port. */
9988 port = params->port;
9989 cfg_pin = (REG_RD(bp, params->shmem_base +
9990 offsetof(struct shmem_region,
9991 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9992 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9993 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9995 /* Drive pin low to put GPHY in reset. */
9996 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
9999 static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
10000 struct link_params *params,
10001 struct link_vars *vars)
10003 struct bnx2x *bp = params->bp;
10006 u16 legacy_status, legacy_speed;
10008 /* Get speed operation status */
10009 bnx2x_cl22_read(bp, phy,
10012 DP(NETIF_MSG_LINK, "54616S read_status: 0x%x\n", legacy_status);
10014 /* Read status to clear the PHY interrupt. */
10015 bnx2x_cl22_read(bp, phy,
10016 MDIO_REG_INTR_STATUS,
10019 link_up = ((legacy_status & (1<<2)) == (1<<2));
10022 legacy_speed = (legacy_status & (7<<8));
10023 if (legacy_speed == (7<<8)) {
10024 vars->line_speed = SPEED_1000;
10025 vars->duplex = DUPLEX_FULL;
10026 } else if (legacy_speed == (6<<8)) {
10027 vars->line_speed = SPEED_1000;
10028 vars->duplex = DUPLEX_HALF;
10029 } else if (legacy_speed == (5<<8)) {
10030 vars->line_speed = SPEED_100;
10031 vars->duplex = DUPLEX_FULL;
10033 /* Omitting 100Base-T4 for now */
10034 else if (legacy_speed == (3<<8)) {
10035 vars->line_speed = SPEED_100;
10036 vars->duplex = DUPLEX_HALF;
10037 } else if (legacy_speed == (2<<8)) {
10038 vars->line_speed = SPEED_10;
10039 vars->duplex = DUPLEX_FULL;
10040 } else if (legacy_speed == (1<<8)) {
10041 vars->line_speed = SPEED_10;
10042 vars->duplex = DUPLEX_HALF;
10043 } else /* Should not happen */
10044 vars->line_speed = 0;
10046 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10047 " is_duplex_full= %d\n", vars->line_speed,
10048 (vars->duplex == DUPLEX_FULL));
10050 /* Check legacy speed AN resolution */
10051 bnx2x_cl22_read(bp, phy,
10055 vars->link_status |=
10056 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10057 bnx2x_cl22_read(bp, phy,
10060 if ((val & (1<<0)) == 0)
10061 vars->link_status |=
10062 LINK_STATUS_PARALLEL_DETECTION_USED;
10064 DP(NETIF_MSG_LINK, "BCM54616S: link speed is %d\n",
10066 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10071 static void bnx2x_54616s_config_loopback(struct bnx2x_phy *phy,
10072 struct link_params *params)
10074 struct bnx2x *bp = params->bp;
10076 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10078 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54616s\n");
10080 /* Enable master/slave manual mmode and set to master */
10081 /* mii write 9 [bits set 11 12] */
10082 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10084 /* forced 1G and disable autoneg */
10085 /* set val [mii read 0] */
10086 /* set val [expr $val & [bits clear 6 12 13]] */
10087 /* set val [expr $val | [bits set 6 8]] */
10088 /* mii write 0 $val */
10089 bnx2x_cl22_read(bp, phy, 0x00, &val);
10090 val &= ~((1<<6) | (1<<12) | (1<<13));
10091 val |= (1<<6) | (1<<8);
10092 bnx2x_cl22_write(bp, phy, 0x00, val);
10094 /* Set external loopback and Tx using 6dB coding */
10095 /* mii write 0x18 7 */
10096 /* set val [mii read 0x18] */
10097 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10098 bnx2x_cl22_write(bp, phy, 0x18, 7);
10099 bnx2x_cl22_read(bp, phy, 0x18, &val);
10100 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10102 /* This register opens the gate for the UMAC despite its name */
10103 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10106 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10107 * length used by the MAC receive logic to check frames.
10109 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10112 /******************************************************************/
10113 /* SFX7101 PHY SECTION */
10114 /******************************************************************/
10115 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10116 struct link_params *params)
10118 struct bnx2x *bp = params->bp;
10119 /* SFX7101_XGXS_TEST1 */
10120 bnx2x_cl45_write(bp, phy,
10121 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10124 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10125 struct link_params *params,
10126 struct link_vars *vars)
10128 u16 fw_ver1, fw_ver2, val;
10129 struct bnx2x *bp = params->bp;
10130 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10132 /* Restore normal power mode*/
10133 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10134 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10136 bnx2x_ext_phy_hw_reset(bp, params->port);
10137 bnx2x_wait_reset_complete(bp, phy, params);
10139 bnx2x_cl45_write(bp, phy,
10140 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
10141 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10142 bnx2x_cl45_write(bp, phy,
10143 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10145 bnx2x_ext_phy_set_pause(params, phy, vars);
10146 /* Restart autoneg */
10147 bnx2x_cl45_read(bp, phy,
10148 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10150 bnx2x_cl45_write(bp, phy,
10151 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10153 /* Save spirom version */
10154 bnx2x_cl45_read(bp, phy,
10155 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10157 bnx2x_cl45_read(bp, phy,
10158 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10159 bnx2x_save_spirom_version(bp, params->port,
10160 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10164 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10165 struct link_params *params,
10166 struct link_vars *vars)
10168 struct bnx2x *bp = params->bp;
10171 bnx2x_cl45_read(bp, phy,
10172 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
10173 bnx2x_cl45_read(bp, phy,
10174 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
10175 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10177 bnx2x_cl45_read(bp, phy,
10178 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10179 bnx2x_cl45_read(bp, phy,
10180 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10181 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10183 link_up = ((val1 & 4) == 4);
10184 /* if link is up print the AN outcome of the SFX7101 PHY */
10186 bnx2x_cl45_read(bp, phy,
10187 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10189 vars->line_speed = SPEED_10000;
10190 vars->duplex = DUPLEX_FULL;
10191 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10192 val2, (val2 & (1<<14)));
10193 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10194 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10199 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10203 str[0] = (spirom_ver & 0xFF);
10204 str[1] = (spirom_ver & 0xFF00) >> 8;
10205 str[2] = (spirom_ver & 0xFF0000) >> 16;
10206 str[3] = (spirom_ver & 0xFF000000) >> 24;
10212 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10216 bnx2x_cl45_read(bp, phy,
10218 MDIO_PMA_REG_7101_RESET, &val);
10220 for (cnt = 0; cnt < 10; cnt++) {
10222 /* Writes a self-clearing reset */
10223 bnx2x_cl45_write(bp, phy,
10225 MDIO_PMA_REG_7101_RESET,
10227 /* Wait for clear */
10228 bnx2x_cl45_read(bp, phy,
10230 MDIO_PMA_REG_7101_RESET, &val);
10232 if ((val & (1<<15)) == 0)
10237 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10238 struct link_params *params) {
10239 /* Low power mode is controlled by GPIO 2 */
10240 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10241 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10242 /* The PHY reset is controlled by GPIO 1 */
10243 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10244 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10247 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10248 struct link_params *params, u8 mode)
10251 struct bnx2x *bp = params->bp;
10253 case LED_MODE_FRONT_PANEL_OFF:
10260 case LED_MODE_OPER:
10264 bnx2x_cl45_write(bp, phy,
10266 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10270 /******************************************************************/
10271 /* STATIC PHY DECLARATION */
10272 /******************************************************************/
10274 static struct bnx2x_phy phy_null = {
10275 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10278 .flags = FLAGS_INIT_XGXS_FIRST,
10279 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10280 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10283 .media_type = ETH_PHY_NOT_PRESENT,
10285 .req_flow_ctrl = 0,
10286 .req_line_speed = 0,
10287 .speed_cap_mask = 0,
10290 .config_init = (config_init_t)NULL,
10291 .read_status = (read_status_t)NULL,
10292 .link_reset = (link_reset_t)NULL,
10293 .config_loopback = (config_loopback_t)NULL,
10294 .format_fw_ver = (format_fw_ver_t)NULL,
10295 .hw_reset = (hw_reset_t)NULL,
10296 .set_link_led = (set_link_led_t)NULL,
10297 .phy_specific_func = (phy_specific_func_t)NULL
10300 static struct bnx2x_phy phy_serdes = {
10301 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10305 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10306 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10308 .supported = (SUPPORTED_10baseT_Half |
10309 SUPPORTED_10baseT_Full |
10310 SUPPORTED_100baseT_Half |
10311 SUPPORTED_100baseT_Full |
10312 SUPPORTED_1000baseT_Full |
10313 SUPPORTED_2500baseX_Full |
10315 SUPPORTED_Autoneg |
10317 SUPPORTED_Asym_Pause),
10318 .media_type = ETH_PHY_BASE_T,
10320 .req_flow_ctrl = 0,
10321 .req_line_speed = 0,
10322 .speed_cap_mask = 0,
10325 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10326 .read_status = (read_status_t)bnx2x_link_settings_status,
10327 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10328 .config_loopback = (config_loopback_t)NULL,
10329 .format_fw_ver = (format_fw_ver_t)NULL,
10330 .hw_reset = (hw_reset_t)NULL,
10331 .set_link_led = (set_link_led_t)NULL,
10332 .phy_specific_func = (phy_specific_func_t)NULL
10335 static struct bnx2x_phy phy_xgxs = {
10336 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10340 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10341 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10343 .supported = (SUPPORTED_10baseT_Half |
10344 SUPPORTED_10baseT_Full |
10345 SUPPORTED_100baseT_Half |
10346 SUPPORTED_100baseT_Full |
10347 SUPPORTED_1000baseT_Full |
10348 SUPPORTED_2500baseX_Full |
10349 SUPPORTED_10000baseT_Full |
10351 SUPPORTED_Autoneg |
10353 SUPPORTED_Asym_Pause),
10354 .media_type = ETH_PHY_CX4,
10356 .req_flow_ctrl = 0,
10357 .req_line_speed = 0,
10358 .speed_cap_mask = 0,
10361 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10362 .read_status = (read_status_t)bnx2x_link_settings_status,
10363 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10364 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10365 .format_fw_ver = (format_fw_ver_t)NULL,
10366 .hw_reset = (hw_reset_t)NULL,
10367 .set_link_led = (set_link_led_t)NULL,
10368 .phy_specific_func = (phy_specific_func_t)NULL
10370 static struct bnx2x_phy phy_warpcore = {
10371 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10374 .flags = FLAGS_HW_LOCK_REQUIRED,
10375 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10376 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10378 .supported = (SUPPORTED_10baseT_Half |
10379 SUPPORTED_10baseT_Full |
10380 SUPPORTED_100baseT_Half |
10381 SUPPORTED_100baseT_Full |
10382 SUPPORTED_1000baseT_Full |
10383 SUPPORTED_10000baseT_Full |
10384 SUPPORTED_20000baseKR2_Full |
10385 SUPPORTED_20000baseMLD2_Full |
10387 SUPPORTED_Autoneg |
10389 SUPPORTED_Asym_Pause),
10390 .media_type = ETH_PHY_UNSPECIFIED,
10392 .req_flow_ctrl = 0,
10393 .req_line_speed = 0,
10394 .speed_cap_mask = 0,
10395 /* req_duplex = */0,
10397 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10398 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10399 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10400 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10401 .format_fw_ver = (format_fw_ver_t)NULL,
10402 .hw_reset = (hw_reset_t)NULL,
10403 .set_link_led = (set_link_led_t)NULL,
10404 .phy_specific_func = (phy_specific_func_t)NULL
10408 static struct bnx2x_phy phy_7101 = {
10409 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10412 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10413 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10414 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10416 .supported = (SUPPORTED_10000baseT_Full |
10418 SUPPORTED_Autoneg |
10420 SUPPORTED_Asym_Pause),
10421 .media_type = ETH_PHY_BASE_T,
10423 .req_flow_ctrl = 0,
10424 .req_line_speed = 0,
10425 .speed_cap_mask = 0,
10428 .config_init = (config_init_t)bnx2x_7101_config_init,
10429 .read_status = (read_status_t)bnx2x_7101_read_status,
10430 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10431 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10432 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10433 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10434 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10435 .phy_specific_func = (phy_specific_func_t)NULL
10437 static struct bnx2x_phy phy_8073 = {
10438 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10441 .flags = FLAGS_HW_LOCK_REQUIRED,
10442 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10443 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10445 .supported = (SUPPORTED_10000baseT_Full |
10446 SUPPORTED_2500baseX_Full |
10447 SUPPORTED_1000baseT_Full |
10449 SUPPORTED_Autoneg |
10451 SUPPORTED_Asym_Pause),
10452 .media_type = ETH_PHY_KR,
10454 .req_flow_ctrl = 0,
10455 .req_line_speed = 0,
10456 .speed_cap_mask = 0,
10459 .config_init = (config_init_t)bnx2x_8073_config_init,
10460 .read_status = (read_status_t)bnx2x_8073_read_status,
10461 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10462 .config_loopback = (config_loopback_t)NULL,
10463 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10464 .hw_reset = (hw_reset_t)NULL,
10465 .set_link_led = (set_link_led_t)NULL,
10466 .phy_specific_func = (phy_specific_func_t)NULL
10468 static struct bnx2x_phy phy_8705 = {
10469 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10472 .flags = FLAGS_INIT_XGXS_FIRST,
10473 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10474 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10476 .supported = (SUPPORTED_10000baseT_Full |
10479 SUPPORTED_Asym_Pause),
10480 .media_type = ETH_PHY_XFP_FIBER,
10482 .req_flow_ctrl = 0,
10483 .req_line_speed = 0,
10484 .speed_cap_mask = 0,
10487 .config_init = (config_init_t)bnx2x_8705_config_init,
10488 .read_status = (read_status_t)bnx2x_8705_read_status,
10489 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10490 .config_loopback = (config_loopback_t)NULL,
10491 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10492 .hw_reset = (hw_reset_t)NULL,
10493 .set_link_led = (set_link_led_t)NULL,
10494 .phy_specific_func = (phy_specific_func_t)NULL
10496 static struct bnx2x_phy phy_8706 = {
10497 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10500 .flags = FLAGS_INIT_XGXS_FIRST,
10501 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10502 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10504 .supported = (SUPPORTED_10000baseT_Full |
10505 SUPPORTED_1000baseT_Full |
10508 SUPPORTED_Asym_Pause),
10509 .media_type = ETH_PHY_SFP_FIBER,
10511 .req_flow_ctrl = 0,
10512 .req_line_speed = 0,
10513 .speed_cap_mask = 0,
10516 .config_init = (config_init_t)bnx2x_8706_config_init,
10517 .read_status = (read_status_t)bnx2x_8706_read_status,
10518 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10519 .config_loopback = (config_loopback_t)NULL,
10520 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10521 .hw_reset = (hw_reset_t)NULL,
10522 .set_link_led = (set_link_led_t)NULL,
10523 .phy_specific_func = (phy_specific_func_t)NULL
10526 static struct bnx2x_phy phy_8726 = {
10527 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10530 .flags = (FLAGS_HW_LOCK_REQUIRED |
10531 FLAGS_INIT_XGXS_FIRST),
10532 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10533 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10535 .supported = (SUPPORTED_10000baseT_Full |
10536 SUPPORTED_1000baseT_Full |
10537 SUPPORTED_Autoneg |
10540 SUPPORTED_Asym_Pause),
10541 .media_type = ETH_PHY_NOT_PRESENT,
10543 .req_flow_ctrl = 0,
10544 .req_line_speed = 0,
10545 .speed_cap_mask = 0,
10548 .config_init = (config_init_t)bnx2x_8726_config_init,
10549 .read_status = (read_status_t)bnx2x_8726_read_status,
10550 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
10551 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10552 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10553 .hw_reset = (hw_reset_t)NULL,
10554 .set_link_led = (set_link_led_t)NULL,
10555 .phy_specific_func = (phy_specific_func_t)NULL
10558 static struct bnx2x_phy phy_8727 = {
10559 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10562 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10563 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10564 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10566 .supported = (SUPPORTED_10000baseT_Full |
10567 SUPPORTED_1000baseT_Full |
10570 SUPPORTED_Asym_Pause),
10571 .media_type = ETH_PHY_NOT_PRESENT,
10573 .req_flow_ctrl = 0,
10574 .req_line_speed = 0,
10575 .speed_cap_mask = 0,
10578 .config_init = (config_init_t)bnx2x_8727_config_init,
10579 .read_status = (read_status_t)bnx2x_8727_read_status,
10580 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
10581 .config_loopback = (config_loopback_t)NULL,
10582 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10583 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
10584 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
10585 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10587 static struct bnx2x_phy phy_8481 = {
10588 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10591 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10592 FLAGS_REARM_LATCH_SIGNAL,
10593 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10594 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10596 .supported = (SUPPORTED_10baseT_Half |
10597 SUPPORTED_10baseT_Full |
10598 SUPPORTED_100baseT_Half |
10599 SUPPORTED_100baseT_Full |
10600 SUPPORTED_1000baseT_Full |
10601 SUPPORTED_10000baseT_Full |
10603 SUPPORTED_Autoneg |
10605 SUPPORTED_Asym_Pause),
10606 .media_type = ETH_PHY_BASE_T,
10608 .req_flow_ctrl = 0,
10609 .req_line_speed = 0,
10610 .speed_cap_mask = 0,
10613 .config_init = (config_init_t)bnx2x_8481_config_init,
10614 .read_status = (read_status_t)bnx2x_848xx_read_status,
10615 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
10616 .config_loopback = (config_loopback_t)NULL,
10617 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10618 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
10619 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10620 .phy_specific_func = (phy_specific_func_t)NULL
10623 static struct bnx2x_phy phy_84823 = {
10624 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10627 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10628 FLAGS_REARM_LATCH_SIGNAL,
10629 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10630 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10632 .supported = (SUPPORTED_10baseT_Half |
10633 SUPPORTED_10baseT_Full |
10634 SUPPORTED_100baseT_Half |
10635 SUPPORTED_100baseT_Full |
10636 SUPPORTED_1000baseT_Full |
10637 SUPPORTED_10000baseT_Full |
10639 SUPPORTED_Autoneg |
10641 SUPPORTED_Asym_Pause),
10642 .media_type = ETH_PHY_BASE_T,
10644 .req_flow_ctrl = 0,
10645 .req_line_speed = 0,
10646 .speed_cap_mask = 0,
10649 .config_init = (config_init_t)bnx2x_848x3_config_init,
10650 .read_status = (read_status_t)bnx2x_848xx_read_status,
10651 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10652 .config_loopback = (config_loopback_t)NULL,
10653 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10654 .hw_reset = (hw_reset_t)NULL,
10655 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10656 .phy_specific_func = (phy_specific_func_t)NULL
10659 static struct bnx2x_phy phy_84833 = {
10660 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10663 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10664 FLAGS_REARM_LATCH_SIGNAL,
10665 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10666 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10668 .supported = (SUPPORTED_10baseT_Half |
10669 SUPPORTED_10baseT_Full |
10670 SUPPORTED_100baseT_Half |
10671 SUPPORTED_100baseT_Full |
10672 SUPPORTED_1000baseT_Full |
10673 SUPPORTED_10000baseT_Full |
10675 SUPPORTED_Autoneg |
10677 SUPPORTED_Asym_Pause),
10678 .media_type = ETH_PHY_BASE_T,
10680 .req_flow_ctrl = 0,
10681 .req_line_speed = 0,
10682 .speed_cap_mask = 0,
10685 .config_init = (config_init_t)bnx2x_848x3_config_init,
10686 .read_status = (read_status_t)bnx2x_848xx_read_status,
10687 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10688 .config_loopback = (config_loopback_t)NULL,
10689 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10690 .hw_reset = (hw_reset_t)NULL,
10691 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10692 .phy_specific_func = (phy_specific_func_t)NULL
10695 static struct bnx2x_phy phy_54616s = {
10696 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616,
10699 .flags = FLAGS_INIT_XGXS_FIRST,
10700 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10701 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10703 .supported = (SUPPORTED_10baseT_Half |
10704 SUPPORTED_10baseT_Full |
10705 SUPPORTED_100baseT_Half |
10706 SUPPORTED_100baseT_Full |
10707 SUPPORTED_1000baseT_Full |
10709 SUPPORTED_Autoneg |
10711 SUPPORTED_Asym_Pause),
10712 .media_type = ETH_PHY_BASE_T,
10714 .req_flow_ctrl = 0,
10715 .req_line_speed = 0,
10716 .speed_cap_mask = 0,
10717 /* req_duplex = */0,
10719 .config_init = (config_init_t)bnx2x_54616s_config_init,
10720 .read_status = (read_status_t)bnx2x_54616s_read_status,
10721 .link_reset = (link_reset_t)bnx2x_54616s_link_reset,
10722 .config_loopback = (config_loopback_t)bnx2x_54616s_config_loopback,
10723 .format_fw_ver = (format_fw_ver_t)NULL,
10724 .hw_reset = (hw_reset_t)NULL,
10725 .set_link_led = (set_link_led_t)bnx2x_54616s_set_link_led,
10726 .phy_specific_func = (phy_specific_func_t)NULL
10728 /*****************************************************************/
10730 /* Populate the phy according. Main function: bnx2x_populate_phy */
10732 /*****************************************************************/
10734 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10735 struct bnx2x_phy *phy, u8 port,
10738 /* Get the 4 lanes xgxs config rx and tx */
10739 u32 rx = 0, tx = 0, i;
10740 for (i = 0; i < 2; i++) {
10742 * INT_PHY and EXT_PHY1 share the same value location in the
10743 * shmem. When num_phys is greater than 1, than this value
10744 * applies only to EXT_PHY1
10746 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10747 rx = REG_RD(bp, shmem_base +
10748 offsetof(struct shmem_region,
10749 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10751 tx = REG_RD(bp, shmem_base +
10752 offsetof(struct shmem_region,
10753 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10755 rx = REG_RD(bp, shmem_base +
10756 offsetof(struct shmem_region,
10757 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10759 tx = REG_RD(bp, shmem_base +
10760 offsetof(struct shmem_region,
10761 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10764 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
10765 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
10767 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
10768 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
10772 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
10773 u8 phy_index, u8 port)
10775 u32 ext_phy_config = 0;
10776 switch (phy_index) {
10778 ext_phy_config = REG_RD(bp, shmem_base +
10779 offsetof(struct shmem_region,
10780 dev_info.port_hw_config[port].external_phy_config));
10783 ext_phy_config = REG_RD(bp, shmem_base +
10784 offsetof(struct shmem_region,
10785 dev_info.port_hw_config[port].external_phy_config2));
10788 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
10792 return ext_phy_config;
10794 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
10795 struct bnx2x_phy *phy)
10799 u32 switch_cfg = (REG_RD(bp, shmem_base +
10800 offsetof(struct shmem_region,
10801 dev_info.port_feature_config[port].link_config)) &
10802 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10803 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
10804 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
10805 if (USES_WARPCORE(bp)) {
10807 phy_addr = REG_RD(bp,
10808 MISC_REG_WC0_CTRL_PHY_ADDR);
10809 *phy = phy_warpcore;
10810 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
10811 phy->flags |= FLAGS_4_PORT_MODE;
10813 phy->flags &= ~FLAGS_4_PORT_MODE;
10814 /* Check Dual mode */
10815 serdes_net_if = (REG_RD(bp, shmem_base +
10816 offsetof(struct shmem_region, dev_info.
10817 port_hw_config[port].default_cfg)) &
10818 PORT_HW_CFG_NET_SERDES_IF_MASK);
10820 * Set the appropriate supported and flags indications per
10821 * interface type of the chip
10823 switch (serdes_net_if) {
10824 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
10825 phy->supported &= (SUPPORTED_10baseT_Half |
10826 SUPPORTED_10baseT_Full |
10827 SUPPORTED_100baseT_Half |
10828 SUPPORTED_100baseT_Full |
10829 SUPPORTED_1000baseT_Full |
10831 SUPPORTED_Autoneg |
10833 SUPPORTED_Asym_Pause);
10834 phy->media_type = ETH_PHY_BASE_T;
10836 case PORT_HW_CFG_NET_SERDES_IF_XFI:
10837 phy->media_type = ETH_PHY_XFP_FIBER;
10839 case PORT_HW_CFG_NET_SERDES_IF_SFI:
10840 phy->supported &= (SUPPORTED_1000baseT_Full |
10841 SUPPORTED_10000baseT_Full |
10844 SUPPORTED_Asym_Pause);
10845 phy->media_type = ETH_PHY_SFP_FIBER;
10847 case PORT_HW_CFG_NET_SERDES_IF_KR:
10848 phy->media_type = ETH_PHY_KR;
10849 phy->supported &= (SUPPORTED_1000baseT_Full |
10850 SUPPORTED_10000baseT_Full |
10852 SUPPORTED_Autoneg |
10854 SUPPORTED_Asym_Pause);
10856 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
10857 phy->media_type = ETH_PHY_KR;
10858 phy->flags |= FLAGS_WC_DUAL_MODE;
10859 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
10862 SUPPORTED_Asym_Pause);
10864 case PORT_HW_CFG_NET_SERDES_IF_KR2:
10865 phy->media_type = ETH_PHY_KR;
10866 phy->flags |= FLAGS_WC_DUAL_MODE;
10867 phy->supported &= (SUPPORTED_20000baseKR2_Full |
10870 SUPPORTED_Asym_Pause);
10873 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
10879 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
10880 * was not set as expected. For B0, ECO will be enabled so there
10881 * won't be an issue there
10883 if (CHIP_REV(bp) == CHIP_REV_Ax)
10884 phy->flags |= FLAGS_MDC_MDIO_WA;
10886 switch (switch_cfg) {
10887 case SWITCH_CFG_1G:
10888 phy_addr = REG_RD(bp,
10889 NIG_REG_SERDES0_CTRL_PHY_ADDR +
10893 case SWITCH_CFG_10G:
10894 phy_addr = REG_RD(bp,
10895 NIG_REG_XGXS0_CTRL_PHY_ADDR +
10900 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
10904 phy->addr = (u8)phy_addr;
10905 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
10906 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
10908 if (CHIP_IS_E2(bp))
10909 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
10911 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
10913 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
10914 port, phy->addr, phy->mdio_ctrl);
10916 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
10920 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
10925 struct bnx2x_phy *phy)
10927 u32 ext_phy_config, phy_type, config2;
10928 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
10929 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
10931 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10932 /* Select the phy type */
10933 switch (phy_type) {
10934 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
10935 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
10938 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
10941 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
10944 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
10945 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10948 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
10949 /* BCM8727_NOC => BCM8727 no over current */
10950 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10952 phy->flags |= FLAGS_NOC;
10954 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
10955 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
10956 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
10962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
10965 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
10968 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
10971 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
10974 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
10982 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
10983 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
10986 * The shmem address of the phy version is located on different
10987 * structures. In case this structure is too old, do not set
10990 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
10991 dev_info.shared_hw_config.config2));
10992 if (phy_index == EXT_PHY1) {
10993 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
10994 port_mb[port].ext_phy_fw_version);
10996 /* Check specific mdc mdio settings */
10997 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
10998 mdc_mdio_access = config2 &
10999 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11001 u32 size = REG_RD(bp, shmem2_base);
11004 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11005 phy->ver_addr = shmem2_base +
11006 offsetof(struct shmem2_region,
11007 ext_phy_fw_version2[port]);
11009 /* Check specific mdc mdio settings */
11010 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11011 mdc_mdio_access = (config2 &
11012 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11013 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11014 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11016 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11019 * In case mdc/mdio_access of the external phy is different than the
11020 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11021 * to prevent one port interfere with another port's CL45 operations.
11023 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11024 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11025 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11026 phy_type, port, phy_index);
11027 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11028 phy->addr, phy->mdio_ctrl);
11032 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11033 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11036 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11037 if (phy_index == INT_PHY)
11038 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11039 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11044 static void bnx2x_phy_def_cfg(struct link_params *params,
11045 struct bnx2x_phy *phy,
11048 struct bnx2x *bp = params->bp;
11050 /* Populate the default phy configuration for MF mode */
11051 if (phy_index == EXT_PHY2) {
11052 link_config = REG_RD(bp, params->shmem_base +
11053 offsetof(struct shmem_region, dev_info.
11054 port_feature_config[params->port].link_config2));
11055 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11056 offsetof(struct shmem_region,
11058 port_hw_config[params->port].speed_capability_mask2));
11060 link_config = REG_RD(bp, params->shmem_base +
11061 offsetof(struct shmem_region, dev_info.
11062 port_feature_config[params->port].link_config));
11063 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11064 offsetof(struct shmem_region,
11066 port_hw_config[params->port].speed_capability_mask));
11068 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11069 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11071 phy->req_duplex = DUPLEX_FULL;
11072 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11073 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11074 phy->req_duplex = DUPLEX_HALF;
11075 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11076 phy->req_line_speed = SPEED_10;
11078 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11079 phy->req_duplex = DUPLEX_HALF;
11080 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11081 phy->req_line_speed = SPEED_100;
11083 case PORT_FEATURE_LINK_SPEED_1G:
11084 phy->req_line_speed = SPEED_1000;
11086 case PORT_FEATURE_LINK_SPEED_2_5G:
11087 phy->req_line_speed = SPEED_2500;
11089 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11090 phy->req_line_speed = SPEED_10000;
11093 phy->req_line_speed = SPEED_AUTO_NEG;
11097 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11098 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11099 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11101 case PORT_FEATURE_FLOW_CONTROL_TX:
11102 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11104 case PORT_FEATURE_FLOW_CONTROL_RX:
11105 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11107 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11108 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11111 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11116 u32 bnx2x_phy_selection(struct link_params *params)
11118 u32 phy_config_swapped, prio_cfg;
11119 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11121 phy_config_swapped = params->multi_phy_config &
11122 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11124 prio_cfg = params->multi_phy_config &
11125 PORT_HW_CFG_PHY_SELECTION_MASK;
11127 if (phy_config_swapped) {
11128 switch (prio_cfg) {
11129 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11130 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11132 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11133 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11135 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11136 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11138 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11139 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11143 return_cfg = prio_cfg;
11149 int bnx2x_phy_probe(struct link_params *params)
11151 u8 phy_index, actual_phy_idx, link_cfg_idx;
11152 u32 phy_config_swapped, sync_offset, media_types;
11153 struct bnx2x *bp = params->bp;
11154 struct bnx2x_phy *phy;
11155 params->num_phys = 0;
11156 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11157 phy_config_swapped = params->multi_phy_config &
11158 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11160 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11162 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11163 actual_phy_idx = phy_index;
11164 if (phy_config_swapped) {
11165 if (phy_index == EXT_PHY1)
11166 actual_phy_idx = EXT_PHY2;
11167 else if (phy_index == EXT_PHY2)
11168 actual_phy_idx = EXT_PHY1;
11170 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11171 " actual_phy_idx %x\n", phy_config_swapped,
11172 phy_index, actual_phy_idx);
11173 phy = ¶ms->phy[actual_phy_idx];
11174 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11175 params->shmem2_base, params->port,
11177 params->num_phys = 0;
11178 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11180 for (phy_index = INT_PHY;
11181 phy_index < MAX_PHYS;
11186 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11189 sync_offset = params->shmem_base +
11190 offsetof(struct shmem_region,
11191 dev_info.port_hw_config[params->port].media_type);
11192 media_types = REG_RD(bp, sync_offset);
11195 * Update media type for non-PMF sync only for the first time
11196 * In case the media type changes afterwards, it will be updated
11197 * using the update_status function
11199 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11200 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11201 actual_phy_idx))) == 0) {
11202 media_types |= ((phy->media_type &
11203 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11204 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11207 REG_WR(bp, sync_offset, media_types);
11209 bnx2x_phy_def_cfg(params, phy, phy_index);
11210 params->num_phys++;
11213 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11217 void bnx2x_init_bmac_loopback(struct link_params *params,
11218 struct link_vars *vars)
11220 struct bnx2x *bp = params->bp;
11222 vars->line_speed = SPEED_10000;
11223 vars->duplex = DUPLEX_FULL;
11224 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11225 vars->mac_type = MAC_TYPE_BMAC;
11227 vars->phy_flags = PHY_XGXS_FLAG;
11229 bnx2x_xgxs_deassert(params);
11231 /* set bmac loopback */
11232 bnx2x_bmac_enable(params, vars, 1);
11234 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11237 void bnx2x_init_emac_loopback(struct link_params *params,
11238 struct link_vars *vars)
11240 struct bnx2x *bp = params->bp;
11242 vars->line_speed = SPEED_1000;
11243 vars->duplex = DUPLEX_FULL;
11244 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11245 vars->mac_type = MAC_TYPE_EMAC;
11247 vars->phy_flags = PHY_XGXS_FLAG;
11249 bnx2x_xgxs_deassert(params);
11250 /* set bmac loopback */
11251 bnx2x_emac_enable(params, vars, 1);
11252 bnx2x_emac_program(params, vars);
11253 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11256 void bnx2x_init_xmac_loopback(struct link_params *params,
11257 struct link_vars *vars)
11259 struct bnx2x *bp = params->bp;
11261 if (!params->req_line_speed[0])
11262 vars->line_speed = SPEED_10000;
11264 vars->line_speed = params->req_line_speed[0];
11265 vars->duplex = DUPLEX_FULL;
11266 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11267 vars->mac_type = MAC_TYPE_XMAC;
11268 vars->phy_flags = PHY_XGXS_FLAG;
11270 * Set WC to loopback mode since link is required to provide clock
11271 * to the XMAC in 20G mode
11273 if (vars->line_speed == SPEED_20000) {
11274 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
11275 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
11276 params->phy[INT_PHY].config_loopback(
11277 ¶ms->phy[INT_PHY],
11280 bnx2x_xmac_enable(params, vars, 1);
11281 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11284 void bnx2x_init_umac_loopback(struct link_params *params,
11285 struct link_vars *vars)
11287 struct bnx2x *bp = params->bp;
11289 vars->line_speed = SPEED_1000;
11290 vars->duplex = DUPLEX_FULL;
11291 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11292 vars->mac_type = MAC_TYPE_UMAC;
11293 vars->phy_flags = PHY_XGXS_FLAG;
11294 bnx2x_umac_enable(params, vars, 1);
11296 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11299 void bnx2x_init_xgxs_loopback(struct link_params *params,
11300 struct link_vars *vars)
11302 struct bnx2x *bp = params->bp;
11304 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11305 vars->duplex = DUPLEX_FULL;
11306 if (params->req_line_speed[0] == SPEED_1000)
11307 vars->line_speed = SPEED_1000;
11309 vars->line_speed = SPEED_10000;
11311 if (!USES_WARPCORE(bp))
11312 bnx2x_xgxs_deassert(params);
11313 bnx2x_link_initialize(params, vars);
11315 if (params->req_line_speed[0] == SPEED_1000) {
11316 if (USES_WARPCORE(bp))
11317 bnx2x_umac_enable(params, vars, 0);
11319 bnx2x_emac_program(params, vars);
11320 bnx2x_emac_enable(params, vars, 0);
11323 if (USES_WARPCORE(bp))
11324 bnx2x_xmac_enable(params, vars, 0);
11326 bnx2x_bmac_enable(params, vars, 0);
11329 if (params->loopback_mode == LOOPBACK_XGXS) {
11330 /* set 10G XGXS loopback */
11331 params->phy[INT_PHY].config_loopback(
11332 ¶ms->phy[INT_PHY],
11336 /* set external phy loopback */
11338 for (phy_index = EXT_PHY1;
11339 phy_index < params->num_phys; phy_index++) {
11340 if (params->phy[phy_index].config_loopback)
11341 params->phy[phy_index].config_loopback(
11342 ¶ms->phy[phy_index],
11346 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11348 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11351 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11353 struct bnx2x *bp = params->bp;
11354 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11355 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11356 params->req_line_speed[0], params->req_flow_ctrl[0]);
11357 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11358 params->req_line_speed[1], params->req_flow_ctrl[1]);
11359 vars->link_status = 0;
11360 vars->phy_link_up = 0;
11362 vars->line_speed = 0;
11363 vars->duplex = DUPLEX_FULL;
11364 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11365 vars->mac_type = MAC_TYPE_NONE;
11366 vars->phy_flags = 0;
11368 /* disable attentions */
11369 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11370 (NIG_MASK_XGXS0_LINK_STATUS |
11371 NIG_MASK_XGXS0_LINK10G |
11372 NIG_MASK_SERDES0_LINK_STATUS |
11375 bnx2x_emac_init(params, vars);
11377 if (params->num_phys == 0) {
11378 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11381 set_phy_vars(params, vars);
11383 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11384 switch (params->loopback_mode) {
11385 case LOOPBACK_BMAC:
11386 bnx2x_init_bmac_loopback(params, vars);
11388 case LOOPBACK_EMAC:
11389 bnx2x_init_emac_loopback(params, vars);
11391 case LOOPBACK_XMAC:
11392 bnx2x_init_xmac_loopback(params, vars);
11394 case LOOPBACK_UMAC:
11395 bnx2x_init_umac_loopback(params, vars);
11397 case LOOPBACK_XGXS:
11398 case LOOPBACK_EXT_PHY:
11399 bnx2x_init_xgxs_loopback(params, vars);
11402 if (!CHIP_IS_E3(bp)) {
11403 if (params->switch_cfg == SWITCH_CFG_10G)
11404 bnx2x_xgxs_deassert(params);
11406 bnx2x_serdes_deassert(bp, params->port);
11408 bnx2x_link_initialize(params, vars);
11410 bnx2x_link_int_enable(params);
11416 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11419 struct bnx2x *bp = params->bp;
11420 u8 phy_index, port = params->port, clear_latch_ind = 0;
11421 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11422 /* disable attentions */
11423 vars->link_status = 0;
11424 bnx2x_update_mng(params, vars->link_status);
11425 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11426 (NIG_MASK_XGXS0_LINK_STATUS |
11427 NIG_MASK_XGXS0_LINK10G |
11428 NIG_MASK_SERDES0_LINK_STATUS |
11431 /* activate nig drain */
11432 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11434 /* disable nig egress interface */
11435 if (!CHIP_IS_E3(bp)) {
11436 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11437 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11440 /* Stop BigMac rx */
11441 if (!CHIP_IS_E3(bp))
11442 bnx2x_bmac_rx_disable(bp, port);
11444 bnx2x_xmac_disable(params);
11446 if (!CHIP_IS_E3(bp))
11447 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11450 /* The PHY reset is controlled by GPIO 1
11451 * Hold it as vars low
11453 /* clear link led */
11454 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11456 if (reset_ext_phy) {
11457 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11459 if (params->phy[phy_index].link_reset)
11460 params->phy[phy_index].link_reset(
11461 ¶ms->phy[phy_index],
11463 if (params->phy[phy_index].flags &
11464 FLAGS_REARM_LATCH_SIGNAL)
11465 clear_latch_ind = 1;
11469 if (clear_latch_ind) {
11470 /* Clear latching indication */
11471 bnx2x_rearm_latch_signal(bp, port, 0);
11472 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11473 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11475 if (params->phy[INT_PHY].link_reset)
11476 params->phy[INT_PHY].link_reset(
11477 ¶ms->phy[INT_PHY], params);
11479 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11480 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11482 /* disable nig ingress interface */
11483 if (!CHIP_IS_E3(bp)) {
11484 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11485 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11488 vars->phy_flags = 0;
11492 /****************************************************************************/
11493 /* Common function */
11494 /****************************************************************************/
11495 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11496 u32 shmem_base_path[],
11497 u32 shmem2_base_path[], u8 phy_index,
11500 struct bnx2x_phy phy[PORT_MAX];
11501 struct bnx2x_phy *phy_blk[PORT_MAX];
11504 s8 port_of_path = 0;
11505 u32 swap_val, swap_override;
11506 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11507 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11508 port ^= (swap_val && swap_override);
11509 bnx2x_ext_phy_hw_reset(bp, port);
11510 /* PART1 - Reset both phys */
11511 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11512 u32 shmem_base, shmem2_base;
11513 /* In E2, same phy is using for port0 of the two paths */
11514 if (CHIP_IS_E1x(bp)) {
11515 shmem_base = shmem_base_path[0];
11516 shmem2_base = shmem2_base_path[0];
11517 port_of_path = port;
11519 shmem_base = shmem_base_path[port];
11520 shmem2_base = shmem2_base_path[port];
11524 /* Extract the ext phy address for the port */
11525 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11526 port_of_path, &phy[port]) !=
11528 DP(NETIF_MSG_LINK, "populate_phy failed\n");
11531 /* disable attentions */
11532 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11534 (NIG_MASK_XGXS0_LINK_STATUS |
11535 NIG_MASK_XGXS0_LINK10G |
11536 NIG_MASK_SERDES0_LINK_STATUS |
11539 /* Need to take the phy out of low power mode in order
11540 to write to access its registers */
11541 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11542 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11545 /* Reset the phy */
11546 bnx2x_cl45_write(bp, &phy[port],
11552 /* Add delay of 150ms after reset */
11555 if (phy[PORT_0].addr & 0x1) {
11556 phy_blk[PORT_0] = &(phy[PORT_1]);
11557 phy_blk[PORT_1] = &(phy[PORT_0]);
11559 phy_blk[PORT_0] = &(phy[PORT_0]);
11560 phy_blk[PORT_1] = &(phy[PORT_1]);
11563 /* PART2 - Download firmware to both phys */
11564 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11565 if (CHIP_IS_E1x(bp))
11566 port_of_path = port;
11570 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11571 phy_blk[port]->addr);
11572 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11576 /* Only set bit 10 = 1 (Tx power down) */
11577 bnx2x_cl45_read(bp, phy_blk[port],
11579 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11581 /* Phase1 of TX_POWER_DOWN reset */
11582 bnx2x_cl45_write(bp, phy_blk[port],
11584 MDIO_PMA_REG_TX_POWER_DOWN,
11589 * Toggle Transmitter: Power down and then up with 600ms delay
11594 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11595 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11596 /* Phase2 of POWER_DOWN_RESET */
11597 /* Release bit 10 (Release Tx power down) */
11598 bnx2x_cl45_read(bp, phy_blk[port],
11600 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11602 bnx2x_cl45_write(bp, phy_blk[port],
11604 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11607 /* Read modify write the SPI-ROM version select register */
11608 bnx2x_cl45_read(bp, phy_blk[port],
11610 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11611 bnx2x_cl45_write(bp, phy_blk[port],
11613 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11615 /* set GPIO2 back to LOW */
11616 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11617 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11621 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11622 u32 shmem_base_path[],
11623 u32 shmem2_base_path[], u8 phy_index,
11628 struct bnx2x_phy phy;
11629 /* Use port1 because of the static port-swap */
11630 /* Enable the module detection interrupt */
11631 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11632 val |= ((1<<MISC_REGISTERS_GPIO_3)|
11633 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11634 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11636 bnx2x_ext_phy_hw_reset(bp, 0);
11638 for (port = 0; port < PORT_MAX; port++) {
11639 u32 shmem_base, shmem2_base;
11641 /* In E2, same phy is using for port0 of the two paths */
11642 if (CHIP_IS_E1x(bp)) {
11643 shmem_base = shmem_base_path[0];
11644 shmem2_base = shmem2_base_path[0];
11646 shmem_base = shmem_base_path[port];
11647 shmem2_base = shmem2_base_path[port];
11649 /* Extract the ext phy address for the port */
11650 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11653 DP(NETIF_MSG_LINK, "populate phy failed\n");
11658 bnx2x_cl45_write(bp, &phy,
11659 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11662 /* Set fault module detected LED on */
11663 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11664 MISC_REGISTERS_GPIO_HIGH,
11670 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11671 u8 *io_gpio, u8 *io_port)
11674 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11675 offsetof(struct shmem_region,
11676 dev_info.port_hw_config[PORT_0].default_cfg));
11677 switch (phy_gpio_reset) {
11678 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11682 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11686 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11690 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11694 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11698 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11702 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11706 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11711 /* Don't override the io_gpio and io_port */
11716 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11717 u32 shmem_base_path[],
11718 u32 shmem2_base_path[], u8 phy_index,
11721 s8 port, reset_gpio;
11722 u32 swap_val, swap_override;
11723 struct bnx2x_phy phy[PORT_MAX];
11724 struct bnx2x_phy *phy_blk[PORT_MAX];
11726 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11727 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11729 reset_gpio = MISC_REGISTERS_GPIO_1;
11733 * Retrieve the reset gpio/port which control the reset.
11734 * Default is GPIO1, PORT1
11736 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11737 (u8 *)&reset_gpio, (u8 *)&port);
11739 /* Calculate the port based on port swap */
11740 port ^= (swap_val && swap_override);
11742 /* Initiate PHY reset*/
11743 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11746 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11751 /* PART1 - Reset both phys */
11752 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11753 u32 shmem_base, shmem2_base;
11755 /* In E2, same phy is using for port0 of the two paths */
11756 if (CHIP_IS_E1x(bp)) {
11757 shmem_base = shmem_base_path[0];
11758 shmem2_base = shmem2_base_path[0];
11759 port_of_path = port;
11761 shmem_base = shmem_base_path[port];
11762 shmem2_base = shmem2_base_path[port];
11766 /* Extract the ext phy address for the port */
11767 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11768 port_of_path, &phy[port]) !=
11770 DP(NETIF_MSG_LINK, "populate phy failed\n");
11773 /* disable attentions */
11774 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11776 (NIG_MASK_XGXS0_LINK_STATUS |
11777 NIG_MASK_XGXS0_LINK10G |
11778 NIG_MASK_SERDES0_LINK_STATUS |
11782 /* Reset the phy */
11783 bnx2x_cl45_write(bp, &phy[port],
11784 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
11787 /* Add delay of 150ms after reset */
11789 if (phy[PORT_0].addr & 0x1) {
11790 phy_blk[PORT_0] = &(phy[PORT_1]);
11791 phy_blk[PORT_1] = &(phy[PORT_0]);
11793 phy_blk[PORT_0] = &(phy[PORT_0]);
11794 phy_blk[PORT_1] = &(phy[PORT_1]);
11796 /* PART2 - Download firmware to both phys */
11797 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11798 if (CHIP_IS_E1x(bp))
11799 port_of_path = port;
11802 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11803 phy_blk[port]->addr);
11804 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11812 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
11813 u32 shmem2_base_path[], u8 phy_index,
11814 u32 ext_phy_type, u32 chip_id)
11818 switch (ext_phy_type) {
11819 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11820 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
11822 phy_index, chip_id);
11824 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11825 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11826 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11827 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
11829 phy_index, chip_id);
11832 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11834 * GPIO1 affects both ports, so there's need to pull
11835 * it for single port alone
11837 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
11839 phy_index, chip_id);
11841 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11843 * GPIO3's are linked, and so both need to be toggled
11844 * to obtain required 2us pulse.
11846 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
11848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11853 "ext_phy 0x%x common init not required\n",
11859 netdev_err(bp->dev, "Warning: PHY was not initialized,"
11865 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
11866 u32 shmem2_base_path[], u32 chip_id)
11871 u32 ext_phy_type, ext_phy_config;
11872 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
11873 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
11874 DP(NETIF_MSG_LINK, "Begin common phy init\n");
11875 if (CHIP_IS_E3(bp)) {
11877 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
11878 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
11880 /* Check if common init was already done */
11881 phy_ver = REG_RD(bp, shmem_base_path[0] +
11882 offsetof(struct shmem_region,
11883 port_mb[PORT_0].ext_phy_fw_version));
11885 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
11890 /* Read the ext_phy_type for arbitrary port(0) */
11891 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
11893 ext_phy_config = bnx2x_get_ext_phy_config(bp,
11894 shmem_base_path[0],
11896 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11897 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
11899 phy_index, ext_phy_type,
11905 static void bnx2x_check_over_curr(struct link_params *params,
11906 struct link_vars *vars)
11908 struct bnx2x *bp = params->bp;
11910 u8 port = params->port;
11913 cfg_pin = (REG_RD(bp, params->shmem_base +
11914 offsetof(struct shmem_region,
11915 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
11916 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
11917 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
11919 /* Ignore check if no external input PIN available */
11920 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
11924 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
11925 netdev_err(bp->dev, "Error: Power fault on Port %d has"
11926 " been detected and the power to "
11927 "that SFP+ module has been removed"
11928 " to prevent failure of the card."
11929 " Please remove the SFP+ module and"
11930 " restart the system to clear this"
11933 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
11936 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
11939 static void bnx2x_analyze_link_error(struct link_params *params,
11940 struct link_vars *vars, u32 lss_status)
11942 struct bnx2x *bp = params->bp;
11943 /* Compare new value with previous value */
11945 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
11947 /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
11949 half_open_conn, lss_status);*/
11951 if ((lss_status ^ half_open_conn) == 0)
11954 /* If values differ */
11955 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
11956 half_open_conn, lss_status);
11959 * a. Update shmem->link_status accordingly
11960 * b. Update link_vars->link_up
11963 vars->link_status &= ~LINK_STATUS_LINK_UP;
11965 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
11967 * Set LED mode to off since the PHY doesn't know about these
11970 led_mode = LED_MODE_OFF;
11972 vars->link_status |= LINK_STATUS_LINK_UP;
11974 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
11975 led_mode = LED_MODE_OPER;
11977 /* Update the LED according to the link state */
11978 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
11980 /* Update link status in the shared memory */
11981 bnx2x_update_mng(params, vars->link_status);
11983 /* C. Trigger General Attention */
11984 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
11985 bnx2x_notify_link_changed(bp);
11988 static void bnx2x_check_half_open_conn(struct link_params *params,
11989 struct link_vars *vars)
11991 struct bnx2x *bp = params->bp;
11992 u32 lss_status = 0;
11994 /* In case link status is physically up @ 10G do */
11995 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
11998 if (!CHIP_IS_E3(bp) &&
11999 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12000 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12001 /* Check E1X / E2 BMAC */
12002 u32 lss_status_reg;
12004 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12005 NIG_REG_INGRESS_BMAC0_MEM;
12006 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12007 if (CHIP_IS_E2(bp))
12008 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12010 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12012 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12013 lss_status = (wb_data[0] > 0);
12015 bnx2x_analyze_link_error(params, vars, lss_status);
12019 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12021 struct bnx2x *bp = params->bp;
12023 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12026 /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12027 RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12028 REG_RD(bp, MISC_REG_RESET_REG_2)); */
12029 bnx2x_check_half_open_conn(params, vars);
12030 if (CHIP_IS_E3(bp))
12031 bnx2x_check_over_curr(params, vars);
12034 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12037 struct bnx2x_phy phy;
12038 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12040 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12042 DP(NETIF_MSG_LINK, "populate phy failed\n");
12046 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12052 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12057 u8 phy_index, fan_failure_det_req = 0;
12058 struct bnx2x_phy phy;
12059 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12061 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12064 DP(NETIF_MSG_LINK, "populate phy failed\n");
12067 fan_failure_det_req |= (phy.flags &
12068 FLAGS_FAN_FAILURE_DET_REQ);
12070 return fan_failure_det_req;
12073 void bnx2x_hw_reset_phy(struct link_params *params)
12076 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12078 if (params->phy[phy_index].hw_reset) {
12079 params->phy[phy_index].hw_reset(
12080 ¶ms->phy[phy_index],
12082 params->phy[phy_index] = phy_null;
12087 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12088 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12091 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12093 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12094 if (CHIP_IS_E3(bp)) {
12095 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12102 struct bnx2x_phy phy;
12103 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12105 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12106 shmem2_base, port, &phy)
12108 DP(NETIF_MSG_LINK, "populate phy failed\n");
12111 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12112 gpio_num = MISC_REGISTERS_GPIO_3;
12119 if (gpio_num == 0xff)
12122 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12123 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12125 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12126 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12127 gpio_port ^= (swap_val && swap_override);
12129 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12130 (gpio_num + (gpio_port << 2));
12132 sync_offset = shmem_base +
12133 offsetof(struct shmem_region,
12134 dev_info.port_hw_config[port].aeu_int_mask);
12135 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12137 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12138 gpio_num, gpio_port, vars->aeu_int_mask);
12141 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12143 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12145 /* Open appropriate AEU for interrupts */
12146 aeu_mask = REG_RD(bp, offset);
12147 aeu_mask |= vars->aeu_int_mask;
12148 REG_WR(bp, offset, aeu_mask);
12150 /* Enable the GPIO to trigger interrupt */
12151 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12152 val |= 1 << (gpio_num + (gpio_port << 2));
12153 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);