drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40
  41 /***********************************************************/
  42 /*                      Shortcut definitions               */
  43 /***********************************************************/
  44
  45 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  46
  47 #define NIG_STATUS_EMAC0_MI_INT \
  48                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  49 #define NIG_STATUS_XGXS0_LINK10G \
  50                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  51 #define NIG_STATUS_XGXS0_LINK_STATUS \
  52                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  53 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  54                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  55 #define NIG_STATUS_SERDES0_LINK_STATUS \
  56                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  57 #define NIG_MASK_MI_INT \
  58                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  59 #define NIG_MASK_XGXS0_LINK10G \
  60                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  61 #define NIG_MASK_XGXS0_LINK_STATUS \
  62                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  63 #define NIG_MASK_SERDES0_LINK_STATUS \
  64                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  65
  66 #define MDIO_AN_CL73_OR_37_COMPLETE \
  67                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  68                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  69
  70 #define XGXS_RESET_BITS \
  71         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  73          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  74          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  75          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  76
  77 #define SERDES_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  82
  83 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  84 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  85 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  86 #define AUTONEG_PARALLEL \
  87                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  88 #define AUTONEG_SGMII_FIBER_AUTODET \
  89                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  90 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  91
  92 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  93                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  94 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  95                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  96 #define GP_STATUS_SPEED_MASK \
  97                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  98 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  99 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 100 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 101 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 102 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 103 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 104 #define GP_STATUS_10G_HIG \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 106 #define GP_STATUS_10G_CX4 \
 107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 108 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 109 #define GP_STATUS_10G_KX4 \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 111
 112 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 113 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 114 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 115 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 116 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 117 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 118 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 119 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 120 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 121 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 122 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 123 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 124 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 125
 126 #define PHY_XGXS_FLAG                   0x1
 127 #define PHY_SGMII_FLAG                  0x2
 128 #define PHY_SERDES_FLAG                 0x4
 129
 130 /* */
 131 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 132         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 133         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 134
 135
 136 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 137         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 138         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 139         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 140
 141 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 142         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 143         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 144
 145 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 146         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 147 #define SFP_EEPROM_OPTIONS_SIZE                 2
 148
 149 #define EDC_MODE_LINEAR                         0x0022
 150 #define EDC_MODE_LIMITING                               0x0044
 151 #define EDC_MODE_PASSIVE_DAC                    0x0055
 152
 153
 154 /* BRB thresholds for E2*/
 155 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 156 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 157
 158 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 159 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 160
 161 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 162 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 163
 164 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 165 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 166
 167 /* BRB thresholds for E3A0 */
 168 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 169 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 170
 171 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 172 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 173
 174 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 175 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 176
 177 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 178 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 179
 180
 181 /* BRB thresholds for E3B0 2 port mode*/
 182 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 183 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 184
 185 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 186 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 187
 188 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 189 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 190
 191 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 192 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 193
 194 /* only for E3B0*/
 195 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 196 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 197
 198 /* Lossy +Lossless GUARANTIED == GUART */
 199 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 200 /* Lossless +Lossless*/
 201 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 202 /* Lossy +Lossy*/
 203 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 204
 205 /* Lossy +Lossless*/
 206 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 207 /* Lossless +Lossless*/
 208 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 209 /* Lossy +Lossy*/
 210 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 211 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 212
 213 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 214 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 215
 216 /* BRB thresholds for E3B0 4 port mode */
 217 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 218 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 219
 220 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 221 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 222
 223 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 224 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 225
 226 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 227 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 228
 229
 230 /* only for E3B0*/
 231 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 232 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 233 #define PFC_E3B0_4P_LB_GUART                            120
 234
 235 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 236 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 237
 238 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 239 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 240
 241 #define DCBX_INVALID_COS                                        (0xFF)
 242
 243 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 244 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 245 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 246 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 247 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 248
 249 #define MAX_PACKET_SIZE                                 (9700)
 250
 251 /**********************************************************/
 252 /*                     INTERFACE                          */
 253 /**********************************************************/
 254
 255 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 256         bnx2x_cl45_write(_bp, _phy, \
 257                 (_phy)->def_md_devad, \
 258                 (_bank + (_addr & 0xf)), \
 259                 _val)
 260
 261 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 262         bnx2x_cl45_read(_bp, _phy, \
 263                 (_phy)->def_md_devad, \
 264                 (_bank + (_addr & 0xf)), \
 265                 _val)
 266
 267 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 268 {
 269         u32 val = REG_RD(bp, reg);
 270
 271         val |= bits;
 272         REG_WR(bp, reg, val);
 273         return val;
 274 }
 275
 276 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 277 {
 278         u32 val = REG_RD(bp, reg);
 279
 280         val &= ~bits;
 281         REG_WR(bp, reg, val);
 282         return val;
 283 }
 284
 285 /******************************************************************/
 286 /*                              ETS section                       */
 287 /******************************************************************/
 288 void bnx2x_ets_disabled(struct link_params *params)
 289 {
 290         /* ETS disabled configuration*/
 291         struct bnx2x *bp = params->bp;
 292
 293         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 294
 295         /*
 296          * mapping between entry  priority to client number (0,1,2 -debug and
 297          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 298          * 3bits client num.
 299          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 300          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 301          */
 302
 303         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 304         /*
 305          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 306          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 307          * COS0 entry, 4 - COS1 entry.
 308          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 309          * bit4   bit3    bit2   bit1     bit0
 310          * MCP and debug are strict
 311          */
 312
 313         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 314         /* defines which entries (clients) are subjected to WFQ arbitration */
 315         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 316         /*
 317          * For strict priority entries defines the number of consecutive
 318          * slots for the highest priority.
 319          */
 320         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 321         /*
 322          * mapping between the CREDIT_WEIGHT registers and actual client
 323          * numbers
 324          */
 325         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 326         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 327         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 328
 329         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 330         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 331         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 332         /* ETS mode disable */
 333         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 334         /*
 335          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 336          * weight for COS0/COS1.
 337          */
 338         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 339         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 340         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 341         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 342         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 343         /* Defines the number of consecutive slots for the strict priority */
 344         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 345 }
 346
 347 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
 348 {
 349         /* ETS disabled configuration */
 350         struct bnx2x *bp = params->bp;
 351         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 352         /*
 353          * defines which entries (clients) are subjected to WFQ arbitration
 354          * COS0 0x8
 355          * COS1 0x10
 356          */
 357         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 358         /*
 359          * mapping between the ARB_CREDIT_WEIGHT registers and actual
 360          * client numbers (WEIGHT_0 does not actually have to represent
 361          * client 0)
 362          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 363          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 364          */
 365         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 366
 367         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 368                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 369         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 370                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 371
 372         /* ETS mode enabled*/
 373         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 374
 375         /* Defines the number of consecutive slots for the strict priority */
 376         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 377         /*
 378          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 379          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 380          * entry, 4 - COS1 entry.
 381          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 382          * bit4   bit3    bit2     bit1    bit0
 383          * MCP and debug are strict
 384          */
 385         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 386
 387         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 388         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 389                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 390         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 391                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 392 }
 393
 394 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 395                         const u32 cos1_bw)
 396 {
 397         /* ETS disabled configuration*/
 398         struct bnx2x *bp = params->bp;
 399         const u32 total_bw = cos0_bw + cos1_bw;
 400         u32 cos0_credit_weight = 0;
 401         u32 cos1_credit_weight = 0;
 402
 403         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 404
 405         if ((0 == total_bw) ||
 406             (0 == cos0_bw) ||
 407             (0 == cos1_bw)) {
 408                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
 409                 return;
 410         }
 411
 412         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 413                 total_bw;
 414         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 415                 total_bw;
 416
 417         bnx2x_ets_bw_limit_common(params);
 418
 419         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 420         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 421
 422         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 423         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 424 }
 425
 426 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 427 {
 428         /* ETS disabled configuration*/
 429         struct bnx2x *bp = params->bp;
 430         u32 val = 0;
 431
 432         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 433         /*
 434          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 435          * as strict.  Bits 0,1,2 - debug and management entries,
 436          * 3 - COS0 entry, 4 - COS1 entry.
 437          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 438          *  bit4   bit3   bit2      bit1     bit0
 439          * MCP and debug are strict
 440          */
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 442         /*
 443          * For strict priority entries defines the number of consecutive slots
 444          * for the highest priority.
 445          */
 446         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 447         /* ETS mode disable */
 448         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 449         /* Defines the number of consecutive slots for the strict priority */
 450         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 451
 452         /* Defines the number of consecutive slots for the strict priority */
 453         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 454
 455         /*
 456          * mapping between entry  priority to client number (0,1,2 -debug and
 457          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 458          * 3bits client num.
 459          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 460          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 461          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 462          */
 463         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 464         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 465
 466         return 0;
 467 }
 468 /******************************************************************/
 469 /*                      PFC section                               */
 470 /******************************************************************/
 471
 472 static void bnx2x_update_pfc_xmac(struct link_params *params,
 473                                   struct link_vars *vars,
 474                                   u8 is_lb)
 475 {
 476         struct bnx2x *bp = params->bp;
 477         u32 xmac_base;
 478         u32 pause_val, pfc0_val, pfc1_val;
 479
 480         /* XMAC base adrr */
 481         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
 482
 483         /* Initialize pause and pfc registers */
 484         pause_val = 0x18000;
 485         pfc0_val = 0xFFFF8000;
 486         pfc1_val = 0x2;
 487
 488         /* No PFC support */
 489         if (!(params->feature_config_flags &
 490               FEATURE_CONFIG_PFC_ENABLED)) {
 491
 492                 /*
 493                  * RX flow control - Process pause frame in receive direction
 494                  */
 495                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 496                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
 497
 498                 /*
 499                  * TX flow control - Send pause packet when buffer is full
 500                  */
 501                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 502                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
 503         } else {/* PFC support */
 504                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
 505                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
 506                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
 507                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
 508         }
 509
 510         /* Write pause and PFC registers */
 511         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
 512         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
 513         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
 514
 515         udelay(30);
 516 }
 517
 518
 519 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 520                                      u32 pfc_frames_sent[2],
 521                                      u32 pfc_frames_received[2])
 522 {
 523         /* Read pfc statistic */
 524         struct bnx2x *bp = params->bp;
 525         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 526                 NIG_REG_INGRESS_BMAC0_MEM;
 527
 528         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 529
 530         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 531                                         pfc_frames_sent, 2);
 532
 533         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 534                                         pfc_frames_received, 2);
 535
 536 }
 537 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 538                                     u32 pfc_frames_sent[2],
 539                                     u32 pfc_frames_received[2])
 540 {
 541         /* Read pfc statistic */
 542         struct bnx2x *bp = params->bp;
 543         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 544         u32 val_xon = 0;
 545         u32 val_xoff = 0;
 546
 547         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 548
 549         /* PFC received frames */
 550         val_xoff = REG_RD(bp, emac_base +
 551                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 552         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 553         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 554         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 555
 556         pfc_frames_received[0] = val_xon + val_xoff;
 557
 558         /* PFC received sent */
 559         val_xoff = REG_RD(bp, emac_base +
 560                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 561         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 562         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 563         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 564
 565         pfc_frames_sent[0] = val_xon + val_xoff;
 566 }
 567
 568 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 569                          u32 pfc_frames_sent[2],
 570                          u32 pfc_frames_received[2])
 571 {
 572         /* Read pfc statistic */
 573         struct bnx2x *bp = params->bp;
 574         u32 val = 0;
 575         DP(NETIF_MSG_LINK, "pfc statistic\n");
 576
 577         if (!vars->link_up)
 578                 return;
 579
 580         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 581         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 582             == 0) {
 583                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 584                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 585                                         pfc_frames_received);
 586         } else {
 587                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 588                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 589                                          pfc_frames_received);
 590         }
 591 }
 592 /******************************************************************/
 593 /*                      MAC/PBF section                           */
 594 /******************************************************************/
 595 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
 596 {
 597         u32 mode, emac_base;
 598         /**
 599          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
 600          * (a value of 49==0x31) and make sure that the AUTO poll is off
 601          */
 602
 603         if (CHIP_IS_E2(bp))
 604                 emac_base = GRCBASE_EMAC0;
 605         else
 606                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 607         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
 608         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
 609                   EMAC_MDIO_MODE_CLOCK_CNT);
 610         mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
 611
 612         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
 613         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
 614
 615         udelay(40);
 616 }
 617
 618 static void bnx2x_emac_init(struct link_params *params,
 619                             struct link_vars *vars)
 620 {
 621         /* reset and unreset the emac core */
 622         struct bnx2x *bp = params->bp;
 623         u8 port = params->port;
 624         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 625         u32 val;
 626         u16 timeout;
 627
 628         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 629                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 630         udelay(5);
 631         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 632                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 633
 634         /* init emac - use read-modify-write */
 635         /* self clear reset */
 636         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 637         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 638
 639         timeout = 200;
 640         do {
 641                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 642                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 643                 if (!timeout) {
 644                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 645                         return;
 646                 }
 647                 timeout--;
 648         } while (val & EMAC_MODE_RESET);
 649         bnx2x_set_mdio_clk(bp, params->chip_id, port);
 650         /* Set mac address */
 651         val = ((params->mac_addr[0] << 8) |
 652                 params->mac_addr[1]);
 653         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 654
 655         val = ((params->mac_addr[2] << 24) |
 656                (params->mac_addr[3] << 16) |
 657                (params->mac_addr[4] << 8) |
 658                 params->mac_addr[5]);
 659         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 660 }
 661
 662 static void bnx2x_set_xumac_nig(struct link_params *params,
 663                                 u16 tx_pause_en,
 664                                 u8 enable)
 665 {
 666         struct bnx2x *bp = params->bp;
 667
 668         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
 669                enable);
 670         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
 671                enable);
 672         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
 673                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
 674 }
 675
 676 static void bnx2x_umac_enable(struct link_params *params,
 677                             struct link_vars *vars, u8 lb)
 678 {
 679         u32 val;
 680         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
 681         struct bnx2x *bp = params->bp;
 682         /* Reset UMAC */
 683         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 684                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
 685         usleep_range(1000, 1000);
 686
 687         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 688                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
 689
 690         DP(NETIF_MSG_LINK, "enabling UMAC\n");
 691
 692         /**
 693          * This register determines on which events the MAC will assert
 694          * error on the i/f to the NIG along w/ EOP.
 695          */
 696
 697         /**
 698          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
 699          * params->port*0x14,      0xfffff.
 700          */
 701         /* This register opens the gate for the UMAC despite its name */
 702         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
 703
 704         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
 705                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
 706                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
 707                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
 708         switch (vars->line_speed) {
 709         case SPEED_10:
 710                 val |= (0<<2);
 711                 break;
 712         case SPEED_100:
 713                 val |= (1<<2);
 714                 break;
 715         case SPEED_1000:
 716                 val |= (2<<2);
 717                 break;
 718         case SPEED_2500:
 719                 val |= (3<<2);
 720                 break;
 721         default:
 722                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
 723                                vars->line_speed);
 724                 break;
 725         }
 726         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
 727         udelay(50);
 728
 729         /* Enable RX and TX */
 730         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
 731         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
 732                UMAC_COMMAND_CONFIG_REG_RX_ENA;
 733         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
 734         udelay(50);
 735
 736         /* Remove SW Reset */
 737         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
 738
 739         /* Check loopback mode */
 740         if (lb)
 741                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
 742         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
 743
 744         /*
 745          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
 746          * length used by the MAC receive logic to check frames.
 747          */
 748         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
 749         bnx2x_set_xumac_nig(params,
 750                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
 751         vars->mac_type = MAC_TYPE_UMAC;
 752
 753 }
 754
 755 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
 756 {
 757         u32 port4mode_ovwr_val;
 758         /* Check 4-port override enabled */
 759         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
 760         if (port4mode_ovwr_val & (1<<0)) {
 761                 /* Return 4-port mode override value */
 762                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
 763         }
 764         /* Return 4-port mode from input pin */
 765         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
 766 }
 767
 768 /* Define the XMAC mode */
 769 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
 770 {
 771         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
 772
 773         /**
 774         * In 4-port mode, need to set the mode only once, so if XMAC is
 775         * already out of reset, it means the mode has already been set,
 776         * and it must not* reset the XMAC again, since it controls both
 777         * ports of the path
 778         **/
 779
 780         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
 781              MISC_REGISTERS_RESET_REG_2_XMAC)) {
 782                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
 783                                    " in 4-port mode\n");
 784                 return;
 785         }
 786
 787         /* Hard reset */
 788         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 789                MISC_REGISTERS_RESET_REG_2_XMAC);
 790         usleep_range(1000, 1000);
 791
 792         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 793                MISC_REGISTERS_RESET_REG_2_XMAC);
 794         if (is_port4mode) {
 795                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
 796
 797                 /*  Set the number of ports on the system side to up to 2 */
 798                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
 799
 800                 /* Set the number of ports on the Warp Core to 10G */
 801                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
 802         } else {
 803                 /*  Set the number of ports on the system side to 1 */
 804                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
 805                 if (max_speed == SPEED_10000) {
 806                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
 807                                            " port per path\n");
 808                         /* Set the number of ports on the Warp Core to 10G */
 809                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
 810                 } else {
 811                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
 812                                            " per path\n");
 813                         /* Set the number of ports on the Warp Core to 20G */
 814                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
 815                 }
 816         }
 817         /* Soft reset */
 818         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 819                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
 820         usleep_range(1000, 1000);
 821
 822         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 823                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
 824
 825 }
 826
 827 static void bnx2x_xmac_disable(struct link_params *params)
 828 {
 829         u8 port = params->port;
 830         struct bnx2x *bp = params->bp;
 831         u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
 832
 833         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
 834             MISC_REGISTERS_RESET_REG_2_XMAC) {
 835                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
 836                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
 837                 usleep_range(1000, 1000);
 838                 bnx2x_set_xumac_nig(params, 0, 0);
 839                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
 840                        XMAC_CTRL_REG_SOFT_RESET);
 841         }
 842 }
 843
 844 static int bnx2x_xmac_enable(struct link_params *params,
 845                              struct link_vars *vars, u8 lb)
 846 {
 847         u32 val, xmac_base;
 848         struct bnx2x *bp = params->bp;
 849         DP(NETIF_MSG_LINK, "enabling XMAC\n");
 850
 851         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
 852
 853         bnx2x_xmac_init(bp, vars->line_speed);
 854
 855         /*
 856          * This register determines on which events the MAC will assert
 857          * error on the i/f to the NIG along w/ EOP.
 858          */
 859
 860         /*
 861          * This register tells the NIG whether to send traffic to UMAC
 862          * or XMAC
 863          */
 864         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
 865
 866         /* Set Max packet size */
 867         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
 868
 869         /* CRC append for Tx packets */
 870         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
 871
 872         /* update PFC */
 873         bnx2x_update_pfc_xmac(params, vars, 0);
 874
 875         /* Enable TX and RX */
 876         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
 877
 878         /* Check loopback mode */
 879         if (lb)
 880                 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
 881         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
 882         bnx2x_set_xumac_nig(params,
 883                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
 884
 885         vars->mac_type = MAC_TYPE_XMAC;
 886
 887         return 0;
 888 }
 889 static int bnx2x_emac_enable(struct link_params *params,
 890                              struct link_vars *vars, u8 lb)
 891 {
 892         struct bnx2x *bp = params->bp;
 893         u8 port = params->port;
 894         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 895         u32 val;
 896
 897         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 898
 899         /* enable emac and not bmac */
 900         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 901
 902         /* ASIC */
 903         if (vars->phy_flags & PHY_XGXS_FLAG) {
 904                 u32 ser_lane = ((params->lane_config &
 905                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 906                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 907
 908                 DP(NETIF_MSG_LINK, "XGXS\n");
 909                 /* select the master lanes (out of 0-3) */
 910                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
 911                 /* select XGXS */
 912                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
 913
 914         } else { /* SerDes */
 915                 DP(NETIF_MSG_LINK, "SerDes\n");
 916                 /* select SerDes */
 917                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
 918         }
 919
 920         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 921                       EMAC_RX_MODE_RESET);
 922         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 923                       EMAC_TX_MODE_RESET);
 924
 925         if (CHIP_REV_IS_SLOW(bp)) {
 926                 /* config GMII mode */
 927                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 928                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
 929         } else { /* ASIC */
 930                 /* pause enable/disable */
 931                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 932                                EMAC_RX_MODE_FLOW_EN);
 933
 934                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 935                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 936                                 EMAC_TX_MODE_FLOW_EN));
 937                 if (!(params->feature_config_flags &
 938                       FEATURE_CONFIG_PFC_ENABLED)) {
 939                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 940                                 bnx2x_bits_en(bp, emac_base +
 941                                               EMAC_REG_EMAC_RX_MODE,
 942                                               EMAC_RX_MODE_FLOW_EN);
 943
 944                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 945                                 bnx2x_bits_en(bp, emac_base +
 946                                               EMAC_REG_EMAC_TX_MODE,
 947                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 948                                                EMAC_TX_MODE_FLOW_EN));
 949                 } else
 950                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 951                                       EMAC_TX_MODE_FLOW_EN);
 952         }
 953
 954         /* KEEP_VLAN_TAG, promiscuous */
 955         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 956         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 957
 958         /*
 959          * Setting this bit causes MAC control frames (except for pause
 960          * frames) to be passed on for processing. This setting has no
 961          * affect on the operation of the pause frames. This bit effects
 962          * all packets regardless of RX Parser packet sorting logic.
 963          * Turn the PFC off to make sure we are in Xon state before
 964          * enabling it.
 965          */
 966         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 967         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 968                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 969                 /* Enable PFC again */
 970                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 971                         EMAC_REG_RX_PFC_MODE_RX_EN |
 972                         EMAC_REG_RX_PFC_MODE_TX_EN |
 973                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 974
 975                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 976                         ((0x0101 <<
 977                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 978                          (0x00ff <<
 979                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 980                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 981         }
 982         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 983
 984         /* Set Loopback */
 985         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 986         if (lb)
 987                 val |= 0x810;
 988         else
 989                 val &= ~0x810;
 990         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 991
 992         /* enable emac */
 993         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 994
 995         /* enable emac for jumbo packets */
 996         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 997                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 998                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 999
1000         /* strip CRC */
1001         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1002
1003         /* disable the NIG in/out to the bmac */
1004         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1005         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1006         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1007
1008         /* enable the NIG in/out to the emac */
1009         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1010         val = 0;
1011         if ((params->feature_config_flags &
1012               FEATURE_CONFIG_PFC_ENABLED) ||
1013             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1014                 val = 1;
1015
1016         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1017         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1018
1019         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1020
1021         vars->mac_type = MAC_TYPE_EMAC;
1022         return 0;
1023 }
1024
1025 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1026                                    struct link_vars *vars)
1027 {
1028         u32 wb_data[2];
1029         struct bnx2x *bp = params->bp;
1030         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1031                 NIG_REG_INGRESS_BMAC0_MEM;
1032
1033         u32 val = 0x14;
1034         if ((!(params->feature_config_flags &
1035               FEATURE_CONFIG_PFC_ENABLED)) &&
1036                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1037                 /* Enable BigMAC to react on received Pause packets */
1038                 val |= (1<<5);
1039         wb_data[0] = val;
1040         wb_data[1] = 0;
1041         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1042
1043         /* tx control */
1044         val = 0xc0;
1045         if (!(params->feature_config_flags &
1046               FEATURE_CONFIG_PFC_ENABLED) &&
1047                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1048                 val |= 0x800000;
1049         wb_data[0] = val;
1050         wb_data[1] = 0;
1051         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1052 }
1053
1054 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1055                                    struct link_vars *vars,
1056                                    u8 is_lb)
1057 {
1058         /*
1059          * Set rx control: Strip CRC and enable BigMAC to relay
1060          * control packets to the system as well
1061          */
1062         u32 wb_data[2];
1063         struct bnx2x *bp = params->bp;
1064         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1065                 NIG_REG_INGRESS_BMAC0_MEM;
1066         u32 val = 0x14;
1067
1068         if ((!(params->feature_config_flags &
1069               FEATURE_CONFIG_PFC_ENABLED)) &&
1070                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1071                 /* Enable BigMAC to react on received Pause packets */
1072                 val |= (1<<5);
1073         wb_data[0] = val;
1074         wb_data[1] = 0;
1075         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1076         udelay(30);
1077
1078         /* Tx control */
1079         val = 0xc0;
1080         if (!(params->feature_config_flags &
1081                                 FEATURE_CONFIG_PFC_ENABLED) &&
1082             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1083                 val |= 0x800000;
1084         wb_data[0] = val;
1085         wb_data[1] = 0;
1086         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1087
1088         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1089                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1090                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1091                 wb_data[0] = 0x0;
1092                 wb_data[0] |= (1<<0);  /* RX */
1093                 wb_data[0] |= (1<<1);  /* TX */
1094                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1095                 wb_data[0] |= (1<<3);  /* 8 cos */
1096                 wb_data[0] |= (1<<5);  /* STATS */
1097                 wb_data[1] = 0;
1098                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1099                             wb_data, 2);
1100                 /* Clear the force Xon */
1101                 wb_data[0] &= ~(1<<2);
1102         } else {
1103                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1104                 /* disable PFC RX & TX & STATS and set 8 COS */
1105                 wb_data[0] = 0x8;
1106                 wb_data[1] = 0;
1107         }
1108
1109         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1110
1111         /*
1112          * Set Time (based unit is 512 bit time) between automatic
1113          * re-sending of PP packets amd enable automatic re-send of
1114          * Per-Priroity Packet as long as pp_gen is asserted and
1115          * pp_disable is low.
1116          */
1117         val = 0x8000;
1118         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1119                 val |= (1<<16); /* enable automatic re-send */
1120
1121         wb_data[0] = val;
1122         wb_data[1] = 0;
1123         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1124                     wb_data, 2);
1125
1126         /* mac control */
1127         val = 0x3; /* Enable RX and TX */
1128         if (is_lb) {
1129                 val |= 0x4; /* Local loopback */
1130                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1131         }
1132         /* When PFC enabled, Pass pause frames towards the NIG. */
1133         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1134                 val |= ((1<<6)|(1<<5));
1135
1136         wb_data[0] = val;
1137         wb_data[1] = 0;
1138         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1139 }
1140
1141
1142 /* PFC BRB internal port configuration params */
1143 struct bnx2x_pfc_brb_threshold_val {
1144         u32 pause_xoff;
1145         u32 pause_xon;
1146         u32 full_xoff;
1147         u32 full_xon;
1148 };
1149
1150 struct bnx2x_pfc_brb_e3b0_val {
1151         u32 full_lb_xoff_th;
1152         u32 full_lb_xon_threshold;
1153         u32 lb_guarantied;
1154         u32 mac_0_class_t_guarantied;
1155         u32 mac_0_class_t_guarantied_hyst;
1156         u32 mac_1_class_t_guarantied;
1157         u32 mac_1_class_t_guarantied_hyst;
1158 };
1159
1160 struct bnx2x_pfc_brb_th_val {
1161         struct bnx2x_pfc_brb_threshold_val pauseable_th;
1162         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1163 };
1164 static int bnx2x_pfc_brb_get_config_params(
1165                                 struct link_params *params,
1166                                 struct bnx2x_pfc_brb_th_val *config_val)
1167 {
1168         struct bnx2x *bp = params->bp;
1169         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
1170         if (CHIP_IS_E2(bp)) {
1171                 config_val->pauseable_th.pause_xoff =
1172                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1173                 config_val->pauseable_th.pause_xon =
1174                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
1175                 config_val->pauseable_th.full_xoff =
1176                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
1177                 config_val->pauseable_th.full_xon =
1178                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
1179                 /* non pause able*/
1180                 config_val->non_pauseable_th.pause_xoff =
1181                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1182                 config_val->non_pauseable_th.pause_xon =
1183                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1184                 config_val->non_pauseable_th.full_xoff =
1185                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1186                 config_val->non_pauseable_th.full_xon =
1187                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1188         } else if (CHIP_IS_E3A0(bp)) {
1189                 config_val->pauseable_th.pause_xoff =
1190                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1191                 config_val->pauseable_th.pause_xon =
1192                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
1193                 config_val->pauseable_th.full_xoff =
1194                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
1195                 config_val->pauseable_th.full_xon =
1196                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
1197                 /* non pause able*/
1198                 config_val->non_pauseable_th.pause_xoff =
1199                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1200                 config_val->non_pauseable_th.pause_xon =
1201                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1202                 config_val->non_pauseable_th.full_xoff =
1203                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1204                 config_val->non_pauseable_th.full_xon =
1205                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1206         } else if (CHIP_IS_E3B0(bp)) {
1207                 if (params->phy[INT_PHY].flags &
1208                     FLAGS_4_PORT_MODE) {
1209                         config_val->pauseable_th.pause_xoff =
1210                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1211                         config_val->pauseable_th.pause_xon =
1212                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
1213                         config_val->pauseable_th.full_xoff =
1214                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
1215                         config_val->pauseable_th.full_xon =
1216                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
1217                         /* non pause able*/
1218                         config_val->non_pauseable_th.pause_xoff =
1219                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1220                         config_val->non_pauseable_th.pause_xon =
1221                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1222                         config_val->non_pauseable_th.full_xoff =
1223                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1224                         config_val->non_pauseable_th.full_xon =
1225                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1226             } else {
1227                 config_val->pauseable_th.pause_xoff =
1228                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
1229                 config_val->pauseable_th.pause_xon =
1230                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
1231                 config_val->pauseable_th.full_xoff =
1232                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
1233                 config_val->pauseable_th.full_xon =
1234                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
1235                 /* non pause able*/
1236                 config_val->non_pauseable_th.pause_xoff =
1237                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
1238                 config_val->non_pauseable_th.pause_xon =
1239                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
1240                 config_val->non_pauseable_th.full_xoff =
1241                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
1242                 config_val->non_pauseable_th.full_xon =
1243                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
1244             }
1245         } else
1246             return -EINVAL;
1247
1248         return 0;
1249 }
1250
1251
1252 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
1253                                                  struct bnx2x_pfc_brb_e3b0_val
1254                                                  *e3b0_val,
1255                                                  u32 cos0_pauseable,
1256                                                  u32 cos1_pauseable)
1257 {
1258         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
1259                 e3b0_val->full_lb_xoff_th =
1260                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
1261                 e3b0_val->full_lb_xon_threshold =
1262                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
1263                 e3b0_val->lb_guarantied =
1264                     PFC_E3B0_4P_LB_GUART;
1265                 e3b0_val->mac_0_class_t_guarantied =
1266                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
1267                 e3b0_val->mac_0_class_t_guarantied_hyst =
1268                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
1269                 e3b0_val->mac_1_class_t_guarantied =
1270                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
1271                 e3b0_val->mac_1_class_t_guarantied_hyst =
1272                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
1273         } else {
1274                 e3b0_val->full_lb_xoff_th =
1275                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
1276                 e3b0_val->full_lb_xon_threshold =
1277                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
1278                 e3b0_val->mac_0_class_t_guarantied_hyst =
1279                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
1280                 e3b0_val->mac_1_class_t_guarantied =
1281                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
1282                 e3b0_val->mac_1_class_t_guarantied_hyst =
1283                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
1284
1285                 if (cos0_pauseable != cos1_pauseable) {
1286                         /* nonpauseable= Lossy + pauseable = Lossless*/
1287                         e3b0_val->lb_guarantied =
1288                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
1289                         e3b0_val->mac_0_class_t_guarantied =
1290                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
1291                 } else if (cos0_pauseable) {
1292                         /* Lossless +Lossless*/
1293                         e3b0_val->lb_guarantied =
1294                             PFC_E3B0_2P_PAUSE_LB_GUART;
1295                         e3b0_val->mac_0_class_t_guarantied =
1296                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
1297                 } else {
1298                         /* Lossy +Lossy*/
1299                         e3b0_val->lb_guarantied =
1300                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
1301                         e3b0_val->mac_0_class_t_guarantied =
1302                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
1303                 }
1304         }
1305 }
1306 static int bnx2x_update_pfc_brb(struct link_params *params,
1307                                 struct link_vars *vars,
1308                                 struct bnx2x_nig_brb_pfc_port_params
1309                                 *pfc_params)
1310 {
1311         struct bnx2x *bp = params->bp;
1312         struct bnx2x_pfc_brb_th_val config_val = { {0} };
1313         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
1314             &config_val.pauseable_th;
1315         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
1316         int set_pfc = params->feature_config_flags &
1317                 FEATURE_CONFIG_PFC_ENABLED;
1318         int bnx2x_status = 0;
1319         u8 port = params->port;
1320
1321         /* default - pause configuration */
1322         reg_th_config = &config_val.pauseable_th;
1323         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
1324         if (0 != bnx2x_status)
1325                 return bnx2x_status;
1326
1327         if (set_pfc && pfc_params)
1328                 /* First COS */
1329                 if (!pfc_params->cos0_pauseable)
1330                         reg_th_config = &config_val.non_pauseable_th;
1331         /*
1332          * The number of free blocks below which the pause signal to class 0
1333          * of MAC #n is asserted. n=0,1
1334          */
1335         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
1336                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
1337                reg_th_config->pause_xoff);
1338         /*
1339          * The number of free blocks above which the pause signal to class 0
1340          * of MAC #n is de-asserted. n=0,1
1341          */
1342         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
1343                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
1344         /*
1345          * The number of free blocks below which the full signal to class 0
1346          * of MAC #n is asserted. n=0,1
1347          */
1348         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
1349                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
1350         /*
1351          * The number of free blocks above which the full signal to class 0
1352          * of MAC #n is de-asserted. n=0,1
1353          */
1354         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
1355                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
1356
1357         if (set_pfc && pfc_params) {
1358                 /* Second COS */
1359                 if (pfc_params->cos1_pauseable)
1360                         reg_th_config = &config_val.pauseable_th;
1361                 else
1362                         reg_th_config = &config_val.non_pauseable_th;
1363                 /*
1364                  * The number of free blocks below which the pause signal to
1365                  * class 1 of MAC #n is asserted. n=0,1
1366                 **/
1367                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
1368                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
1369                        reg_th_config->pause_xoff);
1370                 /*
1371                  * The number of free blocks above which the pause signal to
1372                  * class 1 of MAC #n is de-asserted. n=0,1
1373                  */
1374                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
1375                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
1376                        reg_th_config->pause_xon);
1377                 /*
1378                  * The number of free blocks below which the full signal to
1379                  * class 1 of MAC #n is asserted. n=0,1
1380                  */
1381                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
1382                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
1383                        reg_th_config->full_xoff);
1384                 /*
1385                  * The number of free blocks above which the full signal to
1386                  * class 1 of MAC #n is de-asserted. n=0,1
1387                  */
1388                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
1389                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
1390                        reg_th_config->full_xon);
1391
1392
1393                 if (CHIP_IS_E3B0(bp)) {
1394                         /*Should be done by init tool */
1395                         /*
1396                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
1397                         * reset value
1398                         * 944
1399                         */
1400
1401                         /**
1402                          * The hysteresis on the guarantied buffer space for the Lb port
1403                          * before signaling XON.
1404                          **/
1405                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
1406
1407                         bnx2x_pfc_brb_get_e3b0_config_params(
1408                             params,
1409                             &e3b0_val,
1410                             pfc_params->cos0_pauseable,
1411                             pfc_params->cos1_pauseable);
1412                         /**
1413                          * The number of free blocks below which the full signal to the
1414                          * LB port is asserted.
1415                         */
1416                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
1417                                    e3b0_val.full_lb_xoff_th);
1418                         /**
1419                          * The number of free blocks above which the full signal to the
1420                          * LB port is de-asserted.
1421                         */
1422                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
1423                                    e3b0_val.full_lb_xon_threshold);
1424                         /**
1425                         * The number of blocks guarantied for the MAC #n port. n=0,1
1426                         */
1427
1428                         /*The number of blocks guarantied for the LB port.*/
1429                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
1430                                e3b0_val.lb_guarantied);
1431
1432                         /**
1433                          * The number of blocks guarantied for the MAC #n port.
1434                         */
1435                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
1436                                    2 * e3b0_val.mac_0_class_t_guarantied);
1437                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
1438                                    2 * e3b0_val.mac_1_class_t_guarantied);
1439                         /**
1440                          * The number of blocks guarantied for class #t in MAC0. t=0,1
1441                         */
1442                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
1443                                e3b0_val.mac_0_class_t_guarantied);
1444                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
1445                                e3b0_val.mac_0_class_t_guarantied);
1446                         /**
1447                          * The hysteresis on the guarantied buffer space for class in
1448                          * MAC0.  t=0,1
1449                         */
1450                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
1451                                e3b0_val.mac_0_class_t_guarantied_hyst);
1452                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
1453                                e3b0_val.mac_0_class_t_guarantied_hyst);
1454
1455                         /**
1456                          * The number of blocks guarantied for class #t in MAC1.t=0,1
1457                         */
1458                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
1459                                e3b0_val.mac_1_class_t_guarantied);
1460                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
1461                                e3b0_val.mac_1_class_t_guarantied);
1462                         /**
1463                          * The hysteresis on the guarantied buffer space for class #t
1464                         * in MAC1.  t=0,1
1465                         */
1466                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
1467                                e3b0_val.mac_1_class_t_guarantied_hyst);
1468                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
1469                                e3b0_val.mac_1_class_t_guarantied_hyst);
1470
1471             }
1472
1473         }
1474
1475         return bnx2x_status;
1476 }
1477
1478 /******************************************************************************
1479 * Description:
1480 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1481 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1482 ******************************************************************************/
1483 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
1484                                               u8 cos_entry,
1485                                               u32 priority_mask, u8 port)
1486 {
1487         u32 nig_reg_rx_priority_mask_add = 0;
1488
1489         switch (cos_entry) {
1490         case 0:
1491              nig_reg_rx_priority_mask_add = (port) ?
1492                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1493                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1494              break;
1495         case 1:
1496             nig_reg_rx_priority_mask_add = (port) ?
1497                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1498                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1499             break;
1500         case 2:
1501             nig_reg_rx_priority_mask_add = (port) ?
1502                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1503                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1504             break;
1505         case 3:
1506             if (port)
1507                 return -EINVAL;
1508             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1509             break;
1510         case 4:
1511             if (port)
1512                 return -EINVAL;
1513             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1514             break;
1515         case 5:
1516             if (port)
1517                 return -EINVAL;
1518             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1519             break;
1520         }
1521
1522         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
1523
1524         return 0;
1525 }
1526 static void bnx2x_update_pfc_nig(struct link_params *params,
1527                 struct link_vars *vars,
1528                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
1529 {
1530         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
1531         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
1532         u32 pkt_priority_to_cos = 0;
1533         struct bnx2x *bp = params->bp;
1534         u8 port = params->port;
1535
1536         int set_pfc = params->feature_config_flags &
1537                 FEATURE_CONFIG_PFC_ENABLED;
1538         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
1539
1540         /*
1541          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1542          * MAC control frames (that are not pause packets)
1543          * will be forwarded to the XCM.
1544          */
1545         xcm_mask = REG_RD(bp,
1546                                 port ? NIG_REG_LLH1_XCM_MASK :
1547                                 NIG_REG_LLH0_XCM_MASK);
1548         /*
1549          * nig params will override non PFC params, since it's possible to
1550          * do transition from PFC to SAFC
1551          */
1552         if (set_pfc) {
1553                 pause_enable = 0;
1554                 llfc_out_en = 0;
1555                 llfc_enable = 0;
1556                 if (CHIP_IS_E3(bp))
1557                         ppp_enable = 0;
1558                 else
1559                 ppp_enable = 1;
1560                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1561                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1562                 xcm0_out_en = 0;
1563                 p0_hwpfc_enable = 1;
1564         } else  {
1565                 if (nig_params) {
1566                         llfc_out_en = nig_params->llfc_out_en;
1567                         llfc_enable = nig_params->llfc_enable;
1568                         pause_enable = nig_params->pause_enable;
1569                 } else  /*defaul non PFC mode - PAUSE */
1570                         pause_enable = 1;
1571
1572                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1573                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1574                 xcm0_out_en = 1;
1575         }
1576
1577         if (CHIP_IS_E3(bp))
1578                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1579                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
1580         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
1581                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
1582         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
1583                NIG_REG_LLFC_ENABLE_0, llfc_enable);
1584         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
1585                NIG_REG_PAUSE_ENABLE_0, pause_enable);
1586
1587         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
1588                NIG_REG_PPP_ENABLE_0, ppp_enable);
1589
1590         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
1591                NIG_REG_LLH0_XCM_MASK, xcm_mask);
1592
1593         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
1594
1595         /* output enable for RX_XCM # IF */
1596         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
1597
1598         /* HW PFC TX enable */
1599         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
1600
1601         if (nig_params) {
1602                 u8 i = 0;
1603                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
1604
1605                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
1606                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
1607                 nig_params->rx_cos_priority_mask[i], port);
1608
1609                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
1610                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
1611                        nig_params->llfc_high_priority_classes);
1612
1613                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
1614                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
1615                        nig_params->llfc_low_priority_classes);
1616         }
1617         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
1618                NIG_REG_P0_PKT_PRIORITY_TO_COS,
1619                pkt_priority_to_cos);
1620 }
1621
1622 int bnx2x_update_pfc(struct link_params *params,
1623                       struct link_vars *vars,
1624                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
1625 {
1626         /*
1627          * The PFC and pause are orthogonal to one another, meaning when
1628          * PFC is enabled, the pause are disabled, and when PFC is
1629          * disabled, pause are set according to the pause result.
1630          */
1631         u32 val;
1632         struct bnx2x *bp = params->bp;
1633         int bnx2x_status = 0;
1634         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
1635         /* update NIG params */
1636         bnx2x_update_pfc_nig(params, vars, pfc_params);
1637
1638         /* update BRB params */
1639         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
1640         if (0 != bnx2x_status)
1641                 return bnx2x_status;
1642
1643         if (!vars->link_up)
1644                 return bnx2x_status;
1645
1646         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1647         if (CHIP_IS_E3(bp))
1648                 bnx2x_update_pfc_xmac(params, vars, 0);
1649         else {
1650                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
1651                 if ((val &
1652                     (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1653                     == 0) {
1654                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1655                         bnx2x_emac_enable(params, vars, 0);
1656                         return bnx2x_status;
1657                 }
1658
1659                 if (CHIP_IS_E2(bp))
1660                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
1661                 else
1662                         bnx2x_update_pfc_bmac1(params, vars);
1663
1664                 val = 0;
1665                 if ((params->feature_config_flags &
1666                      FEATURE_CONFIG_PFC_ENABLED) ||
1667                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1668                         val = 1;
1669                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1670         }
1671         return bnx2x_status;
1672 }
1673
1674
1675 static int bnx2x_bmac1_enable(struct link_params *params,
1676                               struct link_vars *vars,
1677                               u8 is_lb)
1678 {
1679         struct bnx2x *bp = params->bp;
1680         u8 port = params->port;
1681         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1682                                NIG_REG_INGRESS_BMAC0_MEM;
1683         u32 wb_data[2];
1684         u32 val;
1685
1686         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1687
1688         /* XGXS control */
1689         wb_data[0] = 0x3c;
1690         wb_data[1] = 0;
1691         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1692                     wb_data, 2);
1693
1694         /* tx MAC SA */
1695         wb_data[0] = ((params->mac_addr[2] << 24) |
1696                        (params->mac_addr[3] << 16) |
1697                        (params->mac_addr[4] << 8) |
1698                         params->mac_addr[5]);
1699         wb_data[1] = ((params->mac_addr[0] << 8) |
1700                         params->mac_addr[1]);
1701         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1702
1703         /* mac control */
1704         val = 0x3;
1705         if (is_lb) {
1706                 val |= 0x4;
1707                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1708         }
1709         wb_data[0] = val;
1710         wb_data[1] = 0;
1711         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1712
1713         /* set rx mtu */
1714         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1715         wb_data[1] = 0;
1716         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1717
1718         bnx2x_update_pfc_bmac1(params, vars);
1719
1720         /* set tx mtu */
1721         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1722         wb_data[1] = 0;
1723         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1724
1725         /* set cnt max size */
1726         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1727         wb_data[1] = 0;
1728         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1729
1730         /* configure safc */
1731         wb_data[0] = 0x1000200;
1732         wb_data[1] = 0;
1733         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1734                     wb_data, 2);
1735
1736         return 0;
1737 }
1738
1739 static int bnx2x_bmac2_enable(struct link_params *params,
1740                               struct link_vars *vars,
1741                               u8 is_lb)
1742 {
1743         struct bnx2x *bp = params->bp;
1744         u8 port = params->port;
1745         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1746                                NIG_REG_INGRESS_BMAC0_MEM;
1747         u32 wb_data[2];
1748
1749         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1750
1751         wb_data[0] = 0;
1752         wb_data[1] = 0;
1753         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1754         udelay(30);
1755
1756         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1757         wb_data[0] = 0x3c;
1758         wb_data[1] = 0;
1759         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1760                     wb_data, 2);
1761
1762         udelay(30);
1763
1764         /* tx MAC SA */
1765         wb_data[0] = ((params->mac_addr[2] << 24) |
1766                        (params->mac_addr[3] << 16) |
1767                        (params->mac_addr[4] << 8) |
1768                         params->mac_addr[5]);
1769         wb_data[1] = ((params->mac_addr[0] << 8) |
1770                         params->mac_addr[1]);
1771         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1772                     wb_data, 2);
1773
1774         udelay(30);
1775
1776         /* Configure SAFC */
1777         wb_data[0] = 0x1000200;
1778         wb_data[1] = 0;
1779         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1780                     wb_data, 2);
1781         udelay(30);
1782
1783         /* set rx mtu */
1784         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1785         wb_data[1] = 0;
1786         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1787         udelay(30);
1788
1789         /* set tx mtu */
1790         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1791         wb_data[1] = 0;
1792         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1793         udelay(30);
1794         /* set cnt max size */
1795         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1796         wb_data[1] = 0;
1797         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1798         udelay(30);
1799         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1800
1801         return 0;
1802 }
1803
1804 static int bnx2x_bmac_enable(struct link_params *params,
1805                              struct link_vars *vars,
1806                              u8 is_lb)
1807 {
1808         int rc = 0;
1809         u8 port = params->port;
1810         struct bnx2x *bp = params->bp;
1811         u32 val;
1812         /* reset and unreset the BigMac */
1813         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1814                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1815         msleep(1);
1816
1817         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1818                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1819
1820         /* enable access for bmac registers */
1821         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1822
1823         /* Enable BMAC according to BMAC type*/
1824         if (CHIP_IS_E2(bp))
1825                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1826         else
1827                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1828         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1829         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1830         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1831         val = 0;
1832         if ((params->feature_config_flags &
1833               FEATURE_CONFIG_PFC_ENABLED) ||
1834             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1835                 val = 1;
1836         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1837         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1838         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1839         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1840         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1841         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1842
1843         vars->mac_type = MAC_TYPE_BMAC;
1844         return rc;
1845 }
1846
1847
1848 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1849 {
1850         struct bnx2x *bp = params->bp;
1851
1852         REG_WR(bp, params->shmem_base +
1853                offsetof(struct shmem_region,
1854                         port_mb[params->port].link_status), link_status);
1855 }
1856
1857 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1858 {
1859         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1860                         NIG_REG_INGRESS_BMAC0_MEM;
1861         u32 wb_data[2];
1862         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1863
1864         /* Only if the bmac is out of reset */
1865         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1866                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1867             nig_bmac_enable) {
1868
1869                 if (CHIP_IS_E2(bp)) {
1870                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1871                         REG_RD_DMAE(bp, bmac_addr +
1872                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1873                                     wb_data, 2);
1874                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1875                         REG_WR_DMAE(bp, bmac_addr +
1876                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1877                                     wb_data, 2);
1878                 } else {
1879                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1880                         REG_RD_DMAE(bp, bmac_addr +
1881                                         BIGMAC_REGISTER_BMAC_CONTROL,
1882                                         wb_data, 2);
1883                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1884                         REG_WR_DMAE(bp, bmac_addr +
1885                                         BIGMAC_REGISTER_BMAC_CONTROL,
1886                                         wb_data, 2);
1887                 }
1888                 msleep(1);
1889         }
1890 }
1891
1892 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1893                             u32 line_speed)
1894 {
1895         struct bnx2x *bp = params->bp;
1896         u8 port = params->port;
1897         u32 init_crd, crd;
1898         u32 count = 1000;
1899
1900         /* disable port */
1901         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1902
1903         /* wait for init credit */
1904         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1905         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1906         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1907
1908         while ((init_crd != crd) && count) {
1909                 msleep(5);
1910
1911                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1912                 count--;
1913         }
1914         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1915         if (init_crd != crd) {
1916                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1917                           init_crd, crd);
1918                 return -EINVAL;
1919         }
1920
1921         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1922             line_speed == SPEED_10 ||
1923             line_speed == SPEED_100 ||
1924             line_speed == SPEED_1000 ||
1925             line_speed == SPEED_2500) {
1926                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1927                 /* update threshold */
1928                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1929                 /* update init credit */
1930                 init_crd = 778;         /* (800-18-4) */
1931
1932         } else {
1933                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1934                               ETH_OVREHEAD)/16;
1935                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1936                 /* update threshold */
1937                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1938                 /* update init credit */
1939                 switch (line_speed) {
1940                 case SPEED_10000:
1941                         init_crd = thresh + 553 - 22;
1942                         break;
1943
1944                 case SPEED_12000:
1945                         init_crd = thresh + 664 - 22;
1946                         break;
1947
1948                 case SPEED_13000:
1949                         init_crd = thresh + 742 - 22;
1950                         break;
1951
1952                 case SPEED_16000:
1953                         init_crd = thresh + 778 - 22;
1954                         break;
1955                 default:
1956                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1957                                   line_speed);
1958                         return -EINVAL;
1959                 }
1960         }
1961         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1962         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1963                  line_speed, init_crd);
1964
1965         /* probe the credit changes */
1966         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1967         msleep(5);
1968         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1969
1970         /* enable port */
1971         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1972         return 0;
1973 }
1974
1975 /**
1976  * bnx2x_get_emac_base - retrive emac base address
1977  *
1978  * @bp:                 driver handle
1979  * @mdc_mdio_access:    access type
1980  * @port:               port id
1981  *
1982  * This function selects the MDC/MDIO access (through emac0 or
1983  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1984  * phy has a default access mode, which could also be overridden
1985  * by nvram configuration. This parameter, whether this is the
1986  * default phy configuration, or the nvram overrun
1987  * configuration, is passed here as mdc_mdio_access and selects
1988  * the emac_base for the CL45 read/writes operations
1989  */
1990 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1991                                u32 mdc_mdio_access, u8 port)
1992 {
1993         u32 emac_base = 0;
1994         switch (mdc_mdio_access) {
1995         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1996                 break;
1997         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1998                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1999                         emac_base = GRCBASE_EMAC1;
2000                 else
2001                         emac_base = GRCBASE_EMAC0;
2002                 break;
2003         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2004                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2005                         emac_base = GRCBASE_EMAC0;
2006                 else
2007                         emac_base = GRCBASE_EMAC1;
2008                 break;
2009         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2010                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2011                 break;
2012         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2013                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2014                 break;
2015         default:
2016                 break;
2017         }
2018         return emac_base;
2019
2020 }
2021
2022 /******************************************************************/
2023 /*                      CL45 access functions                     */
2024 /******************************************************************/
2025 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2026                            u8 devad, u16 reg, u16 *ret_val)
2027 {
2028         u32 val;
2029         u16 i;
2030         int rc = 0;
2031
2032         /* address */
2033         val = ((phy->addr << 21) | (devad << 16) | reg |
2034                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2035                EMAC_MDIO_COMM_START_BUSY);
2036         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2037
2038         for (i = 0; i < 50; i++) {
2039                 udelay(10);
2040
2041                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2042                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2043                         udelay(5);
2044                         break;
2045                 }
2046         }
2047         if (val & EMAC_MDIO_COMM_START_BUSY) {
2048                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2049                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2050                 *ret_val = 0;
2051                 rc = -EFAULT;
2052         } else {
2053                 /* data */
2054                 val = ((phy->addr << 21) | (devad << 16) |
2055                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2056                        EMAC_MDIO_COMM_START_BUSY);
2057                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2058
2059                 for (i = 0; i < 50; i++) {
2060                         udelay(10);
2061
2062                         val = REG_RD(bp, phy->mdio_ctrl +
2063                                      EMAC_REG_EMAC_MDIO_COMM);
2064                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2065                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2066                                 break;
2067                         }
2068                 }
2069                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2070                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2071                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2072                         *ret_val = 0;
2073                         rc = -EFAULT;
2074                 }
2075         }
2076
2077         return rc;
2078 }
2079
2080 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2081                             u8 devad, u16 reg, u16 val)
2082 {
2083         u32 tmp;
2084         u8 i;
2085         int rc = 0;
2086
2087         /* address */
2088
2089         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2090                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2091                EMAC_MDIO_COMM_START_BUSY);
2092         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2093
2094         for (i = 0; i < 50; i++) {
2095                 udelay(10);
2096
2097                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2098                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2099                         udelay(5);
2100                         break;
2101                 }
2102         }
2103         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2104                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2105                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2106                 rc = -EFAULT;
2107
2108         } else {
2109                 /* data */
2110                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2111                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2112                        EMAC_MDIO_COMM_START_BUSY);
2113                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2114
2115                 for (i = 0; i < 50; i++) {
2116                         udelay(10);
2117
2118                         tmp = REG_RD(bp, phy->mdio_ctrl +
2119                                      EMAC_REG_EMAC_MDIO_COMM);
2120                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2121                                 udelay(5);
2122                                 break;
2123                         }
2124                 }
2125                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2126                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2127                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2128                         rc = -EFAULT;
2129                 }
2130         }
2131
2132
2133         return rc;
2134 }
2135
2136 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
2137                    u8 devad, u16 reg, u16 *ret_val)
2138 {
2139         u8 phy_index;
2140         /*
2141          * Probe for the phy according to the given phy_addr, and execute
2142          * the read request on it
2143          */
2144         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
2145                 if (params->phy[phy_index].addr == phy_addr) {
2146                         return bnx2x_cl45_read(params->bp,
2147                                                &params->phy[phy_index], devad,
2148                                                reg, ret_val);
2149                 }
2150         }
2151         return -EINVAL;
2152 }
2153
2154 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
2155                     u8 devad, u16 reg, u16 val)
2156 {
2157         u8 phy_index;
2158         /*
2159          * Probe for the phy according to the given phy_addr, and execute
2160          * the write request on it
2161          */
2162         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
2163                 if (params->phy[phy_index].addr == phy_addr) {
2164                         return bnx2x_cl45_write(params->bp,
2165                                                 &params->phy[phy_index], devad,
2166                                                 reg, val);
2167                 }
2168         }
2169         return -EINVAL;
2170 }
2171
2172 static void bnx2x_set_aer_mmd(struct link_params *params,
2173                               struct bnx2x_phy *phy)
2174 {
2175         u32 ser_lane;
2176         u16 offset, aer_val;
2177         struct bnx2x *bp = params->bp;
2178         ser_lane = ((params->lane_config &
2179                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2180                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2181
2182         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
2183                 (phy->addr + ser_lane) : 0;
2184
2185         if (CHIP_IS_E2(bp))
2186                 aer_val = 0x3800 + offset - 1;
2187         else
2188                 aer_val = 0x3800 + offset;
2189         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
2190         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
2191                           MDIO_AER_BLOCK_AER_REG, aer_val);
2192
2193 }
2194
2195 /******************************************************************/
2196 /*                      Internal phy section                      */
2197 /******************************************************************/
2198
2199 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
2200 {
2201         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2202
2203         /* Set Clause 22 */
2204         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
2205         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
2206         udelay(500);
2207         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
2208         udelay(500);
2209          /* Set Clause 45 */
2210         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
2211 }
2212
2213 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
2214 {
2215         u32 val;
2216
2217         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
2218
2219         val = SERDES_RESET_BITS << (port*16);
2220
2221         /* reset and unreset the SerDes/XGXS */
2222         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
2223         udelay(500);
2224         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
2225
2226         bnx2x_set_serdes_access(bp, port);
2227
2228         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
2229                DEFAULT_PHY_DEV_ADDR);
2230 }
2231
2232 static void bnx2x_xgxs_deassert(struct link_params *params)
2233 {
2234         struct bnx2x *bp = params->bp;
2235         u8 port;
2236         u32 val;
2237         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
2238         port = params->port;
2239
2240         val = XGXS_RESET_BITS << (port*16);
2241
2242         /* reset and unreset the SerDes/XGXS */
2243         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
2244         udelay(500);
2245         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
2246
2247         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
2248         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
2249                params->phy[INT_PHY].def_md_devad);
2250 }
2251
2252 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2253                                      struct link_params *params, u16 *ieee_fc)
2254 {
2255         struct bnx2x *bp = params->bp;
2256         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2257         /**
2258          * resolve pause mode and advertisement Please refer to Table
2259          * 28B-3 of the 802.3ab-1999 spec
2260          */
2261
2262         switch (phy->req_flow_ctrl) {
2263         case BNX2X_FLOW_CTRL_AUTO:
2264                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2265                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2266                 else
2267                         *ieee_fc |=
2268                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2269                 break;
2270
2271         case BNX2X_FLOW_CTRL_TX:
2272                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2273                 break;
2274
2275         case BNX2X_FLOW_CTRL_RX:
2276         case BNX2X_FLOW_CTRL_BOTH:
2277                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2278                 break;
2279
2280         case BNX2X_FLOW_CTRL_NONE:
2281         default:
2282                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2283                 break;
2284         }
2285         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2286 }
2287
2288 static void set_phy_vars(struct link_params *params,
2289                          struct link_vars *vars)
2290 {
2291         struct bnx2x *bp = params->bp;
2292         u8 actual_phy_idx, phy_index, link_cfg_idx;
2293         u8 phy_config_swapped = params->multi_phy_config &
2294                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
2295         for (phy_index = INT_PHY; phy_index < params->num_phys;
2296               phy_index++) {
2297                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
2298                 actual_phy_idx = phy_index;
2299                 if (phy_config_swapped) {
2300                         if (phy_index == EXT_PHY1)
2301                                 actual_phy_idx = EXT_PHY2;
2302                         else if (phy_index == EXT_PHY2)
2303                                 actual_phy_idx = EXT_PHY1;
2304                 }
2305                 params->phy[actual_phy_idx].req_flow_ctrl =
2306                         params->req_flow_ctrl[link_cfg_idx];
2307
2308                 params->phy[actual_phy_idx].req_line_speed =
2309                         params->req_line_speed[link_cfg_idx];
2310
2311                 params->phy[actual_phy_idx].speed_cap_mask =
2312                         params->speed_cap_mask[link_cfg_idx];
2313
2314                 params->phy[actual_phy_idx].req_duplex =
2315                         params->req_duplex[link_cfg_idx];
2316
2317                 if (params->req_line_speed[link_cfg_idx] ==
2318                     SPEED_AUTO_NEG)
2319                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2320
2321                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
2322                            " speed_cap_mask %x\n",
2323                            params->phy[actual_phy_idx].req_flow_ctrl,
2324                            params->phy[actual_phy_idx].req_line_speed,
2325                            params->phy[actual_phy_idx].speed_cap_mask);
2326         }
2327 }
2328
2329 static void bnx2x_ext_phy_set_pause(struct link_params *params,
2330                                     struct bnx2x_phy *phy,
2331                                     struct link_vars *vars)
2332 {
2333         u16 val;
2334         struct bnx2x *bp = params->bp;
2335         /* read modify write pause advertizing */
2336         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
2337
2338         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
2339
2340         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2341         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2342         if ((vars->ieee_fc &
2343             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2344             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2345                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2346         }
2347         if ((vars->ieee_fc &
2348             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2349             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2350                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
2351         }
2352         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
2353         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
2354 }
2355
2356 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2357 {                                               /*  LD      LP   */
2358         switch (pause_result) {                 /* ASYM P ASYM P */
2359         case 0xb:                               /*   1  0   1  1 */
2360                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2361                 break;
2362
2363         case 0xe:                               /*   1  1   1  0 */
2364                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2365                 break;
2366
2367         case 0x5:                               /*   0  1   0  1 */
2368         case 0x7:                               /*   0  1   1  1 */
2369         case 0xd:                               /*   1  1   0  1 */
2370         case 0xf:                               /*   1  1   1  1 */
2371                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2372                 break;
2373
2374         default:
2375                 break;
2376         }
2377         if (pause_result & (1<<0))
2378                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2379         if (pause_result & (1<<1))
2380                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2381 }
2382
2383 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
2384                                    struct link_params *params,
2385                                    struct link_vars *vars)
2386 {
2387         struct bnx2x *bp = params->bp;
2388         u16 ld_pause;           /* local */
2389         u16 lp_pause;           /* link partner */
2390         u16 pause_result;
2391         u8 ret = 0;
2392         /* read twice */
2393
2394         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2395
2396         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2397                 vars->flow_ctrl = phy->req_flow_ctrl;
2398         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2399                 vars->flow_ctrl = params->req_fc_auto_adv;
2400         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
2401                 ret = 1;
2402                 bnx2x_cl45_read(bp, phy,
2403                                 MDIO_AN_DEVAD,
2404                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
2405                 bnx2x_cl45_read(bp, phy,
2406                                 MDIO_AN_DEVAD,
2407                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
2408                 pause_result = (ld_pause &
2409                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
2410                 pause_result |= (lp_pause &
2411                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
2412                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
2413                    pause_result);
2414                 bnx2x_pause_resolve(vars, pause_result);
2415         }
2416         return ret;
2417 }
2418 void bnx2x_link_status_update(struct link_params *params,
2419                               struct link_vars *vars)
2420 {
2421         struct bnx2x *bp = params->bp;
2422         u8 link_10g_plus;
2423         u8 port = params->port;
2424         u32 sync_offset, media_types;
2425         /* Update PHY configuration */
2426         set_phy_vars(params, vars);
2427
2428         vars->link_status = REG_RD(bp, params->shmem_base +
2429                                    offsetof(struct shmem_region,
2430                                             port_mb[port].link_status));
2431
2432         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
2433         vars->phy_flags = PHY_XGXS_FLAG;
2434         if (vars->link_up) {
2435                 DP(NETIF_MSG_LINK, "phy link up\n");
2436
2437                 vars->phy_link_up = 1;
2438                 vars->duplex = DUPLEX_FULL;
2439                 switch (vars->link_status &
2440                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
2441                         case LINK_10THD:
2442                                 vars->duplex = DUPLEX_HALF;
2443                                 /* fall thru */
2444                         case LINK_10TFD:
2445                                 vars->line_speed = SPEED_10;
2446                                 break;
2447
2448                         case LINK_100TXHD:
2449                                 vars->duplex = DUPLEX_HALF;
2450                                 /* fall thru */
2451                         case LINK_100T4:
2452                         case LINK_100TXFD:
2453                                 vars->line_speed = SPEED_100;
2454                                 break;
2455
2456                         case LINK_1000THD:
2457                                 vars->duplex = DUPLEX_HALF;
2458                                 /* fall thru */
2459                         case LINK_1000TFD:
2460                                 vars->line_speed = SPEED_1000;
2461                                 break;
2462
2463                         case LINK_2500THD:
2464                                 vars->duplex = DUPLEX_HALF;
2465                                 /* fall thru */
2466                         case LINK_2500TFD:
2467                                 vars->line_speed = SPEED_2500;
2468                                 break;
2469
2470                         case LINK_10GTFD:
2471                                 vars->line_speed = SPEED_10000;
2472                                 break;
2473
2474                         default:
2475                                 break;
2476                 }
2477                 vars->flow_ctrl = 0;
2478                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
2479                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
2480
2481                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
2482                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
2483
2484                 if (!vars->flow_ctrl)
2485                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2486
2487                 if (vars->line_speed &&
2488                     ((vars->line_speed == SPEED_10) ||
2489                      (vars->line_speed == SPEED_100))) {
2490                         vars->phy_flags |= PHY_SGMII_FLAG;
2491                 } else {
2492                         vars->phy_flags &= ~PHY_SGMII_FLAG;
2493                 }
2494
2495                 /* anything 10 and over uses the bmac */
2496                 link_10g_plus = (vars->line_speed >= SPEED_10000);
2497
2498                 if (link_10g_plus) {
2499                         if (USES_WARPCORE(bp))
2500                                 vars->mac_type = MAC_TYPE_XMAC;
2501                         else
2502                         vars->mac_type = MAC_TYPE_BMAC;
2503                 } else {
2504                         if (USES_WARPCORE(bp))
2505                                 vars->mac_type = MAC_TYPE_UMAC;
2506                 else
2507                         vars->mac_type = MAC_TYPE_EMAC;
2508                 }
2509         } else { /* link down */
2510                 DP(NETIF_MSG_LINK, "phy link down\n");
2511
2512                 vars->phy_link_up = 0;
2513
2514                 vars->line_speed = 0;
2515                 vars->duplex = DUPLEX_FULL;
2516                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2517
2518                 /* indicate no mac active */
2519                 vars->mac_type = MAC_TYPE_NONE;
2520         }
2521
2522         /* Sync media type */
2523         sync_offset = params->shmem_base +
2524                         offsetof(struct shmem_region,
2525                                  dev_info.port_hw_config[port].media_type);
2526         media_types = REG_RD(bp, sync_offset);
2527
2528         params->phy[INT_PHY].media_type =
2529                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
2530                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
2531         params->phy[EXT_PHY1].media_type =
2532                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
2533                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
2534         params->phy[EXT_PHY2].media_type =
2535                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
2536                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
2537         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
2538
2539         /* Sync AEU offset */
2540         sync_offset = params->shmem_base +
2541                         offsetof(struct shmem_region,
2542                                  dev_info.port_hw_config[port].aeu_int_mask);
2543
2544         vars->aeu_int_mask = REG_RD(bp, sync_offset);
2545
2546         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
2547                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
2548         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
2549                  vars->line_speed, vars->duplex, vars->flow_ctrl);
2550 }
2551
2552
2553 static void bnx2x_set_master_ln(struct link_params *params,
2554                                 struct bnx2x_phy *phy)
2555 {
2556         struct bnx2x *bp = params->bp;
2557         u16 new_master_ln, ser_lane;
2558         ser_lane = ((params->lane_config &
2559                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2560                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2561
2562         /* set the master_ln for AN */
2563         CL22_RD_OVER_CL45(bp, phy,
2564                           MDIO_REG_BANK_XGXS_BLOCK2,
2565                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2566                           &new_master_ln);
2567
2568         CL22_WR_OVER_CL45(bp, phy,
2569                           MDIO_REG_BANK_XGXS_BLOCK2 ,
2570                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2571                           (new_master_ln | ser_lane));
2572 }
2573
2574 static int bnx2x_reset_unicore(struct link_params *params,
2575                                struct bnx2x_phy *phy,
2576                                u8 set_serdes)
2577 {
2578         struct bnx2x *bp = params->bp;
2579         u16 mii_control;
2580         u16 i;
2581         CL22_RD_OVER_CL45(bp, phy,
2582                           MDIO_REG_BANK_COMBO_IEEE0,
2583                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2584
2585         /* reset the unicore */
2586         CL22_WR_OVER_CL45(bp, phy,
2587                           MDIO_REG_BANK_COMBO_IEEE0,
2588                           MDIO_COMBO_IEEE0_MII_CONTROL,
2589                           (mii_control |
2590                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2591         if (set_serdes)
2592                 bnx2x_set_serdes_access(bp, params->port);
2593
2594         /* wait for the reset to self clear */
2595         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2596                 udelay(5);
2597
2598                 /* the reset erased the previous bank value */
2599                 CL22_RD_OVER_CL45(bp, phy,
2600                                   MDIO_REG_BANK_COMBO_IEEE0,
2601                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2602                                   &mii_control);
2603
2604                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2605                         udelay(5);
2606                         return 0;
2607                 }
2608         }
2609
2610         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
2611                               " Port %d\n",
2612                          params->port);
2613         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
2614         return -EINVAL;
2615
2616 }
2617
2618 static void bnx2x_set_swap_lanes(struct link_params *params,
2619                                  struct bnx2x_phy *phy)
2620 {
2621         struct bnx2x *bp = params->bp;
2622         /*
2623          *  Each two bits represents a lane number:
2624          *  No swap is 0123 => 0x1b no need to enable the swap
2625          */
2626         u16 ser_lane, rx_lane_swap, tx_lane_swap;
2627
2628         ser_lane = ((params->lane_config &
2629                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2630                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2631         rx_lane_swap = ((params->lane_config &
2632                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
2633                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
2634         tx_lane_swap = ((params->lane_config &
2635                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
2636                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
2637
2638         if (rx_lane_swap != 0x1b) {
2639                 CL22_WR_OVER_CL45(bp, phy,
2640                                   MDIO_REG_BANK_XGXS_BLOCK2,
2641                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2642                                   (rx_lane_swap |
2643                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2644                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2645         } else {
2646                 CL22_WR_OVER_CL45(bp, phy,
2647                                   MDIO_REG_BANK_XGXS_BLOCK2,
2648                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2649         }
2650
2651         if (tx_lane_swap != 0x1b) {
2652                 CL22_WR_OVER_CL45(bp, phy,
2653                                   MDIO_REG_BANK_XGXS_BLOCK2,
2654                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2655                                   (tx_lane_swap |
2656                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2657         } else {
2658                 CL22_WR_OVER_CL45(bp, phy,
2659                                   MDIO_REG_BANK_XGXS_BLOCK2,
2660                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2661         }
2662 }
2663
2664 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
2665                                          struct link_params *params)
2666 {
2667         struct bnx2x *bp = params->bp;
2668         u16 control2;
2669         CL22_RD_OVER_CL45(bp, phy,
2670                           MDIO_REG_BANK_SERDES_DIGITAL,
2671                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2672                           &control2);
2673         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2674                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2675         else
2676                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2677         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
2678                 phy->speed_cap_mask, control2);
2679         CL22_WR_OVER_CL45(bp, phy,
2680                           MDIO_REG_BANK_SERDES_DIGITAL,
2681                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2682                           control2);
2683
2684         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2685              (phy->speed_cap_mask &
2686                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
2687                 DP(NETIF_MSG_LINK, "XGXS\n");
2688
2689                 CL22_WR_OVER_CL45(bp, phy,
2690                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
2691                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2692                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2693
2694                 CL22_RD_OVER_CL45(bp, phy,
2695                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2696                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2697                                   &control2);
2698
2699
2700                 control2 |=
2701                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2702
2703                 CL22_WR_OVER_CL45(bp, phy,
2704                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2705                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2706                                   control2);
2707
2708                 /* Disable parallel detection of HiG */
2709                 CL22_WR_OVER_CL45(bp, phy,
2710                                   MDIO_REG_BANK_XGXS_BLOCK2,
2711                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2712                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2713                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2714         }
2715 }
2716
2717 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2718                               struct link_params *params,
2719                               struct link_vars *vars,
2720                               u8 enable_cl73)
2721 {
2722         struct bnx2x *bp = params->bp;
2723         u16 reg_val;
2724
2725         /* CL37 Autoneg */
2726         CL22_RD_OVER_CL45(bp, phy,
2727                           MDIO_REG_BANK_COMBO_IEEE0,
2728                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2729
2730         /* CL37 Autoneg Enabled */
2731         if (vars->line_speed == SPEED_AUTO_NEG)
2732                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2733         else /* CL37 Autoneg Disabled */
2734                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2735                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2736
2737         CL22_WR_OVER_CL45(bp, phy,
2738                           MDIO_REG_BANK_COMBO_IEEE0,
2739                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2740
2741         /* Enable/Disable Autodetection */
2742
2743         CL22_RD_OVER_CL45(bp, phy,
2744                           MDIO_REG_BANK_SERDES_DIGITAL,
2745                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2746         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
2747                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
2748         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
2749         if (vars->line_speed == SPEED_AUTO_NEG)
2750                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2751         else
2752                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2753
2754         CL22_WR_OVER_CL45(bp, phy,
2755                           MDIO_REG_BANK_SERDES_DIGITAL,
2756                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2757
2758         /* Enable TetonII and BAM autoneg */
2759         CL22_RD_OVER_CL45(bp, phy,
2760                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2761                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2762                           &reg_val);
2763         if (vars->line_speed == SPEED_AUTO_NEG) {
2764                 /* Enable BAM aneg Mode and TetonII aneg Mode */
2765                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2766                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2767         } else {
2768                 /* TetonII and BAM Autoneg Disabled */
2769                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2770                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2771         }
2772         CL22_WR_OVER_CL45(bp, phy,
2773                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2774                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2775                           reg_val);
2776
2777         if (enable_cl73) {
2778                 /* Enable Cl73 FSM status bits */
2779                 CL22_WR_OVER_CL45(bp, phy,
2780                                   MDIO_REG_BANK_CL73_USERB0,
2781                                   MDIO_CL73_USERB0_CL73_UCTRL,
2782                                   0xe);
2783
2784                 /* Enable BAM Station Manager*/
2785                 CL22_WR_OVER_CL45(bp, phy,
2786                         MDIO_REG_BANK_CL73_USERB0,
2787                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2788                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2789                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2790                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2791
2792                 /* Advertise CL73 link speeds */
2793                 CL22_RD_OVER_CL45(bp, phy,
2794                                   MDIO_REG_BANK_CL73_IEEEB1,
2795                                   MDIO_CL73_IEEEB1_AN_ADV2,
2796                                   &reg_val);
2797                 if (phy->speed_cap_mask &
2798                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2799                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2800                 if (phy->speed_cap_mask &
2801                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2802                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2803
2804                 CL22_WR_OVER_CL45(bp, phy,
2805                                   MDIO_REG_BANK_CL73_IEEEB1,
2806                                   MDIO_CL73_IEEEB1_AN_ADV2,
2807                                   reg_val);
2808
2809                 /* CL73 Autoneg Enabled */
2810                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2811
2812         } else /* CL73 Autoneg Disabled */
2813                 reg_val = 0;
2814
2815         CL22_WR_OVER_CL45(bp, phy,
2816                           MDIO_REG_BANK_CL73_IEEEB0,
2817                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2818 }
2819
2820 /* program SerDes, forced speed */
2821 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2822                                  struct link_params *params,
2823                                  struct link_vars *vars)
2824 {
2825         struct bnx2x *bp = params->bp;
2826         u16 reg_val;
2827
2828         /* program duplex, disable autoneg and sgmii*/
2829         CL22_RD_OVER_CL45(bp, phy,
2830                           MDIO_REG_BANK_COMBO_IEEE0,
2831                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2832         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2833                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2834                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2835         if (phy->req_duplex == DUPLEX_FULL)
2836                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2837         CL22_WR_OVER_CL45(bp, phy,
2838                           MDIO_REG_BANK_COMBO_IEEE0,
2839                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2840
2841         /*
2842          * program speed
2843          *  - needed only if the speed is greater than 1G (2.5G or 10G)
2844          */
2845         CL22_RD_OVER_CL45(bp, phy,
2846                           MDIO_REG_BANK_SERDES_DIGITAL,
2847                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2848         /* clearing the speed value before setting the right speed */
2849         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2850
2851         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2852                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2853
2854         if (!((vars->line_speed == SPEED_1000) ||
2855               (vars->line_speed == SPEED_100) ||
2856               (vars->line_speed == SPEED_10))) {
2857
2858                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2859                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2860                 if (vars->line_speed == SPEED_10000)
2861                         reg_val |=
2862                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2863                 if (vars->line_speed == SPEED_13000)
2864                         reg_val |=
2865                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2866         }
2867
2868         CL22_WR_OVER_CL45(bp, phy,
2869                           MDIO_REG_BANK_SERDES_DIGITAL,
2870                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
2871
2872 }
2873
2874 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
2875                                               struct link_params *params)
2876 {
2877         struct bnx2x *bp = params->bp;
2878         u16 val = 0;
2879
2880         /* configure the 48 bits for BAM AN */
2881
2882         /* set extended capabilities */
2883         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2884                 val |= MDIO_OVER_1G_UP1_2_5G;
2885         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2886                 val |= MDIO_OVER_1G_UP1_10G;
2887         CL22_WR_OVER_CL45(bp, phy,
2888                           MDIO_REG_BANK_OVER_1G,
2889                           MDIO_OVER_1G_UP1, val);
2890
2891         CL22_WR_OVER_CL45(bp, phy,
2892                           MDIO_REG_BANK_OVER_1G,
2893                           MDIO_OVER_1G_UP3, 0x400);
2894 }
2895
2896 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
2897                                               struct link_params *params,
2898                                               u16 ieee_fc)
2899 {
2900         struct bnx2x *bp = params->bp;
2901         u16 val;
2902         /* for AN, we are always publishing full duplex */
2903
2904         CL22_WR_OVER_CL45(bp, phy,
2905                           MDIO_REG_BANK_COMBO_IEEE0,
2906                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2907         CL22_RD_OVER_CL45(bp, phy,
2908                           MDIO_REG_BANK_CL73_IEEEB1,
2909                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
2910         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2911         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2912         CL22_WR_OVER_CL45(bp, phy,
2913                           MDIO_REG_BANK_CL73_IEEEB1,
2914                           MDIO_CL73_IEEEB1_AN_ADV1, val);
2915 }
2916
2917 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2918                                   struct link_params *params,
2919                                   u8 enable_cl73)
2920 {
2921         struct bnx2x *bp = params->bp;
2922         u16 mii_control;
2923
2924         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2925         /* Enable and restart BAM/CL37 aneg */
2926
2927         if (enable_cl73) {
2928                 CL22_RD_OVER_CL45(bp, phy,
2929                                   MDIO_REG_BANK_CL73_IEEEB0,
2930                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2931                                   &mii_control);
2932
2933                 CL22_WR_OVER_CL45(bp, phy,
2934                                   MDIO_REG_BANK_CL73_IEEEB0,
2935                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2936                                   (mii_control |
2937                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2938                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2939         } else {
2940
2941                 CL22_RD_OVER_CL45(bp, phy,
2942                                   MDIO_REG_BANK_COMBO_IEEE0,
2943                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2944                                   &mii_control);
2945                 DP(NETIF_MSG_LINK,
2946                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2947                          mii_control);
2948                 CL22_WR_OVER_CL45(bp, phy,
2949                                   MDIO_REG_BANK_COMBO_IEEE0,
2950                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2951                                   (mii_control |
2952                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2953                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2954         }
2955 }
2956
2957 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2958                                            struct link_params *params,
2959                                            struct link_vars *vars)
2960 {
2961         struct bnx2x *bp = params->bp;
2962         u16 control1;
2963
2964         /* in SGMII mode, the unicore is always slave */
2965
2966         CL22_RD_OVER_CL45(bp, phy,
2967                           MDIO_REG_BANK_SERDES_DIGITAL,
2968                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2969                           &control1);
2970         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2971         /* set sgmii mode (and not fiber) */
2972         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2973                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2974                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2975         CL22_WR_OVER_CL45(bp, phy,
2976                           MDIO_REG_BANK_SERDES_DIGITAL,
2977                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2978                           control1);
2979
2980         /* if forced speed */
2981         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2982                 /* set speed, disable autoneg */
2983                 u16 mii_control;
2984
2985                 CL22_RD_OVER_CL45(bp, phy,
2986                                   MDIO_REG_BANK_COMBO_IEEE0,
2987                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2988                                   &mii_control);
2989                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2990                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2991                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2992
2993                 switch (vars->line_speed) {
2994                 case SPEED_100:
2995                         mii_control |=
2996                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2997                         break;
2998                 case SPEED_1000:
2999                         mii_control |=
3000                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
3001                         break;
3002                 case SPEED_10:
3003                         /* there is nothing to set for 10M */
3004                         break;
3005                 default:
3006                         /* invalid speed for SGMII */
3007                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
3008                                   vars->line_speed);
3009                         break;
3010                 }
3011
3012                 /* setting the full duplex */
3013                 if (phy->req_duplex == DUPLEX_FULL)
3014                         mii_control |=
3015                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
3016                 CL22_WR_OVER_CL45(bp, phy,
3017                                   MDIO_REG_BANK_COMBO_IEEE0,
3018                                   MDIO_COMBO_IEEE0_MII_CONTROL,
3019                                   mii_control);
3020
3021         } else { /* AN mode */
3022                 /* enable and restart AN */
3023                 bnx2x_restart_autoneg(phy, params, 0);
3024         }
3025 }
3026
3027
3028 /*
3029  * link management
3030  */
3031
3032 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
3033                                              struct link_params *params)
3034 {
3035         struct bnx2x *bp = params->bp;
3036         u16 pd_10g, status2_1000x;
3037         if (phy->req_line_speed != SPEED_AUTO_NEG)
3038                 return 0;
3039         CL22_RD_OVER_CL45(bp, phy,
3040                           MDIO_REG_BANK_SERDES_DIGITAL,
3041                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
3042                           &status2_1000x);
3043         CL22_RD_OVER_CL45(bp, phy,
3044                           MDIO_REG_BANK_SERDES_DIGITAL,
3045                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
3046                           &status2_1000x);
3047         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
3048                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
3049                          params->port);
3050                 return 1;
3051         }
3052
3053         CL22_RD_OVER_CL45(bp, phy,
3054                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
3055                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
3056                           &pd_10g);
3057
3058         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
3059                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
3060                          params->port);
3061                 return 1;
3062         }
3063         return 0;
3064 }
3065
3066 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
3067                                     struct link_params *params,
3068                                     struct link_vars *vars,
3069                                     u32 gp_status)
3070 {
3071         struct bnx2x *bp = params->bp;
3072         u16 ld_pause;   /* local driver */
3073         u16 lp_pause;   /* link partner */
3074         u16 pause_result;
3075
3076         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3077
3078         /* resolve from gp_status in case of AN complete and not sgmii */
3079         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3080                 vars->flow_ctrl = phy->req_flow_ctrl;
3081         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3082                 vars->flow_ctrl = params->req_fc_auto_adv;
3083         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
3084                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
3085                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
3086                         vars->flow_ctrl = params->req_fc_auto_adv;
3087                         return;
3088                 }
3089                 if ((gp_status &
3090                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
3091                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
3092                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
3093                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
3094
3095                         CL22_RD_OVER_CL45(bp, phy,
3096                                           MDIO_REG_BANK_CL73_IEEEB1,
3097                                           MDIO_CL73_IEEEB1_AN_ADV1,
3098                                           &ld_pause);
3099                         CL22_RD_OVER_CL45(bp, phy,
3100                                           MDIO_REG_BANK_CL73_IEEEB1,
3101                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
3102                                           &lp_pause);
3103                         pause_result = (ld_pause &
3104                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
3105                                         >> 8;
3106                         pause_result |= (lp_pause &
3107                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
3108                                         >> 10;
3109                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
3110                                  pause_result);
3111                 } else {
3112                         CL22_RD_OVER_CL45(bp, phy,
3113                                           MDIO_REG_BANK_COMBO_IEEE0,
3114                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
3115                                           &ld_pause);
3116                         CL22_RD_OVER_CL45(bp, phy,
3117                                 MDIO_REG_BANK_COMBO_IEEE0,
3118                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
3119                                 &lp_pause);
3120                         pause_result = (ld_pause &
3121                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
3122                         pause_result |= (lp_pause &
3123                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
3124                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
3125                                  pause_result);
3126                 }
3127                 bnx2x_pause_resolve(vars, pause_result);
3128         }
3129         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
3130 }
3131
3132 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
3133                                          struct link_params *params)
3134 {
3135         struct bnx2x *bp = params->bp;
3136         u16 rx_status, ustat_val, cl37_fsm_received;
3137         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
3138         /* Step 1: Make sure signal is detected */
3139         CL22_RD_OVER_CL45(bp, phy,
3140                           MDIO_REG_BANK_RX0,
3141                           MDIO_RX0_RX_STATUS,
3142                           &rx_status);
3143         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
3144             (MDIO_RX0_RX_STATUS_SIGDET)) {
3145                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
3146                              "rx_status(0x80b0) = 0x%x\n", rx_status);
3147                 CL22_WR_OVER_CL45(bp, phy,
3148                                   MDIO_REG_BANK_CL73_IEEEB0,
3149                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3150                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
3151                 return;
3152         }
3153         /* Step 2: Check CL73 state machine */
3154         CL22_RD_OVER_CL45(bp, phy,
3155                           MDIO_REG_BANK_CL73_USERB0,
3156                           MDIO_CL73_USERB0_CL73_USTAT1,
3157                           &ustat_val);
3158         if ((ustat_val &
3159              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
3160               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
3161             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
3162               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
3163                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
3164                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
3165                 return;
3166         }
3167         /*
3168          * Step 3: Check CL37 Message Pages received to indicate LP
3169          * supports only CL37
3170          */
3171         CL22_RD_OVER_CL45(bp, phy,
3172                           MDIO_REG_BANK_REMOTE_PHY,
3173                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
3174                           &cl37_fsm_received);
3175         if ((cl37_fsm_received &
3176              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
3177              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
3178             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
3179               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
3180                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
3181                              "misc_rx_status(0x8330) = 0x%x\n",
3182                          cl37_fsm_received);
3183                 return;
3184         }
3185         /*
3186          * The combined cl37/cl73 fsm state information indicating that
3187          * we are connected to a device which does not support cl73, but
3188          * does support cl37 BAM. In this case we disable cl73 and
3189          * restart cl37 auto-neg
3190          */
3191
3192         /* Disable CL73 */
3193         CL22_WR_OVER_CL45(bp, phy,
3194                           MDIO_REG_BANK_CL73_IEEEB0,
3195                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3196                           0);
3197         /* Restart CL37 autoneg */
3198         bnx2x_restart_autoneg(phy, params, 0);
3199         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
3200 }
3201
3202 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
3203                                   struct link_params *params,
3204                                   struct link_vars *vars,
3205                                   u32 gp_status)
3206 {
3207         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
3208                 vars->link_status |=
3209                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3210
3211         if (bnx2x_direct_parallel_detect_used(phy, params))
3212                 vars->link_status |=
3213                         LINK_STATUS_PARALLEL_DETECTION_USED;
3214 }
3215
3216 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
3217                                       struct link_params *params,
3218                                       struct link_vars *vars)
3219 {
3220         struct bnx2x *bp = params->bp;
3221         u16 new_line_speed, gp_status;
3222         int rc = 0;
3223
3224         /* Read gp_status */
3225         CL22_RD_OVER_CL45(bp, phy,
3226                           MDIO_REG_BANK_GP_STATUS,
3227                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3228                           &gp_status);
3229
3230         if (phy->req_line_speed == SPEED_AUTO_NEG)
3231                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3232         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
3233                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
3234                          gp_status);
3235
3236                 vars->phy_link_up = 1;
3237                 vars->link_status |= LINK_STATUS_LINK_UP;
3238
3239                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
3240                         vars->duplex = DUPLEX_FULL;
3241                 else
3242                         vars->duplex = DUPLEX_HALF;
3243
3244                 if (SINGLE_MEDIA_DIRECT(params)) {
3245                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
3246                         if (phy->req_line_speed == SPEED_AUTO_NEG)
3247                                 bnx2x_xgxs_an_resolve(phy, params, vars,
3248                                                       gp_status);
3249                 }
3250
3251                 switch (gp_status & GP_STATUS_SPEED_MASK) {
3252                 case GP_STATUS_10M:
3253                         new_line_speed = SPEED_10;
3254                         if (vars->duplex == DUPLEX_FULL)
3255                                 vars->link_status |= LINK_10TFD;
3256                         else
3257                                 vars->link_status |= LINK_10THD;
3258                         break;
3259
3260                 case GP_STATUS_100M:
3261                         new_line_speed = SPEED_100;
3262                         if (vars->duplex == DUPLEX_FULL)
3263                                 vars->link_status |= LINK_100TXFD;
3264                         else
3265                                 vars->link_status |= LINK_100TXHD;
3266                         break;
3267
3268                 case GP_STATUS_1G:
3269                 case GP_STATUS_1G_KX:
3270                         new_line_speed = SPEED_1000;
3271                         if (vars->duplex == DUPLEX_FULL)
3272                                 vars->link_status |= LINK_1000TFD;
3273                         else
3274                                 vars->link_status |= LINK_1000THD;
3275                         break;
3276
3277                 case GP_STATUS_2_5G:
3278                         new_line_speed = SPEED_2500;
3279                         if (vars->duplex == DUPLEX_FULL)
3280                                 vars->link_status |= LINK_2500TFD;
3281                         else
3282                                 vars->link_status |= LINK_2500THD;
3283                         break;
3284
3285                 case GP_STATUS_5G:
3286                 case GP_STATUS_6G:
3287                         DP(NETIF_MSG_LINK,
3288                                  "link speed unsupported  gp_status 0x%x\n",
3289                                   gp_status);
3290                         return -EINVAL;
3291
3292                 case GP_STATUS_10G_KX4:
3293                 case GP_STATUS_10G_HIG:
3294                 case GP_STATUS_10G_CX4:
3295                         new_line_speed = SPEED_10000;
3296                         vars->link_status |= LINK_10GTFD;
3297                         break;
3298
3299                 default:
3300                         DP(NETIF_MSG_LINK,
3301                                   "link speed unsupported gp_status 0x%x\n",
3302                                   gp_status);
3303                         return -EINVAL;
3304                 }
3305
3306                 vars->line_speed = new_line_speed;
3307
3308         } else { /* link_down */
3309                 DP(NETIF_MSG_LINK, "phy link down\n");
3310
3311                 vars->phy_link_up = 0;
3312
3313                 vars->duplex = DUPLEX_FULL;
3314                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3315                 vars->mac_type = MAC_TYPE_NONE;
3316
3317                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
3318                     SINGLE_MEDIA_DIRECT(params)) {
3319                         /* Check signal is detected */
3320                         bnx2x_check_fallback_to_cl37(phy, params);
3321                 }
3322         }
3323
3324         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
3325                  gp_status, vars->phy_link_up, vars->line_speed);
3326         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
3327                    vars->duplex, vars->flow_ctrl, vars->link_status);
3328         return rc;
3329 }
3330
3331 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
3332 {
3333         struct bnx2x *bp = params->bp;
3334         struct bnx2x_phy *phy = &params->phy[INT_PHY];
3335         u16 lp_up2;
3336         u16 tx_driver;
3337         u16 bank;
3338
3339         /* read precomp */
3340         CL22_RD_OVER_CL45(bp, phy,
3341                           MDIO_REG_BANK_OVER_1G,
3342                           MDIO_OVER_1G_LP_UP2, &lp_up2);
3343
3344         /* bits [10:7] at lp_up2, positioned at [15:12] */
3345         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
3346                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
3347                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
3348
3349         if (lp_up2 == 0)
3350                 return;
3351
3352         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
3353               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
3354                 CL22_RD_OVER_CL45(bp, phy,
3355                                   bank,
3356                                   MDIO_TX0_TX_DRIVER, &tx_driver);
3357
3358                 /* replace tx_driver bits [15:12] */
3359                 if (lp_up2 !=
3360                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
3361                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
3362                         tx_driver |= lp_up2;
3363                         CL22_WR_OVER_CL45(bp, phy,
3364                                           bank,
3365                                           MDIO_TX0_TX_DRIVER, tx_driver);
3366                 }
3367         }
3368 }
3369
3370 static int bnx2x_emac_program(struct link_params *params,
3371                               struct link_vars *vars)
3372 {
3373         struct bnx2x *bp = params->bp;
3374         u8 port = params->port;
3375         u16 mode = 0;
3376
3377         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
3378         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
3379                        EMAC_REG_EMAC_MODE,
3380                        (EMAC_MODE_25G_MODE |
3381                         EMAC_MODE_PORT_MII_10M |
3382                         EMAC_MODE_HALF_DUPLEX));
3383         switch (vars->line_speed) {
3384         case SPEED_10:
3385                 mode |= EMAC_MODE_PORT_MII_10M;
3386                 break;
3387
3388         case SPEED_100:
3389                 mode |= EMAC_MODE_PORT_MII;
3390                 break;
3391
3392         case SPEED_1000:
3393                 mode |= EMAC_MODE_PORT_GMII;
3394                 break;
3395
3396         case SPEED_2500:
3397                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
3398                 break;
3399
3400         default:
3401                 /* 10G not valid for EMAC */
3402                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
3403                            vars->line_speed);
3404                 return -EINVAL;
3405         }
3406
3407         if (vars->duplex == DUPLEX_HALF)
3408                 mode |= EMAC_MODE_HALF_DUPLEX;
3409         bnx2x_bits_en(bp,
3410                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
3411                       mode);
3412
3413         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
3414         return 0;
3415 }
3416
3417 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
3418                                   struct link_params *params)
3419 {
3420
3421         u16 bank, i = 0;
3422         struct bnx2x *bp = params->bp;
3423
3424         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3425               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3426                         CL22_WR_OVER_CL45(bp, phy,
3427                                           bank,
3428                                           MDIO_RX0_RX_EQ_BOOST,
3429                                           phy->rx_preemphasis[i]);
3430         }
3431
3432         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3433                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3434                         CL22_WR_OVER_CL45(bp, phy,
3435                                           bank,
3436                                           MDIO_TX0_TX_DRIVER,
3437                                           phy->tx_preemphasis[i]);
3438         }
3439 }
3440
3441 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
3442                                    struct link_params *params,
3443                                    struct link_vars *vars)
3444 {
3445         struct bnx2x *bp = params->bp;
3446         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
3447                           (params->loopback_mode == LOOPBACK_XGXS));
3448         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3449                 if (SINGLE_MEDIA_DIRECT(params) &&
3450                     (params->feature_config_flags &
3451                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3452                         bnx2x_set_preemphasis(phy, params);
3453
3454                 /* forced speed requested? */
3455                 if (vars->line_speed != SPEED_AUTO_NEG ||
3456                     (SINGLE_MEDIA_DIRECT(params) &&
3457                      params->loopback_mode == LOOPBACK_EXT)) {
3458                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3459
3460                         /* disable autoneg */
3461                         bnx2x_set_autoneg(phy, params, vars, 0);
3462
3463                         /* program speed and duplex */
3464                         bnx2x_program_serdes(phy, params, vars);
3465
3466                 } else { /* AN_mode */
3467                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3468
3469                         /* AN enabled */
3470                         bnx2x_set_brcm_cl37_advertisement(phy, params);
3471
3472                         /* program duplex & pause advertisement (for aneg) */
3473                         bnx2x_set_ieee_aneg_advertisement(phy, params,
3474                                                           vars->ieee_fc);
3475
3476                         /* enable autoneg */
3477                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
3478
3479                         /* enable and restart AN */
3480                         bnx2x_restart_autoneg(phy, params, enable_cl73);
3481                 }
3482
3483         } else { /* SGMII mode */
3484                 DP(NETIF_MSG_LINK, "SGMII\n");
3485
3486                 bnx2x_initialize_sgmii_process(phy, params, vars);
3487         }
3488 }
3489
3490 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
3491                           struct link_params *params,
3492                           struct link_vars *vars)
3493 {
3494         int rc;
3495         vars->phy_flags |= PHY_XGXS_FLAG;
3496         if ((phy->req_line_speed &&
3497              ((phy->req_line_speed == SPEED_100) ||
3498               (phy->req_line_speed == SPEED_10))) ||
3499             (!phy->req_line_speed &&
3500              (phy->speed_cap_mask >=
3501               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
3502              (phy->speed_cap_mask <
3503               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3504             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
3505                 vars->phy_flags |= PHY_SGMII_FLAG;
3506         else
3507                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3508
3509         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3510         bnx2x_set_aer_mmd(params, phy);
3511         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
3512                 bnx2x_set_master_ln(params, phy);
3513
3514         rc = bnx2x_reset_unicore(params, phy, 0);
3515         /* reset the SerDes and wait for reset bit return low */
3516         if (rc != 0)
3517                 return rc;
3518
3519         bnx2x_set_aer_mmd(params, phy);
3520         /* setting the masterLn_def again after the reset */
3521         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
3522                 bnx2x_set_master_ln(params, phy);
3523                 bnx2x_set_swap_lanes(params, phy);
3524         }
3525
3526         return rc;
3527 }
3528
3529 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
3530                                      struct bnx2x_phy *phy,
3531                                      struct link_params *params)
3532 {
3533         u16 cnt, ctrl;
3534         /* Wait for soft reset to get cleared up to 1 sec */
3535         for (cnt = 0; cnt < 1000; cnt++) {
3536                 bnx2x_cl45_read(bp, phy,
3537                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
3538                 if (!(ctrl & (1<<15)))
3539                         break;
3540                 msleep(1);
3541         }
3542
3543         if (cnt == 1000)
3544                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
3545                                       " Port %d\n",
3546                          params->port);
3547         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3548         return cnt;
3549 }
3550
3551 static void bnx2x_link_int_enable(struct link_params *params)
3552 {
3553         u8 port = params->port;
3554         u32 mask;
3555         struct bnx2x *bp = params->bp;
3556
3557         /* Setting the status to report on link up for either XGXS or SerDes */
3558         if (params->switch_cfg == SWITCH_CFG_10G) {
3559                 mask = (NIG_MASK_XGXS0_LINK10G |
3560                         NIG_MASK_XGXS0_LINK_STATUS);
3561                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3562                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
3563                         params->phy[INT_PHY].type !=
3564                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
3565                         mask |= NIG_MASK_MI_INT;
3566                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
3567                 }
3568
3569         } else { /* SerDes */
3570                 mask = NIG_MASK_SERDES0_LINK_STATUS;
3571                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3572                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
3573                         params->phy[INT_PHY].type !=
3574                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
3575                         mask |= NIG_MASK_MI_INT;
3576                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
3577                 }
3578         }
3579         bnx2x_bits_en(bp,
3580                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3581                       mask);
3582
3583         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
3584                  (params->switch_cfg == SWITCH_CFG_10G),
3585                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3586         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
3587                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3588                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3589                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
3590         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3591            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3592            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3593 }
3594
3595 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
3596                                      u8 exp_mi_int)
3597 {
3598         u32 latch_status = 0;
3599
3600         /*
3601          * Disable the MI INT ( external phy int ) by writing 1 to the
3602          * status register. Link down indication is high-active-signal,
3603          * so in this case we need to write the status to clear the XOR
3604          */
3605         /* Read Latched signals */
3606         latch_status = REG_RD(bp,
3607                                     NIG_REG_LATCH_STATUS_0 + port*8);
3608         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
3609         /* Handle only those with latched-signal=up.*/
3610         if (exp_mi_int)
3611                 bnx2x_bits_en(bp,
3612                               NIG_REG_STATUS_INTERRUPT_PORT0
3613                               + port*4,
3614                               NIG_STATUS_EMAC0_MI_INT);
3615         else
3616                 bnx2x_bits_dis(bp,
3617                                NIG_REG_STATUS_INTERRUPT_PORT0
3618                                + port*4,
3619                                NIG_STATUS_EMAC0_MI_INT);
3620
3621         if (latch_status & 1) {
3622
3623                 /* For all latched-signal=up : Re-Arm Latch signals */
3624                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
3625                        (latch_status & 0xfffe) | (latch_status & 1));
3626         }
3627         /* For all latched-signal=up,Write original_signal to status */
3628 }
3629
3630 static void bnx2x_link_int_ack(struct link_params *params,
3631                                struct link_vars *vars, u8 is_10g)
3632 {
3633         struct bnx2x *bp = params->bp;
3634         u8 port = params->port;
3635
3636         /*
3637          * First reset all status we assume only one line will be
3638          * change at a time
3639          */
3640         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3641                        (NIG_STATUS_XGXS0_LINK10G |
3642                         NIG_STATUS_XGXS0_LINK_STATUS |
3643                         NIG_STATUS_SERDES0_LINK_STATUS));
3644         if (vars->phy_link_up) {
3645                 if (is_10g) {
3646                         /*
3647                          * Disable the 10G link interrupt by writing 1 to the
3648                          * status register
3649                          */
3650                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
3651                         bnx2x_bits_en(bp,
3652                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3653                                       NIG_STATUS_XGXS0_LINK10G);
3654
3655                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
3656                         /*
3657                          * Disable the link interrupt by writing 1 to the
3658                          * relevant lane in the status register
3659                          */
3660                         u32 ser_lane = ((params->lane_config &
3661                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3662                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3663
3664                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
3665                                  vars->line_speed);
3666                         bnx2x_bits_en(bp,
3667                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3668                                       ((1 << ser_lane) <<
3669                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
3670
3671                 } else { /* SerDes */
3672                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
3673                         /*
3674                          * Disable the link interrupt by writing 1 to the status
3675                          * register
3676                          */
3677                         bnx2x_bits_en(bp,
3678                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3679                                       NIG_STATUS_SERDES0_LINK_STATUS);
3680                 }
3681
3682         }
3683 }
3684
3685 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
3686 {
3687         u8 *str_ptr = str;
3688         u32 mask = 0xf0000000;
3689         u8 shift = 8*4;
3690         u8 digit;
3691         u8 remove_leading_zeros = 1;
3692         if (*len < 10) {
3693                 /* Need more than 10chars for this format */
3694                 *str_ptr = '\0';
3695                 (*len)--;
3696                 return -EINVAL;
3697         }
3698         while (shift > 0) {
3699
3700                 shift -= 4;
3701                 digit = ((num & mask) >> shift);
3702                 if (digit == 0 && remove_leading_zeros) {
3703                         mask = mask >> 4;
3704                         continue;
3705                 } else if (digit < 0xa)
3706                         *str_ptr = digit + '0';
3707                 else
3708                         *str_ptr = digit - 0xa + 'a';
3709                 remove_leading_zeros = 0;
3710                 str_ptr++;
3711                 (*len)--;
3712                 mask = mask >> 4;
3713                 if (shift == 4*4) {
3714                         *str_ptr = '.';
3715                         str_ptr++;
3716                         (*len)--;
3717                         remove_leading_zeros = 1;
3718                 }
3719         }
3720         return 0;
3721 }
3722
3723
3724 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3725 {
3726         str[0] = '\0';
3727         (*len)--;
3728         return 0;
3729 }
3730
3731 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3732                                  u8 *version, u16 len)
3733 {
3734         struct bnx2x *bp;
3735         u32 spirom_ver = 0;
3736         int status = 0;
3737         u8 *ver_p = version;
3738         u16 remain_len = len;
3739         if (version == NULL || params == NULL)
3740                 return -EINVAL;
3741         bp = params->bp;
3742
3743         /* Extract first external phy*/
3744         version[0] = '\0';
3745         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3746
3747         if (params->phy[EXT_PHY1].format_fw_ver) {
3748                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3749                                                               ver_p,
3750                                                               &remain_len);
3751                 ver_p += (len - remain_len);
3752         }
3753         if ((params->num_phys == MAX_PHYS) &&
3754             (params->phy[EXT_PHY2].ver_addr != 0)) {
3755                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3756                 if (params->phy[EXT_PHY2].format_fw_ver) {
3757                         *ver_p = '/';
3758                         ver_p++;
3759                         remain_len--;
3760                         status |= params->phy[EXT_PHY2].format_fw_ver(
3761                                 spirom_ver,
3762                                 ver_p,
3763                                 &remain_len);
3764                         ver_p = version + (len - remain_len);
3765                 }
3766         }
3767         *ver_p = '\0';
3768         return status;
3769 }
3770
3771 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3772                                     struct link_params *params)
3773 {
3774         u8 port = params->port;
3775         struct bnx2x *bp = params->bp;
3776
3777         if (phy->req_line_speed != SPEED_1000) {
3778                 u32 md_devad;
3779
3780                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3781
3782                 /* change the uni_phy_addr in the nig */
3783                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3784                                        port*0x18));
3785
3786                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3787
3788                 bnx2x_cl45_write(bp, phy,
3789                                  5,
3790                                  (MDIO_REG_BANK_AER_BLOCK +
3791                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
3792                                  0x2800);
3793
3794                 bnx2x_cl45_write(bp, phy,
3795                                  5,
3796                                  (MDIO_REG_BANK_CL73_IEEEB0 +
3797                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3798                                  0x6041);
3799                 msleep(200);
3800                 /* set aer mmd back */
3801                 bnx2x_set_aer_mmd(params, phy);
3802
3803                 /* and md_devad */
3804                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3805         } else {
3806                 u16 mii_ctrl;
3807                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3808                 bnx2x_cl45_read(bp, phy, 5,
3809                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3810                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3811                                 &mii_ctrl);
3812                 bnx2x_cl45_write(bp, phy, 5,
3813                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3814                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3815                                  mii_ctrl |
3816                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3817         }
3818 }
3819
3820 int bnx2x_set_led(struct link_params *params,
3821                   struct link_vars *vars, u8 mode, u32 speed)
3822 {
3823         u8 port = params->port;
3824         u16 hw_led_mode = params->hw_led_mode;
3825         int rc = 0;
3826         u8 phy_idx;
3827         u32 tmp;
3828         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3829         struct bnx2x *bp = params->bp;
3830         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3831         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3832                  speed, hw_led_mode);
3833         /* In case */
3834         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3835                 if (params->phy[phy_idx].set_link_led) {
3836                         params->phy[phy_idx].set_link_led(
3837                                 &params->phy[phy_idx], params, mode);
3838                 }
3839         }
3840
3841         switch (mode) {
3842         case LED_MODE_FRONT_PANEL_OFF:
3843         case LED_MODE_OFF:
3844                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3845                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3846                        SHARED_HW_CFG_LED_MAC1);
3847
3848                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3849                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3850                 break;
3851
3852         case LED_MODE_OPER:
3853                 /*
3854                  * For all other phys, OPER mode is same as ON, so in case
3855                  * link is down, do nothing
3856                  */
3857                 if (!vars->link_up)
3858                         break;
3859         case LED_MODE_ON:
3860                 if (((params->phy[EXT_PHY1].type ==
3861                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3862                          (params->phy[EXT_PHY1].type ==
3863                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
3864                     CHIP_IS_E2(bp) && params->num_phys == 2) {
3865                         /*
3866                          * This is a work-around for E2+8727 Configurations
3867                          */
3868                         if (mode == LED_MODE_ON ||
3869                                 speed == SPEED_10000){
3870                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3871                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3872
3873                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3874                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3875                                         (tmp | EMAC_LED_OVERRIDE));
3876                                 return rc;
3877                         }
3878                 } else if (SINGLE_MEDIA_DIRECT(params)) {
3879                         /*
3880                          * This is a work-around for HW issue found when link
3881                          * is up in CL73
3882                          */
3883                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3884                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3885                 } else {
3886                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3887                 }
3888
3889                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3890                 /* Set blinking rate to ~15.9Hz */
3891                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3892                        LED_BLINK_RATE_VAL);
3893                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3894                        port*4, 1);
3895                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3896                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3897
3898                 if (CHIP_IS_E1(bp) &&
3899                     ((speed == SPEED_2500) ||
3900                      (speed == SPEED_1000) ||
3901                      (speed == SPEED_100) ||
3902                      (speed == SPEED_10))) {
3903                         /*
3904                          * On Everest 1 Ax chip versions for speeds less than
3905                          * 10G LED scheme is different
3906                          */
3907                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3908                                + port*4, 1);
3909                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3910                                port*4, 0);
3911                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3912                                port*4, 1);
3913                 }
3914                 break;
3915
3916         default:
3917                 rc = -EINVAL;
3918                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3919                          mode);
3920                 break;
3921         }
3922         return rc;
3923
3924 }
3925
3926 /*
3927  * This function comes to reflect the actual link state read DIRECTLY from the
3928  * HW
3929  */
3930 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3931                     u8 is_serdes)
3932 {
3933         struct bnx2x *bp = params->bp;
3934         u16 gp_status = 0, phy_index = 0;
3935         u8 ext_phy_link_up = 0, serdes_phy_type;
3936         struct link_vars temp_vars;
3937
3938         CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3939                           MDIO_REG_BANK_GP_STATUS,
3940                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3941                           &gp_status);
3942         /* link is up only if both local phy and external phy are up */
3943         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3944                 return -ESRCH;
3945
3946         switch (params->num_phys) {
3947         case 1:
3948                 /* No external PHY */
3949                 return 0;
3950         case 2:
3951                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3952                         &params->phy[EXT_PHY1],
3953                         params, &temp_vars);
3954                 break;
3955         case 3: /* Dual Media */
3956                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3957                       phy_index++) {
3958                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3959                                             ETH_PHY_SFP_FIBER) ||
3960                                            (params->phy[phy_index].media_type ==
3961                                             ETH_PHY_XFP_FIBER) ||
3962                                            (params->phy[phy_index].media_type ==
3963                                             ETH_PHY_DA_TWINAX));
3964
3965                         if (is_serdes != serdes_phy_type)
3966                                 continue;
3967                         if (params->phy[phy_index].read_status) {
3968                                 ext_phy_link_up |=
3969                                         params->phy[phy_index].read_status(
3970                                                 &params->phy[phy_index],
3971                                                 params, &temp_vars);
3972                         }
3973                 }
3974                 break;
3975         }
3976         if (ext_phy_link_up)
3977                 return 0;
3978         return -ESRCH;
3979 }
3980
3981 static int bnx2x_link_initialize(struct link_params *params,
3982                                  struct link_vars *vars)
3983 {
3984         int rc = 0;
3985         u8 phy_index, non_ext_phy;
3986         struct bnx2x *bp = params->bp;
3987         /*
3988          * In case of external phy existence, the line speed would be the
3989          * line speed linked up by the external phy. In case it is direct
3990          * only, then the line_speed during initialization will be
3991          * equal to the req_line_speed
3992          */
3993         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3994
3995         /*
3996          * Initialize the internal phy in case this is a direct board
3997          * (no external phys), or this board has external phy which requires
3998          * to first.
3999          */
4000
4001         bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
4002         /* init ext phy and enable link state int */
4003         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
4004                        (params->loopback_mode == LOOPBACK_XGXS));
4005
4006         if (non_ext_phy ||
4007             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
4008             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
4009                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
4010                 if (vars->line_speed == SPEED_AUTO_NEG)
4011                         bnx2x_set_parallel_detection(phy, params);
4012                         if (params->phy[INT_PHY].config_init)
4013                                 params->phy[INT_PHY].config_init(phy,
4014                                                                  params,
4015                                                                  vars);
4016         }
4017
4018         /* Init external phy*/
4019         if (non_ext_phy) {
4020                 if (params->phy[INT_PHY].supported &
4021                     SUPPORTED_FIBRE)
4022                         vars->link_status |= LINK_STATUS_SERDES_LINK;
4023         } else {
4024                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
4025                       phy_index++) {
4026                         /*
4027                          * No need to initialize second phy in case of first
4028                          * phy only selection. In case of second phy, we do
4029                          * need to initialize the first phy, since they are
4030                          * connected.
4031                          */
4032                         if (params->phy[phy_index].supported &
4033                             SUPPORTED_FIBRE)
4034                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
4035
4036                         if (phy_index == EXT_PHY2 &&
4037                             (bnx2x_phy_selection(params) ==
4038                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
4039                                 DP(NETIF_MSG_LINK, "Not initializing"
4040                                                 " second phy\n");
4041                                 continue;
4042                         }
4043                         params->phy[phy_index].config_init(
4044                                 &params->phy[phy_index],
4045                                 params, vars);
4046                 }
4047         }
4048         /* Reset the interrupt indication after phy was initialized */
4049         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
4050                        params->port*4,
4051                        (NIG_STATUS_XGXS0_LINK10G |
4052                         NIG_STATUS_XGXS0_LINK_STATUS |
4053                         NIG_STATUS_SERDES0_LINK_STATUS |
4054                         NIG_MASK_MI_INT));
4055         bnx2x_update_mng(params, vars->link_status);
4056         return rc;
4057 }
4058
4059 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
4060                                  struct link_params *params)
4061 {
4062         /* reset the SerDes/XGXS */
4063         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
4064                (0x1ff << (params->port*16)));
4065 }
4066
4067 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
4068                                         struct link_params *params)
4069 {
4070         struct bnx2x *bp = params->bp;
4071         u8 gpio_port;
4072         /* HW reset */
4073         if (CHIP_IS_E2(bp))
4074                 gpio_port = BP_PATH(bp);
4075         else
4076                 gpio_port = params->port;
4077         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4078                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4079                        gpio_port);
4080         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4081                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4082                        gpio_port);
4083         DP(NETIF_MSG_LINK, "reset external PHY\n");
4084 }
4085
4086 static int bnx2x_update_link_down(struct link_params *params,
4087                                   struct link_vars *vars)
4088 {
4089         struct bnx2x *bp = params->bp;
4090         u8 port = params->port;
4091
4092         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
4093         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
4094
4095         /* indicate no mac active */
4096         vars->mac_type = MAC_TYPE_NONE;
4097
4098         /* update shared memory */
4099         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
4100                                LINK_STATUS_LINK_UP |
4101                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
4102                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
4103                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
4104                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
4105         vars->line_speed = 0;
4106         bnx2x_update_mng(params, vars->link_status);
4107
4108         /* activate nig drain */
4109         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4110
4111         /* disable emac */
4112         if (!CHIP_IS_E3(bp))
4113                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4114
4115         msleep(10);
4116         /* reset BigMac/Xmac */
4117         if (CHIP_IS_E1x(bp) ||
4118             CHIP_IS_E2(bp)) {
4119                 bnx2x_bmac_rx_disable(bp, params->port);
4120                 REG_WR(bp, GRCBASE_MISC +
4121                        MISC_REGISTERS_RESET_REG_2_CLEAR,
4122                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4123         }
4124         if (CHIP_IS_E3(bp))
4125                 bnx2x_xmac_disable(params);
4126
4127         return 0;
4128 }
4129
4130 static int bnx2x_update_link_up(struct link_params *params,
4131                                 struct link_vars *vars,
4132                                 u8 link_10g)
4133 {
4134         struct bnx2x *bp = params->bp;
4135         u8 port = params->port;
4136         int rc = 0;
4137
4138         vars->link_status |= LINK_STATUS_LINK_UP;
4139
4140         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
4141                 vars->link_status |=
4142                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
4143
4144         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
4145                 vars->link_status |=
4146                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
4147         if (USES_WARPCORE(bp)) {
4148                 if (link_10g)
4149                         bnx2x_xmac_enable(params, vars, 0);
4150                 else
4151                         bnx2x_umac_enable(params, vars, 0);
4152                 bnx2x_set_led(params, vars,
4153                               LED_MODE_OPER, vars->line_speed);
4154         }
4155         if ((CHIP_IS_E1x(bp) ||
4156              CHIP_IS_E2(bp))) {
4157                 if (link_10g) {
4158                         bnx2x_bmac_enable(params, vars, 0);
4159
4160                         bnx2x_set_led(params, vars,
4161                                       LED_MODE_OPER, SPEED_10000);
4162                 } else {
4163                         rc = bnx2x_emac_program(params, vars);
4164                         bnx2x_emac_enable(params, vars, 0);
4165
4166                         /* AN complete? */
4167                         if ((vars->link_status &
4168                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
4169                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
4170                             SINGLE_MEDIA_DIRECT(params))
4171                                 bnx2x_set_gmii_tx_driver(params);
4172                 }
4173         }
4174
4175         /* PBF - link up */
4176         if (CHIP_IS_E1x(bp))
4177                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
4178                                        vars->line_speed);
4179
4180         /* disable drain */
4181         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
4182
4183         /* update shared memory */
4184         bnx2x_update_mng(params, vars->link_status);
4185         msleep(20);
4186         return rc;
4187 }
4188 /*
4189  * The bnx2x_link_update function should be called upon link
4190  * interrupt.
4191  * Link is considered up as follows:
4192  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
4193  *   to be up
4194  * - SINGLE_MEDIA - The link between the 577xx and the external
4195  *   phy (XGXS) need to up as well as the external link of the
4196  *   phy (PHY_EXT1)
4197  * - DUAL_MEDIA - The link between the 577xx and the first
4198  *   external phy needs to be up, and at least one of the 2
4199  *   external phy link must be up.
4200  */
4201 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4202 {
4203         struct bnx2x *bp = params->bp;
4204         struct link_vars phy_vars[MAX_PHYS];
4205         u8 port = params->port;
4206         u8 link_10g, phy_index;
4207         u8 ext_phy_link_up = 0, cur_link_up;
4208         int rc = 0;
4209         u8 is_mi_int = 0;
4210         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
4211         u8 active_external_phy = INT_PHY;
4212
4213         for (phy_index = INT_PHY; phy_index < params->num_phys;
4214               phy_index++) {
4215                 phy_vars[phy_index].flow_ctrl = 0;
4216                 phy_vars[phy_index].link_status = 0;
4217                 phy_vars[phy_index].line_speed = 0;
4218                 phy_vars[phy_index].duplex = DUPLEX_FULL;
4219                 phy_vars[phy_index].phy_link_up = 0;
4220                 phy_vars[phy_index].link_up = 0;
4221                 phy_vars[phy_index].fault_detected = 0;
4222         }
4223
4224         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
4225                  port, (vars->phy_flags & PHY_XGXS_FLAG),
4226                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4227
4228         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
4229                                 port*0x18) > 0);
4230         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
4231                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
4232                  is_mi_int,
4233                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4234
4235         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
4236           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4237           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4238
4239         /* disable emac */
4240         if (!CHIP_IS_E3(bp))
4241                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4242
4243         /*
4244          * Step 1:
4245          * Check external link change only for external phys, and apply
4246          * priority selection between them in case the link on both phys
4247          * is up. Note that instead of the common vars, a temporary
4248          * vars argument is used since each phy may have different link/
4249          * speed/duplex result
4250          */
4251         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
4252               phy_index++) {
4253                 struct bnx2x_phy *phy = &params->phy[phy_index];
4254                 if (!phy->read_status)
4255                         continue;
4256                 /* Read link status and params of this ext phy */
4257                 cur_link_up = phy->read_status(phy, params,
4258                                                &phy_vars[phy_index]);
4259                 if (cur_link_up) {
4260                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
4261                                    phy_index);
4262                 } else {
4263                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
4264                                    phy_index);
4265                         continue;
4266                 }
4267
4268                 if (!ext_phy_link_up) {
4269                         ext_phy_link_up = 1;
4270                         active_external_phy = phy_index;
4271                 } else {
4272                         switch (bnx2x_phy_selection(params)) {
4273                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4274                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4275                         /*
4276                          * In this option, the first PHY makes sure to pass the
4277                          * traffic through itself only.
4278                          * Its not clear how to reset the link on the second phy
4279                          */
4280                                 active_external_phy = EXT_PHY1;
4281                                 break;
4282                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4283                         /*
4284                          * In this option, the first PHY makes sure to pass the
4285                          * traffic through the second PHY.
4286                          */
4287                                 active_external_phy = EXT_PHY2;
4288                                 break;
4289                         default:
4290                         /*
4291                          * Link indication on both PHYs with the following cases
4292                          * is invalid:
4293                          * - FIRST_PHY means that second phy wasn't initialized,
4294                          * hence its link is expected to be down
4295                          * - SECOND_PHY means that first phy should not be able
4296                          * to link up by itself (using configuration)
4297                          * - DEFAULT should be overriden during initialiazation
4298                          */
4299                                 DP(NETIF_MSG_LINK, "Invalid link indication"
4300                                            "mpc=0x%x. DISABLING LINK !!!\n",
4301                                            params->multi_phy_config);
4302                                 ext_phy_link_up = 0;
4303                                 break;
4304                         }
4305                 }
4306         }
4307         prev_line_speed = vars->line_speed;
4308         /*
4309          * Step 2:
4310          * Read the status of the internal phy. In case of
4311          * DIRECT_SINGLE_MEDIA board, this link is the external link,
4312          * otherwise this is the link between the 577xx and the first
4313          * external phy
4314          */
4315         if (params->phy[INT_PHY].read_status)
4316                 params->phy[INT_PHY].read_status(
4317                         &params->phy[INT_PHY],
4318                         params, vars);
4319         /*
4320          * The INT_PHY flow control reside in the vars. This include the
4321          * case where the speed or flow control are not set to AUTO.
4322          * Otherwise, the active external phy flow control result is set
4323          * to the vars. The ext_phy_line_speed is needed to check if the
4324          * speed is different between the internal phy and external phy.
4325          * This case may be result of intermediate link speed change.
4326          */
4327         if (active_external_phy > INT_PHY) {
4328                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
4329                 /*
4330                  * Link speed is taken from the XGXS. AN and FC result from
4331                  * the external phy.
4332                  */
4333                 vars->link_status |= phy_vars[active_external_phy].link_status;
4334
4335                 /*
4336                  * if active_external_phy is first PHY and link is up - disable
4337                  * disable TX on second external PHY
4338                  */
4339                 if (active_external_phy == EXT_PHY1) {
4340                         if (params->phy[EXT_PHY2].phy_specific_func) {
4341                                 DP(NETIF_MSG_LINK, "Disabling TX on"
4342                                                    " EXT_PHY2\n");
4343                                 params->phy[EXT_PHY2].phy_specific_func(
4344                                         &params->phy[EXT_PHY2],
4345                                         params, DISABLE_TX);
4346                         }
4347                 }
4348
4349                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
4350                 vars->duplex = phy_vars[active_external_phy].duplex;
4351                 if (params->phy[active_external_phy].supported &
4352                     SUPPORTED_FIBRE)
4353                         vars->link_status |= LINK_STATUS_SERDES_LINK;
4354                 else
4355                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
4356                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
4357                            active_external_phy);
4358         }
4359
4360         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
4361               phy_index++) {
4362                 if (params->phy[phy_index].flags &
4363                     FLAGS_REARM_LATCH_SIGNAL) {
4364                         bnx2x_rearm_latch_signal(bp, port,
4365                                                  phy_index ==
4366                                                  active_external_phy);
4367                         break;
4368                 }
4369         }
4370         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
4371                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
4372                    vars->link_status, ext_phy_line_speed);
4373         /*
4374          * Upon link speed change set the NIG into drain mode. Comes to
4375          * deals with possible FIFO glitch due to clk change when speed
4376          * is decreased without link down indicator
4377          */
4378
4379         if (vars->phy_link_up) {
4380                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
4381                     (ext_phy_line_speed != vars->line_speed)) {
4382                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
4383                                    " different than the external"
4384                                    " link speed %d\n", vars->line_speed,
4385                                    ext_phy_line_speed);
4386                         vars->phy_link_up = 0;
4387                 } else if (prev_line_speed != vars->line_speed) {
4388                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
4389                                0);
4390                         msleep(1);
4391                 }
4392         }
4393
4394         /* anything 10 and over uses the bmac */
4395         link_10g = ((vars->line_speed == SPEED_10000) ||
4396                     (vars->line_speed == SPEED_12000) ||
4397                     (vars->line_speed == SPEED_12500) ||
4398                     (vars->line_speed == SPEED_13000) ||
4399                     (vars->line_speed == SPEED_15000) ||
4400                     (vars->line_speed == SPEED_16000));
4401
4402         bnx2x_link_int_ack(params, vars, link_10g);
4403
4404         /*
4405          * In case external phy link is up, and internal link is down
4406          * (not initialized yet probably after link initialization, it
4407          * needs to be initialized.
4408          * Note that after link down-up as result of cable plug, the xgxs
4409          * link would probably become up again without the need
4410          * initialize it
4411          */
4412         if (!(SINGLE_MEDIA_DIRECT(params))) {
4413                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
4414                            " init_preceding = %d\n", ext_phy_link_up,
4415                            vars->phy_link_up,
4416                            params->phy[EXT_PHY1].flags &
4417                            FLAGS_INIT_XGXS_FIRST);
4418                 if (!(params->phy[EXT_PHY1].flags &
4419                       FLAGS_INIT_XGXS_FIRST)
4420                     && ext_phy_link_up && !vars->phy_link_up) {
4421                         vars->line_speed = ext_phy_line_speed;
4422                         if (vars->line_speed < SPEED_1000)
4423                                 vars->phy_flags |= PHY_SGMII_FLAG;
4424                         else
4425                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
4426
4427                         if (params->phy[INT_PHY].config_init)
4428                                 params->phy[INT_PHY].config_init(
4429                                         &params->phy[INT_PHY], params,
4430                                                 vars);
4431                 }
4432         }
4433         /*
4434          * Link is up only if both local phy and external phy (in case of
4435          * non-direct board) are up and no fault detected on active PHY.
4436          */
4437         vars->link_up = (vars->phy_link_up &&
4438                          (ext_phy_link_up ||
4439                           SINGLE_MEDIA_DIRECT(params)) &&
4440                          (phy_vars[active_external_phy].fault_detected == 0));
4441
4442         if (vars->link_up)
4443                 rc = bnx2x_update_link_up(params, vars, link_10g);
4444         else
4445                 rc = bnx2x_update_link_down(params, vars);
4446
4447         return rc;
4448 }
4449
4450
4451 /*****************************************************************************/
4452 /*                          External Phy section                             */
4453 /*****************************************************************************/
4454 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
4455 {
4456         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4457                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
4458         msleep(1);
4459         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4460                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
4461 }
4462
4463 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
4464                                       u32 spirom_ver, u32 ver_addr)
4465 {
4466         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
4467                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4468
4469         if (ver_addr)
4470                 REG_WR(bp, ver_addr, spirom_ver);
4471 }
4472
4473 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
4474                                       struct bnx2x_phy *phy,
4475                                       u8 port)
4476 {
4477         u16 fw_ver1, fw_ver2;
4478
4479         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
4480                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
4481         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
4482                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
4483         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
4484                                   phy->ver_addr);
4485 }
4486
4487 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
4488                                        struct bnx2x_phy *phy,
4489                                        struct link_vars *vars)
4490 {
4491         u16 val;
4492         bnx2x_cl45_read(bp, phy,
4493                         MDIO_AN_DEVAD,
4494                         MDIO_AN_REG_STATUS, &val);
4495         bnx2x_cl45_read(bp, phy,
4496                         MDIO_AN_DEVAD,
4497                         MDIO_AN_REG_STATUS, &val);
4498         if (val & (1<<5))
4499                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
4500         if ((val & (1<<0)) == 0)
4501                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
4502 }
4503
4504 /******************************************************************/
4505 /*              common BCM8073/BCM8727 PHY SECTION                */
4506 /******************************************************************/
4507 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
4508                                   struct link_params *params,
4509                                   struct link_vars *vars)
4510 {
4511         struct bnx2x *bp = params->bp;
4512         if (phy->req_line_speed == SPEED_10 ||
4513             phy->req_line_speed == SPEED_100) {
4514                 vars->flow_ctrl = phy->req_flow_ctrl;
4515                 return;
4516         }
4517
4518         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
4519             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
4520                 u16 pause_result;
4521                 u16 ld_pause;           /* local */
4522                 u16 lp_pause;           /* link partner */
4523                 bnx2x_cl45_read(bp, phy,
4524                                 MDIO_AN_DEVAD,
4525                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4526
4527                 bnx2x_cl45_read(bp, phy,
4528                                 MDIO_AN_DEVAD,
4529                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4530                 pause_result = (ld_pause &
4531                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
4532                 pause_result |= (lp_pause &
4533                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
4534
4535                 bnx2x_pause_resolve(vars, pause_result);
4536                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
4537                            pause_result);
4538         }
4539 }
4540 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
4541                                              struct bnx2x_phy *phy,
4542                                              u8 port)
4543 {
4544         u32 count = 0;
4545         u16 fw_ver1, fw_msgout;
4546         int rc = 0;
4547
4548         /* Boot port from external ROM  */
4549         /* EDC grst */
4550         bnx2x_cl45_write(bp, phy,
4551                          MDIO_PMA_DEVAD,
4552                          MDIO_PMA_REG_GEN_CTRL,
4553                          0x0001);
4554
4555         /* ucode reboot and rst */
4556         bnx2x_cl45_write(bp, phy,
4557                          MDIO_PMA_DEVAD,
4558                          MDIO_PMA_REG_GEN_CTRL,
4559                          0x008c);
4560
4561         bnx2x_cl45_write(bp, phy,
4562                          MDIO_PMA_DEVAD,
4563                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
4564
4565         /* Reset internal microprocessor */
4566         bnx2x_cl45_write(bp, phy,
4567                          MDIO_PMA_DEVAD,
4568                          MDIO_PMA_REG_GEN_CTRL,
4569                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
4570
4571         /* Release srst bit */
4572         bnx2x_cl45_write(bp, phy,
4573                          MDIO_PMA_DEVAD,
4574                          MDIO_PMA_REG_GEN_CTRL,
4575                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
4576
4577         /* Delay 100ms per the PHY specifications */
4578         msleep(100);
4579
4580         /* 8073 sometimes taking longer to download */
4581         do {
4582                 count++;
4583                 if (count > 300) {
4584                         DP(NETIF_MSG_LINK,
4585                                  "bnx2x_8073_8727_external_rom_boot port %x:"
4586                                  "Download failed. fw version = 0x%x\n",
4587                                  port, fw_ver1);
4588                         rc = -EINVAL;
4589                         break;
4590                 }
4591
4592                 bnx2x_cl45_read(bp, phy,
4593                                 MDIO_PMA_DEVAD,
4594                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
4595                 bnx2x_cl45_read(bp, phy,
4596                                 MDIO_PMA_DEVAD,
4597                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
4598
4599                 msleep(1);
4600         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
4601                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
4602                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
4603
4604         /* Clear ser_boot_ctl bit */
4605         bnx2x_cl45_write(bp, phy,
4606                          MDIO_PMA_DEVAD,
4607                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
4608         bnx2x_save_bcm_spirom_ver(bp, phy, port);
4609
4610         DP(NETIF_MSG_LINK,
4611                  "bnx2x_8073_8727_external_rom_boot port %x:"
4612                  "Download complete. fw version = 0x%x\n",
4613                  port, fw_ver1);
4614
4615         return rc;
4616 }
4617
4618 /******************************************************************/
4619 /*                      BCM8073 PHY SECTION                       */
4620 /******************************************************************/
4621 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
4622 {
4623         /* This is only required for 8073A1, version 102 only */
4624         u16 val;
4625
4626         /* Read 8073 HW revision*/
4627         bnx2x_cl45_read(bp, phy,
4628                         MDIO_PMA_DEVAD,
4629                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4630
4631         if (val != 1) {
4632                 /* No need to workaround in 8073 A1 */
4633                 return 0;
4634         }
4635
4636         bnx2x_cl45_read(bp, phy,
4637                         MDIO_PMA_DEVAD,
4638                         MDIO_PMA_REG_ROM_VER2, &val);
4639
4640         /* SNR should be applied only for version 0x102 */
4641         if (val != 0x102)
4642                 return 0;
4643
4644         return 1;
4645 }
4646
4647 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
4648 {
4649         u16 val, cnt, cnt1 ;
4650
4651         bnx2x_cl45_read(bp, phy,
4652                         MDIO_PMA_DEVAD,
4653                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4654
4655         if (val > 0) {
4656                 /* No need to workaround in 8073 A1 */
4657                 return 0;
4658         }
4659         /* XAUI workaround in 8073 A0: */
4660
4661         /*
4662          * After loading the boot ROM and restarting Autoneg, poll
4663          * Dev1, Reg $C820:
4664          */
4665
4666         for (cnt = 0; cnt < 1000; cnt++) {
4667                 bnx2x_cl45_read(bp, phy,
4668                                 MDIO_PMA_DEVAD,
4669                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4670                                 &val);
4671                   /*
4672                    * If bit [14] = 0 or bit [13] = 0, continue on with
4673                    * system initialization (XAUI work-around not required, as
4674                    * these bits indicate 2.5G or 1G link up).
4675                    */
4676                 if (!(val & (1<<14)) || !(val & (1<<13))) {
4677                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4678                         return 0;
4679                 } else if (!(val & (1<<15))) {
4680                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
4681                         /*
4682                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
4683                          * MSB (bit15) goes to 1 (indicating that the XAUI
4684                          * workaround has completed), then continue on with
4685                          * system initialization.
4686                          */
4687                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4688                                 bnx2x_cl45_read(bp, phy,
4689                                         MDIO_PMA_DEVAD,
4690                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4691                                 if (val & (1<<15)) {
4692                                         DP(NETIF_MSG_LINK,
4693                                           "XAUI workaround has completed\n");
4694                                         return 0;
4695                                  }
4696                                  msleep(3);
4697                         }
4698                         break;
4699                 }
4700                 msleep(3);
4701         }
4702         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4703         return -EINVAL;
4704 }
4705
4706 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4707 {
4708         /* Force KR or KX */
4709         bnx2x_cl45_write(bp, phy,
4710                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4711         bnx2x_cl45_write(bp, phy,
4712                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4713         bnx2x_cl45_write(bp, phy,
4714                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4715         bnx2x_cl45_write(bp, phy,
4716                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4717 }
4718
4719 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4720                                       struct bnx2x_phy *phy,
4721                                       struct link_vars *vars)
4722 {
4723         u16 cl37_val;
4724         struct bnx2x *bp = params->bp;
4725         bnx2x_cl45_read(bp, phy,
4726                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4727
4728         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4729         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4730         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4731         if ((vars->ieee_fc &
4732             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4733             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4734                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4735         }
4736         if ((vars->ieee_fc &
4737             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4738             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4739                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4740         }
4741         if ((vars->ieee_fc &
4742             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4743             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4744                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4745         }
4746         DP(NETIF_MSG_LINK,
4747                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4748
4749         bnx2x_cl45_write(bp, phy,
4750                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4751         msleep(500);
4752 }
4753
4754 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
4755                                   struct link_params *params,
4756                                   struct link_vars *vars)
4757 {
4758         struct bnx2x *bp = params->bp;
4759         u16 val = 0, tmp1;
4760         u8 gpio_port;
4761         DP(NETIF_MSG_LINK, "Init 8073\n");
4762
4763         if (CHIP_IS_E2(bp))
4764                 gpio_port = BP_PATH(bp);
4765         else
4766                 gpio_port = params->port;
4767         /* Restore normal power mode*/
4768         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4769                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4770
4771         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4772                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4773
4774         /* enable LASI */
4775         bnx2x_cl45_write(bp, phy,
4776                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4777         bnx2x_cl45_write(bp, phy,
4778                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4779
4780         bnx2x_8073_set_pause_cl37(params, phy, vars);
4781
4782         bnx2x_cl45_read(bp, phy,
4783                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4784
4785         bnx2x_cl45_read(bp, phy,
4786                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4787
4788         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4789
4790         /* Swap polarity if required - Must be done only in non-1G mode */
4791         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4792                 /* Configure the 8073 to swap _P and _N of the KR lines */
4793                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4794                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4795                 bnx2x_cl45_read(bp, phy,
4796                                 MDIO_PMA_DEVAD,
4797                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4798                 bnx2x_cl45_write(bp, phy,
4799                                  MDIO_PMA_DEVAD,
4800                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4801                                  (val | (3<<9)));
4802         }
4803
4804
4805         /* Enable CL37 BAM */
4806         if (REG_RD(bp, params->shmem_base +
4807                          offsetof(struct shmem_region, dev_info.
4808                                   port_hw_config[params->port].default_cfg)) &
4809             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4810
4811                 bnx2x_cl45_read(bp, phy,
4812                                 MDIO_AN_DEVAD,
4813                                 MDIO_AN_REG_8073_BAM, &val);
4814                 bnx2x_cl45_write(bp, phy,
4815                                  MDIO_AN_DEVAD,
4816                                  MDIO_AN_REG_8073_BAM, val | 1);
4817                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4818         }
4819         if (params->loopback_mode == LOOPBACK_EXT) {
4820                 bnx2x_807x_force_10G(bp, phy);
4821                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4822                 return 0;
4823         } else {
4824                 bnx2x_cl45_write(bp, phy,
4825                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4826         }
4827         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4828                 if (phy->req_line_speed == SPEED_10000) {
4829                         val = (1<<7);
4830                 } else if (phy->req_line_speed ==  SPEED_2500) {
4831                         val = (1<<5);
4832                         /*
4833                          * Note that 2.5G works only when used with 1G
4834                          * advertisement
4835                          */
4836                 } else
4837                         val = (1<<5);
4838         } else {
4839                 val = 0;
4840                 if (phy->speed_cap_mask &
4841                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4842                         val |= (1<<7);
4843
4844                 /* Note that 2.5G works only when used with 1G advertisement */
4845                 if (phy->speed_cap_mask &
4846                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4847                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4848                         val |= (1<<5);
4849                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4850         }
4851
4852         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4853         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4854
4855         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4856              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4857             (phy->req_line_speed == SPEED_2500)) {
4858                 u16 phy_ver;
4859                 /* Allow 2.5G for A1 and above */
4860                 bnx2x_cl45_read(bp, phy,
4861                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4862                                 &phy_ver);
4863                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4864                 if (phy_ver > 0)
4865                         tmp1 |= 1;
4866                 else
4867                         tmp1 &= 0xfffe;
4868         } else {
4869                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4870                 tmp1 &= 0xfffe;
4871         }
4872
4873         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4874         /* Add support for CL37 (passive mode) II */
4875
4876         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4877         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4878                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4879                                   0x20 : 0x40)));
4880
4881         /* Add support for CL37 (passive mode) III */
4882         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4883
4884         /*
4885          * The SNR will improve about 2db by changing BW and FEE main
4886          * tap. Rest commands are executed after link is up
4887          * Change FFE main cursor to 5 in EDC register
4888          */
4889         if (bnx2x_8073_is_snr_needed(bp, phy))
4890                 bnx2x_cl45_write(bp, phy,
4891                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4892                                  0xFB0C);
4893
4894         /* Enable FEC (Forware Error Correction) Request in the AN */
4895         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4896         tmp1 |= (1<<15);
4897         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4898
4899         bnx2x_ext_phy_set_pause(params, phy, vars);
4900
4901         /* Restart autoneg */
4902         msleep(500);
4903         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4904         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4905                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4906         return 0;
4907 }
4908
4909 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4910                                  struct link_params *params,
4911                                  struct link_vars *vars)
4912 {
4913         struct bnx2x *bp = params->bp;
4914         u8 link_up = 0;
4915         u16 val1, val2;
4916         u16 link_status = 0;
4917         u16 an1000_status = 0;
4918
4919         bnx2x_cl45_read(bp, phy,
4920                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4921
4922         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4923
4924         /* clear the interrupt LASI status register */
4925         bnx2x_cl45_read(bp, phy,
4926                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4927         bnx2x_cl45_read(bp, phy,
4928                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4929         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4930         /* Clear MSG-OUT */
4931         bnx2x_cl45_read(bp, phy,
4932                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4933
4934         /* Check the LASI */
4935         bnx2x_cl45_read(bp, phy,
4936                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4937
4938         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4939
4940         /* Check the link status */
4941         bnx2x_cl45_read(bp, phy,
4942                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4943         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4944
4945         bnx2x_cl45_read(bp, phy,
4946                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4947         bnx2x_cl45_read(bp, phy,
4948                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4949         link_up = ((val1 & 4) == 4);
4950         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4951
4952         if (link_up &&
4953              ((phy->req_line_speed != SPEED_10000))) {
4954                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4955                         return 0;
4956         }
4957         bnx2x_cl45_read(bp, phy,
4958                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4959         bnx2x_cl45_read(bp, phy,
4960                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4961
4962         /* Check the link status on 1.1.2 */
4963         bnx2x_cl45_read(bp, phy,
4964                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4965         bnx2x_cl45_read(bp, phy,
4966                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4967         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4968                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4969
4970         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4971         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4972                 /*
4973                  * The SNR will improve about 2dbby changing the BW and FEE main
4974                  * tap. The 1st write to change FFE main tap is set before
4975                  * restart AN. Change PLL Bandwidth in EDC register
4976                  */
4977                 bnx2x_cl45_write(bp, phy,
4978                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4979                                  0x26BC);
4980
4981                 /* Change CDR Bandwidth in EDC register */
4982                 bnx2x_cl45_write(bp, phy,
4983                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4984                                  0x0333);
4985         }
4986         bnx2x_cl45_read(bp, phy,
4987                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4988                         &link_status);
4989
4990         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4991         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4992                 link_up = 1;
4993                 vars->line_speed = SPEED_10000;
4994                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4995                            params->port);
4996         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4997                 link_up = 1;
4998                 vars->line_speed = SPEED_2500;
4999                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
5000                            params->port);
5001         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5002                 link_up = 1;
5003                 vars->line_speed = SPEED_1000;
5004                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5005                            params->port);
5006         } else {
5007                 link_up = 0;
5008                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5009                            params->port);
5010         }
5011
5012         if (link_up) {
5013                 /* Swap polarity if required */
5014                 if (params->lane_config &
5015                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
5016                         /* Configure the 8073 to swap P and N of the KR lines */
5017                         bnx2x_cl45_read(bp, phy,
5018                                         MDIO_XS_DEVAD,
5019                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
5020                         /*
5021                          * Set bit 3 to invert Rx in 1G mode and clear this bit
5022                          * when it`s in 10G mode.
5023                          */
5024                         if (vars->line_speed == SPEED_1000) {
5025                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
5026                                               "the 8073\n");
5027                                 val1 |= (1<<3);
5028                         } else
5029                                 val1 &= ~(1<<3);
5030
5031                         bnx2x_cl45_write(bp, phy,
5032                                          MDIO_XS_DEVAD,
5033                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
5034                                          val1);
5035                 }
5036                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
5037                 bnx2x_8073_resolve_fc(phy, params, vars);
5038                 vars->duplex = DUPLEX_FULL;
5039         }
5040         return link_up;
5041 }
5042
5043 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
5044                                   struct link_params *params)
5045 {
5046         struct bnx2x *bp = params->bp;
5047         u8 gpio_port;
5048         if (CHIP_IS_E2(bp))
5049                 gpio_port = BP_PATH(bp);
5050         else
5051                 gpio_port = params->port;
5052         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
5053            gpio_port);
5054         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5055                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
5056                        gpio_port);
5057 }
5058
5059 /******************************************************************/
5060 /*                      BCM8705 PHY SECTION                       */
5061 /******************************************************************/
5062 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
5063                                   struct link_params *params,
5064                                   struct link_vars *vars)
5065 {
5066         struct bnx2x *bp = params->bp;
5067         DP(NETIF_MSG_LINK, "init 8705\n");
5068         /* Restore normal power mode*/
5069         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5070                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5071         /* HW reset */
5072         bnx2x_ext_phy_hw_reset(bp, params->port);
5073         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5074         bnx2x_wait_reset_complete(bp, phy, params);
5075
5076         bnx2x_cl45_write(bp, phy,
5077                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
5078         bnx2x_cl45_write(bp, phy,
5079                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
5080         bnx2x_cl45_write(bp, phy,
5081                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
5082         bnx2x_cl45_write(bp, phy,
5083                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
5084         /* BCM8705 doesn't have microcode, hence the 0 */
5085         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
5086         return 0;
5087 }
5088
5089 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
5090                                  struct link_params *params,
5091                                  struct link_vars *vars)
5092 {
5093         u8 link_up = 0;
5094         u16 val1, rx_sd;
5095         struct bnx2x *bp = params->bp;
5096         DP(NETIF_MSG_LINK, "read status 8705\n");
5097         bnx2x_cl45_read(bp, phy,
5098                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
5099         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
5100
5101         bnx2x_cl45_read(bp, phy,
5102                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
5103         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
5104
5105         bnx2x_cl45_read(bp, phy,
5106                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5107
5108         bnx2x_cl45_read(bp, phy,
5109                       MDIO_PMA_DEVAD, 0xc809, &val1);
5110         bnx2x_cl45_read(bp, phy,
5111                       MDIO_PMA_DEVAD, 0xc809, &val1);
5112
5113         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
5114         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
5115         if (link_up) {
5116                 vars->line_speed = SPEED_10000;
5117                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5118         }
5119         return link_up;
5120 }
5121
5122 /******************************************************************/
5123 /*                      SFP+ module Section                       */
5124 /******************************************************************/
5125 static u8 bnx2x_get_gpio_port(struct link_params *params)
5126 {
5127         u8 gpio_port;
5128         u32 swap_val, swap_override;
5129         struct bnx2x *bp = params->bp;
5130         if (CHIP_IS_E2(bp))
5131                 gpio_port = BP_PATH(bp);
5132         else
5133                 gpio_port = params->port;
5134         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5135         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5136         return gpio_port ^ (swap_val && swap_override);
5137 }
5138 static void bnx2x_sfp_set_transmitter(struct link_params *params,
5139                                       struct bnx2x_phy *phy,
5140                                       u8 tx_en)
5141 {
5142         u16 val;
5143         u8 port = params->port;
5144         struct bnx2x *bp = params->bp;
5145         u32 tx_en_mode;
5146
5147         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
5148         tx_en_mode = REG_RD(bp, params->shmem_base +
5149                             offsetof(struct shmem_region,
5150                                      dev_info.port_hw_config[port].sfp_ctrl)) &
5151                 PORT_HW_CFG_TX_LASER_MASK;
5152         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
5153                            "mode = %x\n", tx_en, port, tx_en_mode);
5154         switch (tx_en_mode) {
5155         case PORT_HW_CFG_TX_LASER_MDIO:
5156
5157                 bnx2x_cl45_read(bp, phy,
5158                                 MDIO_PMA_DEVAD,
5159                                 MDIO_PMA_REG_PHY_IDENTIFIER,
5160                                 &val);
5161
5162                 if (tx_en)
5163                         val &= ~(1<<15);
5164                 else
5165                         val |= (1<<15);
5166
5167                 bnx2x_cl45_write(bp, phy,
5168                                  MDIO_PMA_DEVAD,
5169                                  MDIO_PMA_REG_PHY_IDENTIFIER,
5170                                  val);
5171         break;
5172         case PORT_HW_CFG_TX_LASER_GPIO0:
5173         case PORT_HW_CFG_TX_LASER_GPIO1:
5174         case PORT_HW_CFG_TX_LASER_GPIO2:
5175         case PORT_HW_CFG_TX_LASER_GPIO3:
5176         {
5177                 u16 gpio_pin;
5178                 u8 gpio_port, gpio_mode;
5179                 if (tx_en)
5180                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
5181                 else
5182                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
5183
5184                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
5185                 gpio_port = bnx2x_get_gpio_port(params);
5186                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5187                 break;
5188         }
5189         default:
5190                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
5191                 break;
5192         }
5193 }
5194
5195 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
5196                                              struct link_params *params,
5197                                              u16 addr, u8 byte_cnt, u8 *o_buf)
5198 {
5199         struct bnx2x *bp = params->bp;
5200         u16 val = 0;
5201         u16 i;
5202         if (byte_cnt > 16) {
5203                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
5204                             " is limited to 0xf\n");
5205                 return -EINVAL;
5206         }
5207         /* Set the read command byte count */
5208         bnx2x_cl45_write(bp, phy,
5209                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
5210                          (byte_cnt | 0xa000));
5211
5212         /* Set the read command address */
5213         bnx2x_cl45_write(bp, phy,
5214                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
5215                          addr);
5216
5217         /* Activate read command */
5218         bnx2x_cl45_write(bp, phy,
5219                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
5220                          0x2c0f);
5221
5222         /* Wait up to 500us for command complete status */
5223         for (i = 0; i < 100; i++) {
5224                 bnx2x_cl45_read(bp, phy,
5225                                 MDIO_PMA_DEVAD,
5226                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
5227                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
5228                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
5229                         break;
5230                 udelay(5);
5231         }
5232
5233         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
5234                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
5235                 DP(NETIF_MSG_LINK,
5236                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
5237                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
5238                 return -EINVAL;
5239         }
5240
5241         /* Read the buffer */
5242         for (i = 0; i < byte_cnt; i++) {
5243                 bnx2x_cl45_read(bp, phy,
5244                                 MDIO_PMA_DEVAD,
5245                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
5246                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
5247         }
5248
5249         for (i = 0; i < 100; i++) {
5250                 bnx2x_cl45_read(bp, phy,
5251                                 MDIO_PMA_DEVAD,
5252                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
5253                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
5254                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
5255                         return 0;
5256                 msleep(1);
5257         }
5258         return -EINVAL;
5259 }
5260
5261 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
5262                                              struct link_params *params,
5263                                              u16 addr, u8 byte_cnt, u8 *o_buf)
5264 {
5265         struct bnx2x *bp = params->bp;
5266         u16 val, i;
5267
5268         if (byte_cnt > 16) {
5269                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
5270                             " is limited to 0xf\n");
5271                 return -EINVAL;
5272         }
5273
5274         /* Need to read from 1.8000 to clear it */
5275         bnx2x_cl45_read(bp, phy,
5276                         MDIO_PMA_DEVAD,
5277                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
5278                         &val);
5279
5280         /* Set the read command byte count */
5281         bnx2x_cl45_write(bp, phy,
5282                          MDIO_PMA_DEVAD,
5283                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
5284                          ((byte_cnt < 2) ? 2 : byte_cnt));
5285
5286         /* Set the read command address */
5287         bnx2x_cl45_write(bp, phy,
5288                          MDIO_PMA_DEVAD,
5289                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
5290                          addr);
5291         /* Set the destination address */
5292         bnx2x_cl45_write(bp, phy,
5293                          MDIO_PMA_DEVAD,
5294                          0x8004,
5295                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
5296
5297         /* Activate read command */
5298         bnx2x_cl45_write(bp, phy,
5299                          MDIO_PMA_DEVAD,
5300                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
5301                          0x8002);
5302         /*
5303          * Wait appropriate time for two-wire command to finish before
5304          * polling the status register
5305          */
5306         msleep(1);
5307
5308         /* Wait up to 500us for command complete status */
5309         for (i = 0; i < 100; i++) {
5310                 bnx2x_cl45_read(bp, phy,
5311                                 MDIO_PMA_DEVAD,
5312                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
5313                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
5314                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
5315                         break;
5316                 udelay(5);
5317         }
5318
5319         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
5320                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
5321                 DP(NETIF_MSG_LINK,
5322                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
5323                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
5324                 return -EFAULT;
5325         }
5326
5327         /* Read the buffer */
5328         for (i = 0; i < byte_cnt; i++) {
5329                 bnx2x_cl45_read(bp, phy,
5330                                 MDIO_PMA_DEVAD,
5331                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
5332                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
5333         }
5334
5335         for (i = 0; i < 100; i++) {
5336                 bnx2x_cl45_read(bp, phy,
5337                                 MDIO_PMA_DEVAD,
5338                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
5339                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
5340                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
5341                         return 0;
5342                 msleep(1);
5343         }
5344
5345         return -EINVAL;
5346 }
5347
5348 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
5349                                  struct link_params *params, u16 addr,
5350                                  u8 byte_cnt, u8 *o_buf)
5351 {
5352         int rc = -EINVAL;
5353         switch (phy->type) {
5354         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5355                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
5356                                                        byte_cnt, o_buf);
5357         break;
5358         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5359         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5360                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
5361                                                        byte_cnt, o_buf);
5362         break;
5363         }
5364         return rc;
5365 }
5366
5367 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
5368                               struct link_params *params,
5369                               u16 *edc_mode)
5370 {
5371         struct bnx2x *bp = params->bp;
5372         u32 sync_offset = 0, phy_idx, media_types;
5373         u8 val, check_limiting_mode = 0;
5374         *edc_mode = EDC_MODE_LIMITING;
5375
5376         phy->media_type = ETH_PHY_UNSPECIFIED;
5377         /* First check for copper cable */
5378         if (bnx2x_read_sfp_module_eeprom(phy,
5379                                          params,
5380                                          SFP_EEPROM_CON_TYPE_ADDR,
5381                                          1,
5382                                          &val) != 0) {
5383                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
5384                 return -EINVAL;
5385         }
5386
5387         switch (val) {
5388         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
5389         {
5390                 u8 copper_module_type;
5391                 phy->media_type = ETH_PHY_DA_TWINAX;
5392                 /*
5393                  * Check if its active cable (includes SFP+ module)
5394                  * of passive cable
5395                  */
5396                 if (bnx2x_read_sfp_module_eeprom(phy,
5397                                                params,
5398                                                SFP_EEPROM_FC_TX_TECH_ADDR,
5399                                                1,
5400                                                &copper_module_type) != 0) {
5401                         DP(NETIF_MSG_LINK,
5402                                 "Failed to read copper-cable-type"
5403                                 " from SFP+ EEPROM\n");
5404                         return -EINVAL;
5405                 }
5406
5407                 if (copper_module_type &
5408                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
5409                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
5410                         check_limiting_mode = 1;
5411                 } else if (copper_module_type &
5412                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
5413                                 DP(NETIF_MSG_LINK, "Passive Copper"
5414                                             " cable detected\n");
5415                                 *edc_mode =
5416                                       EDC_MODE_PASSIVE_DAC;
5417                 } else {
5418                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
5419                                      "type 0x%x !!!\n", copper_module_type);
5420                         return -EINVAL;
5421                 }
5422                 break;
5423         }
5424         case SFP_EEPROM_CON_TYPE_VAL_LC:
5425                 phy->media_type = ETH_PHY_SFP_FIBER;
5426                 DP(NETIF_MSG_LINK, "Optic module detected\n");
5427                 check_limiting_mode = 1;
5428                 break;
5429         default:
5430                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
5431                          val);
5432                 return -EINVAL;
5433         }
5434         sync_offset = params->shmem_base +
5435                 offsetof(struct shmem_region,
5436                          dev_info.port_hw_config[params->port].media_type);
5437         media_types = REG_RD(bp, sync_offset);
5438         /* Update media type for non-PMF sync */
5439         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
5440                 if (&(params->phy[phy_idx]) == phy) {
5441                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
5442                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
5443                         media_types |= ((phy->media_type &
5444                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
5445                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
5446                         break;
5447                 }
5448         }
5449         REG_WR(bp, sync_offset, media_types);
5450         if (check_limiting_mode) {
5451                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
5452                 if (bnx2x_read_sfp_module_eeprom(phy,
5453                                                  params,
5454                                                  SFP_EEPROM_OPTIONS_ADDR,
5455                                                  SFP_EEPROM_OPTIONS_SIZE,
5456                                                  options) != 0) {
5457                         DP(NETIF_MSG_LINK, "Failed to read Option"
5458                                 " field from module EEPROM\n");
5459                         return -EINVAL;
5460                 }
5461                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
5462                         *edc_mode = EDC_MODE_LINEAR;
5463                 else
5464                         *edc_mode = EDC_MODE_LIMITING;
5465         }
5466         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
5467         return 0;
5468 }
5469 /*
5470  * This function read the relevant field from the module (SFP+), and verify it
5471  * is compliant with this board
5472  */
5473 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
5474                                    struct link_params *params)
5475 {
5476         struct bnx2x *bp = params->bp;
5477         u32 val, cmd;
5478         u32 fw_resp, fw_cmd_param;
5479         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
5480         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
5481         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
5482         val = REG_RD(bp, params->shmem_base +
5483                          offsetof(struct shmem_region, dev_info.
5484                                   port_feature_config[params->port].config));
5485         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5486             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
5487                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
5488                 return 0;
5489         }
5490
5491         if (params->feature_config_flags &
5492             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
5493                 /* Use specific phy request */
5494                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
5495         } else if (params->feature_config_flags &
5496                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
5497                 /* Use first phy request only in case of non-dual media*/
5498                 if (DUAL_MEDIA(params)) {
5499                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
5500                            "verification\n");
5501                         return -EINVAL;
5502                 }
5503                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
5504         } else {
5505                 /* No support in OPT MDL detection */
5506                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
5507                           "verification\n");
5508                 return -EINVAL;
5509         }
5510
5511         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
5512         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
5513         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
5514                 DP(NETIF_MSG_LINK, "Approved module\n");
5515                 return 0;
5516         }
5517
5518         /* format the warning message */
5519         if (bnx2x_read_sfp_module_eeprom(phy,
5520                                          params,
5521                                          SFP_EEPROM_VENDOR_NAME_ADDR,
5522                                          SFP_EEPROM_VENDOR_NAME_SIZE,
5523                                          (u8 *)vendor_name))
5524                 vendor_name[0] = '\0';
5525         else
5526                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
5527         if (bnx2x_read_sfp_module_eeprom(phy,
5528                                          params,
5529                                          SFP_EEPROM_PART_NO_ADDR,
5530                                          SFP_EEPROM_PART_NO_SIZE,
5531                                          (u8 *)vendor_pn))
5532                 vendor_pn[0] = '\0';
5533         else
5534                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
5535
5536         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
5537                               " Port %d from %s part number %s\n",
5538                          params->port, vendor_name, vendor_pn);
5539         phy->flags |= FLAGS_SFP_NOT_APPROVED;
5540         return -EINVAL;
5541 }
5542
5543 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
5544                                                  struct link_params *params)
5545
5546 {
5547         u8 val;
5548         struct bnx2x *bp = params->bp;
5549         u16 timeout;
5550         /*
5551          * Initialization time after hot-plug may take up to 300ms for
5552          * some phys type ( e.g. JDSU )
5553          */
5554
5555         for (timeout = 0; timeout < 60; timeout++) {
5556                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
5557                     == 0) {
5558                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
5559                                      "took %d ms\n", timeout * 5);
5560                         return 0;
5561                 }
5562                 msleep(5);
5563         }
5564         return -EINVAL;
5565 }
5566
5567 static void bnx2x_8727_power_module(struct bnx2x *bp,
5568                                     struct bnx2x_phy *phy,
5569                                     u8 is_power_up) {
5570         /* Make sure GPIOs are not using for LED mode */
5571         u16 val;
5572         /*
5573          * In the GPIO register, bit 4 is use to determine if the GPIOs are
5574          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
5575          * output
5576          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
5577          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
5578          * where the 1st bit is the over-current(only input), and 2nd bit is
5579          * for power( only output )
5580          *
5581          * In case of NOC feature is disabled and power is up, set GPIO control
5582          *  as input to enable listening of over-current indication
5583          */
5584         if (phy->flags & FLAGS_NOC)
5585                 return;
5586         if (is_power_up)
5587                 val = (1<<4);
5588         else
5589                 /*
5590                  * Set GPIO control to OUTPUT, and set the power bit
5591                  * to according to the is_power_up
5592                  */
5593                 val = (1<<1);
5594
5595         bnx2x_cl45_write(bp, phy,
5596                          MDIO_PMA_DEVAD,
5597                          MDIO_PMA_REG_8727_GPIO_CTRL,
5598                          val);
5599 }
5600
5601 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
5602                                         struct bnx2x_phy *phy,
5603                                         u16 edc_mode)
5604 {
5605         u16 cur_limiting_mode;
5606
5607         bnx2x_cl45_read(bp, phy,
5608                         MDIO_PMA_DEVAD,
5609                         MDIO_PMA_REG_ROM_VER2,
5610                         &cur_limiting_mode);
5611         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
5612                  cur_limiting_mode);
5613
5614         if (edc_mode == EDC_MODE_LIMITING) {
5615                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
5616                 bnx2x_cl45_write(bp, phy,
5617                                  MDIO_PMA_DEVAD,
5618                                  MDIO_PMA_REG_ROM_VER2,
5619                                  EDC_MODE_LIMITING);
5620         } else { /* LRM mode ( default )*/
5621
5622                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
5623
5624                 /*
5625                  * Changing to LRM mode takes quite few seconds. So do it only
5626                  * if current mode is limiting (default is LRM)
5627                  */
5628                 if (cur_limiting_mode != EDC_MODE_LIMITING)
5629                         return 0;
5630
5631                 bnx2x_cl45_write(bp, phy,
5632                                  MDIO_PMA_DEVAD,
5633                                  MDIO_PMA_REG_LRM_MODE,
5634                                  0);
5635                 bnx2x_cl45_write(bp, phy,
5636                                  MDIO_PMA_DEVAD,
5637                                  MDIO_PMA_REG_ROM_VER2,
5638                                  0x128);
5639                 bnx2x_cl45_write(bp, phy,
5640                                  MDIO_PMA_DEVAD,
5641                                  MDIO_PMA_REG_MISC_CTRL0,
5642                                  0x4008);
5643                 bnx2x_cl45_write(bp, phy,
5644                                  MDIO_PMA_DEVAD,
5645                                  MDIO_PMA_REG_LRM_MODE,
5646                                  0xaaaa);
5647         }
5648         return 0;
5649 }
5650
5651 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
5652                                         struct bnx2x_phy *phy,
5653                                         u16 edc_mode)
5654 {
5655         u16 phy_identifier;
5656         u16 rom_ver2_val;
5657         bnx2x_cl45_read(bp, phy,
5658                         MDIO_PMA_DEVAD,
5659                         MDIO_PMA_REG_PHY_IDENTIFIER,
5660                         &phy_identifier);
5661
5662         bnx2x_cl45_write(bp, phy,
5663                          MDIO_PMA_DEVAD,
5664                          MDIO_PMA_REG_PHY_IDENTIFIER,
5665                          (phy_identifier & ~(1<<9)));
5666
5667         bnx2x_cl45_read(bp, phy,
5668                         MDIO_PMA_DEVAD,
5669                         MDIO_PMA_REG_ROM_VER2,
5670                         &rom_ver2_val);
5671         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
5672         bnx2x_cl45_write(bp, phy,
5673                          MDIO_PMA_DEVAD,
5674                          MDIO_PMA_REG_ROM_VER2,
5675                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
5676
5677         bnx2x_cl45_write(bp, phy,
5678                          MDIO_PMA_DEVAD,
5679                          MDIO_PMA_REG_PHY_IDENTIFIER,
5680                          (phy_identifier | (1<<9)));
5681
5682         return 0;
5683 }
5684
5685 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
5686                                      struct link_params *params,
5687                                      u32 action)
5688 {
5689         struct bnx2x *bp = params->bp;
5690
5691         switch (action) {
5692         case DISABLE_TX:
5693                 bnx2x_sfp_set_transmitter(params, phy, 0);
5694                 break;
5695         case ENABLE_TX:
5696                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
5697                         bnx2x_sfp_set_transmitter(params, phy, 1);
5698                 break;
5699         default:
5700                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5701                    action);
5702                 return;
5703         }
5704 }
5705
5706 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5707                                            u8 gpio_mode)
5708 {
5709         struct bnx2x *bp = params->bp;
5710
5711         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5712                             offsetof(struct shmem_region,
5713                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
5714                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5715         switch (fault_led_gpio) {
5716         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5717                 return;
5718         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5719         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5720         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5721         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5722         {
5723                 u8 gpio_port = bnx2x_get_gpio_port(params);
5724                 u16 gpio_pin = fault_led_gpio -
5725                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5726                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5727                                    "pin %x port %x mode %x\n",
5728                                gpio_pin, gpio_port, gpio_mode);
5729                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5730         }
5731         break;
5732         default:
5733                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5734                                fault_led_gpio);
5735         }
5736 }
5737
5738 static void bnx2x_power_sfp_module(struct link_params *params,
5739                                    struct bnx2x_phy *phy,
5740                                    u8 power)
5741 {
5742         struct bnx2x *bp = params->bp;
5743         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5744
5745         switch (phy->type) {
5746         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5747         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5748                 bnx2x_8727_power_module(params->bp, phy, power);
5749                 break;
5750         default:
5751                 break;
5752         }
5753 }
5754
5755 static void bnx2x_set_limiting_mode(struct link_params *params,
5756                                     struct bnx2x_phy *phy,
5757                                     u16 edc_mode)
5758 {
5759         switch (phy->type) {
5760         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5761                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5762                 break;
5763         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5764         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5765                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5766                 break;
5767         }
5768 }
5769
5770 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5771                                struct link_params *params)
5772 {
5773         struct bnx2x *bp = params->bp;
5774         u16 edc_mode;
5775         int rc = 0;
5776
5777         u32 val = REG_RD(bp, params->shmem_base +
5778                              offsetof(struct shmem_region, dev_info.
5779                                      port_feature_config[params->port].config));
5780
5781         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5782                  params->port);
5783         /* Power up module */
5784         bnx2x_power_sfp_module(params, phy, 1);
5785         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5786                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5787                 return -EINVAL;
5788         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5789                 /* check SFP+ module compatibility */
5790                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5791                 rc = -EINVAL;
5792                 /* Turn on fault module-detected led */
5793                 bnx2x_set_sfp_module_fault_led(params,
5794                                                MISC_REGISTERS_GPIO_HIGH);
5795
5796                 /* Check if need to power down the SFP+ module */
5797                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5798                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
5799                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5800                         bnx2x_power_sfp_module(params, phy, 0);
5801                         return rc;
5802                 }
5803         } else {
5804                 /* Turn off fault module-detected led */
5805                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5806         }
5807
5808         /*
5809          * Check and set limiting mode / LRM mode on 8726. On 8727 it
5810          * is done automatically
5811          */
5812         bnx2x_set_limiting_mode(params, phy, edc_mode);
5813
5814         /*
5815          * Enable transmit for this module if the module is approved, or
5816          * if unapproved modules should also enable the Tx laser
5817          */
5818         if (rc == 0 ||
5819             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5820             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5821                 bnx2x_sfp_set_transmitter(params, phy, 1);
5822         else
5823                 bnx2x_sfp_set_transmitter(params, phy, 0);
5824
5825         return rc;
5826 }
5827
5828 void bnx2x_handle_module_detect_int(struct link_params *params)
5829 {
5830         struct bnx2x *bp = params->bp;
5831         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5832         u32 gpio_val;
5833         u8 port = params->port;
5834
5835         /* Set valid module led off */
5836         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5837
5838         /* Get current gpio val reflecting module plugged in / out*/
5839         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5840
5841         /* Call the handling function in case module is detected */
5842         if (gpio_val == 0) {
5843                 bnx2x_power_sfp_module(params, phy, 1);
5844                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5845                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5846                                    port);
5847
5848                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5849                         bnx2x_sfp_module_detection(phy, params);
5850                 else
5851                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5852         } else {
5853                 u32 val = REG_RD(bp, params->shmem_base +
5854                                  offsetof(struct shmem_region, dev_info.
5855                                           port_feature_config[params->port].
5856                                           config));
5857
5858                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5859                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5860                                    port);
5861                 /*
5862                  * Module was plugged out.
5863                  * Disable transmit for this module
5864                  */
5865                 phy->media_type = ETH_PHY_NOT_PRESENT;
5866                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5867                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5868                         bnx2x_sfp_set_transmitter(params, phy, 0);
5869         }
5870 }
5871
5872 /******************************************************************/
5873 /*              Used by 8706 and 8727                             */
5874 /******************************************************************/
5875 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
5876                                  struct bnx2x_phy *phy,
5877                                  u16 alarm_status_offset,
5878                                  u16 alarm_ctrl_offset)
5879 {
5880         u16 alarm_status, val;
5881         bnx2x_cl45_read(bp, phy,
5882                         MDIO_PMA_DEVAD, alarm_status_offset,
5883                         &alarm_status);
5884         bnx2x_cl45_read(bp, phy,
5885                         MDIO_PMA_DEVAD, alarm_status_offset,
5886                         &alarm_status);
5887         /* Mask or enable the fault event. */
5888         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
5889         if (alarm_status & (1<<0))
5890                 val &= ~(1<<0);
5891         else
5892                 val |= (1<<0);
5893         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
5894 }
5895 /******************************************************************/
5896 /*              common BCM8706/BCM8726 PHY SECTION                */
5897 /******************************************************************/
5898 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5899                                       struct link_params *params,
5900                                       struct link_vars *vars)
5901 {
5902         u8 link_up = 0;
5903         u16 val1, val2, rx_sd, pcs_status;
5904         struct bnx2x *bp = params->bp;
5905         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5906         /* Clear RX Alarm*/
5907         bnx2x_cl45_read(bp, phy,
5908                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5909
5910         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5911                              MDIO_PMA_REG_TX_ALARM_CTRL);
5912
5913         /* clear LASI indication*/
5914         bnx2x_cl45_read(bp, phy,
5915                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5916         bnx2x_cl45_read(bp, phy,
5917                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5918         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5919
5920         bnx2x_cl45_read(bp, phy,
5921                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5922         bnx2x_cl45_read(bp, phy,
5923                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5924         bnx2x_cl45_read(bp, phy,
5925                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5926         bnx2x_cl45_read(bp, phy,
5927                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5928
5929         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5930                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5931         /*
5932          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5933          * are set, or if the autoneg bit 1 is set
5934          */
5935         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5936         if (link_up) {
5937                 if (val2 & (1<<1))
5938                         vars->line_speed = SPEED_1000;
5939                 else
5940                         vars->line_speed = SPEED_10000;
5941                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5942                 vars->duplex = DUPLEX_FULL;
5943         }
5944
5945         /* Capture 10G link fault. Read twice to clear stale value. */
5946         if (vars->line_speed == SPEED_10000) {
5947                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5948                             MDIO_PMA_REG_TX_ALARM, &val1);
5949                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5950                             MDIO_PMA_REG_TX_ALARM, &val1);
5951                 if (val1 & (1<<0))
5952                         vars->fault_detected = 1;
5953         }
5954
5955         return link_up;
5956 }
5957
5958 /******************************************************************/
5959 /*                      BCM8706 PHY SECTION                       */
5960 /******************************************************************/
5961 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5962                                  struct link_params *params,
5963                                  struct link_vars *vars)
5964 {
5965         u32 tx_en_mode;
5966         u16 cnt, val, tmp1;
5967         struct bnx2x *bp = params->bp;
5968         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5969                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5970         /* HW reset */
5971         bnx2x_ext_phy_hw_reset(bp, params->port);
5972         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5973         bnx2x_wait_reset_complete(bp, phy, params);
5974
5975         /* Wait until fw is loaded */
5976         for (cnt = 0; cnt < 100; cnt++) {
5977                 bnx2x_cl45_read(bp, phy,
5978                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5979                 if (val)
5980                         break;
5981                 msleep(10);
5982         }
5983         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5984         if ((params->feature_config_flags &
5985              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5986                 u8 i;
5987                 u16 reg;
5988                 for (i = 0; i < 4; i++) {
5989                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5990                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5991                                    MDIO_XS_8706_REG_BANK_RX0);
5992                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5993                         /* Clear first 3 bits of the control */
5994                         val &= ~0x7;
5995                         /* Set control bits according to configuration */
5996                         val |= (phy->rx_preemphasis[i] & 0x7);
5997                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5998                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5999                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
6000                 }
6001         }
6002         /* Force speed */
6003         if (phy->req_line_speed == SPEED_10000) {
6004                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
6005
6006                 bnx2x_cl45_write(bp, phy,
6007                                  MDIO_PMA_DEVAD,
6008                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
6009                 bnx2x_cl45_write(bp, phy,
6010                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
6011                                  0);
6012                 /* Arm LASI for link and Tx fault. */
6013                 bnx2x_cl45_write(bp, phy,
6014                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 3);
6015         } else {
6016                 /* Force 1Gbps using autoneg with 1G advertisement */
6017
6018                 /* Allow CL37 through CL73 */
6019                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
6020                 bnx2x_cl45_write(bp, phy,
6021                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6022
6023                 /* Enable Full-Duplex advertisement on CL37 */
6024                 bnx2x_cl45_write(bp, phy,
6025                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
6026                 /* Enable CL37 AN */
6027                 bnx2x_cl45_write(bp, phy,
6028                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6029                 /* 1G support */
6030                 bnx2x_cl45_write(bp, phy,
6031                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6032
6033                 /* Enable clause 73 AN */
6034                 bnx2x_cl45_write(bp, phy,
6035                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6036                 bnx2x_cl45_write(bp, phy,
6037                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6038                                  0x0400);
6039                 bnx2x_cl45_write(bp, phy,
6040                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
6041                                  0x0004);
6042         }
6043         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
6044
6045         /*
6046          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
6047          * power mode, if TX Laser is disabled
6048          */
6049
6050         tx_en_mode = REG_RD(bp, params->shmem_base +
6051                             offsetof(struct shmem_region,
6052                                 dev_info.port_hw_config[params->port].sfp_ctrl))
6053                         & PORT_HW_CFG_TX_LASER_MASK;
6054
6055         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
6056                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
6057                 bnx2x_cl45_read(bp, phy,
6058                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
6059                 tmp1 |= 0x1;
6060                 bnx2x_cl45_write(bp, phy,
6061                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
6062         }
6063
6064         return 0;
6065 }
6066
6067 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
6068                                   struct link_params *params,
6069                                   struct link_vars *vars)
6070 {
6071         return bnx2x_8706_8726_read_status(phy, params, vars);
6072 }
6073
6074 /******************************************************************/
6075 /*                      BCM8726 PHY SECTION                       */
6076 /******************************************************************/
6077 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
6078                                        struct link_params *params)
6079 {
6080         struct bnx2x *bp = params->bp;
6081         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
6082         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
6083 }
6084
6085 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
6086                                          struct link_params *params)
6087 {
6088         struct bnx2x *bp = params->bp;
6089         /* Need to wait 100ms after reset */
6090         msleep(100);
6091
6092         /* Micro controller re-boot */
6093         bnx2x_cl45_write(bp, phy,
6094                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
6095
6096         /* Set soft reset */
6097         bnx2x_cl45_write(bp, phy,
6098                          MDIO_PMA_DEVAD,
6099                          MDIO_PMA_REG_GEN_CTRL,
6100                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6101
6102         bnx2x_cl45_write(bp, phy,
6103                          MDIO_PMA_DEVAD,
6104                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6105
6106         bnx2x_cl45_write(bp, phy,
6107                          MDIO_PMA_DEVAD,
6108                          MDIO_PMA_REG_GEN_CTRL,
6109                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6110
6111         /* wait for 150ms for microcode load */
6112         msleep(150);
6113
6114         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
6115         bnx2x_cl45_write(bp, phy,
6116                          MDIO_PMA_DEVAD,
6117                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6118
6119         msleep(200);
6120         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
6121 }
6122
6123 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
6124                                  struct link_params *params,
6125                                  struct link_vars *vars)
6126 {
6127         struct bnx2x *bp = params->bp;
6128         u16 val1;
6129         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
6130         if (link_up) {
6131                 bnx2x_cl45_read(bp, phy,
6132                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
6133                                 &val1);
6134                 if (val1 & (1<<15)) {
6135                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
6136                         link_up = 0;
6137                         vars->line_speed = 0;
6138                 }
6139         }
6140         return link_up;
6141 }
6142
6143
6144 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
6145                                   struct link_params *params,
6146                                   struct link_vars *vars)
6147 {
6148         struct bnx2x *bp = params->bp;
6149         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
6150
6151         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6152         bnx2x_wait_reset_complete(bp, phy, params);
6153
6154         bnx2x_8726_external_rom_boot(phy, params);
6155
6156         /*
6157          * Need to call module detected on initialization since the module
6158          * detection triggered by actual module insertion might occur before
6159          * driver is loaded, and when driver is loaded, it reset all
6160          * registers, including the transmitter
6161          */
6162         bnx2x_sfp_module_detection(phy, params);
6163
6164         if (phy->req_line_speed == SPEED_1000) {
6165                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
6166                 bnx2x_cl45_write(bp, phy,
6167                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
6168                 bnx2x_cl45_write(bp, phy,
6169                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
6170                 bnx2x_cl45_write(bp, phy,
6171                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
6172                 bnx2x_cl45_write(bp, phy,
6173                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6174                                  0x400);
6175         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
6176                    (phy->speed_cap_mask &
6177                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
6178                    ((phy->speed_cap_mask &
6179                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
6180                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
6181                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
6182                 /* Set Flow control */
6183                 bnx2x_ext_phy_set_pause(params, phy, vars);
6184                 bnx2x_cl45_write(bp, phy,
6185                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
6186                 bnx2x_cl45_write(bp, phy,
6187                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6188                 bnx2x_cl45_write(bp, phy,
6189                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
6190                 bnx2x_cl45_write(bp, phy,
6191                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6192                 bnx2x_cl45_write(bp, phy,
6193                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6194                 /*
6195                  * Enable RX-ALARM control to receive interrupt for 1G speed
6196                  * change
6197                  */
6198                 bnx2x_cl45_write(bp, phy,
6199                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
6200                 bnx2x_cl45_write(bp, phy,
6201                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6202                                  0x400);
6203
6204         } else { /* Default 10G. Set only LASI control */
6205                 bnx2x_cl45_write(bp, phy,
6206                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
6207         }
6208
6209         /* Set TX PreEmphasis if needed */
6210         if ((params->feature_config_flags &
6211              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
6212                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
6213                          "TX_CTRL2 0x%x\n",
6214                          phy->tx_preemphasis[0],
6215                          phy->tx_preemphasis[1]);
6216                 bnx2x_cl45_write(bp, phy,
6217                                  MDIO_PMA_DEVAD,
6218                                  MDIO_PMA_REG_8726_TX_CTRL1,
6219                                  phy->tx_preemphasis[0]);
6220
6221                 bnx2x_cl45_write(bp, phy,
6222                                  MDIO_PMA_DEVAD,
6223                                  MDIO_PMA_REG_8726_TX_CTRL2,
6224                                  phy->tx_preemphasis[1]);
6225         }
6226
6227         return 0;
6228
6229 }
6230
6231 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
6232                                   struct link_params *params)
6233 {
6234         struct bnx2x *bp = params->bp;
6235         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
6236         /* Set serial boot control for external load */
6237         bnx2x_cl45_write(bp, phy,
6238                          MDIO_PMA_DEVAD,
6239                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
6240 }
6241
6242 /******************************************************************/
6243 /*                      BCM8727 PHY SECTION                       */
6244 /******************************************************************/
6245
6246 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
6247                                     struct link_params *params, u8 mode)
6248 {
6249         struct bnx2x *bp = params->bp;
6250         u16 led_mode_bitmask = 0;
6251         u16 gpio_pins_bitmask = 0;
6252         u16 val;
6253         /* Only NOC flavor requires to set the LED specifically */
6254         if (!(phy->flags & FLAGS_NOC))
6255                 return;
6256         switch (mode) {
6257         case LED_MODE_FRONT_PANEL_OFF:
6258         case LED_MODE_OFF:
6259                 led_mode_bitmask = 0;
6260                 gpio_pins_bitmask = 0x03;
6261                 break;
6262         case LED_MODE_ON:
6263                 led_mode_bitmask = 0;
6264                 gpio_pins_bitmask = 0x02;
6265                 break;
6266         case LED_MODE_OPER:
6267                 led_mode_bitmask = 0x60;
6268                 gpio_pins_bitmask = 0x11;
6269                 break;
6270         }
6271         bnx2x_cl45_read(bp, phy,
6272                         MDIO_PMA_DEVAD,
6273                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
6274                         &val);
6275         val &= 0xff8f;
6276         val |= led_mode_bitmask;
6277         bnx2x_cl45_write(bp, phy,
6278                          MDIO_PMA_DEVAD,
6279                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
6280                          val);
6281         bnx2x_cl45_read(bp, phy,
6282                         MDIO_PMA_DEVAD,
6283                         MDIO_PMA_REG_8727_GPIO_CTRL,
6284                         &val);
6285         val &= 0xffe0;
6286         val |= gpio_pins_bitmask;
6287         bnx2x_cl45_write(bp, phy,
6288                          MDIO_PMA_DEVAD,
6289                          MDIO_PMA_REG_8727_GPIO_CTRL,
6290                          val);
6291 }
6292 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
6293                                 struct link_params *params) {
6294         u32 swap_val, swap_override;
6295         u8 port;
6296         /*
6297          * The PHY reset is controlled by GPIO 1. Fake the port number
6298          * to cancel the swap done in set_gpio()
6299          */
6300         struct bnx2x *bp = params->bp;
6301         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6302         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6303         port = (swap_val && swap_override) ^ 1;
6304         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6305                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6306 }
6307
6308 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
6309                                   struct link_params *params,
6310                                   struct link_vars *vars)
6311 {
6312         u32 tx_en_mode;
6313         u16 tmp1, val, mod_abs, tmp2;
6314         u16 rx_alarm_ctrl_val;
6315         u16 lasi_ctrl_val;
6316         struct bnx2x *bp = params->bp;
6317         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
6318
6319         bnx2x_wait_reset_complete(bp, phy, params);
6320         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
6321         /* Should be 0x6 to enable XS on Tx side. */
6322         lasi_ctrl_val = 0x0006;
6323
6324         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
6325         /* enable LASI */
6326         bnx2x_cl45_write(bp, phy,
6327                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6328                          rx_alarm_ctrl_val);
6329         bnx2x_cl45_write(bp, phy,
6330                          MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
6331                          0);
6332         bnx2x_cl45_write(bp, phy,
6333                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
6334
6335         /*
6336          * Initially configure MOD_ABS to interrupt when module is
6337          * presence( bit 8)
6338          */
6339         bnx2x_cl45_read(bp, phy,
6340                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
6341         /*
6342          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
6343          * When the EDC is off it locks onto a reference clock and avoids
6344          * becoming 'lost'
6345          */
6346         mod_abs &= ~(1<<8);
6347         if (!(phy->flags & FLAGS_NOC))
6348                 mod_abs &= ~(1<<9);
6349         bnx2x_cl45_write(bp, phy,
6350                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
6351
6352
6353         /* Make MOD_ABS give interrupt on change */
6354         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
6355                         &val);
6356         val |= (1<<12);
6357         if (phy->flags & FLAGS_NOC)
6358                 val |= (3<<5);
6359
6360         /*
6361          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
6362          * status which reflect SFP+ module over-current
6363          */
6364         if (!(phy->flags & FLAGS_NOC))
6365                 val &= 0xff8f; /* Reset bits 4-6 */
6366         bnx2x_cl45_write(bp, phy,
6367                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
6368
6369         bnx2x_8727_power_module(bp, phy, 1);
6370
6371         bnx2x_cl45_read(bp, phy,
6372                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6373
6374         bnx2x_cl45_read(bp, phy,
6375                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
6376
6377         /* Set option 1G speed */
6378         if (phy->req_line_speed == SPEED_1000) {
6379                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
6380                 bnx2x_cl45_write(bp, phy,
6381                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
6382                 bnx2x_cl45_write(bp, phy,
6383                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
6384                 bnx2x_cl45_read(bp, phy,
6385                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
6386                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
6387                 /*
6388                  * Power down the XAUI until link is up in case of dual-media
6389                  * and 1G
6390                  */
6391                 if (DUAL_MEDIA(params)) {
6392                         bnx2x_cl45_read(bp, phy,
6393                                         MDIO_PMA_DEVAD,
6394                                         MDIO_PMA_REG_8727_PCS_GP, &val);
6395                         val |= (3<<10);
6396                         bnx2x_cl45_write(bp, phy,
6397                                          MDIO_PMA_DEVAD,
6398                                          MDIO_PMA_REG_8727_PCS_GP, val);
6399                 }
6400         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
6401                    ((phy->speed_cap_mask &
6402                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
6403                    ((phy->speed_cap_mask &
6404                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
6405                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
6406
6407                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
6408                 bnx2x_cl45_write(bp, phy,
6409                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
6410                 bnx2x_cl45_write(bp, phy,
6411                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
6412         } else {
6413                 /*
6414                  * Since the 8727 has only single reset pin, need to set the 10G
6415                  * registers although it is default
6416                  */
6417                 bnx2x_cl45_write(bp, phy,
6418                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
6419                                  0x0020);
6420                 bnx2x_cl45_write(bp, phy,
6421                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
6422                 bnx2x_cl45_write(bp, phy,
6423                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6424                 bnx2x_cl45_write(bp, phy,
6425                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
6426                                  0x0008);
6427         }
6428
6429         /*
6430          * Set 2-wire transfer rate of SFP+ module EEPROM
6431          * to 100Khz since some DACs(direct attached cables) do
6432          * not work at 400Khz.
6433          */
6434         bnx2x_cl45_write(bp, phy,
6435                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
6436                          0xa001);
6437
6438         /* Set TX PreEmphasis if needed */
6439         if ((params->feature_config_flags &
6440              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
6441                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
6442                            phy->tx_preemphasis[0],
6443                            phy->tx_preemphasis[1]);
6444                 bnx2x_cl45_write(bp, phy,
6445                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
6446                                  phy->tx_preemphasis[0]);
6447
6448                 bnx2x_cl45_write(bp, phy,
6449                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
6450                                  phy->tx_preemphasis[1]);
6451         }
6452
6453         /*
6454          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
6455          * power mode, if TX Laser is disabled
6456          */
6457         tx_en_mode = REG_RD(bp, params->shmem_base +
6458                             offsetof(struct shmem_region,
6459                                 dev_info.port_hw_config[params->port].sfp_ctrl))
6460                         & PORT_HW_CFG_TX_LASER_MASK;
6461
6462         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
6463
6464                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
6465                 bnx2x_cl45_read(bp, phy,
6466                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
6467                 tmp2 |= 0x1000;
6468                 tmp2 &= 0xFFEF;
6469                 bnx2x_cl45_write(bp, phy,
6470                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
6471         }
6472
6473         return 0;
6474 }
6475
6476 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
6477                                       struct link_params *params)
6478 {
6479         struct bnx2x *bp = params->bp;
6480         u16 mod_abs, rx_alarm_status;
6481         u32 val = REG_RD(bp, params->shmem_base +
6482                              offsetof(struct shmem_region, dev_info.
6483                                       port_feature_config[params->port].
6484                                       config));
6485         bnx2x_cl45_read(bp, phy,
6486                         MDIO_PMA_DEVAD,
6487                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
6488         if (mod_abs & (1<<8)) {
6489
6490                 /* Module is absent */
6491                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
6492                             "show module is absent\n");
6493                 phy->media_type = ETH_PHY_NOT_PRESENT;
6494                 /*
6495                  * 1. Set mod_abs to detect next module
6496                  *    presence event
6497                  * 2. Set EDC off by setting OPTXLOS signal input to low
6498                  *    (bit 9).
6499                  *    When the EDC is off it locks onto a reference clock and
6500                  *    avoids becoming 'lost'.
6501                  */
6502                 mod_abs &= ~(1<<8);
6503                 if (!(phy->flags & FLAGS_NOC))
6504                         mod_abs &= ~(1<<9);
6505                 bnx2x_cl45_write(bp, phy,
6506                                  MDIO_PMA_DEVAD,
6507                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
6508
6509                 /*
6510                  * Clear RX alarm since it stays up as long as
6511                  * the mod_abs wasn't changed
6512                  */
6513                 bnx2x_cl45_read(bp, phy,
6514                                 MDIO_PMA_DEVAD,
6515                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
6516
6517         } else {
6518                 /* Module is present */
6519                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
6520                             "show module is present\n");
6521                 /*
6522                  * First disable transmitter, and if the module is ok, the
6523                  * module_detection will enable it
6524                  * 1. Set mod_abs to detect next module absent event ( bit 8)
6525                  * 2. Restore the default polarity of the OPRXLOS signal and
6526                  * this signal will then correctly indicate the presence or
6527                  * absence of the Rx signal. (bit 9)
6528                  */
6529                 mod_abs |= (1<<8);
6530                 if (!(phy->flags & FLAGS_NOC))
6531                         mod_abs |= (1<<9);
6532                 bnx2x_cl45_write(bp, phy,
6533                                  MDIO_PMA_DEVAD,
6534                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
6535
6536                 /*
6537                  * Clear RX alarm since it stays up as long as the mod_abs
6538                  * wasn't changed. This is need to be done before calling the
6539                  * module detection, otherwise it will clear* the link update
6540                  * alarm
6541                  */
6542                 bnx2x_cl45_read(bp, phy,
6543                                 MDIO_PMA_DEVAD,
6544                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
6545
6546
6547                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6548                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6549                         bnx2x_sfp_set_transmitter(params, phy, 0);
6550
6551                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
6552                         bnx2x_sfp_module_detection(phy, params);
6553                 else
6554                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
6555         }
6556
6557         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
6558                    rx_alarm_status);
6559         /* No need to check link status in case of module plugged in/out */
6560 }
6561
6562 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
6563                                  struct link_params *params,
6564                                  struct link_vars *vars)
6565
6566 {
6567         struct bnx2x *bp = params->bp;
6568         u8 link_up = 0, oc_port = params->port;
6569         u16 link_status = 0;
6570         u16 rx_alarm_status, lasi_ctrl, val1;
6571
6572         /* If PHY is not initialized, do not check link status */
6573         bnx2x_cl45_read(bp, phy,
6574                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
6575                         &lasi_ctrl);
6576         if (!lasi_ctrl)
6577                 return 0;
6578
6579         /* Check the LASI on Rx */
6580         bnx2x_cl45_read(bp, phy,
6581                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
6582                         &rx_alarm_status);
6583         vars->line_speed = 0;
6584         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
6585
6586         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
6587                              MDIO_PMA_REG_TX_ALARM_CTRL);
6588
6589         bnx2x_cl45_read(bp, phy,
6590                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6591
6592         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
6593
6594         /* Clear MSG-OUT */
6595         bnx2x_cl45_read(bp, phy,
6596                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6597
6598         /*
6599          * If a module is present and there is need to check
6600          * for over current
6601          */
6602         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
6603                 /* Check over-current using 8727 GPIO0 input*/
6604                 bnx2x_cl45_read(bp, phy,
6605                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
6606                                 &val1);
6607
6608                 if ((val1 & (1<<8)) == 0) {
6609                         if (!CHIP_IS_E1x(bp))
6610                                 oc_port = BP_PATH(bp) + (params->port << 1);
6611                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
6612                                        " on port %d\n", oc_port);
6613                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
6614                                             " been detected and the power to "
6615                                             "that SFP+ module has been removed"
6616                                             " to prevent failure of the card."
6617                                             " Please remove the SFP+ module and"
6618                                             " restart the system to clear this"
6619                                             " error.\n",
6620                          oc_port);
6621                         /* Disable all RX_ALARMs except for mod_abs */
6622                         bnx2x_cl45_write(bp, phy,
6623                                          MDIO_PMA_DEVAD,
6624                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
6625
6626                         bnx2x_cl45_read(bp, phy,
6627                                         MDIO_PMA_DEVAD,
6628                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6629                         /* Wait for module_absent_event */
6630                         val1 |= (1<<8);
6631                         bnx2x_cl45_write(bp, phy,
6632                                          MDIO_PMA_DEVAD,
6633                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
6634                         /* Clear RX alarm */
6635                         bnx2x_cl45_read(bp, phy,
6636                                 MDIO_PMA_DEVAD,
6637                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
6638                         return 0;
6639                 }
6640         } /* Over current check */
6641
6642         /* When module absent bit is set, check module */
6643         if (rx_alarm_status & (1<<5)) {
6644                 bnx2x_8727_handle_mod_abs(phy, params);
6645                 /* Enable all mod_abs and link detection bits */
6646                 bnx2x_cl45_write(bp, phy,
6647                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6648                                  ((1<<5) | (1<<2)));
6649         }
6650         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
6651         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
6652         /* If transmitter is disabled, ignore false link up indication */
6653         bnx2x_cl45_read(bp, phy,
6654                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6655         if (val1 & (1<<15)) {
6656                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
6657                 return 0;
6658         }
6659
6660         bnx2x_cl45_read(bp, phy,
6661                         MDIO_PMA_DEVAD,
6662                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
6663
6664         /*
6665          * Bits 0..2 --> speed detected,
6666          * Bits 13..15--> link is down
6667          */
6668         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
6669                 link_up = 1;
6670                 vars->line_speed = SPEED_10000;
6671                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
6672                            params->port);
6673         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
6674                 link_up = 1;
6675                 vars->line_speed = SPEED_1000;
6676                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
6677                            params->port);
6678         } else {
6679                 link_up = 0;
6680                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
6681                            params->port);
6682         }
6683
6684         /* Capture 10G link fault. */
6685         if (vars->line_speed == SPEED_10000) {
6686                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6687                             MDIO_PMA_REG_TX_ALARM, &val1);
6688
6689                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6690                             MDIO_PMA_REG_TX_ALARM, &val1);
6691
6692                 if (val1 & (1<<0)) {
6693                         vars->fault_detected = 1;
6694                 }
6695         }
6696
6697         if (link_up) {
6698                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6699                 vars->duplex = DUPLEX_FULL;
6700                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
6701         }
6702
6703         if ((DUAL_MEDIA(params)) &&
6704             (phy->req_line_speed == SPEED_1000)) {
6705                 bnx2x_cl45_read(bp, phy,
6706                                 MDIO_PMA_DEVAD,
6707                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
6708                 /*
6709                  * In case of dual-media board and 1G, power up the XAUI side,
6710                  * otherwise power it down. For 10G it is done automatically
6711                  */
6712                 if (link_up)
6713                         val1 &= ~(3<<10);
6714                 else
6715                         val1 |= (3<<10);
6716                 bnx2x_cl45_write(bp, phy,
6717                                  MDIO_PMA_DEVAD,
6718                                  MDIO_PMA_REG_8727_PCS_GP, val1);
6719         }
6720         return link_up;
6721 }
6722
6723 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
6724                                   struct link_params *params)
6725 {
6726         struct bnx2x *bp = params->bp;
6727         /* Disable Transmitter */
6728         bnx2x_sfp_set_transmitter(params, phy, 0);
6729         /* Clear LASI */
6730         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
6731
6732 }
6733
6734 /******************************************************************/
6735 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
6736 /******************************************************************/
6737 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
6738                                            struct link_params *params)
6739 {
6740         u16 val, fw_ver1, fw_ver2, cnt;
6741         u8 port;
6742         struct bnx2x *bp = params->bp;
6743
6744         port = params->port;
6745
6746         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6747         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
6748         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
6749         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6750         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
6751         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
6752         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
6753
6754         for (cnt = 0; cnt < 100; cnt++) {
6755                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6756                 if (val & 1)
6757                         break;
6758                 udelay(5);
6759         }
6760         if (cnt == 100) {
6761                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6762                 bnx2x_save_spirom_version(bp, port, 0,
6763                                           phy->ver_addr);
6764                 return;
6765         }
6766
6767
6768         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
6769         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
6770         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6771         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
6772         for (cnt = 0; cnt < 100; cnt++) {
6773                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6774                 if (val & 1)
6775                         break;
6776                 udelay(5);
6777         }
6778         if (cnt == 100) {
6779                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6780                 bnx2x_save_spirom_version(bp, port, 0,
6781                                           phy->ver_addr);
6782                 return;
6783         }
6784
6785         /* lower 16 bits of the register SPI_FW_STATUS */
6786         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
6787         /* upper 16 bits of register SPI_FW_STATUS */
6788         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
6789
6790         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
6791                                   phy->ver_addr);
6792 }
6793
6794 static void bnx2x_848xx_set_led(struct bnx2x *bp,
6795                                 struct bnx2x_phy *phy)
6796 {
6797         u16 val;
6798
6799         /* PHYC_CTL_LED_CTL */
6800         bnx2x_cl45_read(bp, phy,
6801                         MDIO_PMA_DEVAD,
6802                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
6803         val &= 0xFE00;
6804         val |= 0x0092;
6805
6806         bnx2x_cl45_write(bp, phy,
6807                          MDIO_PMA_DEVAD,
6808                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
6809
6810         bnx2x_cl45_write(bp, phy,
6811                          MDIO_PMA_DEVAD,
6812                          MDIO_PMA_REG_8481_LED1_MASK,
6813                          0x80);
6814
6815         bnx2x_cl45_write(bp, phy,
6816                          MDIO_PMA_DEVAD,
6817                          MDIO_PMA_REG_8481_LED2_MASK,
6818                          0x18);
6819
6820         /* Select activity source by Tx and Rx, as suggested by PHY AE */
6821         bnx2x_cl45_write(bp, phy,
6822                          MDIO_PMA_DEVAD,
6823                          MDIO_PMA_REG_8481_LED3_MASK,
6824                          0x0006);
6825
6826         /* Select the closest activity blink rate to that in 10/100/1000 */
6827         bnx2x_cl45_write(bp, phy,
6828                         MDIO_PMA_DEVAD,
6829                         MDIO_PMA_REG_8481_LED3_BLINK,
6830                         0);
6831
6832         bnx2x_cl45_read(bp, phy,
6833                         MDIO_PMA_DEVAD,
6834                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
6835         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6836
6837         bnx2x_cl45_write(bp, phy,
6838                          MDIO_PMA_DEVAD,
6839                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
6840
6841         /* 'Interrupt Mask' */
6842         bnx2x_cl45_write(bp, phy,
6843                          MDIO_AN_DEVAD,
6844                          0xFFFB, 0xFFFD);
6845 }
6846
6847 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
6848                                        struct link_params *params,
6849                                        struct link_vars *vars)
6850 {
6851         struct bnx2x *bp = params->bp;
6852         u16 autoneg_val, an_1000_val, an_10_100_val;
6853         u16 tmp_req_line_speed;
6854
6855         tmp_req_line_speed = phy->req_line_speed;
6856         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6857                 if (phy->req_line_speed == SPEED_10000)
6858                         phy->req_line_speed = SPEED_AUTO_NEG;
6859
6860         /*
6861          * This phy uses the NIG latch mechanism since link indication
6862          * arrives through its LED4 and not via its LASI signal, so we
6863          * get steady signal instead of clear on read
6864          */
6865         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6866                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
6867
6868         bnx2x_cl45_write(bp, phy,
6869                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6870
6871         bnx2x_848xx_set_led(bp, phy);
6872
6873         /* set 1000 speed advertisement */
6874         bnx2x_cl45_read(bp, phy,
6875                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6876                         &an_1000_val);
6877
6878         bnx2x_ext_phy_set_pause(params, phy, vars);
6879         bnx2x_cl45_read(bp, phy,
6880                         MDIO_AN_DEVAD,
6881                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
6882                         &an_10_100_val);
6883         bnx2x_cl45_read(bp, phy,
6884                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6885                         &autoneg_val);
6886         /* Disable forced speed */
6887         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6888         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6889
6890         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6891              (phy->speed_cap_mask &
6892              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6893             (phy->req_line_speed == SPEED_1000)) {
6894                 an_1000_val |= (1<<8);
6895                 autoneg_val |= (1<<9 | 1<<12);
6896                 if (phy->req_duplex == DUPLEX_FULL)
6897                         an_1000_val |= (1<<9);
6898                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6899         } else
6900                 an_1000_val &= ~((1<<8) | (1<<9));
6901
6902         bnx2x_cl45_write(bp, phy,
6903                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6904                          an_1000_val);
6905
6906         /* set 10 speed advertisement */
6907         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6908              (phy->speed_cap_mask &
6909              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6910               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6911                 an_10_100_val |= (1<<7);
6912                 /* Enable autoneg and restart autoneg for legacy speeds */
6913                 autoneg_val |= (1<<9 | 1<<12);
6914
6915                 if (phy->req_duplex == DUPLEX_FULL)
6916                         an_10_100_val |= (1<<8);
6917                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6918         }
6919         /* set 10 speed advertisement */
6920         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6921             (phy->speed_cap_mask &
6922           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6923            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6924                 an_10_100_val |= (1<<5);
6925                 autoneg_val |= (1<<9 | 1<<12);
6926                 if (phy->req_duplex == DUPLEX_FULL)
6927                         an_10_100_val |= (1<<6);
6928                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6929         }
6930
6931         /* Only 10/100 are allowed to work in FORCE mode */
6932         if (phy->req_line_speed == SPEED_100) {
6933                 autoneg_val |= (1<<13);
6934                 /* Enabled AUTO-MDIX when autoneg is disabled */
6935                 bnx2x_cl45_write(bp, phy,
6936                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6937                                  (1<<15 | 1<<9 | 7<<0));
6938                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6939         }
6940         if (phy->req_line_speed == SPEED_10) {
6941                 /* Enabled AUTO-MDIX when autoneg is disabled */
6942                 bnx2x_cl45_write(bp, phy,
6943                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6944                                  (1<<15 | 1<<9 | 7<<0));
6945                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6946         }
6947
6948         bnx2x_cl45_write(bp, phy,
6949                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6950                          an_10_100_val);
6951
6952         if (phy->req_duplex == DUPLEX_FULL)
6953                 autoneg_val |= (1<<8);
6954
6955         bnx2x_cl45_write(bp, phy,
6956                          MDIO_AN_DEVAD,
6957                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6958
6959         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6960             (phy->speed_cap_mask &
6961              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6962                 (phy->req_line_speed == SPEED_10000)) {
6963                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
6964                         /* Restart autoneg for 10G*/
6965
6966                         bnx2x_cl45_write(bp, phy,
6967                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6968                                  0x3200);
6969         } else if (phy->req_line_speed != SPEED_10 &&
6970                    phy->req_line_speed != SPEED_100) {
6971                 bnx2x_cl45_write(bp, phy,
6972                                  MDIO_AN_DEVAD,
6973                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6974                                  1);
6975         }
6976         /* Save spirom version */
6977         bnx2x_save_848xx_spirom_version(phy, params);
6978
6979         phy->req_line_speed = tmp_req_line_speed;
6980
6981         return 0;
6982 }
6983
6984 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
6985                                   struct link_params *params,
6986                                   struct link_vars *vars)
6987 {
6988         struct bnx2x *bp = params->bp;
6989         /* Restore normal power mode*/
6990         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6991                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6992
6993         /* HW reset */
6994         bnx2x_ext_phy_hw_reset(bp, params->port);
6995         bnx2x_wait_reset_complete(bp, phy, params);
6996
6997         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6998         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6999 }
7000
7001
7002 #define PHY84833_HDSHK_WAIT 300
7003 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
7004                                    struct link_params *params,
7005                                    struct link_vars *vars)
7006 {
7007         u32 idx;
7008         u16 val;
7009         u16 data = 0x01b1;
7010         struct bnx2x *bp = params->bp;
7011         /* Do pair swap */
7012
7013
7014         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
7015         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7016                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
7017                         PHY84833_CMD_OPEN_OVERRIDE);
7018         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
7019                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
7020                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
7021                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
7022                         break;
7023                 msleep(1);
7024         }
7025         if (idx >= PHY84833_HDSHK_WAIT) {
7026                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
7027                 return -EINVAL;
7028         }
7029
7030         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7031                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
7032                         data);
7033         /* Issue pair swap command */
7034         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7035                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
7036                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
7037         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
7038                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
7039                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
7040                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
7041                         (val == PHY84833_CMD_COMPLETE_ERROR))
7042                         break;
7043                 msleep(1);
7044         }
7045         if ((idx >= PHY84833_HDSHK_WAIT) ||
7046                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
7047                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
7048                 return -EINVAL;
7049         }
7050         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7051                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
7052                         PHY84833_CMD_CLEAR_COMPLETE);
7053         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
7054         return 0;
7055 }
7056
7057 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
7058                                    struct link_params *params,
7059                                    struct link_vars *vars)
7060 {
7061         struct bnx2x *bp = params->bp;
7062         u8 port, initialize = 1;
7063         u16 val;
7064         u16 temp;
7065         u32 actual_phy_selection, cms_enable;
7066         int rc = 0;
7067
7068         msleep(1);
7069
7070         if (!(CHIP_IS_E1(bp)))
7071                 port = BP_PATH(bp);
7072         else
7073                 port = params->port;
7074
7075         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
7076                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
7077                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7078                                port);
7079         } else {
7080                 bnx2x_cl45_write(bp, phy,
7081                                 MDIO_PMA_DEVAD,
7082                                 MDIO_PMA_REG_CTRL, 0x8000);
7083         }
7084
7085         bnx2x_wait_reset_complete(bp, phy, params);
7086         /* Wait for GPHY to come out of reset */
7087         msleep(50);
7088
7089         /* Bring PHY out of super isolate mode */
7090         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
7091                 bnx2x_cl45_read(bp, phy,
7092                                 MDIO_CTL_DEVAD,
7093                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
7094                 val &= ~MDIO_84833_SUPER_ISOLATE;
7095                 bnx2x_cl45_write(bp, phy,
7096                                 MDIO_CTL_DEVAD,
7097                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
7098                 bnx2x_wait_reset_complete(bp, phy, params);
7099         }
7100
7101         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
7102                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
7103
7104         /*
7105          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
7106          */
7107         temp = vars->line_speed;
7108         vars->line_speed = SPEED_10000;
7109         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
7110         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
7111         vars->line_speed = temp;
7112
7113         /* Set dual-media configuration according to configuration */
7114
7115         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
7116                         MDIO_CTL_REG_84823_MEDIA, &val);
7117         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
7118                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
7119                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
7120                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
7121                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
7122         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
7123                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
7124
7125         actual_phy_selection = bnx2x_phy_selection(params);
7126
7127         switch (actual_phy_selection) {
7128         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7129                 /* Do nothing. Essentially this is like the priority copper */
7130                 break;
7131         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7132                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
7133                 break;
7134         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7135                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
7136                 break;
7137         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7138                 /* Do nothing here. The first PHY won't be initialized at all */
7139                 break;
7140         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7141                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
7142                 initialize = 0;
7143                 break;
7144         }
7145         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
7146                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
7147
7148         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7149                          MDIO_CTL_REG_84823_MEDIA, val);
7150         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
7151                    params->multi_phy_config, val);
7152
7153         if (initialize)
7154                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
7155         else
7156                 bnx2x_save_848xx_spirom_version(phy, params);
7157         cms_enable = REG_RD(bp, params->shmem_base +
7158                         offsetof(struct shmem_region,
7159                         dev_info.port_hw_config[params->port].default_cfg)) &
7160                         PORT_HW_CFG_ENABLE_CMS_MASK;
7161
7162         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
7163                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
7164         if (cms_enable)
7165                 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
7166         else
7167                 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
7168         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
7169                 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
7170
7171
7172         return rc;
7173 }
7174
7175 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
7176                                   struct link_params *params,
7177                                   struct link_vars *vars)
7178 {
7179         struct bnx2x *bp = params->bp;
7180         u16 val, val1, val2;
7181         u8 link_up = 0;
7182
7183
7184         /* Check 10G-BaseT link status */
7185         /* Check PMD signal ok */
7186         bnx2x_cl45_read(bp, phy,
7187                         MDIO_AN_DEVAD, 0xFFFA, &val1);
7188         bnx2x_cl45_read(bp, phy,
7189                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
7190                         &val2);
7191         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
7192
7193         /* Check link 10G */
7194         if (val2 & (1<<11)) {
7195                 vars->line_speed = SPEED_10000;
7196                 vars->duplex = DUPLEX_FULL;
7197                 link_up = 1;
7198                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7199         } else { /* Check Legacy speed link */
7200                 u16 legacy_status, legacy_speed;
7201
7202                 /* Enable expansion register 0x42 (Operation mode status) */
7203                 bnx2x_cl45_write(bp, phy,
7204                                  MDIO_AN_DEVAD,
7205                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
7206
7207                 /* Get legacy speed operation status */
7208                 bnx2x_cl45_read(bp, phy,
7209                                 MDIO_AN_DEVAD,
7210                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
7211                                 &legacy_status);
7212
7213                 DP(NETIF_MSG_LINK, "Legacy speed status"
7214                              " = 0x%x\n", legacy_status);
7215                 link_up = ((legacy_status & (1<<11)) == (1<<11));
7216                 if (link_up) {
7217                         legacy_speed = (legacy_status & (3<<9));
7218                         if (legacy_speed == (0<<9))
7219                                 vars->line_speed = SPEED_10;
7220                         else if (legacy_speed == (1<<9))
7221                                 vars->line_speed = SPEED_100;
7222                         else if (legacy_speed == (2<<9))
7223                                 vars->line_speed = SPEED_1000;
7224                         else /* Should not happen */
7225                                 vars->line_speed = 0;
7226
7227                         if (legacy_status & (1<<8))
7228                                 vars->duplex = DUPLEX_FULL;
7229                         else
7230                                 vars->duplex = DUPLEX_HALF;
7231
7232                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
7233                                    " is_duplex_full= %d\n", vars->line_speed,
7234                                    (vars->duplex == DUPLEX_FULL));
7235                         /* Check legacy speed AN resolution */
7236                         bnx2x_cl45_read(bp, phy,
7237                                         MDIO_AN_DEVAD,
7238                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
7239                                         &val);
7240                         if (val & (1<<5))
7241                                 vars->link_status |=
7242                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7243                         bnx2x_cl45_read(bp, phy,
7244                                         MDIO_AN_DEVAD,
7245                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
7246                                         &val);
7247                         if ((val & (1<<0)) == 0)
7248                                 vars->link_status |=
7249                                         LINK_STATUS_PARALLEL_DETECTION_USED;
7250                 }
7251         }
7252         if (link_up) {
7253                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
7254                            vars->line_speed);
7255                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7256         }
7257
7258         return link_up;
7259 }
7260
7261
7262 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
7263 {
7264         int status = 0;
7265         u32 spirom_ver;
7266         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
7267         status = bnx2x_format_ver(spirom_ver, str, len);
7268         return status;
7269 }
7270
7271 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
7272                                 struct link_params *params)
7273 {
7274         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
7275                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
7276         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
7277                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
7278 }
7279
7280 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
7281                                         struct link_params *params)
7282 {
7283         bnx2x_cl45_write(params->bp, phy,
7284                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7285         bnx2x_cl45_write(params->bp, phy,
7286                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
7287 }
7288
7289 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
7290                                    struct link_params *params)
7291 {
7292         struct bnx2x *bp = params->bp;
7293         u8 port;
7294
7295         if (!(CHIP_IS_E1(bp)))
7296                 port = BP_PATH(bp);
7297         else
7298                 port = params->port;
7299
7300         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
7301                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
7302                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
7303                                port);
7304         } else {
7305                 bnx2x_cl45_write(bp, phy,
7306                                 MDIO_PMA_DEVAD,
7307                                 MDIO_PMA_REG_CTRL, 0x800);
7308         }
7309 }
7310
7311 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
7312                                      struct link_params *params, u8 mode)
7313 {
7314         struct bnx2x *bp = params->bp;
7315         u16 val;
7316         u8 port;
7317
7318         if (!(CHIP_IS_E1(bp)))
7319                 port = BP_PATH(bp);
7320         else
7321                 port = params->port;
7322
7323         switch (mode) {
7324         case LED_MODE_OFF:
7325
7326                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
7327
7328                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
7329                     SHARED_HW_CFG_LED_EXTPHY1) {
7330
7331                         /* Set LED masks */
7332                         bnx2x_cl45_write(bp, phy,
7333                                         MDIO_PMA_DEVAD,
7334                                         MDIO_PMA_REG_8481_LED1_MASK,
7335                                         0x0);
7336
7337                         bnx2x_cl45_write(bp, phy,
7338                                         MDIO_PMA_DEVAD,
7339                                         MDIO_PMA_REG_8481_LED2_MASK,
7340                                         0x0);
7341
7342                         bnx2x_cl45_write(bp, phy,
7343                                         MDIO_PMA_DEVAD,
7344                                         MDIO_PMA_REG_8481_LED3_MASK,
7345                                         0x0);
7346
7347                         bnx2x_cl45_write(bp, phy,
7348                                         MDIO_PMA_DEVAD,
7349                                         MDIO_PMA_REG_8481_LED5_MASK,
7350                                         0x0);
7351
7352                 } else {
7353                         bnx2x_cl45_write(bp, phy,
7354                                          MDIO_PMA_DEVAD,
7355                                          MDIO_PMA_REG_8481_LED1_MASK,
7356                                          0x0);
7357                 }
7358                 break;
7359         case LED_MODE_FRONT_PANEL_OFF:
7360
7361                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
7362                    port);
7363
7364                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
7365                     SHARED_HW_CFG_LED_EXTPHY1) {
7366
7367                         /* Set LED masks */
7368                         bnx2x_cl45_write(bp, phy,
7369                                          MDIO_PMA_DEVAD,
7370                                          MDIO_PMA_REG_8481_LED1_MASK,
7371                                          0x0);
7372
7373                         bnx2x_cl45_write(bp, phy,
7374                                          MDIO_PMA_DEVAD,
7375                                          MDIO_PMA_REG_8481_LED2_MASK,
7376                                          0x0);
7377
7378                         bnx2x_cl45_write(bp, phy,
7379                                          MDIO_PMA_DEVAD,
7380                                          MDIO_PMA_REG_8481_LED3_MASK,
7381                                          0x0);
7382
7383                         bnx2x_cl45_write(bp, phy,
7384                                          MDIO_PMA_DEVAD,
7385                                          MDIO_PMA_REG_8481_LED5_MASK,
7386                                          0x20);
7387
7388                 } else {
7389                         bnx2x_cl45_write(bp, phy,
7390                                          MDIO_PMA_DEVAD,
7391                                          MDIO_PMA_REG_8481_LED1_MASK,
7392                                          0x0);
7393                 }
7394                 break;
7395         case LED_MODE_ON:
7396
7397                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
7398
7399                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
7400                     SHARED_HW_CFG_LED_EXTPHY1) {
7401                         /* Set control reg */
7402                         bnx2x_cl45_read(bp, phy,
7403                                         MDIO_PMA_DEVAD,
7404                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
7405                                         &val);
7406                         val &= 0x8000;
7407                         val |= 0x2492;
7408
7409                         bnx2x_cl45_write(bp, phy,
7410                                          MDIO_PMA_DEVAD,
7411                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
7412                                          val);
7413
7414                         /* Set LED masks */
7415                         bnx2x_cl45_write(bp, phy,
7416                                          MDIO_PMA_DEVAD,
7417                                          MDIO_PMA_REG_8481_LED1_MASK,
7418                                          0x0);
7419
7420                         bnx2x_cl45_write(bp, phy,
7421                                          MDIO_PMA_DEVAD,
7422                                          MDIO_PMA_REG_8481_LED2_MASK,
7423                                          0x20);
7424
7425                         bnx2x_cl45_write(bp, phy,
7426                                          MDIO_PMA_DEVAD,
7427                                          MDIO_PMA_REG_8481_LED3_MASK,
7428                                          0x20);
7429
7430                         bnx2x_cl45_write(bp, phy,
7431                                          MDIO_PMA_DEVAD,
7432                                          MDIO_PMA_REG_8481_LED5_MASK,
7433                                          0x0);
7434                 } else {
7435                         bnx2x_cl45_write(bp, phy,
7436                                          MDIO_PMA_DEVAD,
7437                                          MDIO_PMA_REG_8481_LED1_MASK,
7438                                          0x20);
7439                 }
7440                 break;
7441
7442         case LED_MODE_OPER:
7443
7444                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
7445
7446                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
7447                     SHARED_HW_CFG_LED_EXTPHY1) {
7448
7449                         /* Set control reg */
7450                         bnx2x_cl45_read(bp, phy,
7451                                         MDIO_PMA_DEVAD,
7452                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
7453                                         &val);
7454
7455                         if (!((val &
7456                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
7457                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
7458                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
7459                                 bnx2x_cl45_write(bp, phy,
7460                                                  MDIO_PMA_DEVAD,
7461                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
7462                                                  0xa492);
7463                         }
7464
7465                         /* Set LED masks */
7466                         bnx2x_cl45_write(bp, phy,
7467                                          MDIO_PMA_DEVAD,
7468                                          MDIO_PMA_REG_8481_LED1_MASK,
7469                                          0x10);
7470
7471                         bnx2x_cl45_write(bp, phy,
7472                                          MDIO_PMA_DEVAD,
7473                                          MDIO_PMA_REG_8481_LED2_MASK,
7474                                          0x80);
7475
7476                         bnx2x_cl45_write(bp, phy,
7477                                          MDIO_PMA_DEVAD,
7478                                          MDIO_PMA_REG_8481_LED3_MASK,
7479                                          0x98);
7480
7481                         bnx2x_cl45_write(bp, phy,
7482                                          MDIO_PMA_DEVAD,
7483                                          MDIO_PMA_REG_8481_LED5_MASK,
7484                                          0x40);
7485
7486                 } else {
7487                         bnx2x_cl45_write(bp, phy,
7488                                          MDIO_PMA_DEVAD,
7489                                          MDIO_PMA_REG_8481_LED1_MASK,
7490                                          0x80);
7491
7492                         /* Tell LED3 to blink on source */
7493                         bnx2x_cl45_read(bp, phy,
7494                                         MDIO_PMA_DEVAD,
7495                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
7496                                         &val);
7497                         val &= ~(7<<6);
7498                         val |= (1<<6); /* A83B[8:6]= 1 */
7499                         bnx2x_cl45_write(bp, phy,
7500                                          MDIO_PMA_DEVAD,
7501                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
7502                                          val);
7503                 }
7504                 break;
7505         }
7506 }
7507 /******************************************************************/
7508 /*                      SFX7101 PHY SECTION                       */
7509 /******************************************************************/
7510 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
7511                                        struct link_params *params)
7512 {
7513         struct bnx2x *bp = params->bp;
7514         /* SFX7101_XGXS_TEST1 */
7515         bnx2x_cl45_write(bp, phy,
7516                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
7517 }
7518
7519 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
7520                                   struct link_params *params,
7521                                   struct link_vars *vars)
7522 {
7523         u16 fw_ver1, fw_ver2, val;
7524         struct bnx2x *bp = params->bp;
7525         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
7526
7527         /* Restore normal power mode*/
7528         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7529                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7530         /* HW reset */
7531         bnx2x_ext_phy_hw_reset(bp, params->port);
7532         bnx2x_wait_reset_complete(bp, phy, params);
7533
7534         bnx2x_cl45_write(bp, phy,
7535                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
7536         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
7537         bnx2x_cl45_write(bp, phy,
7538                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
7539
7540         bnx2x_ext_phy_set_pause(params, phy, vars);
7541         /* Restart autoneg */
7542         bnx2x_cl45_read(bp, phy,
7543                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
7544         val |= 0x200;
7545         bnx2x_cl45_write(bp, phy,
7546                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
7547
7548         /* Save spirom version */
7549         bnx2x_cl45_read(bp, phy,
7550                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
7551
7552         bnx2x_cl45_read(bp, phy,
7553                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
7554         bnx2x_save_spirom_version(bp, params->port,
7555                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
7556         return 0;
7557 }
7558
7559 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
7560                                  struct link_params *params,
7561                                  struct link_vars *vars)
7562 {
7563         struct bnx2x *bp = params->bp;
7564         u8 link_up;
7565         u16 val1, val2;
7566         bnx2x_cl45_read(bp, phy,
7567                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
7568         bnx2x_cl45_read(bp, phy,
7569                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
7570         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
7571                    val2, val1);
7572         bnx2x_cl45_read(bp, phy,
7573                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7574         bnx2x_cl45_read(bp, phy,
7575                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7576         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
7577                    val2, val1);
7578         link_up = ((val1 & 4) == 4);
7579         /* if link is up print the AN outcome of the SFX7101 PHY */
7580         if (link_up) {
7581                 bnx2x_cl45_read(bp, phy,
7582                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
7583                                 &val2);
7584                 vars->line_speed = SPEED_10000;
7585                 vars->duplex = DUPLEX_FULL;
7586                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
7587                            val2, (val2 & (1<<14)));
7588                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7589                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7590         }
7591         return link_up;
7592 }
7593
7594 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
7595 {
7596         if (*len < 5)
7597                 return -EINVAL;
7598         str[0] = (spirom_ver & 0xFF);
7599         str[1] = (spirom_ver & 0xFF00) >> 8;
7600         str[2] = (spirom_ver & 0xFF0000) >> 16;
7601         str[3] = (spirom_ver & 0xFF000000) >> 24;
7602         str[4] = '\0';
7603         *len -= 5;
7604         return 0;
7605 }
7606
7607 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
7608 {
7609         u16 val, cnt;
7610
7611         bnx2x_cl45_read(bp, phy,
7612                         MDIO_PMA_DEVAD,
7613                         MDIO_PMA_REG_7101_RESET, &val);
7614
7615         for (cnt = 0; cnt < 10; cnt++) {
7616                 msleep(50);
7617                 /* Writes a self-clearing reset */
7618                 bnx2x_cl45_write(bp, phy,
7619                                  MDIO_PMA_DEVAD,
7620                                  MDIO_PMA_REG_7101_RESET,
7621                                  (val | (1<<15)));
7622                 /* Wait for clear */
7623                 bnx2x_cl45_read(bp, phy,
7624                                 MDIO_PMA_DEVAD,
7625                                 MDIO_PMA_REG_7101_RESET, &val);
7626
7627                 if ((val & (1<<15)) == 0)
7628                         break;
7629         }
7630 }
7631
7632 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
7633                                 struct link_params *params) {
7634         /* Low power mode is controlled by GPIO 2 */
7635         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
7636                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7637         /* The PHY reset is controlled by GPIO 1 */
7638         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
7639                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7640 }
7641
7642 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
7643                                     struct link_params *params, u8 mode)
7644 {
7645         u16 val = 0;
7646         struct bnx2x *bp = params->bp;
7647         switch (mode) {
7648         case LED_MODE_FRONT_PANEL_OFF:
7649         case LED_MODE_OFF:
7650                 val = 2;
7651                 break;
7652         case LED_MODE_ON:
7653                 val = 1;
7654                 break;
7655         case LED_MODE_OPER:
7656                 val = 0;
7657                 break;
7658         }
7659         bnx2x_cl45_write(bp, phy,
7660                          MDIO_PMA_DEVAD,
7661                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
7662                          val);
7663 }
7664
7665 /******************************************************************/
7666 /*                      STATIC PHY DECLARATION                    */
7667 /******************************************************************/
7668
7669 static struct bnx2x_phy phy_null = {
7670         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
7671         .addr           = 0,
7672         .def_md_devad   = 0,
7673         .flags          = FLAGS_INIT_XGXS_FIRST,
7674         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7675         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7676         .mdio_ctrl      = 0,
7677         .supported      = 0,
7678         .media_type     = ETH_PHY_NOT_PRESENT,
7679         .ver_addr       = 0,
7680         .req_flow_ctrl  = 0,
7681         .req_line_speed = 0,
7682         .speed_cap_mask = 0,
7683         .req_duplex     = 0,
7684         .rsrv           = 0,
7685         .config_init    = (config_init_t)NULL,
7686         .read_status    = (read_status_t)NULL,
7687         .link_reset     = (link_reset_t)NULL,
7688         .config_loopback = (config_loopback_t)NULL,
7689         .format_fw_ver  = (format_fw_ver_t)NULL,
7690         .hw_reset       = (hw_reset_t)NULL,
7691         .set_link_led   = (set_link_led_t)NULL,
7692         .phy_specific_func = (phy_specific_func_t)NULL
7693 };
7694
7695 static struct bnx2x_phy phy_serdes = {
7696         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
7697         .addr           = 0xff,
7698         .def_md_devad   = 0,
7699         .flags          = 0,
7700         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7701         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7702         .mdio_ctrl      = 0,
7703         .supported      = (SUPPORTED_10baseT_Half |
7704                            SUPPORTED_10baseT_Full |
7705                            SUPPORTED_100baseT_Half |
7706                            SUPPORTED_100baseT_Full |
7707                            SUPPORTED_1000baseT_Full |
7708                            SUPPORTED_2500baseX_Full |
7709                            SUPPORTED_TP |
7710                            SUPPORTED_Autoneg |
7711                            SUPPORTED_Pause |
7712                            SUPPORTED_Asym_Pause),
7713         .media_type     = ETH_PHY_BASE_T,
7714         .ver_addr       = 0,
7715         .req_flow_ctrl  = 0,
7716         .req_line_speed = 0,
7717         .speed_cap_mask = 0,
7718         .req_duplex     = 0,
7719         .rsrv           = 0,
7720         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
7721         .read_status    = (read_status_t)bnx2x_link_settings_status,
7722         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7723         .config_loopback = (config_loopback_t)NULL,
7724         .format_fw_ver  = (format_fw_ver_t)NULL,
7725         .hw_reset       = (hw_reset_t)NULL,
7726         .set_link_led   = (set_link_led_t)NULL,
7727         .phy_specific_func = (phy_specific_func_t)NULL
7728 };
7729
7730 static struct bnx2x_phy phy_xgxs = {
7731         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
7732         .addr           = 0xff,
7733         .def_md_devad   = 0,
7734         .flags          = 0,
7735         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7736         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7737         .mdio_ctrl      = 0,
7738         .supported      = (SUPPORTED_10baseT_Half |
7739                            SUPPORTED_10baseT_Full |
7740                            SUPPORTED_100baseT_Half |
7741                            SUPPORTED_100baseT_Full |
7742                            SUPPORTED_1000baseT_Full |
7743                            SUPPORTED_2500baseX_Full |
7744                            SUPPORTED_10000baseT_Full |
7745                            SUPPORTED_FIBRE |
7746                            SUPPORTED_Autoneg |
7747                            SUPPORTED_Pause |
7748                            SUPPORTED_Asym_Pause),
7749         .media_type     = ETH_PHY_CX4,
7750         .ver_addr       = 0,
7751         .req_flow_ctrl  = 0,
7752         .req_line_speed = 0,
7753         .speed_cap_mask = 0,
7754         .req_duplex     = 0,
7755         .rsrv           = 0,
7756         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
7757         .read_status    = (read_status_t)bnx2x_link_settings_status,
7758         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7759         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
7760         .format_fw_ver  = (format_fw_ver_t)NULL,
7761         .hw_reset       = (hw_reset_t)NULL,
7762         .set_link_led   = (set_link_led_t)NULL,
7763         .phy_specific_func = (phy_specific_func_t)NULL
7764 };
7765
7766 static struct bnx2x_phy phy_7101 = {
7767         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7768         .addr           = 0xff,
7769         .def_md_devad   = 0,
7770         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7771         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7772         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7773         .mdio_ctrl      = 0,
7774         .supported      = (SUPPORTED_10000baseT_Full |
7775                            SUPPORTED_TP |
7776                            SUPPORTED_Autoneg |
7777                            SUPPORTED_Pause |
7778                            SUPPORTED_Asym_Pause),
7779         .media_type     = ETH_PHY_BASE_T,
7780         .ver_addr       = 0,
7781         .req_flow_ctrl  = 0,
7782         .req_line_speed = 0,
7783         .speed_cap_mask = 0,
7784         .req_duplex     = 0,
7785         .rsrv           = 0,
7786         .config_init    = (config_init_t)bnx2x_7101_config_init,
7787         .read_status    = (read_status_t)bnx2x_7101_read_status,
7788         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7789         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
7790         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
7791         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
7792         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
7793         .phy_specific_func = (phy_specific_func_t)NULL
7794 };
7795 static struct bnx2x_phy phy_8073 = {
7796         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
7797         .addr           = 0xff,
7798         .def_md_devad   = 0,
7799         .flags          = FLAGS_HW_LOCK_REQUIRED,
7800         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7801         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7802         .mdio_ctrl      = 0,
7803         .supported      = (SUPPORTED_10000baseT_Full |
7804                            SUPPORTED_2500baseX_Full |
7805                            SUPPORTED_1000baseT_Full |
7806                            SUPPORTED_FIBRE |
7807                            SUPPORTED_Autoneg |
7808                            SUPPORTED_Pause |
7809                            SUPPORTED_Asym_Pause),
7810         .media_type     = ETH_PHY_KR,
7811         .ver_addr       = 0,
7812         .req_flow_ctrl  = 0,
7813         .req_line_speed = 0,
7814         .speed_cap_mask = 0,
7815         .req_duplex     = 0,
7816         .rsrv           = 0,
7817         .config_init    = (config_init_t)bnx2x_8073_config_init,
7818         .read_status    = (read_status_t)bnx2x_8073_read_status,
7819         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
7820         .config_loopback = (config_loopback_t)NULL,
7821         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7822         .hw_reset       = (hw_reset_t)NULL,
7823         .set_link_led   = (set_link_led_t)NULL,
7824         .phy_specific_func = (phy_specific_func_t)NULL
7825 };
7826 static struct bnx2x_phy phy_8705 = {
7827         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
7828         .addr           = 0xff,
7829         .def_md_devad   = 0,
7830         .flags          = FLAGS_INIT_XGXS_FIRST,
7831         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7832         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7833         .mdio_ctrl      = 0,
7834         .supported      = (SUPPORTED_10000baseT_Full |
7835                            SUPPORTED_FIBRE |
7836                            SUPPORTED_Pause |
7837                            SUPPORTED_Asym_Pause),
7838         .media_type     = ETH_PHY_XFP_FIBER,
7839         .ver_addr       = 0,
7840         .req_flow_ctrl  = 0,
7841         .req_line_speed = 0,
7842         .speed_cap_mask = 0,
7843         .req_duplex     = 0,
7844         .rsrv           = 0,
7845         .config_init    = (config_init_t)bnx2x_8705_config_init,
7846         .read_status    = (read_status_t)bnx2x_8705_read_status,
7847         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7848         .config_loopback = (config_loopback_t)NULL,
7849         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
7850         .hw_reset       = (hw_reset_t)NULL,
7851         .set_link_led   = (set_link_led_t)NULL,
7852         .phy_specific_func = (phy_specific_func_t)NULL
7853 };
7854 static struct bnx2x_phy phy_8706 = {
7855         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7856         .addr           = 0xff,
7857         .def_md_devad   = 0,
7858         .flags          = FLAGS_INIT_XGXS_FIRST,
7859         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7860         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7861         .mdio_ctrl      = 0,
7862         .supported      = (SUPPORTED_10000baseT_Full |
7863                            SUPPORTED_1000baseT_Full |
7864                            SUPPORTED_FIBRE |
7865                            SUPPORTED_Pause |
7866                            SUPPORTED_Asym_Pause),
7867         .media_type     = ETH_PHY_SFP_FIBER,
7868         .ver_addr       = 0,
7869         .req_flow_ctrl  = 0,
7870         .req_line_speed = 0,
7871         .speed_cap_mask = 0,
7872         .req_duplex     = 0,
7873         .rsrv           = 0,
7874         .config_init    = (config_init_t)bnx2x_8706_config_init,
7875         .read_status    = (read_status_t)bnx2x_8706_read_status,
7876         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7877         .config_loopback = (config_loopback_t)NULL,
7878         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7879         .hw_reset       = (hw_reset_t)NULL,
7880         .set_link_led   = (set_link_led_t)NULL,
7881         .phy_specific_func = (phy_specific_func_t)NULL
7882 };
7883
7884 static struct bnx2x_phy phy_8726 = {
7885         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7886         .addr           = 0xff,
7887         .def_md_devad   = 0,
7888         .flags          = (FLAGS_HW_LOCK_REQUIRED |
7889                            FLAGS_INIT_XGXS_FIRST),
7890         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7891         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7892         .mdio_ctrl      = 0,
7893         .supported      = (SUPPORTED_10000baseT_Full |
7894                            SUPPORTED_1000baseT_Full |
7895                            SUPPORTED_Autoneg |
7896                            SUPPORTED_FIBRE |
7897                            SUPPORTED_Pause |
7898                            SUPPORTED_Asym_Pause),
7899         .media_type     = ETH_PHY_NOT_PRESENT,
7900         .ver_addr       = 0,
7901         .req_flow_ctrl  = 0,
7902         .req_line_speed = 0,
7903         .speed_cap_mask = 0,
7904         .req_duplex     = 0,
7905         .rsrv           = 0,
7906         .config_init    = (config_init_t)bnx2x_8726_config_init,
7907         .read_status    = (read_status_t)bnx2x_8726_read_status,
7908         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
7909         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7910         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7911         .hw_reset       = (hw_reset_t)NULL,
7912         .set_link_led   = (set_link_led_t)NULL,
7913         .phy_specific_func = (phy_specific_func_t)NULL
7914 };
7915
7916 static struct bnx2x_phy phy_8727 = {
7917         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7918         .addr           = 0xff,
7919         .def_md_devad   = 0,
7920         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7921         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7922         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7923         .mdio_ctrl      = 0,
7924         .supported      = (SUPPORTED_10000baseT_Full |
7925                            SUPPORTED_1000baseT_Full |
7926                            SUPPORTED_FIBRE |
7927                            SUPPORTED_Pause |
7928                            SUPPORTED_Asym_Pause),
7929         .media_type     = ETH_PHY_NOT_PRESENT,
7930         .ver_addr       = 0,
7931         .req_flow_ctrl  = 0,
7932         .req_line_speed = 0,
7933         .speed_cap_mask = 0,
7934         .req_duplex     = 0,
7935         .rsrv           = 0,
7936         .config_init    = (config_init_t)bnx2x_8727_config_init,
7937         .read_status    = (read_status_t)bnx2x_8727_read_status,
7938         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
7939         .config_loopback = (config_loopback_t)NULL,
7940         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7941         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
7942         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
7943         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
7944 };
7945 static struct bnx2x_phy phy_8481 = {
7946         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7947         .addr           = 0xff,
7948         .def_md_devad   = 0,
7949         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7950                           FLAGS_REARM_LATCH_SIGNAL,
7951         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7952         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7953         .mdio_ctrl      = 0,
7954         .supported      = (SUPPORTED_10baseT_Half |
7955                            SUPPORTED_10baseT_Full |
7956                            SUPPORTED_100baseT_Half |
7957                            SUPPORTED_100baseT_Full |
7958                            SUPPORTED_1000baseT_Full |
7959                            SUPPORTED_10000baseT_Full |
7960                            SUPPORTED_TP |
7961                            SUPPORTED_Autoneg |
7962                            SUPPORTED_Pause |
7963                            SUPPORTED_Asym_Pause),
7964         .media_type     = ETH_PHY_BASE_T,
7965         .ver_addr       = 0,
7966         .req_flow_ctrl  = 0,
7967         .req_line_speed = 0,
7968         .speed_cap_mask = 0,
7969         .req_duplex     = 0,
7970         .rsrv           = 0,
7971         .config_init    = (config_init_t)bnx2x_8481_config_init,
7972         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7973         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
7974         .config_loopback = (config_loopback_t)NULL,
7975         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7976         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
7977         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7978         .phy_specific_func = (phy_specific_func_t)NULL
7979 };
7980
7981 static struct bnx2x_phy phy_84823 = {
7982         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7983         .addr           = 0xff,
7984         .def_md_devad   = 0,
7985         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7986                           FLAGS_REARM_LATCH_SIGNAL,
7987         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7988         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7989         .mdio_ctrl      = 0,
7990         .supported      = (SUPPORTED_10baseT_Half |
7991                            SUPPORTED_10baseT_Full |
7992                            SUPPORTED_100baseT_Half |
7993                            SUPPORTED_100baseT_Full |
7994                            SUPPORTED_1000baseT_Full |
7995                            SUPPORTED_10000baseT_Full |
7996                            SUPPORTED_TP |
7997                            SUPPORTED_Autoneg |
7998                            SUPPORTED_Pause |
7999                            SUPPORTED_Asym_Pause),
8000         .media_type     = ETH_PHY_BASE_T,
8001         .ver_addr       = 0,
8002         .req_flow_ctrl  = 0,
8003         .req_line_speed = 0,
8004         .speed_cap_mask = 0,
8005         .req_duplex     = 0,
8006         .rsrv           = 0,
8007         .config_init    = (config_init_t)bnx2x_848x3_config_init,
8008         .read_status    = (read_status_t)bnx2x_848xx_read_status,
8009         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
8010         .config_loopback = (config_loopback_t)NULL,
8011         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
8012         .hw_reset       = (hw_reset_t)NULL,
8013         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
8014         .phy_specific_func = (phy_specific_func_t)NULL
8015 };
8016
8017 static struct bnx2x_phy phy_84833 = {
8018         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
8019         .addr           = 0xff,
8020         .def_md_devad   = 0,
8021         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
8022                             FLAGS_REARM_LATCH_SIGNAL,
8023         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
8024         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
8025         .mdio_ctrl      = 0,
8026         .supported      = (SUPPORTED_10baseT_Half |
8027                            SUPPORTED_10baseT_Full |
8028                            SUPPORTED_100baseT_Half |
8029                            SUPPORTED_100baseT_Full |
8030                            SUPPORTED_1000baseT_Full |
8031                            SUPPORTED_10000baseT_Full |
8032                            SUPPORTED_TP |
8033                            SUPPORTED_Autoneg |
8034                            SUPPORTED_Pause |
8035                            SUPPORTED_Asym_Pause),
8036         .media_type     = ETH_PHY_BASE_T,
8037         .ver_addr       = 0,
8038         .req_flow_ctrl  = 0,
8039         .req_line_speed = 0,
8040         .speed_cap_mask = 0,
8041         .req_duplex     = 0,
8042         .rsrv           = 0,
8043         .config_init    = (config_init_t)bnx2x_848x3_config_init,
8044         .read_status    = (read_status_t)bnx2x_848xx_read_status,
8045         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
8046         .config_loopback = (config_loopback_t)NULL,
8047         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
8048         .hw_reset       = (hw_reset_t)NULL,
8049         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
8050         .phy_specific_func = (phy_specific_func_t)NULL
8051 };
8052
8053 /*****************************************************************/
8054 /*                                                               */
8055 /* Populate the phy according. Main function: bnx2x_populate_phy   */
8056 /*                                                               */
8057 /*****************************************************************/
8058
8059 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
8060                                      struct bnx2x_phy *phy, u8 port,
8061                                      u8 phy_index)
8062 {
8063         /* Get the 4 lanes xgxs config rx and tx */
8064         u32 rx = 0, tx = 0, i;
8065         for (i = 0; i < 2; i++) {
8066                 /*
8067                  * INT_PHY and EXT_PHY1 share the same value location in the
8068                  * shmem. When num_phys is greater than 1, than this value
8069                  * applies only to EXT_PHY1
8070                  */
8071                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
8072                         rx = REG_RD(bp, shmem_base +
8073                                     offsetof(struct shmem_region,
8074                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
8075
8076                         tx = REG_RD(bp, shmem_base +
8077                                     offsetof(struct shmem_region,
8078                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
8079                 } else {
8080                         rx = REG_RD(bp, shmem_base +
8081                                     offsetof(struct shmem_region,
8082                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
8083
8084                         tx = REG_RD(bp, shmem_base +
8085                                     offsetof(struct shmem_region,
8086                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
8087                 }
8088
8089                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
8090                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
8091
8092                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
8093                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
8094         }
8095 }
8096
8097 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
8098                                     u8 phy_index, u8 port)
8099 {
8100         u32 ext_phy_config = 0;
8101         switch (phy_index) {
8102         case EXT_PHY1:
8103                 ext_phy_config = REG_RD(bp, shmem_base +
8104                                               offsetof(struct shmem_region,
8105                         dev_info.port_hw_config[port].external_phy_config));
8106                 break;
8107         case EXT_PHY2:
8108                 ext_phy_config = REG_RD(bp, shmem_base +
8109                                               offsetof(struct shmem_region,
8110                         dev_info.port_hw_config[port].external_phy_config2));
8111                 break;
8112         default:
8113                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
8114                 return -EINVAL;
8115         }
8116
8117         return ext_phy_config;
8118 }
8119 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
8120                                   struct bnx2x_phy *phy)
8121 {
8122         u32 phy_addr;
8123         u32 chip_id;
8124         u32 switch_cfg = (REG_RD(bp, shmem_base +
8125                                        offsetof(struct shmem_region,
8126                         dev_info.port_feature_config[port].link_config)) &
8127                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
8128         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
8129         switch (switch_cfg) {
8130         case SWITCH_CFG_1G:
8131                 phy_addr = REG_RD(bp,
8132                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
8133                                         port * 0x10);
8134                 *phy = phy_serdes;
8135                 break;
8136         case SWITCH_CFG_10G:
8137                 phy_addr = REG_RD(bp,
8138                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
8139                                         port * 0x18);
8140                 *phy = phy_xgxs;
8141                 break;
8142         default:
8143                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
8144                 return -EINVAL;
8145         }
8146         phy->addr = (u8)phy_addr;
8147         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
8148                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
8149                                             port);
8150         if (CHIP_IS_E2(bp))
8151                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
8152         else
8153                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
8154
8155         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
8156                    port, phy->addr, phy->mdio_ctrl);
8157
8158         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
8159         return 0;
8160 }
8161
8162 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
8163                                   u8 phy_index,
8164                                   u32 shmem_base,
8165                                   u32 shmem2_base,
8166                                   u8 port,
8167                                   struct bnx2x_phy *phy)
8168 {
8169         u32 ext_phy_config, phy_type, config2;
8170         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
8171         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
8172                                                   phy_index, port);
8173         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8174         /* Select the phy type */
8175         switch (phy_type) {
8176         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8177                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
8178                 *phy = phy_8073;
8179                 break;
8180         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
8181                 *phy = phy_8705;
8182                 break;
8183         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
8184                 *phy = phy_8706;
8185                 break;
8186         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8187                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
8188                 *phy = phy_8726;
8189                 break;
8190         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
8191                 /* BCM8727_NOC => BCM8727 no over current */
8192                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
8193                 *phy = phy_8727;
8194                 phy->flags |= FLAGS_NOC;
8195                 break;
8196         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8197         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8198                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
8199                 *phy = phy_8727;
8200                 break;
8201         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
8202                 *phy = phy_8481;
8203                 break;
8204         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
8205                 *phy = phy_84823;
8206                 break;
8207         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
8208                 *phy = phy_84833;
8209                 break;
8210         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
8211                 *phy = phy_7101;
8212                 break;
8213         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8214                 *phy = phy_null;
8215                 return -EINVAL;
8216         default:
8217                 *phy = phy_null;
8218                 return 0;
8219         }
8220
8221         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
8222         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
8223
8224         /*
8225          * The shmem address of the phy version is located on different
8226          * structures. In case this structure is too old, do not set
8227          * the address
8228          */
8229         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
8230                                         dev_info.shared_hw_config.config2));
8231         if (phy_index == EXT_PHY1) {
8232                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
8233                                 port_mb[port].ext_phy_fw_version);
8234
8235                 /* Check specific mdc mdio settings */
8236                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
8237                         mdc_mdio_access = config2 &
8238                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
8239         } else {
8240                 u32 size = REG_RD(bp, shmem2_base);
8241
8242                 if (size >
8243                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
8244                         phy->ver_addr = shmem2_base +
8245                             offsetof(struct shmem2_region,
8246                                      ext_phy_fw_version2[port]);
8247                 }
8248                 /* Check specific mdc mdio settings */
8249                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
8250                         mdc_mdio_access = (config2 &
8251                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
8252                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
8253                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
8254         }
8255         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
8256
8257         /*
8258          * In case mdc/mdio_access of the external phy is different than the
8259          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
8260          * to prevent one port interfere with another port's CL45 operations.
8261          */
8262         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
8263                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
8264         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
8265                    phy_type, port, phy_index);
8266         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
8267                    phy->addr, phy->mdio_ctrl);
8268         return 0;
8269 }
8270
8271 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
8272                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
8273 {
8274         int status = 0;
8275         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
8276         if (phy_index == INT_PHY)
8277                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
8278         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
8279                                         port, phy);
8280         return status;
8281 }
8282
8283 static void bnx2x_phy_def_cfg(struct link_params *params,
8284                               struct bnx2x_phy *phy,
8285                               u8 phy_index)
8286 {
8287         struct bnx2x *bp = params->bp;
8288         u32 link_config;
8289         /* Populate the default phy configuration for MF mode */
8290         if (phy_index == EXT_PHY2) {
8291                 link_config = REG_RD(bp, params->shmem_base +
8292                                      offsetof(struct shmem_region, dev_info.
8293                         port_feature_config[params->port].link_config2));
8294                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
8295                                              offsetof(struct shmem_region,
8296                                                       dev_info.
8297                         port_hw_config[params->port].speed_capability_mask2));
8298         } else {
8299                 link_config = REG_RD(bp, params->shmem_base +
8300                                      offsetof(struct shmem_region, dev_info.
8301                                 port_feature_config[params->port].link_config));
8302                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
8303                                              offsetof(struct shmem_region,
8304                                                       dev_info.
8305                         port_hw_config[params->port].speed_capability_mask));
8306         }
8307         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
8308                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
8309
8310         phy->req_duplex = DUPLEX_FULL;
8311         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
8312         case PORT_FEATURE_LINK_SPEED_10M_HALF:
8313                 phy->req_duplex = DUPLEX_HALF;
8314         case PORT_FEATURE_LINK_SPEED_10M_FULL:
8315                 phy->req_line_speed = SPEED_10;
8316                 break;
8317         case PORT_FEATURE_LINK_SPEED_100M_HALF:
8318                 phy->req_duplex = DUPLEX_HALF;
8319         case PORT_FEATURE_LINK_SPEED_100M_FULL:
8320                 phy->req_line_speed = SPEED_100;
8321                 break;
8322         case PORT_FEATURE_LINK_SPEED_1G:
8323                 phy->req_line_speed = SPEED_1000;
8324                 break;
8325         case PORT_FEATURE_LINK_SPEED_2_5G:
8326                 phy->req_line_speed = SPEED_2500;
8327                 break;
8328         case PORT_FEATURE_LINK_SPEED_10G_CX4:
8329                 phy->req_line_speed = SPEED_10000;
8330                 break;
8331         default:
8332                 phy->req_line_speed = SPEED_AUTO_NEG;
8333                 break;
8334         }
8335
8336         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
8337         case PORT_FEATURE_FLOW_CONTROL_AUTO:
8338                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
8339                 break;
8340         case PORT_FEATURE_FLOW_CONTROL_TX:
8341                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
8342                 break;
8343         case PORT_FEATURE_FLOW_CONTROL_RX:
8344                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
8345                 break;
8346         case PORT_FEATURE_FLOW_CONTROL_BOTH:
8347                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
8348                 break;
8349         default:
8350                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8351                 break;
8352         }
8353 }
8354
8355 u32 bnx2x_phy_selection(struct link_params *params)
8356 {
8357         u32 phy_config_swapped, prio_cfg;
8358         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
8359
8360         phy_config_swapped = params->multi_phy_config &
8361                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
8362
8363         prio_cfg = params->multi_phy_config &
8364                         PORT_HW_CFG_PHY_SELECTION_MASK;
8365
8366         if (phy_config_swapped) {
8367                 switch (prio_cfg) {
8368                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
8369                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
8370                      break;
8371                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
8372                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
8373                      break;
8374                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
8375                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
8376                      break;
8377                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
8378                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
8379                      break;
8380                 }
8381         } else
8382                 return_cfg = prio_cfg;
8383
8384         return return_cfg;
8385 }
8386
8387
8388 int bnx2x_phy_probe(struct link_params *params)
8389 {
8390         u8 phy_index, actual_phy_idx, link_cfg_idx;
8391         u32 phy_config_swapped, sync_offset, media_types;
8392         struct bnx2x *bp = params->bp;
8393         struct bnx2x_phy *phy;
8394         params->num_phys = 0;
8395         DP(NETIF_MSG_LINK, "Begin phy probe\n");
8396         phy_config_swapped = params->multi_phy_config &
8397                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
8398
8399         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8400               phy_index++) {
8401                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
8402                 actual_phy_idx = phy_index;
8403                 if (phy_config_swapped) {
8404                         if (phy_index == EXT_PHY1)
8405                                 actual_phy_idx = EXT_PHY2;
8406                         else if (phy_index == EXT_PHY2)
8407                                 actual_phy_idx = EXT_PHY1;
8408                 }
8409                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
8410                                " actual_phy_idx %x\n", phy_config_swapped,
8411                            phy_index, actual_phy_idx);
8412                 phy = &params->phy[actual_phy_idx];
8413                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
8414                                        params->shmem2_base, params->port,
8415                                        phy) != 0) {
8416                         params->num_phys = 0;
8417                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
8418                                    phy_index);
8419                         for (phy_index = INT_PHY;
8420                               phy_index < MAX_PHYS;
8421                               phy_index++)
8422                                 *phy = phy_null;
8423                         return -EINVAL;
8424                 }
8425                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
8426                         break;
8427
8428                 sync_offset = params->shmem_base +
8429                         offsetof(struct shmem_region,
8430                         dev_info.port_hw_config[params->port].media_type);
8431                 media_types = REG_RD(bp, sync_offset);
8432
8433                 /*
8434                  * Update media type for non-PMF sync only for the first time
8435                  * In case the media type changes afterwards, it will be updated
8436                  * using the update_status function
8437                  */
8438                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8439                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
8440                                      actual_phy_idx))) == 0) {
8441                         media_types |= ((phy->media_type &
8442                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8443                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
8444                                  actual_phy_idx));
8445                 }
8446                 REG_WR(bp, sync_offset, media_types);
8447
8448                 bnx2x_phy_def_cfg(params, phy, phy_index);
8449                 params->num_phys++;
8450         }
8451
8452         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
8453         return 0;
8454 }
8455
8456 void bnx2x_init_bmac_loopback(struct link_params *params,
8457                               struct link_vars *vars)
8458 {
8459         struct bnx2x *bp = params->bp;
8460                 vars->link_up = 1;
8461                 vars->line_speed = SPEED_10000;
8462                 vars->duplex = DUPLEX_FULL;
8463                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8464                 vars->mac_type = MAC_TYPE_BMAC;
8465
8466                 vars->phy_flags = PHY_XGXS_FLAG;
8467
8468                 bnx2x_xgxs_deassert(params);
8469
8470                 /* set bmac loopback */
8471                 bnx2x_bmac_enable(params, vars, 1);
8472
8473                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8474 }
8475
8476 void bnx2x_init_emac_loopback(struct link_params *params,
8477                               struct link_vars *vars)
8478 {
8479         struct bnx2x *bp = params->bp;
8480                 vars->link_up = 1;
8481                 vars->line_speed = SPEED_1000;
8482                 vars->duplex = DUPLEX_FULL;
8483                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8484                 vars->mac_type = MAC_TYPE_EMAC;
8485
8486                 vars->phy_flags = PHY_XGXS_FLAG;
8487
8488                 bnx2x_xgxs_deassert(params);
8489                 /* set bmac loopback */
8490                 bnx2x_emac_enable(params, vars, 1);
8491                 bnx2x_emac_program(params, vars);
8492                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8493 }
8494
8495 void bnx2x_init_xmac_loopback(struct link_params *params,
8496                               struct link_vars *vars)
8497 {
8498         struct bnx2x *bp = params->bp;
8499         vars->link_up = 1;
8500         if (!params->req_line_speed[0])
8501                 vars->line_speed = SPEED_10000;
8502         else
8503                 vars->line_speed = params->req_line_speed[0];
8504         vars->duplex = DUPLEX_FULL;
8505         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8506         vars->mac_type = MAC_TYPE_XMAC;
8507         vars->phy_flags = PHY_XGXS_FLAG;
8508         /*
8509          * Set WC to loopback mode since link is required to provide clock
8510          * to the XMAC in 20G mode
8511          */
8512
8513         bnx2x_xmac_enable(params, vars, 1);
8514         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8515 }
8516
8517 void bnx2x_init_umac_loopback(struct link_params *params,
8518                               struct link_vars *vars)
8519 {
8520         struct bnx2x *bp = params->bp;
8521         vars->link_up = 1;
8522         vars->line_speed = SPEED_1000;
8523         vars->duplex = DUPLEX_FULL;
8524         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8525         vars->mac_type = MAC_TYPE_UMAC;
8526         vars->phy_flags = PHY_XGXS_FLAG;
8527         bnx2x_umac_enable(params, vars, 1);
8528
8529         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8530 }
8531
8532 void bnx2x_init_xgxs_loopback(struct link_params *params,
8533                               struct link_vars *vars)
8534 {
8535         struct bnx2x *bp = params->bp;
8536                 vars->link_up = 1;
8537                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8538                 vars->duplex = DUPLEX_FULL;
8539         if (params->req_line_speed[0] == SPEED_1000)
8540                         vars->line_speed = SPEED_1000;
8541         else
8542                         vars->line_speed = SPEED_10000;
8543
8544         if (!USES_WARPCORE(bp))
8545                 bnx2x_xgxs_deassert(params);
8546         bnx2x_link_initialize(params, vars);
8547
8548         if (params->req_line_speed[0] == SPEED_1000) {
8549                 if (USES_WARPCORE(bp))
8550                         bnx2x_umac_enable(params, vars, 0);
8551                 else {
8552                         bnx2x_emac_program(params, vars);
8553                         bnx2x_emac_enable(params, vars, 0);
8554                 }
8555         } else {
8556                 if (USES_WARPCORE(bp))
8557                         bnx2x_xmac_enable(params, vars, 0);
8558                 else
8559                         bnx2x_bmac_enable(params, vars, 0);
8560         }
8561
8562                 if (params->loopback_mode == LOOPBACK_XGXS) {
8563                         /* set 10G XGXS loopback */
8564                         params->phy[INT_PHY].config_loopback(
8565                                 &params->phy[INT_PHY],
8566                                 params);
8567
8568                 } else {
8569                         /* set external phy loopback */
8570                         u8 phy_index;
8571                         for (phy_index = EXT_PHY1;
8572                               phy_index < params->num_phys; phy_index++) {
8573                                 if (params->phy[phy_index].config_loopback)
8574                                         params->phy[phy_index].config_loopback(
8575                                                 &params->phy[phy_index],
8576                                                 params);
8577                         }
8578                 }
8579                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
8580
8581         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
8582 }
8583
8584 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
8585 {
8586         struct bnx2x *bp = params->bp;
8587         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
8588         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
8589                    params->req_line_speed[0], params->req_flow_ctrl[0]);
8590         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
8591                    params->req_line_speed[1], params->req_flow_ctrl[1]);
8592         vars->link_status = 0;
8593         vars->phy_link_up = 0;
8594         vars->link_up = 0;
8595         vars->line_speed = 0;
8596         vars->duplex = DUPLEX_FULL;
8597         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
8598         vars->mac_type = MAC_TYPE_NONE;
8599         vars->phy_flags = 0;
8600
8601         /* disable attentions */
8602         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
8603                        (NIG_MASK_XGXS0_LINK_STATUS |
8604                         NIG_MASK_XGXS0_LINK10G |
8605                         NIG_MASK_SERDES0_LINK_STATUS |
8606                         NIG_MASK_MI_INT));
8607
8608         bnx2x_emac_init(params, vars);
8609
8610         if (params->num_phys == 0) {
8611                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
8612                 return -EINVAL;
8613         }
8614         set_phy_vars(params, vars);
8615
8616         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
8617         switch (params->loopback_mode) {
8618         case LOOPBACK_BMAC:
8619                 bnx2x_init_bmac_loopback(params, vars);
8620                 break;
8621         case LOOPBACK_EMAC:
8622                 bnx2x_init_emac_loopback(params, vars);
8623                 break;
8624         case LOOPBACK_XMAC:
8625                 bnx2x_init_xmac_loopback(params, vars);
8626                 break;
8627         case LOOPBACK_UMAC:
8628                 bnx2x_init_umac_loopback(params, vars);
8629                 break;
8630         case LOOPBACK_XGXS:
8631         case LOOPBACK_EXT_PHY:
8632                 bnx2x_init_xgxs_loopback(params, vars);
8633                 break;
8634         default:
8635                 if (!CHIP_IS_E3(bp)) {
8636                         if (params->switch_cfg == SWITCH_CFG_10G)
8637                                 bnx2x_xgxs_deassert(params);
8638                         else
8639                                 bnx2x_serdes_deassert(bp, params->port);
8640                 }
8641                 bnx2x_link_initialize(params, vars);
8642                 msleep(30);
8643                 bnx2x_link_int_enable(params);
8644                 break;
8645         }
8646         return 0;
8647 }
8648
8649 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
8650                      u8 reset_ext_phy)
8651 {
8652         struct bnx2x *bp = params->bp;
8653         u8 phy_index, port = params->port, clear_latch_ind = 0;
8654         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
8655         /* disable attentions */
8656         vars->link_status = 0;
8657         bnx2x_update_mng(params, vars->link_status);
8658         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
8659                        (NIG_MASK_XGXS0_LINK_STATUS |
8660                         NIG_MASK_XGXS0_LINK10G |
8661                         NIG_MASK_SERDES0_LINK_STATUS |
8662                         NIG_MASK_MI_INT));
8663
8664         /* activate nig drain */
8665         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
8666
8667         /* disable nig egress interface */
8668         if (!CHIP_IS_E3(bp)) {
8669                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8670                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8671         }
8672
8673         /* Stop BigMac rx */
8674         if (!CHIP_IS_E3(bp))
8675                 bnx2x_bmac_rx_disable(bp, port);
8676         else
8677                 bnx2x_xmac_disable(params);
8678         /* disable emac */
8679         if (!CHIP_IS_E3(bp))
8680                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
8681
8682         msleep(10);
8683         /* The PHY reset is controlled by GPIO 1
8684          * Hold it as vars low
8685          */
8686          /* clear link led */
8687         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
8688
8689         if (reset_ext_phy) {
8690                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
8691                       phy_index++) {
8692                         if (params->phy[phy_index].link_reset)
8693                                 params->phy[phy_index].link_reset(
8694                                         &params->phy[phy_index],
8695                                         params);
8696                         if (params->phy[phy_index].flags &
8697                             FLAGS_REARM_LATCH_SIGNAL)
8698                                 clear_latch_ind = 1;
8699                 }
8700         }
8701
8702         if (clear_latch_ind) {
8703                 /* Clear latching indication */
8704                 bnx2x_rearm_latch_signal(bp, port, 0);
8705                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
8706                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
8707         }
8708         if (params->phy[INT_PHY].link_reset)
8709                 params->phy[INT_PHY].link_reset(
8710                         &params->phy[INT_PHY], params);
8711         /* reset BigMac */
8712         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8713                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
8714
8715         /* disable nig ingress interface */
8716         if (!CHIP_IS_E3(bp)) {
8717                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
8718                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
8719         }
8720         vars->link_up = 0;
8721         return 0;
8722 }
8723
8724 /****************************************************************************/
8725 /*                              Common function                             */
8726 /****************************************************************************/
8727 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
8728                                       u32 shmem_base_path[],
8729                                       u32 shmem2_base_path[], u8 phy_index,
8730                                       u32 chip_id)
8731 {
8732         struct bnx2x_phy phy[PORT_MAX];
8733         struct bnx2x_phy *phy_blk[PORT_MAX];
8734         u16 val;
8735         s8 port = 0;
8736         s8 port_of_path = 0;
8737         u32 swap_val, swap_override;
8738         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
8739         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
8740         port ^= (swap_val && swap_override);
8741         bnx2x_ext_phy_hw_reset(bp, port);
8742         /* PART1 - Reset both phys */
8743         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8744                 u32 shmem_base, shmem2_base;
8745                 /* In E2, same phy is using for port0 of the two paths */
8746                 if (CHIP_IS_E2(bp)) {
8747                         shmem_base = shmem_base_path[port];
8748                         shmem2_base = shmem2_base_path[port];
8749                         port_of_path = 0;
8750                 } else {
8751                         shmem_base = shmem_base_path[0];
8752                         shmem2_base = shmem2_base_path[0];
8753                         port_of_path = port;
8754                 }
8755
8756                 /* Extract the ext phy address for the port */
8757                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8758                                        port_of_path, &phy[port]) !=
8759                     0) {
8760                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
8761                         return -EINVAL;
8762                 }
8763                 /* disable attentions */
8764                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8765                                port_of_path*4,
8766                                (NIG_MASK_XGXS0_LINK_STATUS |
8767                                 NIG_MASK_XGXS0_LINK10G |
8768                                 NIG_MASK_SERDES0_LINK_STATUS |
8769                                 NIG_MASK_MI_INT));
8770
8771                 /* Need to take the phy out of low power mode in order
8772                         to write to access its registers */
8773                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8774                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8775                                port);
8776
8777                 /* Reset the phy */
8778                 bnx2x_cl45_write(bp, &phy[port],
8779                                  MDIO_PMA_DEVAD,
8780                                  MDIO_PMA_REG_CTRL,
8781                                  1<<15);
8782         }
8783
8784         /* Add delay of 150ms after reset */
8785         msleep(150);
8786
8787         if (phy[PORT_0].addr & 0x1) {
8788                 phy_blk[PORT_0] = &(phy[PORT_1]);
8789                 phy_blk[PORT_1] = &(phy[PORT_0]);
8790         } else {
8791                 phy_blk[PORT_0] = &(phy[PORT_0]);
8792                 phy_blk[PORT_1] = &(phy[PORT_1]);
8793         }
8794
8795         /* PART2 - Download firmware to both phys */
8796         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8797                 if (CHIP_IS_E2(bp))
8798                         port_of_path = 0;
8799                 else
8800                         port_of_path = port;
8801
8802                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8803                            phy_blk[port]->addr);
8804                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8805                                                       port_of_path))
8806                         return -EINVAL;
8807
8808                 /* Only set bit 10 = 1 (Tx power down) */
8809                 bnx2x_cl45_read(bp, phy_blk[port],
8810                                 MDIO_PMA_DEVAD,
8811                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8812
8813                 /* Phase1 of TX_POWER_DOWN reset */
8814                 bnx2x_cl45_write(bp, phy_blk[port],
8815                                  MDIO_PMA_DEVAD,
8816                                  MDIO_PMA_REG_TX_POWER_DOWN,
8817                                  (val | 1<<10));
8818         }
8819
8820         /*
8821          * Toggle Transmitter: Power down and then up with 600ms delay
8822          * between
8823          */
8824         msleep(600);
8825
8826         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
8827         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8828                 /* Phase2 of POWER_DOWN_RESET */
8829                 /* Release bit 10 (Release Tx power down) */
8830                 bnx2x_cl45_read(bp, phy_blk[port],
8831                                 MDIO_PMA_DEVAD,
8832                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8833
8834                 bnx2x_cl45_write(bp, phy_blk[port],
8835                                 MDIO_PMA_DEVAD,
8836                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
8837                 msleep(15);
8838
8839                 /* Read modify write the SPI-ROM version select register */
8840                 bnx2x_cl45_read(bp, phy_blk[port],
8841                                 MDIO_PMA_DEVAD,
8842                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
8843                 bnx2x_cl45_write(bp, phy_blk[port],
8844                                  MDIO_PMA_DEVAD,
8845                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
8846
8847                 /* set GPIO2 back to LOW */
8848                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8849                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8850         }
8851         return 0;
8852 }
8853 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
8854                                       u32 shmem_base_path[],
8855                                       u32 shmem2_base_path[], u8 phy_index,
8856                                       u32 chip_id)
8857 {
8858         u32 val;
8859         s8 port;
8860         struct bnx2x_phy phy;
8861         /* Use port1 because of the static port-swap */
8862         /* Enable the module detection interrupt */
8863         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8864         val |= ((1<<MISC_REGISTERS_GPIO_3)|
8865                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
8866         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8867
8868         bnx2x_ext_phy_hw_reset(bp, 0);
8869         msleep(5);
8870         for (port = 0; port < PORT_MAX; port++) {
8871                 u32 shmem_base, shmem2_base;
8872
8873                 /* In E2, same phy is using for port0 of the two paths */
8874                 if (CHIP_IS_E2(bp)) {
8875                         shmem_base = shmem_base_path[port];
8876                         shmem2_base = shmem2_base_path[port];
8877                 } else {
8878                         shmem_base = shmem_base_path[0];
8879                         shmem2_base = shmem2_base_path[0];
8880                 }
8881                 /* Extract the ext phy address for the port */
8882                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8883                                        port, &phy) !=
8884                     0) {
8885                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8886                         return -EINVAL;
8887                 }
8888
8889                 /* Reset phy*/
8890                 bnx2x_cl45_write(bp, &phy,
8891                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8892
8893
8894                 /* Set fault module detected LED on */
8895                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8896                                MISC_REGISTERS_GPIO_HIGH,
8897                                port);
8898         }
8899
8900         return 0;
8901 }
8902 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8903                                          u8 *io_gpio, u8 *io_port)
8904 {
8905
8906         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8907                                           offsetof(struct shmem_region,
8908                                 dev_info.port_hw_config[PORT_0].default_cfg));
8909         switch (phy_gpio_reset) {
8910         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8911                 *io_gpio = 0;
8912                 *io_port = 0;
8913                 break;
8914         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8915                 *io_gpio = 1;
8916                 *io_port = 0;
8917                 break;
8918         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8919                 *io_gpio = 2;
8920                 *io_port = 0;
8921                 break;
8922         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8923                 *io_gpio = 3;
8924                 *io_port = 0;
8925                 break;
8926         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8927                 *io_gpio = 0;
8928                 *io_port = 1;
8929                 break;
8930         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8931                 *io_gpio = 1;
8932                 *io_port = 1;
8933                 break;
8934         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8935                 *io_gpio = 2;
8936                 *io_port = 1;
8937                 break;
8938         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8939                 *io_gpio = 3;
8940                 *io_port = 1;
8941                 break;
8942         default:
8943                 /* Don't override the io_gpio and io_port */
8944                 break;
8945         }
8946 }
8947
8948 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
8949                                       u32 shmem_base_path[],
8950                                       u32 shmem2_base_path[], u8 phy_index,
8951                                       u32 chip_id)
8952 {
8953         s8 port, reset_gpio;
8954         u32 swap_val, swap_override;
8955         struct bnx2x_phy phy[PORT_MAX];
8956         struct bnx2x_phy *phy_blk[PORT_MAX];
8957         s8 port_of_path;
8958         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8959         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8960
8961         reset_gpio = MISC_REGISTERS_GPIO_1;
8962         port = 1;
8963
8964         /*
8965          * Retrieve the reset gpio/port which control the reset.
8966          * Default is GPIO1, PORT1
8967          */
8968         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8969                                      (u8 *)&reset_gpio, (u8 *)&port);
8970
8971         /* Calculate the port based on port swap */
8972         port ^= (swap_val && swap_override);
8973
8974         /* Initiate PHY reset*/
8975         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8976                        port);
8977         msleep(1);
8978         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8979                        port);
8980
8981         msleep(5);
8982
8983         /* PART1 - Reset both phys */
8984         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8985                 u32 shmem_base, shmem2_base;
8986
8987                 /* In E2, same phy is using for port0 of the two paths */
8988                 if (CHIP_IS_E2(bp)) {
8989                         shmem_base = shmem_base_path[port];
8990                         shmem2_base = shmem2_base_path[port];
8991                         port_of_path = 0;
8992                 } else {
8993                         shmem_base = shmem_base_path[0];
8994                         shmem2_base = shmem2_base_path[0];
8995                         port_of_path = port;
8996                 }
8997
8998                 /* Extract the ext phy address for the port */
8999                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
9000                                        port_of_path, &phy[port]) !=
9001                                        0) {
9002                         DP(NETIF_MSG_LINK, "populate phy failed\n");
9003                         return -EINVAL;
9004                 }
9005                 /* disable attentions */
9006                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
9007                                port_of_path*4,
9008                                (NIG_MASK_XGXS0_LINK_STATUS |
9009                                 NIG_MASK_XGXS0_LINK10G |
9010                                 NIG_MASK_SERDES0_LINK_STATUS |
9011                                 NIG_MASK_MI_INT));
9012
9013
9014                 /* Reset the phy */
9015                 bnx2x_cl45_write(bp, &phy[port],
9016                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9017         }
9018
9019         /* Add delay of 150ms after reset */
9020         msleep(150);
9021         if (phy[PORT_0].addr & 0x1) {
9022                 phy_blk[PORT_0] = &(phy[PORT_1]);
9023                 phy_blk[PORT_1] = &(phy[PORT_0]);
9024         } else {
9025                 phy_blk[PORT_0] = &(phy[PORT_0]);
9026                 phy_blk[PORT_1] = &(phy[PORT_1]);
9027         }
9028         /* PART2 - Download firmware to both phys */
9029         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
9030                 if (CHIP_IS_E2(bp))
9031                         port_of_path = 0;
9032                 else
9033                         port_of_path = port;
9034                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
9035                            phy_blk[port]->addr);
9036                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
9037                                                       port_of_path))
9038                         return -EINVAL;
9039
9040         }
9041         return 0;
9042 }
9043
9044 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
9045                                      u32 shmem2_base_path[], u8 phy_index,
9046                                      u32 ext_phy_type, u32 chip_id)
9047 {
9048         int rc = 0;
9049
9050         switch (ext_phy_type) {
9051         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
9052                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
9053                                                 shmem2_base_path,
9054                                                 phy_index, chip_id);
9055                 break;
9056         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9057         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9058         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
9059                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
9060                                                 shmem2_base_path,
9061                                                 phy_index, chip_id);
9062                 break;
9063
9064         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9065                 /*
9066                  * GPIO1 affects both ports, so there's need to pull
9067                  * it for single port alone
9068                  */
9069                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
9070                                                 shmem2_base_path,
9071                                                 phy_index, chip_id);
9072                 break;
9073         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
9074                 rc = -EINVAL;
9075                 break;
9076         default:
9077                 DP(NETIF_MSG_LINK,
9078                            "ext_phy 0x%x common init not required\n",
9079                            ext_phy_type);
9080                 break;
9081         }
9082
9083         if (rc != 0)
9084                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
9085                                       " Port %d\n",
9086                          0);
9087         return rc;
9088 }
9089
9090 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
9091                           u32 shmem2_base_path[], u32 chip_id)
9092 {
9093         int rc = 0;
9094         u32 phy_ver;
9095         u8 phy_index;
9096         u32 ext_phy_type, ext_phy_config;
9097         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
9098         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
9099         DP(NETIF_MSG_LINK, "Begin common phy init\n");
9100
9101         /* Check if common init was already done */
9102         phy_ver = REG_RD(bp, shmem_base_path[0] +
9103                          offsetof(struct shmem_region,
9104                                   port_mb[PORT_0].ext_phy_fw_version));
9105         if (phy_ver) {
9106                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
9107                                phy_ver);
9108                 return 0;
9109         }
9110
9111         /* Read the ext_phy_type for arbitrary port(0) */
9112         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
9113               phy_index++) {
9114                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
9115                                                           shmem_base_path[0],
9116                                                           phy_index, 0);
9117                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9118                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
9119                                                 shmem2_base_path,
9120                                                 phy_index, ext_phy_type,
9121                                                 chip_id);
9122         }
9123         return rc;
9124 }
9125
9126 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
9127 {
9128         u8 phy_index;
9129         struct bnx2x_phy phy;
9130         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
9131               phy_index++) {
9132                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
9133                                        0, &phy) != 0) {
9134                         DP(NETIF_MSG_LINK, "populate phy failed\n");
9135                         return 0;
9136                 }
9137
9138                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
9139                         return 1;
9140         }
9141         return 0;
9142 }
9143
9144 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
9145                              u32 shmem_base,
9146                              u32 shmem2_base,
9147                              u8 port)
9148 {
9149         u8 phy_index, fan_failure_det_req = 0;
9150         struct bnx2x_phy phy;
9151         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
9152               phy_index++) {
9153                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
9154                                        port, &phy)
9155                     != 0) {
9156                         DP(NETIF_MSG_LINK, "populate phy failed\n");
9157                         return 0;
9158                 }
9159                 fan_failure_det_req |= (phy.flags &
9160                                         FLAGS_FAN_FAILURE_DET_REQ);
9161         }
9162         return fan_failure_det_req;
9163 }
9164
9165 void bnx2x_hw_reset_phy(struct link_params *params)
9166 {
9167         u8 phy_index;
9168         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
9169               phy_index++) {
9170                 if (params->phy[phy_index].hw_reset) {
9171                         params->phy[phy_index].hw_reset(
9172                                 &params->phy[phy_index],
9173                                 params);
9174                         params->phy[phy_index] = phy_null;
9175                 }
9176         }
9177 }
9178
9179 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
9180                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
9181                             u8 port)
9182 {
9183         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
9184         u32 val;
9185         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
9186
9187         {
9188                 struct bnx2x_phy phy;
9189                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
9190                       phy_index++) {
9191                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
9192                                                shmem2_base, port, &phy)
9193                             != 0) {
9194                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
9195                                 return;
9196                         }
9197                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
9198                                 gpio_num = MISC_REGISTERS_GPIO_3;
9199                                 gpio_port = port;
9200                                 break;
9201                         }
9202                 }
9203         }
9204
9205         if (gpio_num == 0xff)
9206                 return;
9207
9208         /* Set GPIO3 to trigger SFP+ module insertion/removal */
9209         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
9210
9211         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9212         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9213         gpio_port ^= (swap_val && swap_override);
9214
9215         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
9216                 (gpio_num + (gpio_port << 2));
9217
9218         sync_offset = shmem_base +
9219                 offsetof(struct shmem_region,
9220                          dev_info.port_hw_config[port].aeu_int_mask);
9221         REG_WR(bp, sync_offset, vars->aeu_int_mask);
9222
9223         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
9224                        gpio_num, gpio_port, vars->aeu_int_mask);
9225
9226         if (port == 0)
9227                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
9228         else
9229                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
9230
9231         /* Open appropriate AEU for interrupts */
9232         aeu_mask = REG_RD(bp, offset);
9233         aeu_mask |= vars->aeu_int_mask;
9234         REG_WR(bp, offset, aeu_mask);
9235
9236         /* Enable the GPIO to trigger interrupt */
9237         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
9238         val |= 1 << (gpio_num + (gpio_port << 2));
9239         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
9240 }