drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28
  29 /********************************************************/
  30 #define ETH_HLEN                        14
  31 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  32 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  33 #define ETH_MIN_PACKET_SIZE             60
  34 #define ETH_MAX_PACKET_SIZE             1500
  35 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  36 #define MDIO_ACCESS_TIMEOUT             1000
  37 #define BMAC_CONTROL_RX_ENABLE          2
  38
  39 /***********************************************************/
  40 /*                      Shortcut definitions               */
  41 /***********************************************************/
  42
  43 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  44
  45 #define NIG_STATUS_EMAC0_MI_INT \
  46                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  47 #define NIG_STATUS_XGXS0_LINK10G \
  48                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  49 #define NIG_STATUS_XGXS0_LINK_STATUS \
  50                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  51 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  52                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  53 #define NIG_STATUS_SERDES0_LINK_STATUS \
  54                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  55 #define NIG_MASK_MI_INT \
  56                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  57 #define NIG_MASK_XGXS0_LINK10G \
  58                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  59 #define NIG_MASK_XGXS0_LINK_STATUS \
  60                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  61 #define NIG_MASK_SERDES0_LINK_STATUS \
  62                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  63
  64 #define MDIO_AN_CL73_OR_37_COMPLETE \
  65                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  66                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  67
  68 #define XGXS_RESET_BITS \
  69         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  73          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  74
  75 #define SERDES_RESET_BITS \
  76         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  80
  81 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  82 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  83 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  84 #define AUTONEG_PARALLEL \
  85                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  86 #define AUTONEG_SGMII_FIBER_AUTODET \
  87                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  88 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  89
  90 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  91                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  92 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  93                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  94 #define GP_STATUS_SPEED_MASK \
  95                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  96 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  97 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
  98 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
  99 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 100 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 101 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 102 #define GP_STATUS_10G_HIG \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 104 #define GP_STATUS_10G_CX4 \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 106 #define GP_STATUS_12G_HIG \
 107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 108 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 109 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 110 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 111 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 112 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 113 #define GP_STATUS_10G_KX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 115
 116 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 117 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 118 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 119 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 120 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 121 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 122 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 123 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 124 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 125 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 126 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 127 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 128 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 129 #define LINK_12GTFD             LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
 130 #define LINK_12GXFD             LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
 131 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
 132 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
 133 #define LINK_13GTFD             LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
 134 #define LINK_13GXFD             LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
 135 #define LINK_15GTFD             LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
 136 #define LINK_15GXFD             LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
 137 #define LINK_16GTFD             LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 138 #define LINK_16GXFD             LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 139
 140 #define PHY_XGXS_FLAG                   0x1
 141 #define PHY_SGMII_FLAG                  0x2
 142 #define PHY_SERDES_FLAG                 0x4
 143
 144 /* */
 145 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 146         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 147         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 148
 149
 150 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 151         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 152         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 153         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 154
 155 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 157         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 158
 159 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 160         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 161 #define SFP_EEPROM_OPTIONS_SIZE                 2
 162
 163 #define EDC_MODE_LINEAR                         0x0022
 164 #define EDC_MODE_LIMITING                               0x0044
 165 #define EDC_MODE_PASSIVE_DAC                    0x0055
 166
 167
 168 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 169 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 170 /**********************************************************/
 171 /*                     INTERFACE                          */
 172 /**********************************************************/
 173
 174 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 175         bnx2x_cl45_write(_bp, _phy, \
 176                 (_phy)->def_md_devad, \
 177                 (_bank + (_addr & 0xf)), \
 178                 _val)
 179
 180 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 181         bnx2x_cl45_read(_bp, _phy, \
 182                 (_phy)->def_md_devad, \
 183                 (_bank + (_addr & 0xf)), \
 184                 _val)
 185
 186 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 187 {
 188         u32 val = REG_RD(bp, reg);
 189
 190         val |= bits;
 191         REG_WR(bp, reg, val);
 192         return val;
 193 }
 194
 195 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 196 {
 197         u32 val = REG_RD(bp, reg);
 198
 199         val &= ~bits;
 200         REG_WR(bp, reg, val);
 201         return val;
 202 }
 203
 204 /******************************************************************/
 205 /*                              ETS section                       */
 206 /******************************************************************/
 207 void bnx2x_ets_disabled(struct link_params *params)
 208 {
 209         /* ETS disabled configuration*/
 210         struct bnx2x *bp = params->bp;
 211
 212         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 213
 214         /*
 215          * mapping between entry  priority to client number (0,1,2 -debug and
 216          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 217          * 3bits client num.
 218          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 219          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 220          */
 221
 222         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 223         /*
 224          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 225          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 226          * COS0 entry, 4 - COS1 entry.
 227          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 228          * bit4   bit3    bit2   bit1     bit0
 229          * MCP and debug are strict
 230          */
 231
 232         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 233         /* defines which entries (clients) are subjected to WFQ arbitration */
 234         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 235         /*
 236          * For strict priority entries defines the number of consecutive
 237          * slots for the highest priority.
 238          */
 239         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 240         /*
 241          * mapping between the CREDIT_WEIGHT registers and actual client
 242          * numbers
 243          */
 244         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 245         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 246         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 247
 248         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 249         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 250         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 251         /* ETS mode disable */
 252         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 253         /*
 254          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 255          * weight for COS0/COS1.
 256          */
 257         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 258         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 262         /* Defines the number of consecutive slots for the strict priority */
 263         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 264 }
 265
 266 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
 267 {
 268         /* ETS disabled configuration */
 269         struct bnx2x *bp = params->bp;
 270         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 271         /*
 272          * defines which entries (clients) are subjected to WFQ arbitration
 273          * COS0 0x8
 274          * COS1 0x10
 275          */
 276         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 277         /*
 278          * mapping between the ARB_CREDIT_WEIGHT registers and actual
 279          * client numbers (WEIGHT_0 does not actually have to represent
 280          * client 0)
 281          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 282          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 283          */
 284         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 285
 286         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 287                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 288         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 289                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 290
 291         /* ETS mode enabled*/
 292         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 293
 294         /* Defines the number of consecutive slots for the strict priority */
 295         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 296         /*
 297          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 298          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 299          * entry, 4 - COS1 entry.
 300          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 301          * bit4   bit3    bit2     bit1    bit0
 302          * MCP and debug are strict
 303          */
 304         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 305
 306         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 307         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 308                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 309         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 310                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 311 }
 312
 313 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 314                         const u32 cos1_bw)
 315 {
 316         /* ETS disabled configuration*/
 317         struct bnx2x *bp = params->bp;
 318         const u32 total_bw = cos0_bw + cos1_bw;
 319         u32 cos0_credit_weight = 0;
 320         u32 cos1_credit_weight = 0;
 321
 322         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 323
 324         if ((0 == total_bw) ||
 325             (0 == cos0_bw) ||
 326             (0 == cos1_bw)) {
 327                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
 328                 return;
 329         }
 330
 331         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 332                 total_bw;
 333         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 334                 total_bw;
 335
 336         bnx2x_ets_bw_limit_common(params);
 337
 338         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 339         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 340
 341         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 342         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 343 }
 344
 345 u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 346 {
 347         /* ETS disabled configuration*/
 348         struct bnx2x *bp = params->bp;
 349         u32 val = 0;
 350
 351         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 352         /*
 353          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 354          * as strict.  Bits 0,1,2 - debug and management entries,
 355          * 3 - COS0 entry, 4 - COS1 entry.
 356          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 357          *  bit4   bit3   bit2      bit1     bit0
 358          * MCP and debug are strict
 359          */
 360         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 361         /*
 362          * For strict priority entries defines the number of consecutive slots
 363          * for the highest priority.
 364          */
 365         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 366         /* ETS mode disable */
 367         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 368         /* Defines the number of consecutive slots for the strict priority */
 369         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 370
 371         /* Defines the number of consecutive slots for the strict priority */
 372         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 373
 374         /*
 375          * mapping between entry  priority to client number (0,1,2 -debug and
 376          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 377          * 3bits client num.
 378          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 379          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 380          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 381          */
 382         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 383         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 384
 385         return 0;
 386 }
 387 /******************************************************************/
 388 /*                      PFC section                               */
 389 /******************************************************************/
 390
 391 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 392                                      u32 pfc_frames_sent[2],
 393                                      u32 pfc_frames_received[2])
 394 {
 395         /* Read pfc statistic */
 396         struct bnx2x *bp = params->bp;
 397         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 398                 NIG_REG_INGRESS_BMAC0_MEM;
 399
 400         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 401
 402         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 403                                         pfc_frames_sent, 2);
 404
 405         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 406                                         pfc_frames_received, 2);
 407
 408 }
 409 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 410                                     u32 pfc_frames_sent[2],
 411                                     u32 pfc_frames_received[2])
 412 {
 413         /* Read pfc statistic */
 414         struct bnx2x *bp = params->bp;
 415         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 416         u32 val_xon = 0;
 417         u32 val_xoff = 0;
 418
 419         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 420
 421         /* PFC received frames */
 422         val_xoff = REG_RD(bp, emac_base +
 423                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 424         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 425         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 426         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 427
 428         pfc_frames_received[0] = val_xon + val_xoff;
 429
 430         /* PFC received sent */
 431         val_xoff = REG_RD(bp, emac_base +
 432                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 433         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 434         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 435         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 436
 437         pfc_frames_sent[0] = val_xon + val_xoff;
 438 }
 439
 440 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 441                          u32 pfc_frames_sent[2],
 442                          u32 pfc_frames_received[2])
 443 {
 444         /* Read pfc statistic */
 445         struct bnx2x *bp = params->bp;
 446         u32 val = 0;
 447         DP(NETIF_MSG_LINK, "pfc statistic\n");
 448
 449         if (!vars->link_up)
 450                 return;
 451
 452         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 453         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 454             == 0) {
 455                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 456                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 457                                         pfc_frames_received);
 458         } else {
 459                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 460                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 461                                          pfc_frames_received);
 462         }
 463 }
 464 /******************************************************************/
 465 /*                      MAC/PBF section                           */
 466 /******************************************************************/
 467 static void bnx2x_emac_init(struct link_params *params,
 468                             struct link_vars *vars)
 469 {
 470         /* reset and unreset the emac core */
 471         struct bnx2x *bp = params->bp;
 472         u8 port = params->port;
 473         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 474         u32 val;
 475         u16 timeout;
 476
 477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 478                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 479         udelay(5);
 480         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 481                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 482
 483         /* init emac - use read-modify-write */
 484         /* self clear reset */
 485         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 486         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 487
 488         timeout = 200;
 489         do {
 490                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 491                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 492                 if (!timeout) {
 493                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 494                         return;
 495                 }
 496                 timeout--;
 497         } while (val & EMAC_MODE_RESET);
 498
 499         /* Set mac address */
 500         val = ((params->mac_addr[0] << 8) |
 501                 params->mac_addr[1]);
 502         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 503
 504         val = ((params->mac_addr[2] << 24) |
 505                (params->mac_addr[3] << 16) |
 506                (params->mac_addr[4] << 8) |
 507                 params->mac_addr[5]);
 508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 509 }
 510
 511 static u8 bnx2x_emac_enable(struct link_params *params,
 512                             struct link_vars *vars, u8 lb)
 513 {
 514         struct bnx2x *bp = params->bp;
 515         u8 port = params->port;
 516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 517         u32 val;
 518
 519         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 520
 521         /* enable emac and not bmac */
 522         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 523
 524         /* ASIC */
 525         if (vars->phy_flags & PHY_XGXS_FLAG) {
 526                 u32 ser_lane = ((params->lane_config &
 527                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 528                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 529
 530                 DP(NETIF_MSG_LINK, "XGXS\n");
 531                 /* select the master lanes (out of 0-3) */
 532                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
 533                 /* select XGXS */
 534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
 535
 536         } else { /* SerDes */
 537                 DP(NETIF_MSG_LINK, "SerDes\n");
 538                 /* select SerDes */
 539                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
 540         }
 541
 542         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 543                       EMAC_RX_MODE_RESET);
 544         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 545                       EMAC_TX_MODE_RESET);
 546
 547         if (CHIP_REV_IS_SLOW(bp)) {
 548                 /* config GMII mode */
 549                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 550                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
 551         } else { /* ASIC */
 552                 /* pause enable/disable */
 553                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 554                                EMAC_RX_MODE_FLOW_EN);
 555
 556                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 557                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 558                                 EMAC_TX_MODE_FLOW_EN));
 559                 if (!(params->feature_config_flags &
 560                       FEATURE_CONFIG_PFC_ENABLED)) {
 561                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 562                                 bnx2x_bits_en(bp, emac_base +
 563                                               EMAC_REG_EMAC_RX_MODE,
 564                                               EMAC_RX_MODE_FLOW_EN);
 565
 566                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 567                                 bnx2x_bits_en(bp, emac_base +
 568                                               EMAC_REG_EMAC_TX_MODE,
 569                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 570                                                EMAC_TX_MODE_FLOW_EN));
 571                 } else
 572                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 573                                       EMAC_TX_MODE_FLOW_EN);
 574         }
 575
 576         /* KEEP_VLAN_TAG, promiscuous */
 577         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 578         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 579
 580         /*
 581          * Setting this bit causes MAC control frames (except for pause
 582          * frames) to be passed on for processing. This setting has no
 583          * affect on the operation of the pause frames. This bit effects
 584          * all packets regardless of RX Parser packet sorting logic.
 585          * Turn the PFC off to make sure we are in Xon state before
 586          * enabling it.
 587          */
 588         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 589         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 590                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 591                 /* Enable PFC again */
 592                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 593                         EMAC_REG_RX_PFC_MODE_RX_EN |
 594                         EMAC_REG_RX_PFC_MODE_TX_EN |
 595                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 596
 597                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 598                         ((0x0101 <<
 599                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 600                          (0x00ff <<
 601                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 602                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 603         }
 604         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 605
 606         /* Set Loopback */
 607         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 608         if (lb)
 609                 val |= 0x810;
 610         else
 611                 val &= ~0x810;
 612         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 613
 614         /* enable emac */
 615         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 616
 617         /* enable emac for jumbo packets */
 618         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 619                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 620                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 621
 622         /* strip CRC */
 623         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
 624
 625         /* disable the NIG in/out to the bmac */
 626         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
 627         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
 628         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
 629
 630         /* enable the NIG in/out to the emac */
 631         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
 632         val = 0;
 633         if ((params->feature_config_flags &
 634               FEATURE_CONFIG_PFC_ENABLED) ||
 635             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 636                 val = 1;
 637
 638         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
 639         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
 640
 641         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
 642
 643         vars->mac_type = MAC_TYPE_EMAC;
 644         return 0;
 645 }
 646
 647 static void bnx2x_update_pfc_bmac1(struct link_params *params,
 648                                    struct link_vars *vars)
 649 {
 650         u32 wb_data[2];
 651         struct bnx2x *bp = params->bp;
 652         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 653                 NIG_REG_INGRESS_BMAC0_MEM;
 654
 655         u32 val = 0x14;
 656         if ((!(params->feature_config_flags &
 657               FEATURE_CONFIG_PFC_ENABLED)) &&
 658                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 659                 /* Enable BigMAC to react on received Pause packets */
 660                 val |= (1<<5);
 661         wb_data[0] = val;
 662         wb_data[1] = 0;
 663         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
 664
 665         /* tx control */
 666         val = 0xc0;
 667         if (!(params->feature_config_flags &
 668               FEATURE_CONFIG_PFC_ENABLED) &&
 669                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 670                 val |= 0x800000;
 671         wb_data[0] = val;
 672         wb_data[1] = 0;
 673         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
 674 }
 675
 676 static void bnx2x_update_pfc_bmac2(struct link_params *params,
 677                                    struct link_vars *vars,
 678                                    u8 is_lb)
 679 {
 680         /*
 681          * Set rx control: Strip CRC and enable BigMAC to relay
 682          * control packets to the system as well
 683          */
 684         u32 wb_data[2];
 685         struct bnx2x *bp = params->bp;
 686         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 687                 NIG_REG_INGRESS_BMAC0_MEM;
 688         u32 val = 0x14;
 689
 690         if ((!(params->feature_config_flags &
 691               FEATURE_CONFIG_PFC_ENABLED)) &&
 692                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 693                 /* Enable BigMAC to react on received Pause packets */
 694                 val |= (1<<5);
 695         wb_data[0] = val;
 696         wb_data[1] = 0;
 697         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
 698         udelay(30);
 699
 700         /* Tx control */
 701         val = 0xc0;
 702         if (!(params->feature_config_flags &
 703                                 FEATURE_CONFIG_PFC_ENABLED) &&
 704             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 705                 val |= 0x800000;
 706         wb_data[0] = val;
 707         wb_data[1] = 0;
 708         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
 709
 710         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 711                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 712                 /* Enable PFC RX & TX & STATS and set 8 COS  */
 713                 wb_data[0] = 0x0;
 714                 wb_data[0] |= (1<<0);  /* RX */
 715                 wb_data[0] |= (1<<1);  /* TX */
 716                 wb_data[0] |= (1<<2);  /* Force initial Xon */
 717                 wb_data[0] |= (1<<3);  /* 8 cos */
 718                 wb_data[0] |= (1<<5);  /* STATS */
 719                 wb_data[1] = 0;
 720                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
 721                             wb_data, 2);
 722                 /* Clear the force Xon */
 723                 wb_data[0] &= ~(1<<2);
 724         } else {
 725                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
 726                 /* disable PFC RX & TX & STATS and set 8 COS */
 727                 wb_data[0] = 0x8;
 728                 wb_data[1] = 0;
 729         }
 730
 731         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 732
 733         /*
 734          * Set Time (based unit is 512 bit time) between automatic
 735          * re-sending of PP packets amd enable automatic re-send of
 736          * Per-Priroity Packet as long as pp_gen is asserted and
 737          * pp_disable is low.
 738          */
 739         val = 0x8000;
 740         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 741                 val |= (1<<16); /* enable automatic re-send */
 742
 743         wb_data[0] = val;
 744         wb_data[1] = 0;
 745         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
 746                     wb_data, 2);
 747
 748         /* mac control */
 749         val = 0x3; /* Enable RX and TX */
 750         if (is_lb) {
 751                 val |= 0x4; /* Local loopback */
 752                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
 753         }
 754         /* When PFC enabled, Pass pause frames towards the NIG. */
 755         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 756                 val |= ((1<<6)|(1<<5));
 757
 758         wb_data[0] = val;
 759         wb_data[1] = 0;
 760         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
 761 }
 762
 763 static void bnx2x_update_pfc_brb(struct link_params *params,
 764                 struct link_vars *vars,
 765                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 766 {
 767         struct bnx2x *bp = params->bp;
 768         int set_pfc = params->feature_config_flags &
 769                 FEATURE_CONFIG_PFC_ENABLED;
 770
 771         /* default - pause configuration */
 772         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 773         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 774         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 775         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 776
 777         if (set_pfc && pfc_params)
 778                 /* First COS */
 779                 if (!pfc_params->cos0_pauseable) {
 780                         pause_xoff_th =
 781                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 782                         pause_xon_th =
 783                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 784                         full_xoff_th =
 785                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 786                         full_xon_th =
 787                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 788                 }
 789         /*
 790          * The number of free blocks below which the pause signal to class 0
 791          * of MAC #n is asserted. n=0,1
 792          */
 793         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
 794         /*
 795          * The number of free blocks above which the pause signal to class 0
 796          * of MAC #n is de-asserted. n=0,1
 797          */
 798         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
 799         /*
 800          * The number of free blocks below which the full signal to class 0
 801          * of MAC #n is asserted. n=0,1
 802          */
 803         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
 804         /*
 805          * The number of free blocks above which the full signal to class 0
 806          * of MAC #n is de-asserted. n=0,1
 807          */
 808         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
 809
 810         if (set_pfc && pfc_params) {
 811                 /* Second COS */
 812                 if (pfc_params->cos1_pauseable) {
 813                         pause_xoff_th =
 814                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 815                         pause_xon_th =
 816                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 817                         full_xoff_th =
 818                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 819                         full_xon_th =
 820                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 821                 } else {
 822                         pause_xoff_th =
 823                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 824                         pause_xon_th =
 825                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 826                         full_xoff_th =
 827                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 828                         full_xon_th =
 829                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 830                 }
 831                 /*
 832                  * The number of free blocks below which the pause signal to
 833                  * class 1 of MAC #n is asserted. n=0,1
 834                  */
 835                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
 836                 /*
 837                  * The number of free blocks above which the pause signal to
 838                  * class 1 of MAC #n is de-asserted. n=0,1
 839                  */
 840                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
 841                 /*
 842                  * The number of free blocks below which the full signal to
 843                  * class 1 of MAC #n is asserted. n=0,1
 844                  */
 845                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
 846                 /*
 847                  * The number of free blocks above which the full signal to
 848                  * class 1 of MAC #n is de-asserted. n=0,1
 849                  */
 850                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
 851         }
 852 }
 853
 854 static void bnx2x_update_pfc_nig(struct link_params *params,
 855                 struct link_vars *vars,
 856                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
 857 {
 858         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
 859         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
 860         u32 pkt_priority_to_cos = 0;
 861         u32 val;
 862         struct bnx2x *bp = params->bp;
 863         int port = params->port;
 864         int set_pfc = params->feature_config_flags &
 865                 FEATURE_CONFIG_PFC_ENABLED;
 866         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
 867
 868         /*
 869          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
 870          * MAC control frames (that are not pause packets)
 871          * will be forwarded to the XCM.
 872          */
 873         xcm_mask = REG_RD(bp,
 874                                 port ? NIG_REG_LLH1_XCM_MASK :
 875                                 NIG_REG_LLH0_XCM_MASK);
 876         /*
 877          * nig params will override non PFC params, since it's possible to
 878          * do transition from PFC to SAFC
 879          */
 880         if (set_pfc) {
 881                 pause_enable = 0;
 882                 llfc_out_en = 0;
 883                 llfc_enable = 0;
 884                 ppp_enable = 1;
 885                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 886                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 887                 xcm0_out_en = 0;
 888                 p0_hwpfc_enable = 1;
 889         } else  {
 890                 if (nig_params) {
 891                         llfc_out_en = nig_params->llfc_out_en;
 892                         llfc_enable = nig_params->llfc_enable;
 893                         pause_enable = nig_params->pause_enable;
 894                 } else  /*defaul non PFC mode - PAUSE */
 895                         pause_enable = 1;
 896
 897                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 898                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 899                 xcm0_out_en = 1;
 900         }
 901
 902         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
 903                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
 904         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
 905                NIG_REG_LLFC_ENABLE_0, llfc_enable);
 906         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
 907                NIG_REG_PAUSE_ENABLE_0, pause_enable);
 908
 909         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
 910                NIG_REG_PPP_ENABLE_0, ppp_enable);
 911
 912         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
 913                NIG_REG_LLH0_XCM_MASK, xcm_mask);
 914
 915         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
 916
 917         /* output enable for RX_XCM # IF */
 918         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
 919
 920         /* HW PFC TX enable */
 921         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
 922
 923         /* 0x2 = BMAC, 0x1= EMAC */
 924         switch (vars->mac_type) {
 925         case MAC_TYPE_EMAC:
 926                 val = 1;
 927                 break;
 928         case MAC_TYPE_BMAC:
 929                 val = 0;
 930                 break;
 931         default:
 932                 val = 0;
 933                 break;
 934         }
 935         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
 936
 937         if (nig_params) {
 938                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
 939
 940                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
 941                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
 942                        nig_params->rx_cos0_priority_mask);
 943
 944                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
 945                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
 946                        nig_params->rx_cos1_priority_mask);
 947
 948                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
 949                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
 950                        nig_params->llfc_high_priority_classes);
 951
 952                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
 953                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
 954                        nig_params->llfc_low_priority_classes);
 955         }
 956         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
 957                NIG_REG_P0_PKT_PRIORITY_TO_COS,
 958                pkt_priority_to_cos);
 959 }
 960
 961
 962 void bnx2x_update_pfc(struct link_params *params,
 963                       struct link_vars *vars,
 964                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 965 {
 966         /*
 967          * The PFC and pause are orthogonal to one another, meaning when
 968          * PFC is enabled, the pause are disabled, and when PFC is
 969          * disabled, pause are set according to the pause result.
 970          */
 971         u32 val;
 972         struct bnx2x *bp = params->bp;
 973
 974         /* update NIG params */
 975         bnx2x_update_pfc_nig(params, vars, pfc_params);
 976
 977         /* update BRB params */
 978         bnx2x_update_pfc_brb(params, vars, pfc_params);
 979
 980         if (!vars->link_up)
 981                 return;
 982
 983         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 984         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 985             == 0) {
 986                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
 987                 bnx2x_emac_enable(params, vars, 0);
 988                 return;
 989         }
 990
 991         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
 992         if (CHIP_IS_E2(bp))
 993                 bnx2x_update_pfc_bmac2(params, vars, 0);
 994         else
 995                 bnx2x_update_pfc_bmac1(params, vars);
 996
 997         val = 0;
 998         if ((params->feature_config_flags &
 999               FEATURE_CONFIG_PFC_ENABLED) ||
1000             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001                 val = 1;
1002         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003 }
1004
1005 static u8 bnx2x_bmac1_enable(struct link_params *params,
1006                              struct link_vars *vars,
1007                              u8 is_lb)
1008 {
1009         struct bnx2x *bp = params->bp;
1010         u8 port = params->port;
1011         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012                                NIG_REG_INGRESS_BMAC0_MEM;
1013         u32 wb_data[2];
1014         u32 val;
1015
1016         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1017
1018         /* XGXS control */
1019         wb_data[0] = 0x3c;
1020         wb_data[1] = 0;
1021         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022                     wb_data, 2);
1023
1024         /* tx MAC SA */
1025         wb_data[0] = ((params->mac_addr[2] << 24) |
1026                        (params->mac_addr[3] << 16) |
1027                        (params->mac_addr[4] << 8) |
1028                         params->mac_addr[5]);
1029         wb_data[1] = ((params->mac_addr[0] << 8) |
1030                         params->mac_addr[1]);
1031         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1032
1033         /* mac control */
1034         val = 0x3;
1035         if (is_lb) {
1036                 val |= 0x4;
1037                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038         }
1039         wb_data[0] = val;
1040         wb_data[1] = 0;
1041         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1042
1043         /* set rx mtu */
1044         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045         wb_data[1] = 0;
1046         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1047
1048         bnx2x_update_pfc_bmac1(params, vars);
1049
1050         /* set tx mtu */
1051         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052         wb_data[1] = 0;
1053         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1054
1055         /* set cnt max size */
1056         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057         wb_data[1] = 0;
1058         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1059
1060         /* configure safc */
1061         wb_data[0] = 0x1000200;
1062         wb_data[1] = 0;
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064                     wb_data, 2);
1065
1066         return 0;
1067 }
1068
1069 static u8 bnx2x_bmac2_enable(struct link_params *params,
1070                              struct link_vars *vars,
1071                              u8 is_lb)
1072 {
1073         struct bnx2x *bp = params->bp;
1074         u8 port = params->port;
1075         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076                                NIG_REG_INGRESS_BMAC0_MEM;
1077         u32 wb_data[2];
1078
1079         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081         wb_data[0] = 0;
1082         wb_data[1] = 0;
1083         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1084         udelay(30);
1085
1086         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087         wb_data[0] = 0x3c;
1088         wb_data[1] = 0;
1089         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090                     wb_data, 2);
1091
1092         udelay(30);
1093
1094         /* tx MAC SA */
1095         wb_data[0] = ((params->mac_addr[2] << 24) |
1096                        (params->mac_addr[3] << 16) |
1097                        (params->mac_addr[4] << 8) |
1098                         params->mac_addr[5]);
1099         wb_data[1] = ((params->mac_addr[0] << 8) |
1100                         params->mac_addr[1]);
1101         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1102                     wb_data, 2);
1103
1104         udelay(30);
1105
1106         /* Configure SAFC */
1107         wb_data[0] = 0x1000200;
1108         wb_data[1] = 0;
1109         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1110                     wb_data, 2);
1111         udelay(30);
1112
1113         /* set rx mtu */
1114         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115         wb_data[1] = 0;
1116         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1117         udelay(30);
1118
1119         /* set tx mtu */
1120         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121         wb_data[1] = 0;
1122         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1123         udelay(30);
1124         /* set cnt max size */
1125         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126         wb_data[1] = 0;
1127         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1128         udelay(30);
1129         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1130
1131         return 0;
1132 }
1133
1134 static u8 bnx2x_bmac_enable(struct link_params *params,
1135                             struct link_vars *vars,
1136                             u8 is_lb)
1137 {
1138         u8 rc, port = params->port;
1139         struct bnx2x *bp = params->bp;
1140         u32 val;
1141         /* reset and unreset the BigMac */
1142         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1143                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1144         msleep(1);
1145
1146         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1147                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1148
1149         /* enable access for bmac registers */
1150         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1151
1152         /* Enable BMAC according to BMAC type*/
1153         if (CHIP_IS_E2(bp))
1154                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1155         else
1156                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1157         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1158         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1159         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1160         val = 0;
1161         if ((params->feature_config_flags &
1162               FEATURE_CONFIG_PFC_ENABLED) ||
1163             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1164                 val = 1;
1165         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1166         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1167         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1168         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1169         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1170         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1171
1172         vars->mac_type = MAC_TYPE_BMAC;
1173         return rc;
1174 }
1175
1176
1177 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1178 {
1179         struct bnx2x *bp = params->bp;
1180
1181         REG_WR(bp, params->shmem_base +
1182                offsetof(struct shmem_region,
1183                         port_mb[params->port].link_status), link_status);
1184 }
1185
1186 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1187 {
1188         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1189                         NIG_REG_INGRESS_BMAC0_MEM;
1190         u32 wb_data[2];
1191         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1192
1193         /* Only if the bmac is out of reset */
1194         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1195                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1196             nig_bmac_enable) {
1197
1198                 if (CHIP_IS_E2(bp)) {
1199                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1200                         REG_RD_DMAE(bp, bmac_addr +
1201                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1202                                     wb_data, 2);
1203                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1204                         REG_WR_DMAE(bp, bmac_addr +
1205                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1206                                     wb_data, 2);
1207                 } else {
1208                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1209                         REG_RD_DMAE(bp, bmac_addr +
1210                                         BIGMAC_REGISTER_BMAC_CONTROL,
1211                                         wb_data, 2);
1212                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1213                         REG_WR_DMAE(bp, bmac_addr +
1214                                         BIGMAC_REGISTER_BMAC_CONTROL,
1215                                         wb_data, 2);
1216                 }
1217                 msleep(1);
1218         }
1219 }
1220
1221 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1222                            u32 line_speed)
1223 {
1224         struct bnx2x *bp = params->bp;
1225         u8 port = params->port;
1226         u32 init_crd, crd;
1227         u32 count = 1000;
1228
1229         /* disable port */
1230         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1231
1232         /* wait for init credit */
1233         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1234         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1235         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1236
1237         while ((init_crd != crd) && count) {
1238                 msleep(5);
1239
1240                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1241                 count--;
1242         }
1243         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1244         if (init_crd != crd) {
1245                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1246                           init_crd, crd);
1247                 return -EINVAL;
1248         }
1249
1250         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1251             line_speed == SPEED_10 ||
1252             line_speed == SPEED_100 ||
1253             line_speed == SPEED_1000 ||
1254             line_speed == SPEED_2500) {
1255                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1256                 /* update threshold */
1257                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1258                 /* update init credit */
1259                 init_crd = 778;         /* (800-18-4) */
1260
1261         } else {
1262                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1263                               ETH_OVREHEAD)/16;
1264                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1265                 /* update threshold */
1266                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1267                 /* update init credit */
1268                 switch (line_speed) {
1269                 case SPEED_10000:
1270                         init_crd = thresh + 553 - 22;
1271                         break;
1272
1273                 case SPEED_12000:
1274                         init_crd = thresh + 664 - 22;
1275                         break;
1276
1277                 case SPEED_13000:
1278                         init_crd = thresh + 742 - 22;
1279                         break;
1280
1281                 case SPEED_16000:
1282                         init_crd = thresh + 778 - 22;
1283                         break;
1284                 default:
1285                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1286                                   line_speed);
1287                         return -EINVAL;
1288                 }
1289         }
1290         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1291         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1292                  line_speed, init_crd);
1293
1294         /* probe the credit changes */
1295         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1296         msleep(5);
1297         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1298
1299         /* enable port */
1300         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1301         return 0;
1302 }
1303
1304 /**
1305  * bnx2x_get_emac_base - retrive emac base address
1306  *
1307  * @bp:                 driver handle
1308  * @mdc_mdio_access:    access type
1309  * @port:               port id
1310  *
1311  * This function selects the MDC/MDIO access (through emac0 or
1312  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1313  * phy has a default access mode, which could also be overridden
1314  * by nvram configuration. This parameter, whether this is the
1315  * default phy configuration, or the nvram overrun
1316  * configuration, is passed here as mdc_mdio_access and selects
1317  * the emac_base for the CL45 read/writes operations
1318  */
1319 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1320                                u32 mdc_mdio_access, u8 port)
1321 {
1322         u32 emac_base = 0;
1323         switch (mdc_mdio_access) {
1324         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1325                 break;
1326         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1327                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1328                         emac_base = GRCBASE_EMAC1;
1329                 else
1330                         emac_base = GRCBASE_EMAC0;
1331                 break;
1332         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1333                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1334                         emac_base = GRCBASE_EMAC0;
1335                 else
1336                         emac_base = GRCBASE_EMAC1;
1337                 break;
1338         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1339                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1340                 break;
1341         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1342                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1343                 break;
1344         default:
1345                 break;
1346         }
1347         return emac_base;
1348
1349 }
1350
1351 /******************************************************************/
1352 /*                      CL45 access functions                     */
1353 /******************************************************************/
1354 static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1355                            u8 devad, u16 reg, u16 val)
1356 {
1357         u32 tmp, saved_mode;
1358         u8 i, rc = 0;
1359         /*
1360          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1361          * (a value of 49==0x31) and make sure that the AUTO poll is off
1362          */
1363
1364         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1365         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1366                              EMAC_MDIO_MODE_CLOCK_CNT);
1367         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1368                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1369         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1370         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1371         udelay(40);
1372
1373         /* address */
1374
1375         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1376                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1377                EMAC_MDIO_COMM_START_BUSY);
1378         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1379
1380         for (i = 0; i < 50; i++) {
1381                 udelay(10);
1382
1383                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1384                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1385                         udelay(5);
1386                         break;
1387                 }
1388         }
1389         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1390                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1391                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1392                 rc = -EFAULT;
1393         } else {
1394                 /* data */
1395                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1396                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1397                        EMAC_MDIO_COMM_START_BUSY);
1398                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1399
1400                 for (i = 0; i < 50; i++) {
1401                         udelay(10);
1402
1403                         tmp = REG_RD(bp, phy->mdio_ctrl +
1404                                      EMAC_REG_EMAC_MDIO_COMM);
1405                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1406                                 udelay(5);
1407                                 break;
1408                         }
1409                 }
1410                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1411                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1412                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1413                         rc = -EFAULT;
1414                 }
1415         }
1416
1417         /* Restore the saved mode */
1418         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1419
1420         return rc;
1421 }
1422
1423 static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1424                           u8 devad, u16 reg, u16 *ret_val)
1425 {
1426         u32 val, saved_mode;
1427         u16 i;
1428         u8 rc = 0;
1429         /*
1430          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1431          * (a value of 49==0x31) and make sure that the AUTO poll is off
1432          */
1433
1434         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1435         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1436                               EMAC_MDIO_MODE_CLOCK_CNT));
1437         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1438                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1439         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1440         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1441         udelay(40);
1442
1443         /* address */
1444         val = ((phy->addr << 21) | (devad << 16) | reg |
1445                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1446                EMAC_MDIO_COMM_START_BUSY);
1447         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1448
1449         for (i = 0; i < 50; i++) {
1450                 udelay(10);
1451
1452                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1453                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1454                         udelay(5);
1455                         break;
1456                 }
1457         }
1458         if (val & EMAC_MDIO_COMM_START_BUSY) {
1459                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1460                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1461                 *ret_val = 0;
1462                 rc = -EFAULT;
1463
1464         } else {
1465                 /* data */
1466                 val = ((phy->addr << 21) | (devad << 16) |
1467                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1468                        EMAC_MDIO_COMM_START_BUSY);
1469                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1470
1471                 for (i = 0; i < 50; i++) {
1472                         udelay(10);
1473
1474                         val = REG_RD(bp, phy->mdio_ctrl +
1475                                      EMAC_REG_EMAC_MDIO_COMM);
1476                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1477                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1478                                 break;
1479                         }
1480                 }
1481                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1482                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1483                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1484                         *ret_val = 0;
1485                         rc = -EFAULT;
1486                 }
1487         }
1488
1489         /* Restore the saved mode */
1490         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1491
1492         return rc;
1493 }
1494
1495 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1496                   u8 devad, u16 reg, u16 *ret_val)
1497 {
1498         u8 phy_index;
1499         /*
1500          * Probe for the phy according to the given phy_addr, and execute
1501          * the read request on it
1502          */
1503         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1504                 if (params->phy[phy_index].addr == phy_addr) {
1505                         return bnx2x_cl45_read(params->bp,
1506                                                &params->phy[phy_index], devad,
1507                                                reg, ret_val);
1508                 }
1509         }
1510         return -EINVAL;
1511 }
1512
1513 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1514                    u8 devad, u16 reg, u16 val)
1515 {
1516         u8 phy_index;
1517         /*
1518          * Probe for the phy according to the given phy_addr, and execute
1519          * the write request on it
1520          */
1521         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1522                 if (params->phy[phy_index].addr == phy_addr) {
1523                         return bnx2x_cl45_write(params->bp,
1524                                                 &params->phy[phy_index], devad,
1525                                                 reg, val);
1526                 }
1527         }
1528         return -EINVAL;
1529 }
1530
1531 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1532                                    struct bnx2x_phy *phy)
1533 {
1534         u32 ser_lane;
1535         u16 offset, aer_val;
1536         struct bnx2x *bp = params->bp;
1537         ser_lane = ((params->lane_config &
1538                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1539                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1540
1541         offset = phy->addr + ser_lane;
1542         if (CHIP_IS_E2(bp))
1543                 aer_val = 0x3800 + offset - 1;
1544         else
1545                 aer_val = 0x3800 + offset;
1546         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1547                           MDIO_AER_BLOCK_AER_REG, aer_val);
1548 }
1549 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1550                                      struct bnx2x_phy *phy)
1551 {
1552         CL22_WR_OVER_CL45(bp, phy,
1553                           MDIO_REG_BANK_AER_BLOCK,
1554                           MDIO_AER_BLOCK_AER_REG, 0x3800);
1555 }
1556
1557 /******************************************************************/
1558 /*                      Internal phy section                      */
1559 /******************************************************************/
1560
1561 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1562 {
1563         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1564
1565         /* Set Clause 22 */
1566         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1567         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1568         udelay(500);
1569         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1570         udelay(500);
1571          /* Set Clause 45 */
1572         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1573 }
1574
1575 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1576 {
1577         u32 val;
1578
1579         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1580
1581         val = SERDES_RESET_BITS << (port*16);
1582
1583         /* reset and unreset the SerDes/XGXS */
1584         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1585         udelay(500);
1586         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1587
1588         bnx2x_set_serdes_access(bp, port);
1589
1590         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1591                DEFAULT_PHY_DEV_ADDR);
1592 }
1593
1594 static void bnx2x_xgxs_deassert(struct link_params *params)
1595 {
1596         struct bnx2x *bp = params->bp;
1597         u8 port;
1598         u32 val;
1599         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1600         port = params->port;
1601
1602         val = XGXS_RESET_BITS << (port*16);
1603
1604         /* reset and unreset the SerDes/XGXS */
1605         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1606         udelay(500);
1607         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1608
1609         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1610         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1611                params->phy[INT_PHY].def_md_devad);
1612 }
1613
1614
1615 void bnx2x_link_status_update(struct link_params *params,
1616                               struct link_vars *vars)
1617 {
1618         struct bnx2x *bp = params->bp;
1619         u8 link_10g;
1620         u8 port = params->port;
1621         u32 sync_offset, media_types;
1622         vars->link_status = REG_RD(bp, params->shmem_base +
1623                                    offsetof(struct shmem_region,
1624                                             port_mb[port].link_status));
1625
1626         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1627
1628         if (vars->link_up) {
1629                 DP(NETIF_MSG_LINK, "phy link up\n");
1630
1631                 vars->phy_link_up = 1;
1632                 vars->duplex = DUPLEX_FULL;
1633                 switch (vars->link_status &
1634                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1635                         case LINK_10THD:
1636                                 vars->duplex = DUPLEX_HALF;
1637                                 /* fall thru */
1638                         case LINK_10TFD:
1639                                 vars->line_speed = SPEED_10;
1640                                 break;
1641
1642                         case LINK_100TXHD:
1643                                 vars->duplex = DUPLEX_HALF;
1644                                 /* fall thru */
1645                         case LINK_100T4:
1646                         case LINK_100TXFD:
1647                                 vars->line_speed = SPEED_100;
1648                                 break;
1649
1650                         case LINK_1000THD:
1651                                 vars->duplex = DUPLEX_HALF;
1652                                 /* fall thru */
1653                         case LINK_1000TFD:
1654                                 vars->line_speed = SPEED_1000;
1655                                 break;
1656
1657                         case LINK_2500THD:
1658                                 vars->duplex = DUPLEX_HALF;
1659                                 /* fall thru */
1660                         case LINK_2500TFD:
1661                                 vars->line_speed = SPEED_2500;
1662                                 break;
1663
1664                         case LINK_10GTFD:
1665                                 vars->line_speed = SPEED_10000;
1666                                 break;
1667
1668                         case LINK_12GTFD:
1669                                 vars->line_speed = SPEED_12000;
1670                                 break;
1671
1672                         case LINK_12_5GTFD:
1673                                 vars->line_speed = SPEED_12500;
1674                                 break;
1675
1676                         case LINK_13GTFD:
1677                                 vars->line_speed = SPEED_13000;
1678                                 break;
1679
1680                         case LINK_15GTFD:
1681                                 vars->line_speed = SPEED_15000;
1682                                 break;
1683
1684                         case LINK_16GTFD:
1685                                 vars->line_speed = SPEED_16000;
1686                                 break;
1687
1688                         default:
1689                                 break;
1690                 }
1691                 vars->flow_ctrl = 0;
1692                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1693                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1694
1695                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1696                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1697
1698                 if (!vars->flow_ctrl)
1699                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1700
1701                 if (vars->line_speed &&
1702                     ((vars->line_speed == SPEED_10) ||
1703                      (vars->line_speed == SPEED_100))) {
1704                         vars->phy_flags |= PHY_SGMII_FLAG;
1705                 } else {
1706                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1707                 }
1708
1709                 /* anything 10 and over uses the bmac */
1710                 link_10g = ((vars->line_speed == SPEED_10000) ||
1711                             (vars->line_speed == SPEED_12000) ||
1712                             (vars->line_speed == SPEED_12500) ||
1713                             (vars->line_speed == SPEED_13000) ||
1714                             (vars->line_speed == SPEED_15000) ||
1715                             (vars->line_speed == SPEED_16000));
1716                 if (link_10g)
1717                         vars->mac_type = MAC_TYPE_BMAC;
1718                 else
1719                         vars->mac_type = MAC_TYPE_EMAC;
1720
1721         } else { /* link down */
1722                 DP(NETIF_MSG_LINK, "phy link down\n");
1723
1724                 vars->phy_link_up = 0;
1725
1726                 vars->line_speed = 0;
1727                 vars->duplex = DUPLEX_FULL;
1728                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1729
1730                 /* indicate no mac active */
1731                 vars->mac_type = MAC_TYPE_NONE;
1732         }
1733
1734         /* Sync media type */
1735         sync_offset = params->shmem_base +
1736                         offsetof(struct shmem_region,
1737                                  dev_info.port_hw_config[port].media_type);
1738         media_types = REG_RD(bp, sync_offset);
1739
1740         params->phy[INT_PHY].media_type =
1741                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
1742                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
1743         params->phy[EXT_PHY1].media_type =
1744                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
1745                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
1746         params->phy[EXT_PHY2].media_type =
1747                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
1748                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
1749         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
1750
1751         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x\n",
1752                  vars->link_status, vars->phy_link_up);
1753         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1754                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1755 }
1756
1757
1758 static void bnx2x_set_master_ln(struct link_params *params,
1759                                 struct bnx2x_phy *phy)
1760 {
1761         struct bnx2x *bp = params->bp;
1762         u16 new_master_ln, ser_lane;
1763         ser_lane = ((params->lane_config &
1764                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1765                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1766
1767         /* set the master_ln for AN */
1768         CL22_RD_OVER_CL45(bp, phy,
1769                           MDIO_REG_BANK_XGXS_BLOCK2,
1770                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1771                           &new_master_ln);
1772
1773         CL22_WR_OVER_CL45(bp, phy,
1774                           MDIO_REG_BANK_XGXS_BLOCK2 ,
1775                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1776                           (new_master_ln | ser_lane));
1777 }
1778
1779 static u8 bnx2x_reset_unicore(struct link_params *params,
1780                               struct bnx2x_phy *phy,
1781                               u8 set_serdes)
1782 {
1783         struct bnx2x *bp = params->bp;
1784         u16 mii_control;
1785         u16 i;
1786         CL22_RD_OVER_CL45(bp, phy,
1787                           MDIO_REG_BANK_COMBO_IEEE0,
1788                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1789
1790         /* reset the unicore */
1791         CL22_WR_OVER_CL45(bp, phy,
1792                           MDIO_REG_BANK_COMBO_IEEE0,
1793                           MDIO_COMBO_IEEE0_MII_CONTROL,
1794                           (mii_control |
1795                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1796         if (set_serdes)
1797                 bnx2x_set_serdes_access(bp, params->port);
1798
1799         /* wait for the reset to self clear */
1800         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1801                 udelay(5);
1802
1803                 /* the reset erased the previous bank value */
1804                 CL22_RD_OVER_CL45(bp, phy,
1805                                   MDIO_REG_BANK_COMBO_IEEE0,
1806                                   MDIO_COMBO_IEEE0_MII_CONTROL,
1807                                   &mii_control);
1808
1809                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1810                         udelay(5);
1811                         return 0;
1812                 }
1813         }
1814
1815         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
1816                               " Port %d\n",
1817                          params->port);
1818         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1819         return -EINVAL;
1820
1821 }
1822
1823 static void bnx2x_set_swap_lanes(struct link_params *params,
1824                                  struct bnx2x_phy *phy)
1825 {
1826         struct bnx2x *bp = params->bp;
1827         /*
1828          *  Each two bits represents a lane number:
1829          *  No swap is 0123 => 0x1b no need to enable the swap
1830          */
1831         u16 ser_lane, rx_lane_swap, tx_lane_swap;
1832
1833         ser_lane = ((params->lane_config &
1834                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1835                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1836         rx_lane_swap = ((params->lane_config &
1837                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1838                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1839         tx_lane_swap = ((params->lane_config &
1840                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1841                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1842
1843         if (rx_lane_swap != 0x1b) {
1844                 CL22_WR_OVER_CL45(bp, phy,
1845                                   MDIO_REG_BANK_XGXS_BLOCK2,
1846                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1847                                   (rx_lane_swap |
1848                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1849                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1850         } else {
1851                 CL22_WR_OVER_CL45(bp, phy,
1852                                   MDIO_REG_BANK_XGXS_BLOCK2,
1853                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1854         }
1855
1856         if (tx_lane_swap != 0x1b) {
1857                 CL22_WR_OVER_CL45(bp, phy,
1858                                   MDIO_REG_BANK_XGXS_BLOCK2,
1859                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1860                                   (tx_lane_swap |
1861                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1862         } else {
1863                 CL22_WR_OVER_CL45(bp, phy,
1864                                   MDIO_REG_BANK_XGXS_BLOCK2,
1865                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1866         }
1867 }
1868
1869 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1870                                          struct link_params *params)
1871 {
1872         struct bnx2x *bp = params->bp;
1873         u16 control2;
1874         CL22_RD_OVER_CL45(bp, phy,
1875                           MDIO_REG_BANK_SERDES_DIGITAL,
1876                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1877                           &control2);
1878         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1879                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1880         else
1881                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1882         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1883                 phy->speed_cap_mask, control2);
1884         CL22_WR_OVER_CL45(bp, phy,
1885                           MDIO_REG_BANK_SERDES_DIGITAL,
1886                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1887                           control2);
1888
1889         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1890              (phy->speed_cap_mask &
1891                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1892                 DP(NETIF_MSG_LINK, "XGXS\n");
1893
1894                 CL22_WR_OVER_CL45(bp, phy,
1895                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
1896                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1897                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1898
1899                 CL22_RD_OVER_CL45(bp, phy,
1900                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
1901                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1902                                   &control2);
1903
1904
1905                 control2 |=
1906                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1907
1908                 CL22_WR_OVER_CL45(bp, phy,
1909                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
1910                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1911                                   control2);
1912
1913                 /* Disable parallel detection of HiG */
1914                 CL22_WR_OVER_CL45(bp, phy,
1915                                   MDIO_REG_BANK_XGXS_BLOCK2,
1916                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1917                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1918                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1919         }
1920 }
1921
1922 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1923                               struct link_params *params,
1924                               struct link_vars *vars,
1925                               u8 enable_cl73)
1926 {
1927         struct bnx2x *bp = params->bp;
1928         u16 reg_val;
1929
1930         /* CL37 Autoneg */
1931         CL22_RD_OVER_CL45(bp, phy,
1932                           MDIO_REG_BANK_COMBO_IEEE0,
1933                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1934
1935         /* CL37 Autoneg Enabled */
1936         if (vars->line_speed == SPEED_AUTO_NEG)
1937                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1938         else /* CL37 Autoneg Disabled */
1939                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1940                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1941
1942         CL22_WR_OVER_CL45(bp, phy,
1943                           MDIO_REG_BANK_COMBO_IEEE0,
1944                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1945
1946         /* Enable/Disable Autodetection */
1947
1948         CL22_RD_OVER_CL45(bp, phy,
1949                           MDIO_REG_BANK_SERDES_DIGITAL,
1950                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1951         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1952                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1953         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1954         if (vars->line_speed == SPEED_AUTO_NEG)
1955                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1956         else
1957                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1958
1959         CL22_WR_OVER_CL45(bp, phy,
1960                           MDIO_REG_BANK_SERDES_DIGITAL,
1961                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1962
1963         /* Enable TetonII and BAM autoneg */
1964         CL22_RD_OVER_CL45(bp, phy,
1965                           MDIO_REG_BANK_BAM_NEXT_PAGE,
1966                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1967                           &reg_val);
1968         if (vars->line_speed == SPEED_AUTO_NEG) {
1969                 /* Enable BAM aneg Mode and TetonII aneg Mode */
1970                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1971                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1972         } else {
1973                 /* TetonII and BAM Autoneg Disabled */
1974                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1975                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1976         }
1977         CL22_WR_OVER_CL45(bp, phy,
1978                           MDIO_REG_BANK_BAM_NEXT_PAGE,
1979                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1980                           reg_val);
1981
1982         if (enable_cl73) {
1983                 /* Enable Cl73 FSM status bits */
1984                 CL22_WR_OVER_CL45(bp, phy,
1985                                   MDIO_REG_BANK_CL73_USERB0,
1986                                   MDIO_CL73_USERB0_CL73_UCTRL,
1987                                   0xe);
1988
1989                 /* Enable BAM Station Manager*/
1990                 CL22_WR_OVER_CL45(bp, phy,
1991                         MDIO_REG_BANK_CL73_USERB0,
1992                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1993                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1994                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1995                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1996
1997                 /* Advertise CL73 link speeds */
1998                 CL22_RD_OVER_CL45(bp, phy,
1999                                   MDIO_REG_BANK_CL73_IEEEB1,
2000                                   MDIO_CL73_IEEEB1_AN_ADV2,
2001                                   &reg_val);
2002                 if (phy->speed_cap_mask &
2003                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2004                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2005                 if (phy->speed_cap_mask &
2006                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2007                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2008
2009                 CL22_WR_OVER_CL45(bp, phy,
2010                                   MDIO_REG_BANK_CL73_IEEEB1,
2011                                   MDIO_CL73_IEEEB1_AN_ADV2,
2012                                   reg_val);
2013
2014                 /* CL73 Autoneg Enabled */
2015                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2016
2017         } else /* CL73 Autoneg Disabled */
2018                 reg_val = 0;
2019
2020         CL22_WR_OVER_CL45(bp, phy,
2021                           MDIO_REG_BANK_CL73_IEEEB0,
2022                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2023 }
2024
2025 /* program SerDes, forced speed */
2026 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2027                                  struct link_params *params,
2028                                  struct link_vars *vars)
2029 {
2030         struct bnx2x *bp = params->bp;
2031         u16 reg_val;
2032
2033         /* program duplex, disable autoneg and sgmii*/
2034         CL22_RD_OVER_CL45(bp, phy,
2035                           MDIO_REG_BANK_COMBO_IEEE0,
2036                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2037         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2038                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2039                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2040         if (phy->req_duplex == DUPLEX_FULL)
2041                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2042         CL22_WR_OVER_CL45(bp, phy,
2043                           MDIO_REG_BANK_COMBO_IEEE0,
2044                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2045
2046         /*
2047          * program speed
2048          *  - needed only if the speed is greater than 1G (2.5G or 10G)
2049          */
2050         CL22_RD_OVER_CL45(bp, phy,
2051                           MDIO_REG_BANK_SERDES_DIGITAL,
2052                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2053         /* clearing the speed value before setting the right speed */
2054         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2055
2056         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2057                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2058
2059         if (!((vars->line_speed == SPEED_1000) ||
2060               (vars->line_speed == SPEED_100) ||
2061               (vars->line_speed == SPEED_10))) {
2062
2063                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2064                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2065                 if (vars->line_speed == SPEED_10000)
2066                         reg_val |=
2067                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2068                 if (vars->line_speed == SPEED_13000)
2069                         reg_val |=
2070                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2071         }
2072
2073         CL22_WR_OVER_CL45(bp, phy,
2074                           MDIO_REG_BANK_SERDES_DIGITAL,
2075                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
2076
2077 }
2078
2079 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2080                                              struct link_params *params)
2081 {
2082         struct bnx2x *bp = params->bp;
2083         u16 val = 0;
2084
2085         /* configure the 48 bits for BAM AN */
2086
2087         /* set extended capabilities */
2088         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2089                 val |= MDIO_OVER_1G_UP1_2_5G;
2090         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2091                 val |= MDIO_OVER_1G_UP1_10G;
2092         CL22_WR_OVER_CL45(bp, phy,
2093                           MDIO_REG_BANK_OVER_1G,
2094                           MDIO_OVER_1G_UP1, val);
2095
2096         CL22_WR_OVER_CL45(bp, phy,
2097                           MDIO_REG_BANK_OVER_1G,
2098                           MDIO_OVER_1G_UP3, 0x400);
2099 }
2100
2101 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2102                                      struct link_params *params, u16 *ieee_fc)
2103 {
2104         struct bnx2x *bp = params->bp;
2105         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2106         /*
2107          * Resolve pause mode and advertisement.
2108          * Please refer to Table 28B-3 of the 802.3ab-1999 spec
2109          */
2110
2111         switch (phy->req_flow_ctrl) {
2112         case BNX2X_FLOW_CTRL_AUTO:
2113                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2114                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2115                 else
2116                         *ieee_fc |=
2117                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2118                 break;
2119         case BNX2X_FLOW_CTRL_TX:
2120                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2121                 break;
2122
2123         case BNX2X_FLOW_CTRL_RX:
2124         case BNX2X_FLOW_CTRL_BOTH:
2125                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2126                 break;
2127
2128         case BNX2X_FLOW_CTRL_NONE:
2129         default:
2130                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2131                 break;
2132         }
2133         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2134 }
2135
2136 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2137                                              struct link_params *params,
2138                                              u16 ieee_fc)
2139 {
2140         struct bnx2x *bp = params->bp;
2141         u16 val;
2142         /* for AN, we are always publishing full duplex */
2143
2144         CL22_WR_OVER_CL45(bp, phy,
2145                           MDIO_REG_BANK_COMBO_IEEE0,
2146                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2147         CL22_RD_OVER_CL45(bp, phy,
2148                           MDIO_REG_BANK_CL73_IEEEB1,
2149                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
2150         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2151         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2152         CL22_WR_OVER_CL45(bp, phy,
2153                           MDIO_REG_BANK_CL73_IEEEB1,
2154                           MDIO_CL73_IEEEB1_AN_ADV1, val);
2155 }
2156
2157 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2158                                   struct link_params *params,
2159                                   u8 enable_cl73)
2160 {
2161         struct bnx2x *bp = params->bp;
2162         u16 mii_control;
2163
2164         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2165         /* Enable and restart BAM/CL37 aneg */
2166
2167         if (enable_cl73) {
2168                 CL22_RD_OVER_CL45(bp, phy,
2169                                   MDIO_REG_BANK_CL73_IEEEB0,
2170                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2171                                   &mii_control);
2172
2173                 CL22_WR_OVER_CL45(bp, phy,
2174                                   MDIO_REG_BANK_CL73_IEEEB0,
2175                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2176                                   (mii_control |
2177                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2178                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2179         } else {
2180
2181                 CL22_RD_OVER_CL45(bp, phy,
2182                                   MDIO_REG_BANK_COMBO_IEEE0,
2183                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2184                                   &mii_control);
2185                 DP(NETIF_MSG_LINK,
2186                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2187                          mii_control);
2188                 CL22_WR_OVER_CL45(bp, phy,
2189                                   MDIO_REG_BANK_COMBO_IEEE0,
2190                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2191                                   (mii_control |
2192                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2193                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2194         }
2195 }
2196
2197 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2198                                            struct link_params *params,
2199                                            struct link_vars *vars)
2200 {
2201         struct bnx2x *bp = params->bp;
2202         u16 control1;
2203
2204         /* in SGMII mode, the unicore is always slave */
2205
2206         CL22_RD_OVER_CL45(bp, phy,
2207                           MDIO_REG_BANK_SERDES_DIGITAL,
2208                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2209                           &control1);
2210         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2211         /* set sgmii mode (and not fiber) */
2212         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2213                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2214                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2215         CL22_WR_OVER_CL45(bp, phy,
2216                           MDIO_REG_BANK_SERDES_DIGITAL,
2217                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2218                           control1);
2219
2220         /* if forced speed */
2221         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2222                 /* set speed, disable autoneg */
2223                 u16 mii_control;
2224
2225                 CL22_RD_OVER_CL45(bp, phy,
2226                                   MDIO_REG_BANK_COMBO_IEEE0,
2227                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2228                                   &mii_control);
2229                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2230                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2231                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2232
2233                 switch (vars->line_speed) {
2234                 case SPEED_100:
2235                         mii_control |=
2236                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2237                         break;
2238                 case SPEED_1000:
2239                         mii_control |=
2240                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2241                         break;
2242                 case SPEED_10:
2243                         /* there is nothing to set for 10M */
2244                         break;
2245                 default:
2246                         /* invalid speed for SGMII */
2247                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2248                                   vars->line_speed);
2249                         break;
2250                 }
2251
2252                 /* setting the full duplex */
2253                 if (phy->req_duplex == DUPLEX_FULL)
2254                         mii_control |=
2255                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2256                 CL22_WR_OVER_CL45(bp, phy,
2257                                   MDIO_REG_BANK_COMBO_IEEE0,
2258                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2259                                   mii_control);
2260
2261         } else { /* AN mode */
2262                 /* enable and restart AN */
2263                 bnx2x_restart_autoneg(phy, params, 0);
2264         }
2265 }
2266
2267
2268 /*
2269  * link management
2270  */
2271
2272 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2273 {                                               /*  LD      LP   */
2274         switch (pause_result) {                 /* ASYM P ASYM P */
2275         case 0xb:                               /*   1  0   1  1 */
2276                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2277                 break;
2278
2279         case 0xe:                               /*   1  1   1  0 */
2280                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2281                 break;
2282
2283         case 0x5:                               /*   0  1   0  1 */
2284         case 0x7:                               /*   0  1   1  1 */
2285         case 0xd:                               /*   1  1   0  1 */
2286         case 0xf:                               /*   1  1   1  1 */
2287                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2288                 break;
2289
2290         default:
2291                 break;
2292         }
2293         if (pause_result & (1<<0))
2294                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2295         if (pause_result & (1<<1))
2296                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2297 }
2298
2299 static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2300                                             struct link_params *params)
2301 {
2302         struct bnx2x *bp = params->bp;
2303         u16 pd_10g, status2_1000x;
2304         if (phy->req_line_speed != SPEED_AUTO_NEG)
2305                 return 0;
2306         CL22_RD_OVER_CL45(bp, phy,
2307                           MDIO_REG_BANK_SERDES_DIGITAL,
2308                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2309                           &status2_1000x);
2310         CL22_RD_OVER_CL45(bp, phy,
2311                           MDIO_REG_BANK_SERDES_DIGITAL,
2312                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2313                           &status2_1000x);
2314         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2315                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2316                          params->port);
2317                 return 1;
2318         }
2319
2320         CL22_RD_OVER_CL45(bp, phy,
2321                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
2322                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2323                           &pd_10g);
2324
2325         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2326                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2327                          params->port);
2328                 return 1;
2329         }
2330         return 0;
2331 }
2332
2333 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2334                                     struct link_params *params,
2335                                     struct link_vars *vars,
2336                                     u32 gp_status)
2337 {
2338         struct bnx2x *bp = params->bp;
2339         u16 ld_pause;   /* local driver */
2340         u16 lp_pause;   /* link partner */
2341         u16 pause_result;
2342
2343         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2344
2345         /* resolve from gp_status in case of AN complete and not sgmii */
2346         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2347                 vars->flow_ctrl = phy->req_flow_ctrl;
2348         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2349                 vars->flow_ctrl = params->req_fc_auto_adv;
2350         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2351                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2352                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2353                         vars->flow_ctrl = params->req_fc_auto_adv;
2354                         return;
2355                 }
2356                 if ((gp_status &
2357                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2358                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2359                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2360                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2361
2362                         CL22_RD_OVER_CL45(bp, phy,
2363                                           MDIO_REG_BANK_CL73_IEEEB1,
2364                                           MDIO_CL73_IEEEB1_AN_ADV1,
2365                                           &ld_pause);
2366                         CL22_RD_OVER_CL45(bp, phy,
2367                                           MDIO_REG_BANK_CL73_IEEEB1,
2368                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
2369                                           &lp_pause);
2370                         pause_result = (ld_pause &
2371                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2372                                         >> 8;
2373                         pause_result |= (lp_pause &
2374                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2375                                         >> 10;
2376                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2377                                  pause_result);
2378                 } else {
2379                         CL22_RD_OVER_CL45(bp, phy,
2380                                           MDIO_REG_BANK_COMBO_IEEE0,
2381                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2382                                           &ld_pause);
2383                         CL22_RD_OVER_CL45(bp, phy,
2384                                 MDIO_REG_BANK_COMBO_IEEE0,
2385                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2386                                 &lp_pause);
2387                         pause_result = (ld_pause &
2388                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2389                         pause_result |= (lp_pause &
2390                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2391                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2392                                  pause_result);
2393                 }
2394                 bnx2x_pause_resolve(vars, pause_result);
2395         }
2396         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2397 }
2398
2399 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2400                                          struct link_params *params)
2401 {
2402         struct bnx2x *bp = params->bp;
2403         u16 rx_status, ustat_val, cl37_fsm_recieved;
2404         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2405         /* Step 1: Make sure signal is detected */
2406         CL22_RD_OVER_CL45(bp, phy,
2407                           MDIO_REG_BANK_RX0,
2408                           MDIO_RX0_RX_STATUS,
2409                           &rx_status);
2410         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2411             (MDIO_RX0_RX_STATUS_SIGDET)) {
2412                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2413                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2414                 CL22_WR_OVER_CL45(bp, phy,
2415                                   MDIO_REG_BANK_CL73_IEEEB0,
2416                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2417                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2418                 return;
2419         }
2420         /* Step 2: Check CL73 state machine */
2421         CL22_RD_OVER_CL45(bp, phy,
2422                           MDIO_REG_BANK_CL73_USERB0,
2423                           MDIO_CL73_USERB0_CL73_USTAT1,
2424                           &ustat_val);
2425         if ((ustat_val &
2426              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2427               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2428             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2429               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2430                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2431                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2432                 return;
2433         }
2434         /*
2435          * Step 3: Check CL37 Message Pages received to indicate LP
2436          * supports only CL37
2437          */
2438         CL22_RD_OVER_CL45(bp, phy,
2439                           MDIO_REG_BANK_REMOTE_PHY,
2440                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
2441                           &cl37_fsm_recieved);
2442         if ((cl37_fsm_recieved &
2443              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2444              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2445             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2446               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2447                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2448                              "misc_rx_status(0x8330) = 0x%x\n",
2449                          cl37_fsm_recieved);
2450                 return;
2451         }
2452         /*
2453          * The combined cl37/cl73 fsm state information indicating that
2454          * we are connected to a device which does not support cl73, but
2455          * does support cl37 BAM. In this case we disable cl73 and
2456          * restart cl37 auto-neg
2457          */
2458
2459         /* Disable CL73 */
2460         CL22_WR_OVER_CL45(bp, phy,
2461                           MDIO_REG_BANK_CL73_IEEEB0,
2462                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2463                           0);
2464         /* Restart CL37 autoneg */
2465         bnx2x_restart_autoneg(phy, params, 0);
2466         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2467 }
2468
2469 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2470                                   struct link_params *params,
2471                                   struct link_vars *vars,
2472                                   u32 gp_status)
2473 {
2474         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2475                 vars->link_status |=
2476                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2477
2478         if (bnx2x_direct_parallel_detect_used(phy, params))
2479                 vars->link_status |=
2480                         LINK_STATUS_PARALLEL_DETECTION_USED;
2481 }
2482
2483 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2484                                      struct link_params *params,
2485                                      struct link_vars *vars)
2486 {
2487         struct bnx2x *bp = params->bp;
2488         u16 new_line_speed, gp_status;
2489         u8 rc = 0;
2490
2491         /* Read gp_status */
2492         CL22_RD_OVER_CL45(bp, phy,
2493                           MDIO_REG_BANK_GP_STATUS,
2494                           MDIO_GP_STATUS_TOP_AN_STATUS1,
2495                           &gp_status);
2496
2497         if (phy->req_line_speed == SPEED_AUTO_NEG)
2498                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2499         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2500                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2501                          gp_status);
2502
2503                 vars->phy_link_up = 1;
2504                 vars->link_status |= LINK_STATUS_LINK_UP;
2505
2506                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2507                         vars->duplex = DUPLEX_FULL;
2508                 else
2509                         vars->duplex = DUPLEX_HALF;
2510
2511                 if (SINGLE_MEDIA_DIRECT(params)) {
2512                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2513                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2514                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2515                                                       gp_status);
2516                 }
2517
2518                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2519                 case GP_STATUS_10M:
2520                         new_line_speed = SPEED_10;
2521                         if (vars->duplex == DUPLEX_FULL)
2522                                 vars->link_status |= LINK_10TFD;
2523                         else
2524                                 vars->link_status |= LINK_10THD;
2525                         break;
2526
2527                 case GP_STATUS_100M:
2528                         new_line_speed = SPEED_100;
2529                         if (vars->duplex == DUPLEX_FULL)
2530                                 vars->link_status |= LINK_100TXFD;
2531                         else
2532                                 vars->link_status |= LINK_100TXHD;
2533                         break;
2534
2535                 case GP_STATUS_1G:
2536                 case GP_STATUS_1G_KX:
2537                         new_line_speed = SPEED_1000;
2538                         if (vars->duplex == DUPLEX_FULL)
2539                                 vars->link_status |= LINK_1000TFD;
2540                         else
2541                                 vars->link_status |= LINK_1000THD;
2542                         break;
2543
2544                 case GP_STATUS_2_5G:
2545                         new_line_speed = SPEED_2500;
2546                         if (vars->duplex == DUPLEX_FULL)
2547                                 vars->link_status |= LINK_2500TFD;
2548                         else
2549                                 vars->link_status |= LINK_2500THD;
2550                         break;
2551
2552                 case GP_STATUS_5G:
2553                 case GP_STATUS_6G:
2554                         DP(NETIF_MSG_LINK,
2555                                  "link speed unsupported  gp_status 0x%x\n",
2556                                   gp_status);
2557                         return -EINVAL;
2558
2559                 case GP_STATUS_10G_KX4:
2560                 case GP_STATUS_10G_HIG:
2561                 case GP_STATUS_10G_CX4:
2562                         new_line_speed = SPEED_10000;
2563                         vars->link_status |= LINK_10GTFD;
2564                         break;
2565
2566                 case GP_STATUS_12G_HIG:
2567                         new_line_speed = SPEED_12000;
2568                         vars->link_status |= LINK_12GTFD;
2569                         break;
2570
2571                 case GP_STATUS_12_5G:
2572                         new_line_speed = SPEED_12500;
2573                         vars->link_status |= LINK_12_5GTFD;
2574                         break;
2575
2576                 case GP_STATUS_13G:
2577                         new_line_speed = SPEED_13000;
2578                         vars->link_status |= LINK_13GTFD;
2579                         break;
2580
2581                 case GP_STATUS_15G:
2582                         new_line_speed = SPEED_15000;
2583                         vars->link_status |= LINK_15GTFD;
2584                         break;
2585
2586                 case GP_STATUS_16G:
2587                         new_line_speed = SPEED_16000;
2588                         vars->link_status |= LINK_16GTFD;
2589                         break;
2590
2591                 default:
2592                         DP(NETIF_MSG_LINK,
2593                                   "link speed unsupported gp_status 0x%x\n",
2594                                   gp_status);
2595                         return -EINVAL;
2596                 }
2597
2598                 vars->line_speed = new_line_speed;
2599
2600         } else { /* link_down */
2601                 DP(NETIF_MSG_LINK, "phy link down\n");
2602
2603                 vars->phy_link_up = 0;
2604
2605                 vars->duplex = DUPLEX_FULL;
2606                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2607                 vars->mac_type = MAC_TYPE_NONE;
2608
2609                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2610                     SINGLE_MEDIA_DIRECT(params)) {
2611                         /* Check signal is detected */
2612                         bnx2x_check_fallback_to_cl37(phy, params);
2613                 }
2614         }
2615
2616         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2617                  gp_status, vars->phy_link_up, vars->line_speed);
2618         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2619                    vars->duplex, vars->flow_ctrl, vars->link_status);
2620         return rc;
2621 }
2622
2623 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2624 {
2625         struct bnx2x *bp = params->bp;
2626         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2627         u16 lp_up2;
2628         u16 tx_driver;
2629         u16 bank;
2630
2631         /* read precomp */
2632         CL22_RD_OVER_CL45(bp, phy,
2633                           MDIO_REG_BANK_OVER_1G,
2634                           MDIO_OVER_1G_LP_UP2, &lp_up2);
2635
2636         /* bits [10:7] at lp_up2, positioned at [15:12] */
2637         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2638                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2639                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2640
2641         if (lp_up2 == 0)
2642                 return;
2643
2644         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2645               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2646                 CL22_RD_OVER_CL45(bp, phy,
2647                                   bank,
2648                                   MDIO_TX0_TX_DRIVER, &tx_driver);
2649
2650                 /* replace tx_driver bits [15:12] */
2651                 if (lp_up2 !=
2652                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2653                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2654                         tx_driver |= lp_up2;
2655                         CL22_WR_OVER_CL45(bp, phy,
2656                                           bank,
2657                                           MDIO_TX0_TX_DRIVER, tx_driver);
2658                 }
2659         }
2660 }
2661
2662 static u8 bnx2x_emac_program(struct link_params *params,
2663                              struct link_vars *vars)
2664 {
2665         struct bnx2x *bp = params->bp;
2666         u8 port = params->port;
2667         u16 mode = 0;
2668
2669         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2670         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2671                        EMAC_REG_EMAC_MODE,
2672                        (EMAC_MODE_25G_MODE |
2673                         EMAC_MODE_PORT_MII_10M |
2674                         EMAC_MODE_HALF_DUPLEX));
2675         switch (vars->line_speed) {
2676         case SPEED_10:
2677                 mode |= EMAC_MODE_PORT_MII_10M;
2678                 break;
2679
2680         case SPEED_100:
2681                 mode |= EMAC_MODE_PORT_MII;
2682                 break;
2683
2684         case SPEED_1000:
2685                 mode |= EMAC_MODE_PORT_GMII;
2686                 break;
2687
2688         case SPEED_2500:
2689                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2690                 break;
2691
2692         default:
2693                 /* 10G not valid for EMAC */
2694                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2695                            vars->line_speed);
2696                 return -EINVAL;
2697         }
2698
2699         if (vars->duplex == DUPLEX_HALF)
2700                 mode |= EMAC_MODE_HALF_DUPLEX;
2701         bnx2x_bits_en(bp,
2702                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2703                       mode);
2704
2705         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2706         return 0;
2707 }
2708
2709 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2710                                   struct link_params *params)
2711 {
2712
2713         u16 bank, i = 0;
2714         struct bnx2x *bp = params->bp;
2715
2716         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2717               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2718                         CL22_WR_OVER_CL45(bp, phy,
2719                                           bank,
2720                                           MDIO_RX0_RX_EQ_BOOST,
2721                                           phy->rx_preemphasis[i]);
2722         }
2723
2724         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2725                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2726                         CL22_WR_OVER_CL45(bp, phy,
2727                                           bank,
2728                                           MDIO_TX0_TX_DRIVER,
2729                                           phy->tx_preemphasis[i]);
2730         }
2731 }
2732
2733 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2734                                     struct link_params *params,
2735                                     struct link_vars *vars)
2736 {
2737         struct bnx2x *bp = params->bp;
2738         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2739                           (params->loopback_mode == LOOPBACK_XGXS));
2740         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2741                 if (SINGLE_MEDIA_DIRECT(params) &&
2742                     (params->feature_config_flags &
2743                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2744                         bnx2x_set_preemphasis(phy, params);
2745
2746                 /* forced speed requested? */
2747                 if (vars->line_speed != SPEED_AUTO_NEG ||
2748                     (SINGLE_MEDIA_DIRECT(params) &&
2749                      params->loopback_mode == LOOPBACK_EXT)) {
2750                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2751
2752                         /* disable autoneg */
2753                         bnx2x_set_autoneg(phy, params, vars, 0);
2754
2755                         /* program speed and duplex */
2756                         bnx2x_program_serdes(phy, params, vars);
2757
2758                 } else { /* AN_mode */
2759                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2760
2761                         /* AN enabled */
2762                         bnx2x_set_brcm_cl37_advertisment(phy, params);
2763
2764                         /* program duplex & pause advertisement (for aneg) */
2765                         bnx2x_set_ieee_aneg_advertisment(phy, params,
2766                                                          vars->ieee_fc);
2767
2768                         /* enable autoneg */
2769                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2770
2771                         /* enable and restart AN */
2772                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2773                 }
2774
2775         } else { /* SGMII mode */
2776                 DP(NETIF_MSG_LINK, "SGMII\n");
2777
2778                 bnx2x_initialize_sgmii_process(phy, params, vars);
2779         }
2780 }
2781
2782 static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2783                             struct link_params *params,
2784                             struct link_vars *vars)
2785 {
2786         u8 rc;
2787         vars->phy_flags |= PHY_SGMII_FLAG;
2788         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2789         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2790         rc = bnx2x_reset_unicore(params, phy, 1);
2791         /* reset the SerDes and wait for reset bit return low */
2792         if (rc != 0)
2793                 return rc;
2794         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2795
2796         return rc;
2797 }
2798
2799 static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2800                           struct link_params *params,
2801                           struct link_vars *vars)
2802 {
2803         u8 rc;
2804         vars->phy_flags = PHY_XGXS_FLAG;
2805         if ((phy->req_line_speed &&
2806              ((phy->req_line_speed == SPEED_100) ||
2807               (phy->req_line_speed == SPEED_10))) ||
2808             (!phy->req_line_speed &&
2809              (phy->speed_cap_mask >=
2810               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2811              (phy->speed_cap_mask <
2812               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2813              ))
2814                 vars->phy_flags |= PHY_SGMII_FLAG;
2815         else
2816                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2817
2818         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2819         bnx2x_set_aer_mmd_xgxs(params, phy);
2820         bnx2x_set_master_ln(params, phy);
2821
2822         rc = bnx2x_reset_unicore(params, phy, 0);
2823         /* reset the SerDes and wait for reset bit return low */
2824         if (rc != 0)
2825                 return rc;
2826
2827         bnx2x_set_aer_mmd_xgxs(params, phy);
2828
2829         /* setting the masterLn_def again after the reset */
2830         bnx2x_set_master_ln(params, phy);
2831         bnx2x_set_swap_lanes(params, phy);
2832
2833         return rc;
2834 }
2835
2836 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2837                                      struct bnx2x_phy *phy,
2838                                      struct link_params *params)
2839 {
2840         u16 cnt, ctrl;
2841         /* Wait for soft reset to get cleared up to 1 sec */
2842         for (cnt = 0; cnt < 1000; cnt++) {
2843                 bnx2x_cl45_read(bp, phy,
2844                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2845                 if (!(ctrl & (1<<15)))
2846                         break;
2847                 msleep(1);
2848         }
2849
2850         if (cnt == 1000)
2851                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
2852                                       " Port %d\n",
2853                          params->port);
2854         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2855         return cnt;
2856 }
2857
2858 static void bnx2x_link_int_enable(struct link_params *params)
2859 {
2860         u8 port = params->port;
2861         u32 mask;
2862         struct bnx2x *bp = params->bp;
2863
2864         /* Setting the status to report on link up for either XGXS or SerDes */
2865         if (params->switch_cfg == SWITCH_CFG_10G) {
2866                 mask = (NIG_MASK_XGXS0_LINK10G |
2867                         NIG_MASK_XGXS0_LINK_STATUS);
2868                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2869                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2870                         params->phy[INT_PHY].type !=
2871                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2872                         mask |= NIG_MASK_MI_INT;
2873                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2874                 }
2875
2876         } else { /* SerDes */
2877                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2878                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2879                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2880                         params->phy[INT_PHY].type !=
2881                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2882                         mask |= NIG_MASK_MI_INT;
2883                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2884                 }
2885         }
2886         bnx2x_bits_en(bp,
2887                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2888                       mask);
2889
2890         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2891                  (params->switch_cfg == SWITCH_CFG_10G),
2892                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2893         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2894                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2895                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2896                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2897         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2898            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2899            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2900 }
2901
2902 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2903                                      u8 exp_mi_int)
2904 {
2905         u32 latch_status = 0;
2906
2907         /*
2908          * Disable the MI INT ( external phy int ) by writing 1 to the
2909          * status register. Link down indication is high-active-signal,
2910          * so in this case we need to write the status to clear the XOR
2911          */
2912         /* Read Latched signals */
2913         latch_status = REG_RD(bp,
2914                                     NIG_REG_LATCH_STATUS_0 + port*8);
2915         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2916         /* Handle only those with latched-signal=up.*/
2917         if (exp_mi_int)
2918                 bnx2x_bits_en(bp,
2919                               NIG_REG_STATUS_INTERRUPT_PORT0
2920                               + port*4,
2921                               NIG_STATUS_EMAC0_MI_INT);
2922         else
2923                 bnx2x_bits_dis(bp,
2924                                NIG_REG_STATUS_INTERRUPT_PORT0
2925                                + port*4,
2926                                NIG_STATUS_EMAC0_MI_INT);
2927
2928         if (latch_status & 1) {
2929
2930                 /* For all latched-signal=up : Re-Arm Latch signals */
2931                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2932                        (latch_status & 0xfffe) | (latch_status & 1));
2933         }
2934         /* For all latched-signal=up,Write original_signal to status */
2935 }
2936
2937 static void bnx2x_link_int_ack(struct link_params *params,
2938                                struct link_vars *vars, u8 is_10g)
2939 {
2940         struct bnx2x *bp = params->bp;
2941         u8 port = params->port;
2942
2943         /*
2944          * First reset all status we assume only one line will be
2945          * change at a time
2946          */
2947         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2948                        (NIG_STATUS_XGXS0_LINK10G |
2949                         NIG_STATUS_XGXS0_LINK_STATUS |
2950                         NIG_STATUS_SERDES0_LINK_STATUS));
2951         if (vars->phy_link_up) {
2952                 if (is_10g) {
2953                         /*
2954                          * Disable the 10G link interrupt by writing 1 to the
2955                          * status register
2956                          */
2957                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2958                         bnx2x_bits_en(bp,
2959                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2960                                       NIG_STATUS_XGXS0_LINK10G);
2961
2962                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2963                         /*
2964                          * Disable the link interrupt by writing 1 to the
2965                          * relevant lane in the status register
2966                          */
2967                         u32 ser_lane = ((params->lane_config &
2968                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2969                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2970
2971                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2972                                  vars->line_speed);
2973                         bnx2x_bits_en(bp,
2974                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2975                                       ((1 << ser_lane) <<
2976                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2977
2978                 } else { /* SerDes */
2979                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2980                         /*
2981                          * Disable the link interrupt by writing 1 to the status
2982                          * register
2983                          */
2984                         bnx2x_bits_en(bp,
2985                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2986                                       NIG_STATUS_SERDES0_LINK_STATUS);
2987                 }
2988
2989         }
2990 }
2991
2992 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2993 {
2994         u8 *str_ptr = str;
2995         u32 mask = 0xf0000000;
2996         u8 shift = 8*4;
2997         u8 digit;
2998         u8 remove_leading_zeros = 1;
2999         if (*len < 10) {
3000                 /* Need more than 10chars for this format */
3001                 *str_ptr = '\0';
3002                 (*len)--;
3003                 return -EINVAL;
3004         }
3005         while (shift > 0) {
3006
3007                 shift -= 4;
3008                 digit = ((num & mask) >> shift);
3009                 if (digit == 0 && remove_leading_zeros) {
3010                         mask = mask >> 4;
3011                         continue;
3012                 } else if (digit < 0xa)
3013                         *str_ptr = digit + '0';
3014                 else
3015                         *str_ptr = digit - 0xa + 'a';
3016                 remove_leading_zeros = 0;
3017                 str_ptr++;
3018                 (*len)--;
3019                 mask = mask >> 4;
3020                 if (shift == 4*4) {
3021                         *str_ptr = '.';
3022                         str_ptr++;
3023                         (*len)--;
3024                         remove_leading_zeros = 1;
3025                 }
3026         }
3027         return 0;
3028 }
3029
3030
3031 static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3032 {
3033         str[0] = '\0';
3034         (*len)--;
3035         return 0;
3036 }
3037
3038 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3039                               u8 *version, u16 len)
3040 {
3041         struct bnx2x *bp;
3042         u32 spirom_ver = 0;
3043         u8 status = 0;
3044         u8 *ver_p = version;
3045         u16 remain_len = len;
3046         if (version == NULL || params == NULL)
3047                 return -EINVAL;
3048         bp = params->bp;
3049
3050         /* Extract first external phy*/
3051         version[0] = '\0';
3052         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3053
3054         if (params->phy[EXT_PHY1].format_fw_ver) {
3055                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3056                                                               ver_p,
3057                                                               &remain_len);
3058                 ver_p += (len - remain_len);
3059         }
3060         if ((params->num_phys == MAX_PHYS) &&
3061             (params->phy[EXT_PHY2].ver_addr != 0)) {
3062                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3063                 if (params->phy[EXT_PHY2].format_fw_ver) {
3064                         *ver_p = '/';
3065                         ver_p++;
3066                         remain_len--;
3067                         status |= params->phy[EXT_PHY2].format_fw_ver(
3068                                 spirom_ver,
3069                                 ver_p,
3070                                 &remain_len);
3071                         ver_p = version + (len - remain_len);
3072                 }
3073         }
3074         *ver_p = '\0';
3075         return status;
3076 }
3077
3078 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3079                                     struct link_params *params)
3080 {
3081         u8 port = params->port;
3082         struct bnx2x *bp = params->bp;
3083
3084         if (phy->req_line_speed != SPEED_1000) {
3085                 u32 md_devad;
3086
3087                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3088
3089                 /* change the uni_phy_addr in the nig */
3090                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3091                                        port*0x18));
3092
3093                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3094
3095                 bnx2x_cl45_write(bp, phy,
3096                                  5,
3097                                  (MDIO_REG_BANK_AER_BLOCK +
3098                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
3099                                  0x2800);
3100
3101                 bnx2x_cl45_write(bp, phy,
3102                                  5,
3103                                  (MDIO_REG_BANK_CL73_IEEEB0 +
3104                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3105                                  0x6041);
3106                 msleep(200);
3107                 /* set aer mmd back */
3108                 bnx2x_set_aer_mmd_xgxs(params, phy);
3109
3110                 /* and md_devad */
3111                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3112         } else {
3113                 u16 mii_ctrl;
3114                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3115                 bnx2x_cl45_read(bp, phy, 5,
3116                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3117                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3118                                 &mii_ctrl);
3119                 bnx2x_cl45_write(bp, phy, 5,
3120                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3121                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3122                                  mii_ctrl |
3123                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3124         }
3125 }
3126
3127 u8 bnx2x_set_led(struct link_params *params,
3128                  struct link_vars *vars, u8 mode, u32 speed)
3129 {
3130         u8 port = params->port;
3131         u16 hw_led_mode = params->hw_led_mode;
3132         u8 rc = 0, phy_idx;
3133         u32 tmp;
3134         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3135         struct bnx2x *bp = params->bp;
3136         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3137         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3138                  speed, hw_led_mode);
3139         /* In case */
3140         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3141                 if (params->phy[phy_idx].set_link_led) {
3142                         params->phy[phy_idx].set_link_led(
3143                                 &params->phy[phy_idx], params, mode);
3144                 }
3145         }
3146
3147         switch (mode) {
3148         case LED_MODE_FRONT_PANEL_OFF:
3149         case LED_MODE_OFF:
3150                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3151                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3152                        SHARED_HW_CFG_LED_MAC1);
3153
3154                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3155                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3156                 break;
3157
3158         case LED_MODE_OPER:
3159                 /*
3160                  * For all other phys, OPER mode is same as ON, so in case
3161                  * link is down, do nothing
3162                  */
3163                 if (!vars->link_up)
3164                         break;
3165         case LED_MODE_ON:
3166                 if (((params->phy[EXT_PHY1].type ==
3167                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3168                          (params->phy[EXT_PHY1].type ==
3169                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
3170                     CHIP_IS_E2(bp) && params->num_phys == 2) {
3171                         /*
3172                          * This is a work-around for E2+8727 Configurations
3173                          */
3174                         if (mode == LED_MODE_ON ||
3175                                 speed == SPEED_10000){
3176                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3177                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3178
3179                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3180                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3181                                         (tmp | EMAC_LED_OVERRIDE));
3182                                 return rc;
3183                         }
3184                 } else if (SINGLE_MEDIA_DIRECT(params)) {
3185                         /*
3186                          * This is a work-around for HW issue found when link
3187                          * is up in CL73
3188                          */
3189                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3190                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3191                 } else {
3192                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3193                 }
3194
3195                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3196                 /* Set blinking rate to ~15.9Hz */
3197                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3198                        LED_BLINK_RATE_VAL);
3199                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3200                        port*4, 1);
3201                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3202                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3203
3204                 if (CHIP_IS_E1(bp) &&
3205                     ((speed == SPEED_2500) ||
3206                      (speed == SPEED_1000) ||
3207                      (speed == SPEED_100) ||
3208                      (speed == SPEED_10))) {
3209                         /*
3210                          * On Everest 1 Ax chip versions for speeds less than
3211                          * 10G LED scheme is different
3212                          */
3213                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3214                                + port*4, 1);
3215                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3216                                port*4, 0);
3217                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3218                                port*4, 1);
3219                 }
3220                 break;
3221
3222         default:
3223                 rc = -EINVAL;
3224                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3225                          mode);
3226                 break;
3227         }
3228         return rc;
3229
3230 }
3231
3232 /*
3233  * This function comes to reflect the actual link state read DIRECTLY from the
3234  * HW
3235  */
3236 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3237                    u8 is_serdes)
3238 {
3239         struct bnx2x *bp = params->bp;
3240         u16 gp_status = 0, phy_index = 0;
3241         u8 ext_phy_link_up = 0, serdes_phy_type;
3242         struct link_vars temp_vars;
3243
3244         CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3245                           MDIO_REG_BANK_GP_STATUS,
3246                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3247                           &gp_status);
3248         /* link is up only if both local phy and external phy are up */
3249         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3250                 return -ESRCH;
3251
3252         switch (params->num_phys) {
3253         case 1:
3254                 /* No external PHY */
3255                 return 0;
3256         case 2:
3257                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3258                         &params->phy[EXT_PHY1],
3259                         params, &temp_vars);
3260                 break;
3261         case 3: /* Dual Media */
3262                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3263                       phy_index++) {
3264                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3265                                             ETH_PHY_SFP_FIBER) ||
3266                                            (params->phy[phy_index].media_type ==
3267                                             ETH_PHY_XFP_FIBER) ||
3268                                            (params->phy[phy_index].media_type ==
3269                                             ETH_PHY_DA_TWINAX));
3270
3271                         if (is_serdes != serdes_phy_type)
3272                                 continue;
3273                         if (params->phy[phy_index].read_status) {
3274                                 ext_phy_link_up |=
3275                                         params->phy[phy_index].read_status(
3276                                                 &params->phy[phy_index],
3277                                                 params, &temp_vars);
3278                         }
3279                 }
3280                 break;
3281         }
3282         if (ext_phy_link_up)
3283                 return 0;
3284         return -ESRCH;
3285 }
3286
3287 static u8 bnx2x_link_initialize(struct link_params *params,
3288                                 struct link_vars *vars)
3289 {
3290         u8 rc = 0;
3291         u8 phy_index, non_ext_phy;
3292         struct bnx2x *bp = params->bp;
3293         /*
3294          * In case of external phy existence, the line speed would be the
3295          * line speed linked up by the external phy. In case it is direct
3296          * only, then the line_speed during initialization will be
3297          * equal to the req_line_speed
3298          */
3299         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3300
3301         /*
3302          * Initialize the internal phy in case this is a direct board
3303          * (no external phys), or this board has external phy which requires
3304          * to first.
3305          */
3306
3307         if (params->phy[INT_PHY].config_init)
3308                 params->phy[INT_PHY].config_init(
3309                         &params->phy[INT_PHY],
3310                         params, vars);
3311
3312         /* init ext phy and enable link state int */
3313         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3314                        (params->loopback_mode == LOOPBACK_XGXS));
3315
3316         if (non_ext_phy ||
3317             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3318             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3319                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3320                 if (vars->line_speed == SPEED_AUTO_NEG)
3321                         bnx2x_set_parallel_detection(phy, params);
3322                 bnx2x_init_internal_phy(phy, params, vars);
3323         }
3324
3325         /* Init external phy*/
3326         if (!non_ext_phy)
3327                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3328                       phy_index++) {
3329                         /*
3330                          * No need to initialize second phy in case of first
3331                          * phy only selection. In case of second phy, we do
3332                          * need to initialize the first phy, since they are
3333                          * connected.
3334                          */
3335                         if (phy_index == EXT_PHY2 &&
3336                             (bnx2x_phy_selection(params) ==
3337                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3338                                 DP(NETIF_MSG_LINK, "Ignoring second phy\n");
3339                                 continue;
3340                         }
3341                         params->phy[phy_index].config_init(
3342                                 &params->phy[phy_index],
3343                                 params, vars);
3344                 }
3345
3346         /* Reset the interrupt indication after phy was initialized */
3347         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3348                        params->port*4,
3349                        (NIG_STATUS_XGXS0_LINK10G |
3350                         NIG_STATUS_XGXS0_LINK_STATUS |
3351                         NIG_STATUS_SERDES0_LINK_STATUS |
3352                         NIG_MASK_MI_INT));
3353         return rc;
3354 }
3355
3356 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3357                                  struct link_params *params)
3358 {
3359         /* reset the SerDes/XGXS */
3360         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3361                (0x1ff << (params->port*16)));
3362 }
3363
3364 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3365                                         struct link_params *params)
3366 {
3367         struct bnx2x *bp = params->bp;
3368         u8 gpio_port;
3369         /* HW reset */
3370         if (CHIP_IS_E2(bp))
3371                 gpio_port = BP_PATH(bp);
3372         else
3373                 gpio_port = params->port;
3374         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3375                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3376                        gpio_port);
3377         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3378                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3379                        gpio_port);
3380         DP(NETIF_MSG_LINK, "reset external PHY\n");
3381 }
3382
3383 static u8 bnx2x_update_link_down(struct link_params *params,
3384                                struct link_vars *vars)
3385 {
3386         struct bnx2x *bp = params->bp;
3387         u8 port = params->port;
3388
3389         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3390         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3391
3392         /* indicate no mac active */
3393         vars->mac_type = MAC_TYPE_NONE;
3394
3395         /* update shared memory */
3396         vars->link_status = 0;
3397         vars->line_speed = 0;
3398         bnx2x_update_mng(params, vars->link_status);
3399
3400         /* activate nig drain */
3401         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3402
3403         /* disable emac */
3404         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3405
3406         msleep(10);
3407
3408         /* reset BigMac */
3409         bnx2x_bmac_rx_disable(bp, params->port);
3410         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3411                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3412         return 0;
3413 }
3414
3415 static u8 bnx2x_update_link_up(struct link_params *params,
3416                              struct link_vars *vars,
3417                              u8 link_10g)
3418 {
3419         struct bnx2x *bp = params->bp;
3420         u8 port = params->port;
3421         u8 rc = 0;
3422
3423         vars->link_status |= LINK_STATUS_LINK_UP;
3424
3425         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3426                 vars->link_status |=
3427                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3428
3429         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3430                 vars->link_status |=
3431                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3432
3433         if (link_10g) {
3434                 bnx2x_bmac_enable(params, vars, 0);
3435                 bnx2x_set_led(params, vars,
3436                               LED_MODE_OPER, SPEED_10000);
3437         } else {
3438                 rc = bnx2x_emac_program(params, vars);
3439
3440                 bnx2x_emac_enable(params, vars, 0);
3441
3442                 /* AN complete? */
3443                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3444                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3445                     SINGLE_MEDIA_DIRECT(params))
3446                         bnx2x_set_gmii_tx_driver(params);
3447         }
3448
3449         /* PBF - link up */
3450         if (!(CHIP_IS_E2(bp)))
3451                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3452                                        vars->line_speed);
3453
3454         /* disable drain */
3455         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3456
3457         /* update shared memory */
3458         bnx2x_update_mng(params, vars->link_status);
3459         msleep(20);
3460         return rc;
3461 }
3462 /*
3463  * The bnx2x_link_update function should be called upon link
3464  * interrupt.
3465  * Link is considered up as follows:
3466  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3467  *   to be up
3468  * - SINGLE_MEDIA - The link between the 577xx and the external
3469  *   phy (XGXS) need to up as well as the external link of the
3470  *   phy (PHY_EXT1)
3471  * - DUAL_MEDIA - The link between the 577xx and the first
3472  *   external phy needs to be up, and at least one of the 2
3473  *   external phy link must be up.
3474  */
3475 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3476 {
3477         struct bnx2x *bp = params->bp;
3478         struct link_vars phy_vars[MAX_PHYS];
3479         u8 port = params->port;
3480         u8 link_10g, phy_index;
3481         u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3482         u8 is_mi_int = 0;
3483         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3484         u8 active_external_phy = INT_PHY;
3485         vars->link_status = 0;
3486         for (phy_index = INT_PHY; phy_index < params->num_phys;
3487               phy_index++) {
3488                 phy_vars[phy_index].flow_ctrl = 0;
3489                 phy_vars[phy_index].link_status = 0;
3490                 phy_vars[phy_index].line_speed = 0;
3491                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3492                 phy_vars[phy_index].phy_link_up = 0;
3493                 phy_vars[phy_index].link_up = 0;
3494         }
3495
3496         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3497                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3498                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3499
3500         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3501                                 port*0x18) > 0);
3502         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3503                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3504                  is_mi_int,
3505                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3506
3507         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3508           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3509           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3510
3511         /* disable emac */
3512         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3513
3514         /*
3515          * Step 1:
3516          * Check external link change only for external phys, and apply
3517          * priority selection between them in case the link on both phys
3518          * is up. Note that the instead of the common vars, a temporary
3519          * vars argument is used since each phy may have different link/
3520          * speed/duplex result
3521          */
3522         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3523               phy_index++) {
3524                 struct bnx2x_phy *phy = &params->phy[phy_index];
3525                 if (!phy->read_status)
3526                         continue;
3527                 /* Read link status and params of this ext phy */
3528                 cur_link_up = phy->read_status(phy, params,
3529                                                &phy_vars[phy_index]);
3530                 if (cur_link_up) {
3531                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3532                                    phy_index);
3533                 } else {
3534                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3535                                    phy_index);
3536                         continue;
3537                 }
3538
3539                 if (!ext_phy_link_up) {
3540                         ext_phy_link_up = 1;
3541                         active_external_phy = phy_index;
3542                 } else {
3543                         switch (bnx2x_phy_selection(params)) {
3544                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3545                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3546                         /*
3547                          * In this option, the first PHY makes sure to pass the
3548                          * traffic through itself only.
3549                          * Its not clear how to reset the link on the second phy
3550                          */
3551                                 active_external_phy = EXT_PHY1;
3552                                 break;
3553                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3554                         /*
3555                          * In this option, the first PHY makes sure to pass the
3556                          * traffic through the second PHY.
3557                          */
3558                                 active_external_phy = EXT_PHY2;
3559                                 break;
3560                         default:
3561                         /*
3562                          * Link indication on both PHYs with the following cases
3563                          * is invalid:
3564                          * - FIRST_PHY means that second phy wasn't initialized,
3565                          * hence its link is expected to be down
3566                          * - SECOND_PHY means that first phy should not be able
3567                          * to link up by itself (using configuration)
3568                          * - DEFAULT should be overriden during initialiazation
3569                          */
3570                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3571                                            "mpc=0x%x. DISABLING LINK !!!\n",
3572                                            params->multi_phy_config);
3573                                 ext_phy_link_up = 0;
3574                                 break;
3575                         }
3576                 }
3577         }
3578         prev_line_speed = vars->line_speed;
3579         /*
3580          * Step 2:
3581          * Read the status of the internal phy. In case of
3582          * DIRECT_SINGLE_MEDIA board, this link is the external link,
3583          * otherwise this is the link between the 577xx and the first
3584          * external phy
3585          */
3586         if (params->phy[INT_PHY].read_status)
3587                 params->phy[INT_PHY].read_status(
3588                         &params->phy[INT_PHY],
3589                         params, vars);
3590         /*
3591          * The INT_PHY flow control reside in the vars. This include the
3592          * case where the speed or flow control are not set to AUTO.
3593          * Otherwise, the active external phy flow control result is set
3594          * to the vars. The ext_phy_line_speed is needed to check if the
3595          * speed is different between the internal phy and external phy.
3596          * This case may be result of intermediate link speed change.
3597          */
3598         if (active_external_phy > INT_PHY) {
3599                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3600                 /*
3601                  * Link speed is taken from the XGXS. AN and FC result from
3602                  * the external phy.
3603                  */
3604                 vars->link_status |= phy_vars[active_external_phy].link_status;
3605
3606                 /*
3607                  * if active_external_phy is first PHY and link is up - disable
3608                  * disable TX on second external PHY
3609                  */
3610                 if (active_external_phy == EXT_PHY1) {
3611                         if (params->phy[EXT_PHY2].phy_specific_func) {
3612                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3613                                                    " EXT_PHY2\n");
3614                                 params->phy[EXT_PHY2].phy_specific_func(
3615                                         &params->phy[EXT_PHY2],
3616                                         params, DISABLE_TX);
3617                         }
3618                 }
3619
3620                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3621                 vars->duplex = phy_vars[active_external_phy].duplex;
3622                 if (params->phy[active_external_phy].supported &
3623                     SUPPORTED_FIBRE)
3624                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3625                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3626                            active_external_phy);
3627         }
3628
3629         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3630               phy_index++) {
3631                 if (params->phy[phy_index].flags &
3632                     FLAGS_REARM_LATCH_SIGNAL) {
3633                         bnx2x_rearm_latch_signal(bp, port,
3634                                                  phy_index ==
3635                                                  active_external_phy);
3636                         break;
3637                 }
3638         }
3639         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3640                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3641                    vars->link_status, ext_phy_line_speed);
3642         /*
3643          * Upon link speed change set the NIG into drain mode. Comes to
3644          * deals with possible FIFO glitch due to clk change when speed
3645          * is decreased without link down indicator
3646          */
3647
3648         if (vars->phy_link_up) {
3649                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3650                     (ext_phy_line_speed != vars->line_speed)) {
3651                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3652                                    " different than the external"
3653                                    " link speed %d\n", vars->line_speed,
3654                                    ext_phy_line_speed);
3655                         vars->phy_link_up = 0;
3656                 } else if (prev_line_speed != vars->line_speed) {
3657                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3658                                0);
3659                         msleep(1);
3660                 }
3661         }
3662
3663         /* anything 10 and over uses the bmac */
3664         link_10g = ((vars->line_speed == SPEED_10000) ||
3665                     (vars->line_speed == SPEED_12000) ||
3666                     (vars->line_speed == SPEED_12500) ||
3667                     (vars->line_speed == SPEED_13000) ||
3668                     (vars->line_speed == SPEED_15000) ||
3669                     (vars->line_speed == SPEED_16000));
3670
3671         bnx2x_link_int_ack(params, vars, link_10g);
3672
3673         /*
3674          * In case external phy link is up, and internal link is down
3675          * (not initialized yet probably after link initialization, it
3676          * needs to be initialized.
3677          * Note that after link down-up as result of cable plug, the xgxs
3678          * link would probably become up again without the need
3679          * initialize it
3680          */
3681         if (!(SINGLE_MEDIA_DIRECT(params))) {
3682                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3683                            " init_preceding = %d\n", ext_phy_link_up,
3684                            vars->phy_link_up,
3685                            params->phy[EXT_PHY1].flags &
3686                            FLAGS_INIT_XGXS_FIRST);
3687                 if (!(params->phy[EXT_PHY1].flags &
3688                       FLAGS_INIT_XGXS_FIRST)
3689                     && ext_phy_link_up && !vars->phy_link_up) {
3690                         vars->line_speed = ext_phy_line_speed;
3691                         if (vars->line_speed < SPEED_1000)
3692                                 vars->phy_flags |= PHY_SGMII_FLAG;
3693                         else
3694                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3695                         bnx2x_init_internal_phy(&params->phy[INT_PHY],
3696                                                 params,
3697                                                 vars);
3698                 }
3699         }
3700         /*
3701          * Link is up only if both local phy and external phy (in case of
3702          * non-direct board) are up
3703          */
3704         vars->link_up = (vars->phy_link_up &&
3705                          (ext_phy_link_up ||
3706                           SINGLE_MEDIA_DIRECT(params)));
3707
3708         if (vars->link_up)
3709                 rc = bnx2x_update_link_up(params, vars, link_10g);
3710         else
3711                 rc = bnx2x_update_link_down(params, vars);
3712
3713         return rc;
3714 }
3715
3716
3717 /*****************************************************************************/
3718 /*                          External Phy section                             */
3719 /*****************************************************************************/
3720 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3721 {
3722         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3723                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3724         msleep(1);
3725         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3726                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3727 }
3728
3729 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3730                                       u32 spirom_ver, u32 ver_addr)
3731 {
3732         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3733                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3734
3735         if (ver_addr)
3736                 REG_WR(bp, ver_addr, spirom_ver);
3737 }
3738
3739 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3740                                       struct bnx2x_phy *phy,
3741                                       u8 port)
3742 {
3743         u16 fw_ver1, fw_ver2;
3744
3745         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3746                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3747         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3748                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3749         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3750                                   phy->ver_addr);
3751 }
3752
3753 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3754                                     struct bnx2x_phy *phy,
3755                                     struct link_vars *vars)
3756 {
3757         u16 val;
3758         struct bnx2x *bp = params->bp;
3759         /* read modify write pause advertizing */
3760         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3761
3762         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3763
3764         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3765         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3766         if ((vars->ieee_fc &
3767             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3768             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3769                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3770         }
3771         if ((vars->ieee_fc &
3772             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3773             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3774                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3775         }
3776         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3777         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3778 }
3779
3780 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3781                                    struct link_params *params,
3782                                    struct link_vars *vars)
3783 {
3784         struct bnx2x *bp = params->bp;
3785         u16 ld_pause;           /* local */
3786         u16 lp_pause;           /* link partner */
3787         u16 pause_result;
3788         u8 ret = 0;
3789         /* read twice */
3790
3791         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3792
3793         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3794                 vars->flow_ctrl = phy->req_flow_ctrl;
3795         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3796                 vars->flow_ctrl = params->req_fc_auto_adv;
3797         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3798                 ret = 1;
3799                 bnx2x_cl45_read(bp, phy,
3800                                 MDIO_AN_DEVAD,
3801                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3802                 bnx2x_cl45_read(bp, phy,
3803                                 MDIO_AN_DEVAD,
3804                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3805                 pause_result = (ld_pause &
3806                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3807                 pause_result |= (lp_pause &
3808                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3809                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3810                    pause_result);
3811                 bnx2x_pause_resolve(vars, pause_result);
3812         }
3813         return ret;
3814 }
3815
3816 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3817                                        struct bnx2x_phy *phy,
3818                                        struct link_vars *vars)
3819 {
3820         u16 val;
3821         bnx2x_cl45_read(bp, phy,
3822                         MDIO_AN_DEVAD,
3823                         MDIO_AN_REG_STATUS, &val);
3824         bnx2x_cl45_read(bp, phy,
3825                         MDIO_AN_DEVAD,
3826                         MDIO_AN_REG_STATUS, &val);
3827         if (val & (1<<5))
3828                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3829         if ((val & (1<<0)) == 0)
3830                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3831 }
3832
3833 /******************************************************************/
3834 /*              common BCM8073/BCM8727 PHY SECTION                */
3835 /******************************************************************/
3836 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3837                                   struct link_params *params,
3838                                   struct link_vars *vars)
3839 {
3840         struct bnx2x *bp = params->bp;
3841         if (phy->req_line_speed == SPEED_10 ||
3842             phy->req_line_speed == SPEED_100) {
3843                 vars->flow_ctrl = phy->req_flow_ctrl;
3844                 return;
3845         }
3846
3847         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3848             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3849                 u16 pause_result;
3850                 u16 ld_pause;           /* local */
3851                 u16 lp_pause;           /* link partner */
3852                 bnx2x_cl45_read(bp, phy,
3853                                 MDIO_AN_DEVAD,
3854                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3855
3856                 bnx2x_cl45_read(bp, phy,
3857                                 MDIO_AN_DEVAD,
3858                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3859                 pause_result = (ld_pause &
3860                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3861                 pause_result |= (lp_pause &
3862                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3863
3864                 bnx2x_pause_resolve(vars, pause_result);
3865                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3866                            pause_result);
3867         }
3868 }
3869 static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3870                                               struct bnx2x_phy *phy,
3871                                               u8 port)
3872 {
3873         u32 count = 0;
3874         u16 fw_ver1, fw_msgout;
3875         u8 rc = 0;
3876
3877         /* Boot port from external ROM  */
3878         /* EDC grst */
3879         bnx2x_cl45_write(bp, phy,
3880                          MDIO_PMA_DEVAD,
3881                          MDIO_PMA_REG_GEN_CTRL,
3882                          0x0001);
3883
3884         /* ucode reboot and rst */
3885         bnx2x_cl45_write(bp, phy,
3886                          MDIO_PMA_DEVAD,
3887                          MDIO_PMA_REG_GEN_CTRL,
3888                          0x008c);
3889
3890         bnx2x_cl45_write(bp, phy,
3891                          MDIO_PMA_DEVAD,
3892                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3893
3894         /* Reset internal microprocessor */
3895         bnx2x_cl45_write(bp, phy,
3896                          MDIO_PMA_DEVAD,
3897                          MDIO_PMA_REG_GEN_CTRL,
3898                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3899
3900         /* Release srst bit */
3901         bnx2x_cl45_write(bp, phy,
3902                          MDIO_PMA_DEVAD,
3903                          MDIO_PMA_REG_GEN_CTRL,
3904                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3905
3906         /* Delay 100ms per the PHY specifications */
3907         msleep(100);
3908
3909         /* 8073 sometimes taking longer to download */
3910         do {
3911                 count++;
3912                 if (count > 300) {
3913                         DP(NETIF_MSG_LINK,
3914                                  "bnx2x_8073_8727_external_rom_boot port %x:"
3915                                  "Download failed. fw version = 0x%x\n",
3916                                  port, fw_ver1);
3917                         rc = -EINVAL;
3918                         break;
3919                 }
3920
3921                 bnx2x_cl45_read(bp, phy,
3922                                 MDIO_PMA_DEVAD,
3923                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3924                 bnx2x_cl45_read(bp, phy,
3925                                 MDIO_PMA_DEVAD,
3926                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3927
3928                 msleep(1);
3929         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3930                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3931                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3932
3933         /* Clear ser_boot_ctl bit */
3934         bnx2x_cl45_write(bp, phy,
3935                          MDIO_PMA_DEVAD,
3936                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3937         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3938
3939         DP(NETIF_MSG_LINK,
3940                  "bnx2x_8073_8727_external_rom_boot port %x:"
3941                  "Download complete. fw version = 0x%x\n",
3942                  port, fw_ver1);
3943
3944         return rc;
3945 }
3946
3947 /******************************************************************/
3948 /*                      BCM8073 PHY SECTION                       */
3949 /******************************************************************/
3950 static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3951 {
3952         /* This is only required for 8073A1, version 102 only */
3953         u16 val;
3954
3955         /* Read 8073 HW revision*/
3956         bnx2x_cl45_read(bp, phy,
3957                         MDIO_PMA_DEVAD,
3958                         MDIO_PMA_REG_8073_CHIP_REV, &val);
3959
3960         if (val != 1) {
3961                 /* No need to workaround in 8073 A1 */
3962                 return 0;
3963         }
3964
3965         bnx2x_cl45_read(bp, phy,
3966                         MDIO_PMA_DEVAD,
3967                         MDIO_PMA_REG_ROM_VER2, &val);
3968
3969         /* SNR should be applied only for version 0x102 */
3970         if (val != 0x102)
3971                 return 0;
3972
3973         return 1;
3974 }
3975
3976 static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3977 {
3978         u16 val, cnt, cnt1 ;
3979
3980         bnx2x_cl45_read(bp, phy,
3981                         MDIO_PMA_DEVAD,
3982                         MDIO_PMA_REG_8073_CHIP_REV, &val);
3983
3984         if (val > 0) {
3985                 /* No need to workaround in 8073 A1 */
3986                 return 0;
3987         }
3988         /* XAUI workaround in 8073 A0: */
3989
3990         /*
3991          * After loading the boot ROM and restarting Autoneg, poll
3992          * Dev1, Reg $C820:
3993          */
3994
3995         for (cnt = 0; cnt < 1000; cnt++) {
3996                 bnx2x_cl45_read(bp, phy,
3997                                 MDIO_PMA_DEVAD,
3998                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3999                                 &val);
4000                   /*
4001                    * If bit [14] = 0 or bit [13] = 0, continue on with
4002                    * system initialization (XAUI work-around not required, as
4003                    * these bits indicate 2.5G or 1G link up).
4004                    */
4005                 if (!(val & (1<<14)) || !(val & (1<<13))) {
4006                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4007                         return 0;
4008                 } else if (!(val & (1<<15))) {
4009                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
4010                         /*
4011                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
4012                          * MSB (bit15) goes to 1 (indicating that the XAUI
4013                          * workaround has completed), then continue on with
4014                          * system initialization.
4015                          */
4016                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4017                                 bnx2x_cl45_read(bp, phy,
4018                                         MDIO_PMA_DEVAD,
4019                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4020                                 if (val & (1<<15)) {
4021                                         DP(NETIF_MSG_LINK,
4022                                           "XAUI workaround has completed\n");
4023                                         return 0;
4024                                  }
4025                                  msleep(3);
4026                         }
4027                         break;
4028                 }
4029                 msleep(3);
4030         }
4031         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4032         return -EINVAL;
4033 }
4034
4035 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4036 {
4037         /* Force KR or KX */
4038         bnx2x_cl45_write(bp, phy,
4039                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4040         bnx2x_cl45_write(bp, phy,
4041                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4042         bnx2x_cl45_write(bp, phy,
4043                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4044         bnx2x_cl45_write(bp, phy,
4045                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4046 }
4047
4048 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4049                                       struct bnx2x_phy *phy,
4050                                       struct link_vars *vars)
4051 {
4052         u16 cl37_val;
4053         struct bnx2x *bp = params->bp;
4054         bnx2x_cl45_read(bp, phy,
4055                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4056
4057         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4058         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4059         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4060         if ((vars->ieee_fc &
4061             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4062             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4063                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4064         }
4065         if ((vars->ieee_fc &
4066             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4067             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4068                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4069         }
4070         if ((vars->ieee_fc &
4071             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4072             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4073                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4074         }
4075         DP(NETIF_MSG_LINK,
4076                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4077
4078         bnx2x_cl45_write(bp, phy,
4079                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4080         msleep(500);
4081 }
4082
4083 static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4084                                  struct link_params *params,
4085                                  struct link_vars *vars)
4086 {
4087         struct bnx2x *bp = params->bp;
4088         u16 val = 0, tmp1;
4089         u8 gpio_port;
4090         DP(NETIF_MSG_LINK, "Init 8073\n");
4091
4092         if (CHIP_IS_E2(bp))
4093                 gpio_port = BP_PATH(bp);
4094         else
4095                 gpio_port = params->port;
4096         /* Restore normal power mode*/
4097         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4098                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4099
4100         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4101                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4102
4103         /* enable LASI */
4104         bnx2x_cl45_write(bp, phy,
4105                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4106         bnx2x_cl45_write(bp, phy,
4107                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4108
4109         bnx2x_8073_set_pause_cl37(params, phy, vars);
4110
4111         bnx2x_cl45_read(bp, phy,
4112                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4113
4114         bnx2x_cl45_read(bp, phy,
4115                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4116
4117         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4118
4119         /* Swap polarity if required - Must be done only in non-1G mode */
4120         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4121                 /* Configure the 8073 to swap _P and _N of the KR lines */
4122                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4123                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4124                 bnx2x_cl45_read(bp, phy,
4125                                 MDIO_PMA_DEVAD,
4126                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4127                 bnx2x_cl45_write(bp, phy,
4128                                  MDIO_PMA_DEVAD,
4129                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4130                                  (val | (3<<9)));
4131         }
4132
4133
4134         /* Enable CL37 BAM */
4135         if (REG_RD(bp, params->shmem_base +
4136                          offsetof(struct shmem_region, dev_info.
4137                                   port_hw_config[params->port].default_cfg)) &
4138             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4139
4140                 bnx2x_cl45_read(bp, phy,
4141                                 MDIO_AN_DEVAD,
4142                                 MDIO_AN_REG_8073_BAM, &val);
4143                 bnx2x_cl45_write(bp, phy,
4144                                  MDIO_AN_DEVAD,
4145                                  MDIO_AN_REG_8073_BAM, val | 1);
4146                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4147         }
4148         if (params->loopback_mode == LOOPBACK_EXT) {
4149                 bnx2x_807x_force_10G(bp, phy);
4150                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4151                 return 0;
4152         } else {
4153                 bnx2x_cl45_write(bp, phy,
4154                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4155         }
4156         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4157                 if (phy->req_line_speed == SPEED_10000) {
4158                         val = (1<<7);
4159                 } else if (phy->req_line_speed ==  SPEED_2500) {
4160                         val = (1<<5);
4161                         /*
4162                          * Note that 2.5G works only when used with 1G
4163                          * advertisement
4164                          */
4165                 } else
4166                         val = (1<<5);
4167         } else {
4168                 val = 0;
4169                 if (phy->speed_cap_mask &
4170                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4171                         val |= (1<<7);
4172
4173                 /* Note that 2.5G works only when used with 1G advertisement */
4174                 if (phy->speed_cap_mask &
4175                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4176                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4177                         val |= (1<<5);
4178                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4179         }
4180
4181         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4182         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4183
4184         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4185              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4186             (phy->req_line_speed == SPEED_2500)) {
4187                 u16 phy_ver;
4188                 /* Allow 2.5G for A1 and above */
4189                 bnx2x_cl45_read(bp, phy,
4190                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4191                                 &phy_ver);
4192                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4193                 if (phy_ver > 0)
4194                         tmp1 |= 1;
4195                 else
4196                         tmp1 &= 0xfffe;
4197         } else {
4198                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4199                 tmp1 &= 0xfffe;
4200         }
4201
4202         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4203         /* Add support for CL37 (passive mode) II */
4204
4205         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4206         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4207                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4208                                   0x20 : 0x40)));
4209
4210         /* Add support for CL37 (passive mode) III */
4211         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4212
4213         /*
4214          * The SNR will improve about 2db by changing BW and FEE main
4215          * tap. Rest commands are executed after link is up
4216          * Change FFE main cursor to 5 in EDC register
4217          */
4218         if (bnx2x_8073_is_snr_needed(bp, phy))
4219                 bnx2x_cl45_write(bp, phy,
4220                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4221                                  0xFB0C);
4222
4223         /* Enable FEC (Forware Error Correction) Request in the AN */
4224         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4225         tmp1 |= (1<<15);
4226         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4227
4228         bnx2x_ext_phy_set_pause(params, phy, vars);
4229
4230         /* Restart autoneg */
4231         msleep(500);
4232         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4233         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4234                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4235         return 0;
4236 }
4237
4238 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4239                                  struct link_params *params,
4240                                  struct link_vars *vars)
4241 {
4242         struct bnx2x *bp = params->bp;
4243         u8 link_up = 0;
4244         u16 val1, val2;
4245         u16 link_status = 0;
4246         u16 an1000_status = 0;
4247
4248         bnx2x_cl45_read(bp, phy,
4249                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4250
4251         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4252
4253         /* clear the interrupt LASI status register */
4254         bnx2x_cl45_read(bp, phy,
4255                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4256         bnx2x_cl45_read(bp, phy,
4257                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4258         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4259         /* Clear MSG-OUT */
4260         bnx2x_cl45_read(bp, phy,
4261                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4262
4263         /* Check the LASI */
4264         bnx2x_cl45_read(bp, phy,
4265                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4266
4267         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4268
4269         /* Check the link status */
4270         bnx2x_cl45_read(bp, phy,
4271                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4272         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4273
4274         bnx2x_cl45_read(bp, phy,
4275                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4276         bnx2x_cl45_read(bp, phy,
4277                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4278         link_up = ((val1 & 4) == 4);
4279         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4280
4281         if (link_up &&
4282              ((phy->req_line_speed != SPEED_10000))) {
4283                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4284                         return 0;
4285         }
4286         bnx2x_cl45_read(bp, phy,
4287                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4288         bnx2x_cl45_read(bp, phy,
4289                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4290
4291         /* Check the link status on 1.1.2 */
4292         bnx2x_cl45_read(bp, phy,
4293                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4294         bnx2x_cl45_read(bp, phy,
4295                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4296         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4297                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4298
4299         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4300         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4301                 /*
4302                  * The SNR will improve about 2dbby changing the BW and FEE main
4303                  * tap. The 1st write to change FFE main tap is set before
4304                  * restart AN. Change PLL Bandwidth in EDC register
4305                  */
4306                 bnx2x_cl45_write(bp, phy,
4307                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4308                                  0x26BC);
4309
4310                 /* Change CDR Bandwidth in EDC register */
4311                 bnx2x_cl45_write(bp, phy,
4312                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4313                                  0x0333);
4314         }
4315         bnx2x_cl45_read(bp, phy,
4316                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4317                         &link_status);
4318
4319         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4320         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4321                 link_up = 1;
4322                 vars->line_speed = SPEED_10000;
4323                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4324                            params->port);
4325         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4326                 link_up = 1;
4327                 vars->line_speed = SPEED_2500;
4328                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4329                            params->port);
4330         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4331                 link_up = 1;
4332                 vars->line_speed = SPEED_1000;
4333                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4334                            params->port);
4335         } else {
4336                 link_up = 0;
4337                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4338                            params->port);
4339         }
4340
4341         if (link_up) {
4342                 /* Swap polarity if required */
4343                 if (params->lane_config &
4344                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4345                         /* Configure the 8073 to swap P and N of the KR lines */
4346                         bnx2x_cl45_read(bp, phy,
4347                                         MDIO_XS_DEVAD,
4348                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4349                         /*
4350                          * Set bit 3 to invert Rx in 1G mode and clear this bit
4351                          * when it`s in 10G mode.
4352                          */
4353                         if (vars->line_speed == SPEED_1000) {
4354                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4355                                               "the 8073\n");
4356                                 val1 |= (1<<3);
4357                         } else
4358                                 val1 &= ~(1<<3);
4359
4360                         bnx2x_cl45_write(bp, phy,
4361                                          MDIO_XS_DEVAD,
4362                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
4363                                          val1);
4364                 }
4365                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4366                 bnx2x_8073_resolve_fc(phy, params, vars);
4367                 vars->duplex = DUPLEX_FULL;
4368         }
4369         return link_up;
4370 }
4371
4372 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4373                                   struct link_params *params)
4374 {
4375         struct bnx2x *bp = params->bp;
4376         u8 gpio_port;
4377         if (CHIP_IS_E2(bp))
4378                 gpio_port = BP_PATH(bp);
4379         else
4380                 gpio_port = params->port;
4381         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4382            gpio_port);
4383         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4384                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4385                        gpio_port);
4386 }
4387
4388 /******************************************************************/
4389 /*                      BCM8705 PHY SECTION                       */
4390 /******************************************************************/
4391 static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4392                                  struct link_params *params,
4393                                  struct link_vars *vars)
4394 {
4395         struct bnx2x *bp = params->bp;
4396         DP(NETIF_MSG_LINK, "init 8705\n");
4397         /* Restore normal power mode*/
4398         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4399                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4400         /* HW reset */
4401         bnx2x_ext_phy_hw_reset(bp, params->port);
4402         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4403         bnx2x_wait_reset_complete(bp, phy, params);
4404
4405         bnx2x_cl45_write(bp, phy,
4406                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4407         bnx2x_cl45_write(bp, phy,
4408                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4409         bnx2x_cl45_write(bp, phy,
4410                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4411         bnx2x_cl45_write(bp, phy,
4412                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4413         /* BCM8705 doesn't have microcode, hence the 0 */
4414         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4415         return 0;
4416 }
4417
4418 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4419                                  struct link_params *params,
4420                                  struct link_vars *vars)
4421 {
4422         u8 link_up = 0;
4423         u16 val1, rx_sd;
4424         struct bnx2x *bp = params->bp;
4425         DP(NETIF_MSG_LINK, "read status 8705\n");
4426         bnx2x_cl45_read(bp, phy,
4427                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4428         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4429
4430         bnx2x_cl45_read(bp, phy,
4431                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4432         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4433
4434         bnx2x_cl45_read(bp, phy,
4435                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4436
4437         bnx2x_cl45_read(bp, phy,
4438                       MDIO_PMA_DEVAD, 0xc809, &val1);
4439         bnx2x_cl45_read(bp, phy,
4440                       MDIO_PMA_DEVAD, 0xc809, &val1);
4441
4442         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4443         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4444         if (link_up) {
4445                 vars->line_speed = SPEED_10000;
4446                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4447         }
4448         return link_up;
4449 }
4450
4451 /******************************************************************/
4452 /*                      SFP+ module Section                       */
4453 /******************************************************************/
4454 static u8 bnx2x_get_gpio_port(struct link_params *params)
4455 {
4456         u8 gpio_port;
4457         u32 swap_val, swap_override;
4458         struct bnx2x *bp = params->bp;
4459         if (CHIP_IS_E2(bp))
4460                 gpio_port = BP_PATH(bp);
4461         else
4462                 gpio_port = params->port;
4463         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4464         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4465         return gpio_port ^ (swap_val && swap_override);
4466 }
4467 static void bnx2x_sfp_set_transmitter(struct link_params *params,
4468                                       struct bnx2x_phy *phy,
4469                                       u8 tx_en)
4470 {
4471         u16 val;
4472         u8 port = params->port;
4473         struct bnx2x *bp = params->bp;
4474         u32 tx_en_mode;
4475
4476         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4477         tx_en_mode = REG_RD(bp, params->shmem_base +
4478                             offsetof(struct shmem_region,
4479                                      dev_info.port_hw_config[port].sfp_ctrl)) &
4480                 PORT_HW_CFG_TX_LASER_MASK;
4481         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4482                            "mode = %x\n", tx_en, port, tx_en_mode);
4483         switch (tx_en_mode) {
4484         case PORT_HW_CFG_TX_LASER_MDIO:
4485
4486                 bnx2x_cl45_read(bp, phy,
4487                                 MDIO_PMA_DEVAD,
4488                                 MDIO_PMA_REG_PHY_IDENTIFIER,
4489                                 &val);
4490
4491                 if (tx_en)
4492                         val &= ~(1<<15);
4493                 else
4494                         val |= (1<<15);
4495
4496                 bnx2x_cl45_write(bp, phy,
4497                                  MDIO_PMA_DEVAD,
4498                                  MDIO_PMA_REG_PHY_IDENTIFIER,
4499                                  val);
4500         break;
4501         case PORT_HW_CFG_TX_LASER_GPIO0:
4502         case PORT_HW_CFG_TX_LASER_GPIO1:
4503         case PORT_HW_CFG_TX_LASER_GPIO2:
4504         case PORT_HW_CFG_TX_LASER_GPIO3:
4505         {
4506                 u16 gpio_pin;
4507                 u8 gpio_port, gpio_mode;
4508                 if (tx_en)
4509                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4510                 else
4511                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4512
4513                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4514                 gpio_port = bnx2x_get_gpio_port(params);
4515                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4516                 break;
4517         }
4518         default:
4519                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4520                 break;
4521         }
4522 }
4523
4524 static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4525                                             struct link_params *params,
4526                                             u16 addr, u8 byte_cnt, u8 *o_buf)
4527 {
4528         struct bnx2x *bp = params->bp;
4529         u16 val = 0;
4530         u16 i;
4531         if (byte_cnt > 16) {
4532                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4533                             " is limited to 0xf\n");
4534                 return -EINVAL;
4535         }
4536         /* Set the read command byte count */
4537         bnx2x_cl45_write(bp, phy,
4538                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4539                          (byte_cnt | 0xa000));
4540
4541         /* Set the read command address */
4542         bnx2x_cl45_write(bp, phy,
4543                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4544                          addr);
4545
4546         /* Activate read command */
4547         bnx2x_cl45_write(bp, phy,
4548                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4549                          0x2c0f);
4550
4551         /* Wait up to 500us for command complete status */
4552         for (i = 0; i < 100; i++) {
4553                 bnx2x_cl45_read(bp, phy,
4554                                 MDIO_PMA_DEVAD,
4555                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4556                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4557                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4558                         break;
4559                 udelay(5);
4560         }
4561
4562         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4563                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4564                 DP(NETIF_MSG_LINK,
4565                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4566                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4567                 return -EINVAL;
4568         }
4569
4570         /* Read the buffer */
4571         for (i = 0; i < byte_cnt; i++) {
4572                 bnx2x_cl45_read(bp, phy,
4573                                 MDIO_PMA_DEVAD,
4574                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4575                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4576         }
4577
4578         for (i = 0; i < 100; i++) {
4579                 bnx2x_cl45_read(bp, phy,
4580                                 MDIO_PMA_DEVAD,
4581                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4582                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4583                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4584                         return 0;
4585                 msleep(1);
4586         }
4587         return -EINVAL;
4588 }
4589
4590 static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4591                                             struct link_params *params,
4592                                             u16 addr, u8 byte_cnt, u8 *o_buf)
4593 {
4594         struct bnx2x *bp = params->bp;
4595         u16 val, i;
4596
4597         if (byte_cnt > 16) {
4598                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4599                             " is limited to 0xf\n");
4600                 return -EINVAL;
4601         }
4602
4603         /* Need to read from 1.8000 to clear it */
4604         bnx2x_cl45_read(bp, phy,
4605                         MDIO_PMA_DEVAD,
4606                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4607                         &val);
4608
4609         /* Set the read command byte count */
4610         bnx2x_cl45_write(bp, phy,
4611                          MDIO_PMA_DEVAD,
4612                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4613                          ((byte_cnt < 2) ? 2 : byte_cnt));
4614
4615         /* Set the read command address */
4616         bnx2x_cl45_write(bp, phy,
4617                          MDIO_PMA_DEVAD,
4618                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4619                          addr);
4620         /* Set the destination address */
4621         bnx2x_cl45_write(bp, phy,
4622                          MDIO_PMA_DEVAD,
4623                          0x8004,
4624                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4625
4626         /* Activate read command */
4627         bnx2x_cl45_write(bp, phy,
4628                          MDIO_PMA_DEVAD,
4629                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4630                          0x8002);
4631         /*
4632          * Wait appropriate time for two-wire command to finish before
4633          * polling the status register
4634          */
4635         msleep(1);
4636
4637         /* Wait up to 500us for command complete status */
4638         for (i = 0; i < 100; i++) {
4639                 bnx2x_cl45_read(bp, phy,
4640                                 MDIO_PMA_DEVAD,
4641                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4642                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4643                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4644                         break;
4645                 udelay(5);
4646         }
4647
4648         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4649                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4650                 DP(NETIF_MSG_LINK,
4651                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4652                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4653                 return -EFAULT;
4654         }
4655
4656         /* Read the buffer */
4657         for (i = 0; i < byte_cnt; i++) {
4658                 bnx2x_cl45_read(bp, phy,
4659                                 MDIO_PMA_DEVAD,
4660                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4661                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4662         }
4663
4664         for (i = 0; i < 100; i++) {
4665                 bnx2x_cl45_read(bp, phy,
4666                                 MDIO_PMA_DEVAD,
4667                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4668                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4669                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4670                         return 0;
4671                 msleep(1);
4672         }
4673
4674         return -EINVAL;
4675 }
4676
4677 u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4678                                 struct link_params *params, u16 addr,
4679                                 u8 byte_cnt, u8 *o_buf)
4680 {
4681         u8 rc = -EINVAL;
4682         switch (phy->type) {
4683         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4684                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4685                                                        byte_cnt, o_buf);
4686         break;
4687         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4688         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4689                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4690                                                        byte_cnt, o_buf);
4691         break;
4692         }
4693         return rc;
4694 }
4695
4696 static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4697                              struct link_params *params,
4698                              u16 *edc_mode)
4699 {
4700         struct bnx2x *bp = params->bp;
4701         u32 sync_offset = 0, phy_idx, media_types;
4702         u8 val, check_limiting_mode = 0;
4703         *edc_mode = EDC_MODE_LIMITING;
4704
4705         phy->media_type = ETH_PHY_UNSPECIFIED;
4706         /* First check for copper cable */
4707         if (bnx2x_read_sfp_module_eeprom(phy,
4708                                          params,
4709                                          SFP_EEPROM_CON_TYPE_ADDR,
4710                                          1,
4711                                          &val) != 0) {
4712                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4713                 return -EINVAL;
4714         }
4715
4716         switch (val) {
4717         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4718         {
4719                 u8 copper_module_type;
4720                 phy->media_type = ETH_PHY_DA_TWINAX;
4721                 /*
4722                  * Check if its active cable (includes SFP+ module)
4723                  * of passive cable
4724                  */
4725                 if (bnx2x_read_sfp_module_eeprom(phy,
4726                                                params,
4727                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4728                                                1,
4729                                                &copper_module_type) !=
4730                     0) {
4731                         DP(NETIF_MSG_LINK,
4732                                 "Failed to read copper-cable-type"
4733                                 " from SFP+ EEPROM\n");
4734                         return -EINVAL;
4735                 }
4736
4737                 if (copper_module_type &
4738                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4739                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4740                         check_limiting_mode = 1;
4741                 } else if (copper_module_type &
4742                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4743                                 DP(NETIF_MSG_LINK, "Passive Copper"
4744                                             " cable detected\n");
4745                                 *edc_mode =
4746                                       EDC_MODE_PASSIVE_DAC;
4747                 } else {
4748                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4749                                      "type 0x%x !!!\n", copper_module_type);
4750                         return -EINVAL;
4751                 }
4752                 break;
4753         }
4754         case SFP_EEPROM_CON_TYPE_VAL_LC:
4755                 phy->media_type = ETH_PHY_SFP_FIBER;
4756                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4757                 check_limiting_mode = 1;
4758                 break;
4759         default:
4760                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4761                          val);
4762                 return -EINVAL;
4763         }
4764         sync_offset = params->shmem_base +
4765                 offsetof(struct shmem_region,
4766                          dev_info.port_hw_config[params->port].media_type);
4767         media_types = REG_RD(bp, sync_offset);
4768         /* Update media type for non-PMF sync */
4769         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
4770                 if (&(params->phy[phy_idx]) == phy) {
4771                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
4772                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4773                         media_types |= ((phy->media_type &
4774                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
4775                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4776                         break;
4777                 }
4778         }
4779         REG_WR(bp, sync_offset, media_types);
4780         if (check_limiting_mode) {
4781                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4782                 if (bnx2x_read_sfp_module_eeprom(phy,
4783                                                  params,
4784                                                  SFP_EEPROM_OPTIONS_ADDR,
4785                                                  SFP_EEPROM_OPTIONS_SIZE,
4786                                                  options) != 0) {
4787                         DP(NETIF_MSG_LINK, "Failed to read Option"
4788                                 " field from module EEPROM\n");
4789                         return -EINVAL;
4790                 }
4791                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4792                         *edc_mode = EDC_MODE_LINEAR;
4793                 else
4794                         *edc_mode = EDC_MODE_LIMITING;
4795         }
4796         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4797         return 0;
4798 }
4799 /*
4800  * This function read the relevant field from the module (SFP+), and verify it
4801  * is compliant with this board
4802  */
4803 static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4804                                   struct link_params *params)
4805 {
4806         struct bnx2x *bp = params->bp;
4807         u32 val, cmd;
4808         u32 fw_resp, fw_cmd_param;
4809         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4810         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4811         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4812         val = REG_RD(bp, params->shmem_base +
4813                          offsetof(struct shmem_region, dev_info.
4814                                   port_feature_config[params->port].config));
4815         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4816             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4817                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4818                 return 0;
4819         }
4820
4821         if (params->feature_config_flags &
4822             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4823                 /* Use specific phy request */
4824                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4825         } else if (params->feature_config_flags &
4826                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4827                 /* Use first phy request only in case of non-dual media*/
4828                 if (DUAL_MEDIA(params)) {
4829                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4830                            "verification\n");
4831                         return -EINVAL;
4832                 }
4833                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4834         } else {
4835                 /* No support in OPT MDL detection */
4836                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4837                           "verification\n");
4838                 return -EINVAL;
4839         }
4840
4841         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4842         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4843         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4844                 DP(NETIF_MSG_LINK, "Approved module\n");
4845                 return 0;
4846         }
4847
4848         /* format the warning message */
4849         if (bnx2x_read_sfp_module_eeprom(phy,
4850                                          params,
4851                                          SFP_EEPROM_VENDOR_NAME_ADDR,
4852                                          SFP_EEPROM_VENDOR_NAME_SIZE,
4853                                          (u8 *)vendor_name))
4854                 vendor_name[0] = '\0';
4855         else
4856                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4857         if (bnx2x_read_sfp_module_eeprom(phy,
4858                                          params,
4859                                          SFP_EEPROM_PART_NO_ADDR,
4860                                          SFP_EEPROM_PART_NO_SIZE,
4861                                          (u8 *)vendor_pn))
4862                 vendor_pn[0] = '\0';
4863         else
4864                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4865
4866         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
4867                               " Port %d from %s part number %s\n",
4868                          params->port, vendor_name, vendor_pn);
4869         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4870         return -EINVAL;
4871 }
4872
4873 static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4874                                                 struct link_params *params)
4875
4876 {
4877         u8 val;
4878         struct bnx2x *bp = params->bp;
4879         u16 timeout;
4880         /*
4881          * Initialization time after hot-plug may take up to 300ms for
4882          * some phys type ( e.g. JDSU )
4883          */
4884
4885         for (timeout = 0; timeout < 60; timeout++) {
4886                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4887                     == 0) {
4888                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4889                                      "took %d ms\n", timeout * 5);
4890                         return 0;
4891                 }
4892                 msleep(5);
4893         }
4894         return -EINVAL;
4895 }
4896
4897 static void bnx2x_8727_power_module(struct bnx2x *bp,
4898                                     struct bnx2x_phy *phy,
4899                                     u8 is_power_up) {
4900         /* Make sure GPIOs are not using for LED mode */
4901         u16 val;
4902         /*
4903          * In the GPIO register, bit 4 is use to determine if the GPIOs are
4904          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4905          * output
4906          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4907          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4908          * where the 1st bit is the over-current(only input), and 2nd bit is
4909          * for power( only output )
4910          *
4911          * In case of NOC feature is disabled and power is up, set GPIO control
4912          *  as input to enable listening of over-current indication
4913          */
4914         if (phy->flags & FLAGS_NOC)
4915                 return;
4916         if (!(phy->flags &
4917               FLAGS_NOC) && is_power_up)
4918                 val = (1<<4);
4919         else
4920                 /*
4921                  * Set GPIO control to OUTPUT, and set the power bit
4922                  * to according to the is_power_up
4923                  */
4924                 val = ((!(is_power_up)) << 1);
4925
4926         bnx2x_cl45_write(bp, phy,
4927                          MDIO_PMA_DEVAD,
4928                          MDIO_PMA_REG_8727_GPIO_CTRL,
4929                          val);
4930 }
4931
4932 static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4933                                        struct bnx2x_phy *phy,
4934                                        u16 edc_mode)
4935 {
4936         u16 cur_limiting_mode;
4937
4938         bnx2x_cl45_read(bp, phy,
4939                         MDIO_PMA_DEVAD,
4940                         MDIO_PMA_REG_ROM_VER2,
4941                         &cur_limiting_mode);
4942         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4943                  cur_limiting_mode);
4944
4945         if (edc_mode == EDC_MODE_LIMITING) {
4946                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
4947                 bnx2x_cl45_write(bp, phy,
4948                                  MDIO_PMA_DEVAD,
4949                                  MDIO_PMA_REG_ROM_VER2,
4950                                  EDC_MODE_LIMITING);
4951         } else { /* LRM mode ( default )*/
4952
4953                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4954
4955                 /*
4956                  * Changing to LRM mode takes quite few seconds. So do it only
4957                  * if current mode is limiting (default is LRM)
4958                  */
4959                 if (cur_limiting_mode != EDC_MODE_LIMITING)
4960                         return 0;
4961
4962                 bnx2x_cl45_write(bp, phy,
4963                                  MDIO_PMA_DEVAD,
4964                                  MDIO_PMA_REG_LRM_MODE,
4965                                  0);
4966                 bnx2x_cl45_write(bp, phy,
4967                                  MDIO_PMA_DEVAD,
4968                                  MDIO_PMA_REG_ROM_VER2,
4969                                  0x128);
4970                 bnx2x_cl45_write(bp, phy,
4971                                  MDIO_PMA_DEVAD,
4972                                  MDIO_PMA_REG_MISC_CTRL0,
4973                                  0x4008);
4974                 bnx2x_cl45_write(bp, phy,
4975                                  MDIO_PMA_DEVAD,
4976                                  MDIO_PMA_REG_LRM_MODE,
4977                                  0xaaaa);
4978         }
4979         return 0;
4980 }
4981
4982 static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4983                                        struct bnx2x_phy *phy,
4984                                        u16 edc_mode)
4985 {
4986         u16 phy_identifier;
4987         u16 rom_ver2_val;
4988         bnx2x_cl45_read(bp, phy,
4989                         MDIO_PMA_DEVAD,
4990                         MDIO_PMA_REG_PHY_IDENTIFIER,
4991                         &phy_identifier);
4992
4993         bnx2x_cl45_write(bp, phy,
4994                          MDIO_PMA_DEVAD,
4995                          MDIO_PMA_REG_PHY_IDENTIFIER,
4996                          (phy_identifier & ~(1<<9)));
4997
4998         bnx2x_cl45_read(bp, phy,
4999                         MDIO_PMA_DEVAD,
5000                         MDIO_PMA_REG_ROM_VER2,
5001                         &rom_ver2_val);
5002         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
5003         bnx2x_cl45_write(bp, phy,
5004                          MDIO_PMA_DEVAD,
5005                          MDIO_PMA_REG_ROM_VER2,
5006                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
5007
5008         bnx2x_cl45_write(bp, phy,
5009                          MDIO_PMA_DEVAD,
5010                          MDIO_PMA_REG_PHY_IDENTIFIER,
5011                          (phy_identifier | (1<<9)));
5012
5013         return 0;
5014 }
5015
5016 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
5017                                      struct link_params *params,
5018                                      u32 action)
5019 {
5020         struct bnx2x *bp = params->bp;
5021
5022         switch (action) {
5023         case DISABLE_TX:
5024                 bnx2x_sfp_set_transmitter(params, phy, 0);
5025                 break;
5026         case ENABLE_TX:
5027                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
5028                         bnx2x_sfp_set_transmitter(params, phy, 1);
5029                 break;
5030         default:
5031                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5032                    action);
5033                 return;
5034         }
5035 }
5036
5037 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5038                                            u8 gpio_mode)
5039 {
5040         struct bnx2x *bp = params->bp;
5041
5042         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5043                             offsetof(struct shmem_region,
5044                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
5045                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5046         switch (fault_led_gpio) {
5047         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5048                 return;
5049         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5050         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5051         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5052         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5053         {
5054                 u8 gpio_port = bnx2x_get_gpio_port(params);
5055                 u16 gpio_pin = fault_led_gpio -
5056                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5057                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5058                                    "pin %x port %x mode %x\n",
5059                                gpio_pin, gpio_port, gpio_mode);
5060                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5061         }
5062         break;
5063         default:
5064                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5065                                fault_led_gpio);
5066         }
5067 }
5068
5069 static void bnx2x_power_sfp_module(struct link_params *params,
5070                                    struct bnx2x_phy *phy,
5071                                    u8 power)
5072 {
5073         struct bnx2x *bp = params->bp;
5074         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5075
5076         switch (phy->type) {
5077         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5078         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5079                 bnx2x_8727_power_module(params->bp, phy, power);
5080                 break;
5081         default:
5082                 break;
5083         }
5084 }
5085
5086 static void bnx2x_set_limiting_mode(struct link_params *params,
5087                                     struct bnx2x_phy *phy,
5088                                     u16 edc_mode)
5089 {
5090         switch (phy->type) {
5091         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5092                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5093                 break;
5094         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5095         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5096                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5097                 break;
5098         }
5099 }
5100
5101 static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5102                                      struct link_params *params)
5103 {
5104         struct bnx2x *bp = params->bp;
5105         u16 edc_mode;
5106         u8 rc = 0;
5107
5108         u32 val = REG_RD(bp, params->shmem_base +
5109                              offsetof(struct shmem_region, dev_info.
5110                                      port_feature_config[params->port].config));
5111
5112         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5113                  params->port);
5114         /* Power up module */
5115         bnx2x_power_sfp_module(params, phy, 1);
5116         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5117                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5118                 return -EINVAL;
5119         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5120                 /* check SFP+ module compatibility */
5121                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5122                 rc = -EINVAL;
5123                 /* Turn on fault module-detected led */
5124                 bnx2x_set_sfp_module_fault_led(params,
5125                                                MISC_REGISTERS_GPIO_HIGH);
5126
5127                 /* Check if need to power down the SFP+ module */
5128                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5129                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
5130                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5131                         bnx2x_power_sfp_module(params, phy, 0);
5132                         return rc;
5133                 }
5134         } else {
5135                 /* Turn off fault module-detected led */
5136                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5137         }
5138
5139         /*
5140          * Check and set limiting mode / LRM mode on 8726. On 8727 it
5141          * is done automatically
5142          */
5143         bnx2x_set_limiting_mode(params, phy, edc_mode);
5144
5145         /*
5146          * Enable transmit for this module if the module is approved, or
5147          * if unapproved modules should also enable the Tx laser
5148          */
5149         if (rc == 0 ||
5150             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5151             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5152                 bnx2x_sfp_set_transmitter(params, phy, 1);
5153         else
5154                 bnx2x_sfp_set_transmitter(params, phy, 0);
5155
5156         return rc;
5157 }
5158
5159 void bnx2x_handle_module_detect_int(struct link_params *params)
5160 {
5161         struct bnx2x *bp = params->bp;
5162         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5163         u32 gpio_val;
5164         u8 port = params->port;
5165
5166         /* Set valid module led off */
5167         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5168
5169         /* Get current gpio val reflecting module plugged in / out*/
5170         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5171
5172         /* Call the handling function in case module is detected */
5173         if (gpio_val == 0) {
5174                 bnx2x_power_sfp_module(params, phy, 1);
5175                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5176                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5177                                    port);
5178
5179                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5180                         bnx2x_sfp_module_detection(phy, params);
5181                 else
5182                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5183         } else {
5184                 u32 val = REG_RD(bp, params->shmem_base +
5185                                  offsetof(struct shmem_region, dev_info.
5186                                           port_feature_config[params->port].
5187                                           config));
5188
5189                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5190                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5191                                    port);
5192                 /*
5193                  * Module was plugged out.
5194                  * Disable transmit for this module
5195                  */
5196                 phy->media_type = ETH_PHY_NOT_PRESENT;
5197                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5198                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5199                         bnx2x_sfp_set_transmitter(params, phy, 0);
5200         }
5201 }
5202
5203 /******************************************************************/
5204 /*              common BCM8706/BCM8726 PHY SECTION                */
5205 /******************************************************************/
5206 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5207                                       struct link_params *params,
5208                                       struct link_vars *vars)
5209 {
5210         u8 link_up = 0;
5211         u16 val1, val2, rx_sd, pcs_status;
5212         struct bnx2x *bp = params->bp;
5213         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5214         /* Clear RX Alarm*/
5215         bnx2x_cl45_read(bp, phy,
5216                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5217         /* clear LASI indication*/
5218         bnx2x_cl45_read(bp, phy,
5219                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5220         bnx2x_cl45_read(bp, phy,
5221                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5222         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5223
5224         bnx2x_cl45_read(bp, phy,
5225                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5226         bnx2x_cl45_read(bp, phy,
5227                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5228         bnx2x_cl45_read(bp, phy,
5229                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5230         bnx2x_cl45_read(bp, phy,
5231                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5232
5233         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5234                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5235         /*
5236          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5237          * are set, or if the autoneg bit 1 is set
5238          */
5239         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5240         if (link_up) {
5241                 if (val2 & (1<<1))
5242                         vars->line_speed = SPEED_1000;
5243                 else
5244                         vars->line_speed = SPEED_10000;
5245                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5246                 vars->duplex = DUPLEX_FULL;
5247         }
5248         return link_up;
5249 }
5250
5251 /******************************************************************/
5252 /*                      BCM8706 PHY SECTION                       */
5253 /******************************************************************/
5254 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5255                                  struct link_params *params,
5256                                  struct link_vars *vars)
5257 {
5258         u32 tx_en_mode;
5259         u16 cnt, val, tmp1;
5260         struct bnx2x *bp = params->bp;
5261         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5262                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5263         /* HW reset */
5264         bnx2x_ext_phy_hw_reset(bp, params->port);
5265         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5266         bnx2x_wait_reset_complete(bp, phy, params);
5267
5268         /* Wait until fw is loaded */
5269         for (cnt = 0; cnt < 100; cnt++) {
5270                 bnx2x_cl45_read(bp, phy,
5271                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5272                 if (val)
5273                         break;
5274                 msleep(10);
5275         }
5276         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5277         if ((params->feature_config_flags &
5278              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5279                 u8 i;
5280                 u16 reg;
5281                 for (i = 0; i < 4; i++) {
5282                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5283                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5284                                    MDIO_XS_8706_REG_BANK_RX0);
5285                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5286                         /* Clear first 3 bits of the control */
5287                         val &= ~0x7;
5288                         /* Set control bits according to configuration */
5289                         val |= (phy->rx_preemphasis[i] & 0x7);
5290                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5291                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5292                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5293                 }
5294         }
5295         /* Force speed */
5296         if (phy->req_line_speed == SPEED_10000) {
5297                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5298
5299                 bnx2x_cl45_write(bp, phy,
5300                                  MDIO_PMA_DEVAD,
5301                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5302                 bnx2x_cl45_write(bp, phy,
5303                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5304         } else {
5305                 /* Force 1Gbps using autoneg with 1G advertisement */
5306
5307                 /* Allow CL37 through CL73 */
5308                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5309                 bnx2x_cl45_write(bp, phy,
5310                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5311
5312                 /* Enable Full-Duplex advertisement on CL37 */
5313                 bnx2x_cl45_write(bp, phy,
5314                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5315                 /* Enable CL37 AN */
5316                 bnx2x_cl45_write(bp, phy,
5317                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5318                 /* 1G support */
5319                 bnx2x_cl45_write(bp, phy,
5320                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5321
5322                 /* Enable clause 73 AN */
5323                 bnx2x_cl45_write(bp, phy,
5324                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5325                 bnx2x_cl45_write(bp, phy,
5326                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5327                                  0x0400);
5328                 bnx2x_cl45_write(bp, phy,
5329                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5330                                  0x0004);
5331         }
5332         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5333
5334         /*
5335          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5336          * power mode, if TX Laser is disabled
5337          */
5338
5339         tx_en_mode = REG_RD(bp, params->shmem_base +
5340                             offsetof(struct shmem_region,
5341                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5342                         & PORT_HW_CFG_TX_LASER_MASK;
5343
5344         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5345                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5346                 bnx2x_cl45_read(bp, phy,
5347                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5348                 tmp1 |= 0x1;
5349                 bnx2x_cl45_write(bp, phy,
5350                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5351         }
5352
5353         return 0;
5354 }
5355
5356 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5357                                  struct link_params *params,
5358                                  struct link_vars *vars)
5359 {
5360         return bnx2x_8706_8726_read_status(phy, params, vars);
5361 }
5362
5363 /******************************************************************/
5364 /*                      BCM8726 PHY SECTION                       */
5365 /******************************************************************/
5366 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5367                                        struct link_params *params)
5368 {
5369         struct bnx2x *bp = params->bp;
5370         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5371         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5372 }
5373
5374 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5375                                          struct link_params *params)
5376 {
5377         struct bnx2x *bp = params->bp;
5378         /* Need to wait 100ms after reset */
5379         msleep(100);
5380
5381         /* Micro controller re-boot */
5382         bnx2x_cl45_write(bp, phy,
5383                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5384
5385         /* Set soft reset */
5386         bnx2x_cl45_write(bp, phy,
5387                          MDIO_PMA_DEVAD,
5388                          MDIO_PMA_REG_GEN_CTRL,
5389                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5390
5391         bnx2x_cl45_write(bp, phy,
5392                          MDIO_PMA_DEVAD,
5393                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5394
5395         bnx2x_cl45_write(bp, phy,
5396                          MDIO_PMA_DEVAD,
5397                          MDIO_PMA_REG_GEN_CTRL,
5398                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5399
5400         /* wait for 150ms for microcode load */
5401         msleep(150);
5402
5403         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5404         bnx2x_cl45_write(bp, phy,
5405                          MDIO_PMA_DEVAD,
5406                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5407
5408         msleep(200);
5409         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5410 }
5411
5412 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5413                                  struct link_params *params,
5414                                  struct link_vars *vars)
5415 {
5416         struct bnx2x *bp = params->bp;
5417         u16 val1;
5418         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5419         if (link_up) {
5420                 bnx2x_cl45_read(bp, phy,
5421                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5422                                 &val1);
5423                 if (val1 & (1<<15)) {
5424                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5425                         link_up = 0;
5426                         vars->line_speed = 0;
5427                 }
5428         }
5429         return link_up;
5430 }
5431
5432
5433 static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5434                                  struct link_params *params,
5435                                  struct link_vars *vars)
5436 {
5437         struct bnx2x *bp = params->bp;
5438         u32 val;
5439         u32 swap_val, swap_override, aeu_gpio_mask, offset;
5440         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5441
5442         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5443         bnx2x_wait_reset_complete(bp, phy, params);
5444
5445         bnx2x_8726_external_rom_boot(phy, params);
5446
5447         /*
5448          * Need to call module detected on initialization since the module
5449          * detection triggered by actual module insertion might occur before
5450          * driver is loaded, and when driver is loaded, it reset all
5451          * registers, including the transmitter
5452          */
5453         bnx2x_sfp_module_detection(phy, params);
5454
5455         if (phy->req_line_speed == SPEED_1000) {
5456                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5457                 bnx2x_cl45_write(bp, phy,
5458                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5459                 bnx2x_cl45_write(bp, phy,
5460                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5461                 bnx2x_cl45_write(bp, phy,
5462                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5463                 bnx2x_cl45_write(bp, phy,
5464                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5465                                  0x400);
5466         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5467                    (phy->speed_cap_mask &
5468                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5469                    ((phy->speed_cap_mask &
5470                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5471                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5472                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5473                 /* Set Flow control */
5474                 bnx2x_ext_phy_set_pause(params, phy, vars);
5475                 bnx2x_cl45_write(bp, phy,
5476                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5477                 bnx2x_cl45_write(bp, phy,
5478                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5479                 bnx2x_cl45_write(bp, phy,
5480                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5481                 bnx2x_cl45_write(bp, phy,
5482                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5483                 bnx2x_cl45_write(bp, phy,
5484                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5485                 /*
5486                  * Enable RX-ALARM control to receive interrupt for 1G speed
5487                  * change
5488                  */
5489                 bnx2x_cl45_write(bp, phy,
5490                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5491                 bnx2x_cl45_write(bp, phy,
5492                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5493                                  0x400);
5494
5495         } else { /* Default 10G. Set only LASI control */
5496                 bnx2x_cl45_write(bp, phy,
5497                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5498         }
5499
5500         /* Set TX PreEmphasis if needed */
5501         if ((params->feature_config_flags &
5502              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5503                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5504                          "TX_CTRL2 0x%x\n",
5505                          phy->tx_preemphasis[0],
5506                          phy->tx_preemphasis[1]);
5507                 bnx2x_cl45_write(bp, phy,
5508                                  MDIO_PMA_DEVAD,
5509                                  MDIO_PMA_REG_8726_TX_CTRL1,
5510                                  phy->tx_preemphasis[0]);
5511
5512                 bnx2x_cl45_write(bp, phy,
5513                                  MDIO_PMA_DEVAD,
5514                                  MDIO_PMA_REG_8726_TX_CTRL2,
5515                                  phy->tx_preemphasis[1]);
5516         }
5517
5518         /* Set GPIO3 to trigger SFP+ module insertion/removal */
5519         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5520                        MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5521
5522         /* The GPIO should be swapped if the swap register is set and active */
5523         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5524         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5525
5526         /* Select function upon port-swap configuration */
5527         if (params->port == 0) {
5528                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5529                 aeu_gpio_mask = (swap_val && swap_override) ?
5530                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5531                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5532         } else {
5533                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5534                 aeu_gpio_mask = (swap_val && swap_override) ?
5535                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5536                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
5537         }
5538         val = REG_RD(bp, offset);
5539         /* add GPIO3 to group */
5540         val |= aeu_gpio_mask;
5541         REG_WR(bp, offset, val);
5542         return 0;
5543
5544 }
5545
5546 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5547                                   struct link_params *params)
5548 {
5549         struct bnx2x *bp = params->bp;
5550         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5551         /* Set serial boot control for external load */
5552         bnx2x_cl45_write(bp, phy,
5553                          MDIO_PMA_DEVAD,
5554                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
5555 }
5556
5557 /******************************************************************/
5558 /*                      BCM8727 PHY SECTION                       */
5559 /******************************************************************/
5560
5561 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5562                                     struct link_params *params, u8 mode)
5563 {
5564         struct bnx2x *bp = params->bp;
5565         u16 led_mode_bitmask = 0;
5566         u16 gpio_pins_bitmask = 0;
5567         u16 val;
5568         /* Only NOC flavor requires to set the LED specifically */
5569         if (!(phy->flags & FLAGS_NOC))
5570                 return;
5571         switch (mode) {
5572         case LED_MODE_FRONT_PANEL_OFF:
5573         case LED_MODE_OFF:
5574                 led_mode_bitmask = 0;
5575                 gpio_pins_bitmask = 0x03;
5576                 break;
5577         case LED_MODE_ON:
5578                 led_mode_bitmask = 0;
5579                 gpio_pins_bitmask = 0x02;
5580                 break;
5581         case LED_MODE_OPER:
5582                 led_mode_bitmask = 0x60;
5583                 gpio_pins_bitmask = 0x11;
5584                 break;
5585         }
5586         bnx2x_cl45_read(bp, phy,
5587                         MDIO_PMA_DEVAD,
5588                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5589                         &val);
5590         val &= 0xff8f;
5591         val |= led_mode_bitmask;
5592         bnx2x_cl45_write(bp, phy,
5593                          MDIO_PMA_DEVAD,
5594                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5595                          val);
5596         bnx2x_cl45_read(bp, phy,
5597                         MDIO_PMA_DEVAD,
5598                         MDIO_PMA_REG_8727_GPIO_CTRL,
5599                         &val);
5600         val &= 0xffe0;
5601         val |= gpio_pins_bitmask;
5602         bnx2x_cl45_write(bp, phy,
5603                          MDIO_PMA_DEVAD,
5604                          MDIO_PMA_REG_8727_GPIO_CTRL,
5605                          val);
5606 }
5607 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5608                                 struct link_params *params) {
5609         u32 swap_val, swap_override;
5610         u8 port;
5611         /*
5612          * The PHY reset is controlled by GPIO 1. Fake the port number
5613          * to cancel the swap done in set_gpio()
5614          */
5615         struct bnx2x *bp = params->bp;
5616         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5617         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5618         port = (swap_val && swap_override) ^ 1;
5619         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5620                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5621 }
5622
5623 static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5624                                  struct link_params *params,
5625                                  struct link_vars *vars)
5626 {
5627         u32 tx_en_mode;
5628         u16 tmp1, val, mod_abs, tmp2;
5629         u16 rx_alarm_ctrl_val;
5630         u16 lasi_ctrl_val;
5631         struct bnx2x *bp = params->bp;
5632         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5633
5634         bnx2x_wait_reset_complete(bp, phy, params);
5635         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5636         lasi_ctrl_val = 0x0004;
5637
5638         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5639         /* enable LASI */
5640         bnx2x_cl45_write(bp, phy,
5641                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5642                          rx_alarm_ctrl_val);
5643
5644         bnx2x_cl45_write(bp, phy,
5645                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5646
5647         /*
5648          * Initially configure MOD_ABS to interrupt when module is
5649          * presence( bit 8)
5650          */
5651         bnx2x_cl45_read(bp, phy,
5652                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5653         /*
5654          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5655          * When the EDC is off it locks onto a reference clock and avoids
5656          * becoming 'lost'
5657          */
5658         mod_abs &= ~(1<<8);
5659         if (!(phy->flags & FLAGS_NOC))
5660                 mod_abs &= ~(1<<9);
5661         bnx2x_cl45_write(bp, phy,
5662                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5663
5664
5665         /* Make MOD_ABS give interrupt on change */
5666         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5667                         &val);
5668         val |= (1<<12);
5669         if (phy->flags & FLAGS_NOC)
5670                 val |= (3<<5);
5671
5672         /*
5673          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5674          * status which reflect SFP+ module over-current
5675          */
5676         if (!(phy->flags & FLAGS_NOC))
5677                 val &= 0xff8f; /* Reset bits 4-6 */
5678         bnx2x_cl45_write(bp, phy,
5679                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5680
5681         bnx2x_8727_power_module(bp, phy, 1);
5682
5683         bnx2x_cl45_read(bp, phy,
5684                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5685
5686         bnx2x_cl45_read(bp, phy,
5687                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5688
5689         /* Set option 1G speed */
5690         if (phy->req_line_speed == SPEED_1000) {
5691                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5692                 bnx2x_cl45_write(bp, phy,
5693                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5694                 bnx2x_cl45_write(bp, phy,
5695                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5696                 bnx2x_cl45_read(bp, phy,
5697                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5698                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5699                 /*
5700                  * Power down the XAUI until link is up in case of dual-media
5701                  * and 1G
5702                  */
5703                 if (DUAL_MEDIA(params)) {
5704                         bnx2x_cl45_read(bp, phy,
5705                                         MDIO_PMA_DEVAD,
5706                                         MDIO_PMA_REG_8727_PCS_GP, &val);
5707                         val |= (3<<10);
5708                         bnx2x_cl45_write(bp, phy,
5709                                          MDIO_PMA_DEVAD,
5710                                          MDIO_PMA_REG_8727_PCS_GP, val);
5711                 }
5712         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5713                    ((phy->speed_cap_mask &
5714                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5715                    ((phy->speed_cap_mask &
5716                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5717                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5718
5719                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5720                 bnx2x_cl45_write(bp, phy,
5721                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5722                 bnx2x_cl45_write(bp, phy,
5723                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5724         } else {
5725                 /*
5726                  * Since the 8727 has only single reset pin, need to set the 10G
5727                  * registers although it is default
5728                  */
5729                 bnx2x_cl45_write(bp, phy,
5730                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5731                                  0x0020);
5732                 bnx2x_cl45_write(bp, phy,
5733                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5734                 bnx2x_cl45_write(bp, phy,
5735                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5736                 bnx2x_cl45_write(bp, phy,
5737                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5738                                  0x0008);
5739         }
5740
5741         /*
5742          * Set 2-wire transfer rate of SFP+ module EEPROM
5743          * to 100Khz since some DACs(direct attached cables) do
5744          * not work at 400Khz.
5745          */
5746         bnx2x_cl45_write(bp, phy,
5747                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5748                          0xa001);
5749
5750         /* Set TX PreEmphasis if needed */
5751         if ((params->feature_config_flags &
5752              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5753                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5754                            phy->tx_preemphasis[0],
5755                            phy->tx_preemphasis[1]);
5756                 bnx2x_cl45_write(bp, phy,
5757                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5758                                  phy->tx_preemphasis[0]);
5759
5760                 bnx2x_cl45_write(bp, phy,
5761                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5762                                  phy->tx_preemphasis[1]);
5763         }
5764
5765         /*
5766          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5767          * power mode, if TX Laser is disabled
5768          */
5769         tx_en_mode = REG_RD(bp, params->shmem_base +
5770                             offsetof(struct shmem_region,
5771                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5772                         & PORT_HW_CFG_TX_LASER_MASK;
5773
5774         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5775
5776                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5777                 bnx2x_cl45_read(bp, phy,
5778                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5779                 tmp2 |= 0x1000;
5780                 tmp2 &= 0xFFEF;
5781                 bnx2x_cl45_write(bp, phy,
5782                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5783         }
5784
5785         return 0;
5786 }
5787
5788 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5789                                       struct link_params *params)
5790 {
5791         struct bnx2x *bp = params->bp;
5792         u16 mod_abs, rx_alarm_status;
5793         u32 val = REG_RD(bp, params->shmem_base +
5794                              offsetof(struct shmem_region, dev_info.
5795                                       port_feature_config[params->port].
5796                                       config));
5797         bnx2x_cl45_read(bp, phy,
5798                         MDIO_PMA_DEVAD,
5799                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5800         if (mod_abs & (1<<8)) {
5801
5802                 /* Module is absent */
5803                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5804                             "show module is absent\n");
5805                 phy->media_type = ETH_PHY_NOT_PRESENT;
5806                 /*
5807                  * 1. Set mod_abs to detect next module
5808                  *    presence event
5809                  * 2. Set EDC off by setting OPTXLOS signal input to low
5810                  *    (bit 9).
5811                  *    When the EDC is off it locks onto a reference clock and
5812                  *    avoids becoming 'lost'.
5813                  */
5814                 mod_abs &= ~(1<<8);
5815                 if (!(phy->flags & FLAGS_NOC))
5816                         mod_abs &= ~(1<<9);
5817                 bnx2x_cl45_write(bp, phy,
5818                                  MDIO_PMA_DEVAD,
5819                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5820
5821                 /*
5822                  * Clear RX alarm since it stays up as long as
5823                  * the mod_abs wasn't changed
5824                  */
5825                 bnx2x_cl45_read(bp, phy,
5826                                 MDIO_PMA_DEVAD,
5827                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5828
5829         } else {
5830                 /* Module is present */
5831                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5832                             "show module is present\n");
5833                 /*
5834                  * First disable transmitter, and if the module is ok, the
5835                  * module_detection will enable it
5836                  * 1. Set mod_abs to detect next module absent event ( bit 8)
5837                  * 2. Restore the default polarity of the OPRXLOS signal and
5838                  * this signal will then correctly indicate the presence or
5839                  * absence of the Rx signal. (bit 9)
5840                  */
5841                 mod_abs |= (1<<8);
5842                 if (!(phy->flags & FLAGS_NOC))
5843                         mod_abs |= (1<<9);
5844                 bnx2x_cl45_write(bp, phy,
5845                                  MDIO_PMA_DEVAD,
5846                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5847
5848                 /*
5849                  * Clear RX alarm since it stays up as long as the mod_abs
5850                  * wasn't changed. This is need to be done before calling the
5851                  * module detection, otherwise it will clear* the link update
5852                  * alarm
5853                  */
5854                 bnx2x_cl45_read(bp, phy,
5855                                 MDIO_PMA_DEVAD,
5856                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5857
5858
5859                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5860                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5861                         bnx2x_sfp_set_transmitter(params, phy, 0);
5862
5863                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5864                         bnx2x_sfp_module_detection(phy, params);
5865                 else
5866                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5867         }
5868
5869         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5870                    rx_alarm_status);
5871         /* No need to check link status in case of module plugged in/out */
5872 }
5873
5874 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5875                                  struct link_params *params,
5876                                  struct link_vars *vars)
5877
5878 {
5879         struct bnx2x *bp = params->bp;
5880         u8 link_up = 0;
5881         u16 link_status = 0;
5882         u16 rx_alarm_status, lasi_ctrl, val1;
5883
5884         /* If PHY is not initialized, do not check link status */
5885         bnx2x_cl45_read(bp, phy,
5886                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5887                         &lasi_ctrl);
5888         if (!lasi_ctrl)
5889                 return 0;
5890
5891         /* Check the LASI */
5892         bnx2x_cl45_read(bp, phy,
5893                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5894                         &rx_alarm_status);
5895         vars->line_speed = 0;
5896         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
5897
5898         bnx2x_cl45_read(bp, phy,
5899                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5900
5901         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5902
5903         /* Clear MSG-OUT */
5904         bnx2x_cl45_read(bp, phy,
5905                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5906
5907         /*
5908          * If a module is present and there is need to check
5909          * for over current
5910          */
5911         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5912                 /* Check over-current using 8727 GPIO0 input*/
5913                 bnx2x_cl45_read(bp, phy,
5914                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5915                                 &val1);
5916
5917                 if ((val1 & (1<<8)) == 0) {
5918                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5919                                        " on port %d\n", params->port);
5920                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
5921                                             " been detected and the power to "
5922                                             "that SFP+ module has been removed"
5923                                             " to prevent failure of the card."
5924                                             " Please remove the SFP+ module and"
5925                                             " restart the system to clear this"
5926                                             " error.\n",
5927                          params->port);
5928                         /* Disable all RX_ALARMs except for mod_abs */
5929                         bnx2x_cl45_write(bp, phy,
5930                                          MDIO_PMA_DEVAD,
5931                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5932
5933                         bnx2x_cl45_read(bp, phy,
5934                                         MDIO_PMA_DEVAD,
5935                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5936                         /* Wait for module_absent_event */
5937                         val1 |= (1<<8);
5938                         bnx2x_cl45_write(bp, phy,
5939                                          MDIO_PMA_DEVAD,
5940                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5941                         /* Clear RX alarm */
5942                         bnx2x_cl45_read(bp, phy,
5943                                 MDIO_PMA_DEVAD,
5944                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5945                         return 0;
5946                 }
5947         } /* Over current check */
5948
5949         /* When module absent bit is set, check module */
5950         if (rx_alarm_status & (1<<5)) {
5951                 bnx2x_8727_handle_mod_abs(phy, params);
5952                 /* Enable all mod_abs and link detection bits */
5953                 bnx2x_cl45_write(bp, phy,
5954                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5955                                  ((1<<5) | (1<<2)));
5956         }
5957         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5958         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
5959         /* If transmitter is disabled, ignore false link up indication */
5960         bnx2x_cl45_read(bp, phy,
5961                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5962         if (val1 & (1<<15)) {
5963                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5964                 return 0;
5965         }
5966
5967         bnx2x_cl45_read(bp, phy,
5968                         MDIO_PMA_DEVAD,
5969                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5970
5971         /*
5972          * Bits 0..2 --> speed detected,
5973          * Bits 13..15--> link is down
5974          */
5975         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5976                 link_up = 1;
5977                 vars->line_speed = SPEED_10000;
5978                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
5979                            params->port);
5980         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5981                 link_up = 1;
5982                 vars->line_speed = SPEED_1000;
5983                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5984                            params->port);
5985         } else {
5986                 link_up = 0;
5987                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5988                            params->port);
5989         }
5990         if (link_up) {
5991                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5992                 vars->duplex = DUPLEX_FULL;
5993                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
5994         }
5995
5996         if ((DUAL_MEDIA(params)) &&
5997             (phy->req_line_speed == SPEED_1000)) {
5998                 bnx2x_cl45_read(bp, phy,
5999                                 MDIO_PMA_DEVAD,
6000                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
6001                 /*
6002                  * In case of dual-media board and 1G, power up the XAUI side,
6003                  * otherwise power it down. For 10G it is done automatically
6004                  */
6005                 if (link_up)
6006                         val1 &= ~(3<<10);
6007                 else
6008                         val1 |= (3<<10);
6009                 bnx2x_cl45_write(bp, phy,
6010                                  MDIO_PMA_DEVAD,
6011                                  MDIO_PMA_REG_8727_PCS_GP, val1);
6012         }
6013         return link_up;
6014 }
6015
6016 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
6017                                   struct link_params *params)
6018 {
6019         struct bnx2x *bp = params->bp;
6020         /* Disable Transmitter */
6021         bnx2x_sfp_set_transmitter(params, phy, 0);
6022         /* Clear LASI */
6023         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
6024
6025 }
6026
6027 /******************************************************************/
6028 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
6029 /******************************************************************/
6030 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
6031                                            struct link_params *params)
6032 {
6033         u16 val, fw_ver1, fw_ver2, cnt, adj;
6034         struct bnx2x *bp = params->bp;
6035
6036         adj = 0;
6037         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6038                 adj = -1;
6039
6040         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6041         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
6042         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0014);
6043         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6044         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, 0x0000);
6045         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, 0x0300);
6046         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x0009);
6047
6048         for (cnt = 0; cnt < 100; cnt++) {
6049                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
6050                 if (val & 1)
6051                         break;
6052                 udelay(5);
6053         }
6054         if (cnt == 100) {
6055                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6056                 bnx2x_save_spirom_version(bp, params->port, 0,
6057                                           phy->ver_addr);
6058                 return;
6059         }
6060
6061
6062         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
6063         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0000);
6064         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6065         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x000A);
6066         for (cnt = 0; cnt < 100; cnt++) {
6067                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
6068                 if (val & 1)
6069                         break;
6070                 udelay(5);
6071         }
6072         if (cnt == 100) {
6073                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6074                 bnx2x_save_spirom_version(bp, params->port, 0,
6075                                           phy->ver_addr);
6076                 return;
6077         }
6078
6079         /* lower 16 bits of the register SPI_FW_STATUS */
6080         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, &fw_ver1);
6081         /* upper 16 bits of register SPI_FW_STATUS */
6082         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, &fw_ver2);
6083
6084         bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
6085                                   phy->ver_addr);
6086 }
6087
6088 static void bnx2x_848xx_set_led(struct bnx2x *bp,
6089                                 struct bnx2x_phy *phy)
6090 {
6091         u16 val, adj;
6092
6093         adj = 0;
6094         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6095                 adj = -1;
6096
6097         /* PHYC_CTL_LED_CTL */
6098         bnx2x_cl45_read(bp, phy,
6099                         MDIO_PMA_DEVAD,
6100                         MDIO_PMA_REG_8481_LINK_SIGNAL + adj, &val);
6101         val &= 0xFE00;
6102         val |= 0x0092;
6103
6104         bnx2x_cl45_write(bp, phy,
6105                          MDIO_PMA_DEVAD,
6106                          MDIO_PMA_REG_8481_LINK_SIGNAL + adj, val);
6107
6108         bnx2x_cl45_write(bp, phy,
6109                          MDIO_PMA_DEVAD,
6110                          MDIO_PMA_REG_8481_LED1_MASK + adj,
6111                          0x80);
6112
6113         bnx2x_cl45_write(bp, phy,
6114                          MDIO_PMA_DEVAD,
6115                          MDIO_PMA_REG_8481_LED2_MASK + adj,
6116                          0x18);
6117
6118         /* Select activity source by Tx and Rx, as suggested by PHY AE */
6119         bnx2x_cl45_write(bp, phy,
6120                          MDIO_PMA_DEVAD,
6121                          MDIO_PMA_REG_8481_LED3_MASK + adj,
6122                          0x0006);
6123
6124         /* Select the closest activity blink rate to that in 10/100/1000 */
6125         bnx2x_cl45_write(bp, phy,
6126                         MDIO_PMA_DEVAD,
6127                         MDIO_PMA_REG_8481_LED3_BLINK + adj,
6128                         0);
6129
6130         bnx2x_cl45_read(bp, phy,
6131                         MDIO_PMA_DEVAD,
6132                         MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, &val);
6133         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6134
6135         bnx2x_cl45_write(bp, phy,
6136                          MDIO_PMA_DEVAD,
6137                          MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, val);
6138
6139         /* 'Interrupt Mask' */
6140         bnx2x_cl45_write(bp, phy,
6141                          MDIO_AN_DEVAD,
6142                          0xFFFB, 0xFFFD);
6143 }
6144
6145 static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
6146                                       struct link_params *params,
6147                                       struct link_vars *vars)
6148 {
6149         struct bnx2x *bp = params->bp;
6150         u16 autoneg_val, an_1000_val, an_10_100_val;
6151         /*
6152          * This phy uses the NIG latch mechanism since link indication
6153          * arrives through its LED4 and not via its LASI signal, so we
6154          * get steady signal instead of clear on read
6155          */
6156         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6157                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
6158
6159         bnx2x_cl45_write(bp, phy,
6160                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6161
6162         bnx2x_848xx_set_led(bp, phy);
6163
6164         /* set 1000 speed advertisement */
6165         bnx2x_cl45_read(bp, phy,
6166                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6167                         &an_1000_val);
6168
6169         bnx2x_ext_phy_set_pause(params, phy, vars);
6170         bnx2x_cl45_read(bp, phy,
6171                         MDIO_AN_DEVAD,
6172                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
6173                         &an_10_100_val);
6174         bnx2x_cl45_read(bp, phy,
6175                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6176                         &autoneg_val);
6177         /* Disable forced speed */
6178         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6179         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6180
6181         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6182              (phy->speed_cap_mask &
6183              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6184             (phy->req_line_speed == SPEED_1000)) {
6185                 an_1000_val |= (1<<8);
6186                 autoneg_val |= (1<<9 | 1<<12);
6187                 if (phy->req_duplex == DUPLEX_FULL)
6188                         an_1000_val |= (1<<9);
6189                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6190         } else
6191                 an_1000_val &= ~((1<<8) | (1<<9));
6192
6193         bnx2x_cl45_write(bp, phy,
6194                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6195                          an_1000_val);
6196
6197         /* set 10 speed advertisement */
6198         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6199              (phy->speed_cap_mask &
6200              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6201               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6202                 an_10_100_val |= (1<<7);
6203                 /* Enable autoneg and restart autoneg for legacy speeds */
6204                 autoneg_val |= (1<<9 | 1<<12);
6205
6206                 if (phy->req_duplex == DUPLEX_FULL)
6207                         an_10_100_val |= (1<<8);
6208                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6209         }
6210         /* set 10 speed advertisement */
6211         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6212             (phy->speed_cap_mask &
6213           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6214            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6215                 an_10_100_val |= (1<<5);
6216                 autoneg_val |= (1<<9 | 1<<12);
6217                 if (phy->req_duplex == DUPLEX_FULL)
6218                         an_10_100_val |= (1<<6);
6219                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6220         }
6221
6222         /* Only 10/100 are allowed to work in FORCE mode */
6223         if (phy->req_line_speed == SPEED_100) {
6224                 autoneg_val |= (1<<13);
6225                 /* Enabled AUTO-MDIX when autoneg is disabled */
6226                 bnx2x_cl45_write(bp, phy,
6227                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6228                                  (1<<15 | 1<<9 | 7<<0));
6229                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6230         }
6231         if (phy->req_line_speed == SPEED_10) {
6232                 /* Enabled AUTO-MDIX when autoneg is disabled */
6233                 bnx2x_cl45_write(bp, phy,
6234                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6235                                  (1<<15 | 1<<9 | 7<<0));
6236                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6237         }
6238
6239         bnx2x_cl45_write(bp, phy,
6240                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6241                          an_10_100_val);
6242
6243         if (phy->req_duplex == DUPLEX_FULL)
6244                 autoneg_val |= (1<<8);
6245
6246         bnx2x_cl45_write(bp, phy,
6247                          MDIO_AN_DEVAD,
6248                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6249
6250         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6251             (phy->speed_cap_mask &
6252              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6253                 (phy->req_line_speed == SPEED_10000)) {
6254                 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6255                 /* Restart autoneg for 10G*/
6256
6257                 bnx2x_cl45_write(bp, phy,
6258                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6259                                  0x3200);
6260         } else if (phy->req_line_speed != SPEED_10 &&
6261                    phy->req_line_speed != SPEED_100) {
6262                 bnx2x_cl45_write(bp, phy,
6263                                  MDIO_AN_DEVAD,
6264                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6265                                  1);
6266         }
6267         /* Save spirom version */
6268         bnx2x_save_848xx_spirom_version(phy, params);
6269
6270         return 0;
6271 }
6272
6273 static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6274                                  struct link_params *params,
6275                                  struct link_vars *vars)
6276 {
6277         struct bnx2x *bp = params->bp;
6278         /* Restore normal power mode*/
6279         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6280                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6281
6282         /* HW reset */
6283         bnx2x_ext_phy_hw_reset(bp, params->port);
6284         bnx2x_wait_reset_complete(bp, phy, params);
6285
6286         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6287         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6288 }
6289
6290 static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6291                                   struct link_params *params,
6292                                   struct link_vars *vars)
6293 {
6294         struct bnx2x *bp = params->bp;
6295         u8 port, initialize = 1;
6296         u16 val, adj;
6297         u16 temp;
6298         u32 actual_phy_selection, cms_enable;
6299         u8 rc = 0;
6300
6301         /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6302         adj = 0;
6303         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6304                 adj = 3;
6305
6306         msleep(1);
6307         if (CHIP_IS_E2(bp))
6308                 port = BP_PATH(bp);
6309         else
6310                 port = params->port;
6311         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6312                        MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6313                        port);
6314         bnx2x_wait_reset_complete(bp, phy, params);
6315         /* Wait for GPHY to come out of reset */
6316         msleep(50);
6317         /*
6318          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6319          */
6320         temp = vars->line_speed;
6321         vars->line_speed = SPEED_10000;
6322         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6323         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6324         vars->line_speed = temp;
6325
6326         /* Set dual-media configuration according to configuration */
6327
6328         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6329                         MDIO_CTL_REG_84823_MEDIA + adj, &val);
6330         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6331                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6332                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6333                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6334                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6335         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6336                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6337
6338         actual_phy_selection = bnx2x_phy_selection(params);
6339
6340         switch (actual_phy_selection) {
6341         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6342                 /* Do nothing. Essentially this is like the priority copper */
6343                 break;
6344         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6345                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6346                 break;
6347         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6348                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6349                 break;
6350         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6351                 /* Do nothing here. The first PHY won't be initialized at all */
6352                 break;
6353         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6354                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6355                 initialize = 0;
6356                 break;
6357         }
6358         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6359                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6360
6361         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6362                          MDIO_CTL_REG_84823_MEDIA + adj, val);
6363         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6364                    params->multi_phy_config, val);
6365
6366         if (initialize)
6367                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6368         else
6369                 bnx2x_save_848xx_spirom_version(phy, params);
6370         cms_enable = REG_RD(bp, params->shmem_base +
6371                         offsetof(struct shmem_region,
6372                         dev_info.port_hw_config[params->port].default_cfg)) &
6373                         PORT_HW_CFG_ENABLE_CMS_MASK;
6374
6375         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6376                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6377         if (cms_enable)
6378                 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6379         else
6380                 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6381         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6382                 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6383
6384
6385         return rc;
6386 }
6387
6388 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6389                                   struct link_params *params,
6390                                   struct link_vars *vars)
6391 {
6392         struct bnx2x *bp = params->bp;
6393         u16 val, val1, val2, adj;
6394         u8 link_up = 0;
6395
6396         /* Reg offset adjustment for 84833 */
6397         adj = 0;
6398         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6399                 adj = -1;
6400
6401         /* Check 10G-BaseT link status */
6402         /* Check PMD signal ok */
6403         bnx2x_cl45_read(bp, phy,
6404                         MDIO_AN_DEVAD, 0xFFFA, &val1);
6405         bnx2x_cl45_read(bp, phy,
6406                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL + adj,
6407                         &val2);
6408         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6409
6410         /* Check link 10G */
6411         if (val2 & (1<<11)) {
6412                 vars->line_speed = SPEED_10000;
6413                 vars->duplex = DUPLEX_FULL;
6414                 link_up = 1;
6415                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6416         } else { /* Check Legacy speed link */
6417                 u16 legacy_status, legacy_speed;
6418
6419                 /* Enable expansion register 0x42 (Operation mode status) */
6420                 bnx2x_cl45_write(bp, phy,
6421                                  MDIO_AN_DEVAD,
6422                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6423
6424                 /* Get legacy speed operation status */
6425                 bnx2x_cl45_read(bp, phy,
6426                                 MDIO_AN_DEVAD,
6427                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6428                                 &legacy_status);
6429
6430                 DP(NETIF_MSG_LINK, "Legacy speed status"
6431                              " = 0x%x\n", legacy_status);
6432                 link_up = ((legacy_status & (1<<11)) == (1<<11));
6433                 if (link_up) {
6434                         legacy_speed = (legacy_status & (3<<9));
6435                         if (legacy_speed == (0<<9))
6436                                 vars->line_speed = SPEED_10;
6437                         else if (legacy_speed == (1<<9))
6438                                 vars->line_speed = SPEED_100;
6439                         else if (legacy_speed == (2<<9))
6440                                 vars->line_speed = SPEED_1000;
6441                         else /* Should not happen */
6442                                 vars->line_speed = 0;
6443
6444                         if (legacy_status & (1<<8))
6445                                 vars->duplex = DUPLEX_FULL;
6446                         else
6447                                 vars->duplex = DUPLEX_HALF;
6448
6449                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6450                                    " is_duplex_full= %d\n", vars->line_speed,
6451                                    (vars->duplex == DUPLEX_FULL));
6452                         /* Check legacy speed AN resolution */
6453                         bnx2x_cl45_read(bp, phy,
6454                                         MDIO_AN_DEVAD,
6455                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6456                                         &val);
6457                         if (val & (1<<5))
6458                                 vars->link_status |=
6459                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6460                         bnx2x_cl45_read(bp, phy,
6461                                         MDIO_AN_DEVAD,
6462                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6463                                         &val);
6464                         if ((val & (1<<0)) == 0)
6465                                 vars->link_status |=
6466                                         LINK_STATUS_PARALLEL_DETECTION_USED;
6467                 }
6468         }
6469         if (link_up) {
6470                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6471                            vars->line_speed);
6472                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6473         }
6474
6475         return link_up;
6476 }
6477
6478 static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6479 {
6480         u8 status = 0;
6481         u32 spirom_ver;
6482         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6483         status = bnx2x_format_ver(spirom_ver, str, len);
6484         return status;
6485 }
6486
6487 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6488                                 struct link_params *params)
6489 {
6490         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6491                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6492         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6493                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6494 }
6495
6496 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6497                                         struct link_params *params)
6498 {
6499         bnx2x_cl45_write(params->bp, phy,
6500                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6501         bnx2x_cl45_write(params->bp, phy,
6502                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6503 }
6504
6505 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6506                                    struct link_params *params)
6507 {
6508         struct bnx2x *bp = params->bp;
6509         u8 port;
6510         if (CHIP_IS_E2(bp))
6511                 port = BP_PATH(bp);
6512         else
6513                 port = params->port;
6514         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6515                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6516                        port);
6517 }
6518
6519 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6520                                      struct link_params *params, u8 mode)
6521 {
6522         struct bnx2x *bp = params->bp;
6523         u16 val;
6524
6525         switch (mode) {
6526         case LED_MODE_OFF:
6527
6528                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6529
6530                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6531                     SHARED_HW_CFG_LED_EXTPHY1) {
6532
6533                         /* Set LED masks */
6534                         bnx2x_cl45_write(bp, phy,
6535                                         MDIO_PMA_DEVAD,
6536                                         MDIO_PMA_REG_8481_LED1_MASK,
6537                                         0x0);
6538
6539                         bnx2x_cl45_write(bp, phy,
6540                                         MDIO_PMA_DEVAD,
6541                                         MDIO_PMA_REG_8481_LED2_MASK,
6542                                         0x0);
6543
6544                         bnx2x_cl45_write(bp, phy,
6545                                         MDIO_PMA_DEVAD,
6546                                         MDIO_PMA_REG_8481_LED3_MASK,
6547                                         0x0);
6548
6549                         bnx2x_cl45_write(bp, phy,
6550                                         MDIO_PMA_DEVAD,
6551                                         MDIO_PMA_REG_8481_LED5_MASK,
6552                                         0x0);
6553
6554                 } else {
6555                         bnx2x_cl45_write(bp, phy,
6556                                          MDIO_PMA_DEVAD,
6557                                          MDIO_PMA_REG_8481_LED1_MASK,
6558                                          0x0);
6559                 }
6560                 break;
6561         case LED_MODE_FRONT_PANEL_OFF:
6562
6563                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6564                    params->port);
6565
6566                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6567                     SHARED_HW_CFG_LED_EXTPHY1) {
6568
6569                         /* Set LED masks */
6570                         bnx2x_cl45_write(bp, phy,
6571                                          MDIO_PMA_DEVAD,
6572                                          MDIO_PMA_REG_8481_LED1_MASK,
6573                                          0x0);
6574
6575                         bnx2x_cl45_write(bp, phy,
6576                                          MDIO_PMA_DEVAD,
6577                                          MDIO_PMA_REG_8481_LED2_MASK,
6578                                          0x0);
6579
6580                         bnx2x_cl45_write(bp, phy,
6581                                          MDIO_PMA_DEVAD,
6582                                          MDIO_PMA_REG_8481_LED3_MASK,
6583                                          0x0);
6584
6585                         bnx2x_cl45_write(bp, phy,
6586                                          MDIO_PMA_DEVAD,
6587                                          MDIO_PMA_REG_8481_LED5_MASK,
6588                                          0x20);
6589
6590                 } else {
6591                         bnx2x_cl45_write(bp, phy,
6592                                          MDIO_PMA_DEVAD,
6593                                          MDIO_PMA_REG_8481_LED1_MASK,
6594                                          0x0);
6595                 }
6596                 break;
6597         case LED_MODE_ON:
6598
6599                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6600
6601                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6602                     SHARED_HW_CFG_LED_EXTPHY1) {
6603                         /* Set control reg */
6604                         bnx2x_cl45_read(bp, phy,
6605                                         MDIO_PMA_DEVAD,
6606                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6607                                         &val);
6608                         val &= 0x8000;
6609                         val |= 0x2492;
6610
6611                         bnx2x_cl45_write(bp, phy,
6612                                          MDIO_PMA_DEVAD,
6613                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6614                                          val);
6615
6616                         /* Set LED masks */
6617                         bnx2x_cl45_write(bp, phy,
6618                                          MDIO_PMA_DEVAD,
6619                                          MDIO_PMA_REG_8481_LED1_MASK,
6620                                          0x0);
6621
6622                         bnx2x_cl45_write(bp, phy,
6623                                          MDIO_PMA_DEVAD,
6624                                          MDIO_PMA_REG_8481_LED2_MASK,
6625                                          0x20);
6626
6627                         bnx2x_cl45_write(bp, phy,
6628                                          MDIO_PMA_DEVAD,
6629                                          MDIO_PMA_REG_8481_LED3_MASK,
6630                                          0x20);
6631
6632                         bnx2x_cl45_write(bp, phy,
6633                                          MDIO_PMA_DEVAD,
6634                                          MDIO_PMA_REG_8481_LED5_MASK,
6635                                          0x0);
6636                 } else {
6637                         bnx2x_cl45_write(bp, phy,
6638                                          MDIO_PMA_DEVAD,
6639                                          MDIO_PMA_REG_8481_LED1_MASK,
6640                                          0x20);
6641                 }
6642                 break;
6643
6644         case LED_MODE_OPER:
6645
6646                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6647
6648                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6649                     SHARED_HW_CFG_LED_EXTPHY1) {
6650
6651                         /* Set control reg */
6652                         bnx2x_cl45_read(bp, phy,
6653                                         MDIO_PMA_DEVAD,
6654                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6655                                         &val);
6656
6657                         if (!((val &
6658                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6659                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
6660                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
6661                                 bnx2x_cl45_write(bp, phy,
6662                                                  MDIO_PMA_DEVAD,
6663                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
6664                                                  0xa492);
6665                         }
6666
6667                         /* Set LED masks */
6668                         bnx2x_cl45_write(bp, phy,
6669                                          MDIO_PMA_DEVAD,
6670                                          MDIO_PMA_REG_8481_LED1_MASK,
6671                                          0x10);
6672
6673                         bnx2x_cl45_write(bp, phy,
6674                                          MDIO_PMA_DEVAD,
6675                                          MDIO_PMA_REG_8481_LED2_MASK,
6676                                          0x80);
6677
6678                         bnx2x_cl45_write(bp, phy,
6679                                          MDIO_PMA_DEVAD,
6680                                          MDIO_PMA_REG_8481_LED3_MASK,
6681                                          0x98);
6682
6683                         bnx2x_cl45_write(bp, phy,
6684                                          MDIO_PMA_DEVAD,
6685                                          MDIO_PMA_REG_8481_LED5_MASK,
6686                                          0x40);
6687
6688                 } else {
6689                         bnx2x_cl45_write(bp, phy,
6690                                          MDIO_PMA_DEVAD,
6691                                          MDIO_PMA_REG_8481_LED1_MASK,
6692                                          0x80);
6693
6694                         /* Tell LED3 to blink on source */
6695                         bnx2x_cl45_read(bp, phy,
6696                                         MDIO_PMA_DEVAD,
6697                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6698                                         &val);
6699                         val &= ~(7<<6);
6700                         val |= (1<<6); /* A83B[8:6]= 1 */
6701                         bnx2x_cl45_write(bp, phy,
6702                                          MDIO_PMA_DEVAD,
6703                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6704                                          val);
6705                 }
6706                 break;
6707         }
6708 }
6709 /******************************************************************/
6710 /*                      SFX7101 PHY SECTION                       */
6711 /******************************************************************/
6712 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6713                                        struct link_params *params)
6714 {
6715         struct bnx2x *bp = params->bp;
6716         /* SFX7101_XGXS_TEST1 */
6717         bnx2x_cl45_write(bp, phy,
6718                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6719 }
6720
6721 static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6722                                  struct link_params *params,
6723                                  struct link_vars *vars)
6724 {
6725         u16 fw_ver1, fw_ver2, val;
6726         struct bnx2x *bp = params->bp;
6727         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6728
6729         /* Restore normal power mode*/
6730         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6731                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6732         /* HW reset */
6733         bnx2x_ext_phy_hw_reset(bp, params->port);
6734         bnx2x_wait_reset_complete(bp, phy, params);
6735
6736         bnx2x_cl45_write(bp, phy,
6737                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6738         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6739         bnx2x_cl45_write(bp, phy,
6740                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6741
6742         bnx2x_ext_phy_set_pause(params, phy, vars);
6743         /* Restart autoneg */
6744         bnx2x_cl45_read(bp, phy,
6745                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6746         val |= 0x200;
6747         bnx2x_cl45_write(bp, phy,
6748                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6749
6750         /* Save spirom version */
6751         bnx2x_cl45_read(bp, phy,
6752                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6753
6754         bnx2x_cl45_read(bp, phy,
6755                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6756         bnx2x_save_spirom_version(bp, params->port,
6757                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6758         return 0;
6759 }
6760
6761 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6762                                  struct link_params *params,
6763                                  struct link_vars *vars)
6764 {
6765         struct bnx2x *bp = params->bp;
6766         u8 link_up;
6767         u16 val1, val2;
6768         bnx2x_cl45_read(bp, phy,
6769                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6770         bnx2x_cl45_read(bp, phy,
6771                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6772         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6773                    val2, val1);
6774         bnx2x_cl45_read(bp, phy,
6775                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6776         bnx2x_cl45_read(bp, phy,
6777                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6778         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6779                    val2, val1);
6780         link_up = ((val1 & 4) == 4);
6781         /* if link is up print the AN outcome of the SFX7101 PHY */
6782         if (link_up) {
6783                 bnx2x_cl45_read(bp, phy,
6784                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6785                                 &val2);
6786                 vars->line_speed = SPEED_10000;
6787                 vars->duplex = DUPLEX_FULL;
6788                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6789                            val2, (val2 & (1<<14)));
6790                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6791                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6792         }
6793         return link_up;
6794 }
6795
6796
6797 static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6798 {
6799         if (*len < 5)
6800                 return -EINVAL;
6801         str[0] = (spirom_ver & 0xFF);
6802         str[1] = (spirom_ver & 0xFF00) >> 8;
6803         str[2] = (spirom_ver & 0xFF0000) >> 16;
6804         str[3] = (spirom_ver & 0xFF000000) >> 24;
6805         str[4] = '\0';
6806         *len -= 5;
6807         return 0;
6808 }
6809
6810 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6811 {
6812         u16 val, cnt;
6813
6814         bnx2x_cl45_read(bp, phy,
6815                         MDIO_PMA_DEVAD,
6816                         MDIO_PMA_REG_7101_RESET, &val);
6817
6818         for (cnt = 0; cnt < 10; cnt++) {
6819                 msleep(50);
6820                 /* Writes a self-clearing reset */
6821                 bnx2x_cl45_write(bp, phy,
6822                                  MDIO_PMA_DEVAD,
6823                                  MDIO_PMA_REG_7101_RESET,
6824                                  (val | (1<<15)));
6825                 /* Wait for clear */
6826                 bnx2x_cl45_read(bp, phy,
6827                                 MDIO_PMA_DEVAD,
6828                                 MDIO_PMA_REG_7101_RESET, &val);
6829
6830                 if ((val & (1<<15)) == 0)
6831                         break;
6832         }
6833 }
6834
6835 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6836                                 struct link_params *params) {
6837         /* Low power mode is controlled by GPIO 2 */
6838         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6839                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6840         /* The PHY reset is controlled by GPIO 1 */
6841         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6842                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6843 }
6844
6845 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6846                                     struct link_params *params, u8 mode)
6847 {
6848         u16 val = 0;
6849         struct bnx2x *bp = params->bp;
6850         switch (mode) {
6851         case LED_MODE_FRONT_PANEL_OFF:
6852         case LED_MODE_OFF:
6853                 val = 2;
6854                 break;
6855         case LED_MODE_ON:
6856                 val = 1;
6857                 break;
6858         case LED_MODE_OPER:
6859                 val = 0;
6860                 break;
6861         }
6862         bnx2x_cl45_write(bp, phy,
6863                          MDIO_PMA_DEVAD,
6864                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
6865                          val);
6866 }
6867
6868 /******************************************************************/
6869 /*                      STATIC PHY DECLARATION                    */
6870 /******************************************************************/
6871
6872 static struct bnx2x_phy phy_null = {
6873         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6874         .addr           = 0,
6875         .flags          = FLAGS_INIT_XGXS_FIRST,
6876         .def_md_devad   = 0,
6877         .reserved       = 0,
6878         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6879         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6880         .mdio_ctrl      = 0,
6881         .supported      = 0,
6882         .media_type     = ETH_PHY_NOT_PRESENT,
6883         .ver_addr       = 0,
6884         .req_flow_ctrl  = 0,
6885         .req_line_speed = 0,
6886         .speed_cap_mask = 0,
6887         .req_duplex     = 0,
6888         .rsrv           = 0,
6889         .config_init    = (config_init_t)NULL,
6890         .read_status    = (read_status_t)NULL,
6891         .link_reset     = (link_reset_t)NULL,
6892         .config_loopback = (config_loopback_t)NULL,
6893         .format_fw_ver  = (format_fw_ver_t)NULL,
6894         .hw_reset       = (hw_reset_t)NULL,
6895         .set_link_led   = (set_link_led_t)NULL,
6896         .phy_specific_func = (phy_specific_func_t)NULL
6897 };
6898
6899 static struct bnx2x_phy phy_serdes = {
6900         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6901         .addr           = 0xff,
6902         .flags          = 0,
6903         .def_md_devad   = 0,
6904         .reserved       = 0,
6905         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6906         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6907         .mdio_ctrl      = 0,
6908         .supported      = (SUPPORTED_10baseT_Half |
6909                            SUPPORTED_10baseT_Full |
6910                            SUPPORTED_100baseT_Half |
6911                            SUPPORTED_100baseT_Full |
6912                            SUPPORTED_1000baseT_Full |
6913                            SUPPORTED_2500baseX_Full |
6914                            SUPPORTED_TP |
6915                            SUPPORTED_Autoneg |
6916                            SUPPORTED_Pause |
6917                            SUPPORTED_Asym_Pause),
6918         .media_type     = ETH_PHY_BASE_T,
6919         .ver_addr       = 0,
6920         .req_flow_ctrl  = 0,
6921         .req_line_speed = 0,
6922         .speed_cap_mask = 0,
6923         .req_duplex     = 0,
6924         .rsrv           = 0,
6925         .config_init    = (config_init_t)bnx2x_init_serdes,
6926         .read_status    = (read_status_t)bnx2x_link_settings_status,
6927         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6928         .config_loopback = (config_loopback_t)NULL,
6929         .format_fw_ver  = (format_fw_ver_t)NULL,
6930         .hw_reset       = (hw_reset_t)NULL,
6931         .set_link_led   = (set_link_led_t)NULL,
6932         .phy_specific_func = (phy_specific_func_t)NULL
6933 };
6934
6935 static struct bnx2x_phy phy_xgxs = {
6936         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6937         .addr           = 0xff,
6938         .flags          = 0,
6939         .def_md_devad   = 0,
6940         .reserved       = 0,
6941         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6942         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6943         .mdio_ctrl      = 0,
6944         .supported      = (SUPPORTED_10baseT_Half |
6945                            SUPPORTED_10baseT_Full |
6946                            SUPPORTED_100baseT_Half |
6947                            SUPPORTED_100baseT_Full |
6948                            SUPPORTED_1000baseT_Full |
6949                            SUPPORTED_2500baseX_Full |
6950                            SUPPORTED_10000baseT_Full |
6951                            SUPPORTED_FIBRE |
6952                            SUPPORTED_Autoneg |
6953                            SUPPORTED_Pause |
6954                            SUPPORTED_Asym_Pause),
6955         .media_type     = ETH_PHY_CX4,
6956         .ver_addr       = 0,
6957         .req_flow_ctrl  = 0,
6958         .req_line_speed = 0,
6959         .speed_cap_mask = 0,
6960         .req_duplex     = 0,
6961         .rsrv           = 0,
6962         .config_init    = (config_init_t)bnx2x_init_xgxs,
6963         .read_status    = (read_status_t)bnx2x_link_settings_status,
6964         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6965         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6966         .format_fw_ver  = (format_fw_ver_t)NULL,
6967         .hw_reset       = (hw_reset_t)NULL,
6968         .set_link_led   = (set_link_led_t)NULL,
6969         .phy_specific_func = (phy_specific_func_t)NULL
6970 };
6971
6972 static struct bnx2x_phy phy_7101 = {
6973         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6974         .addr           = 0xff,
6975         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
6976         .def_md_devad   = 0,
6977         .reserved       = 0,
6978         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6979         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6980         .mdio_ctrl      = 0,
6981         .supported      = (SUPPORTED_10000baseT_Full |
6982                            SUPPORTED_TP |
6983                            SUPPORTED_Autoneg |
6984                            SUPPORTED_Pause |
6985                            SUPPORTED_Asym_Pause),
6986         .media_type     = ETH_PHY_BASE_T,
6987         .ver_addr       = 0,
6988         .req_flow_ctrl  = 0,
6989         .req_line_speed = 0,
6990         .speed_cap_mask = 0,
6991         .req_duplex     = 0,
6992         .rsrv           = 0,
6993         .config_init    = (config_init_t)bnx2x_7101_config_init,
6994         .read_status    = (read_status_t)bnx2x_7101_read_status,
6995         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6996         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6997         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
6998         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
6999         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
7000         .phy_specific_func = (phy_specific_func_t)NULL
7001 };
7002 static struct bnx2x_phy phy_8073 = {
7003         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
7004         .addr           = 0xff,
7005         .flags          = FLAGS_HW_LOCK_REQUIRED,
7006         .def_md_devad   = 0,
7007         .reserved       = 0,
7008         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7009         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7010         .mdio_ctrl      = 0,
7011         .supported      = (SUPPORTED_10000baseT_Full |
7012                            SUPPORTED_2500baseX_Full |
7013                            SUPPORTED_1000baseT_Full |
7014                            SUPPORTED_FIBRE |
7015                            SUPPORTED_Autoneg |
7016                            SUPPORTED_Pause |
7017                            SUPPORTED_Asym_Pause),
7018         .media_type     = ETH_PHY_KR,
7019         .ver_addr       = 0,
7020         .req_flow_ctrl  = 0,
7021         .req_line_speed = 0,
7022         .speed_cap_mask = 0,
7023         .req_duplex     = 0,
7024         .rsrv           = 0,
7025         .config_init    = (config_init_t)bnx2x_8073_config_init,
7026         .read_status    = (read_status_t)bnx2x_8073_read_status,
7027         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
7028         .config_loopback = (config_loopback_t)NULL,
7029         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7030         .hw_reset       = (hw_reset_t)NULL,
7031         .set_link_led   = (set_link_led_t)NULL,
7032         .phy_specific_func = (phy_specific_func_t)NULL
7033 };
7034 static struct bnx2x_phy phy_8705 = {
7035         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
7036         .addr           = 0xff,
7037         .flags          = FLAGS_INIT_XGXS_FIRST,
7038         .def_md_devad   = 0,
7039         .reserved       = 0,
7040         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7041         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7042         .mdio_ctrl      = 0,
7043         .supported      = (SUPPORTED_10000baseT_Full |
7044                            SUPPORTED_FIBRE |
7045                            SUPPORTED_Pause |
7046                            SUPPORTED_Asym_Pause),
7047         .media_type     = ETH_PHY_XFP_FIBER,
7048         .ver_addr       = 0,
7049         .req_flow_ctrl  = 0,
7050         .req_line_speed = 0,
7051         .speed_cap_mask = 0,
7052         .req_duplex     = 0,
7053         .rsrv           = 0,
7054         .config_init    = (config_init_t)bnx2x_8705_config_init,
7055         .read_status    = (read_status_t)bnx2x_8705_read_status,
7056         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7057         .config_loopback = (config_loopback_t)NULL,
7058         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
7059         .hw_reset       = (hw_reset_t)NULL,
7060         .set_link_led   = (set_link_led_t)NULL,
7061         .phy_specific_func = (phy_specific_func_t)NULL
7062 };
7063 static struct bnx2x_phy phy_8706 = {
7064         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7065         .addr           = 0xff,
7066         .flags          = FLAGS_INIT_XGXS_FIRST,
7067         .def_md_devad   = 0,
7068         .reserved       = 0,
7069         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7070         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7071         .mdio_ctrl      = 0,
7072         .supported      = (SUPPORTED_10000baseT_Full |
7073                            SUPPORTED_1000baseT_Full |
7074                            SUPPORTED_FIBRE |
7075                            SUPPORTED_Pause |
7076                            SUPPORTED_Asym_Pause),
7077         .media_type     = ETH_PHY_SFP_FIBER,
7078         .ver_addr       = 0,
7079         .req_flow_ctrl  = 0,
7080         .req_line_speed = 0,
7081         .speed_cap_mask = 0,
7082         .req_duplex     = 0,
7083         .rsrv           = 0,
7084         .config_init    = (config_init_t)bnx2x_8706_config_init,
7085         .read_status    = (read_status_t)bnx2x_8706_read_status,
7086         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7087         .config_loopback = (config_loopback_t)NULL,
7088         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7089         .hw_reset       = (hw_reset_t)NULL,
7090         .set_link_led   = (set_link_led_t)NULL,
7091         .phy_specific_func = (phy_specific_func_t)NULL
7092 };
7093
7094 static struct bnx2x_phy phy_8726 = {
7095         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7096         .addr           = 0xff,
7097         .flags          = (FLAGS_HW_LOCK_REQUIRED |
7098                            FLAGS_INIT_XGXS_FIRST),
7099         .def_md_devad   = 0,
7100         .reserved       = 0,
7101         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7102         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7103         .mdio_ctrl      = 0,
7104         .supported      = (SUPPORTED_10000baseT_Full |
7105                            SUPPORTED_1000baseT_Full |
7106                            SUPPORTED_Autoneg |
7107                            SUPPORTED_FIBRE |
7108                            SUPPORTED_Pause |
7109                            SUPPORTED_Asym_Pause),
7110         .media_type     = ETH_PHY_NOT_PRESENT,
7111         .ver_addr       = 0,
7112         .req_flow_ctrl  = 0,
7113         .req_line_speed = 0,
7114         .speed_cap_mask = 0,
7115         .req_duplex     = 0,
7116         .rsrv           = 0,
7117         .config_init    = (config_init_t)bnx2x_8726_config_init,
7118         .read_status    = (read_status_t)bnx2x_8726_read_status,
7119         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
7120         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7121         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7122         .hw_reset       = (hw_reset_t)NULL,
7123         .set_link_led   = (set_link_led_t)NULL,
7124         .phy_specific_func = (phy_specific_func_t)NULL
7125 };
7126
7127 static struct bnx2x_phy phy_8727 = {
7128         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7129         .addr           = 0xff,
7130         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7131         .def_md_devad   = 0,
7132         .reserved       = 0,
7133         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7134         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7135         .mdio_ctrl      = 0,
7136         .supported      = (SUPPORTED_10000baseT_Full |
7137                            SUPPORTED_1000baseT_Full |
7138                            SUPPORTED_FIBRE |
7139                            SUPPORTED_Pause |
7140                            SUPPORTED_Asym_Pause),
7141         .media_type     = ETH_PHY_NOT_PRESENT,
7142         .ver_addr       = 0,
7143         .req_flow_ctrl  = 0,
7144         .req_line_speed = 0,
7145         .speed_cap_mask = 0,
7146         .req_duplex     = 0,
7147         .rsrv           = 0,
7148         .config_init    = (config_init_t)bnx2x_8727_config_init,
7149         .read_status    = (read_status_t)bnx2x_8727_read_status,
7150         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
7151         .config_loopback = (config_loopback_t)NULL,
7152         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7153         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
7154         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
7155         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
7156 };
7157 static struct bnx2x_phy phy_8481 = {
7158         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7159         .addr           = 0xff,
7160         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7161                           FLAGS_REARM_LATCH_SIGNAL,
7162         .def_md_devad   = 0,
7163         .reserved       = 0,
7164         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7165         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7166         .mdio_ctrl      = 0,
7167         .supported      = (SUPPORTED_10baseT_Half |
7168                            SUPPORTED_10baseT_Full |
7169                            SUPPORTED_100baseT_Half |
7170                            SUPPORTED_100baseT_Full |
7171                            SUPPORTED_1000baseT_Full |
7172                            SUPPORTED_10000baseT_Full |
7173                            SUPPORTED_TP |
7174                            SUPPORTED_Autoneg |
7175                            SUPPORTED_Pause |
7176                            SUPPORTED_Asym_Pause),
7177         .media_type     = ETH_PHY_BASE_T,
7178         .ver_addr       = 0,
7179         .req_flow_ctrl  = 0,
7180         .req_line_speed = 0,
7181         .speed_cap_mask = 0,
7182         .req_duplex     = 0,
7183         .rsrv           = 0,
7184         .config_init    = (config_init_t)bnx2x_8481_config_init,
7185         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7186         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
7187         .config_loopback = (config_loopback_t)NULL,
7188         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7189         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
7190         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7191         .phy_specific_func = (phy_specific_func_t)NULL
7192 };
7193
7194 static struct bnx2x_phy phy_84823 = {
7195         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7196         .addr           = 0xff,
7197         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7198                           FLAGS_REARM_LATCH_SIGNAL,
7199         .def_md_devad   = 0,
7200         .reserved       = 0,
7201         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7202         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7203         .mdio_ctrl      = 0,
7204         .supported      = (SUPPORTED_10baseT_Half |
7205                            SUPPORTED_10baseT_Full |
7206                            SUPPORTED_100baseT_Half |
7207                            SUPPORTED_100baseT_Full |
7208                            SUPPORTED_1000baseT_Full |
7209                            SUPPORTED_10000baseT_Full |
7210                            SUPPORTED_TP |
7211                            SUPPORTED_Autoneg |
7212                            SUPPORTED_Pause |
7213                            SUPPORTED_Asym_Pause),
7214         .media_type     = ETH_PHY_BASE_T,
7215         .ver_addr       = 0,
7216         .req_flow_ctrl  = 0,
7217         .req_line_speed = 0,
7218         .speed_cap_mask = 0,
7219         .req_duplex     = 0,
7220         .rsrv           = 0,
7221         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7222         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7223         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7224         .config_loopback = (config_loopback_t)NULL,
7225         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7226         .hw_reset       = (hw_reset_t)NULL,
7227         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7228         .phy_specific_func = (phy_specific_func_t)NULL
7229 };
7230
7231 static struct bnx2x_phy phy_84833 = {
7232         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7233         .addr           = 0xff,
7234         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7235                             FLAGS_REARM_LATCH_SIGNAL,
7236         .def_md_devad   = 0,
7237         .reserved       = 0,
7238         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7239         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7240         .mdio_ctrl      = 0,
7241         .supported      = (SUPPORTED_10baseT_Half |
7242                            SUPPORTED_10baseT_Full |
7243                            SUPPORTED_100baseT_Half |
7244                            SUPPORTED_100baseT_Full |
7245                            SUPPORTED_1000baseT_Full |
7246                            SUPPORTED_10000baseT_Full |
7247                            SUPPORTED_TP |
7248                            SUPPORTED_Autoneg |
7249                            SUPPORTED_Pause |
7250                            SUPPORTED_Asym_Pause),
7251         .media_type     = ETH_PHY_BASE_T,
7252         .ver_addr       = 0,
7253         .req_flow_ctrl  = 0,
7254         .req_line_speed = 0,
7255         .speed_cap_mask = 0,
7256         .req_duplex     = 0,
7257         .rsrv           = 0,
7258         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7259         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7260         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7261         .config_loopback = (config_loopback_t)NULL,
7262         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7263         .hw_reset       = (hw_reset_t)NULL,
7264         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7265         .phy_specific_func = (phy_specific_func_t)NULL
7266 };
7267
7268 /*****************************************************************/
7269 /*                                                               */
7270 /* Populate the phy according. Main function: bnx2x_populate_phy   */
7271 /*                                                               */
7272 /*****************************************************************/
7273
7274 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7275                                      struct bnx2x_phy *phy, u8 port,
7276                                      u8 phy_index)
7277 {
7278         /* Get the 4 lanes xgxs config rx and tx */
7279         u32 rx = 0, tx = 0, i;
7280         for (i = 0; i < 2; i++) {
7281                 /*
7282                  * INT_PHY and EXT_PHY1 share the same value location in the
7283                  * shmem. When num_phys is greater than 1, than this value
7284                  * applies only to EXT_PHY1
7285                  */
7286                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7287                         rx = REG_RD(bp, shmem_base +
7288                                     offsetof(struct shmem_region,
7289                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7290
7291                         tx = REG_RD(bp, shmem_base +
7292                                     offsetof(struct shmem_region,
7293                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7294                 } else {
7295                         rx = REG_RD(bp, shmem_base +
7296                                     offsetof(struct shmem_region,
7297                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7298
7299                         tx = REG_RD(bp, shmem_base +
7300                                     offsetof(struct shmem_region,
7301                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7302                 }
7303
7304                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7305                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7306
7307                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7308                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7309         }
7310 }
7311
7312 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7313                                     u8 phy_index, u8 port)
7314 {
7315         u32 ext_phy_config = 0;
7316         switch (phy_index) {
7317         case EXT_PHY1:
7318                 ext_phy_config = REG_RD(bp, shmem_base +
7319                                               offsetof(struct shmem_region,
7320                         dev_info.port_hw_config[port].external_phy_config));
7321                 break;
7322         case EXT_PHY2:
7323                 ext_phy_config = REG_RD(bp, shmem_base +
7324                                               offsetof(struct shmem_region,
7325                         dev_info.port_hw_config[port].external_phy_config2));
7326                 break;
7327         default:
7328                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7329                 return -EINVAL;
7330         }
7331
7332         return ext_phy_config;
7333 }
7334 static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7335                                  struct bnx2x_phy *phy)
7336 {
7337         u32 phy_addr;
7338         u32 chip_id;
7339         u32 switch_cfg = (REG_RD(bp, shmem_base +
7340                                        offsetof(struct shmem_region,
7341                         dev_info.port_feature_config[port].link_config)) &
7342                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
7343         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7344         switch (switch_cfg) {
7345         case SWITCH_CFG_1G:
7346                 phy_addr = REG_RD(bp,
7347                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
7348                                         port * 0x10);
7349                 *phy = phy_serdes;
7350                 break;
7351         case SWITCH_CFG_10G:
7352                 phy_addr = REG_RD(bp,
7353                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
7354                                         port * 0x18);
7355                 *phy = phy_xgxs;
7356                 break;
7357         default:
7358                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7359                 return -EINVAL;
7360         }
7361         phy->addr = (u8)phy_addr;
7362         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7363                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7364                                             port);
7365         if (CHIP_IS_E2(bp))
7366                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7367         else
7368                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7369
7370         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7371                    port, phy->addr, phy->mdio_ctrl);
7372
7373         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7374         return 0;
7375 }
7376
7377 static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7378                                  u8 phy_index,
7379                                  u32 shmem_base,
7380                                  u32 shmem2_base,
7381                                  u8 port,
7382                                  struct bnx2x_phy *phy)
7383 {
7384         u32 ext_phy_config, phy_type, config2;
7385         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7386         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7387                                                   phy_index, port);
7388         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7389         /* Select the phy type */
7390         switch (phy_type) {
7391         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7392                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7393                 *phy = phy_8073;
7394                 break;
7395         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7396                 *phy = phy_8705;
7397                 break;
7398         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7399                 *phy = phy_8706;
7400                 break;
7401         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7402                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7403                 *phy = phy_8726;
7404                 break;
7405         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7406                 /* BCM8727_NOC => BCM8727 no over current */
7407                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7408                 *phy = phy_8727;
7409                 phy->flags |= FLAGS_NOC;
7410                 break;
7411         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7412         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7413                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7414                 *phy = phy_8727;
7415                 break;
7416         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7417                 *phy = phy_8481;
7418                 break;
7419         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7420                 *phy = phy_84823;
7421                 break;
7422         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7423                 *phy = phy_84833;
7424                 break;
7425         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7426                 *phy = phy_7101;
7427                 break;
7428         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7429                 *phy = phy_null;
7430                 return -EINVAL;
7431         default:
7432                 *phy = phy_null;
7433                 return 0;
7434         }
7435
7436         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7437         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7438
7439         /*
7440          * The shmem address of the phy version is located on different
7441          * structures. In case this structure is too old, do not set
7442          * the address
7443          */
7444         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7445                                         dev_info.shared_hw_config.config2));
7446         if (phy_index == EXT_PHY1) {
7447                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7448                                 port_mb[port].ext_phy_fw_version);
7449
7450                 /* Check specific mdc mdio settings */
7451                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7452                         mdc_mdio_access = config2 &
7453                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7454         } else {
7455                 u32 size = REG_RD(bp, shmem2_base);
7456
7457                 if (size >
7458                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7459                         phy->ver_addr = shmem2_base +
7460                             offsetof(struct shmem2_region,
7461                                      ext_phy_fw_version2[port]);
7462                 }
7463                 /* Check specific mdc mdio settings */
7464                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7465                         mdc_mdio_access = (config2 &
7466                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7467                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7468                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7469         }
7470         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7471
7472         /*
7473          * In case mdc/mdio_access of the external phy is different than the
7474          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7475          * to prevent one port interfere with another port's CL45 operations.
7476          */
7477         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7478                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7479         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7480                    phy_type, port, phy_index);
7481         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
7482                    phy->addr, phy->mdio_ctrl);
7483         return 0;
7484 }
7485
7486 static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7487                              u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7488 {
7489         u8 status = 0;
7490         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7491         if (phy_index == INT_PHY)
7492                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7493         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7494                                         port, phy);
7495         return status;
7496 }
7497
7498 static void bnx2x_phy_def_cfg(struct link_params *params,
7499                               struct bnx2x_phy *phy,
7500                               u8 phy_index)
7501 {
7502         struct bnx2x *bp = params->bp;
7503         u32 link_config;
7504         /* Populate the default phy configuration for MF mode */
7505         if (phy_index == EXT_PHY2) {
7506                 link_config = REG_RD(bp, params->shmem_base +
7507                                      offsetof(struct shmem_region, dev_info.
7508                         port_feature_config[params->port].link_config2));
7509                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7510                                              offsetof(struct shmem_region,
7511                                                       dev_info.
7512                         port_hw_config[params->port].speed_capability_mask2));
7513         } else {
7514                 link_config = REG_RD(bp, params->shmem_base +
7515                                      offsetof(struct shmem_region, dev_info.
7516                                 port_feature_config[params->port].link_config));
7517                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7518                                              offsetof(struct shmem_region,
7519                                                       dev_info.
7520                         port_hw_config[params->port].speed_capability_mask));
7521         }
7522         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7523                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7524
7525         phy->req_duplex = DUPLEX_FULL;
7526         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
7527         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7528                 phy->req_duplex = DUPLEX_HALF;
7529         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7530                 phy->req_line_speed = SPEED_10;
7531                 break;
7532         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7533                 phy->req_duplex = DUPLEX_HALF;
7534         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7535                 phy->req_line_speed = SPEED_100;
7536                 break;
7537         case PORT_FEATURE_LINK_SPEED_1G:
7538                 phy->req_line_speed = SPEED_1000;
7539                 break;
7540         case PORT_FEATURE_LINK_SPEED_2_5G:
7541                 phy->req_line_speed = SPEED_2500;
7542                 break;
7543         case PORT_FEATURE_LINK_SPEED_10G_CX4:
7544                 phy->req_line_speed = SPEED_10000;
7545                 break;
7546         default:
7547                 phy->req_line_speed = SPEED_AUTO_NEG;
7548                 break;
7549         }
7550
7551         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
7552         case PORT_FEATURE_FLOW_CONTROL_AUTO:
7553                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7554                 break;
7555         case PORT_FEATURE_FLOW_CONTROL_TX:
7556                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7557                 break;
7558         case PORT_FEATURE_FLOW_CONTROL_RX:
7559                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7560                 break;
7561         case PORT_FEATURE_FLOW_CONTROL_BOTH:
7562                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7563                 break;
7564         default:
7565                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7566                 break;
7567         }
7568 }
7569
7570 u32 bnx2x_phy_selection(struct link_params *params)
7571 {
7572         u32 phy_config_swapped, prio_cfg;
7573         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7574
7575         phy_config_swapped = params->multi_phy_config &
7576                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7577
7578         prio_cfg = params->multi_phy_config &
7579                         PORT_HW_CFG_PHY_SELECTION_MASK;
7580
7581         if (phy_config_swapped) {
7582                 switch (prio_cfg) {
7583                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7584                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7585                      break;
7586                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7587                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7588                      break;
7589                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7590                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7591                      break;
7592                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7593                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7594                      break;
7595                 }
7596         } else
7597                 return_cfg = prio_cfg;
7598
7599         return return_cfg;
7600 }
7601
7602
7603 u8 bnx2x_phy_probe(struct link_params *params)
7604 {
7605         u8 phy_index, actual_phy_idx, link_cfg_idx;
7606         u32 phy_config_swapped, sync_offset, media_types;
7607         struct bnx2x *bp = params->bp;
7608         struct bnx2x_phy *phy;
7609         params->num_phys = 0;
7610         DP(NETIF_MSG_LINK, "Begin phy probe\n");
7611         phy_config_swapped = params->multi_phy_config &
7612                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7613
7614         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7615               phy_index++) {
7616                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7617                 actual_phy_idx = phy_index;
7618                 if (phy_config_swapped) {
7619                         if (phy_index == EXT_PHY1)
7620                                 actual_phy_idx = EXT_PHY2;
7621                         else if (phy_index == EXT_PHY2)
7622                                 actual_phy_idx = EXT_PHY1;
7623                 }
7624                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7625                                " actual_phy_idx %x\n", phy_config_swapped,
7626                            phy_index, actual_phy_idx);
7627                 phy = &params->phy[actual_phy_idx];
7628                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7629                                        params->shmem2_base, params->port,
7630                                        phy) != 0) {
7631                         params->num_phys = 0;
7632                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7633                                    phy_index);
7634                         for (phy_index = INT_PHY;
7635                               phy_index < MAX_PHYS;
7636                               phy_index++)
7637                                 *phy = phy_null;
7638                         return -EINVAL;
7639                 }
7640                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7641                         break;
7642
7643                 sync_offset = params->shmem_base +
7644                         offsetof(struct shmem_region,
7645                         dev_info.port_hw_config[params->port].media_type);
7646                 media_types = REG_RD(bp, sync_offset);
7647
7648                 /*
7649                  * Update media type for non-PMF sync only for the first time
7650                  * In case the media type changes afterwards, it will be updated
7651                  * using the update_status function
7652                  */
7653                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7654                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7655                                      actual_phy_idx))) == 0) {
7656                         media_types |= ((phy->media_type &
7657                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7658                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7659                                  actual_phy_idx));
7660                 }
7661                 REG_WR(bp, sync_offset, media_types);
7662
7663                 bnx2x_phy_def_cfg(params, phy, phy_index);
7664                 params->num_phys++;
7665         }
7666
7667         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7668         return 0;
7669 }
7670
7671 static void set_phy_vars(struct link_params *params)
7672 {
7673         struct bnx2x *bp = params->bp;
7674         u8 actual_phy_idx, phy_index, link_cfg_idx;
7675         u8 phy_config_swapped = params->multi_phy_config &
7676                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7677         for (phy_index = INT_PHY; phy_index < params->num_phys;
7678               phy_index++) {
7679                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7680                 actual_phy_idx = phy_index;
7681                 if (phy_config_swapped) {
7682                         if (phy_index == EXT_PHY1)
7683                                 actual_phy_idx = EXT_PHY2;
7684                         else if (phy_index == EXT_PHY2)
7685                                 actual_phy_idx = EXT_PHY1;
7686                 }
7687                 params->phy[actual_phy_idx].req_flow_ctrl =
7688                         params->req_flow_ctrl[link_cfg_idx];
7689
7690                 params->phy[actual_phy_idx].req_line_speed =
7691                         params->req_line_speed[link_cfg_idx];
7692
7693                 params->phy[actual_phy_idx].speed_cap_mask =
7694                         params->speed_cap_mask[link_cfg_idx];
7695
7696                 params->phy[actual_phy_idx].req_duplex =
7697                         params->req_duplex[link_cfg_idx];
7698
7699                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7700                            " speed_cap_mask %x\n",
7701                            params->phy[actual_phy_idx].req_flow_ctrl,
7702                            params->phy[actual_phy_idx].req_line_speed,
7703                            params->phy[actual_phy_idx].speed_cap_mask);
7704         }
7705 }
7706
7707 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7708 {
7709         struct bnx2x *bp = params->bp;
7710         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7711         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7712                    params->req_line_speed[0], params->req_flow_ctrl[0]);
7713         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7714                    params->req_line_speed[1], params->req_flow_ctrl[1]);
7715         vars->link_status = 0;
7716         vars->phy_link_up = 0;
7717         vars->link_up = 0;
7718         vars->line_speed = 0;
7719         vars->duplex = DUPLEX_FULL;
7720         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7721         vars->mac_type = MAC_TYPE_NONE;
7722         vars->phy_flags = 0;
7723
7724         /* disable attentions */
7725         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7726                        (NIG_MASK_XGXS0_LINK_STATUS |
7727                         NIG_MASK_XGXS0_LINK10G |
7728                         NIG_MASK_SERDES0_LINK_STATUS |
7729                         NIG_MASK_MI_INT));
7730
7731         bnx2x_emac_init(params, vars);
7732
7733         if (params->num_phys == 0) {
7734                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7735                 return -EINVAL;
7736         }
7737         set_phy_vars(params);
7738
7739         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7740         if (params->loopback_mode == LOOPBACK_BMAC) {
7741
7742                 vars->link_up = 1;
7743                 vars->line_speed = SPEED_10000;
7744                 vars->duplex = DUPLEX_FULL;
7745                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7746                 vars->mac_type = MAC_TYPE_BMAC;
7747
7748                 vars->phy_flags = PHY_XGXS_FLAG;
7749
7750                 bnx2x_xgxs_deassert(params);
7751
7752                 /* set bmac loopback */
7753                 bnx2x_bmac_enable(params, vars, 1);
7754
7755                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7756
7757         } else if (params->loopback_mode == LOOPBACK_EMAC) {
7758
7759                 vars->link_up = 1;
7760                 vars->line_speed = SPEED_1000;
7761                 vars->duplex = DUPLEX_FULL;
7762                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7763                 vars->mac_type = MAC_TYPE_EMAC;
7764
7765                 vars->phy_flags = PHY_XGXS_FLAG;
7766
7767                 bnx2x_xgxs_deassert(params);
7768                 /* set bmac loopback */
7769                 bnx2x_emac_enable(params, vars, 1);
7770                 bnx2x_emac_program(params, vars);
7771                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7772
7773         } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7774                    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
7775
7776                 vars->link_up = 1;
7777                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7778                 vars->duplex = DUPLEX_FULL;
7779                 if (params->req_line_speed[0] == SPEED_1000) {
7780                         vars->line_speed = SPEED_1000;
7781                         vars->mac_type = MAC_TYPE_EMAC;
7782                 } else {
7783                         vars->line_speed = SPEED_10000;
7784                         vars->mac_type = MAC_TYPE_BMAC;
7785                 }
7786
7787                 bnx2x_xgxs_deassert(params);
7788                 bnx2x_link_initialize(params, vars);
7789
7790                 if (params->req_line_speed[0] == SPEED_1000) {
7791                         bnx2x_emac_program(params, vars);
7792                         bnx2x_emac_enable(params, vars, 0);
7793                 } else
7794                         bnx2x_bmac_enable(params, vars, 0);
7795                 if (params->loopback_mode == LOOPBACK_XGXS) {
7796                         /* set 10G XGXS loopback */
7797                         params->phy[INT_PHY].config_loopback(
7798                                 &params->phy[INT_PHY],
7799                                 params);
7800
7801                 } else {
7802                         /* set external phy loopback */
7803                         u8 phy_index;
7804                         for (phy_index = EXT_PHY1;
7805                               phy_index < params->num_phys; phy_index++) {
7806                                 if (params->phy[phy_index].config_loopback)
7807                                         params->phy[phy_index].config_loopback(
7808                                                 &params->phy[phy_index],
7809                                                 params);
7810                         }
7811                 }
7812                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7813
7814                 bnx2x_set_led(params, vars,
7815                               LED_MODE_OPER, vars->line_speed);
7816         } else
7817         /* No loopback */
7818         {
7819                 if (params->switch_cfg == SWITCH_CFG_10G)
7820                         bnx2x_xgxs_deassert(params);
7821                 else
7822                         bnx2x_serdes_deassert(bp, params->port);
7823
7824                 bnx2x_link_initialize(params, vars);
7825                 msleep(30);
7826                 bnx2x_link_int_enable(params);
7827         }
7828         return 0;
7829 }
7830 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7831                     u8 reset_ext_phy)
7832 {
7833         struct bnx2x *bp = params->bp;
7834         u8 phy_index, port = params->port, clear_latch_ind = 0;
7835         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7836         /* disable attentions */
7837         vars->link_status = 0;
7838         bnx2x_update_mng(params, vars->link_status);
7839         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7840                        (NIG_MASK_XGXS0_LINK_STATUS |
7841                         NIG_MASK_XGXS0_LINK10G |
7842                         NIG_MASK_SERDES0_LINK_STATUS |
7843                         NIG_MASK_MI_INT));
7844
7845         /* activate nig drain */
7846         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7847
7848         /* disable nig egress interface */
7849         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7850         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7851
7852         /* Stop BigMac rx */
7853         bnx2x_bmac_rx_disable(bp, port);
7854
7855         /* disable emac */
7856         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7857
7858         msleep(10);
7859         /* The PHY reset is controlled by GPIO 1
7860          * Hold it as vars low
7861          */
7862          /* clear link led */
7863         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7864
7865         if (reset_ext_phy) {
7866                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7867                       phy_index++) {
7868                         if (params->phy[phy_index].link_reset)
7869                                 params->phy[phy_index].link_reset(
7870                                         &params->phy[phy_index],
7871                                         params);
7872                         if (params->phy[phy_index].flags &
7873                             FLAGS_REARM_LATCH_SIGNAL)
7874                                 clear_latch_ind = 1;
7875                 }
7876         }
7877
7878         if (clear_latch_ind) {
7879                 /* Clear latching indication */
7880                 bnx2x_rearm_latch_signal(bp, port, 0);
7881                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7882                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
7883         }
7884         if (params->phy[INT_PHY].link_reset)
7885                 params->phy[INT_PHY].link_reset(
7886                         &params->phy[INT_PHY], params);
7887         /* reset BigMac */
7888         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7889                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7890
7891         /* disable nig ingress interface */
7892         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7893         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7894         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7895         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7896         vars->link_up = 0;
7897         return 0;
7898 }
7899
7900 /****************************************************************************/
7901 /*                              Common function                             */
7902 /****************************************************************************/
7903 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7904                                      u32 shmem_base_path[],
7905                                      u32 shmem2_base_path[], u8 phy_index,
7906                                      u32 chip_id)
7907 {
7908         struct bnx2x_phy phy[PORT_MAX];
7909         struct bnx2x_phy *phy_blk[PORT_MAX];
7910         u16 val;
7911         s8 port = 0;
7912         s8 port_of_path = 0;
7913         u32 swap_val, swap_override;
7914         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
7915         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
7916         port ^= (swap_val && swap_override);
7917         bnx2x_ext_phy_hw_reset(bp, port);
7918         /* PART1 - Reset both phys */
7919         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7920                 u32 shmem_base, shmem2_base;
7921                 /* In E2, same phy is using for port0 of the two paths */
7922                 if (CHIP_IS_E2(bp)) {
7923                         shmem_base = shmem_base_path[port];
7924                         shmem2_base = shmem2_base_path[port];
7925                         port_of_path = 0;
7926                 } else {
7927                         shmem_base = shmem_base_path[0];
7928                         shmem2_base = shmem2_base_path[0];
7929                         port_of_path = port;
7930                 }
7931
7932                 /* Extract the ext phy address for the port */
7933                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7934                                        port_of_path, &phy[port]) !=
7935                     0) {
7936                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
7937                         return -EINVAL;
7938                 }
7939                 /* disable attentions */
7940                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7941                                port_of_path*4,
7942                                (NIG_MASK_XGXS0_LINK_STATUS |
7943                                 NIG_MASK_XGXS0_LINK10G |
7944                                 NIG_MASK_SERDES0_LINK_STATUS |
7945                                 NIG_MASK_MI_INT));
7946
7947                 /* Need to take the phy out of low power mode in order
7948                         to write to access its registers */
7949                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7950                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7951                                port);
7952
7953                 /* Reset the phy */
7954                 bnx2x_cl45_write(bp, &phy[port],
7955                                  MDIO_PMA_DEVAD,
7956                                  MDIO_PMA_REG_CTRL,
7957                                  1<<15);
7958         }
7959
7960         /* Add delay of 150ms after reset */
7961         msleep(150);
7962
7963         if (phy[PORT_0].addr & 0x1) {
7964                 phy_blk[PORT_0] = &(phy[PORT_1]);
7965                 phy_blk[PORT_1] = &(phy[PORT_0]);
7966         } else {
7967                 phy_blk[PORT_0] = &(phy[PORT_0]);
7968                 phy_blk[PORT_1] = &(phy[PORT_1]);
7969         }
7970
7971         /* PART2 - Download firmware to both phys */
7972         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7973                 if (CHIP_IS_E2(bp))
7974                         port_of_path = 0;
7975                 else
7976                         port_of_path = port;
7977
7978                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7979                            phy_blk[port]->addr);
7980                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7981                                                       port_of_path))
7982                         return -EINVAL;
7983
7984                 /* Only set bit 10 = 1 (Tx power down) */
7985                 bnx2x_cl45_read(bp, phy_blk[port],
7986                                 MDIO_PMA_DEVAD,
7987                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
7988
7989                 /* Phase1 of TX_POWER_DOWN reset */
7990                 bnx2x_cl45_write(bp, phy_blk[port],
7991                                  MDIO_PMA_DEVAD,
7992                                  MDIO_PMA_REG_TX_POWER_DOWN,
7993                                  (val | 1<<10));
7994         }
7995
7996         /*
7997          * Toggle Transmitter: Power down and then up with 600ms delay
7998          * between
7999          */
8000         msleep(600);
8001
8002         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
8003         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8004                 /* Phase2 of POWER_DOWN_RESET */
8005                 /* Release bit 10 (Release Tx power down) */
8006                 bnx2x_cl45_read(bp, phy_blk[port],
8007                                 MDIO_PMA_DEVAD,
8008                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8009
8010                 bnx2x_cl45_write(bp, phy_blk[port],
8011                                 MDIO_PMA_DEVAD,
8012                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
8013                 msleep(15);
8014
8015                 /* Read modify write the SPI-ROM version select register */
8016                 bnx2x_cl45_read(bp, phy_blk[port],
8017                                 MDIO_PMA_DEVAD,
8018                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
8019                 bnx2x_cl45_write(bp, phy_blk[port],
8020                                  MDIO_PMA_DEVAD,
8021                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
8022
8023                 /* set GPIO2 back to LOW */
8024                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8025                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8026         }
8027         return 0;
8028 }
8029 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
8030                                      u32 shmem_base_path[],
8031                                      u32 shmem2_base_path[], u8 phy_index,
8032                                      u32 chip_id)
8033 {
8034         u32 val;
8035         s8 port;
8036         struct bnx2x_phy phy;
8037         /* Use port1 because of the static port-swap */
8038         /* Enable the module detection interrupt */
8039         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8040         val |= ((1<<MISC_REGISTERS_GPIO_3)|
8041                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
8042         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8043
8044         bnx2x_ext_phy_hw_reset(bp, 0);
8045         msleep(5);
8046         for (port = 0; port < PORT_MAX; port++) {
8047                 u32 shmem_base, shmem2_base;
8048
8049                 /* In E2, same phy is using for port0 of the two paths */
8050                 if (CHIP_IS_E2(bp)) {
8051                         shmem_base = shmem_base_path[port];
8052                         shmem2_base = shmem2_base_path[port];
8053                 } else {
8054                         shmem_base = shmem_base_path[0];
8055                         shmem2_base = shmem2_base_path[0];
8056                 }
8057                 /* Extract the ext phy address for the port */
8058                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8059                                        port, &phy) !=
8060                     0) {
8061                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8062                         return -EINVAL;
8063                 }
8064
8065                 /* Reset phy*/
8066                 bnx2x_cl45_write(bp, &phy,
8067                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8068
8069
8070                 /* Set fault module detected LED on */
8071                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8072                                MISC_REGISTERS_GPIO_HIGH,
8073                                port);
8074         }
8075
8076         return 0;
8077 }
8078 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8079                                          u8 *io_gpio, u8 *io_port)
8080 {
8081
8082         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8083                                           offsetof(struct shmem_region,
8084                                 dev_info.port_hw_config[PORT_0].default_cfg));
8085         switch (phy_gpio_reset) {
8086         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8087                 *io_gpio = 0;
8088                 *io_port = 0;
8089                 break;
8090         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8091                 *io_gpio = 1;
8092                 *io_port = 0;
8093                 break;
8094         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8095                 *io_gpio = 2;
8096                 *io_port = 0;
8097                 break;
8098         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8099                 *io_gpio = 3;
8100                 *io_port = 0;
8101                 break;
8102         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8103                 *io_gpio = 0;
8104                 *io_port = 1;
8105                 break;
8106         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8107                 *io_gpio = 1;
8108                 *io_port = 1;
8109                 break;
8110         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8111                 *io_gpio = 2;
8112                 *io_port = 1;
8113                 break;
8114         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8115                 *io_gpio = 3;
8116                 *io_port = 1;
8117                 break;
8118         default:
8119                 /* Don't override the io_gpio and io_port */
8120                 break;
8121         }
8122 }
8123 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
8124                                      u32 shmem_base_path[],
8125                                      u32 shmem2_base_path[], u8 phy_index,
8126                                      u32 chip_id)
8127 {
8128         s8 port, reset_gpio;
8129         u32 swap_val, swap_override;
8130         struct bnx2x_phy phy[PORT_MAX];
8131         struct bnx2x_phy *phy_blk[PORT_MAX];
8132         s8 port_of_path;
8133         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8134         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8135
8136         reset_gpio = MISC_REGISTERS_GPIO_1;
8137         port = 1;
8138
8139         /*
8140          * Retrieve the reset gpio/port which control the reset.
8141          * Default is GPIO1, PORT1
8142          */
8143         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8144                                      (u8 *)&reset_gpio, (u8 *)&port);
8145
8146         /* Calculate the port based on port swap */
8147         port ^= (swap_val && swap_override);
8148
8149         /* Initiate PHY reset*/
8150         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8151                        port);
8152         msleep(1);
8153         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8154                        port);
8155
8156         msleep(5);
8157
8158         /* PART1 - Reset both phys */
8159         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8160                 u32 shmem_base, shmem2_base;
8161
8162                 /* In E2, same phy is using for port0 of the two paths */
8163                 if (CHIP_IS_E2(bp)) {
8164                         shmem_base = shmem_base_path[port];
8165                         shmem2_base = shmem2_base_path[port];
8166                         port_of_path = 0;
8167                 } else {
8168                         shmem_base = shmem_base_path[0];
8169                         shmem2_base = shmem2_base_path[0];
8170                         port_of_path = port;
8171                 }
8172
8173                 /* Extract the ext phy address for the port */
8174                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8175                                        port_of_path, &phy[port]) !=
8176                                        0) {
8177                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8178                         return -EINVAL;
8179                 }
8180                 /* disable attentions */
8181                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8182                                port_of_path*4,
8183                                (NIG_MASK_XGXS0_LINK_STATUS |
8184                                 NIG_MASK_XGXS0_LINK10G |
8185                                 NIG_MASK_SERDES0_LINK_STATUS |
8186                                 NIG_MASK_MI_INT));
8187
8188
8189                 /* Reset the phy */
8190                 bnx2x_cl45_write(bp, &phy[port],
8191                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8192         }
8193
8194         /* Add delay of 150ms after reset */
8195         msleep(150);
8196         if (phy[PORT_0].addr & 0x1) {
8197                 phy_blk[PORT_0] = &(phy[PORT_1]);
8198                 phy_blk[PORT_1] = &(phy[PORT_0]);
8199         } else {
8200                 phy_blk[PORT_0] = &(phy[PORT_0]);
8201                 phy_blk[PORT_1] = &(phy[PORT_1]);
8202         }
8203         /* PART2 - Download firmware to both phys */
8204         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8205                 if (CHIP_IS_E2(bp))
8206                         port_of_path = 0;
8207                 else
8208                         port_of_path = port;
8209                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8210                            phy_blk[port]->addr);
8211                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8212                                                       port_of_path))
8213                         return -EINVAL;
8214
8215         }
8216         return 0;
8217 }
8218
8219 static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8220                                     u32 shmem2_base_path[], u8 phy_index,
8221                                     u32 ext_phy_type, u32 chip_id)
8222 {
8223         u8 rc = 0;
8224
8225         switch (ext_phy_type) {
8226         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8227                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8228                                                 shmem2_base_path,
8229                                                 phy_index, chip_id);
8230                 break;
8231         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8232         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8233         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
8234                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8235                                                 shmem2_base_path,
8236                                                 phy_index, chip_id);
8237                 break;
8238
8239         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8240                 /*
8241                  * GPIO1 affects both ports, so there's need to pull
8242                  * it for single port alone
8243                  */
8244                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8245                                                 shmem2_base_path,
8246                                                 phy_index, chip_id);
8247                 break;
8248         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8249                 rc = -EINVAL;
8250                 break;
8251         default:
8252                 DP(NETIF_MSG_LINK,
8253                            "ext_phy 0x%x common init not required\n",
8254                            ext_phy_type);
8255                 break;
8256         }
8257
8258         if (rc != 0)
8259                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
8260                                       " Port %d\n",
8261                          0);
8262         return rc;
8263 }
8264
8265 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8266                          u32 shmem2_base_path[], u32 chip_id)
8267 {
8268         u8 rc = 0;
8269         u32 phy_ver;
8270         u8 phy_index;
8271         u32 ext_phy_type, ext_phy_config;
8272         DP(NETIF_MSG_LINK, "Begin common phy init\n");
8273
8274         /* Check if common init was already done */
8275         phy_ver = REG_RD(bp, shmem_base_path[0] +
8276                          offsetof(struct shmem_region,
8277                                   port_mb[PORT_0].ext_phy_fw_version));
8278         if (phy_ver) {
8279                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8280                                phy_ver);
8281                 return 0;
8282         }
8283
8284         /* Read the ext_phy_type for arbitrary port(0) */
8285         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8286               phy_index++) {
8287                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
8288                                                           shmem_base_path[0],
8289                                                           phy_index, 0);
8290                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8291                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8292                                                 shmem2_base_path,
8293                                                 phy_index, ext_phy_type,
8294                                                 chip_id);
8295         }
8296         return rc;
8297 }
8298
8299 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
8300 {
8301         u8 phy_index;
8302         struct bnx2x_phy phy;
8303         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8304               phy_index++) {
8305                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8306                                        0, &phy) != 0) {
8307                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8308                         return 0;
8309                 }
8310
8311                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8312                         return 1;
8313         }
8314         return 0;
8315 }
8316
8317 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8318                              u32 shmem_base,
8319                              u32 shmem2_base,
8320                              u8 port)
8321 {
8322         u8 phy_index, fan_failure_det_req = 0;
8323         struct bnx2x_phy phy;
8324         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8325               phy_index++) {
8326                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8327                                        port, &phy)
8328                     != 0) {
8329                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8330                         return 0;
8331                 }
8332                 fan_failure_det_req |= (phy.flags &
8333                                         FLAGS_FAN_FAILURE_DET_REQ);
8334         }
8335         return fan_failure_det_req;
8336 }
8337
8338 void bnx2x_hw_reset_phy(struct link_params *params)
8339 {
8340         u8 phy_index;
8341         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8342               phy_index++) {
8343                 if (params->phy[phy_index].hw_reset) {
8344                         params->phy[phy_index].hw_reset(
8345                                 &params->phy[phy_index],
8346                                 params);
8347                         params->phy[phy_index] = phy_null;
8348                 }
8349         }
8350 }