1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
31 /********************************************************/
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
41 #define I2C_SWITCH_WIDTH 2
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
48 /***********************************************************/
49 /* Shortcut definitions */
50 /***********************************************************/
52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
54 #define NIG_STATUS_EMAC0_MI_INT \
55 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
56 #define NIG_STATUS_XGXS0_LINK10G \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
58 #define NIG_STATUS_XGXS0_LINK_STATUS \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
62 #define NIG_STATUS_SERDES0_LINK_STATUS \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
64 #define NIG_MASK_MI_INT \
65 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
66 #define NIG_MASK_XGXS0_LINK10G \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
68 #define NIG_MASK_XGXS0_LINK_STATUS \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
70 #define NIG_MASK_SERDES0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
73 #define MDIO_AN_CL73_OR_37_COMPLETE \
74 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
75 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
77 #define XGXS_RESET_BITS \
78 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
84 #define SERDES_RESET_BITS \
85 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
90 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
91 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
92 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
93 #define AUTONEG_PARALLEL \
94 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
95 #define AUTONEG_SGMII_FIBER_AUTODET \
96 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
97 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
103 #define GP_STATUS_SPEED_MASK \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
105 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
106 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
107 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
108 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
109 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
110 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
111 #define GP_STATUS_10G_HIG \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
113 #define GP_STATUS_10G_CX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
116 #define GP_STATUS_10G_KX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
119 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
121 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
122 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
123 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
124 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
125 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
126 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
127 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
128 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
129 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
130 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
131 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
132 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
133 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
134 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
135 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
136 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB thresholds for E2*/
165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
177 /* BRB thresholds for E3A0 */
178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
191 /* BRB thresholds for E3B0 2 port mode*/
192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
208 /* Lossy +Lossless GUARANTIED == GUART */
209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
210 /* Lossless +Lossless*/
211 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
217 /* Lossless +Lossless*/
218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
226 /* BRB thresholds for E3B0 4 port mode */
227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
243 #define PFC_E3B0_4P_LB_GUART 120
245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
251 #define DCBX_INVALID_COS (0xFF)
253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
254 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
257 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
259 #define MAX_PACKET_SIZE (9700)
260 #define WC_UC_TIMEOUT 100
262 /**********************************************************/
264 /**********************************************************/
266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
267 bnx2x_cl45_write(_bp, _phy, \
268 (_phy)->def_md_devad, \
269 (_bank + (_addr & 0xf)), \
272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
273 bnx2x_cl45_read(_bp, _phy, \
274 (_phy)->def_md_devad, \
275 (_bank + (_addr & 0xf)), \
278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
280 u32 val = REG_RD(bp, reg);
283 REG_WR(bp, reg, val);
287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
289 u32 val = REG_RD(bp, reg);
292 REG_WR(bp, reg, val);
296 /******************************************************************/
297 /* EPIO/GPIO section */
298 /******************************************************************/
299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
301 u32 epio_mask, gp_oenable;
305 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
309 epio_mask = 1 << epio_pin;
310 /* Set this EPIO to output */
311 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
312 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
314 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
318 u32 epio_mask, gp_output, gp_oenable;
322 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
325 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
326 epio_mask = 1 << epio_pin;
327 /* Set this EPIO to output */
328 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
330 gp_output |= epio_mask;
332 gp_output &= ~epio_mask;
334 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
336 /* Set the value for this EPIO */
337 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
338 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
343 if (pin_cfg == PIN_CFG_NA)
345 if (pin_cfg >= PIN_CFG_EPIO0) {
346 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
348 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
349 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
350 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
356 if (pin_cfg == PIN_CFG_NA)
358 if (pin_cfg >= PIN_CFG_EPIO0) {
359 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
361 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
362 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
363 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
368 /******************************************************************/
370 /******************************************************************/
371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
373 /* ETS disabled configuration*/
374 struct bnx2x *bp = params->bp;
376 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
379 * mapping between entry priority to client number (0,1,2 -debug and
380 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
382 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
383 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
386 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
388 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
389 * as strict. Bits 0,1,2 - debug and management entries, 3 -
390 * COS0 entry, 4 - COS1 entry.
391 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
392 * bit4 bit3 bit2 bit1 bit0
393 * MCP and debug are strict
396 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
397 /* defines which entries (clients) are subjected to WFQ arbitration */
398 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
400 * For strict priority entries defines the number of consecutive
401 * slots for the highest priority.
403 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
405 * mapping between the CREDIT_WEIGHT registers and actual client
408 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
409 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
410 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
412 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
413 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
414 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
415 /* ETS mode disable */
416 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
418 * If ETS mode is enabled (there is no strict priority) defines a WFQ
419 * weight for COS0/COS1.
421 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
422 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
423 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
424 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
425 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
426 /* Defines the number of consecutive slots for the strict priority */
427 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
429 /******************************************************************************
431 * Getting min_w_val will be set according to line speed .
433 ******************************************************************************/
434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
437 /* Calculate min_w_val.*/
439 if (SPEED_20000 == vars->line_speed)
440 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
442 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
444 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
446 * If the link isn't up (static configuration for example ) The
447 * link will be according to 20GBPS.
451 /******************************************************************************
453 * Getting credit upper bound form min_w_val.
455 ******************************************************************************/
456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
458 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
460 return credit_upper_bound;
462 /******************************************************************************
464 * Set credit upper bound for NIG.
466 ******************************************************************************/
467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
468 const struct link_params *params,
471 struct bnx2x *bp = params->bp;
472 const u8 port = params->port;
473 const u32 credit_upper_bound =
474 bnx2x_ets_get_credit_upper_bound(min_w_val);
476 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
477 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
478 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
479 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
480 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
481 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
482 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
483 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
484 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
485 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
486 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
487 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
490 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
492 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
494 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
498 /******************************************************************************
500 * Will return the NIG ETS registers to init values.Except
501 * credit_upper_bound.
502 * That isn't used in this configuration (No WFQ is enabled) and will be
503 * configured acording to spec
505 ******************************************************************************/
506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
507 const struct link_vars *vars)
509 struct bnx2x *bp = params->bp;
510 const u8 port = params->port;
511 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
513 * mapping between entry priority to client number (0,1,2 -debug and
514 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
515 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
516 * reset value or init tool
519 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
520 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
522 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
526 * For strict priority entries defines the number of consecutive
527 * slots for the highest priority.
529 /* TODO_ETS - Should be done by reset value or init tool */
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
531 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
533 * mapping between the CREDIT_WEIGHT registers and actual client
536 /* TODO_ETS - Should be done by reset value or init tool */
539 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
540 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
549 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
550 * as strict. Bits 0,1,2 - debug and management entries, 3 -
551 * COS0 entry, 4 - COS1 entry.
552 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
553 * bit4 bit3 bit2 bit1 bit0
554 * MCP and debug are strict
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
560 /* defines which entries (clients) are subjected to WFQ arbitration */
561 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
562 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
565 * Please notice the register address are note continuous and a
566 * for here is note appropriate.In 2 port mode port0 only COS0-5
567 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
568 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
569 * are never used for WFQ
571 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
572 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
573 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
574 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
575 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
578 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
579 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
581 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
582 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
584 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
586 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
589 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
591 /******************************************************************************
593 * Set credit upper bound for PBF.
595 ******************************************************************************/
596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
597 const struct link_params *params,
600 struct bnx2x *bp = params->bp;
601 const u32 credit_upper_bound =
602 bnx2x_ets_get_credit_upper_bound(min_w_val);
603 const u8 port = params->port;
604 u32 base_upper_bound = 0;
608 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
609 * port mode port1 has COS0-2 that can be used for WFQ.
612 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
613 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
615 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
616 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
619 for (i = 0; i < max_cos; i++)
620 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
623 /******************************************************************************
625 * Will return the PBF ETS registers to init values.Except
626 * credit_upper_bound.
627 * That isn't used in this configuration (No WFQ is enabled) and will be
628 * configured acording to spec
630 ******************************************************************************/
631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
633 struct bnx2x *bp = params->bp;
634 const u8 port = params->port;
635 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
641 * mapping between entry priority to client number 0 - COS0
642 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
643 * TODO_ETS - Should be done by reset value or init tool
646 /* 0x688 (|011|0 10|00 1|000) */
647 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
649 /* (10 1|100 |011|0 10|00 1|000) */
650 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
652 /* TODO_ETS - Should be done by reset value or init tool */
654 /* 0x688 (|011|0 10|00 1|000)*/
655 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
657 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
658 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
660 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
661 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
664 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
665 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
667 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
668 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
670 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
671 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
674 base_weight = PBF_REG_COS0_WEIGHT_P0;
675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
677 base_weight = PBF_REG_COS0_WEIGHT_P1;
678 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
681 for (i = 0; i < max_cos; i++)
682 REG_WR(bp, base_weight + (0x4 * i), 0);
684 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
686 /******************************************************************************
688 * E3B0 disable will return basicly the values to init values.
690 ******************************************************************************/
691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
692 const struct link_vars *vars)
694 struct bnx2x *bp = params->bp;
696 if (!CHIP_IS_E3B0(bp)) {
697 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
702 bnx2x_ets_e3b0_nig_disabled(params, vars);
704 bnx2x_ets_e3b0_pbf_disabled(params);
709 /******************************************************************************
711 * Disable will return basicly the values to init values.
713 ******************************************************************************/
714 int bnx2x_ets_disabled(struct link_params *params,
715 struct link_vars *vars)
717 struct bnx2x *bp = params->bp;
718 int bnx2x_status = 0;
720 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
721 bnx2x_ets_e2e3a0_disabled(params);
722 else if (CHIP_IS_E3B0(bp))
723 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
725 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
732 /******************************************************************************
734 * Set the COS mappimg to SP and BW until this point all the COS are not
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
738 const struct bnx2x_ets_params *ets_params,
739 const u8 cos_sp_bitmap,
740 const u8 cos_bw_bitmap)
742 struct bnx2x *bp = params->bp;
743 const u8 port = params->port;
744 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
745 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
746 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
747 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
749 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
750 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
752 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
753 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
755 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
756 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
757 nig_cli_subject2wfq_bitmap);
759 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
760 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
761 pbf_cli_subject2wfq_bitmap);
766 /******************************************************************************
768 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
769 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
770 ******************************************************************************/
771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
773 const u32 min_w_val_nig,
774 const u32 min_w_val_pbf,
779 u32 nig_reg_adress_crd_weight = 0;
780 u32 pbf_reg_adress_crd_weight = 0;
781 /* Calculate and set BW for this COS*/
782 const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
783 const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
787 nig_reg_adress_crd_weight =
788 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
789 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
790 pbf_reg_adress_crd_weight = (port) ?
791 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
794 nig_reg_adress_crd_weight = (port) ?
795 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
796 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
797 pbf_reg_adress_crd_weight = (port) ?
798 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
801 nig_reg_adress_crd_weight = (port) ?
802 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
803 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
805 pbf_reg_adress_crd_weight = (port) ?
806 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
811 nig_reg_adress_crd_weight =
812 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
813 pbf_reg_adress_crd_weight =
814 PBF_REG_COS3_WEIGHT_P0;
819 nig_reg_adress_crd_weight =
820 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
821 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
826 nig_reg_adress_crd_weight =
827 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
828 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
832 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
834 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
838 /******************************************************************************
840 * Calculate the total BW.A value of 0 isn't legal.
842 ******************************************************************************/
843 static int bnx2x_ets_e3b0_get_total_bw(
844 const struct link_params *params,
845 const struct bnx2x_ets_params *ets_params,
848 struct bnx2x *bp = params->bp;
852 /* Calculate total BW requested */
853 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
854 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
856 if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
857 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
862 ets_params->cos[cos_idx].params.bw_params.bw;
866 /*Check taotl BW is valid */
867 if ((100 != *total_bw) || (0 == *total_bw)) {
868 if (0 == *total_bw) {
869 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
873 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
876 * We can handle a case whre the BW isn't 100 this can happen
877 * if the TC are joined.
883 /******************************************************************************
885 * Invalidate all the sp_pri_to_cos.
887 ******************************************************************************/
888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
891 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
892 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
894 /******************************************************************************
896 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
897 * according to sp_pri_to_cos.
899 ******************************************************************************/
900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
901 u8 *sp_pri_to_cos, const u8 pri,
904 struct bnx2x *bp = params->bp;
905 const u8 port = params->port;
906 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
907 DCBX_E3B0_MAX_NUM_COS_PORT0;
909 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
910 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
911 "parameter There can't be two COS's with"
912 "the same strict pri\n");
916 if (pri > max_num_of_cos) {
917 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
918 "parameter Illegal strict priority\n");
922 sp_pri_to_cos[pri] = cos_entry;
927 /******************************************************************************
929 * Returns the correct value according to COS and priority in
930 * the sp_pri_cli register.
932 ******************************************************************************/
933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
939 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
940 (pri_set + pri_offset));
944 /******************************************************************************
946 * Returns the correct value according to COS and priority in the
947 * sp_pri_cli register for NIG.
949 ******************************************************************************/
950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
952 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
953 const u8 nig_cos_offset = 3;
954 const u8 nig_pri_offset = 3;
956 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
960 /******************************************************************************
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for PBF.
965 ******************************************************************************/
966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
968 const u8 pbf_cos_offset = 0;
969 const u8 pbf_pri_offset = 0;
971 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
976 /******************************************************************************
978 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
979 * according to sp_pri_to_cos.(which COS has higher priority)
981 ******************************************************************************/
982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
985 struct bnx2x *bp = params->bp;
987 const u8 port = params->port;
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
989 u64 pri_cli_nig = 0x210;
990 u32 pri_cli_pbf = 0x0;
993 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
994 DCBX_E3B0_MAX_NUM_COS_PORT0;
996 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
998 /* Set all the strict priority first */
999 for (i = 0; i < max_num_of_cos; i++) {
1000 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1003 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004 "invalid cos entry\n");
1008 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009 sp_pri_to_cos[i], pri_set);
1011 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012 sp_pri_to_cos[i], pri_set);
1013 pri_bitmask = 1 << sp_pri_to_cos[i];
1014 /* COS is used remove it from bitmap.*/
1015 if (0 == (pri_bitmask & cos_bit_to_set)) {
1017 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018 "invalid There can't be two COS's with"
1019 " the same strict pri\n");
1022 cos_bit_to_set &= ~pri_bitmask;
1027 /* Set all the Non strict priority i= COS*/
1028 for (i = 0; i < max_num_of_cos; i++) {
1029 pri_bitmask = 1 << i;
1030 /* Check if COS was already used for SP */
1031 if (pri_bitmask & cos_bit_to_set) {
1032 /* COS wasn't used for SP */
1033 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1036 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1038 /* COS is used remove it from bitmap.*/
1039 cos_bit_to_set &= ~pri_bitmask;
1044 if (pri_set != max_num_of_cos) {
1045 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046 "entries were set\n");
1051 /* Only 6 usable clients*/
1052 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1055 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1057 /* Only 9 usable clients*/
1058 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1061 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1063 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1066 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1071 /******************************************************************************
1073 * Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076 const struct link_vars *vars,
1077 const struct bnx2x_ets_params *ets_params)
1079 struct bnx2x *bp = params->bp;
1080 int bnx2x_status = 0;
1081 const u8 port = params->port;
1083 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085 u8 cos_bw_bitmap = 0;
1086 u8 cos_sp_bitmap = 0;
1087 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089 DCBX_E3B0_MAX_NUM_COS_PORT0;
1092 if (!CHIP_IS_E3B0(bp)) {
1093 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1098 if ((ets_params->num_of_cos > max_num_of_cos)) {
1099 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100 "isn't supported\n");
1104 /* Prepare sp strict priority parameters*/
1105 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1107 /* Prepare BW parameters*/
1108 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1110 if (0 != bnx2x_status) {
1111 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1117 * Upper bound is set according to current link speed (min_w_val
1118 * should be the same for upper bound and COS credit val).
1120 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1124 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126 cos_bw_bitmap |= (1 << cos_entry);
1128 * The function also sets the BW in HW(not the mappin
1131 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1134 ets_params->cos[cos_entry].params.bw_params.bw,
1136 } else if (bnx2x_cos_state_strict ==
1137 ets_params->cos[cos_entry].state){
1138 cos_sp_bitmap |= (1 << cos_entry);
1140 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1143 ets_params->cos[cos_entry].params.sp_params.pri,
1147 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1151 if (0 != bnx2x_status) {
1152 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1154 return bnx2x_status;
1158 /* Set SP register (which COS has higher priority) */
1159 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1162 if (0 != bnx2x_status) {
1163 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1165 return bnx2x_status;
1168 /* Set client mapping of BW and strict */
1169 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1173 if (0 != bnx2x_status) {
1174 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175 return bnx2x_status;
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1181 /* ETS disabled configuration */
1182 struct bnx2x *bp = params->bp;
1183 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1185 * defines which entries (clients) are subjected to WFQ arbitration
1189 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1191 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192 * client numbers (WEIGHT_0 does not actually have to represent
1194 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1195 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1197 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1199 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1204 /* ETS mode enabled*/
1205 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1207 /* Defines the number of consecutive slots for the strict priority */
1208 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1210 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1212 * entry, 4 - COS1 entry.
1213 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214 * bit4 bit3 bit2 bit1 bit0
1215 * MCP and debug are strict
1217 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1219 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1229 /* ETS disabled configuration*/
1230 struct bnx2x *bp = params->bp;
1231 const u32 total_bw = cos0_bw + cos1_bw;
1232 u32 cos0_credit_weight = 0;
1233 u32 cos1_credit_weight = 0;
1235 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1237 if ((0 == total_bw) ||
1240 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1244 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1246 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1249 bnx2x_ets_bw_limit_common(params);
1251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1254 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1260 /* ETS disabled configuration*/
1261 struct bnx2x *bp = params->bp;
1264 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1266 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267 * as strict. Bits 0,1,2 - debug and management entries,
1268 * 3 - COS0 entry, 4 - COS1 entry.
1269 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270 * bit4 bit3 bit2 bit1 bit0
1271 * MCP and debug are strict
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1275 * For strict priority entries defines the number of consecutive slots
1276 * for the highest priority.
1278 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279 /* ETS mode disable */
1280 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281 /* Defines the number of consecutive slots for the strict priority */
1282 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1284 /* Defines the number of consecutive slots for the strict priority */
1285 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1288 * mapping between entry priority to client number (0,1,2 -debug and
1289 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1291 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1292 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1293 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1295 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1300 /******************************************************************/
1302 /******************************************************************/
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305 struct link_vars *vars,
1308 struct bnx2x *bp = params->bp;
1310 u32 pause_val, pfc0_val, pfc1_val;
1312 /* XMAC base adrr */
1313 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1315 /* Initialize pause and pfc registers */
1316 pause_val = 0x18000;
1317 pfc0_val = 0xFFFF8000;
1320 /* No PFC support */
1321 if (!(params->feature_config_flags &
1322 FEATURE_CONFIG_PFC_ENABLED)) {
1325 * RX flow control - Process pause frame in receive direction
1327 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1331 * TX flow control - Send pause packet when buffer is full
1333 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335 } else {/* PFC support */
1336 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1342 /* Write pause and PFC registers */
1343 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1348 /* Set MAC address for source TX Pause/PFC frames */
1349 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350 ((params->mac_addr[2] << 24) |
1351 (params->mac_addr[3] << 16) |
1352 (params->mac_addr[4] << 8) |
1353 (params->mac_addr[5])));
1354 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355 ((params->mac_addr[0] << 8) |
1356 (params->mac_addr[1])));
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363 u32 pfc_frames_sent[2],
1364 u32 pfc_frames_received[2])
1366 /* Read pfc statistic */
1367 struct bnx2x *bp = params->bp;
1368 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1372 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1374 /* PFC received frames */
1375 val_xoff = REG_RD(bp, emac_base +
1376 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1381 pfc_frames_received[0] = val_xon + val_xoff;
1383 /* PFC received sent */
1384 val_xoff = REG_RD(bp, emac_base +
1385 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1390 pfc_frames_sent[0] = val_xon + val_xoff;
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395 u32 pfc_frames_sent[2],
1396 u32 pfc_frames_received[2])
1398 /* Read pfc statistic */
1399 struct bnx2x *bp = params->bp;
1401 DP(NETIF_MSG_LINK, "pfc statistic\n");
1406 if (MAC_TYPE_EMAC == vars->mac_type) {
1407 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409 pfc_frames_received);
1412 /******************************************************************/
1413 /* MAC/PBF section */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1417 u32 mode, emac_base;
1419 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420 * (a value of 49==0x31) and make sure that the AUTO poll is off
1424 emac_base = GRCBASE_EMAC0;
1426 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429 EMAC_MDIO_MODE_CLOCK_CNT);
1430 if (USES_WARPCORE(bp))
1431 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1433 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1435 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1441 static void bnx2x_emac_init(struct link_params *params,
1442 struct link_vars *vars)
1444 /* reset and unreset the emac core */
1445 struct bnx2x *bp = params->bp;
1446 u8 port = params->port;
1447 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1451 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1457 /* init emac - use read-modify-write */
1458 /* self clear reset */
1459 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1464 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1467 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1471 } while (val & EMAC_MODE_RESET);
1472 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473 /* Set mac address */
1474 val = ((params->mac_addr[0] << 8) |
1475 params->mac_addr[1]);
1476 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1478 val = ((params->mac_addr[2] << 24) |
1479 (params->mac_addr[3] << 16) |
1480 (params->mac_addr[4] << 8) |
1481 params->mac_addr[5]);
1482 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1489 struct bnx2x *bp = params->bp;
1491 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1493 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1495 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1499 static void bnx2x_umac_enable(struct link_params *params,
1500 struct link_vars *vars, u8 lb)
1503 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504 struct bnx2x *bp = params->bp;
1506 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508 usleep_range(1000, 1000);
1510 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1513 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1516 * This register determines on which events the MAC will assert
1517 * error on the i/f to the NIG along w/ EOP.
1521 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522 * params->port*0x14, 0xfffff.
1524 /* This register opens the gate for the UMAC despite its name */
1525 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1527 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531 switch (vars->line_speed) {
1545 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1549 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1550 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1552 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1553 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1555 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1558 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1559 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1560 ((params->mac_addr[2] << 24) |
1561 (params->mac_addr[3] << 16) |
1562 (params->mac_addr[4] << 8) |
1563 (params->mac_addr[5])));
1564 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1565 ((params->mac_addr[0] << 8) |
1566 (params->mac_addr[1])));
1568 /* Enable RX and TX */
1569 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1570 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1571 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1572 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1575 /* Remove SW Reset */
1576 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1578 /* Check loopback mode */
1580 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1581 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1584 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1585 * length used by the MAC receive logic to check frames.
1587 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1588 bnx2x_set_xumac_nig(params,
1589 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1590 vars->mac_type = MAC_TYPE_UMAC;
1594 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1596 u32 port4mode_ovwr_val;
1597 /* Check 4-port override enabled */
1598 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1599 if (port4mode_ovwr_val & (1<<0)) {
1600 /* Return 4-port mode override value */
1601 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1603 /* Return 4-port mode from input pin */
1604 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1607 /* Define the XMAC mode */
1608 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1610 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1613 * In 4-port mode, need to set the mode only once, so if XMAC is
1614 * already out of reset, it means the mode has already been set,
1615 * and it must not* reset the XMAC again, since it controls both
1619 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1620 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1621 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1622 " in 4-port mode\n");
1627 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1628 MISC_REGISTERS_RESET_REG_2_XMAC);
1629 usleep_range(1000, 1000);
1631 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1632 MISC_REGISTERS_RESET_REG_2_XMAC);
1634 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1636 /* Set the number of ports on the system side to up to 2 */
1637 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1639 /* Set the number of ports on the Warp Core to 10G */
1640 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1642 /* Set the number of ports on the system side to 1 */
1643 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1644 if (max_speed == SPEED_10000) {
1645 DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1646 " port per path\n");
1647 /* Set the number of ports on the Warp Core to 10G */
1648 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1650 DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1652 /* Set the number of ports on the Warp Core to 20G */
1653 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1657 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1658 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1659 usleep_range(1000, 1000);
1661 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1662 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1666 static void bnx2x_xmac_disable(struct link_params *params)
1668 u8 port = params->port;
1669 struct bnx2x *bp = params->bp;
1670 u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1672 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1673 MISC_REGISTERS_RESET_REG_2_XMAC) {
1674 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1675 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1676 usleep_range(1000, 1000);
1677 bnx2x_set_xumac_nig(params, 0, 0);
1678 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1679 XMAC_CTRL_REG_SOFT_RESET);
1683 static int bnx2x_xmac_enable(struct link_params *params,
1684 struct link_vars *vars, u8 lb)
1687 struct bnx2x *bp = params->bp;
1688 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1690 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1692 bnx2x_xmac_init(bp, vars->line_speed);
1695 * This register determines on which events the MAC will assert
1696 * error on the i/f to the NIG along w/ EOP.
1700 * This register tells the NIG whether to send traffic to UMAC
1703 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1705 /* Set Max packet size */
1706 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1708 /* CRC append for Tx packets */
1709 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1712 bnx2x_update_pfc_xmac(params, vars, 0);
1714 /* Enable TX and RX */
1715 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1717 /* Check loopback mode */
1719 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1720 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1721 bnx2x_set_xumac_nig(params,
1722 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1724 vars->mac_type = MAC_TYPE_XMAC;
1728 static int bnx2x_emac_enable(struct link_params *params,
1729 struct link_vars *vars, u8 lb)
1731 struct bnx2x *bp = params->bp;
1732 u8 port = params->port;
1733 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1736 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1738 /* enable emac and not bmac */
1739 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1742 if (vars->phy_flags & PHY_XGXS_FLAG) {
1743 u32 ser_lane = ((params->lane_config &
1744 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1745 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1747 DP(NETIF_MSG_LINK, "XGXS\n");
1748 /* select the master lanes (out of 0-3) */
1749 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1751 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1753 } else { /* SerDes */
1754 DP(NETIF_MSG_LINK, "SerDes\n");
1756 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1759 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1760 EMAC_RX_MODE_RESET);
1761 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1762 EMAC_TX_MODE_RESET);
1764 if (CHIP_REV_IS_SLOW(bp)) {
1765 /* config GMII mode */
1766 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1767 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1769 /* pause enable/disable */
1770 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1771 EMAC_RX_MODE_FLOW_EN);
1773 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1774 (EMAC_TX_MODE_EXT_PAUSE_EN |
1775 EMAC_TX_MODE_FLOW_EN));
1776 if (!(params->feature_config_flags &
1777 FEATURE_CONFIG_PFC_ENABLED)) {
1778 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1779 bnx2x_bits_en(bp, emac_base +
1780 EMAC_REG_EMAC_RX_MODE,
1781 EMAC_RX_MODE_FLOW_EN);
1783 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1784 bnx2x_bits_en(bp, emac_base +
1785 EMAC_REG_EMAC_TX_MODE,
1786 (EMAC_TX_MODE_EXT_PAUSE_EN |
1787 EMAC_TX_MODE_FLOW_EN));
1789 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1790 EMAC_TX_MODE_FLOW_EN);
1793 /* KEEP_VLAN_TAG, promiscuous */
1794 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1795 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1798 * Setting this bit causes MAC control frames (except for pause
1799 * frames) to be passed on for processing. This setting has no
1800 * affect on the operation of the pause frames. This bit effects
1801 * all packets regardless of RX Parser packet sorting logic.
1802 * Turn the PFC off to make sure we are in Xon state before
1805 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1806 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1807 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1808 /* Enable PFC again */
1809 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1810 EMAC_REG_RX_PFC_MODE_RX_EN |
1811 EMAC_REG_RX_PFC_MODE_TX_EN |
1812 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1814 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1816 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1818 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1819 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1821 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1824 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1829 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1832 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1834 /* enable emac for jumbo packets */
1835 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1836 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1837 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1840 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1842 /* disable the NIG in/out to the bmac */
1843 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1844 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1845 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1847 /* enable the NIG in/out to the emac */
1848 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1850 if ((params->feature_config_flags &
1851 FEATURE_CONFIG_PFC_ENABLED) ||
1852 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1855 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1856 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1858 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1860 vars->mac_type = MAC_TYPE_EMAC;
1864 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1865 struct link_vars *vars)
1868 struct bnx2x *bp = params->bp;
1869 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1870 NIG_REG_INGRESS_BMAC0_MEM;
1873 if ((!(params->feature_config_flags &
1874 FEATURE_CONFIG_PFC_ENABLED)) &&
1875 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1876 /* Enable BigMAC to react on received Pause packets */
1880 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1884 if (!(params->feature_config_flags &
1885 FEATURE_CONFIG_PFC_ENABLED) &&
1886 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1890 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1893 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1894 struct link_vars *vars,
1898 * Set rx control: Strip CRC and enable BigMAC to relay
1899 * control packets to the system as well
1902 struct bnx2x *bp = params->bp;
1903 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1904 NIG_REG_INGRESS_BMAC0_MEM;
1907 if ((!(params->feature_config_flags &
1908 FEATURE_CONFIG_PFC_ENABLED)) &&
1909 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1910 /* Enable BigMAC to react on received Pause packets */
1914 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1919 if (!(params->feature_config_flags &
1920 FEATURE_CONFIG_PFC_ENABLED) &&
1921 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1925 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1927 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1928 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1929 /* Enable PFC RX & TX & STATS and set 8 COS */
1931 wb_data[0] |= (1<<0); /* RX */
1932 wb_data[0] |= (1<<1); /* TX */
1933 wb_data[0] |= (1<<2); /* Force initial Xon */
1934 wb_data[0] |= (1<<3); /* 8 cos */
1935 wb_data[0] |= (1<<5); /* STATS */
1937 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1939 /* Clear the force Xon */
1940 wb_data[0] &= ~(1<<2);
1942 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1943 /* disable PFC RX & TX & STATS and set 8 COS */
1948 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1951 * Set Time (based unit is 512 bit time) between automatic
1952 * re-sending of PP packets amd enable automatic re-send of
1953 * Per-Priroity Packet as long as pp_gen is asserted and
1954 * pp_disable is low.
1957 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1958 val |= (1<<16); /* enable automatic re-send */
1962 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1966 val = 0x3; /* Enable RX and TX */
1968 val |= 0x4; /* Local loopback */
1969 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1971 /* When PFC enabled, Pass pause frames towards the NIG. */
1972 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1973 val |= ((1<<6)|(1<<5));
1977 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1981 /* PFC BRB internal port configuration params */
1982 struct bnx2x_pfc_brb_threshold_val {
1989 struct bnx2x_pfc_brb_e3b0_val {
1990 u32 full_lb_xoff_th;
1991 u32 full_lb_xon_threshold;
1993 u32 mac_0_class_t_guarantied;
1994 u32 mac_0_class_t_guarantied_hyst;
1995 u32 mac_1_class_t_guarantied;
1996 u32 mac_1_class_t_guarantied_hyst;
1999 struct bnx2x_pfc_brb_th_val {
2000 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2001 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2003 static int bnx2x_pfc_brb_get_config_params(
2004 struct link_params *params,
2005 struct bnx2x_pfc_brb_th_val *config_val)
2007 struct bnx2x *bp = params->bp;
2008 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2009 if (CHIP_IS_E2(bp)) {
2010 config_val->pauseable_th.pause_xoff =
2011 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2012 config_val->pauseable_th.pause_xon =
2013 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2014 config_val->pauseable_th.full_xoff =
2015 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2016 config_val->pauseable_th.full_xon =
2017 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2019 config_val->non_pauseable_th.pause_xoff =
2020 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2021 config_val->non_pauseable_th.pause_xon =
2022 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2023 config_val->non_pauseable_th.full_xoff =
2024 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2025 config_val->non_pauseable_th.full_xon =
2026 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2027 } else if (CHIP_IS_E3A0(bp)) {
2028 config_val->pauseable_th.pause_xoff =
2029 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2030 config_val->pauseable_th.pause_xon =
2031 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2032 config_val->pauseable_th.full_xoff =
2033 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2034 config_val->pauseable_th.full_xon =
2035 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2037 config_val->non_pauseable_th.pause_xoff =
2038 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2039 config_val->non_pauseable_th.pause_xon =
2040 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2041 config_val->non_pauseable_th.full_xoff =
2042 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2043 config_val->non_pauseable_th.full_xon =
2044 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2045 } else if (CHIP_IS_E3B0(bp)) {
2046 if (params->phy[INT_PHY].flags &
2047 FLAGS_4_PORT_MODE) {
2048 config_val->pauseable_th.pause_xoff =
2049 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2050 config_val->pauseable_th.pause_xon =
2051 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2052 config_val->pauseable_th.full_xoff =
2053 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2054 config_val->pauseable_th.full_xon =
2055 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2057 config_val->non_pauseable_th.pause_xoff =
2058 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2059 config_val->non_pauseable_th.pause_xon =
2060 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2061 config_val->non_pauseable_th.full_xoff =
2062 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2063 config_val->non_pauseable_th.full_xon =
2064 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2066 config_val->pauseable_th.pause_xoff =
2067 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2068 config_val->pauseable_th.pause_xon =
2069 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2070 config_val->pauseable_th.full_xoff =
2071 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2072 config_val->pauseable_th.full_xon =
2073 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2075 config_val->non_pauseable_th.pause_xoff =
2076 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2077 config_val->non_pauseable_th.pause_xon =
2078 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2079 config_val->non_pauseable_th.full_xoff =
2080 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2081 config_val->non_pauseable_th.full_xon =
2082 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2091 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2092 struct bnx2x_pfc_brb_e3b0_val
2097 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2098 e3b0_val->full_lb_xoff_th =
2099 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2100 e3b0_val->full_lb_xon_threshold =
2101 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2102 e3b0_val->lb_guarantied =
2103 PFC_E3B0_4P_LB_GUART;
2104 e3b0_val->mac_0_class_t_guarantied =
2105 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2106 e3b0_val->mac_0_class_t_guarantied_hyst =
2107 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2108 e3b0_val->mac_1_class_t_guarantied =
2109 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2110 e3b0_val->mac_1_class_t_guarantied_hyst =
2111 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2113 e3b0_val->full_lb_xoff_th =
2114 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2115 e3b0_val->full_lb_xon_threshold =
2116 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2117 e3b0_val->mac_0_class_t_guarantied_hyst =
2118 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2119 e3b0_val->mac_1_class_t_guarantied =
2120 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2121 e3b0_val->mac_1_class_t_guarantied_hyst =
2122 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2124 if (cos0_pauseable != cos1_pauseable) {
2125 /* nonpauseable= Lossy + pauseable = Lossless*/
2126 e3b0_val->lb_guarantied =
2127 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2128 e3b0_val->mac_0_class_t_guarantied =
2129 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2130 } else if (cos0_pauseable) {
2131 /* Lossless +Lossless*/
2132 e3b0_val->lb_guarantied =
2133 PFC_E3B0_2P_PAUSE_LB_GUART;
2134 e3b0_val->mac_0_class_t_guarantied =
2135 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2138 e3b0_val->lb_guarantied =
2139 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2140 e3b0_val->mac_0_class_t_guarantied =
2141 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2145 static int bnx2x_update_pfc_brb(struct link_params *params,
2146 struct link_vars *vars,
2147 struct bnx2x_nig_brb_pfc_port_params
2150 struct bnx2x *bp = params->bp;
2151 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2152 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2153 &config_val.pauseable_th;
2154 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2155 int set_pfc = params->feature_config_flags &
2156 FEATURE_CONFIG_PFC_ENABLED;
2157 int bnx2x_status = 0;
2158 u8 port = params->port;
2160 /* default - pause configuration */
2161 reg_th_config = &config_val.pauseable_th;
2162 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2163 if (0 != bnx2x_status)
2164 return bnx2x_status;
2166 if (set_pfc && pfc_params)
2168 if (!pfc_params->cos0_pauseable)
2169 reg_th_config = &config_val.non_pauseable_th;
2171 * The number of free blocks below which the pause signal to class 0
2172 * of MAC #n is asserted. n=0,1
2174 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2175 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2176 reg_th_config->pause_xoff);
2178 * The number of free blocks above which the pause signal to class 0
2179 * of MAC #n is de-asserted. n=0,1
2181 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2182 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2184 * The number of free blocks below which the full signal to class 0
2185 * of MAC #n is asserted. n=0,1
2187 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2188 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2190 * The number of free blocks above which the full signal to class 0
2191 * of MAC #n is de-asserted. n=0,1
2193 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2194 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2196 if (set_pfc && pfc_params) {
2198 if (pfc_params->cos1_pauseable)
2199 reg_th_config = &config_val.pauseable_th;
2201 reg_th_config = &config_val.non_pauseable_th;
2203 * The number of free blocks below which the pause signal to
2204 * class 1 of MAC #n is asserted. n=0,1
2206 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2207 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2208 reg_th_config->pause_xoff);
2210 * The number of free blocks above which the pause signal to
2211 * class 1 of MAC #n is de-asserted. n=0,1
2213 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2214 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2215 reg_th_config->pause_xon);
2217 * The number of free blocks below which the full signal to
2218 * class 1 of MAC #n is asserted. n=0,1
2220 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2221 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2222 reg_th_config->full_xoff);
2224 * The number of free blocks above which the full signal to
2225 * class 1 of MAC #n is de-asserted. n=0,1
2227 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2228 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2229 reg_th_config->full_xon);
2232 if (CHIP_IS_E3B0(bp)) {
2233 /*Should be done by init tool */
2235 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2241 * The hysteresis on the guarantied buffer space for the Lb port
2242 * before signaling XON.
2244 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2246 bnx2x_pfc_brb_get_e3b0_config_params(
2249 pfc_params->cos0_pauseable,
2250 pfc_params->cos1_pauseable);
2252 * The number of free blocks below which the full signal to the
2253 * LB port is asserted.
2255 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2256 e3b0_val.full_lb_xoff_th);
2258 * The number of free blocks above which the full signal to the
2259 * LB port is de-asserted.
2261 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2262 e3b0_val.full_lb_xon_threshold);
2264 * The number of blocks guarantied for the MAC #n port. n=0,1
2267 /*The number of blocks guarantied for the LB port.*/
2268 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2269 e3b0_val.lb_guarantied);
2272 * The number of blocks guarantied for the MAC #n port.
2274 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2275 2 * e3b0_val.mac_0_class_t_guarantied);
2276 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2277 2 * e3b0_val.mac_1_class_t_guarantied);
2279 * The number of blocks guarantied for class #t in MAC0. t=0,1
2281 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2282 e3b0_val.mac_0_class_t_guarantied);
2283 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2284 e3b0_val.mac_0_class_t_guarantied);
2286 * The hysteresis on the guarantied buffer space for class in
2289 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2290 e3b0_val.mac_0_class_t_guarantied_hyst);
2291 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2292 e3b0_val.mac_0_class_t_guarantied_hyst);
2295 * The number of blocks guarantied for class #t in MAC1.t=0,1
2297 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2298 e3b0_val.mac_1_class_t_guarantied);
2299 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2300 e3b0_val.mac_1_class_t_guarantied);
2302 * The hysteresis on the guarantied buffer space for class #t
2305 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2306 e3b0_val.mac_1_class_t_guarantied_hyst);
2307 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2308 e3b0_val.mac_1_class_t_guarantied_hyst);
2314 return bnx2x_status;
2317 /******************************************************************************
2319 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2320 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2321 ******************************************************************************/
2322 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2324 u32 priority_mask, u8 port)
2326 u32 nig_reg_rx_priority_mask_add = 0;
2328 switch (cos_entry) {
2330 nig_reg_rx_priority_mask_add = (port) ?
2331 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2332 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2335 nig_reg_rx_priority_mask_add = (port) ?
2336 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2337 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2340 nig_reg_rx_priority_mask_add = (port) ?
2341 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2342 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2347 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2352 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2357 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2361 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2365 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2367 struct bnx2x *bp = params->bp;
2369 REG_WR(bp, params->shmem_base +
2370 offsetof(struct shmem_region,
2371 port_mb[params->port].link_status), link_status);
2374 static void bnx2x_update_pfc_nig(struct link_params *params,
2375 struct link_vars *vars,
2376 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2378 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2379 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2380 u32 pkt_priority_to_cos = 0;
2381 struct bnx2x *bp = params->bp;
2382 u8 port = params->port;
2384 int set_pfc = params->feature_config_flags &
2385 FEATURE_CONFIG_PFC_ENABLED;
2386 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2389 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2390 * MAC control frames (that are not pause packets)
2391 * will be forwarded to the XCM.
2393 xcm_mask = REG_RD(bp,
2394 port ? NIG_REG_LLH1_XCM_MASK :
2395 NIG_REG_LLH0_XCM_MASK);
2397 * nig params will override non PFC params, since it's possible to
2398 * do transition from PFC to SAFC
2408 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2409 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2411 p0_hwpfc_enable = 1;
2414 llfc_out_en = nig_params->llfc_out_en;
2415 llfc_enable = nig_params->llfc_enable;
2416 pause_enable = nig_params->pause_enable;
2417 } else /*defaul non PFC mode - PAUSE */
2420 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2421 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2426 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2427 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2428 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2429 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2430 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2431 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2432 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2433 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2435 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2436 NIG_REG_PPP_ENABLE_0, ppp_enable);
2438 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2439 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2441 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2443 /* output enable for RX_XCM # IF */
2444 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2446 /* HW PFC TX enable */
2447 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2451 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2453 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2454 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2455 nig_params->rx_cos_priority_mask[i], port);
2457 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2458 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2459 nig_params->llfc_high_priority_classes);
2461 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2462 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2463 nig_params->llfc_low_priority_classes);
2465 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2466 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2467 pkt_priority_to_cos);
2470 int bnx2x_update_pfc(struct link_params *params,
2471 struct link_vars *vars,
2472 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2475 * The PFC and pause are orthogonal to one another, meaning when
2476 * PFC is enabled, the pause are disabled, and when PFC is
2477 * disabled, pause are set according to the pause result.
2480 struct bnx2x *bp = params->bp;
2481 int bnx2x_status = 0;
2482 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2484 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2485 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2487 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2489 bnx2x_update_mng(params, vars->link_status);
2491 /* update NIG params */
2492 bnx2x_update_pfc_nig(params, vars, pfc_params);
2494 /* update BRB params */
2495 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2496 if (0 != bnx2x_status)
2497 return bnx2x_status;
2500 return bnx2x_status;
2502 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2504 bnx2x_update_pfc_xmac(params, vars, 0);
2506 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2508 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2510 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2511 bnx2x_emac_enable(params, vars, 0);
2512 return bnx2x_status;
2516 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2518 bnx2x_update_pfc_bmac1(params, vars);
2521 if ((params->feature_config_flags &
2522 FEATURE_CONFIG_PFC_ENABLED) ||
2523 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2525 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2527 return bnx2x_status;
2531 static int bnx2x_bmac1_enable(struct link_params *params,
2532 struct link_vars *vars,
2535 struct bnx2x *bp = params->bp;
2536 u8 port = params->port;
2537 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2538 NIG_REG_INGRESS_BMAC0_MEM;
2542 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2547 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2551 wb_data[0] = ((params->mac_addr[2] << 24) |
2552 (params->mac_addr[3] << 16) |
2553 (params->mac_addr[4] << 8) |
2554 params->mac_addr[5]);
2555 wb_data[1] = ((params->mac_addr[0] << 8) |
2556 params->mac_addr[1]);
2557 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2563 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2567 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2570 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2572 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2574 bnx2x_update_pfc_bmac1(params, vars);
2577 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2579 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2581 /* set cnt max size */
2582 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2584 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2586 /* configure safc */
2587 wb_data[0] = 0x1000200;
2589 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2592 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2593 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2601 static int bnx2x_bmac2_enable(struct link_params *params,
2602 struct link_vars *vars,
2605 struct bnx2x *bp = params->bp;
2606 u8 port = params->port;
2607 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2608 NIG_REG_INGRESS_BMAC0_MEM;
2611 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2615 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2618 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2621 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2627 wb_data[0] = ((params->mac_addr[2] << 24) |
2628 (params->mac_addr[3] << 16) |
2629 (params->mac_addr[4] << 8) |
2630 params->mac_addr[5]);
2631 wb_data[1] = ((params->mac_addr[0] << 8) |
2632 params->mac_addr[1]);
2633 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2638 /* Configure SAFC */
2639 wb_data[0] = 0x1000200;
2641 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2646 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2648 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2652 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2654 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2656 /* set cnt max size */
2657 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2659 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2661 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2663 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2664 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2666 if (wb_data[0] > 0) {
2667 DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2676 static int bnx2x_bmac_enable(struct link_params *params,
2677 struct link_vars *vars,
2681 u8 port = params->port;
2682 struct bnx2x *bp = params->bp;
2684 /* reset and unreset the BigMac */
2685 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2686 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2689 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2690 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2692 /* enable access for bmac registers */
2693 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2695 /* Enable BMAC according to BMAC type*/
2697 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2699 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2700 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2701 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2702 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2704 if ((params->feature_config_flags &
2705 FEATURE_CONFIG_PFC_ENABLED) ||
2706 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2708 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2709 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2710 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2711 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2712 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2713 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2715 vars->mac_type = MAC_TYPE_BMAC;
2719 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2721 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2722 NIG_REG_INGRESS_BMAC0_MEM;
2724 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2726 /* Only if the bmac is out of reset */
2727 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2728 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2731 if (CHIP_IS_E2(bp)) {
2732 /* Clear Rx Enable bit in BMAC_CONTROL register */
2733 REG_RD_DMAE(bp, bmac_addr +
2734 BIGMAC2_REGISTER_BMAC_CONTROL,
2736 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2737 REG_WR_DMAE(bp, bmac_addr +
2738 BIGMAC2_REGISTER_BMAC_CONTROL,
2741 /* Clear Rx Enable bit in BMAC_CONTROL register */
2742 REG_RD_DMAE(bp, bmac_addr +
2743 BIGMAC_REGISTER_BMAC_CONTROL,
2745 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2746 REG_WR_DMAE(bp, bmac_addr +
2747 BIGMAC_REGISTER_BMAC_CONTROL,
2754 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2757 struct bnx2x *bp = params->bp;
2758 u8 port = params->port;
2763 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2765 /* wait for init credit */
2766 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2767 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2768 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2770 while ((init_crd != crd) && count) {
2773 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2776 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2777 if (init_crd != crd) {
2778 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2783 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2784 line_speed == SPEED_10 ||
2785 line_speed == SPEED_100 ||
2786 line_speed == SPEED_1000 ||
2787 line_speed == SPEED_2500) {
2788 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2789 /* update threshold */
2790 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2791 /* update init credit */
2792 init_crd = 778; /* (800-18-4) */
2795 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2797 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2798 /* update threshold */
2799 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2800 /* update init credit */
2801 switch (line_speed) {
2803 init_crd = thresh + 553 - 22;
2806 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2811 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2812 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2813 line_speed, init_crd);
2815 /* probe the credit changes */
2816 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2818 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2821 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2826 * bnx2x_get_emac_base - retrive emac base address
2828 * @bp: driver handle
2829 * @mdc_mdio_access: access type
2832 * This function selects the MDC/MDIO access (through emac0 or
2833 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2834 * phy has a default access mode, which could also be overridden
2835 * by nvram configuration. This parameter, whether this is the
2836 * default phy configuration, or the nvram overrun
2837 * configuration, is passed here as mdc_mdio_access and selects
2838 * the emac_base for the CL45 read/writes operations
2840 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2841 u32 mdc_mdio_access, u8 port)
2844 switch (mdc_mdio_access) {
2845 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2847 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2848 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2849 emac_base = GRCBASE_EMAC1;
2851 emac_base = GRCBASE_EMAC0;
2853 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2854 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2855 emac_base = GRCBASE_EMAC0;
2857 emac_base = GRCBASE_EMAC1;
2859 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2860 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2862 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2863 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2872 /******************************************************************/
2873 /* CL22 access functions */
2874 /******************************************************************/
2875 static int bnx2x_cl22_write(struct bnx2x *bp,
2876 struct bnx2x_phy *phy,
2882 /* Switch to CL22 */
2883 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2884 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2885 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2888 tmp = ((phy->addr << 21) | (reg << 16) | val |
2889 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2890 EMAC_MDIO_COMM_START_BUSY);
2891 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2893 for (i = 0; i < 50; i++) {
2896 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2897 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2902 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2903 DP(NETIF_MSG_LINK, "write phy register failed\n");
2906 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2910 static int bnx2x_cl22_read(struct bnx2x *bp,
2911 struct bnx2x_phy *phy,
2912 u16 reg, u16 *ret_val)
2918 /* Switch to CL22 */
2919 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2920 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2921 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2924 val = ((phy->addr << 21) | (reg << 16) |
2925 EMAC_MDIO_COMM_COMMAND_READ_22 |
2926 EMAC_MDIO_COMM_START_BUSY);
2927 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2929 for (i = 0; i < 50; i++) {
2932 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2933 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2934 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2939 if (val & EMAC_MDIO_COMM_START_BUSY) {
2940 DP(NETIF_MSG_LINK, "read phy register failed\n");
2945 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2949 /******************************************************************/
2950 /* CL45 access functions */
2951 /******************************************************************/
2952 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2953 u8 devad, u16 reg, u16 *ret_val)
2960 val = ((phy->addr << 21) | (devad << 16) | reg |
2961 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2962 EMAC_MDIO_COMM_START_BUSY);
2963 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2965 for (i = 0; i < 50; i++) {
2968 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2969 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2974 if (val & EMAC_MDIO_COMM_START_BUSY) {
2975 DP(NETIF_MSG_LINK, "read phy register failed\n");
2976 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2981 val = ((phy->addr << 21) | (devad << 16) |
2982 EMAC_MDIO_COMM_COMMAND_READ_45 |
2983 EMAC_MDIO_COMM_START_BUSY);
2984 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2986 for (i = 0; i < 50; i++) {
2989 val = REG_RD(bp, phy->mdio_ctrl +
2990 EMAC_REG_EMAC_MDIO_COMM);
2991 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2992 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2996 if (val & EMAC_MDIO_COMM_START_BUSY) {
2997 DP(NETIF_MSG_LINK, "read phy register failed\n");
2998 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3003 /* Work around for E3 A0 */
3004 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3005 phy->flags ^= FLAGS_DUMMY_READ;
3006 if (phy->flags & FLAGS_DUMMY_READ) {
3008 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3015 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3016 u8 devad, u16 reg, u16 val)
3024 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3025 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3026 EMAC_MDIO_COMM_START_BUSY);
3027 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3029 for (i = 0; i < 50; i++) {
3032 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3033 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3038 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3039 DP(NETIF_MSG_LINK, "write phy register failed\n");
3040 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3045 tmp = ((phy->addr << 21) | (devad << 16) | val |
3046 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3047 EMAC_MDIO_COMM_START_BUSY);
3048 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3050 for (i = 0; i < 50; i++) {
3053 tmp = REG_RD(bp, phy->mdio_ctrl +
3054 EMAC_REG_EMAC_MDIO_COMM);
3055 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3060 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3061 DP(NETIF_MSG_LINK, "write phy register failed\n");
3062 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3066 /* Work around for E3 A0 */
3067 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3068 phy->flags ^= FLAGS_DUMMY_READ;
3069 if (phy->flags & FLAGS_DUMMY_READ) {
3071 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3079 /******************************************************************/
3080 /* BSC access functions from E3 */
3081 /******************************************************************/
3082 static void bnx2x_bsc_module_sel(struct link_params *params)
3085 u32 board_cfg, sfp_ctrl;
3086 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3087 struct bnx2x *bp = params->bp;
3088 u8 port = params->port;
3089 /* Read I2C output PINs */
3090 board_cfg = REG_RD(bp, params->shmem_base +
3091 offsetof(struct shmem_region,
3092 dev_info.shared_hw_config.board));
3093 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3094 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3095 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3097 /* Read I2C output value */
3098 sfp_ctrl = REG_RD(bp, params->shmem_base +
3099 offsetof(struct shmem_region,
3100 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3101 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3102 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3103 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3104 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3105 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3108 static int bnx2x_bsc_read(struct link_params *params,
3109 struct bnx2x_phy *phy,
3118 struct bnx2x *bp = params->bp;
3120 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3121 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3125 if (xfer_cnt > 16) {
3126 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3130 bnx2x_bsc_module_sel(params);
3132 xfer_cnt = 16 - lc_addr;
3134 /* enable the engine */
3135 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3136 val |= MCPR_IMC_COMMAND_ENABLE;
3137 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3139 /* program slave device ID */
3140 val = (sl_devid << 16) | sl_addr;
3141 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3143 /* start xfer with 0 byte to update the address pointer ???*/
3144 val = (MCPR_IMC_COMMAND_ENABLE) |
3145 (MCPR_IMC_COMMAND_WRITE_OP <<
3146 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3147 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3148 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3150 /* poll for completion */
3152 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3153 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3155 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3157 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3166 /* start xfer with read op */
3167 val = (MCPR_IMC_COMMAND_ENABLE) |
3168 (MCPR_IMC_COMMAND_READ_OP <<
3169 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3170 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3172 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3174 /* poll for completion */
3176 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3177 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3179 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3181 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3189 for (i = (lc_addr >> 2); i < 4; i++) {
3190 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3192 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3193 ((data_array[i] & 0x0000ff00) << 8) |
3194 ((data_array[i] & 0x00ff0000) >> 8) |
3195 ((data_array[i] & 0xff000000) >> 24);
3201 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3202 u8 devad, u16 reg, u16 or_val)
3205 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3206 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3209 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3210 u8 devad, u16 reg, u16 *ret_val)
3214 * Probe for the phy according to the given phy_addr, and execute
3215 * the read request on it
3217 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3218 if (params->phy[phy_index].addr == phy_addr) {
3219 return bnx2x_cl45_read(params->bp,
3220 ¶ms->phy[phy_index], devad,
3227 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3228 u8 devad, u16 reg, u16 val)
3232 * Probe for the phy according to the given phy_addr, and execute
3233 * the write request on it
3235 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236 if (params->phy[phy_index].addr == phy_addr) {
3237 return bnx2x_cl45_write(params->bp,
3238 ¶ms->phy[phy_index], devad,
3244 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3245 struct link_params *params)
3248 struct bnx2x *bp = params->bp;
3249 u32 path_swap, path_swap_ovr;
3253 port = params->port;
3255 if (bnx2x_is_4_port_mode(bp)) {
3256 u32 port_swap, port_swap_ovr;
3258 /*figure out path swap value */
3259 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3260 if (path_swap_ovr & 0x1)
3261 path_swap = (path_swap_ovr & 0x2);
3263 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3268 /*figure out port swap value */
3269 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3270 if (port_swap_ovr & 0x1)
3271 port_swap = (port_swap_ovr & 0x2);
3273 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3278 lane = (port<<1) + path;
3279 } else { /* two port mode - no port swap */
3281 /*figure out path swap value */
3283 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3284 if (path_swap_ovr & 0x1) {
3285 path_swap = (path_swap_ovr & 0x2);
3288 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3298 static void bnx2x_set_aer_mmd(struct link_params *params,
3299 struct bnx2x_phy *phy)
3302 u16 offset, aer_val;
3303 struct bnx2x *bp = params->bp;
3304 ser_lane = ((params->lane_config &
3305 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3306 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3308 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3309 (phy->addr + ser_lane) : 0;
3311 if (USES_WARPCORE(bp)) {
3312 aer_val = bnx2x_get_warpcore_lane(phy, params);
3314 * In Dual-lane mode, two lanes are joined together,
3315 * so in order to configure them, the AER broadcast method is
3317 * 0x200 is the broadcast address for lanes 0,1
3318 * 0x201 is the broadcast address for lanes 2,3
3320 if (phy->flags & FLAGS_WC_DUAL_MODE)
3321 aer_val = (aer_val >> 1) | 0x200;
3322 } else if (CHIP_IS_E2(bp))
3323 aer_val = 0x3800 + offset - 1;
3325 aer_val = 0x3800 + offset;
3326 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3327 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3328 MDIO_AER_BLOCK_AER_REG, aer_val);
3332 /******************************************************************/
3333 /* Internal phy section */
3334 /******************************************************************/
3336 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3338 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3342 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3344 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3347 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3350 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3354 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3356 val = SERDES_RESET_BITS << (port*16);
3358 /* reset and unreset the SerDes/XGXS */
3359 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3361 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3363 bnx2x_set_serdes_access(bp, port);
3365 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3366 DEFAULT_PHY_DEV_ADDR);
3369 static void bnx2x_xgxs_deassert(struct link_params *params)
3371 struct bnx2x *bp = params->bp;
3374 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3375 port = params->port;
3377 val = XGXS_RESET_BITS << (port*16);
3379 /* reset and unreset the SerDes/XGXS */
3380 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3382 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3384 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3385 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3386 params->phy[INT_PHY].def_md_devad);
3389 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3390 struct link_params *params, u16 *ieee_fc)
3392 struct bnx2x *bp = params->bp;
3393 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3395 * resolve pause mode and advertisement Please refer to Table
3396 * 28B-3 of the 802.3ab-1999 spec
3399 switch (phy->req_flow_ctrl) {
3400 case BNX2X_FLOW_CTRL_AUTO:
3401 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3402 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3408 case BNX2X_FLOW_CTRL_TX:
3409 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3412 case BNX2X_FLOW_CTRL_RX:
3413 case BNX2X_FLOW_CTRL_BOTH:
3414 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3417 case BNX2X_FLOW_CTRL_NONE:
3419 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3422 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3425 static void set_phy_vars(struct link_params *params,
3426 struct link_vars *vars)
3428 struct bnx2x *bp = params->bp;
3429 u8 actual_phy_idx, phy_index, link_cfg_idx;
3430 u8 phy_config_swapped = params->multi_phy_config &
3431 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3432 for (phy_index = INT_PHY; phy_index < params->num_phys;
3434 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3435 actual_phy_idx = phy_index;
3436 if (phy_config_swapped) {
3437 if (phy_index == EXT_PHY1)
3438 actual_phy_idx = EXT_PHY2;
3439 else if (phy_index == EXT_PHY2)
3440 actual_phy_idx = EXT_PHY1;
3442 params->phy[actual_phy_idx].req_flow_ctrl =
3443 params->req_flow_ctrl[link_cfg_idx];
3445 params->phy[actual_phy_idx].req_line_speed =
3446 params->req_line_speed[link_cfg_idx];
3448 params->phy[actual_phy_idx].speed_cap_mask =
3449 params->speed_cap_mask[link_cfg_idx];
3451 params->phy[actual_phy_idx].req_duplex =
3452 params->req_duplex[link_cfg_idx];
3454 if (params->req_line_speed[link_cfg_idx] ==
3456 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3458 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3459 " speed_cap_mask %x\n",
3460 params->phy[actual_phy_idx].req_flow_ctrl,
3461 params->phy[actual_phy_idx].req_line_speed,
3462 params->phy[actual_phy_idx].speed_cap_mask);
3466 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3467 struct bnx2x_phy *phy,
3468 struct link_vars *vars)
3471 struct bnx2x *bp = params->bp;
3472 /* read modify write pause advertizing */
3473 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3475 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3477 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3478 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3479 if ((vars->ieee_fc &
3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3481 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3482 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3484 if ((vars->ieee_fc &
3485 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3486 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3487 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3489 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3490 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3493 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3495 switch (pause_result) { /* ASYM P ASYM P */
3496 case 0xb: /* 1 0 1 1 */
3497 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3500 case 0xe: /* 1 1 1 0 */
3501 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3504 case 0x5: /* 0 1 0 1 */
3505 case 0x7: /* 0 1 1 1 */
3506 case 0xd: /* 1 1 0 1 */
3507 case 0xf: /* 1 1 1 1 */
3508 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3514 if (pause_result & (1<<0))
3515 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3516 if (pause_result & (1<<1))
3517 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3520 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3521 struct link_params *params,
3522 struct link_vars *vars)
3524 struct bnx2x *bp = params->bp;
3525 u16 ld_pause; /* local */
3526 u16 lp_pause; /* link partner */
3531 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3533 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3534 vars->flow_ctrl = phy->req_flow_ctrl;
3535 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3536 vars->flow_ctrl = params->req_fc_auto_adv;
3537 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3539 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3540 bnx2x_cl22_read(bp, phy,
3542 bnx2x_cl22_read(bp, phy,
3545 bnx2x_cl45_read(bp, phy,
3547 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3548 bnx2x_cl45_read(bp, phy,
3550 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3552 pause_result = (ld_pause &
3553 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3554 pause_result |= (lp_pause &
3555 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3556 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3558 bnx2x_pause_resolve(vars, pause_result);
3562 /******************************************************************/
3563 /* Warpcore section */
3564 /******************************************************************/
3565 /* The init_internal_warpcore should mirror the xgxs,
3566 * i.e. reset the lane (if needed), set aer for the
3567 * init configuration, and set/clear SGMII flag. Internal
3568 * phy init is done purely in phy_init stage.
3570 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3571 struct link_params *params,
3572 struct link_vars *vars) {
3573 u16 val16 = 0, lane, bam37 = 0;
3574 struct bnx2x *bp = params->bp;
3575 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3576 /* Check adding advertisement for 1G KX */
3577 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3578 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3579 (vars->line_speed == SPEED_1000)) {
3583 /* Enable CL37 1G Parallel Detect */
3584 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3585 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3586 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3587 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3588 (sd_digital | 0x1));
3590 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3592 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3593 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3594 (vars->line_speed == SPEED_10000)) {
3595 /* Check adding advertisement for 10G KR */
3597 /* Enable 10G Parallel Detect */
3598 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3599 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3601 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3604 /* Set Transmit PMD settings */
3605 lane = bnx2x_get_warpcore_lane(phy, params);
3606 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3607 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3608 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3609 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3610 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3611 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3612 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3614 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3615 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3617 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3618 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3621 /* Advertised speeds */
3622 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3623 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3625 /* Enable CL37 BAM */
3626 if (REG_RD(bp, params->shmem_base +
3627 offsetof(struct shmem_region, dev_info.
3628 port_hw_config[params->port].default_cfg)) &
3629 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3630 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3631 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3632 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3633 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3634 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3637 /* Advertise pause */
3638 bnx2x_ext_phy_set_pause(params, phy, vars);
3640 /* Enable Autoneg */
3641 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3642 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3644 /* Over 1G - AN local device user page 1 */
3645 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3646 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3649 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3651 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3652 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3655 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3656 struct link_params *params,
3657 struct link_vars *vars)
3659 struct bnx2x *bp = params->bp;
3662 /* Disable Autoneg */
3663 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3664 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3666 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3667 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3669 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3670 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3672 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3673 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3675 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3676 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3678 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3679 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3681 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3682 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3684 /* Disable CL36 PCS Tx */
3685 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3686 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3688 /* Double Wide Single Data Rate @ pll rate */
3689 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3692 /* Leave cl72 training enable, needed for KR */
3693 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3694 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3697 /* Leave CL72 enabled */
3698 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3699 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3701 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3702 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3705 /* Set speed via PMA/PMD register */
3706 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3707 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3709 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3710 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3712 /*Enable encoded forced speed */
3713 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3714 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3716 /* Turn TX scramble payload only the 64/66 scrambler */
3717 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3718 MDIO_WC_REG_TX66_CONTROL, 0x9);
3720 /* Turn RX scramble payload only the 64/66 scrambler */
3721 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3722 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3724 /* set and clear loopback to cause a reset to 64/66 decoder */
3725 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3727 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3728 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3732 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3733 struct link_params *params,
3736 struct bnx2x *bp = params->bp;
3737 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3738 /* Hold rxSeqStart */
3739 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3740 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3741 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3742 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3744 /* Hold tx_fifo_reset */
3745 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3746 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3747 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3748 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3750 /* Disable CL73 AN */
3751 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3753 /* Disable 100FX Enable and Auto-Detect */
3754 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3755 MDIO_WC_REG_FX100_CTRL1, &val);
3756 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3757 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3759 /* Disable 100FX Idle detect */
3760 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3761 MDIO_WC_REG_FX100_CTRL3, &val);
3762 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3765 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3766 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3767 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3768 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3769 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3771 /* Turn off auto-detect & fiber mode */
3772 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3773 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3774 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3778 /* Set filter_force_link, disable_false_link and parallel_detect */
3779 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3780 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3781 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3783 ((val | 0x0006) & 0xFFFE));
3786 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3787 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3789 misc1_val &= ~(0x1f);
3793 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3794 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3795 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3797 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3798 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3799 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3803 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3804 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3805 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3807 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3808 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3809 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3811 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3812 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3814 /* Set Transmit PMD settings */
3815 lane = bnx2x_get_warpcore_lane(phy, params);
3816 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817 MDIO_WC_REG_TX_FIR_TAP,
3818 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3819 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3823 /* Enable fiber mode, enable and invert sig_det */
3824 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3825 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3826 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3829 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3830 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3832 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3833 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3835 /* 10G XFI Full Duplex */
3836 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3839 /* Release tx_fifo_reset */
3840 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3842 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3843 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3845 /* Release rxSeqStart */
3846 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3847 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3848 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3852 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3853 struct bnx2x_phy *phy)
3855 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3858 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3859 struct bnx2x_phy *phy,
3862 /* Rx0 anaRxControl1G */
3863 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3864 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3866 /* Rx2 anaRxControl1G */
3867 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3868 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3870 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871 MDIO_WC_REG_RX66_SCW0, 0xE070);
3873 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3874 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3879 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880 MDIO_WC_REG_RX66_SCW3, 0x8090);
3882 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3883 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3885 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3886 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3888 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3889 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3891 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3894 /* Serdes Digital Misc1 */
3895 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3896 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3898 /* Serdes Digital4 Misc3 */
3899 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3902 /* Set Transmit PMD settings */
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_TX_FIR_TAP,
3905 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3906 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3907 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3908 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3909 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3910 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3911 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3912 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3913 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3916 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3917 struct link_params *params,
3920 struct bnx2x *bp = params->bp;
3921 u16 val16, digctrl_kx1, digctrl_kx2;
3924 lane = bnx2x_get_warpcore_lane(phy, params);
3926 /* Clear XFI clock comp in non-10G single lane mode. */
3927 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3928 MDIO_WC_REG_RX66_CONTROL, &val16);
3929 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3930 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3932 if (phy->req_line_speed == SPEED_AUTO_NEG) {
3934 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3935 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3936 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3939 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3941 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3942 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3944 switch (phy->req_line_speed) {
3954 DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3955 "\n", phy->req_line_speed);
3959 if (phy->req_duplex == DUPLEX_FULL)
3962 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3963 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3965 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3966 phy->req_line_speed);
3967 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3968 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3969 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
3972 /* SGMII Slave mode and disable signal detect */
3973 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3974 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3978 digctrl_kx1 &= 0xff4a;
3980 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3981 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3984 /* Turn off parallel detect */
3985 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3986 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3987 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3988 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3989 (digctrl_kx2 & ~(1<<2)));
3991 /* Re-enable parallel detect */
3992 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3993 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3994 (digctrl_kx2 | (1<<2)));
3996 /* Enable autodet */
3997 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3998 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3999 (digctrl_kx1 | 0x10));
4002 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4003 struct bnx2x_phy *phy,
4007 /* Take lane out of reset after configuration is finished */
4008 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4009 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4014 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015 MDIO_WC_REG_DIGITAL5_MISC6, val);
4016 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4021 /* Clear SFI/XFI link settings registers */
4022 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4023 struct link_params *params,
4026 struct bnx2x *bp = params->bp;
4029 /* Set XFI clock comp as default. */
4030 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4031 MDIO_WC_REG_RX66_CONTROL, &val16);
4032 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4033 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4035 bnx2x_warpcore_reset_lane(bp, phy, 1);
4036 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4037 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4038 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4039 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4041 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4042 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4043 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4045 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4047 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4049 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4051 lane = bnx2x_get_warpcore_lane(phy, params);
4052 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4053 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4054 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4055 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4056 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4058 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4060 bnx2x_warpcore_reset_lane(bp, phy, 0);
4063 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4065 u32 shmem_base, u8 port,
4066 u8 *gpio_num, u8 *gpio_port)
4071 if (CHIP_IS_E3(bp)) {
4072 cfg_pin = (REG_RD(bp, shmem_base +
4073 offsetof(struct shmem_region,
4074 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4075 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4076 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4079 * Should not happen. This function called upon interrupt
4080 * triggered by GPIO ( since EPIO can only generate interrupts
4082 * So if this function was called and none of the GPIOs was set,
4083 * it means the shit hit the fan.
4085 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4086 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4087 DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4088 "module detect indication\n",
4093 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4094 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4096 *gpio_num = MISC_REGISTERS_GPIO_3;
4099 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4103 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4104 struct link_params *params)
4106 struct bnx2x *bp = params->bp;
4107 u8 gpio_num, gpio_port;
4109 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4110 params->shmem_base, params->port,
4111 &gpio_num, &gpio_port) != 0)
4113 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4115 /* Call the handling function in case module is detected */
4122 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4123 struct link_params *params,
4124 struct link_vars *vars)
4126 struct bnx2x *bp = params->bp;
4129 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4130 serdes_net_if = (REG_RD(bp, params->shmem_base +
4131 offsetof(struct shmem_region, dev_info.
4132 port_hw_config[params->port].default_cfg)) &
4133 PORT_HW_CFG_NET_SERDES_IF_MASK);
4134 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4135 "serdes_net_if = 0x%x\n",
4136 vars->line_speed, serdes_net_if);
4137 bnx2x_set_aer_mmd(params, phy);
4139 vars->phy_flags |= PHY_XGXS_FLAG;
4140 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4141 (phy->req_line_speed &&
4142 ((phy->req_line_speed == SPEED_100) ||
4143 (phy->req_line_speed == SPEED_10)))) {
4144 vars->phy_flags |= PHY_SGMII_FLAG;
4145 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4146 bnx2x_warpcore_clear_regs(phy, params, lane);
4147 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4149 switch (serdes_net_if) {
4150 case PORT_HW_CFG_NET_SERDES_IF_KR:
4151 /* Enable KR Auto Neg */
4152 if (params->loopback_mode == LOOPBACK_NONE)
4153 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4155 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4156 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4160 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4161 bnx2x_warpcore_clear_regs(phy, params, lane);
4162 if (vars->line_speed == SPEED_10000) {
4163 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4164 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4166 if (SINGLE_MEDIA_DIRECT(params)) {
4167 DP(NETIF_MSG_LINK, "1G Fiber\n");
4170 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4173 bnx2x_warpcore_set_sgmii_speed(phy,
4180 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4182 bnx2x_warpcore_clear_regs(phy, params, lane);
4183 if (vars->line_speed == SPEED_10000) {
4184 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4185 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4186 } else if (vars->line_speed == SPEED_1000) {
4187 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4188 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4190 /* Issue Module detection */
4191 if (bnx2x_is_sfp_module_plugged(phy, params))
4192 bnx2x_sfp_module_detection(phy, params);
4195 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4196 if (vars->line_speed != SPEED_20000) {
4197 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4200 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4201 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4202 /* Issue Module detection */
4204 bnx2x_sfp_module_detection(phy, params);
4207 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4208 if (vars->line_speed != SPEED_20000) {
4209 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4212 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4213 bnx2x_warpcore_set_20G_KR2(bp, phy);
4217 DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4218 "0x%x\n", serdes_net_if);
4223 /* Take lane out of reset after configuration is finished */
4224 bnx2x_warpcore_reset_lane(bp, phy, 0);
4225 DP(NETIF_MSG_LINK, "Exit config init\n");
4228 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4229 struct bnx2x_phy *phy,
4232 struct bnx2x *bp = params->bp;
4234 u8 port = params->port;
4236 cfg_pin = REG_RD(bp, params->shmem_base +
4237 offsetof(struct shmem_region,
4238 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4239 PORT_HW_CFG_TX_LASER_MASK;
4240 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4241 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4242 /* For 20G, the expected pin to be used is 3 pins after the current */
4244 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4245 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4246 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4249 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4250 struct link_params *params)
4252 struct bnx2x *bp = params->bp;
4254 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4255 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4256 bnx2x_set_aer_mmd(params, phy);
4257 /* Global register */
4258 bnx2x_warpcore_reset_lane(bp, phy, 1);
4260 /* Clear loopback settings (if any) */
4262 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4263 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4264 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4268 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4269 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4270 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4271 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4273 /* Update those 1-copy registers */
4274 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4275 MDIO_AER_BLOCK_AER_REG, 0);
4276 /* Enable 1G MDIO (1-copy) */
4277 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4278 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4280 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4281 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4284 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4285 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4286 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4292 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4293 struct link_params *params)
4295 struct bnx2x *bp = params->bp;
4298 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4299 params->loopback_mode, phy->req_line_speed);
4301 if (phy->req_line_speed < SPEED_10000) {
4304 /* Update those 1-copy registers */
4305 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4306 MDIO_AER_BLOCK_AER_REG, 0);
4307 /* Enable 1G MDIO (1-copy) */
4308 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4309 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4311 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4312 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4314 /* Set 1G loopback based on lane (1-copy) */
4315 lane = bnx2x_get_warpcore_lane(phy, params);
4316 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4317 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4318 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4319 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4322 /* Switch back to 4-copy registers */
4323 bnx2x_set_aer_mmd(params, phy);
4324 /* Global loopback, not recommended. */
4325 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4326 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4327 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4328 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4332 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4333 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4334 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4335 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4338 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4339 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4340 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4341 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4346 void bnx2x_link_status_update(struct link_params *params,
4347 struct link_vars *vars)
4349 struct bnx2x *bp = params->bp;
4351 u8 port = params->port;
4352 u32 sync_offset, media_types;
4353 /* Update PHY configuration */
4354 set_phy_vars(params, vars);
4356 vars->link_status = REG_RD(bp, params->shmem_base +
4357 offsetof(struct shmem_region,
4358 port_mb[port].link_status));
4360 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4361 vars->phy_flags = PHY_XGXS_FLAG;
4362 if (vars->link_up) {
4363 DP(NETIF_MSG_LINK, "phy link up\n");
4365 vars->phy_link_up = 1;
4366 vars->duplex = DUPLEX_FULL;
4367 switch (vars->link_status &
4368 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4370 vars->duplex = DUPLEX_HALF;
4373 vars->line_speed = SPEED_10;
4377 vars->duplex = DUPLEX_HALF;
4381 vars->line_speed = SPEED_100;
4385 vars->duplex = DUPLEX_HALF;
4388 vars->line_speed = SPEED_1000;
4392 vars->duplex = DUPLEX_HALF;
4395 vars->line_speed = SPEED_2500;
4399 vars->line_speed = SPEED_10000;
4402 vars->line_speed = SPEED_20000;
4407 vars->flow_ctrl = 0;
4408 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4409 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4411 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4412 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4414 if (!vars->flow_ctrl)
4415 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4417 if (vars->line_speed &&
4418 ((vars->line_speed == SPEED_10) ||
4419 (vars->line_speed == SPEED_100))) {
4420 vars->phy_flags |= PHY_SGMII_FLAG;
4422 vars->phy_flags &= ~PHY_SGMII_FLAG;
4424 if (vars->line_speed &&
4425 USES_WARPCORE(bp) &&
4426 (vars->line_speed == SPEED_1000))
4427 vars->phy_flags |= PHY_SGMII_FLAG;
4428 /* anything 10 and over uses the bmac */
4429 link_10g_plus = (vars->line_speed >= SPEED_10000);
4431 if (link_10g_plus) {
4432 if (USES_WARPCORE(bp))
4433 vars->mac_type = MAC_TYPE_XMAC;
4435 vars->mac_type = MAC_TYPE_BMAC;
4437 if (USES_WARPCORE(bp))
4438 vars->mac_type = MAC_TYPE_UMAC;
4440 vars->mac_type = MAC_TYPE_EMAC;
4442 } else { /* link down */
4443 DP(NETIF_MSG_LINK, "phy link down\n");
4445 vars->phy_link_up = 0;
4447 vars->line_speed = 0;
4448 vars->duplex = DUPLEX_FULL;
4449 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4451 /* indicate no mac active */
4452 vars->mac_type = MAC_TYPE_NONE;
4455 /* Sync media type */
4456 sync_offset = params->shmem_base +
4457 offsetof(struct shmem_region,
4458 dev_info.port_hw_config[port].media_type);
4459 media_types = REG_RD(bp, sync_offset);
4461 params->phy[INT_PHY].media_type =
4462 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4463 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4464 params->phy[EXT_PHY1].media_type =
4465 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4466 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4467 params->phy[EXT_PHY2].media_type =
4468 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4469 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4470 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4472 /* Sync AEU offset */
4473 sync_offset = params->shmem_base +
4474 offsetof(struct shmem_region,
4475 dev_info.port_hw_config[port].aeu_int_mask);
4477 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4479 /* Sync PFC status */
4480 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4481 params->feature_config_flags |=
4482 FEATURE_CONFIG_PFC_ENABLED;
4484 params->feature_config_flags &=
4485 ~FEATURE_CONFIG_PFC_ENABLED;
4487 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4488 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4489 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4490 vars->line_speed, vars->duplex, vars->flow_ctrl);
4494 static void bnx2x_set_master_ln(struct link_params *params,
4495 struct bnx2x_phy *phy)
4497 struct bnx2x *bp = params->bp;
4498 u16 new_master_ln, ser_lane;
4499 ser_lane = ((params->lane_config &
4500 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4501 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4503 /* set the master_ln for AN */
4504 CL22_RD_OVER_CL45(bp, phy,
4505 MDIO_REG_BANK_XGXS_BLOCK2,
4506 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4509 CL22_WR_OVER_CL45(bp, phy,
4510 MDIO_REG_BANK_XGXS_BLOCK2 ,
4511 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4512 (new_master_ln | ser_lane));
4515 static int bnx2x_reset_unicore(struct link_params *params,
4516 struct bnx2x_phy *phy,
4519 struct bnx2x *bp = params->bp;
4522 CL22_RD_OVER_CL45(bp, phy,
4523 MDIO_REG_BANK_COMBO_IEEE0,
4524 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4526 /* reset the unicore */
4527 CL22_WR_OVER_CL45(bp, phy,
4528 MDIO_REG_BANK_COMBO_IEEE0,
4529 MDIO_COMBO_IEEE0_MII_CONTROL,
4531 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4533 bnx2x_set_serdes_access(bp, params->port);
4535 /* wait for the reset to self clear */
4536 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4539 /* the reset erased the previous bank value */
4540 CL22_RD_OVER_CL45(bp, phy,
4541 MDIO_REG_BANK_COMBO_IEEE0,
4542 MDIO_COMBO_IEEE0_MII_CONTROL,
4545 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4551 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4554 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4559 static void bnx2x_set_swap_lanes(struct link_params *params,
4560 struct bnx2x_phy *phy)
4562 struct bnx2x *bp = params->bp;
4564 * Each two bits represents a lane number:
4565 * No swap is 0123 => 0x1b no need to enable the swap
4567 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4569 ser_lane = ((params->lane_config &
4570 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4571 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4572 rx_lane_swap = ((params->lane_config &
4573 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4574 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4575 tx_lane_swap = ((params->lane_config &
4576 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4577 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4579 if (rx_lane_swap != 0x1b) {
4580 CL22_WR_OVER_CL45(bp, phy,
4581 MDIO_REG_BANK_XGXS_BLOCK2,
4582 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4584 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4585 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4587 CL22_WR_OVER_CL45(bp, phy,
4588 MDIO_REG_BANK_XGXS_BLOCK2,
4589 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4592 if (tx_lane_swap != 0x1b) {
4593 CL22_WR_OVER_CL45(bp, phy,
4594 MDIO_REG_BANK_XGXS_BLOCK2,
4595 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4597 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4599 CL22_WR_OVER_CL45(bp, phy,
4600 MDIO_REG_BANK_XGXS_BLOCK2,
4601 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4605 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4606 struct link_params *params)
4608 struct bnx2x *bp = params->bp;
4610 CL22_RD_OVER_CL45(bp, phy,
4611 MDIO_REG_BANK_SERDES_DIGITAL,
4612 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4614 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4615 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4617 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4618 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4619 phy->speed_cap_mask, control2);
4620 CL22_WR_OVER_CL45(bp, phy,
4621 MDIO_REG_BANK_SERDES_DIGITAL,
4622 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4625 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4626 (phy->speed_cap_mask &
4627 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4628 DP(NETIF_MSG_LINK, "XGXS\n");
4630 CL22_WR_OVER_CL45(bp, phy,
4631 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4632 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4633 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4635 CL22_RD_OVER_CL45(bp, phy,
4636 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4637 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4642 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4644 CL22_WR_OVER_CL45(bp, phy,
4645 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4646 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4649 /* Disable parallel detection of HiG */
4650 CL22_WR_OVER_CL45(bp, phy,
4651 MDIO_REG_BANK_XGXS_BLOCK2,
4652 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4653 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4654 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4658 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4659 struct link_params *params,
4660 struct link_vars *vars,
4663 struct bnx2x *bp = params->bp;
4667 CL22_RD_OVER_CL45(bp, phy,
4668 MDIO_REG_BANK_COMBO_IEEE0,
4669 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4671 /* CL37 Autoneg Enabled */
4672 if (vars->line_speed == SPEED_AUTO_NEG)
4673 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4674 else /* CL37 Autoneg Disabled */
4675 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4676 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4678 CL22_WR_OVER_CL45(bp, phy,
4679 MDIO_REG_BANK_COMBO_IEEE0,
4680 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4682 /* Enable/Disable Autodetection */
4684 CL22_RD_OVER_CL45(bp, phy,
4685 MDIO_REG_BANK_SERDES_DIGITAL,
4686 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4687 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4688 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4689 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4690 if (vars->line_speed == SPEED_AUTO_NEG)
4691 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4693 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4695 CL22_WR_OVER_CL45(bp, phy,
4696 MDIO_REG_BANK_SERDES_DIGITAL,
4697 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4699 /* Enable TetonII and BAM autoneg */
4700 CL22_RD_OVER_CL45(bp, phy,
4701 MDIO_REG_BANK_BAM_NEXT_PAGE,
4702 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4704 if (vars->line_speed == SPEED_AUTO_NEG) {
4705 /* Enable BAM aneg Mode and TetonII aneg Mode */
4706 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4707 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4709 /* TetonII and BAM Autoneg Disabled */
4710 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4711 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4713 CL22_WR_OVER_CL45(bp, phy,
4714 MDIO_REG_BANK_BAM_NEXT_PAGE,
4715 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4719 /* Enable Cl73 FSM status bits */
4720 CL22_WR_OVER_CL45(bp, phy,
4721 MDIO_REG_BANK_CL73_USERB0,
4722 MDIO_CL73_USERB0_CL73_UCTRL,
4725 /* Enable BAM Station Manager*/
4726 CL22_WR_OVER_CL45(bp, phy,
4727 MDIO_REG_BANK_CL73_USERB0,
4728 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4729 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4730 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4731 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4733 /* Advertise CL73 link speeds */
4734 CL22_RD_OVER_CL45(bp, phy,
4735 MDIO_REG_BANK_CL73_IEEEB1,
4736 MDIO_CL73_IEEEB1_AN_ADV2,
4738 if (phy->speed_cap_mask &
4739 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4740 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4741 if (phy->speed_cap_mask &
4742 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4743 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4745 CL22_WR_OVER_CL45(bp, phy,
4746 MDIO_REG_BANK_CL73_IEEEB1,
4747 MDIO_CL73_IEEEB1_AN_ADV2,
4750 /* CL73 Autoneg Enabled */
4751 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4753 } else /* CL73 Autoneg Disabled */
4756 CL22_WR_OVER_CL45(bp, phy,
4757 MDIO_REG_BANK_CL73_IEEEB0,
4758 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4761 /* program SerDes, forced speed */
4762 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4763 struct link_params *params,
4764 struct link_vars *vars)
4766 struct bnx2x *bp = params->bp;
4769 /* program duplex, disable autoneg and sgmii*/
4770 CL22_RD_OVER_CL45(bp, phy,
4771 MDIO_REG_BANK_COMBO_IEEE0,
4772 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4773 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4774 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4775 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4776 if (phy->req_duplex == DUPLEX_FULL)
4777 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4778 CL22_WR_OVER_CL45(bp, phy,
4779 MDIO_REG_BANK_COMBO_IEEE0,
4780 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4784 * - needed only if the speed is greater than 1G (2.5G or 10G)
4786 CL22_RD_OVER_CL45(bp, phy,
4787 MDIO_REG_BANK_SERDES_DIGITAL,
4788 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4789 /* clearing the speed value before setting the right speed */
4790 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4792 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4793 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4795 if (!((vars->line_speed == SPEED_1000) ||
4796 (vars->line_speed == SPEED_100) ||
4797 (vars->line_speed == SPEED_10))) {
4799 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4800 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4801 if (vars->line_speed == SPEED_10000)
4803 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4806 CL22_WR_OVER_CL45(bp, phy,
4807 MDIO_REG_BANK_SERDES_DIGITAL,
4808 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4812 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4813 struct link_params *params)
4815 struct bnx2x *bp = params->bp;
4818 /* configure the 48 bits for BAM AN */
4820 /* set extended capabilities */
4821 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4822 val |= MDIO_OVER_1G_UP1_2_5G;
4823 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4824 val |= MDIO_OVER_1G_UP1_10G;
4825 CL22_WR_OVER_CL45(bp, phy,
4826 MDIO_REG_BANK_OVER_1G,
4827 MDIO_OVER_1G_UP1, val);
4829 CL22_WR_OVER_CL45(bp, phy,
4830 MDIO_REG_BANK_OVER_1G,
4831 MDIO_OVER_1G_UP3, 0x400);
4834 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4835 struct link_params *params,
4838 struct bnx2x *bp = params->bp;
4840 /* for AN, we are always publishing full duplex */
4842 CL22_WR_OVER_CL45(bp, phy,
4843 MDIO_REG_BANK_COMBO_IEEE0,
4844 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4845 CL22_RD_OVER_CL45(bp, phy,
4846 MDIO_REG_BANK_CL73_IEEEB1,
4847 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4848 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4849 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4850 CL22_WR_OVER_CL45(bp, phy,
4851 MDIO_REG_BANK_CL73_IEEEB1,
4852 MDIO_CL73_IEEEB1_AN_ADV1, val);
4855 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4856 struct link_params *params,
4859 struct bnx2x *bp = params->bp;
4862 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4863 /* Enable and restart BAM/CL37 aneg */
4866 CL22_RD_OVER_CL45(bp, phy,
4867 MDIO_REG_BANK_CL73_IEEEB0,
4868 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4871 CL22_WR_OVER_CL45(bp, phy,
4872 MDIO_REG_BANK_CL73_IEEEB0,
4873 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4875 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4876 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4879 CL22_RD_OVER_CL45(bp, phy,
4880 MDIO_REG_BANK_COMBO_IEEE0,
4881 MDIO_COMBO_IEEE0_MII_CONTROL,
4884 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4886 CL22_WR_OVER_CL45(bp, phy,
4887 MDIO_REG_BANK_COMBO_IEEE0,
4888 MDIO_COMBO_IEEE0_MII_CONTROL,
4890 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4891 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4895 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4896 struct link_params *params,
4897 struct link_vars *vars)
4899 struct bnx2x *bp = params->bp;
4902 /* in SGMII mode, the unicore is always slave */
4904 CL22_RD_OVER_CL45(bp, phy,
4905 MDIO_REG_BANK_SERDES_DIGITAL,
4906 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4908 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4909 /* set sgmii mode (and not fiber) */
4910 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4911 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4912 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4913 CL22_WR_OVER_CL45(bp, phy,
4914 MDIO_REG_BANK_SERDES_DIGITAL,
4915 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4918 /* if forced speed */
4919 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4920 /* set speed, disable autoneg */
4923 CL22_RD_OVER_CL45(bp, phy,
4924 MDIO_REG_BANK_COMBO_IEEE0,
4925 MDIO_COMBO_IEEE0_MII_CONTROL,
4927 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4928 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4929 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4931 switch (vars->line_speed) {
4934 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4938 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4941 /* there is nothing to set for 10M */
4944 /* invalid speed for SGMII */
4945 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4950 /* setting the full duplex */
4951 if (phy->req_duplex == DUPLEX_FULL)
4953 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4954 CL22_WR_OVER_CL45(bp, phy,
4955 MDIO_REG_BANK_COMBO_IEEE0,
4956 MDIO_COMBO_IEEE0_MII_CONTROL,
4959 } else { /* AN mode */
4960 /* enable and restart AN */
4961 bnx2x_restart_autoneg(phy, params, 0);
4970 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4971 struct link_params *params)
4973 struct bnx2x *bp = params->bp;
4974 u16 pd_10g, status2_1000x;
4975 if (phy->req_line_speed != SPEED_AUTO_NEG)
4977 CL22_RD_OVER_CL45(bp, phy,
4978 MDIO_REG_BANK_SERDES_DIGITAL,
4979 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4981 CL22_RD_OVER_CL45(bp, phy,
4982 MDIO_REG_BANK_SERDES_DIGITAL,
4983 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4985 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4986 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4991 CL22_RD_OVER_CL45(bp, phy,
4992 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4993 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4996 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4997 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5004 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5005 struct link_params *params,
5006 struct link_vars *vars,
5009 struct bnx2x *bp = params->bp;
5010 u16 ld_pause; /* local driver */
5011 u16 lp_pause; /* link partner */
5014 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5016 /* resolve from gp_status in case of AN complete and not sgmii */
5017 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5018 vars->flow_ctrl = phy->req_flow_ctrl;
5019 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5020 vars->flow_ctrl = params->req_fc_auto_adv;
5021 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5022 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5023 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5024 vars->flow_ctrl = params->req_fc_auto_adv;
5028 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5029 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5030 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5031 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5033 CL22_RD_OVER_CL45(bp, phy,
5034 MDIO_REG_BANK_CL73_IEEEB1,
5035 MDIO_CL73_IEEEB1_AN_ADV1,
5037 CL22_RD_OVER_CL45(bp, phy,
5038 MDIO_REG_BANK_CL73_IEEEB1,
5039 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5041 pause_result = (ld_pause &
5042 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5044 pause_result |= (lp_pause &
5045 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5047 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5050 CL22_RD_OVER_CL45(bp, phy,
5051 MDIO_REG_BANK_COMBO_IEEE0,
5052 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5054 CL22_RD_OVER_CL45(bp, phy,
5055 MDIO_REG_BANK_COMBO_IEEE0,
5056 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5058 pause_result = (ld_pause &
5059 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5060 pause_result |= (lp_pause &
5061 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5062 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5065 bnx2x_pause_resolve(vars, pause_result);
5067 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5070 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5071 struct link_params *params)
5073 struct bnx2x *bp = params->bp;
5074 u16 rx_status, ustat_val, cl37_fsm_received;
5075 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5076 /* Step 1: Make sure signal is detected */
5077 CL22_RD_OVER_CL45(bp, phy,
5081 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5082 (MDIO_RX0_RX_STATUS_SIGDET)) {
5083 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5084 "rx_status(0x80b0) = 0x%x\n", rx_status);
5085 CL22_WR_OVER_CL45(bp, phy,
5086 MDIO_REG_BANK_CL73_IEEEB0,
5087 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5088 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5091 /* Step 2: Check CL73 state machine */
5092 CL22_RD_OVER_CL45(bp, phy,
5093 MDIO_REG_BANK_CL73_USERB0,
5094 MDIO_CL73_USERB0_CL73_USTAT1,
5097 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5098 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5099 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5100 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5101 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5102 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5106 * Step 3: Check CL37 Message Pages received to indicate LP
5107 * supports only CL37
5109 CL22_RD_OVER_CL45(bp, phy,
5110 MDIO_REG_BANK_REMOTE_PHY,
5111 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5112 &cl37_fsm_received);
5113 if ((cl37_fsm_received &
5114 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5115 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5116 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5117 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5118 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5119 "misc_rx_status(0x8330) = 0x%x\n",
5124 * The combined cl37/cl73 fsm state information indicating that
5125 * we are connected to a device which does not support cl73, but
5126 * does support cl37 BAM. In this case we disable cl73 and
5127 * restart cl37 auto-neg
5131 CL22_WR_OVER_CL45(bp, phy,
5132 MDIO_REG_BANK_CL73_IEEEB0,
5133 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5135 /* Restart CL37 autoneg */
5136 bnx2x_restart_autoneg(phy, params, 0);
5137 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5140 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5141 struct link_params *params,
5142 struct link_vars *vars,
5145 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5146 vars->link_status |=
5147 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5149 if (bnx2x_direct_parallel_detect_used(phy, params))
5150 vars->link_status |=
5151 LINK_STATUS_PARALLEL_DETECTION_USED;
5153 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5154 struct link_params *params,
5155 struct link_vars *vars,
5160 struct bnx2x *bp = params->bp;
5161 if (phy->req_line_speed == SPEED_AUTO_NEG)
5162 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5164 DP(NETIF_MSG_LINK, "phy link up\n");
5166 vars->phy_link_up = 1;
5167 vars->link_status |= LINK_STATUS_LINK_UP;
5169 switch (speed_mask) {
5171 vars->line_speed = SPEED_10;
5172 if (vars->duplex == DUPLEX_FULL)
5173 vars->link_status |= LINK_10TFD;
5175 vars->link_status |= LINK_10THD;
5178 case GP_STATUS_100M:
5179 vars->line_speed = SPEED_100;
5180 if (vars->duplex == DUPLEX_FULL)
5181 vars->link_status |= LINK_100TXFD;
5183 vars->link_status |= LINK_100TXHD;
5187 case GP_STATUS_1G_KX:
5188 vars->line_speed = SPEED_1000;
5189 if (vars->duplex == DUPLEX_FULL)
5190 vars->link_status |= LINK_1000TFD;
5192 vars->link_status |= LINK_1000THD;
5195 case GP_STATUS_2_5G:
5196 vars->line_speed = SPEED_2500;
5197 if (vars->duplex == DUPLEX_FULL)
5198 vars->link_status |= LINK_2500TFD;
5200 vars->link_status |= LINK_2500THD;
5206 "link speed unsupported gp_status 0x%x\n",
5210 case GP_STATUS_10G_KX4:
5211 case GP_STATUS_10G_HIG:
5212 case GP_STATUS_10G_CX4:
5213 case GP_STATUS_10G_KR:
5214 case GP_STATUS_10G_SFI:
5215 case GP_STATUS_10G_XFI:
5216 vars->line_speed = SPEED_10000;
5217 vars->link_status |= LINK_10GTFD;
5219 case GP_STATUS_20G_DXGXS:
5220 vars->line_speed = SPEED_20000;
5221 vars->link_status |= LINK_20GTFD;
5225 "link speed unsupported gp_status 0x%x\n",
5229 } else { /* link_down */
5230 DP(NETIF_MSG_LINK, "phy link down\n");
5232 vars->phy_link_up = 0;
5234 vars->duplex = DUPLEX_FULL;
5235 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5236 vars->mac_type = MAC_TYPE_NONE;
5238 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5239 vars->phy_link_up, vars->line_speed);
5243 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5244 struct link_params *params,
5245 struct link_vars *vars)
5248 struct bnx2x *bp = params->bp;
5250 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5253 /* Read gp_status */
5254 CL22_RD_OVER_CL45(bp, phy,
5255 MDIO_REG_BANK_GP_STATUS,
5256 MDIO_GP_STATUS_TOP_AN_STATUS1,
5258 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5259 duplex = DUPLEX_FULL;
5260 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5262 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5263 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5264 gp_status, link_up, speed_mask);
5265 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5270 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5271 if (SINGLE_MEDIA_DIRECT(params)) {
5272 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5273 if (phy->req_line_speed == SPEED_AUTO_NEG)
5274 bnx2x_xgxs_an_resolve(phy, params, vars,
5277 } else { /* link_down */
5278 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5279 SINGLE_MEDIA_DIRECT(params)) {
5280 /* Check signal is detected */
5281 bnx2x_check_fallback_to_cl37(phy, params);
5285 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5286 vars->duplex, vars->flow_ctrl, vars->link_status);
5290 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5291 struct link_params *params,
5292 struct link_vars *vars)
5295 struct bnx2x *bp = params->bp;
5298 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5300 lane = bnx2x_get_warpcore_lane(phy, params);
5301 /* Read gp_status */
5302 if (phy->req_line_speed > SPEED_10000) {
5304 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5306 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5308 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5309 temp_link_up, link_up);
5312 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5314 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5315 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5316 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5317 /* Check for either KR or generic link up. */
5318 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5319 ((gp_status1 >> 12) & 0xf);
5320 link_up = gp_status1 & (1 << lane);
5321 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5323 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5324 /* Check Autoneg complete */
5325 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5326 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5328 if (gp_status4 & ((1<<12)<<lane))
5329 vars->link_status |=
5330 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5332 /* Check parallel detect used */
5333 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5334 MDIO_WC_REG_PAR_DET_10G_STATUS,
5337 vars->link_status |=
5338 LINK_STATUS_PARALLEL_DETECTION_USED;
5340 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5345 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5346 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5348 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5349 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5351 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5353 if ((lane & 1) == 0)
5358 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5361 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5362 vars->duplex, vars->flow_ctrl, vars->link_status);
5365 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5367 struct bnx2x *bp = params->bp;
5368 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5374 CL22_RD_OVER_CL45(bp, phy,
5375 MDIO_REG_BANK_OVER_1G,
5376 MDIO_OVER_1G_LP_UP2, &lp_up2);
5378 /* bits [10:7] at lp_up2, positioned at [15:12] */
5379 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5380 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5381 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5386 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5387 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5388 CL22_RD_OVER_CL45(bp, phy,
5390 MDIO_TX0_TX_DRIVER, &tx_driver);
5392 /* replace tx_driver bits [15:12] */
5394 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5395 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5396 tx_driver |= lp_up2;
5397 CL22_WR_OVER_CL45(bp, phy,
5399 MDIO_TX0_TX_DRIVER, tx_driver);
5404 static int bnx2x_emac_program(struct link_params *params,
5405 struct link_vars *vars)
5407 struct bnx2x *bp = params->bp;
5408 u8 port = params->port;
5411 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5412 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5414 (EMAC_MODE_25G_MODE |
5415 EMAC_MODE_PORT_MII_10M |
5416 EMAC_MODE_HALF_DUPLEX));
5417 switch (vars->line_speed) {
5419 mode |= EMAC_MODE_PORT_MII_10M;
5423 mode |= EMAC_MODE_PORT_MII;
5427 mode |= EMAC_MODE_PORT_GMII;
5431 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5435 /* 10G not valid for EMAC */
5436 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5441 if (vars->duplex == DUPLEX_HALF)
5442 mode |= EMAC_MODE_HALF_DUPLEX;
5444 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5447 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5451 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5452 struct link_params *params)
5456 struct bnx2x *bp = params->bp;
5458 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5459 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5460 CL22_WR_OVER_CL45(bp, phy,
5462 MDIO_RX0_RX_EQ_BOOST,
5463 phy->rx_preemphasis[i]);
5466 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5467 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5468 CL22_WR_OVER_CL45(bp, phy,
5471 phy->tx_preemphasis[i]);
5475 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5476 struct link_params *params,
5477 struct link_vars *vars)
5479 struct bnx2x *bp = params->bp;
5480 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5481 (params->loopback_mode == LOOPBACK_XGXS));
5482 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5483 if (SINGLE_MEDIA_DIRECT(params) &&
5484 (params->feature_config_flags &
5485 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5486 bnx2x_set_preemphasis(phy, params);
5488 /* forced speed requested? */
5489 if (vars->line_speed != SPEED_AUTO_NEG ||
5490 (SINGLE_MEDIA_DIRECT(params) &&
5491 params->loopback_mode == LOOPBACK_EXT)) {
5492 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5494 /* disable autoneg */
5495 bnx2x_set_autoneg(phy, params, vars, 0);
5497 /* program speed and duplex */
5498 bnx2x_program_serdes(phy, params, vars);
5500 } else { /* AN_mode */
5501 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5504 bnx2x_set_brcm_cl37_advertisement(phy, params);
5506 /* program duplex & pause advertisement (for aneg) */
5507 bnx2x_set_ieee_aneg_advertisement(phy, params,
5510 /* enable autoneg */
5511 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5513 /* enable and restart AN */
5514 bnx2x_restart_autoneg(phy, params, enable_cl73);
5517 } else { /* SGMII mode */
5518 DP(NETIF_MSG_LINK, "SGMII\n");
5520 bnx2x_initialize_sgmii_process(phy, params, vars);
5524 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5525 struct link_params *params,
5526 struct link_vars *vars)
5529 vars->phy_flags |= PHY_XGXS_FLAG;
5530 if ((phy->req_line_speed &&
5531 ((phy->req_line_speed == SPEED_100) ||
5532 (phy->req_line_speed == SPEED_10))) ||
5533 (!phy->req_line_speed &&
5534 (phy->speed_cap_mask >=
5535 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5536 (phy->speed_cap_mask <
5537 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5538 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5539 vars->phy_flags |= PHY_SGMII_FLAG;
5541 vars->phy_flags &= ~PHY_SGMII_FLAG;
5543 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5544 bnx2x_set_aer_mmd(params, phy);
5545 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5546 bnx2x_set_master_ln(params, phy);
5548 rc = bnx2x_reset_unicore(params, phy, 0);
5549 /* reset the SerDes and wait for reset bit return low */
5553 bnx2x_set_aer_mmd(params, phy);
5554 /* setting the masterLn_def again after the reset */
5555 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5556 bnx2x_set_master_ln(params, phy);
5557 bnx2x_set_swap_lanes(params, phy);
5563 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5564 struct bnx2x_phy *phy,
5565 struct link_params *params)
5568 /* Wait for soft reset to get cleared up to 1 sec */
5569 for (cnt = 0; cnt < 1000; cnt++) {
5570 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5571 bnx2x_cl22_read(bp, phy,
5572 MDIO_PMA_REG_CTRL, &ctrl);
5574 bnx2x_cl45_read(bp, phy,
5576 MDIO_PMA_REG_CTRL, &ctrl);
5577 if (!(ctrl & (1<<15)))
5583 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5586 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5590 static void bnx2x_link_int_enable(struct link_params *params)
5592 u8 port = params->port;
5594 struct bnx2x *bp = params->bp;
5596 /* Setting the status to report on link up for either XGXS or SerDes */
5597 if (CHIP_IS_E3(bp)) {
5598 mask = NIG_MASK_XGXS0_LINK_STATUS;
5599 if (!(SINGLE_MEDIA_DIRECT(params)))
5600 mask |= NIG_MASK_MI_INT;
5601 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5602 mask = (NIG_MASK_XGXS0_LINK10G |
5603 NIG_MASK_XGXS0_LINK_STATUS);
5604 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5605 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5606 params->phy[INT_PHY].type !=
5607 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5608 mask |= NIG_MASK_MI_INT;
5609 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5612 } else { /* SerDes */
5613 mask = NIG_MASK_SERDES0_LINK_STATUS;
5614 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5615 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5616 params->phy[INT_PHY].type !=
5617 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5618 mask |= NIG_MASK_MI_INT;
5619 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5623 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5626 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5627 (params->switch_cfg == SWITCH_CFG_10G),
5628 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5629 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5630 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5631 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5632 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5633 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5634 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5635 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5638 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5641 u32 latch_status = 0;
5644 * Disable the MI INT ( external phy int ) by writing 1 to the
5645 * status register. Link down indication is high-active-signal,
5646 * so in this case we need to write the status to clear the XOR
5648 /* Read Latched signals */
5649 latch_status = REG_RD(bp,
5650 NIG_REG_LATCH_STATUS_0 + port*8);
5651 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5652 /* Handle only those with latched-signal=up.*/
5655 NIG_REG_STATUS_INTERRUPT_PORT0
5657 NIG_STATUS_EMAC0_MI_INT);
5660 NIG_REG_STATUS_INTERRUPT_PORT0
5662 NIG_STATUS_EMAC0_MI_INT);
5664 if (latch_status & 1) {
5666 /* For all latched-signal=up : Re-Arm Latch signals */
5667 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5668 (latch_status & 0xfffe) | (latch_status & 1));
5670 /* For all latched-signal=up,Write original_signal to status */
5673 static void bnx2x_link_int_ack(struct link_params *params,
5674 struct link_vars *vars, u8 is_10g_plus)
5676 struct bnx2x *bp = params->bp;
5677 u8 port = params->port;
5680 * First reset all status we assume only one line will be
5683 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5684 (NIG_STATUS_XGXS0_LINK10G |
5685 NIG_STATUS_XGXS0_LINK_STATUS |
5686 NIG_STATUS_SERDES0_LINK_STATUS));
5687 if (vars->phy_link_up) {
5688 if (USES_WARPCORE(bp))
5689 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5692 mask = NIG_STATUS_XGXS0_LINK10G;
5693 else if (params->switch_cfg == SWITCH_CFG_10G) {
5695 * Disable the link interrupt by writing 1 to
5696 * the relevant lane in the status register
5699 ((params->lane_config &
5700 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5701 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5702 mask = ((1 << ser_lane) <<
5703 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5705 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5707 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5710 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5715 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5718 u32 mask = 0xf0000000;
5721 u8 remove_leading_zeros = 1;
5723 /* Need more than 10chars for this format */
5731 digit = ((num & mask) >> shift);
5732 if (digit == 0 && remove_leading_zeros) {
5735 } else if (digit < 0xa)
5736 *str_ptr = digit + '0';
5738 *str_ptr = digit - 0xa + 'a';
5739 remove_leading_zeros = 0;
5747 remove_leading_zeros = 1;
5754 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5761 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5762 u8 *version, u16 len)
5767 u8 *ver_p = version;
5768 u16 remain_len = len;
5769 if (version == NULL || params == NULL)
5773 /* Extract first external phy*/
5775 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5777 if (params->phy[EXT_PHY1].format_fw_ver) {
5778 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5781 ver_p += (len - remain_len);
5783 if ((params->num_phys == MAX_PHYS) &&
5784 (params->phy[EXT_PHY2].ver_addr != 0)) {
5785 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5786 if (params->phy[EXT_PHY2].format_fw_ver) {
5790 status |= params->phy[EXT_PHY2].format_fw_ver(
5794 ver_p = version + (len - remain_len);
5801 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5802 struct link_params *params)
5804 u8 port = params->port;
5805 struct bnx2x *bp = params->bp;
5807 if (phy->req_line_speed != SPEED_1000) {
5810 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5812 if (!CHIP_IS_E3(bp)) {
5813 /* change the uni_phy_addr in the nig */
5814 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5817 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5821 bnx2x_cl45_write(bp, phy,
5823 (MDIO_REG_BANK_AER_BLOCK +
5824 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5827 bnx2x_cl45_write(bp, phy,
5829 (MDIO_REG_BANK_CL73_IEEEB0 +
5830 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5833 /* set aer mmd back */
5834 bnx2x_set_aer_mmd(params, phy);
5836 if (!CHIP_IS_E3(bp)) {
5838 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5843 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5844 bnx2x_cl45_read(bp, phy, 5,
5845 (MDIO_REG_BANK_COMBO_IEEE0 +
5846 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5848 bnx2x_cl45_write(bp, phy, 5,
5849 (MDIO_REG_BANK_COMBO_IEEE0 +
5850 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5852 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5856 int bnx2x_set_led(struct link_params *params,
5857 struct link_vars *vars, u8 mode, u32 speed)
5859 u8 port = params->port;
5860 u16 hw_led_mode = params->hw_led_mode;
5864 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5865 struct bnx2x *bp = params->bp;
5866 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5867 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5868 speed, hw_led_mode);
5870 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5871 if (params->phy[phy_idx].set_link_led) {
5872 params->phy[phy_idx].set_link_led(
5873 ¶ms->phy[phy_idx], params, mode);
5878 case LED_MODE_FRONT_PANEL_OFF:
5880 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5881 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5882 SHARED_HW_CFG_LED_MAC1);
5884 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5885 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5890 * For all other phys, OPER mode is same as ON, so in case
5891 * link is down, do nothing
5896 if (((params->phy[EXT_PHY1].type ==
5897 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5898 (params->phy[EXT_PHY1].type ==
5899 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5900 CHIP_IS_E2(bp) && params->num_phys == 2) {
5902 * This is a work-around for E2+8727 Configurations
5904 if (mode == LED_MODE_ON ||
5905 speed == SPEED_10000){
5906 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5907 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5909 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5910 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5911 (tmp | EMAC_LED_OVERRIDE));
5914 } else if (SINGLE_MEDIA_DIRECT(params) &&
5918 * This is a work-around for HW issue found when link
5921 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5922 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5924 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5927 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5928 /* Set blinking rate to ~15.9Hz */
5929 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5930 LED_BLINK_RATE_VAL);
5931 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5933 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5934 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5936 if (CHIP_IS_E1(bp) &&
5937 ((speed == SPEED_2500) ||
5938 (speed == SPEED_1000) ||
5939 (speed == SPEED_100) ||
5940 (speed == SPEED_10))) {
5942 * On Everest 1 Ax chip versions for speeds less than
5943 * 10G LED scheme is different
5945 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5947 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5949 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5956 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5965 * This function comes to reflect the actual link state read DIRECTLY from the
5968 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5971 struct bnx2x *bp = params->bp;
5972 u16 gp_status = 0, phy_index = 0;
5973 u8 ext_phy_link_up = 0, serdes_phy_type;
5974 struct link_vars temp_vars;
5975 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
5977 if (CHIP_IS_E3(bp)) {
5979 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5981 /* Check 20G link */
5982 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5984 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5988 /* Check 10G link and below*/
5989 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5990 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5991 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5993 gp_status = ((gp_status >> 8) & 0xf) |
5994 ((gp_status >> 12) & 0xf);
5995 link_up = gp_status & (1 << lane);
6000 CL22_RD_OVER_CL45(bp, int_phy,
6001 MDIO_REG_BANK_GP_STATUS,
6002 MDIO_GP_STATUS_TOP_AN_STATUS1,
6004 /* link is up only if both local phy and external phy are up */
6005 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6008 /* In XGXS loopback mode, do not check external PHY */
6009 if (params->loopback_mode == LOOPBACK_XGXS)
6012 switch (params->num_phys) {
6014 /* No external PHY */
6017 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6018 ¶ms->phy[EXT_PHY1],
6019 params, &temp_vars);
6021 case 3: /* Dual Media */
6022 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6024 serdes_phy_type = ((params->phy[phy_index].media_type ==
6025 ETH_PHY_SFP_FIBER) ||
6026 (params->phy[phy_index].media_type ==
6027 ETH_PHY_XFP_FIBER) ||
6028 (params->phy[phy_index].media_type ==
6029 ETH_PHY_DA_TWINAX));
6031 if (is_serdes != serdes_phy_type)
6033 if (params->phy[phy_index].read_status) {
6035 params->phy[phy_index].read_status(
6036 ¶ms->phy[phy_index],
6037 params, &temp_vars);
6042 if (ext_phy_link_up)
6047 static int bnx2x_link_initialize(struct link_params *params,
6048 struct link_vars *vars)
6051 u8 phy_index, non_ext_phy;
6052 struct bnx2x *bp = params->bp;
6054 * In case of external phy existence, the line speed would be the
6055 * line speed linked up by the external phy. In case it is direct
6056 * only, then the line_speed during initialization will be
6057 * equal to the req_line_speed
6059 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6062 * Initialize the internal phy in case this is a direct board
6063 * (no external phys), or this board has external phy which requires
6066 if (!USES_WARPCORE(bp))
6067 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6068 /* init ext phy and enable link state int */
6069 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6070 (params->loopback_mode == LOOPBACK_XGXS));
6073 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6074 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6075 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6076 if (vars->line_speed == SPEED_AUTO_NEG &&
6079 bnx2x_set_parallel_detection(phy, params);
6080 if (params->phy[INT_PHY].config_init)
6081 params->phy[INT_PHY].config_init(phy,
6086 /* Init external phy*/
6088 if (params->phy[INT_PHY].supported &
6090 vars->link_status |= LINK_STATUS_SERDES_LINK;
6092 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6095 * No need to initialize second phy in case of first
6096 * phy only selection. In case of second phy, we do
6097 * need to initialize the first phy, since they are
6100 if (params->phy[phy_index].supported &
6102 vars->link_status |= LINK_STATUS_SERDES_LINK;
6104 if (phy_index == EXT_PHY2 &&
6105 (bnx2x_phy_selection(params) ==
6106 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6107 DP(NETIF_MSG_LINK, "Not initializing"
6111 params->phy[phy_index].config_init(
6112 ¶ms->phy[phy_index],
6116 /* Reset the interrupt indication after phy was initialized */
6117 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6119 (NIG_STATUS_XGXS0_LINK10G |
6120 NIG_STATUS_XGXS0_LINK_STATUS |
6121 NIG_STATUS_SERDES0_LINK_STATUS |
6123 bnx2x_update_mng(params, vars->link_status);
6127 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6128 struct link_params *params)
6130 /* reset the SerDes/XGXS */
6131 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6132 (0x1ff << (params->port*16)));
6135 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6136 struct link_params *params)
6138 struct bnx2x *bp = params->bp;
6142 gpio_port = BP_PATH(bp);
6144 gpio_port = params->port;
6145 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6146 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6148 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6149 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6151 DP(NETIF_MSG_LINK, "reset external PHY\n");
6154 static int bnx2x_update_link_down(struct link_params *params,
6155 struct link_vars *vars)
6157 struct bnx2x *bp = params->bp;
6158 u8 port = params->port;
6160 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6161 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6162 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6163 /* indicate no mac active */
6164 vars->mac_type = MAC_TYPE_NONE;
6166 /* update shared memory */
6167 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6168 LINK_STATUS_LINK_UP |
6169 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6170 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6171 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6172 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6173 vars->line_speed = 0;
6174 bnx2x_update_mng(params, vars->link_status);
6176 /* activate nig drain */
6177 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6180 if (!CHIP_IS_E3(bp))
6181 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6184 /* reset BigMac/Xmac */
6185 if (CHIP_IS_E1x(bp) ||
6187 bnx2x_bmac_rx_disable(bp, params->port);
6188 REG_WR(bp, GRCBASE_MISC +
6189 MISC_REGISTERS_RESET_REG_2_CLEAR,
6190 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6193 bnx2x_xmac_disable(params);
6198 static int bnx2x_update_link_up(struct link_params *params,
6199 struct link_vars *vars,
6202 struct bnx2x *bp = params->bp;
6203 u8 port = params->port;
6206 vars->link_status |= LINK_STATUS_LINK_UP;
6207 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6209 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6210 vars->link_status |=
6211 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6213 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6214 vars->link_status |=
6215 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6216 if (USES_WARPCORE(bp)) {
6218 if (bnx2x_xmac_enable(params, vars, 0) ==
6220 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6222 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6223 vars->link_status &= ~LINK_STATUS_LINK_UP;
6226 bnx2x_umac_enable(params, vars, 0);
6227 bnx2x_set_led(params, vars,
6228 LED_MODE_OPER, vars->line_speed);
6230 if ((CHIP_IS_E1x(bp) ||
6233 if (bnx2x_bmac_enable(params, vars, 0) ==
6235 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6237 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6238 vars->link_status &= ~LINK_STATUS_LINK_UP;
6241 bnx2x_set_led(params, vars,
6242 LED_MODE_OPER, SPEED_10000);
6244 rc = bnx2x_emac_program(params, vars);
6245 bnx2x_emac_enable(params, vars, 0);
6248 if ((vars->link_status &
6249 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6250 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6251 SINGLE_MEDIA_DIRECT(params))
6252 bnx2x_set_gmii_tx_driver(params);
6257 if (CHIP_IS_E1x(bp))
6258 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6262 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6264 /* update shared memory */
6265 bnx2x_update_mng(params, vars->link_status);
6270 * The bnx2x_link_update function should be called upon link
6272 * Link is considered up as follows:
6273 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6275 * - SINGLE_MEDIA - The link between the 577xx and the external
6276 * phy (XGXS) need to up as well as the external link of the
6278 * - DUAL_MEDIA - The link between the 577xx and the first
6279 * external phy needs to be up, and at least one of the 2
6280 * external phy link must be up.
6282 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6284 struct bnx2x *bp = params->bp;
6285 struct link_vars phy_vars[MAX_PHYS];
6286 u8 port = params->port;
6287 u8 link_10g_plus, phy_index;
6288 u8 ext_phy_link_up = 0, cur_link_up;
6291 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6292 u8 active_external_phy = INT_PHY;
6293 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6294 for (phy_index = INT_PHY; phy_index < params->num_phys;
6296 phy_vars[phy_index].flow_ctrl = 0;
6297 phy_vars[phy_index].link_status = 0;
6298 phy_vars[phy_index].line_speed = 0;
6299 phy_vars[phy_index].duplex = DUPLEX_FULL;
6300 phy_vars[phy_index].phy_link_up = 0;
6301 phy_vars[phy_index].link_up = 0;
6302 phy_vars[phy_index].fault_detected = 0;
6305 if (USES_WARPCORE(bp))
6306 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6308 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6309 port, (vars->phy_flags & PHY_XGXS_FLAG),
6310 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6312 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6314 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6315 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6317 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6319 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6320 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6321 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6324 if (!CHIP_IS_E3(bp))
6325 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6329 * Check external link change only for external phys, and apply
6330 * priority selection between them in case the link on both phys
6331 * is up. Note that instead of the common vars, a temporary
6332 * vars argument is used since each phy may have different link/
6333 * speed/duplex result
6335 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6337 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6338 if (!phy->read_status)
6340 /* Read link status and params of this ext phy */
6341 cur_link_up = phy->read_status(phy, params,
6342 &phy_vars[phy_index]);
6344 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6347 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6352 if (!ext_phy_link_up) {
6353 ext_phy_link_up = 1;
6354 active_external_phy = phy_index;
6356 switch (bnx2x_phy_selection(params)) {
6357 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6358 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6360 * In this option, the first PHY makes sure to pass the
6361 * traffic through itself only.
6362 * Its not clear how to reset the link on the second phy
6364 active_external_phy = EXT_PHY1;
6366 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6368 * In this option, the first PHY makes sure to pass the
6369 * traffic through the second PHY.
6371 active_external_phy = EXT_PHY2;
6375 * Link indication on both PHYs with the following cases
6377 * - FIRST_PHY means that second phy wasn't initialized,
6378 * hence its link is expected to be down
6379 * - SECOND_PHY means that first phy should not be able
6380 * to link up by itself (using configuration)
6381 * - DEFAULT should be overriden during initialiazation
6383 DP(NETIF_MSG_LINK, "Invalid link indication"
6384 "mpc=0x%x. DISABLING LINK !!!\n",
6385 params->multi_phy_config);
6386 ext_phy_link_up = 0;
6391 prev_line_speed = vars->line_speed;
6394 * Read the status of the internal phy. In case of
6395 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6396 * otherwise this is the link between the 577xx and the first
6399 if (params->phy[INT_PHY].read_status)
6400 params->phy[INT_PHY].read_status(
6401 ¶ms->phy[INT_PHY],
6404 * The INT_PHY flow control reside in the vars. This include the
6405 * case where the speed or flow control are not set to AUTO.
6406 * Otherwise, the active external phy flow control result is set
6407 * to the vars. The ext_phy_line_speed is needed to check if the
6408 * speed is different between the internal phy and external phy.
6409 * This case may be result of intermediate link speed change.
6411 if (active_external_phy > INT_PHY) {
6412 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6414 * Link speed is taken from the XGXS. AN and FC result from
6417 vars->link_status |= phy_vars[active_external_phy].link_status;
6420 * if active_external_phy is first PHY and link is up - disable
6421 * disable TX on second external PHY
6423 if (active_external_phy == EXT_PHY1) {
6424 if (params->phy[EXT_PHY2].phy_specific_func) {
6425 DP(NETIF_MSG_LINK, "Disabling TX on"
6427 params->phy[EXT_PHY2].phy_specific_func(
6428 ¶ms->phy[EXT_PHY2],
6429 params, DISABLE_TX);
6433 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6434 vars->duplex = phy_vars[active_external_phy].duplex;
6435 if (params->phy[active_external_phy].supported &
6437 vars->link_status |= LINK_STATUS_SERDES_LINK;
6439 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6440 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6441 active_external_phy);
6444 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6446 if (params->phy[phy_index].flags &
6447 FLAGS_REARM_LATCH_SIGNAL) {
6448 bnx2x_rearm_latch_signal(bp, port,
6450 active_external_phy);
6454 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6455 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6456 vars->link_status, ext_phy_line_speed);
6458 * Upon link speed change set the NIG into drain mode. Comes to
6459 * deals with possible FIFO glitch due to clk change when speed
6460 * is decreased without link down indicator
6463 if (vars->phy_link_up) {
6464 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6465 (ext_phy_line_speed != vars->line_speed)) {
6466 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6467 " different than the external"
6468 " link speed %d\n", vars->line_speed,
6469 ext_phy_line_speed);
6470 vars->phy_link_up = 0;
6471 } else if (prev_line_speed != vars->line_speed) {
6472 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6478 /* anything 10 and over uses the bmac */
6479 link_10g_plus = (vars->line_speed >= SPEED_10000);
6481 bnx2x_link_int_ack(params, vars, link_10g_plus);
6484 * In case external phy link is up, and internal link is down
6485 * (not initialized yet probably after link initialization, it
6486 * needs to be initialized.
6487 * Note that after link down-up as result of cable plug, the xgxs
6488 * link would probably become up again without the need
6491 if (!(SINGLE_MEDIA_DIRECT(params))) {
6492 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6493 " init_preceding = %d\n", ext_phy_link_up,
6495 params->phy[EXT_PHY1].flags &
6496 FLAGS_INIT_XGXS_FIRST);
6497 if (!(params->phy[EXT_PHY1].flags &
6498 FLAGS_INIT_XGXS_FIRST)
6499 && ext_phy_link_up && !vars->phy_link_up) {
6500 vars->line_speed = ext_phy_line_speed;
6501 if (vars->line_speed < SPEED_1000)
6502 vars->phy_flags |= PHY_SGMII_FLAG;
6504 vars->phy_flags &= ~PHY_SGMII_FLAG;
6506 if (params->phy[INT_PHY].config_init)
6507 params->phy[INT_PHY].config_init(
6508 ¶ms->phy[INT_PHY], params,
6513 * Link is up only if both local phy and external phy (in case of
6514 * non-direct board) are up and no fault detected on active PHY.
6516 vars->link_up = (vars->phy_link_up &&
6518 SINGLE_MEDIA_DIRECT(params)) &&
6519 (phy_vars[active_external_phy].fault_detected == 0));
6522 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6524 rc = bnx2x_update_link_down(params, vars);
6530 /*****************************************************************************/
6531 /* External Phy section */
6532 /*****************************************************************************/
6533 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6535 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6536 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6538 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6539 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6542 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6543 u32 spirom_ver, u32 ver_addr)
6545 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6546 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6549 REG_WR(bp, ver_addr, spirom_ver);
6552 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6553 struct bnx2x_phy *phy,
6556 u16 fw_ver1, fw_ver2;
6558 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6559 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6560 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6561 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6562 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6566 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6567 struct bnx2x_phy *phy,
6568 struct link_vars *vars)
6571 bnx2x_cl45_read(bp, phy,
6573 MDIO_AN_REG_STATUS, &val);
6574 bnx2x_cl45_read(bp, phy,
6576 MDIO_AN_REG_STATUS, &val);
6578 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6579 if ((val & (1<<0)) == 0)
6580 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6583 /******************************************************************/
6584 /* common BCM8073/BCM8727 PHY SECTION */
6585 /******************************************************************/
6586 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6587 struct link_params *params,
6588 struct link_vars *vars)
6590 struct bnx2x *bp = params->bp;
6591 if (phy->req_line_speed == SPEED_10 ||
6592 phy->req_line_speed == SPEED_100) {
6593 vars->flow_ctrl = phy->req_flow_ctrl;
6597 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6598 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6600 u16 ld_pause; /* local */
6601 u16 lp_pause; /* link partner */
6602 bnx2x_cl45_read(bp, phy,
6604 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6606 bnx2x_cl45_read(bp, phy,
6608 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6609 pause_result = (ld_pause &
6610 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6611 pause_result |= (lp_pause &
6612 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6614 bnx2x_pause_resolve(vars, pause_result);
6615 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6619 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6620 struct bnx2x_phy *phy,
6624 u16 fw_ver1, fw_msgout;
6627 /* Boot port from external ROM */
6629 bnx2x_cl45_write(bp, phy,
6631 MDIO_PMA_REG_GEN_CTRL,
6634 /* ucode reboot and rst */
6635 bnx2x_cl45_write(bp, phy,
6637 MDIO_PMA_REG_GEN_CTRL,
6640 bnx2x_cl45_write(bp, phy,
6642 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6644 /* Reset internal microprocessor */
6645 bnx2x_cl45_write(bp, phy,
6647 MDIO_PMA_REG_GEN_CTRL,
6648 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6650 /* Release srst bit */
6651 bnx2x_cl45_write(bp, phy,
6653 MDIO_PMA_REG_GEN_CTRL,
6654 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6656 /* Delay 100ms per the PHY specifications */
6659 /* 8073 sometimes taking longer to download */
6664 "bnx2x_8073_8727_external_rom_boot port %x:"
6665 "Download failed. fw version = 0x%x\n",
6671 bnx2x_cl45_read(bp, phy,
6673 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6674 bnx2x_cl45_read(bp, phy,
6676 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6679 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6680 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6681 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6683 /* Clear ser_boot_ctl bit */
6684 bnx2x_cl45_write(bp, phy,
6686 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6687 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6690 "bnx2x_8073_8727_external_rom_boot port %x:"
6691 "Download complete. fw version = 0x%x\n",
6697 /******************************************************************/
6698 /* BCM8073 PHY SECTION */
6699 /******************************************************************/
6700 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6702 /* This is only required for 8073A1, version 102 only */
6705 /* Read 8073 HW revision*/
6706 bnx2x_cl45_read(bp, phy,
6708 MDIO_PMA_REG_8073_CHIP_REV, &val);
6711 /* No need to workaround in 8073 A1 */
6715 bnx2x_cl45_read(bp, phy,
6717 MDIO_PMA_REG_ROM_VER2, &val);
6719 /* SNR should be applied only for version 0x102 */
6726 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6728 u16 val, cnt, cnt1 ;
6730 bnx2x_cl45_read(bp, phy,
6732 MDIO_PMA_REG_8073_CHIP_REV, &val);
6735 /* No need to workaround in 8073 A1 */
6738 /* XAUI workaround in 8073 A0: */
6741 * After loading the boot ROM and restarting Autoneg, poll
6745 for (cnt = 0; cnt < 1000; cnt++) {
6746 bnx2x_cl45_read(bp, phy,
6748 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6751 * If bit [14] = 0 or bit [13] = 0, continue on with
6752 * system initialization (XAUI work-around not required, as
6753 * these bits indicate 2.5G or 1G link up).
6755 if (!(val & (1<<14)) || !(val & (1<<13))) {
6756 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6758 } else if (!(val & (1<<15))) {
6759 DP(NETIF_MSG_LINK, "bit 15 went off\n");
6761 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6762 * MSB (bit15) goes to 1 (indicating that the XAUI
6763 * workaround has completed), then continue on with
6764 * system initialization.
6766 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6767 bnx2x_cl45_read(bp, phy,
6769 MDIO_PMA_REG_8073_XAUI_WA, &val);
6770 if (val & (1<<15)) {
6772 "XAUI workaround has completed\n");
6781 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6785 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6787 /* Force KR or KX */
6788 bnx2x_cl45_write(bp, phy,
6789 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6790 bnx2x_cl45_write(bp, phy,
6791 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6792 bnx2x_cl45_write(bp, phy,
6793 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6794 bnx2x_cl45_write(bp, phy,
6795 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6798 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6799 struct bnx2x_phy *phy,
6800 struct link_vars *vars)
6803 struct bnx2x *bp = params->bp;
6804 bnx2x_cl45_read(bp, phy,
6805 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6807 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6808 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6809 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6810 if ((vars->ieee_fc &
6811 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6812 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6813 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6815 if ((vars->ieee_fc &
6816 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6817 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6818 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6820 if ((vars->ieee_fc &
6821 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6822 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6823 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6826 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6828 bnx2x_cl45_write(bp, phy,
6829 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6833 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6834 struct link_params *params,
6835 struct link_vars *vars)
6837 struct bnx2x *bp = params->bp;
6840 DP(NETIF_MSG_LINK, "Init 8073\n");
6843 gpio_port = BP_PATH(bp);
6845 gpio_port = params->port;
6846 /* Restore normal power mode*/
6847 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6848 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6850 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6851 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6854 bnx2x_cl45_write(bp, phy,
6855 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6856 bnx2x_cl45_write(bp, phy,
6857 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
6859 bnx2x_8073_set_pause_cl37(params, phy, vars);
6861 bnx2x_cl45_read(bp, phy,
6862 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6864 bnx2x_cl45_read(bp, phy,
6865 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6867 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6869 /* Swap polarity if required - Must be done only in non-1G mode */
6870 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6871 /* Configure the 8073 to swap _P and _N of the KR lines */
6872 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6873 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6874 bnx2x_cl45_read(bp, phy,
6876 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6877 bnx2x_cl45_write(bp, phy,
6879 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6884 /* Enable CL37 BAM */
6885 if (REG_RD(bp, params->shmem_base +
6886 offsetof(struct shmem_region, dev_info.
6887 port_hw_config[params->port].default_cfg)) &
6888 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6890 bnx2x_cl45_read(bp, phy,
6892 MDIO_AN_REG_8073_BAM, &val);
6893 bnx2x_cl45_write(bp, phy,
6895 MDIO_AN_REG_8073_BAM, val | 1);
6896 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6898 if (params->loopback_mode == LOOPBACK_EXT) {
6899 bnx2x_807x_force_10G(bp, phy);
6900 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6903 bnx2x_cl45_write(bp, phy,
6904 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6906 if (phy->req_line_speed != SPEED_AUTO_NEG) {
6907 if (phy->req_line_speed == SPEED_10000) {
6909 } else if (phy->req_line_speed == SPEED_2500) {
6912 * Note that 2.5G works only when used with 1G
6919 if (phy->speed_cap_mask &
6920 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6923 /* Note that 2.5G works only when used with 1G advertisement */
6924 if (phy->speed_cap_mask &
6925 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6926 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6928 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6931 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6932 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6934 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6935 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6936 (phy->req_line_speed == SPEED_2500)) {
6938 /* Allow 2.5G for A1 and above */
6939 bnx2x_cl45_read(bp, phy,
6940 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6942 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6948 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6952 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6953 /* Add support for CL37 (passive mode) II */
6955 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6956 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6957 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6960 /* Add support for CL37 (passive mode) III */
6961 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6964 * The SNR will improve about 2db by changing BW and FEE main
6965 * tap. Rest commands are executed after link is up
6966 * Change FFE main cursor to 5 in EDC register
6968 if (bnx2x_8073_is_snr_needed(bp, phy))
6969 bnx2x_cl45_write(bp, phy,
6970 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6973 /* Enable FEC (Forware Error Correction) Request in the AN */
6974 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6976 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6978 bnx2x_ext_phy_set_pause(params, phy, vars);
6980 /* Restart autoneg */
6982 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6983 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6984 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6988 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6989 struct link_params *params,
6990 struct link_vars *vars)
6992 struct bnx2x *bp = params->bp;
6995 u16 link_status = 0;
6996 u16 an1000_status = 0;
6998 bnx2x_cl45_read(bp, phy,
6999 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7001 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7003 /* clear the interrupt LASI status register */
7004 bnx2x_cl45_read(bp, phy,
7005 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7006 bnx2x_cl45_read(bp, phy,
7007 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7008 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7010 bnx2x_cl45_read(bp, phy,
7011 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7013 /* Check the LASI */
7014 bnx2x_cl45_read(bp, phy,
7015 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7017 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7019 /* Check the link status */
7020 bnx2x_cl45_read(bp, phy,
7021 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7022 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7024 bnx2x_cl45_read(bp, phy,
7025 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7026 bnx2x_cl45_read(bp, phy,
7027 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7028 link_up = ((val1 & 4) == 4);
7029 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7032 ((phy->req_line_speed != SPEED_10000))) {
7033 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7036 bnx2x_cl45_read(bp, phy,
7037 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7038 bnx2x_cl45_read(bp, phy,
7039 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7041 /* Check the link status on 1.1.2 */
7042 bnx2x_cl45_read(bp, phy,
7043 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7044 bnx2x_cl45_read(bp, phy,
7045 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7046 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7047 "an_link_status=0x%x\n", val2, val1, an1000_status);
7049 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7050 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7052 * The SNR will improve about 2dbby changing the BW and FEE main
7053 * tap. The 1st write to change FFE main tap is set before
7054 * restart AN. Change PLL Bandwidth in EDC register
7056 bnx2x_cl45_write(bp, phy,
7057 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7060 /* Change CDR Bandwidth in EDC register */
7061 bnx2x_cl45_write(bp, phy,
7062 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7065 bnx2x_cl45_read(bp, phy,
7066 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7069 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7070 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7072 vars->line_speed = SPEED_10000;
7073 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7075 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7077 vars->line_speed = SPEED_2500;
7078 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7080 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7082 vars->line_speed = SPEED_1000;
7083 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7087 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7092 /* Swap polarity if required */
7093 if (params->lane_config &
7094 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7095 /* Configure the 8073 to swap P and N of the KR lines */
7096 bnx2x_cl45_read(bp, phy,
7098 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7100 * Set bit 3 to invert Rx in 1G mode and clear this bit
7101 * when it`s in 10G mode.
7103 if (vars->line_speed == SPEED_1000) {
7104 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7110 bnx2x_cl45_write(bp, phy,
7112 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7115 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7116 bnx2x_8073_resolve_fc(phy, params, vars);
7117 vars->duplex = DUPLEX_FULL;
7122 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7123 struct link_params *params)
7125 struct bnx2x *bp = params->bp;
7128 gpio_port = BP_PATH(bp);
7130 gpio_port = params->port;
7131 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7133 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7134 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7138 /******************************************************************/
7139 /* BCM8705 PHY SECTION */
7140 /******************************************************************/
7141 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7142 struct link_params *params,
7143 struct link_vars *vars)
7145 struct bnx2x *bp = params->bp;
7146 DP(NETIF_MSG_LINK, "init 8705\n");
7147 /* Restore normal power mode*/
7148 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7149 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7151 bnx2x_ext_phy_hw_reset(bp, params->port);
7152 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7153 bnx2x_wait_reset_complete(bp, phy, params);
7155 bnx2x_cl45_write(bp, phy,
7156 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7157 bnx2x_cl45_write(bp, phy,
7158 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7159 bnx2x_cl45_write(bp, phy,
7160 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7161 bnx2x_cl45_write(bp, phy,
7162 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7163 /* BCM8705 doesn't have microcode, hence the 0 */
7164 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7168 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7169 struct link_params *params,
7170 struct link_vars *vars)
7174 struct bnx2x *bp = params->bp;
7175 DP(NETIF_MSG_LINK, "read status 8705\n");
7176 bnx2x_cl45_read(bp, phy,
7177 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7178 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7180 bnx2x_cl45_read(bp, phy,
7181 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7182 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7184 bnx2x_cl45_read(bp, phy,
7185 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7187 bnx2x_cl45_read(bp, phy,
7188 MDIO_PMA_DEVAD, 0xc809, &val1);
7189 bnx2x_cl45_read(bp, phy,
7190 MDIO_PMA_DEVAD, 0xc809, &val1);
7192 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7193 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7195 vars->line_speed = SPEED_10000;
7196 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7201 /******************************************************************/
7202 /* SFP+ module Section */
7203 /******************************************************************/
7204 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7205 struct bnx2x_phy *phy,
7208 struct bnx2x *bp = params->bp;
7210 * Disable transmitter only for bootcodes which can enable it afterwards
7214 if (params->feature_config_flags &
7215 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7216 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7218 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7222 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7223 bnx2x_cl45_write(bp, phy,
7225 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7228 static u8 bnx2x_get_gpio_port(struct link_params *params)
7231 u32 swap_val, swap_override;
7232 struct bnx2x *bp = params->bp;
7234 gpio_port = BP_PATH(bp);
7236 gpio_port = params->port;
7237 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7238 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7239 return gpio_port ^ (swap_val && swap_override);
7242 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7243 struct bnx2x_phy *phy,
7247 u8 port = params->port;
7248 struct bnx2x *bp = params->bp;
7251 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7252 tx_en_mode = REG_RD(bp, params->shmem_base +
7253 offsetof(struct shmem_region,
7254 dev_info.port_hw_config[port].sfp_ctrl)) &
7255 PORT_HW_CFG_TX_LASER_MASK;
7256 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7257 "mode = %x\n", tx_en, port, tx_en_mode);
7258 switch (tx_en_mode) {
7259 case PORT_HW_CFG_TX_LASER_MDIO:
7261 bnx2x_cl45_read(bp, phy,
7263 MDIO_PMA_REG_PHY_IDENTIFIER,
7271 bnx2x_cl45_write(bp, phy,
7273 MDIO_PMA_REG_PHY_IDENTIFIER,
7276 case PORT_HW_CFG_TX_LASER_GPIO0:
7277 case PORT_HW_CFG_TX_LASER_GPIO1:
7278 case PORT_HW_CFG_TX_LASER_GPIO2:
7279 case PORT_HW_CFG_TX_LASER_GPIO3:
7282 u8 gpio_port, gpio_mode;
7284 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7286 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7288 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7289 gpio_port = bnx2x_get_gpio_port(params);
7290 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7294 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7299 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7300 struct bnx2x_phy *phy,
7303 struct bnx2x *bp = params->bp;
7304 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7306 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7308 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7311 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7312 struct link_params *params,
7313 u16 addr, u8 byte_cnt, u8 *o_buf)
7315 struct bnx2x *bp = params->bp;
7318 if (byte_cnt > 16) {
7319 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7320 " is limited to 0xf\n");
7323 /* Set the read command byte count */
7324 bnx2x_cl45_write(bp, phy,
7325 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7326 (byte_cnt | 0xa000));
7328 /* Set the read command address */
7329 bnx2x_cl45_write(bp, phy,
7330 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7333 /* Activate read command */
7334 bnx2x_cl45_write(bp, phy,
7335 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7338 /* Wait up to 500us for command complete status */
7339 for (i = 0; i < 100; i++) {
7340 bnx2x_cl45_read(bp, phy,
7342 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7343 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7344 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7349 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7350 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7352 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7353 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7357 /* Read the buffer */
7358 for (i = 0; i < byte_cnt; i++) {
7359 bnx2x_cl45_read(bp, phy,
7361 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7362 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7365 for (i = 0; i < 100; i++) {
7366 bnx2x_cl45_read(bp, phy,
7368 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7369 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7370 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7377 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7378 struct link_params *params,
7379 u16 addr, u8 byte_cnt,
7383 u8 i, j = 0, cnt = 0;
7386 struct bnx2x *bp = params->bp;
7387 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7388 " addr %d, cnt %d\n",
7390 if (byte_cnt > 16) {
7391 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7392 " is limited to 16 bytes\n");
7396 /* 4 byte aligned address */
7397 addr32 = addr & (~0x3);
7399 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7401 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7404 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7405 o_buf[j] = *((u8 *)data_array + i);
7413 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7414 struct link_params *params,
7415 u16 addr, u8 byte_cnt, u8 *o_buf)
7417 struct bnx2x *bp = params->bp;
7420 if (byte_cnt > 16) {
7421 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7422 " is limited to 0xf\n");
7426 /* Need to read from 1.8000 to clear it */
7427 bnx2x_cl45_read(bp, phy,
7429 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7432 /* Set the read command byte count */
7433 bnx2x_cl45_write(bp, phy,
7435 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7436 ((byte_cnt < 2) ? 2 : byte_cnt));
7438 /* Set the read command address */
7439 bnx2x_cl45_write(bp, phy,
7441 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7443 /* Set the destination address */
7444 bnx2x_cl45_write(bp, phy,
7447 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7449 /* Activate read command */
7450 bnx2x_cl45_write(bp, phy,
7452 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7455 * Wait appropriate time for two-wire command to finish before
7456 * polling the status register
7460 /* Wait up to 500us for command complete status */
7461 for (i = 0; i < 100; i++) {
7462 bnx2x_cl45_read(bp, phy,
7464 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7465 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7466 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7471 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7472 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7474 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7475 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7479 /* Read the buffer */
7480 for (i = 0; i < byte_cnt; i++) {
7481 bnx2x_cl45_read(bp, phy,
7483 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7484 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7487 for (i = 0; i < 100; i++) {
7488 bnx2x_cl45_read(bp, phy,
7490 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7491 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7492 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7500 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7501 struct link_params *params, u16 addr,
7502 u8 byte_cnt, u8 *o_buf)
7505 switch (phy->type) {
7506 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7507 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7510 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7511 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7512 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7515 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7516 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7523 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7524 struct link_params *params,
7527 struct bnx2x *bp = params->bp;
7528 u32 sync_offset = 0, phy_idx, media_types;
7529 u8 val, check_limiting_mode = 0;
7530 *edc_mode = EDC_MODE_LIMITING;
7532 phy->media_type = ETH_PHY_UNSPECIFIED;
7533 /* First check for copper cable */
7534 if (bnx2x_read_sfp_module_eeprom(phy,
7536 SFP_EEPROM_CON_TYPE_ADDR,
7539 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7544 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7546 u8 copper_module_type;
7547 phy->media_type = ETH_PHY_DA_TWINAX;
7549 * Check if its active cable (includes SFP+ module)
7552 if (bnx2x_read_sfp_module_eeprom(phy,
7554 SFP_EEPROM_FC_TX_TECH_ADDR,
7556 &copper_module_type) != 0) {
7558 "Failed to read copper-cable-type"
7559 " from SFP+ EEPROM\n");
7563 if (copper_module_type &
7564 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7565 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7566 check_limiting_mode = 1;
7567 } else if (copper_module_type &
7568 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7569 DP(NETIF_MSG_LINK, "Passive Copper"
7570 " cable detected\n");
7572 EDC_MODE_PASSIVE_DAC;
7574 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7575 "type 0x%x !!!\n", copper_module_type);
7580 case SFP_EEPROM_CON_TYPE_VAL_LC:
7581 phy->media_type = ETH_PHY_SFP_FIBER;
7582 DP(NETIF_MSG_LINK, "Optic module detected\n");
7583 check_limiting_mode = 1;
7586 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7590 sync_offset = params->shmem_base +
7591 offsetof(struct shmem_region,
7592 dev_info.port_hw_config[params->port].media_type);
7593 media_types = REG_RD(bp, sync_offset);
7594 /* Update media type for non-PMF sync */
7595 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7596 if (&(params->phy[phy_idx]) == phy) {
7597 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7598 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7599 media_types |= ((phy->media_type &
7600 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7601 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7605 REG_WR(bp, sync_offset, media_types);
7606 if (check_limiting_mode) {
7607 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7608 if (bnx2x_read_sfp_module_eeprom(phy,
7610 SFP_EEPROM_OPTIONS_ADDR,
7611 SFP_EEPROM_OPTIONS_SIZE,
7613 DP(NETIF_MSG_LINK, "Failed to read Option"
7614 " field from module EEPROM\n");
7617 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7618 *edc_mode = EDC_MODE_LINEAR;
7620 *edc_mode = EDC_MODE_LIMITING;
7622 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7626 * This function read the relevant field from the module (SFP+), and verify it
7627 * is compliant with this board
7629 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7630 struct link_params *params)
7632 struct bnx2x *bp = params->bp;
7634 u32 fw_resp, fw_cmd_param;
7635 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7636 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7637 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7638 val = REG_RD(bp, params->shmem_base +
7639 offsetof(struct shmem_region, dev_info.
7640 port_feature_config[params->port].config));
7641 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7642 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7643 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7647 if (params->feature_config_flags &
7648 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7649 /* Use specific phy request */
7650 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7651 } else if (params->feature_config_flags &
7652 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7653 /* Use first phy request only in case of non-dual media*/
7654 if (DUAL_MEDIA(params)) {
7655 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7659 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7661 /* No support in OPT MDL detection */
7662 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7667 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7668 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7669 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7670 DP(NETIF_MSG_LINK, "Approved module\n");
7674 /* format the warning message */
7675 if (bnx2x_read_sfp_module_eeprom(phy,
7677 SFP_EEPROM_VENDOR_NAME_ADDR,
7678 SFP_EEPROM_VENDOR_NAME_SIZE,
7680 vendor_name[0] = '\0';
7682 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7683 if (bnx2x_read_sfp_module_eeprom(phy,
7685 SFP_EEPROM_PART_NO_ADDR,
7686 SFP_EEPROM_PART_NO_SIZE,
7688 vendor_pn[0] = '\0';
7690 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7692 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7693 " Port %d from %s part number %s\n",
7694 params->port, vendor_name, vendor_pn);
7695 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7699 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7700 struct link_params *params)
7704 struct bnx2x *bp = params->bp;
7707 * Initialization time after hot-plug may take up to 300ms for
7708 * some phys type ( e.g. JDSU )
7711 for (timeout = 0; timeout < 60; timeout++) {
7712 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7714 DP(NETIF_MSG_LINK, "SFP+ module initialization "
7715 "took %d ms\n", timeout * 5);
7723 static void bnx2x_8727_power_module(struct bnx2x *bp,
7724 struct bnx2x_phy *phy,
7726 /* Make sure GPIOs are not using for LED mode */
7729 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7730 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7732 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7733 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7734 * where the 1st bit is the over-current(only input), and 2nd bit is
7735 * for power( only output )
7737 * In case of NOC feature is disabled and power is up, set GPIO control
7738 * as input to enable listening of over-current indication
7740 if (phy->flags & FLAGS_NOC)
7746 * Set GPIO control to OUTPUT, and set the power bit
7747 * to according to the is_power_up
7751 bnx2x_cl45_write(bp, phy,
7753 MDIO_PMA_REG_8727_GPIO_CTRL,
7757 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7758 struct bnx2x_phy *phy,
7761 u16 cur_limiting_mode;
7763 bnx2x_cl45_read(bp, phy,
7765 MDIO_PMA_REG_ROM_VER2,
7766 &cur_limiting_mode);
7767 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7770 if (edc_mode == EDC_MODE_LIMITING) {
7771 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7772 bnx2x_cl45_write(bp, phy,
7774 MDIO_PMA_REG_ROM_VER2,
7776 } else { /* LRM mode ( default )*/
7778 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7781 * Changing to LRM mode takes quite few seconds. So do it only
7782 * if current mode is limiting (default is LRM)
7784 if (cur_limiting_mode != EDC_MODE_LIMITING)
7787 bnx2x_cl45_write(bp, phy,
7789 MDIO_PMA_REG_LRM_MODE,
7791 bnx2x_cl45_write(bp, phy,
7793 MDIO_PMA_REG_ROM_VER2,
7795 bnx2x_cl45_write(bp, phy,
7797 MDIO_PMA_REG_MISC_CTRL0,
7799 bnx2x_cl45_write(bp, phy,
7801 MDIO_PMA_REG_LRM_MODE,
7807 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7808 struct bnx2x_phy *phy,
7813 bnx2x_cl45_read(bp, phy,
7815 MDIO_PMA_REG_PHY_IDENTIFIER,
7818 bnx2x_cl45_write(bp, phy,
7820 MDIO_PMA_REG_PHY_IDENTIFIER,
7821 (phy_identifier & ~(1<<9)));
7823 bnx2x_cl45_read(bp, phy,
7825 MDIO_PMA_REG_ROM_VER2,
7827 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7828 bnx2x_cl45_write(bp, phy,
7830 MDIO_PMA_REG_ROM_VER2,
7831 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7833 bnx2x_cl45_write(bp, phy,
7835 MDIO_PMA_REG_PHY_IDENTIFIER,
7836 (phy_identifier | (1<<9)));
7841 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7842 struct link_params *params,
7845 struct bnx2x *bp = params->bp;
7849 bnx2x_sfp_set_transmitter(params, phy, 0);
7852 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7853 bnx2x_sfp_set_transmitter(params, phy, 1);
7856 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7862 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7865 struct bnx2x *bp = params->bp;
7867 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7868 offsetof(struct shmem_region,
7869 dev_info.port_hw_config[params->port].sfp_ctrl)) &
7870 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7871 switch (fault_led_gpio) {
7872 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7874 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7875 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7876 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7877 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7879 u8 gpio_port = bnx2x_get_gpio_port(params);
7880 u16 gpio_pin = fault_led_gpio -
7881 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7882 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7883 "pin %x port %x mode %x\n",
7884 gpio_pin, gpio_port, gpio_mode);
7885 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7889 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7894 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7898 u8 port = params->port;
7899 struct bnx2x *bp = params->bp;
7900 pin_cfg = (REG_RD(bp, params->shmem_base +
7901 offsetof(struct shmem_region,
7902 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7903 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7904 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7905 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7906 gpio_mode, pin_cfg);
7907 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7910 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7913 struct bnx2x *bp = params->bp;
7914 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7915 if (CHIP_IS_E3(bp)) {
7917 * Low ==> if SFP+ module is supported otherwise
7918 * High ==> if SFP+ module is not on the approved vendor list
7920 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7922 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7925 static void bnx2x_warpcore_power_module(struct link_params *params,
7926 struct bnx2x_phy *phy,
7930 struct bnx2x *bp = params->bp;
7932 pin_cfg = (REG_RD(bp, params->shmem_base +
7933 offsetof(struct shmem_region,
7934 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7935 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7936 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7938 if (pin_cfg == PIN_CFG_NA)
7940 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7943 * Low ==> corresponding SFP+ module is powered
7944 * high ==> the SFP+ module is powered down
7946 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7949 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7950 struct link_params *params)
7952 bnx2x_warpcore_power_module(params, phy, 0);
7955 static void bnx2x_power_sfp_module(struct link_params *params,
7956 struct bnx2x_phy *phy,
7959 struct bnx2x *bp = params->bp;
7960 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7962 switch (phy->type) {
7963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7964 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7965 bnx2x_8727_power_module(params->bp, phy, power);
7967 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7968 bnx2x_warpcore_power_module(params, phy, power);
7974 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7975 struct bnx2x_phy *phy,
7979 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7980 struct bnx2x *bp = params->bp;
7982 u8 lane = bnx2x_get_warpcore_lane(phy, params);
7983 /* This is a global register which controls all lanes */
7984 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7985 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7986 val &= ~(0xf << (lane << 2));
7989 case EDC_MODE_LINEAR:
7990 case EDC_MODE_LIMITING:
7991 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7993 case EDC_MODE_PASSIVE_DAC:
7994 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8000 val |= (mode << (lane << 2));
8001 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8002 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8004 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8005 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8010 static void bnx2x_set_limiting_mode(struct link_params *params,
8011 struct bnx2x_phy *phy,
8014 switch (phy->type) {
8015 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8016 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8018 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8019 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8020 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8022 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8023 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8028 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8029 struct link_params *params)
8031 struct bnx2x *bp = params->bp;
8035 u32 val = REG_RD(bp, params->shmem_base +
8036 offsetof(struct shmem_region, dev_info.
8037 port_feature_config[params->port].config));
8039 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8041 /* Power up module */
8042 bnx2x_power_sfp_module(params, phy, 1);
8043 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8044 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8046 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8047 /* check SFP+ module compatibility */
8048 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8050 /* Turn on fault module-detected led */
8051 bnx2x_set_sfp_module_fault_led(params,
8052 MISC_REGISTERS_GPIO_HIGH);
8054 /* Check if need to power down the SFP+ module */
8055 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8056 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8057 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8058 bnx2x_power_sfp_module(params, phy, 0);
8062 /* Turn off fault module-detected led */
8063 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8067 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8068 * is done automatically
8070 bnx2x_set_limiting_mode(params, phy, edc_mode);
8073 * Enable transmit for this module if the module is approved, or
8074 * if unapproved modules should also enable the Tx laser
8077 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8078 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8079 bnx2x_sfp_set_transmitter(params, phy, 1);
8081 bnx2x_sfp_set_transmitter(params, phy, 0);
8086 void bnx2x_handle_module_detect_int(struct link_params *params)
8088 struct bnx2x *bp = params->bp;
8089 struct bnx2x_phy *phy;
8091 u8 gpio_num, gpio_port;
8093 phy = ¶ms->phy[INT_PHY];
8095 phy = ¶ms->phy[EXT_PHY1];
8097 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8098 params->port, &gpio_num, &gpio_port) ==
8100 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8104 /* Set valid module led off */
8105 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8107 /* Get current gpio val reflecting module plugged in / out*/
8108 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8110 /* Call the handling function in case module is detected */
8111 if (gpio_val == 0) {
8112 bnx2x_power_sfp_module(params, phy, 1);
8113 bnx2x_set_gpio_int(bp, gpio_num,
8114 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8116 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8117 bnx2x_sfp_module_detection(phy, params);
8119 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8121 u32 val = REG_RD(bp, params->shmem_base +
8122 offsetof(struct shmem_region, dev_info.
8123 port_feature_config[params->port].
8126 bnx2x_set_gpio_int(bp, gpio_num,
8127 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8130 * Module was plugged out.
8131 * Disable transmit for this module
8133 phy->media_type = ETH_PHY_NOT_PRESENT;
8134 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8135 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8136 bnx2x_sfp_set_transmitter(params, phy, 0);
8140 /******************************************************************/
8141 /* Used by 8706 and 8727 */
8142 /******************************************************************/
8143 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8144 struct bnx2x_phy *phy,
8145 u16 alarm_status_offset,
8146 u16 alarm_ctrl_offset)
8148 u16 alarm_status, val;
8149 bnx2x_cl45_read(bp, phy,
8150 MDIO_PMA_DEVAD, alarm_status_offset,
8152 bnx2x_cl45_read(bp, phy,
8153 MDIO_PMA_DEVAD, alarm_status_offset,
8155 /* Mask or enable the fault event. */
8156 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8157 if (alarm_status & (1<<0))
8161 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8163 /******************************************************************/
8164 /* common BCM8706/BCM8726 PHY SECTION */
8165 /******************************************************************/
8166 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8167 struct link_params *params,
8168 struct link_vars *vars)
8171 u16 val1, val2, rx_sd, pcs_status;
8172 struct bnx2x *bp = params->bp;
8173 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8175 bnx2x_cl45_read(bp, phy,
8176 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8178 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8179 MDIO_PMA_LASI_TXCTRL);
8181 /* clear LASI indication*/
8182 bnx2x_cl45_read(bp, phy,
8183 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8184 bnx2x_cl45_read(bp, phy,
8185 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8186 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8188 bnx2x_cl45_read(bp, phy,
8189 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8190 bnx2x_cl45_read(bp, phy,
8191 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8192 bnx2x_cl45_read(bp, phy,
8193 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8194 bnx2x_cl45_read(bp, phy,
8195 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8197 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8198 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8200 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8201 * are set, or if the autoneg bit 1 is set
8203 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8206 vars->line_speed = SPEED_1000;
8208 vars->line_speed = SPEED_10000;
8209 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8210 vars->duplex = DUPLEX_FULL;
8213 /* Capture 10G link fault. Read twice to clear stale value. */
8214 if (vars->line_speed == SPEED_10000) {
8215 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8216 MDIO_PMA_LASI_TXSTAT, &val1);
8217 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8218 MDIO_PMA_LASI_TXSTAT, &val1);
8220 vars->fault_detected = 1;
8226 /******************************************************************/
8227 /* BCM8706 PHY SECTION */
8228 /******************************************************************/
8229 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8230 struct link_params *params,
8231 struct link_vars *vars)
8235 struct bnx2x *bp = params->bp;
8237 /* SPF+ PHY: Set flag to check for Tx error */
8238 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8240 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8241 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8243 bnx2x_ext_phy_hw_reset(bp, params->port);
8244 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8245 bnx2x_wait_reset_complete(bp, phy, params);
8247 /* Wait until fw is loaded */
8248 for (cnt = 0; cnt < 100; cnt++) {
8249 bnx2x_cl45_read(bp, phy,
8250 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8255 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8256 if ((params->feature_config_flags &
8257 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8260 for (i = 0; i < 4; i++) {
8261 reg = MDIO_XS_8706_REG_BANK_RX0 +
8262 i*(MDIO_XS_8706_REG_BANK_RX1 -
8263 MDIO_XS_8706_REG_BANK_RX0);
8264 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8265 /* Clear first 3 bits of the control */
8267 /* Set control bits according to configuration */
8268 val |= (phy->rx_preemphasis[i] & 0x7);
8269 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8270 " reg 0x%x <-- val 0x%x\n", reg, val);
8271 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8275 if (phy->req_line_speed == SPEED_10000) {
8276 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8278 bnx2x_cl45_write(bp, phy,
8280 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8281 bnx2x_cl45_write(bp, phy,
8282 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8284 /* Arm LASI for link and Tx fault. */
8285 bnx2x_cl45_write(bp, phy,
8286 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8288 /* Force 1Gbps using autoneg with 1G advertisement */
8290 /* Allow CL37 through CL73 */
8291 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8292 bnx2x_cl45_write(bp, phy,
8293 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8295 /* Enable Full-Duplex advertisement on CL37 */
8296 bnx2x_cl45_write(bp, phy,
8297 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8298 /* Enable CL37 AN */
8299 bnx2x_cl45_write(bp, phy,
8300 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8302 bnx2x_cl45_write(bp, phy,
8303 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8305 /* Enable clause 73 AN */
8306 bnx2x_cl45_write(bp, phy,
8307 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8308 bnx2x_cl45_write(bp, phy,
8309 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8311 bnx2x_cl45_write(bp, phy,
8312 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8315 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8318 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8319 * power mode, if TX Laser is disabled
8322 tx_en_mode = REG_RD(bp, params->shmem_base +
8323 offsetof(struct shmem_region,
8324 dev_info.port_hw_config[params->port].sfp_ctrl))
8325 & PORT_HW_CFG_TX_LASER_MASK;
8327 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8328 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8329 bnx2x_cl45_read(bp, phy,
8330 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8332 bnx2x_cl45_write(bp, phy,
8333 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8339 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8340 struct link_params *params,
8341 struct link_vars *vars)
8343 return bnx2x_8706_8726_read_status(phy, params, vars);
8346 /******************************************************************/
8347 /* BCM8726 PHY SECTION */
8348 /******************************************************************/
8349 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8350 struct link_params *params)
8352 struct bnx2x *bp = params->bp;
8353 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8354 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8357 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8358 struct link_params *params)
8360 struct bnx2x *bp = params->bp;
8361 /* Need to wait 100ms after reset */
8364 /* Micro controller re-boot */
8365 bnx2x_cl45_write(bp, phy,
8366 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8368 /* Set soft reset */
8369 bnx2x_cl45_write(bp, phy,
8371 MDIO_PMA_REG_GEN_CTRL,
8372 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8374 bnx2x_cl45_write(bp, phy,
8376 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8378 bnx2x_cl45_write(bp, phy,
8380 MDIO_PMA_REG_GEN_CTRL,
8381 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8383 /* wait for 150ms for microcode load */
8386 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8387 bnx2x_cl45_write(bp, phy,
8389 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8392 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8395 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8396 struct link_params *params,
8397 struct link_vars *vars)
8399 struct bnx2x *bp = params->bp;
8401 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8403 bnx2x_cl45_read(bp, phy,
8404 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8406 if (val1 & (1<<15)) {
8407 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8409 vars->line_speed = 0;
8416 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8417 struct link_params *params,
8418 struct link_vars *vars)
8420 struct bnx2x *bp = params->bp;
8421 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8423 /* SPF+ PHY: Set flag to check for Tx error */
8424 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8426 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8427 bnx2x_wait_reset_complete(bp, phy, params);
8429 bnx2x_8726_external_rom_boot(phy, params);
8432 * Need to call module detected on initialization since the module
8433 * detection triggered by actual module insertion might occur before
8434 * driver is loaded, and when driver is loaded, it reset all
8435 * registers, including the transmitter
8437 bnx2x_sfp_module_detection(phy, params);
8439 if (phy->req_line_speed == SPEED_1000) {
8440 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8441 bnx2x_cl45_write(bp, phy,
8442 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8443 bnx2x_cl45_write(bp, phy,
8444 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8445 bnx2x_cl45_write(bp, phy,
8446 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8447 bnx2x_cl45_write(bp, phy,
8448 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8450 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8451 (phy->speed_cap_mask &
8452 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8453 ((phy->speed_cap_mask &
8454 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8455 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8456 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8457 /* Set Flow control */
8458 bnx2x_ext_phy_set_pause(params, phy, vars);
8459 bnx2x_cl45_write(bp, phy,
8460 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8461 bnx2x_cl45_write(bp, phy,
8462 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8463 bnx2x_cl45_write(bp, phy,
8464 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8465 bnx2x_cl45_write(bp, phy,
8466 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8467 bnx2x_cl45_write(bp, phy,
8468 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8470 * Enable RX-ALARM control to receive interrupt for 1G speed
8473 bnx2x_cl45_write(bp, phy,
8474 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8475 bnx2x_cl45_write(bp, phy,
8476 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8479 } else { /* Default 10G. Set only LASI control */
8480 bnx2x_cl45_write(bp, phy,
8481 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8484 /* Set TX PreEmphasis if needed */
8485 if ((params->feature_config_flags &
8486 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8487 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8489 phy->tx_preemphasis[0],
8490 phy->tx_preemphasis[1]);
8491 bnx2x_cl45_write(bp, phy,
8493 MDIO_PMA_REG_8726_TX_CTRL1,
8494 phy->tx_preemphasis[0]);
8496 bnx2x_cl45_write(bp, phy,
8498 MDIO_PMA_REG_8726_TX_CTRL2,
8499 phy->tx_preemphasis[1]);
8506 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8507 struct link_params *params)
8509 struct bnx2x *bp = params->bp;
8510 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8511 /* Set serial boot control for external load */
8512 bnx2x_cl45_write(bp, phy,
8514 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8517 /******************************************************************/
8518 /* BCM8727 PHY SECTION */
8519 /******************************************************************/
8521 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8522 struct link_params *params, u8 mode)
8524 struct bnx2x *bp = params->bp;
8525 u16 led_mode_bitmask = 0;
8526 u16 gpio_pins_bitmask = 0;
8528 /* Only NOC flavor requires to set the LED specifically */
8529 if (!(phy->flags & FLAGS_NOC))
8532 case LED_MODE_FRONT_PANEL_OFF:
8534 led_mode_bitmask = 0;
8535 gpio_pins_bitmask = 0x03;
8538 led_mode_bitmask = 0;
8539 gpio_pins_bitmask = 0x02;
8542 led_mode_bitmask = 0x60;
8543 gpio_pins_bitmask = 0x11;
8546 bnx2x_cl45_read(bp, phy,
8548 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8551 val |= led_mode_bitmask;
8552 bnx2x_cl45_write(bp, phy,
8554 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8556 bnx2x_cl45_read(bp, phy,
8558 MDIO_PMA_REG_8727_GPIO_CTRL,
8561 val |= gpio_pins_bitmask;
8562 bnx2x_cl45_write(bp, phy,
8564 MDIO_PMA_REG_8727_GPIO_CTRL,
8567 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8568 struct link_params *params) {
8569 u32 swap_val, swap_override;
8572 * The PHY reset is controlled by GPIO 1. Fake the port number
8573 * to cancel the swap done in set_gpio()
8575 struct bnx2x *bp = params->bp;
8576 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8577 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8578 port = (swap_val && swap_override) ^ 1;
8579 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8580 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8583 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8584 struct link_params *params,
8585 struct link_vars *vars)
8588 u16 tmp1, val, mod_abs, tmp2;
8589 u16 rx_alarm_ctrl_val;
8591 struct bnx2x *bp = params->bp;
8592 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8594 /* SPF+ PHY: Set flag to check for Tx error */
8595 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8597 bnx2x_wait_reset_complete(bp, phy, params);
8598 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8599 /* Should be 0x6 to enable XS on Tx side. */
8600 lasi_ctrl_val = 0x0006;
8602 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8604 bnx2x_cl45_write(bp, phy,
8605 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8607 bnx2x_cl45_write(bp, phy,
8608 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8610 bnx2x_cl45_write(bp, phy,
8611 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8614 * Initially configure MOD_ABS to interrupt when module is
8617 bnx2x_cl45_read(bp, phy,
8618 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8620 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8621 * When the EDC is off it locks onto a reference clock and avoids
8625 if (!(phy->flags & FLAGS_NOC))
8627 bnx2x_cl45_write(bp, phy,
8628 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8631 /* Enable/Disable PHY transmitter output */
8632 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8634 /* Make MOD_ABS give interrupt on change */
8635 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8638 if (phy->flags & FLAGS_NOC)
8642 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8643 * status which reflect SFP+ module over-current
8645 if (!(phy->flags & FLAGS_NOC))
8646 val &= 0xff8f; /* Reset bits 4-6 */
8647 bnx2x_cl45_write(bp, phy,
8648 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8650 bnx2x_8727_power_module(bp, phy, 1);
8652 bnx2x_cl45_read(bp, phy,
8653 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8655 bnx2x_cl45_read(bp, phy,
8656 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8658 /* Set option 1G speed */
8659 if (phy->req_line_speed == SPEED_1000) {
8660 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8661 bnx2x_cl45_write(bp, phy,
8662 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8663 bnx2x_cl45_write(bp, phy,
8664 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8665 bnx2x_cl45_read(bp, phy,
8666 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8667 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8669 * Power down the XAUI until link is up in case of dual-media
8672 if (DUAL_MEDIA(params)) {
8673 bnx2x_cl45_read(bp, phy,
8675 MDIO_PMA_REG_8727_PCS_GP, &val);
8677 bnx2x_cl45_write(bp, phy,
8679 MDIO_PMA_REG_8727_PCS_GP, val);
8681 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8682 ((phy->speed_cap_mask &
8683 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8684 ((phy->speed_cap_mask &
8685 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8686 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8688 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8689 bnx2x_cl45_write(bp, phy,
8690 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8691 bnx2x_cl45_write(bp, phy,
8692 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8695 * Since the 8727 has only single reset pin, need to set the 10G
8696 * registers although it is default
8698 bnx2x_cl45_write(bp, phy,
8699 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8701 bnx2x_cl45_write(bp, phy,
8702 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8703 bnx2x_cl45_write(bp, phy,
8704 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8705 bnx2x_cl45_write(bp, phy,
8706 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8711 * Set 2-wire transfer rate of SFP+ module EEPROM
8712 * to 100Khz since some DACs(direct attached cables) do
8713 * not work at 400Khz.
8715 bnx2x_cl45_write(bp, phy,
8716 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8719 /* Set TX PreEmphasis if needed */
8720 if ((params->feature_config_flags &
8721 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8722 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8723 phy->tx_preemphasis[0],
8724 phy->tx_preemphasis[1]);
8725 bnx2x_cl45_write(bp, phy,
8726 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8727 phy->tx_preemphasis[0]);
8729 bnx2x_cl45_write(bp, phy,
8730 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8731 phy->tx_preemphasis[1]);
8735 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8736 * power mode, if TX Laser is disabled
8738 tx_en_mode = REG_RD(bp, params->shmem_base +
8739 offsetof(struct shmem_region,
8740 dev_info.port_hw_config[params->port].sfp_ctrl))
8741 & PORT_HW_CFG_TX_LASER_MASK;
8743 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8745 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8746 bnx2x_cl45_read(bp, phy,
8747 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8750 bnx2x_cl45_write(bp, phy,
8751 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8757 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8758 struct link_params *params)
8760 struct bnx2x *bp = params->bp;
8761 u16 mod_abs, rx_alarm_status;
8762 u32 val = REG_RD(bp, params->shmem_base +
8763 offsetof(struct shmem_region, dev_info.
8764 port_feature_config[params->port].
8766 bnx2x_cl45_read(bp, phy,
8768 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8769 if (mod_abs & (1<<8)) {
8771 /* Module is absent */
8772 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8773 "show module is absent\n");
8774 phy->media_type = ETH_PHY_NOT_PRESENT;
8776 * 1. Set mod_abs to detect next module
8778 * 2. Set EDC off by setting OPTXLOS signal input to low
8780 * When the EDC is off it locks onto a reference clock and
8781 * avoids becoming 'lost'.
8784 if (!(phy->flags & FLAGS_NOC))
8786 bnx2x_cl45_write(bp, phy,
8788 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8791 * Clear RX alarm since it stays up as long as
8792 * the mod_abs wasn't changed
8794 bnx2x_cl45_read(bp, phy,
8796 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8799 /* Module is present */
8800 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8801 "show module is present\n");
8803 * First disable transmitter, and if the module is ok, the
8804 * module_detection will enable it
8805 * 1. Set mod_abs to detect next module absent event ( bit 8)
8806 * 2. Restore the default polarity of the OPRXLOS signal and
8807 * this signal will then correctly indicate the presence or
8808 * absence of the Rx signal. (bit 9)
8811 if (!(phy->flags & FLAGS_NOC))
8813 bnx2x_cl45_write(bp, phy,
8815 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8818 * Clear RX alarm since it stays up as long as the mod_abs
8819 * wasn't changed. This is need to be done before calling the
8820 * module detection, otherwise it will clear* the link update
8823 bnx2x_cl45_read(bp, phy,
8825 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8828 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8829 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8830 bnx2x_sfp_set_transmitter(params, phy, 0);
8832 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8833 bnx2x_sfp_module_detection(phy, params);
8835 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8838 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8840 /* No need to check link status in case of module plugged in/out */
8843 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8844 struct link_params *params,
8845 struct link_vars *vars)
8848 struct bnx2x *bp = params->bp;
8849 u8 link_up = 0, oc_port = params->port;
8850 u16 link_status = 0;
8851 u16 rx_alarm_status, lasi_ctrl, val1;
8853 /* If PHY is not initialized, do not check link status */
8854 bnx2x_cl45_read(bp, phy,
8855 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8860 /* Check the LASI on Rx */
8861 bnx2x_cl45_read(bp, phy,
8862 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8864 vars->line_speed = 0;
8865 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
8867 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8868 MDIO_PMA_LASI_TXCTRL);
8870 bnx2x_cl45_read(bp, phy,
8871 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8873 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8876 bnx2x_cl45_read(bp, phy,
8877 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8880 * If a module is present and there is need to check
8883 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8884 /* Check over-current using 8727 GPIO0 input*/
8885 bnx2x_cl45_read(bp, phy,
8886 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8889 if ((val1 & (1<<8)) == 0) {
8890 if (!CHIP_IS_E1x(bp))
8891 oc_port = BP_PATH(bp) + (params->port << 1);
8892 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8893 " on port %d\n", oc_port);
8894 netdev_err(bp->dev, "Error: Power fault on Port %d has"
8895 " been detected and the power to "
8896 "that SFP+ module has been removed"
8897 " to prevent failure of the card."
8898 " Please remove the SFP+ module and"
8899 " restart the system to clear this"
8902 /* Disable all RX_ALARMs except for mod_abs */
8903 bnx2x_cl45_write(bp, phy,
8905 MDIO_PMA_LASI_RXCTRL, (1<<5));
8907 bnx2x_cl45_read(bp, phy,
8909 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8910 /* Wait for module_absent_event */
8912 bnx2x_cl45_write(bp, phy,
8914 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8915 /* Clear RX alarm */
8916 bnx2x_cl45_read(bp, phy,
8918 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8921 } /* Over current check */
8923 /* When module absent bit is set, check module */
8924 if (rx_alarm_status & (1<<5)) {
8925 bnx2x_8727_handle_mod_abs(phy, params);
8926 /* Enable all mod_abs and link detection bits */
8927 bnx2x_cl45_write(bp, phy,
8928 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8931 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8932 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8933 /* If transmitter is disabled, ignore false link up indication */
8934 bnx2x_cl45_read(bp, phy,
8935 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8936 if (val1 & (1<<15)) {
8937 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8941 bnx2x_cl45_read(bp, phy,
8943 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8946 * Bits 0..2 --> speed detected,
8947 * Bits 13..15--> link is down
8949 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8951 vars->line_speed = SPEED_10000;
8952 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8954 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8956 vars->line_speed = SPEED_1000;
8957 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8961 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8965 /* Capture 10G link fault. */
8966 if (vars->line_speed == SPEED_10000) {
8967 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8968 MDIO_PMA_LASI_TXSTAT, &val1);
8970 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8971 MDIO_PMA_LASI_TXSTAT, &val1);
8973 if (val1 & (1<<0)) {
8974 vars->fault_detected = 1;
8979 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8980 vars->duplex = DUPLEX_FULL;
8981 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8984 if ((DUAL_MEDIA(params)) &&
8985 (phy->req_line_speed == SPEED_1000)) {
8986 bnx2x_cl45_read(bp, phy,
8988 MDIO_PMA_REG_8727_PCS_GP, &val1);
8990 * In case of dual-media board and 1G, power up the XAUI side,
8991 * otherwise power it down. For 10G it is done automatically
8997 bnx2x_cl45_write(bp, phy,
8999 MDIO_PMA_REG_8727_PCS_GP, val1);
9004 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9005 struct link_params *params)
9007 struct bnx2x *bp = params->bp;
9009 /* Enable/Disable PHY transmitter output */
9010 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9012 /* Disable Transmitter */
9013 bnx2x_sfp_set_transmitter(params, phy, 0);
9015 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9019 /******************************************************************/
9020 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9021 /******************************************************************/
9022 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9023 struct link_params *params)
9025 u16 val, fw_ver1, fw_ver2, cnt;
9027 struct bnx2x *bp = params->bp;
9029 port = params->port;
9031 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9032 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9033 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9034 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9035 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9036 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9037 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9039 for (cnt = 0; cnt < 100; cnt++) {
9040 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9046 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9047 bnx2x_save_spirom_version(bp, port, 0,
9053 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9054 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9055 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9056 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9057 for (cnt = 0; cnt < 100; cnt++) {
9058 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9064 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9065 bnx2x_save_spirom_version(bp, port, 0,
9070 /* lower 16 bits of the register SPI_FW_STATUS */
9071 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9072 /* upper 16 bits of register SPI_FW_STATUS */
9073 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9075 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9079 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9080 struct bnx2x_phy *phy)
9084 /* PHYC_CTL_LED_CTL */
9085 bnx2x_cl45_read(bp, phy,
9087 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9091 bnx2x_cl45_write(bp, phy,
9093 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9095 bnx2x_cl45_write(bp, phy,
9097 MDIO_PMA_REG_8481_LED1_MASK,
9100 bnx2x_cl45_write(bp, phy,
9102 MDIO_PMA_REG_8481_LED2_MASK,
9105 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9106 bnx2x_cl45_write(bp, phy,
9108 MDIO_PMA_REG_8481_LED3_MASK,
9111 /* Select the closest activity blink rate to that in 10/100/1000 */
9112 bnx2x_cl45_write(bp, phy,
9114 MDIO_PMA_REG_8481_LED3_BLINK,
9117 bnx2x_cl45_read(bp, phy,
9119 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9120 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9122 bnx2x_cl45_write(bp, phy,
9124 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9126 /* 'Interrupt Mask' */
9127 bnx2x_cl45_write(bp, phy,
9132 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9133 struct link_params *params,
9134 struct link_vars *vars)
9136 struct bnx2x *bp = params->bp;
9137 u16 autoneg_val, an_1000_val, an_10_100_val;
9138 u16 tmp_req_line_speed;
9140 tmp_req_line_speed = phy->req_line_speed;
9141 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9142 if (phy->req_line_speed == SPEED_10000)
9143 phy->req_line_speed = SPEED_AUTO_NEG;
9146 * This phy uses the NIG latch mechanism since link indication
9147 * arrives through its LED4 and not via its LASI signal, so we
9148 * get steady signal instead of clear on read
9150 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9151 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9153 bnx2x_cl45_write(bp, phy,
9154 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9156 bnx2x_848xx_set_led(bp, phy);
9158 /* set 1000 speed advertisement */
9159 bnx2x_cl45_read(bp, phy,
9160 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9163 bnx2x_ext_phy_set_pause(params, phy, vars);
9164 bnx2x_cl45_read(bp, phy,
9166 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9168 bnx2x_cl45_read(bp, phy,
9169 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9171 /* Disable forced speed */
9172 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9173 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9175 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176 (phy->speed_cap_mask &
9177 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9178 (phy->req_line_speed == SPEED_1000)) {
9179 an_1000_val |= (1<<8);
9180 autoneg_val |= (1<<9 | 1<<12);
9181 if (phy->req_duplex == DUPLEX_FULL)
9182 an_1000_val |= (1<<9);
9183 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9185 an_1000_val &= ~((1<<8) | (1<<9));
9187 bnx2x_cl45_write(bp, phy,
9188 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9191 /* set 100 speed advertisement */
9192 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9193 (phy->speed_cap_mask &
9194 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9197 (SUPPORTED_100baseT_Half |
9198 SUPPORTED_100baseT_Full)))) {
9199 an_10_100_val |= (1<<7);
9200 /* Enable autoneg and restart autoneg for legacy speeds */
9201 autoneg_val |= (1<<9 | 1<<12);
9203 if (phy->req_duplex == DUPLEX_FULL)
9204 an_10_100_val |= (1<<8);
9205 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9207 /* set 10 speed advertisement */
9208 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9209 (phy->speed_cap_mask &
9210 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9211 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9213 (SUPPORTED_10baseT_Half |
9214 SUPPORTED_10baseT_Full)))) {
9215 an_10_100_val |= (1<<5);
9216 autoneg_val |= (1<<9 | 1<<12);
9217 if (phy->req_duplex == DUPLEX_FULL)
9218 an_10_100_val |= (1<<6);
9219 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9222 /* Only 10/100 are allowed to work in FORCE mode */
9223 if ((phy->req_line_speed == SPEED_100) &&
9225 (SUPPORTED_100baseT_Half |
9226 SUPPORTED_100baseT_Full))) {
9227 autoneg_val |= (1<<13);
9228 /* Enabled AUTO-MDIX when autoneg is disabled */
9229 bnx2x_cl45_write(bp, phy,
9230 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9231 (1<<15 | 1<<9 | 7<<0));
9232 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9234 if ((phy->req_line_speed == SPEED_10) &&
9236 (SUPPORTED_10baseT_Half |
9237 SUPPORTED_10baseT_Full))) {
9238 /* Enabled AUTO-MDIX when autoneg is disabled */
9239 bnx2x_cl45_write(bp, phy,
9240 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9241 (1<<15 | 1<<9 | 7<<0));
9242 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9245 bnx2x_cl45_write(bp, phy,
9246 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9249 if (phy->req_duplex == DUPLEX_FULL)
9250 autoneg_val |= (1<<8);
9252 bnx2x_cl45_write(bp, phy,
9254 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9256 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9257 (phy->speed_cap_mask &
9258 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9259 (phy->req_line_speed == SPEED_10000)) {
9260 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9261 /* Restart autoneg for 10G*/
9263 bnx2x_cl45_write(bp, phy,
9264 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9266 } else if (phy->req_line_speed != SPEED_10 &&
9267 phy->req_line_speed != SPEED_100) {
9268 bnx2x_cl45_write(bp, phy,
9270 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9273 /* Save spirom version */
9274 bnx2x_save_848xx_spirom_version(phy, params);
9276 phy->req_line_speed = tmp_req_line_speed;
9281 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9282 struct link_params *params,
9283 struct link_vars *vars)
9285 struct bnx2x *bp = params->bp;
9286 /* Restore normal power mode*/
9287 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9288 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9291 bnx2x_ext_phy_hw_reset(bp, params->port);
9292 bnx2x_wait_reset_complete(bp, phy, params);
9294 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9295 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9299 #define PHY84833_HDSHK_WAIT 300
9300 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9301 struct link_params *params,
9302 struct link_vars *vars)
9308 struct bnx2x *bp = params->bp;
9311 /* Check for configuration. */
9312 pair_swap = REG_RD(bp, params->shmem_base +
9313 offsetof(struct shmem_region,
9314 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9315 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9320 data = (u16)pair_swap;
9322 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9323 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9324 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9325 PHY84833_CMD_OPEN_OVERRIDE);
9326 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9327 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9328 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9329 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9333 if (idx >= PHY84833_HDSHK_WAIT) {
9334 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9338 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9339 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9341 /* Issue pair swap command */
9342 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9343 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9344 PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9345 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9346 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9347 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9348 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9349 (val == PHY84833_CMD_COMPLETE_ERROR))
9353 if ((idx >= PHY84833_HDSHK_WAIT) ||
9354 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9355 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9358 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9359 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9360 PHY84833_CMD_CLEAR_COMPLETE);
9361 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9366 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9367 u32 shmem_base_path[],
9373 if (CHIP_IS_E3(bp)) {
9374 /* Assume that these will be GPIOs, not EPIOs. */
9375 for (idx = 0; idx < 2; idx++) {
9376 /* Map config param to register bit. */
9377 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9378 offsetof(struct shmem_region,
9379 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9380 reset_pin[idx] = (reset_pin[idx] &
9381 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9382 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9383 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9384 reset_pin[idx] = (1 << reset_pin[idx]);
9386 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9388 /* E2, look from diff place of shmem. */
9389 for (idx = 0; idx < 2; idx++) {
9390 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9391 offsetof(struct shmem_region,
9392 dev_info.port_hw_config[0].default_cfg));
9393 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9394 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9395 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9396 reset_pin[idx] = (1 << reset_pin[idx]);
9398 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9404 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9405 struct link_params *params)
9407 struct bnx2x *bp = params->bp;
9409 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9410 offsetof(struct shmem2_region,
9411 other_shmem_base_addr));
9413 u32 shmem_base_path[2];
9414 shmem_base_path[0] = params->shmem_base;
9415 shmem_base_path[1] = other_shmem_base_addr;
9417 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9420 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9422 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9428 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9429 u32 shmem_base_path[],
9434 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9436 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9438 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9440 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9446 #define PHY84833_CONSTANT_LATENCY 1193
9447 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9448 struct link_params *params,
9449 struct link_vars *vars)
9451 struct bnx2x *bp = params->bp;
9452 u8 port, initialize = 1;
9455 u32 actual_phy_selection, cms_enable, idx;
9460 if (!(CHIP_IS_E1(bp)))
9463 port = params->port;
9465 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9466 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9467 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9471 bnx2x_cl45_write(bp, phy,
9473 MDIO_PMA_REG_CTRL, 0x8000);
9474 /* Bring PHY out of super isolate mode */
9475 bnx2x_cl45_read(bp, phy,
9477 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9478 val &= ~MDIO_84833_SUPER_ISOLATE;
9479 bnx2x_cl45_write(bp, phy,
9481 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9484 bnx2x_wait_reset_complete(bp, phy, params);
9486 /* Wait for GPHY to come out of reset */
9489 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9490 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9493 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9495 temp = vars->line_speed;
9496 vars->line_speed = SPEED_10000;
9497 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
9498 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
9499 vars->line_speed = temp;
9501 /* Set dual-media configuration according to configuration */
9503 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9504 MDIO_CTL_REG_84823_MEDIA, &val);
9505 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9506 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9507 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9508 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9509 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9511 if (CHIP_IS_E3(bp)) {
9512 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9513 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9515 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9516 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9519 actual_phy_selection = bnx2x_phy_selection(params);
9521 switch (actual_phy_selection) {
9522 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9523 /* Do nothing. Essentially this is like the priority copper */
9525 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9526 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9528 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9529 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9531 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9532 /* Do nothing here. The first PHY won't be initialized at all */
9534 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9535 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9539 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9540 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9542 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9543 MDIO_CTL_REG_84823_MEDIA, val);
9544 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9545 params->multi_phy_config, val);
9548 if (params->feature_config_flags &
9549 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9550 /* Ensure that f/w is ready */
9551 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9552 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9553 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9554 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9556 usleep_range(1000, 1000);
9558 if (idx >= PHY84833_HDSHK_WAIT) {
9559 DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9563 /* Select EEE mode */
9564 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9565 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9568 /* Set Idle and Latency */
9569 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9570 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9571 PHY84833_CONSTANT_LATENCY + 1);
9573 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9574 MDIO_84833_TOP_CFG_DATA3_REG,
9575 PHY84833_CONSTANT_LATENCY + 1);
9577 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9578 MDIO_84833_TOP_CFG_DATA4_REG,
9579 PHY84833_CONSTANT_LATENCY);
9581 /* Send EEE instruction to command register */
9582 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9583 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9584 PHY84833_DIAG_CMD_SET_EEE_MODE);
9586 /* Ensure that the command has completed */
9587 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9588 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9589 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9590 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9591 (val == PHY84833_CMD_COMPLETE_ERROR))
9593 usleep_range(1000, 1000);
9595 if ((idx >= PHY84833_HDSHK_WAIT) ||
9596 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9597 DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9601 /* Reset command handler */
9602 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9603 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9604 PHY84833_CMD_CLEAR_COMPLETE);
9608 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9610 bnx2x_save_848xx_spirom_version(phy, params);
9611 /* 84833 PHY has a better feature and doesn't need to support this. */
9612 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9613 cms_enable = REG_RD(bp, params->shmem_base +
9614 offsetof(struct shmem_region,
9615 dev_info.port_hw_config[params->port].default_cfg)) &
9616 PORT_HW_CFG_ENABLE_CMS_MASK;
9618 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9619 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9621 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9623 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9624 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9625 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9631 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9632 struct link_params *params,
9633 struct link_vars *vars)
9635 struct bnx2x *bp = params->bp;
9636 u16 val, val1, val2;
9640 /* Check 10G-BaseT link status */
9641 /* Check PMD signal ok */
9642 bnx2x_cl45_read(bp, phy,
9643 MDIO_AN_DEVAD, 0xFFFA, &val1);
9644 bnx2x_cl45_read(bp, phy,
9645 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9647 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9649 /* Check link 10G */
9650 if (val2 & (1<<11)) {
9651 vars->line_speed = SPEED_10000;
9652 vars->duplex = DUPLEX_FULL;
9654 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9655 } else { /* Check Legacy speed link */
9656 u16 legacy_status, legacy_speed;
9658 /* Enable expansion register 0x42 (Operation mode status) */
9659 bnx2x_cl45_write(bp, phy,
9661 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9663 /* Get legacy speed operation status */
9664 bnx2x_cl45_read(bp, phy,
9666 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9669 DP(NETIF_MSG_LINK, "Legacy speed status"
9670 " = 0x%x\n", legacy_status);
9671 link_up = ((legacy_status & (1<<11)) == (1<<11));
9673 legacy_speed = (legacy_status & (3<<9));
9674 if (legacy_speed == (0<<9))
9675 vars->line_speed = SPEED_10;
9676 else if (legacy_speed == (1<<9))
9677 vars->line_speed = SPEED_100;
9678 else if (legacy_speed == (2<<9))
9679 vars->line_speed = SPEED_1000;
9680 else /* Should not happen */
9681 vars->line_speed = 0;
9683 if (legacy_status & (1<<8))
9684 vars->duplex = DUPLEX_FULL;
9686 vars->duplex = DUPLEX_HALF;
9688 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9689 " is_duplex_full= %d\n", vars->line_speed,
9690 (vars->duplex == DUPLEX_FULL));
9691 /* Check legacy speed AN resolution */
9692 bnx2x_cl45_read(bp, phy,
9694 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9697 vars->link_status |=
9698 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9699 bnx2x_cl45_read(bp, phy,
9701 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9703 if ((val & (1<<0)) == 0)
9704 vars->link_status |=
9705 LINK_STATUS_PARALLEL_DETECTION_USED;
9709 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9711 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9718 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9722 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9723 status = bnx2x_format_ver(spirom_ver, str, len);
9727 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9728 struct link_params *params)
9730 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9731 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9732 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9733 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9736 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9737 struct link_params *params)
9739 bnx2x_cl45_write(params->bp, phy,
9740 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9741 bnx2x_cl45_write(params->bp, phy,
9742 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9745 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9746 struct link_params *params)
9748 struct bnx2x *bp = params->bp;
9752 if (!(CHIP_IS_E1(bp)))
9755 port = params->port;
9757 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9758 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9759 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9762 bnx2x_cl45_read(bp, phy,
9765 /* Put to low power mode on newer FW */
9766 if ((val16 & 0x303f) > 0x1009)
9767 bnx2x_cl45_write(bp, phy,
9769 MDIO_PMA_REG_CTRL, 0x800);
9773 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9774 struct link_params *params, u8 mode)
9776 struct bnx2x *bp = params->bp;
9780 if (!(CHIP_IS_E1(bp)))
9783 port = params->port;
9788 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9790 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9791 SHARED_HW_CFG_LED_EXTPHY1) {
9794 bnx2x_cl45_write(bp, phy,
9796 MDIO_PMA_REG_8481_LED1_MASK,
9799 bnx2x_cl45_write(bp, phy,
9801 MDIO_PMA_REG_8481_LED2_MASK,
9804 bnx2x_cl45_write(bp, phy,
9806 MDIO_PMA_REG_8481_LED3_MASK,
9809 bnx2x_cl45_write(bp, phy,
9811 MDIO_PMA_REG_8481_LED5_MASK,
9815 bnx2x_cl45_write(bp, phy,
9817 MDIO_PMA_REG_8481_LED1_MASK,
9821 case LED_MODE_FRONT_PANEL_OFF:
9823 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9826 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9827 SHARED_HW_CFG_LED_EXTPHY1) {
9830 bnx2x_cl45_write(bp, phy,
9832 MDIO_PMA_REG_8481_LED1_MASK,
9835 bnx2x_cl45_write(bp, phy,
9837 MDIO_PMA_REG_8481_LED2_MASK,
9840 bnx2x_cl45_write(bp, phy,
9842 MDIO_PMA_REG_8481_LED3_MASK,
9845 bnx2x_cl45_write(bp, phy,
9847 MDIO_PMA_REG_8481_LED5_MASK,
9851 bnx2x_cl45_write(bp, phy,
9853 MDIO_PMA_REG_8481_LED1_MASK,
9859 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9861 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9862 SHARED_HW_CFG_LED_EXTPHY1) {
9863 /* Set control reg */
9864 bnx2x_cl45_read(bp, phy,
9866 MDIO_PMA_REG_8481_LINK_SIGNAL,
9871 bnx2x_cl45_write(bp, phy,
9873 MDIO_PMA_REG_8481_LINK_SIGNAL,
9877 bnx2x_cl45_write(bp, phy,
9879 MDIO_PMA_REG_8481_LED1_MASK,
9882 bnx2x_cl45_write(bp, phy,
9884 MDIO_PMA_REG_8481_LED2_MASK,
9887 bnx2x_cl45_write(bp, phy,
9889 MDIO_PMA_REG_8481_LED3_MASK,
9892 bnx2x_cl45_write(bp, phy,
9894 MDIO_PMA_REG_8481_LED5_MASK,
9897 bnx2x_cl45_write(bp, phy,
9899 MDIO_PMA_REG_8481_LED1_MASK,
9906 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9908 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9909 SHARED_HW_CFG_LED_EXTPHY1) {
9911 /* Set control reg */
9912 bnx2x_cl45_read(bp, phy,
9914 MDIO_PMA_REG_8481_LINK_SIGNAL,
9918 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9919 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9920 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9921 bnx2x_cl45_write(bp, phy,
9923 MDIO_PMA_REG_8481_LINK_SIGNAL,
9928 bnx2x_cl45_write(bp, phy,
9930 MDIO_PMA_REG_8481_LED1_MASK,
9933 bnx2x_cl45_write(bp, phy,
9935 MDIO_PMA_REG_8481_LED2_MASK,
9938 bnx2x_cl45_write(bp, phy,
9940 MDIO_PMA_REG_8481_LED3_MASK,
9943 bnx2x_cl45_write(bp, phy,
9945 MDIO_PMA_REG_8481_LED5_MASK,
9949 bnx2x_cl45_write(bp, phy,
9951 MDIO_PMA_REG_8481_LED1_MASK,
9954 /* Tell LED3 to blink on source */
9955 bnx2x_cl45_read(bp, phy,
9957 MDIO_PMA_REG_8481_LINK_SIGNAL,
9960 val |= (1<<6); /* A83B[8:6]= 1 */
9961 bnx2x_cl45_write(bp, phy,
9963 MDIO_PMA_REG_8481_LINK_SIGNAL,
9970 * This is a workaround for E3+84833 until autoneg
9971 * restart is fixed in f/w
9973 if (CHIP_IS_E3(bp)) {
9974 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9975 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9979 /******************************************************************/
9980 /* 54618SE PHY SECTION */
9981 /******************************************************************/
9982 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
9983 struct link_params *params,
9984 struct link_vars *vars)
9986 struct bnx2x *bp = params->bp;
9988 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9991 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
9992 usleep_range(1000, 1000);
9994 /* This works with E3 only, no need to check the chip
9995 before determining the port. */
9996 port = params->port;
9998 cfg_pin = (REG_RD(bp, params->shmem_base +
9999 offsetof(struct shmem_region,
10000 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10001 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10002 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10004 /* Drive pin high to bring the GPHY out of reset. */
10005 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10007 /* wait for GPHY to reset */
10011 bnx2x_cl22_write(bp, phy,
10012 MDIO_PMA_REG_CTRL, 0x8000);
10013 bnx2x_wait_reset_complete(bp, phy, params);
10015 /*wait for GPHY to reset */
10018 /* Configure LED4: set to INTR (0x6). */
10019 /* Accessing shadow register 0xe. */
10020 bnx2x_cl22_write(bp, phy,
10021 MDIO_REG_GPHY_SHADOW,
10022 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10023 bnx2x_cl22_read(bp, phy,
10024 MDIO_REG_GPHY_SHADOW,
10026 temp &= ~(0xf << 4);
10027 temp |= (0x6 << 4);
10028 bnx2x_cl22_write(bp, phy,
10029 MDIO_REG_GPHY_SHADOW,
10030 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10031 /* Configure INTR based on link status change. */
10032 bnx2x_cl22_write(bp, phy,
10033 MDIO_REG_INTR_MASK,
10034 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10036 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10037 bnx2x_cl22_write(bp, phy,
10038 MDIO_REG_GPHY_SHADOW,
10039 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10040 bnx2x_cl22_read(bp, phy,
10041 MDIO_REG_GPHY_SHADOW,
10043 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10044 bnx2x_cl22_write(bp, phy,
10045 MDIO_REG_GPHY_SHADOW,
10046 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10049 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10050 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10052 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10053 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10054 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10056 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10057 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10058 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10060 /* read all advertisement */
10061 bnx2x_cl22_read(bp, phy,
10065 bnx2x_cl22_read(bp, phy,
10069 bnx2x_cl22_read(bp, phy,
10073 /* Disable forced speed */
10074 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10075 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10078 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10079 (phy->speed_cap_mask &
10080 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10081 (phy->req_line_speed == SPEED_1000)) {
10082 an_1000_val |= (1<<8);
10083 autoneg_val |= (1<<9 | 1<<12);
10084 if (phy->req_duplex == DUPLEX_FULL)
10085 an_1000_val |= (1<<9);
10086 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10088 an_1000_val &= ~((1<<8) | (1<<9));
10090 bnx2x_cl22_write(bp, phy,
10093 bnx2x_cl22_read(bp, phy,
10097 /* set 100 speed advertisement */
10098 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10099 (phy->speed_cap_mask &
10100 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10101 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10102 an_10_100_val |= (1<<7);
10103 /* Enable autoneg and restart autoneg for legacy speeds */
10104 autoneg_val |= (1<<9 | 1<<12);
10106 if (phy->req_duplex == DUPLEX_FULL)
10107 an_10_100_val |= (1<<8);
10108 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10111 /* set 10 speed advertisement */
10112 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10113 (phy->speed_cap_mask &
10114 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10115 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10116 an_10_100_val |= (1<<5);
10117 autoneg_val |= (1<<9 | 1<<12);
10118 if (phy->req_duplex == DUPLEX_FULL)
10119 an_10_100_val |= (1<<6);
10120 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10123 /* Only 10/100 are allowed to work in FORCE mode */
10124 if (phy->req_line_speed == SPEED_100) {
10125 autoneg_val |= (1<<13);
10126 /* Enabled AUTO-MDIX when autoneg is disabled */
10127 bnx2x_cl22_write(bp, phy,
10129 (1<<15 | 1<<9 | 7<<0));
10130 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10132 if (phy->req_line_speed == SPEED_10) {
10133 /* Enabled AUTO-MDIX when autoneg is disabled */
10134 bnx2x_cl22_write(bp, phy,
10136 (1<<15 | 1<<9 | 7<<0));
10137 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10140 /* Check if we should turn on Auto-GrEEEn */
10141 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10142 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10143 if (params->feature_config_flags &
10144 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10146 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10149 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10151 bnx2x_cl22_write(bp, phy,
10152 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10153 bnx2x_cl22_write(bp, phy,
10154 MDIO_REG_GPHY_CL45_DATA_REG,
10155 MDIO_REG_GPHY_EEE_ADV);
10156 bnx2x_cl22_write(bp, phy,
10157 MDIO_REG_GPHY_CL45_ADDR_REG,
10158 (0x1 << 14) | MDIO_AN_DEVAD);
10159 bnx2x_cl22_write(bp, phy,
10160 MDIO_REG_GPHY_CL45_DATA_REG,
10164 bnx2x_cl22_write(bp, phy,
10166 an_10_100_val | fc_val);
10168 if (phy->req_duplex == DUPLEX_FULL)
10169 autoneg_val |= (1<<8);
10171 bnx2x_cl22_write(bp, phy,
10172 MDIO_PMA_REG_CTRL, autoneg_val);
10177 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10178 struct link_params *params, u8 mode)
10180 struct bnx2x *bp = params->bp;
10181 DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10183 case LED_MODE_FRONT_PANEL_OFF:
10185 case LED_MODE_OPER:
10193 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10194 struct link_params *params)
10196 struct bnx2x *bp = params->bp;
10200 /* This works with E3 only, no need to check the chip
10201 before determining the port. */
10202 port = params->port;
10203 cfg_pin = (REG_RD(bp, params->shmem_base +
10204 offsetof(struct shmem_region,
10205 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10206 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10207 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10209 /* Drive pin low to put GPHY in reset. */
10210 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10213 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10214 struct link_params *params,
10215 struct link_vars *vars)
10217 struct bnx2x *bp = params->bp;
10220 u16 legacy_status, legacy_speed;
10222 /* Get speed operation status */
10223 bnx2x_cl22_read(bp, phy,
10226 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10228 /* Read status to clear the PHY interrupt. */
10229 bnx2x_cl22_read(bp, phy,
10230 MDIO_REG_INTR_STATUS,
10233 link_up = ((legacy_status & (1<<2)) == (1<<2));
10236 legacy_speed = (legacy_status & (7<<8));
10237 if (legacy_speed == (7<<8)) {
10238 vars->line_speed = SPEED_1000;
10239 vars->duplex = DUPLEX_FULL;
10240 } else if (legacy_speed == (6<<8)) {
10241 vars->line_speed = SPEED_1000;
10242 vars->duplex = DUPLEX_HALF;
10243 } else if (legacy_speed == (5<<8)) {
10244 vars->line_speed = SPEED_100;
10245 vars->duplex = DUPLEX_FULL;
10247 /* Omitting 100Base-T4 for now */
10248 else if (legacy_speed == (3<<8)) {
10249 vars->line_speed = SPEED_100;
10250 vars->duplex = DUPLEX_HALF;
10251 } else if (legacy_speed == (2<<8)) {
10252 vars->line_speed = SPEED_10;
10253 vars->duplex = DUPLEX_FULL;
10254 } else if (legacy_speed == (1<<8)) {
10255 vars->line_speed = SPEED_10;
10256 vars->duplex = DUPLEX_HALF;
10257 } else /* Should not happen */
10258 vars->line_speed = 0;
10260 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10261 " is_duplex_full= %d\n", vars->line_speed,
10262 (vars->duplex == DUPLEX_FULL));
10264 /* Check legacy speed AN resolution */
10265 bnx2x_cl22_read(bp, phy,
10269 vars->link_status |=
10270 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10271 bnx2x_cl22_read(bp, phy,
10274 if ((val & (1<<0)) == 0)
10275 vars->link_status |=
10276 LINK_STATUS_PARALLEL_DETECTION_USED;
10278 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10281 /* Report whether EEE is resolved. */
10282 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10283 if (val == MDIO_REG_GPHY_ID_54618SE) {
10284 if (vars->link_status &
10285 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10288 bnx2x_cl22_write(bp, phy,
10289 MDIO_REG_GPHY_CL45_ADDR_REG,
10291 bnx2x_cl22_write(bp, phy,
10292 MDIO_REG_GPHY_CL45_DATA_REG,
10293 MDIO_REG_GPHY_EEE_RESOLVED);
10294 bnx2x_cl22_write(bp, phy,
10295 MDIO_REG_GPHY_CL45_ADDR_REG,
10296 (0x1 << 14) | MDIO_AN_DEVAD);
10297 bnx2x_cl22_read(bp, phy,
10298 MDIO_REG_GPHY_CL45_DATA_REG,
10301 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10304 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10309 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10310 struct link_params *params)
10312 struct bnx2x *bp = params->bp;
10314 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10316 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10318 /* Enable master/slave manual mmode and set to master */
10319 /* mii write 9 [bits set 11 12] */
10320 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10322 /* forced 1G and disable autoneg */
10323 /* set val [mii read 0] */
10324 /* set val [expr $val & [bits clear 6 12 13]] */
10325 /* set val [expr $val | [bits set 6 8]] */
10326 /* mii write 0 $val */
10327 bnx2x_cl22_read(bp, phy, 0x00, &val);
10328 val &= ~((1<<6) | (1<<12) | (1<<13));
10329 val |= (1<<6) | (1<<8);
10330 bnx2x_cl22_write(bp, phy, 0x00, val);
10332 /* Set external loopback and Tx using 6dB coding */
10333 /* mii write 0x18 7 */
10334 /* set val [mii read 0x18] */
10335 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10336 bnx2x_cl22_write(bp, phy, 0x18, 7);
10337 bnx2x_cl22_read(bp, phy, 0x18, &val);
10338 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10340 /* This register opens the gate for the UMAC despite its name */
10341 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10344 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10345 * length used by the MAC receive logic to check frames.
10347 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10350 /******************************************************************/
10351 /* SFX7101 PHY SECTION */
10352 /******************************************************************/
10353 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10354 struct link_params *params)
10356 struct bnx2x *bp = params->bp;
10357 /* SFX7101_XGXS_TEST1 */
10358 bnx2x_cl45_write(bp, phy,
10359 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10362 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10363 struct link_params *params,
10364 struct link_vars *vars)
10366 u16 fw_ver1, fw_ver2, val;
10367 struct bnx2x *bp = params->bp;
10368 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10370 /* Restore normal power mode*/
10371 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10372 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10374 bnx2x_ext_phy_hw_reset(bp, params->port);
10375 bnx2x_wait_reset_complete(bp, phy, params);
10377 bnx2x_cl45_write(bp, phy,
10378 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10379 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10380 bnx2x_cl45_write(bp, phy,
10381 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10383 bnx2x_ext_phy_set_pause(params, phy, vars);
10384 /* Restart autoneg */
10385 bnx2x_cl45_read(bp, phy,
10386 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10388 bnx2x_cl45_write(bp, phy,
10389 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10391 /* Save spirom version */
10392 bnx2x_cl45_read(bp, phy,
10393 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10395 bnx2x_cl45_read(bp, phy,
10396 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10397 bnx2x_save_spirom_version(bp, params->port,
10398 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10402 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10403 struct link_params *params,
10404 struct link_vars *vars)
10406 struct bnx2x *bp = params->bp;
10409 bnx2x_cl45_read(bp, phy,
10410 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10411 bnx2x_cl45_read(bp, phy,
10412 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10413 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10415 bnx2x_cl45_read(bp, phy,
10416 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10417 bnx2x_cl45_read(bp, phy,
10418 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10419 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10421 link_up = ((val1 & 4) == 4);
10422 /* if link is up print the AN outcome of the SFX7101 PHY */
10424 bnx2x_cl45_read(bp, phy,
10425 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10427 vars->line_speed = SPEED_10000;
10428 vars->duplex = DUPLEX_FULL;
10429 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10430 val2, (val2 & (1<<14)));
10431 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10432 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10437 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10441 str[0] = (spirom_ver & 0xFF);
10442 str[1] = (spirom_ver & 0xFF00) >> 8;
10443 str[2] = (spirom_ver & 0xFF0000) >> 16;
10444 str[3] = (spirom_ver & 0xFF000000) >> 24;
10450 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10454 bnx2x_cl45_read(bp, phy,
10456 MDIO_PMA_REG_7101_RESET, &val);
10458 for (cnt = 0; cnt < 10; cnt++) {
10460 /* Writes a self-clearing reset */
10461 bnx2x_cl45_write(bp, phy,
10463 MDIO_PMA_REG_7101_RESET,
10465 /* Wait for clear */
10466 bnx2x_cl45_read(bp, phy,
10468 MDIO_PMA_REG_7101_RESET, &val);
10470 if ((val & (1<<15)) == 0)
10475 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10476 struct link_params *params) {
10477 /* Low power mode is controlled by GPIO 2 */
10478 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10479 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10480 /* The PHY reset is controlled by GPIO 1 */
10481 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10482 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10485 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10486 struct link_params *params, u8 mode)
10489 struct bnx2x *bp = params->bp;
10491 case LED_MODE_FRONT_PANEL_OFF:
10498 case LED_MODE_OPER:
10502 bnx2x_cl45_write(bp, phy,
10504 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10508 /******************************************************************/
10509 /* STATIC PHY DECLARATION */
10510 /******************************************************************/
10512 static struct bnx2x_phy phy_null = {
10513 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10516 .flags = FLAGS_INIT_XGXS_FIRST,
10517 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10518 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10521 .media_type = ETH_PHY_NOT_PRESENT,
10523 .req_flow_ctrl = 0,
10524 .req_line_speed = 0,
10525 .speed_cap_mask = 0,
10528 .config_init = (config_init_t)NULL,
10529 .read_status = (read_status_t)NULL,
10530 .link_reset = (link_reset_t)NULL,
10531 .config_loopback = (config_loopback_t)NULL,
10532 .format_fw_ver = (format_fw_ver_t)NULL,
10533 .hw_reset = (hw_reset_t)NULL,
10534 .set_link_led = (set_link_led_t)NULL,
10535 .phy_specific_func = (phy_specific_func_t)NULL
10538 static struct bnx2x_phy phy_serdes = {
10539 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10543 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10544 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10546 .supported = (SUPPORTED_10baseT_Half |
10547 SUPPORTED_10baseT_Full |
10548 SUPPORTED_100baseT_Half |
10549 SUPPORTED_100baseT_Full |
10550 SUPPORTED_1000baseT_Full |
10551 SUPPORTED_2500baseX_Full |
10553 SUPPORTED_Autoneg |
10555 SUPPORTED_Asym_Pause),
10556 .media_type = ETH_PHY_BASE_T,
10558 .req_flow_ctrl = 0,
10559 .req_line_speed = 0,
10560 .speed_cap_mask = 0,
10563 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10564 .read_status = (read_status_t)bnx2x_link_settings_status,
10565 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10566 .config_loopback = (config_loopback_t)NULL,
10567 .format_fw_ver = (format_fw_ver_t)NULL,
10568 .hw_reset = (hw_reset_t)NULL,
10569 .set_link_led = (set_link_led_t)NULL,
10570 .phy_specific_func = (phy_specific_func_t)NULL
10573 static struct bnx2x_phy phy_xgxs = {
10574 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10578 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10579 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10581 .supported = (SUPPORTED_10baseT_Half |
10582 SUPPORTED_10baseT_Full |
10583 SUPPORTED_100baseT_Half |
10584 SUPPORTED_100baseT_Full |
10585 SUPPORTED_1000baseT_Full |
10586 SUPPORTED_2500baseX_Full |
10587 SUPPORTED_10000baseT_Full |
10589 SUPPORTED_Autoneg |
10591 SUPPORTED_Asym_Pause),
10592 .media_type = ETH_PHY_CX4,
10594 .req_flow_ctrl = 0,
10595 .req_line_speed = 0,
10596 .speed_cap_mask = 0,
10599 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10600 .read_status = (read_status_t)bnx2x_link_settings_status,
10601 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10602 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10603 .format_fw_ver = (format_fw_ver_t)NULL,
10604 .hw_reset = (hw_reset_t)NULL,
10605 .set_link_led = (set_link_led_t)NULL,
10606 .phy_specific_func = (phy_specific_func_t)NULL
10608 static struct bnx2x_phy phy_warpcore = {
10609 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10612 .flags = FLAGS_HW_LOCK_REQUIRED,
10613 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10614 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10616 .supported = (SUPPORTED_10baseT_Half |
10617 SUPPORTED_10baseT_Full |
10618 SUPPORTED_100baseT_Half |
10619 SUPPORTED_100baseT_Full |
10620 SUPPORTED_1000baseT_Full |
10621 SUPPORTED_10000baseT_Full |
10622 SUPPORTED_20000baseKR2_Full |
10623 SUPPORTED_20000baseMLD2_Full |
10625 SUPPORTED_Autoneg |
10627 SUPPORTED_Asym_Pause),
10628 .media_type = ETH_PHY_UNSPECIFIED,
10630 .req_flow_ctrl = 0,
10631 .req_line_speed = 0,
10632 .speed_cap_mask = 0,
10633 /* req_duplex = */0,
10635 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10636 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10637 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10638 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10639 .format_fw_ver = (format_fw_ver_t)NULL,
10640 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10641 .set_link_led = (set_link_led_t)NULL,
10642 .phy_specific_func = (phy_specific_func_t)NULL
10646 static struct bnx2x_phy phy_7101 = {
10647 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10650 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10651 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10652 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10654 .supported = (SUPPORTED_10000baseT_Full |
10656 SUPPORTED_Autoneg |
10658 SUPPORTED_Asym_Pause),
10659 .media_type = ETH_PHY_BASE_T,
10661 .req_flow_ctrl = 0,
10662 .req_line_speed = 0,
10663 .speed_cap_mask = 0,
10666 .config_init = (config_init_t)bnx2x_7101_config_init,
10667 .read_status = (read_status_t)bnx2x_7101_read_status,
10668 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10669 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10670 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10671 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10672 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10673 .phy_specific_func = (phy_specific_func_t)NULL
10675 static struct bnx2x_phy phy_8073 = {
10676 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10679 .flags = FLAGS_HW_LOCK_REQUIRED,
10680 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10681 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10683 .supported = (SUPPORTED_10000baseT_Full |
10684 SUPPORTED_2500baseX_Full |
10685 SUPPORTED_1000baseT_Full |
10687 SUPPORTED_Autoneg |
10689 SUPPORTED_Asym_Pause),
10690 .media_type = ETH_PHY_KR,
10692 .req_flow_ctrl = 0,
10693 .req_line_speed = 0,
10694 .speed_cap_mask = 0,
10697 .config_init = (config_init_t)bnx2x_8073_config_init,
10698 .read_status = (read_status_t)bnx2x_8073_read_status,
10699 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10700 .config_loopback = (config_loopback_t)NULL,
10701 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10702 .hw_reset = (hw_reset_t)NULL,
10703 .set_link_led = (set_link_led_t)NULL,
10704 .phy_specific_func = (phy_specific_func_t)NULL
10706 static struct bnx2x_phy phy_8705 = {
10707 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10710 .flags = FLAGS_INIT_XGXS_FIRST,
10711 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10712 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10714 .supported = (SUPPORTED_10000baseT_Full |
10717 SUPPORTED_Asym_Pause),
10718 .media_type = ETH_PHY_XFP_FIBER,
10720 .req_flow_ctrl = 0,
10721 .req_line_speed = 0,
10722 .speed_cap_mask = 0,
10725 .config_init = (config_init_t)bnx2x_8705_config_init,
10726 .read_status = (read_status_t)bnx2x_8705_read_status,
10727 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10728 .config_loopback = (config_loopback_t)NULL,
10729 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10730 .hw_reset = (hw_reset_t)NULL,
10731 .set_link_led = (set_link_led_t)NULL,
10732 .phy_specific_func = (phy_specific_func_t)NULL
10734 static struct bnx2x_phy phy_8706 = {
10735 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10738 .flags = FLAGS_INIT_XGXS_FIRST,
10739 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10740 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10742 .supported = (SUPPORTED_10000baseT_Full |
10743 SUPPORTED_1000baseT_Full |
10746 SUPPORTED_Asym_Pause),
10747 .media_type = ETH_PHY_SFP_FIBER,
10749 .req_flow_ctrl = 0,
10750 .req_line_speed = 0,
10751 .speed_cap_mask = 0,
10754 .config_init = (config_init_t)bnx2x_8706_config_init,
10755 .read_status = (read_status_t)bnx2x_8706_read_status,
10756 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10757 .config_loopback = (config_loopback_t)NULL,
10758 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10759 .hw_reset = (hw_reset_t)NULL,
10760 .set_link_led = (set_link_led_t)NULL,
10761 .phy_specific_func = (phy_specific_func_t)NULL
10764 static struct bnx2x_phy phy_8726 = {
10765 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10768 .flags = (FLAGS_HW_LOCK_REQUIRED |
10769 FLAGS_INIT_XGXS_FIRST),
10770 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10771 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10773 .supported = (SUPPORTED_10000baseT_Full |
10774 SUPPORTED_1000baseT_Full |
10775 SUPPORTED_Autoneg |
10778 SUPPORTED_Asym_Pause),
10779 .media_type = ETH_PHY_NOT_PRESENT,
10781 .req_flow_ctrl = 0,
10782 .req_line_speed = 0,
10783 .speed_cap_mask = 0,
10786 .config_init = (config_init_t)bnx2x_8726_config_init,
10787 .read_status = (read_status_t)bnx2x_8726_read_status,
10788 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
10789 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10790 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10791 .hw_reset = (hw_reset_t)NULL,
10792 .set_link_led = (set_link_led_t)NULL,
10793 .phy_specific_func = (phy_specific_func_t)NULL
10796 static struct bnx2x_phy phy_8727 = {
10797 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10800 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10801 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10802 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10804 .supported = (SUPPORTED_10000baseT_Full |
10805 SUPPORTED_1000baseT_Full |
10808 SUPPORTED_Asym_Pause),
10809 .media_type = ETH_PHY_NOT_PRESENT,
10811 .req_flow_ctrl = 0,
10812 .req_line_speed = 0,
10813 .speed_cap_mask = 0,
10816 .config_init = (config_init_t)bnx2x_8727_config_init,
10817 .read_status = (read_status_t)bnx2x_8727_read_status,
10818 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
10819 .config_loopback = (config_loopback_t)NULL,
10820 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10821 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
10822 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
10823 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10825 static struct bnx2x_phy phy_8481 = {
10826 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10829 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10830 FLAGS_REARM_LATCH_SIGNAL,
10831 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10832 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10834 .supported = (SUPPORTED_10baseT_Half |
10835 SUPPORTED_10baseT_Full |
10836 SUPPORTED_100baseT_Half |
10837 SUPPORTED_100baseT_Full |
10838 SUPPORTED_1000baseT_Full |
10839 SUPPORTED_10000baseT_Full |
10841 SUPPORTED_Autoneg |
10843 SUPPORTED_Asym_Pause),
10844 .media_type = ETH_PHY_BASE_T,
10846 .req_flow_ctrl = 0,
10847 .req_line_speed = 0,
10848 .speed_cap_mask = 0,
10851 .config_init = (config_init_t)bnx2x_8481_config_init,
10852 .read_status = (read_status_t)bnx2x_848xx_read_status,
10853 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
10854 .config_loopback = (config_loopback_t)NULL,
10855 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10856 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
10857 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10858 .phy_specific_func = (phy_specific_func_t)NULL
10861 static struct bnx2x_phy phy_84823 = {
10862 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10865 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10866 FLAGS_REARM_LATCH_SIGNAL,
10867 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10868 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10870 .supported = (SUPPORTED_10baseT_Half |
10871 SUPPORTED_10baseT_Full |
10872 SUPPORTED_100baseT_Half |
10873 SUPPORTED_100baseT_Full |
10874 SUPPORTED_1000baseT_Full |
10875 SUPPORTED_10000baseT_Full |
10877 SUPPORTED_Autoneg |
10879 SUPPORTED_Asym_Pause),
10880 .media_type = ETH_PHY_BASE_T,
10882 .req_flow_ctrl = 0,
10883 .req_line_speed = 0,
10884 .speed_cap_mask = 0,
10887 .config_init = (config_init_t)bnx2x_848x3_config_init,
10888 .read_status = (read_status_t)bnx2x_848xx_read_status,
10889 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10890 .config_loopback = (config_loopback_t)NULL,
10891 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10892 .hw_reset = (hw_reset_t)NULL,
10893 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10894 .phy_specific_func = (phy_specific_func_t)NULL
10897 static struct bnx2x_phy phy_84833 = {
10898 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10901 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10902 FLAGS_REARM_LATCH_SIGNAL,
10903 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10904 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10906 .supported = (SUPPORTED_100baseT_Half |
10907 SUPPORTED_100baseT_Full |
10908 SUPPORTED_1000baseT_Full |
10909 SUPPORTED_10000baseT_Full |
10911 SUPPORTED_Autoneg |
10913 SUPPORTED_Asym_Pause),
10914 .media_type = ETH_PHY_BASE_T,
10916 .req_flow_ctrl = 0,
10917 .req_line_speed = 0,
10918 .speed_cap_mask = 0,
10921 .config_init = (config_init_t)bnx2x_848x3_config_init,
10922 .read_status = (read_status_t)bnx2x_848xx_read_status,
10923 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10924 .config_loopback = (config_loopback_t)NULL,
10925 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10926 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10927 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10928 .phy_specific_func = (phy_specific_func_t)NULL
10931 static struct bnx2x_phy phy_54618se = {
10932 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10935 .flags = FLAGS_INIT_XGXS_FIRST,
10936 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10937 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10939 .supported = (SUPPORTED_10baseT_Half |
10940 SUPPORTED_10baseT_Full |
10941 SUPPORTED_100baseT_Half |
10942 SUPPORTED_100baseT_Full |
10943 SUPPORTED_1000baseT_Full |
10945 SUPPORTED_Autoneg |
10947 SUPPORTED_Asym_Pause),
10948 .media_type = ETH_PHY_BASE_T,
10950 .req_flow_ctrl = 0,
10951 .req_line_speed = 0,
10952 .speed_cap_mask = 0,
10953 /* req_duplex = */0,
10955 .config_init = (config_init_t)bnx2x_54618se_config_init,
10956 .read_status = (read_status_t)bnx2x_54618se_read_status,
10957 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
10958 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10959 .format_fw_ver = (format_fw_ver_t)NULL,
10960 .hw_reset = (hw_reset_t)NULL,
10961 .set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led,
10962 .phy_specific_func = (phy_specific_func_t)NULL
10964 /*****************************************************************/
10966 /* Populate the phy according. Main function: bnx2x_populate_phy */
10968 /*****************************************************************/
10970 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10971 struct bnx2x_phy *phy, u8 port,
10974 /* Get the 4 lanes xgxs config rx and tx */
10975 u32 rx = 0, tx = 0, i;
10976 for (i = 0; i < 2; i++) {
10978 * INT_PHY and EXT_PHY1 share the same value location in the
10979 * shmem. When num_phys is greater than 1, than this value
10980 * applies only to EXT_PHY1
10982 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10983 rx = REG_RD(bp, shmem_base +
10984 offsetof(struct shmem_region,
10985 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10987 tx = REG_RD(bp, shmem_base +
10988 offsetof(struct shmem_region,
10989 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10991 rx = REG_RD(bp, shmem_base +
10992 offsetof(struct shmem_region,
10993 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10995 tx = REG_RD(bp, shmem_base +
10996 offsetof(struct shmem_region,
10997 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11000 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11001 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11003 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11004 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11008 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11009 u8 phy_index, u8 port)
11011 u32 ext_phy_config = 0;
11012 switch (phy_index) {
11014 ext_phy_config = REG_RD(bp, shmem_base +
11015 offsetof(struct shmem_region,
11016 dev_info.port_hw_config[port].external_phy_config));
11019 ext_phy_config = REG_RD(bp, shmem_base +
11020 offsetof(struct shmem_region,
11021 dev_info.port_hw_config[port].external_phy_config2));
11024 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11028 return ext_phy_config;
11030 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11031 struct bnx2x_phy *phy)
11035 u32 switch_cfg = (REG_RD(bp, shmem_base +
11036 offsetof(struct shmem_region,
11037 dev_info.port_feature_config[port].link_config)) &
11038 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11039 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11040 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11041 if (USES_WARPCORE(bp)) {
11043 phy_addr = REG_RD(bp,
11044 MISC_REG_WC0_CTRL_PHY_ADDR);
11045 *phy = phy_warpcore;
11046 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11047 phy->flags |= FLAGS_4_PORT_MODE;
11049 phy->flags &= ~FLAGS_4_PORT_MODE;
11050 /* Check Dual mode */
11051 serdes_net_if = (REG_RD(bp, shmem_base +
11052 offsetof(struct shmem_region, dev_info.
11053 port_hw_config[port].default_cfg)) &
11054 PORT_HW_CFG_NET_SERDES_IF_MASK);
11056 * Set the appropriate supported and flags indications per
11057 * interface type of the chip
11059 switch (serdes_net_if) {
11060 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11061 phy->supported &= (SUPPORTED_10baseT_Half |
11062 SUPPORTED_10baseT_Full |
11063 SUPPORTED_100baseT_Half |
11064 SUPPORTED_100baseT_Full |
11065 SUPPORTED_1000baseT_Full |
11067 SUPPORTED_Autoneg |
11069 SUPPORTED_Asym_Pause);
11070 phy->media_type = ETH_PHY_BASE_T;
11072 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11073 phy->media_type = ETH_PHY_XFP_FIBER;
11075 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11076 phy->supported &= (SUPPORTED_1000baseT_Full |
11077 SUPPORTED_10000baseT_Full |
11080 SUPPORTED_Asym_Pause);
11081 phy->media_type = ETH_PHY_SFP_FIBER;
11083 case PORT_HW_CFG_NET_SERDES_IF_KR:
11084 phy->media_type = ETH_PHY_KR;
11085 phy->supported &= (SUPPORTED_1000baseT_Full |
11086 SUPPORTED_10000baseT_Full |
11088 SUPPORTED_Autoneg |
11090 SUPPORTED_Asym_Pause);
11092 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11093 phy->media_type = ETH_PHY_KR;
11094 phy->flags |= FLAGS_WC_DUAL_MODE;
11095 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11098 SUPPORTED_Asym_Pause);
11100 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11101 phy->media_type = ETH_PHY_KR;
11102 phy->flags |= FLAGS_WC_DUAL_MODE;
11103 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11106 SUPPORTED_Asym_Pause);
11109 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11115 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11116 * was not set as expected. For B0, ECO will be enabled so there
11117 * won't be an issue there
11119 if (CHIP_REV(bp) == CHIP_REV_Ax)
11120 phy->flags |= FLAGS_MDC_MDIO_WA;
11122 switch (switch_cfg) {
11123 case SWITCH_CFG_1G:
11124 phy_addr = REG_RD(bp,
11125 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11129 case SWITCH_CFG_10G:
11130 phy_addr = REG_RD(bp,
11131 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11136 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11140 phy->addr = (u8)phy_addr;
11141 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11142 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11144 if (CHIP_IS_E2(bp))
11145 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11147 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11149 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11150 port, phy->addr, phy->mdio_ctrl);
11152 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11156 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11161 struct bnx2x_phy *phy)
11163 u32 ext_phy_config, phy_type, config2;
11164 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11165 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11167 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11168 /* Select the phy type */
11169 switch (phy_type) {
11170 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11171 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11177 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11180 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11181 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11184 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11185 /* BCM8727_NOC => BCM8727 no over current */
11186 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11188 phy->flags |= FLAGS_NOC;
11190 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11192 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11198 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11204 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11205 *phy = phy_54618se;
11207 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11210 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11218 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11219 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11222 * The shmem address of the phy version is located on different
11223 * structures. In case this structure is too old, do not set
11226 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11227 dev_info.shared_hw_config.config2));
11228 if (phy_index == EXT_PHY1) {
11229 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11230 port_mb[port].ext_phy_fw_version);
11232 /* Check specific mdc mdio settings */
11233 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11234 mdc_mdio_access = config2 &
11235 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11237 u32 size = REG_RD(bp, shmem2_base);
11240 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11241 phy->ver_addr = shmem2_base +
11242 offsetof(struct shmem2_region,
11243 ext_phy_fw_version2[port]);
11245 /* Check specific mdc mdio settings */
11246 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11247 mdc_mdio_access = (config2 &
11248 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11249 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11250 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11252 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11255 * In case mdc/mdio_access of the external phy is different than the
11256 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11257 * to prevent one port interfere with another port's CL45 operations.
11259 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11260 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11261 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11262 phy_type, port, phy_index);
11263 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11264 phy->addr, phy->mdio_ctrl);
11268 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11269 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11272 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11273 if (phy_index == INT_PHY)
11274 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11275 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11280 static void bnx2x_phy_def_cfg(struct link_params *params,
11281 struct bnx2x_phy *phy,
11284 struct bnx2x *bp = params->bp;
11286 /* Populate the default phy configuration for MF mode */
11287 if (phy_index == EXT_PHY2) {
11288 link_config = REG_RD(bp, params->shmem_base +
11289 offsetof(struct shmem_region, dev_info.
11290 port_feature_config[params->port].link_config2));
11291 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11292 offsetof(struct shmem_region,
11294 port_hw_config[params->port].speed_capability_mask2));
11296 link_config = REG_RD(bp, params->shmem_base +
11297 offsetof(struct shmem_region, dev_info.
11298 port_feature_config[params->port].link_config));
11299 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11300 offsetof(struct shmem_region,
11302 port_hw_config[params->port].speed_capability_mask));
11304 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11305 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11307 phy->req_duplex = DUPLEX_FULL;
11308 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11309 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11310 phy->req_duplex = DUPLEX_HALF;
11311 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11312 phy->req_line_speed = SPEED_10;
11314 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11315 phy->req_duplex = DUPLEX_HALF;
11316 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11317 phy->req_line_speed = SPEED_100;
11319 case PORT_FEATURE_LINK_SPEED_1G:
11320 phy->req_line_speed = SPEED_1000;
11322 case PORT_FEATURE_LINK_SPEED_2_5G:
11323 phy->req_line_speed = SPEED_2500;
11325 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11326 phy->req_line_speed = SPEED_10000;
11329 phy->req_line_speed = SPEED_AUTO_NEG;
11333 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11334 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11335 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11337 case PORT_FEATURE_FLOW_CONTROL_TX:
11338 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11340 case PORT_FEATURE_FLOW_CONTROL_RX:
11341 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11343 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11344 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11347 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11352 u32 bnx2x_phy_selection(struct link_params *params)
11354 u32 phy_config_swapped, prio_cfg;
11355 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11357 phy_config_swapped = params->multi_phy_config &
11358 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11360 prio_cfg = params->multi_phy_config &
11361 PORT_HW_CFG_PHY_SELECTION_MASK;
11363 if (phy_config_swapped) {
11364 switch (prio_cfg) {
11365 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11366 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11368 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11369 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11371 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11372 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11374 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11375 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11379 return_cfg = prio_cfg;
11385 int bnx2x_phy_probe(struct link_params *params)
11387 u8 phy_index, actual_phy_idx, link_cfg_idx;
11388 u32 phy_config_swapped, sync_offset, media_types;
11389 struct bnx2x *bp = params->bp;
11390 struct bnx2x_phy *phy;
11391 params->num_phys = 0;
11392 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11393 phy_config_swapped = params->multi_phy_config &
11394 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11396 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11398 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11399 actual_phy_idx = phy_index;
11400 if (phy_config_swapped) {
11401 if (phy_index == EXT_PHY1)
11402 actual_phy_idx = EXT_PHY2;
11403 else if (phy_index == EXT_PHY2)
11404 actual_phy_idx = EXT_PHY1;
11406 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11407 " actual_phy_idx %x\n", phy_config_swapped,
11408 phy_index, actual_phy_idx);
11409 phy = ¶ms->phy[actual_phy_idx];
11410 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11411 params->shmem2_base, params->port,
11413 params->num_phys = 0;
11414 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11416 for (phy_index = INT_PHY;
11417 phy_index < MAX_PHYS;
11422 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11425 sync_offset = params->shmem_base +
11426 offsetof(struct shmem_region,
11427 dev_info.port_hw_config[params->port].media_type);
11428 media_types = REG_RD(bp, sync_offset);
11431 * Update media type for non-PMF sync only for the first time
11432 * In case the media type changes afterwards, it will be updated
11433 * using the update_status function
11435 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11436 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11437 actual_phy_idx))) == 0) {
11438 media_types |= ((phy->media_type &
11439 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11440 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11443 REG_WR(bp, sync_offset, media_types);
11445 bnx2x_phy_def_cfg(params, phy, phy_index);
11446 params->num_phys++;
11449 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11453 void bnx2x_init_bmac_loopback(struct link_params *params,
11454 struct link_vars *vars)
11456 struct bnx2x *bp = params->bp;
11458 vars->line_speed = SPEED_10000;
11459 vars->duplex = DUPLEX_FULL;
11460 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11461 vars->mac_type = MAC_TYPE_BMAC;
11463 vars->phy_flags = PHY_XGXS_FLAG;
11465 bnx2x_xgxs_deassert(params);
11467 /* set bmac loopback */
11468 bnx2x_bmac_enable(params, vars, 1);
11470 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11473 void bnx2x_init_emac_loopback(struct link_params *params,
11474 struct link_vars *vars)
11476 struct bnx2x *bp = params->bp;
11478 vars->line_speed = SPEED_1000;
11479 vars->duplex = DUPLEX_FULL;
11480 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11481 vars->mac_type = MAC_TYPE_EMAC;
11483 vars->phy_flags = PHY_XGXS_FLAG;
11485 bnx2x_xgxs_deassert(params);
11486 /* set bmac loopback */
11487 bnx2x_emac_enable(params, vars, 1);
11488 bnx2x_emac_program(params, vars);
11489 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11492 void bnx2x_init_xmac_loopback(struct link_params *params,
11493 struct link_vars *vars)
11495 struct bnx2x *bp = params->bp;
11497 if (!params->req_line_speed[0])
11498 vars->line_speed = SPEED_10000;
11500 vars->line_speed = params->req_line_speed[0];
11501 vars->duplex = DUPLEX_FULL;
11502 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11503 vars->mac_type = MAC_TYPE_XMAC;
11504 vars->phy_flags = PHY_XGXS_FLAG;
11506 * Set WC to loopback mode since link is required to provide clock
11507 * to the XMAC in 20G mode
11509 if (vars->line_speed == SPEED_20000) {
11510 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
11511 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
11512 params->phy[INT_PHY].config_loopback(
11513 ¶ms->phy[INT_PHY],
11516 bnx2x_xmac_enable(params, vars, 1);
11517 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11520 void bnx2x_init_umac_loopback(struct link_params *params,
11521 struct link_vars *vars)
11523 struct bnx2x *bp = params->bp;
11525 vars->line_speed = SPEED_1000;
11526 vars->duplex = DUPLEX_FULL;
11527 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11528 vars->mac_type = MAC_TYPE_UMAC;
11529 vars->phy_flags = PHY_XGXS_FLAG;
11530 bnx2x_umac_enable(params, vars, 1);
11532 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11535 void bnx2x_init_xgxs_loopback(struct link_params *params,
11536 struct link_vars *vars)
11538 struct bnx2x *bp = params->bp;
11540 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11541 vars->duplex = DUPLEX_FULL;
11542 if (params->req_line_speed[0] == SPEED_1000)
11543 vars->line_speed = SPEED_1000;
11545 vars->line_speed = SPEED_10000;
11547 if (!USES_WARPCORE(bp))
11548 bnx2x_xgxs_deassert(params);
11549 bnx2x_link_initialize(params, vars);
11551 if (params->req_line_speed[0] == SPEED_1000) {
11552 if (USES_WARPCORE(bp))
11553 bnx2x_umac_enable(params, vars, 0);
11555 bnx2x_emac_program(params, vars);
11556 bnx2x_emac_enable(params, vars, 0);
11559 if (USES_WARPCORE(bp))
11560 bnx2x_xmac_enable(params, vars, 0);
11562 bnx2x_bmac_enable(params, vars, 0);
11565 if (params->loopback_mode == LOOPBACK_XGXS) {
11566 /* set 10G XGXS loopback */
11567 params->phy[INT_PHY].config_loopback(
11568 ¶ms->phy[INT_PHY],
11572 /* set external phy loopback */
11574 for (phy_index = EXT_PHY1;
11575 phy_index < params->num_phys; phy_index++) {
11576 if (params->phy[phy_index].config_loopback)
11577 params->phy[phy_index].config_loopback(
11578 ¶ms->phy[phy_index],
11582 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11584 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11587 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11589 struct bnx2x *bp = params->bp;
11590 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11591 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11592 params->req_line_speed[0], params->req_flow_ctrl[0]);
11593 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11594 params->req_line_speed[1], params->req_flow_ctrl[1]);
11595 vars->link_status = 0;
11596 vars->phy_link_up = 0;
11598 vars->line_speed = 0;
11599 vars->duplex = DUPLEX_FULL;
11600 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11601 vars->mac_type = MAC_TYPE_NONE;
11602 vars->phy_flags = 0;
11604 /* disable attentions */
11605 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11606 (NIG_MASK_XGXS0_LINK_STATUS |
11607 NIG_MASK_XGXS0_LINK10G |
11608 NIG_MASK_SERDES0_LINK_STATUS |
11611 bnx2x_emac_init(params, vars);
11613 if (params->num_phys == 0) {
11614 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11617 set_phy_vars(params, vars);
11619 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11620 switch (params->loopback_mode) {
11621 case LOOPBACK_BMAC:
11622 bnx2x_init_bmac_loopback(params, vars);
11624 case LOOPBACK_EMAC:
11625 bnx2x_init_emac_loopback(params, vars);
11627 case LOOPBACK_XMAC:
11628 bnx2x_init_xmac_loopback(params, vars);
11630 case LOOPBACK_UMAC:
11631 bnx2x_init_umac_loopback(params, vars);
11633 case LOOPBACK_XGXS:
11634 case LOOPBACK_EXT_PHY:
11635 bnx2x_init_xgxs_loopback(params, vars);
11638 if (!CHIP_IS_E3(bp)) {
11639 if (params->switch_cfg == SWITCH_CFG_10G)
11640 bnx2x_xgxs_deassert(params);
11642 bnx2x_serdes_deassert(bp, params->port);
11644 bnx2x_link_initialize(params, vars);
11646 bnx2x_link_int_enable(params);
11652 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11655 struct bnx2x *bp = params->bp;
11656 u8 phy_index, port = params->port, clear_latch_ind = 0;
11657 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11658 /* disable attentions */
11659 vars->link_status = 0;
11660 bnx2x_update_mng(params, vars->link_status);
11661 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11662 (NIG_MASK_XGXS0_LINK_STATUS |
11663 NIG_MASK_XGXS0_LINK10G |
11664 NIG_MASK_SERDES0_LINK_STATUS |
11667 /* activate nig drain */
11668 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11670 /* disable nig egress interface */
11671 if (!CHIP_IS_E3(bp)) {
11672 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11673 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11676 /* Stop BigMac rx */
11677 if (!CHIP_IS_E3(bp))
11678 bnx2x_bmac_rx_disable(bp, port);
11680 bnx2x_xmac_disable(params);
11682 if (!CHIP_IS_E3(bp))
11683 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11686 /* The PHY reset is controlled by GPIO 1
11687 * Hold it as vars low
11689 /* clear link led */
11690 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11692 if (reset_ext_phy) {
11693 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11695 if (params->phy[phy_index].link_reset)
11696 params->phy[phy_index].link_reset(
11697 ¶ms->phy[phy_index],
11699 if (params->phy[phy_index].flags &
11700 FLAGS_REARM_LATCH_SIGNAL)
11701 clear_latch_ind = 1;
11705 if (clear_latch_ind) {
11706 /* Clear latching indication */
11707 bnx2x_rearm_latch_signal(bp, port, 0);
11708 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11709 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11711 if (params->phy[INT_PHY].link_reset)
11712 params->phy[INT_PHY].link_reset(
11713 ¶ms->phy[INT_PHY], params);
11715 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11716 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11718 /* disable nig ingress interface */
11719 if (!CHIP_IS_E3(bp)) {
11720 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11721 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11724 vars->phy_flags = 0;
11728 /****************************************************************************/
11729 /* Common function */
11730 /****************************************************************************/
11731 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11732 u32 shmem_base_path[],
11733 u32 shmem2_base_path[], u8 phy_index,
11736 struct bnx2x_phy phy[PORT_MAX];
11737 struct bnx2x_phy *phy_blk[PORT_MAX];
11740 s8 port_of_path = 0;
11741 u32 swap_val, swap_override;
11742 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11743 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11744 port ^= (swap_val && swap_override);
11745 bnx2x_ext_phy_hw_reset(bp, port);
11746 /* PART1 - Reset both phys */
11747 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11748 u32 shmem_base, shmem2_base;
11749 /* In E2, same phy is using for port0 of the two paths */
11750 if (CHIP_IS_E1x(bp)) {
11751 shmem_base = shmem_base_path[0];
11752 shmem2_base = shmem2_base_path[0];
11753 port_of_path = port;
11755 shmem_base = shmem_base_path[port];
11756 shmem2_base = shmem2_base_path[port];
11760 /* Extract the ext phy address for the port */
11761 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11762 port_of_path, &phy[port]) !=
11764 DP(NETIF_MSG_LINK, "populate_phy failed\n");
11767 /* disable attentions */
11768 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11770 (NIG_MASK_XGXS0_LINK_STATUS |
11771 NIG_MASK_XGXS0_LINK10G |
11772 NIG_MASK_SERDES0_LINK_STATUS |
11775 /* Need to take the phy out of low power mode in order
11776 to write to access its registers */
11777 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11778 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11781 /* Reset the phy */
11782 bnx2x_cl45_write(bp, &phy[port],
11788 /* Add delay of 150ms after reset */
11791 if (phy[PORT_0].addr & 0x1) {
11792 phy_blk[PORT_0] = &(phy[PORT_1]);
11793 phy_blk[PORT_1] = &(phy[PORT_0]);
11795 phy_blk[PORT_0] = &(phy[PORT_0]);
11796 phy_blk[PORT_1] = &(phy[PORT_1]);
11799 /* PART2 - Download firmware to both phys */
11800 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11801 if (CHIP_IS_E1x(bp))
11802 port_of_path = port;
11806 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11807 phy_blk[port]->addr);
11808 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11812 /* Only set bit 10 = 1 (Tx power down) */
11813 bnx2x_cl45_read(bp, phy_blk[port],
11815 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11817 /* Phase1 of TX_POWER_DOWN reset */
11818 bnx2x_cl45_write(bp, phy_blk[port],
11820 MDIO_PMA_REG_TX_POWER_DOWN,
11825 * Toggle Transmitter: Power down and then up with 600ms delay
11830 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11831 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11832 /* Phase2 of POWER_DOWN_RESET */
11833 /* Release bit 10 (Release Tx power down) */
11834 bnx2x_cl45_read(bp, phy_blk[port],
11836 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11838 bnx2x_cl45_write(bp, phy_blk[port],
11840 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11843 /* Read modify write the SPI-ROM version select register */
11844 bnx2x_cl45_read(bp, phy_blk[port],
11846 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11847 bnx2x_cl45_write(bp, phy_blk[port],
11849 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11851 /* set GPIO2 back to LOW */
11852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11853 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11857 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11858 u32 shmem_base_path[],
11859 u32 shmem2_base_path[], u8 phy_index,
11864 struct bnx2x_phy phy;
11865 /* Use port1 because of the static port-swap */
11866 /* Enable the module detection interrupt */
11867 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11868 val |= ((1<<MISC_REGISTERS_GPIO_3)|
11869 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11870 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11872 bnx2x_ext_phy_hw_reset(bp, 0);
11874 for (port = 0; port < PORT_MAX; port++) {
11875 u32 shmem_base, shmem2_base;
11877 /* In E2, same phy is using for port0 of the two paths */
11878 if (CHIP_IS_E1x(bp)) {
11879 shmem_base = shmem_base_path[0];
11880 shmem2_base = shmem2_base_path[0];
11882 shmem_base = shmem_base_path[port];
11883 shmem2_base = shmem2_base_path[port];
11885 /* Extract the ext phy address for the port */
11886 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11889 DP(NETIF_MSG_LINK, "populate phy failed\n");
11894 bnx2x_cl45_write(bp, &phy,
11895 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11898 /* Set fault module detected LED on */
11899 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11900 MISC_REGISTERS_GPIO_HIGH,
11906 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11907 u8 *io_gpio, u8 *io_port)
11910 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11911 offsetof(struct shmem_region,
11912 dev_info.port_hw_config[PORT_0].default_cfg));
11913 switch (phy_gpio_reset) {
11914 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11918 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11922 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11926 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11930 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11934 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11938 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11942 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11947 /* Don't override the io_gpio and io_port */
11952 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11953 u32 shmem_base_path[],
11954 u32 shmem2_base_path[], u8 phy_index,
11957 s8 port, reset_gpio;
11958 u32 swap_val, swap_override;
11959 struct bnx2x_phy phy[PORT_MAX];
11960 struct bnx2x_phy *phy_blk[PORT_MAX];
11962 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11963 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11965 reset_gpio = MISC_REGISTERS_GPIO_1;
11969 * Retrieve the reset gpio/port which control the reset.
11970 * Default is GPIO1, PORT1
11972 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11973 (u8 *)&reset_gpio, (u8 *)&port);
11975 /* Calculate the port based on port swap */
11976 port ^= (swap_val && swap_override);
11978 /* Initiate PHY reset*/
11979 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11982 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11987 /* PART1 - Reset both phys */
11988 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11989 u32 shmem_base, shmem2_base;
11991 /* In E2, same phy is using for port0 of the two paths */
11992 if (CHIP_IS_E1x(bp)) {
11993 shmem_base = shmem_base_path[0];
11994 shmem2_base = shmem2_base_path[0];
11995 port_of_path = port;
11997 shmem_base = shmem_base_path[port];
11998 shmem2_base = shmem2_base_path[port];
12002 /* Extract the ext phy address for the port */
12003 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12004 port_of_path, &phy[port]) !=
12006 DP(NETIF_MSG_LINK, "populate phy failed\n");
12009 /* disable attentions */
12010 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12012 (NIG_MASK_XGXS0_LINK_STATUS |
12013 NIG_MASK_XGXS0_LINK10G |
12014 NIG_MASK_SERDES0_LINK_STATUS |
12018 /* Reset the phy */
12019 bnx2x_cl45_write(bp, &phy[port],
12020 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12023 /* Add delay of 150ms after reset */
12025 if (phy[PORT_0].addr & 0x1) {
12026 phy_blk[PORT_0] = &(phy[PORT_1]);
12027 phy_blk[PORT_1] = &(phy[PORT_0]);
12029 phy_blk[PORT_0] = &(phy[PORT_0]);
12030 phy_blk[PORT_1] = &(phy[PORT_1]);
12032 /* PART2 - Download firmware to both phys */
12033 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12034 if (CHIP_IS_E1x(bp))
12035 port_of_path = port;
12038 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12039 phy_blk[port]->addr);
12040 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12043 /* Disable PHY transmitter output */
12044 bnx2x_cl45_write(bp, phy_blk[port],
12046 MDIO_PMA_REG_TX_DISABLE, 1);
12052 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12053 u32 shmem2_base_path[], u8 phy_index,
12054 u32 ext_phy_type, u32 chip_id)
12058 switch (ext_phy_type) {
12059 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12060 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12062 phy_index, chip_id);
12064 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12065 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12066 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12067 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12069 phy_index, chip_id);
12072 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12074 * GPIO1 affects both ports, so there's need to pull
12075 * it for single port alone
12077 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12079 phy_index, chip_id);
12081 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12083 * GPIO3's are linked, and so both need to be toggled
12084 * to obtain required 2us pulse.
12086 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12088 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12093 "ext_phy 0x%x common init not required\n",
12099 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12105 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12106 u32 shmem2_base_path[], u32 chip_id)
12111 u32 ext_phy_type, ext_phy_config;
12112 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12113 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12114 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12115 if (CHIP_IS_E3(bp)) {
12117 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12118 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12120 /* Check if common init was already done */
12121 phy_ver = REG_RD(bp, shmem_base_path[0] +
12122 offsetof(struct shmem_region,
12123 port_mb[PORT_0].ext_phy_fw_version));
12125 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12130 /* Read the ext_phy_type for arbitrary port(0) */
12131 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12133 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12134 shmem_base_path[0],
12136 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12137 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12139 phy_index, ext_phy_type,
12145 static void bnx2x_check_over_curr(struct link_params *params,
12146 struct link_vars *vars)
12148 struct bnx2x *bp = params->bp;
12150 u8 port = params->port;
12153 cfg_pin = (REG_RD(bp, params->shmem_base +
12154 offsetof(struct shmem_region,
12155 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12156 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12157 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12159 /* Ignore check if no external input PIN available */
12160 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12164 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12165 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12166 " been detected and the power to "
12167 "that SFP+ module has been removed"
12168 " to prevent failure of the card."
12169 " Please remove the SFP+ module and"
12170 " restart the system to clear this"
12173 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12176 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12179 static void bnx2x_analyze_link_error(struct link_params *params,
12180 struct link_vars *vars, u32 lss_status)
12182 struct bnx2x *bp = params->bp;
12183 /* Compare new value with previous value */
12185 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12187 /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
12189 half_open_conn, lss_status);*/
12191 if ((lss_status ^ half_open_conn) == 0)
12194 /* If values differ */
12195 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12196 half_open_conn, lss_status);
12199 * a. Update shmem->link_status accordingly
12200 * b. Update link_vars->link_up
12203 vars->link_status &= ~LINK_STATUS_LINK_UP;
12205 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12207 * Set LED mode to off since the PHY doesn't know about these
12210 led_mode = LED_MODE_OFF;
12212 vars->link_status |= LINK_STATUS_LINK_UP;
12214 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12215 led_mode = LED_MODE_OPER;
12217 /* Update the LED according to the link state */
12218 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12220 /* Update link status in the shared memory */
12221 bnx2x_update_mng(params, vars->link_status);
12223 /* C. Trigger General Attention */
12224 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12225 bnx2x_notify_link_changed(bp);
12228 static void bnx2x_check_half_open_conn(struct link_params *params,
12229 struct link_vars *vars)
12231 struct bnx2x *bp = params->bp;
12232 u32 lss_status = 0;
12234 /* In case link status is physically up @ 10G do */
12235 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12238 if (!CHIP_IS_E3(bp) &&
12239 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12240 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12241 /* Check E1X / E2 BMAC */
12242 u32 lss_status_reg;
12244 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12245 NIG_REG_INGRESS_BMAC0_MEM;
12246 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12247 if (CHIP_IS_E2(bp))
12248 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12250 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12252 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12253 lss_status = (wb_data[0] > 0);
12255 bnx2x_analyze_link_error(params, vars, lss_status);
12259 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12261 struct bnx2x *bp = params->bp;
12263 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12266 /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12267 RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12268 REG_RD(bp, MISC_REG_RESET_REG_2)); */
12269 bnx2x_check_half_open_conn(params, vars);
12270 if (CHIP_IS_E3(bp))
12271 bnx2x_check_over_curr(params, vars);
12274 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12277 struct bnx2x_phy phy;
12278 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12280 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12282 DP(NETIF_MSG_LINK, "populate phy failed\n");
12286 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12292 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12297 u8 phy_index, fan_failure_det_req = 0;
12298 struct bnx2x_phy phy;
12299 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12301 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12304 DP(NETIF_MSG_LINK, "populate phy failed\n");
12307 fan_failure_det_req |= (phy.flags &
12308 FLAGS_FAN_FAILURE_DET_REQ);
12310 return fan_failure_det_req;
12313 void bnx2x_hw_reset_phy(struct link_params *params)
12316 struct bnx2x *bp = params->bp;
12317 bnx2x_update_mng(params, 0);
12318 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12319 (NIG_MASK_XGXS0_LINK_STATUS |
12320 NIG_MASK_XGXS0_LINK10G |
12321 NIG_MASK_SERDES0_LINK_STATUS |
12324 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12326 if (params->phy[phy_index].hw_reset) {
12327 params->phy[phy_index].hw_reset(
12328 ¶ms->phy[phy_index],
12330 params->phy[phy_index] = phy_null;
12335 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12336 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12339 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12341 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12342 if (CHIP_IS_E3(bp)) {
12343 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12350 struct bnx2x_phy phy;
12351 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12353 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12354 shmem2_base, port, &phy)
12356 DP(NETIF_MSG_LINK, "populate phy failed\n");
12359 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12360 gpio_num = MISC_REGISTERS_GPIO_3;
12367 if (gpio_num == 0xff)
12370 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12371 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12373 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12374 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12375 gpio_port ^= (swap_val && swap_override);
12377 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12378 (gpio_num + (gpio_port << 2));
12380 sync_offset = shmem_base +
12381 offsetof(struct shmem_region,
12382 dev_info.port_hw_config[port].aeu_int_mask);
12383 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12385 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12386 gpio_num, gpio_port, vars->aeu_int_mask);
12389 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12391 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12393 /* Open appropriate AEU for interrupts */
12394 aeu_mask = REG_RD(bp, offset);
12395 aeu_mask |= vars->aeu_int_mask;
12396 REG_WR(bp, offset, aeu_mask);
12398 /* Enable the GPIO to trigger interrupt */
12399 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12400 val |= 1 << (gpio_num + (gpio_port << 2));
12401 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);