drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28
  29 /********************************************************/
  30 #define ETH_HLEN                        14
  31 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  32 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  33 #define ETH_MIN_PACKET_SIZE             60
  34 #define ETH_MAX_PACKET_SIZE             1500
  35 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  36 #define MDIO_ACCESS_TIMEOUT             1000
  37 #define BMAC_CONTROL_RX_ENABLE          2
  38
  39 /***********************************************************/
  40 /*                      Shortcut definitions               */
  41 /***********************************************************/
  42
  43 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  44
  45 #define NIG_STATUS_EMAC0_MI_INT \
  46                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  47 #define NIG_STATUS_XGXS0_LINK10G \
  48                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  49 #define NIG_STATUS_XGXS0_LINK_STATUS \
  50                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  51 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  52                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  53 #define NIG_STATUS_SERDES0_LINK_STATUS \
  54                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  55 #define NIG_MASK_MI_INT \
  56                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  57 #define NIG_MASK_XGXS0_LINK10G \
  58                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  59 #define NIG_MASK_XGXS0_LINK_STATUS \
  60                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  61 #define NIG_MASK_SERDES0_LINK_STATUS \
  62                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  63
  64 #define MDIO_AN_CL73_OR_37_COMPLETE \
  65                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  66                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  67
  68 #define XGXS_RESET_BITS \
  69         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  73          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  74
  75 #define SERDES_RESET_BITS \
  76         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  80
  81 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  82 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  83 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  84 #define AUTONEG_PARALLEL \
  85                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  86 #define AUTONEG_SGMII_FIBER_AUTODET \
  87                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  88 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  89
  90 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  91                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  92 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  93                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  94 #define GP_STATUS_SPEED_MASK \
  95                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  96 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  97 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
  98 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
  99 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 100 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 101 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 102 #define GP_STATUS_10G_HIG \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 104 #define GP_STATUS_10G_CX4 \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 106 #define GP_STATUS_12G_HIG \
 107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 108 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 109 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 110 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 111 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 112 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 113 #define GP_STATUS_10G_KX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 115
 116 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 117 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 118 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 119 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 120 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 121 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 122 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 123 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 124 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 125 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 126 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 127 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 128 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 129 #define LINK_12GTFD             LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
 130 #define LINK_12GXFD             LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
 131 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
 132 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
 133 #define LINK_13GTFD             LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
 134 #define LINK_13GXFD             LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
 135 #define LINK_15GTFD             LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
 136 #define LINK_15GXFD             LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
 137 #define LINK_16GTFD             LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 138 #define LINK_16GXFD             LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 139
 140 #define PHY_XGXS_FLAG                   0x1
 141 #define PHY_SGMII_FLAG                  0x2
 142 #define PHY_SERDES_FLAG                 0x4
 143
 144 /* */
 145 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 146         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 147         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 148
 149
 150 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 151         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 152         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 153         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 154
 155 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 157         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 158
 159 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 160         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 161 #define SFP_EEPROM_OPTIONS_SIZE                 2
 162
 163 #define EDC_MODE_LINEAR                         0x0022
 164 #define EDC_MODE_LIMITING                               0x0044
 165 #define EDC_MODE_PASSIVE_DAC                    0x0055
 166
 167
 168 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 169 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 170 /**********************************************************/
 171 /*                     INTERFACE                          */
 172 /**********************************************************/
 173
 174 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 175         bnx2x_cl45_write(_bp, _phy, \
 176                 (_phy)->def_md_devad, \
 177                 (_bank + (_addr & 0xf)), \
 178                 _val)
 179
 180 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 181         bnx2x_cl45_read(_bp, _phy, \
 182                 (_phy)->def_md_devad, \
 183                 (_bank + (_addr & 0xf)), \
 184                 _val)
 185
 186 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 187 {
 188         u32 val = REG_RD(bp, reg);
 189
 190         val |= bits;
 191         REG_WR(bp, reg, val);
 192         return val;
 193 }
 194
 195 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 196 {
 197         u32 val = REG_RD(bp, reg);
 198
 199         val &= ~bits;
 200         REG_WR(bp, reg, val);
 201         return val;
 202 }
 203
 204 /******************************************************************/
 205 /*                              ETS section                       */
 206 /******************************************************************/
 207 void bnx2x_ets_disabled(struct link_params *params)
 208 {
 209         /* ETS disabled configuration*/
 210         struct bnx2x *bp = params->bp;
 211
 212         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 213
 214         /*
 215          * mapping between entry  priority to client number (0,1,2 -debug and
 216          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 217          * 3bits client num.
 218          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 219          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 220          */
 221
 222         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 223         /*
 224          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 225          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 226          * COS0 entry, 4 - COS1 entry.
 227          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 228          * bit4   bit3    bit2   bit1     bit0
 229          * MCP and debug are strict
 230          */
 231
 232         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 233         /* defines which entries (clients) are subjected to WFQ arbitration */
 234         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 235         /*
 236          * For strict priority entries defines the number of consecutive
 237          * slots for the highest priority.
 238          */
 239         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 240         /*
 241          * mapping between the CREDIT_WEIGHT registers and actual client
 242          * numbers
 243          */
 244         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 245         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 246         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 247
 248         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 249         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 250         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 251         /* ETS mode disable */
 252         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 253         /*
 254          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 255          * weight for COS0/COS1.
 256          */
 257         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 258         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 262         /* Defines the number of consecutive slots for the strict priority */
 263         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 264 }
 265
 266 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
 267 {
 268         /* ETS disabled configuration */
 269         struct bnx2x *bp = params->bp;
 270         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 271         /*
 272          * defines which entries (clients) are subjected to WFQ arbitration
 273          * COS0 0x8
 274          * COS1 0x10
 275          */
 276         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 277         /*
 278          * mapping between the ARB_CREDIT_WEIGHT registers and actual
 279          * client numbers (WEIGHT_0 does not actually have to represent
 280          * client 0)
 281          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 282          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 283          */
 284         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 285
 286         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 287                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 288         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 289                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 290
 291         /* ETS mode enabled*/
 292         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 293
 294         /* Defines the number of consecutive slots for the strict priority */
 295         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 296         /*
 297          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 298          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 299          * entry, 4 - COS1 entry.
 300          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 301          * bit4   bit3    bit2     bit1    bit0
 302          * MCP and debug are strict
 303          */
 304         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 305
 306         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 307         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 308                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 309         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 310                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 311 }
 312
 313 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 314                         const u32 cos1_bw)
 315 {
 316         /* ETS disabled configuration*/
 317         struct bnx2x *bp = params->bp;
 318         const u32 total_bw = cos0_bw + cos1_bw;
 319         u32 cos0_credit_weight = 0;
 320         u32 cos1_credit_weight = 0;
 321
 322         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 323
 324         if ((0 == total_bw) ||
 325             (0 == cos0_bw) ||
 326             (0 == cos1_bw)) {
 327                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
 328                 return;
 329         }
 330
 331         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 332                 total_bw;
 333         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 334                 total_bw;
 335
 336         bnx2x_ets_bw_limit_common(params);
 337
 338         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 339         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 340
 341         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 342         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 343 }
 344
 345 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 346 {
 347         /* ETS disabled configuration*/
 348         struct bnx2x *bp = params->bp;
 349         u32 val = 0;
 350
 351         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 352         /*
 353          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 354          * as strict.  Bits 0,1,2 - debug and management entries,
 355          * 3 - COS0 entry, 4 - COS1 entry.
 356          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 357          *  bit4   bit3   bit2      bit1     bit0
 358          * MCP and debug are strict
 359          */
 360         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 361         /*
 362          * For strict priority entries defines the number of consecutive slots
 363          * for the highest priority.
 364          */
 365         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 366         /* ETS mode disable */
 367         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 368         /* Defines the number of consecutive slots for the strict priority */
 369         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 370
 371         /* Defines the number of consecutive slots for the strict priority */
 372         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 373
 374         /*
 375          * mapping between entry  priority to client number (0,1,2 -debug and
 376          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 377          * 3bits client num.
 378          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 379          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 380          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 381          */
 382         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 383         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 384
 385         return 0;
 386 }
 387 /******************************************************************/
 388 /*                      PFC section                               */
 389 /******************************************************************/
 390
 391 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 392                                      u32 pfc_frames_sent[2],
 393                                      u32 pfc_frames_received[2])
 394 {
 395         /* Read pfc statistic */
 396         struct bnx2x *bp = params->bp;
 397         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 398                 NIG_REG_INGRESS_BMAC0_MEM;
 399
 400         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 401
 402         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 403                                         pfc_frames_sent, 2);
 404
 405         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 406                                         pfc_frames_received, 2);
 407
 408 }
 409 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 410                                     u32 pfc_frames_sent[2],
 411                                     u32 pfc_frames_received[2])
 412 {
 413         /* Read pfc statistic */
 414         struct bnx2x *bp = params->bp;
 415         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 416         u32 val_xon = 0;
 417         u32 val_xoff = 0;
 418
 419         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 420
 421         /* PFC received frames */
 422         val_xoff = REG_RD(bp, emac_base +
 423                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 424         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 425         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 426         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 427
 428         pfc_frames_received[0] = val_xon + val_xoff;
 429
 430         /* PFC received sent */
 431         val_xoff = REG_RD(bp, emac_base +
 432                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 433         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 434         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 435         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 436
 437         pfc_frames_sent[0] = val_xon + val_xoff;
 438 }
 439
 440 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 441                          u32 pfc_frames_sent[2],
 442                          u32 pfc_frames_received[2])
 443 {
 444         /* Read pfc statistic */
 445         struct bnx2x *bp = params->bp;
 446         u32 val = 0;
 447         DP(NETIF_MSG_LINK, "pfc statistic\n");
 448
 449         if (!vars->link_up)
 450                 return;
 451
 452         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 453         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 454             == 0) {
 455                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 456                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 457                                         pfc_frames_received);
 458         } else {
 459                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 460                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 461                                          pfc_frames_received);
 462         }
 463 }
 464 /******************************************************************/
 465 /*                      MAC/PBF section                           */
 466 /******************************************************************/
 467 static void bnx2x_emac_init(struct link_params *params,
 468                             struct link_vars *vars)
 469 {
 470         /* reset and unreset the emac core */
 471         struct bnx2x *bp = params->bp;
 472         u8 port = params->port;
 473         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 474         u32 val;
 475         u16 timeout;
 476
 477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 478                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 479         udelay(5);
 480         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 481                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 482
 483         /* init emac - use read-modify-write */
 484         /* self clear reset */
 485         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 486         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 487
 488         timeout = 200;
 489         do {
 490                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 491                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 492                 if (!timeout) {
 493                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 494                         return;
 495                 }
 496                 timeout--;
 497         } while (val & EMAC_MODE_RESET);
 498
 499         /* Set mac address */
 500         val = ((params->mac_addr[0] << 8) |
 501                 params->mac_addr[1]);
 502         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 503
 504         val = ((params->mac_addr[2] << 24) |
 505                (params->mac_addr[3] << 16) |
 506                (params->mac_addr[4] << 8) |
 507                 params->mac_addr[5]);
 508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 509 }
 510
 511 static int bnx2x_emac_enable(struct link_params *params,
 512                              struct link_vars *vars, u8 lb)
 513 {
 514         struct bnx2x *bp = params->bp;
 515         u8 port = params->port;
 516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 517         u32 val;
 518
 519         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 520
 521         /* enable emac and not bmac */
 522         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 523
 524         /* ASIC */
 525         if (vars->phy_flags & PHY_XGXS_FLAG) {
 526                 u32 ser_lane = ((params->lane_config &
 527                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 528                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 529
 530                 DP(NETIF_MSG_LINK, "XGXS\n");
 531                 /* select the master lanes (out of 0-3) */
 532                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
 533                 /* select XGXS */
 534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
 535
 536         } else { /* SerDes */
 537                 DP(NETIF_MSG_LINK, "SerDes\n");
 538                 /* select SerDes */
 539                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
 540         }
 541
 542         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 543                       EMAC_RX_MODE_RESET);
 544         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 545                       EMAC_TX_MODE_RESET);
 546
 547         if (CHIP_REV_IS_SLOW(bp)) {
 548                 /* config GMII mode */
 549                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 550                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
 551         } else { /* ASIC */
 552                 /* pause enable/disable */
 553                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 554                                EMAC_RX_MODE_FLOW_EN);
 555
 556                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 557                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 558                                 EMAC_TX_MODE_FLOW_EN));
 559                 if (!(params->feature_config_flags &
 560                       FEATURE_CONFIG_PFC_ENABLED)) {
 561                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 562                                 bnx2x_bits_en(bp, emac_base +
 563                                               EMAC_REG_EMAC_RX_MODE,
 564                                               EMAC_RX_MODE_FLOW_EN);
 565
 566                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 567                                 bnx2x_bits_en(bp, emac_base +
 568                                               EMAC_REG_EMAC_TX_MODE,
 569                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 570                                                EMAC_TX_MODE_FLOW_EN));
 571                 } else
 572                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 573                                       EMAC_TX_MODE_FLOW_EN);
 574         }
 575
 576         /* KEEP_VLAN_TAG, promiscuous */
 577         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 578         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 579
 580         /*
 581          * Setting this bit causes MAC control frames (except for pause
 582          * frames) to be passed on for processing. This setting has no
 583          * affect on the operation of the pause frames. This bit effects
 584          * all packets regardless of RX Parser packet sorting logic.
 585          * Turn the PFC off to make sure we are in Xon state before
 586          * enabling it.
 587          */
 588         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 589         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 590                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 591                 /* Enable PFC again */
 592                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 593                         EMAC_REG_RX_PFC_MODE_RX_EN |
 594                         EMAC_REG_RX_PFC_MODE_TX_EN |
 595                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 596
 597                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 598                         ((0x0101 <<
 599                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 600                          (0x00ff <<
 601                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 602                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 603         }
 604         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 605
 606         /* Set Loopback */
 607         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 608         if (lb)
 609                 val |= 0x810;
 610         else
 611                 val &= ~0x810;
 612         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 613
 614         /* enable emac */
 615         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 616
 617         /* enable emac for jumbo packets */
 618         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 619                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 620                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 621
 622         /* strip CRC */
 623         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
 624
 625         /* disable the NIG in/out to the bmac */
 626         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
 627         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
 628         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
 629
 630         /* enable the NIG in/out to the emac */
 631         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
 632         val = 0;
 633         if ((params->feature_config_flags &
 634               FEATURE_CONFIG_PFC_ENABLED) ||
 635             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 636                 val = 1;
 637
 638         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
 639         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
 640
 641         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
 642
 643         vars->mac_type = MAC_TYPE_EMAC;
 644         return 0;
 645 }
 646
 647 static void bnx2x_update_pfc_bmac1(struct link_params *params,
 648                                    struct link_vars *vars)
 649 {
 650         u32 wb_data[2];
 651         struct bnx2x *bp = params->bp;
 652         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 653                 NIG_REG_INGRESS_BMAC0_MEM;
 654
 655         u32 val = 0x14;
 656         if ((!(params->feature_config_flags &
 657               FEATURE_CONFIG_PFC_ENABLED)) &&
 658                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 659                 /* Enable BigMAC to react on received Pause packets */
 660                 val |= (1<<5);
 661         wb_data[0] = val;
 662         wb_data[1] = 0;
 663         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
 664
 665         /* tx control */
 666         val = 0xc0;
 667         if (!(params->feature_config_flags &
 668               FEATURE_CONFIG_PFC_ENABLED) &&
 669                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 670                 val |= 0x800000;
 671         wb_data[0] = val;
 672         wb_data[1] = 0;
 673         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
 674 }
 675
 676 static void bnx2x_update_pfc_bmac2(struct link_params *params,
 677                                    struct link_vars *vars,
 678                                    u8 is_lb)
 679 {
 680         /*
 681          * Set rx control: Strip CRC and enable BigMAC to relay
 682          * control packets to the system as well
 683          */
 684         u32 wb_data[2];
 685         struct bnx2x *bp = params->bp;
 686         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 687                 NIG_REG_INGRESS_BMAC0_MEM;
 688         u32 val = 0x14;
 689
 690         if ((!(params->feature_config_flags &
 691               FEATURE_CONFIG_PFC_ENABLED)) &&
 692                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 693                 /* Enable BigMAC to react on received Pause packets */
 694                 val |= (1<<5);
 695         wb_data[0] = val;
 696         wb_data[1] = 0;
 697         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
 698         udelay(30);
 699
 700         /* Tx control */
 701         val = 0xc0;
 702         if (!(params->feature_config_flags &
 703                                 FEATURE_CONFIG_PFC_ENABLED) &&
 704             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 705                 val |= 0x800000;
 706         wb_data[0] = val;
 707         wb_data[1] = 0;
 708         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
 709
 710         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 711                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 712                 /* Enable PFC RX & TX & STATS and set 8 COS  */
 713                 wb_data[0] = 0x0;
 714                 wb_data[0] |= (1<<0);  /* RX */
 715                 wb_data[0] |= (1<<1);  /* TX */
 716                 wb_data[0] |= (1<<2);  /* Force initial Xon */
 717                 wb_data[0] |= (1<<3);  /* 8 cos */
 718                 wb_data[0] |= (1<<5);  /* STATS */
 719                 wb_data[1] = 0;
 720                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
 721                             wb_data, 2);
 722                 /* Clear the force Xon */
 723                 wb_data[0] &= ~(1<<2);
 724         } else {
 725                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
 726                 /* disable PFC RX & TX & STATS and set 8 COS */
 727                 wb_data[0] = 0x8;
 728                 wb_data[1] = 0;
 729         }
 730
 731         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 732
 733         /*
 734          * Set Time (based unit is 512 bit time) between automatic
 735          * re-sending of PP packets amd enable automatic re-send of
 736          * Per-Priroity Packet as long as pp_gen is asserted and
 737          * pp_disable is low.
 738          */
 739         val = 0x8000;
 740         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 741                 val |= (1<<16); /* enable automatic re-send */
 742
 743         wb_data[0] = val;
 744         wb_data[1] = 0;
 745         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
 746                     wb_data, 2);
 747
 748         /* mac control */
 749         val = 0x3; /* Enable RX and TX */
 750         if (is_lb) {
 751                 val |= 0x4; /* Local loopback */
 752                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
 753         }
 754         /* When PFC enabled, Pass pause frames towards the NIG. */
 755         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 756                 val |= ((1<<6)|(1<<5));
 757
 758         wb_data[0] = val;
 759         wb_data[1] = 0;
 760         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
 761 }
 762
 763 static void bnx2x_update_pfc_brb(struct link_params *params,
 764                 struct link_vars *vars,
 765                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 766 {
 767         struct bnx2x *bp = params->bp;
 768         int set_pfc = params->feature_config_flags &
 769                 FEATURE_CONFIG_PFC_ENABLED;
 770
 771         /* default - pause configuration */
 772         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 773         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 774         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 775         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 776
 777         if (set_pfc && pfc_params)
 778                 /* First COS */
 779                 if (!pfc_params->cos0_pauseable) {
 780                         pause_xoff_th =
 781                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 782                         pause_xon_th =
 783                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 784                         full_xoff_th =
 785                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 786                         full_xon_th =
 787                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 788                 }
 789         /*
 790          * The number of free blocks below which the pause signal to class 0
 791          * of MAC #n is asserted. n=0,1
 792          */
 793         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
 794         /*
 795          * The number of free blocks above which the pause signal to class 0
 796          * of MAC #n is de-asserted. n=0,1
 797          */
 798         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
 799         /*
 800          * The number of free blocks below which the full signal to class 0
 801          * of MAC #n is asserted. n=0,1
 802          */
 803         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
 804         /*
 805          * The number of free blocks above which the full signal to class 0
 806          * of MAC #n is de-asserted. n=0,1
 807          */
 808         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
 809
 810         if (set_pfc && pfc_params) {
 811                 /* Second COS */
 812                 if (pfc_params->cos1_pauseable) {
 813                         pause_xoff_th =
 814                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 815                         pause_xon_th =
 816                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 817                         full_xoff_th =
 818                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 819                         full_xon_th =
 820                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 821                 } else {
 822                         pause_xoff_th =
 823                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 824                         pause_xon_th =
 825                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 826                         full_xoff_th =
 827                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 828                         full_xon_th =
 829                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 830                 }
 831                 /*
 832                  * The number of free blocks below which the pause signal to
 833                  * class 1 of MAC #n is asserted. n=0,1
 834                  */
 835                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
 836                 /*
 837                  * The number of free blocks above which the pause signal to
 838                  * class 1 of MAC #n is de-asserted. n=0,1
 839                  */
 840                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
 841                 /*
 842                  * The number of free blocks below which the full signal to
 843                  * class 1 of MAC #n is asserted. n=0,1
 844                  */
 845                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
 846                 /*
 847                  * The number of free blocks above which the full signal to
 848                  * class 1 of MAC #n is de-asserted. n=0,1
 849                  */
 850                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
 851         }
 852 }
 853
 854 static void bnx2x_update_pfc_nig(struct link_params *params,
 855                 struct link_vars *vars,
 856                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
 857 {
 858         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
 859         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
 860         u32 pkt_priority_to_cos = 0;
 861         u32 val;
 862         struct bnx2x *bp = params->bp;
 863         int port = params->port;
 864         int set_pfc = params->feature_config_flags &
 865                 FEATURE_CONFIG_PFC_ENABLED;
 866         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
 867
 868         /*
 869          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
 870          * MAC control frames (that are not pause packets)
 871          * will be forwarded to the XCM.
 872          */
 873         xcm_mask = REG_RD(bp,
 874                                 port ? NIG_REG_LLH1_XCM_MASK :
 875                                 NIG_REG_LLH0_XCM_MASK);
 876         /*
 877          * nig params will override non PFC params, since it's possible to
 878          * do transition from PFC to SAFC
 879          */
 880         if (set_pfc) {
 881                 pause_enable = 0;
 882                 llfc_out_en = 0;
 883                 llfc_enable = 0;
 884                 ppp_enable = 1;
 885                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 886                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 887                 xcm0_out_en = 0;
 888                 p0_hwpfc_enable = 1;
 889         } else  {
 890                 if (nig_params) {
 891                         llfc_out_en = nig_params->llfc_out_en;
 892                         llfc_enable = nig_params->llfc_enable;
 893                         pause_enable = nig_params->pause_enable;
 894                 } else  /*defaul non PFC mode - PAUSE */
 895                         pause_enable = 1;
 896
 897                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 898                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 899                 xcm0_out_en = 1;
 900         }
 901
 902         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
 903                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
 904         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
 905                NIG_REG_LLFC_ENABLE_0, llfc_enable);
 906         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
 907                NIG_REG_PAUSE_ENABLE_0, pause_enable);
 908
 909         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
 910                NIG_REG_PPP_ENABLE_0, ppp_enable);
 911
 912         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
 913                NIG_REG_LLH0_XCM_MASK, xcm_mask);
 914
 915         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
 916
 917         /* output enable for RX_XCM # IF */
 918         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
 919
 920         /* HW PFC TX enable */
 921         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
 922
 923         /* 0x2 = BMAC, 0x1= EMAC */
 924         switch (vars->mac_type) {
 925         case MAC_TYPE_EMAC:
 926                 val = 1;
 927                 break;
 928         case MAC_TYPE_BMAC:
 929                 val = 0;
 930                 break;
 931         default:
 932                 val = 0;
 933                 break;
 934         }
 935         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
 936
 937         if (nig_params) {
 938                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
 939
 940                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
 941                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
 942                        nig_params->rx_cos0_priority_mask);
 943
 944                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
 945                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
 946                        nig_params->rx_cos1_priority_mask);
 947
 948                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
 949                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
 950                        nig_params->llfc_high_priority_classes);
 951
 952                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
 953                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
 954                        nig_params->llfc_low_priority_classes);
 955         }
 956         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
 957                NIG_REG_P0_PKT_PRIORITY_TO_COS,
 958                pkt_priority_to_cos);
 959 }
 960
 961
 962 void bnx2x_update_pfc(struct link_params *params,
 963                       struct link_vars *vars,
 964                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 965 {
 966         /*
 967          * The PFC and pause are orthogonal to one another, meaning when
 968          * PFC is enabled, the pause are disabled, and when PFC is
 969          * disabled, pause are set according to the pause result.
 970          */
 971         u32 val;
 972         struct bnx2x *bp = params->bp;
 973
 974         /* update NIG params */
 975         bnx2x_update_pfc_nig(params, vars, pfc_params);
 976
 977         /* update BRB params */
 978         bnx2x_update_pfc_brb(params, vars, pfc_params);
 979
 980         if (!vars->link_up)
 981                 return;
 982
 983         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 984         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 985             == 0) {
 986                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
 987                 bnx2x_emac_enable(params, vars, 0);
 988                 return;
 989         }
 990
 991         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
 992         if (CHIP_IS_E2(bp))
 993                 bnx2x_update_pfc_bmac2(params, vars, 0);
 994         else
 995                 bnx2x_update_pfc_bmac1(params, vars);
 996
 997         val = 0;
 998         if ((params->feature_config_flags &
 999               FEATURE_CONFIG_PFC_ENABLED) ||
1000             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001                 val = 1;
1002         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003 }
1004
1005 static int bnx2x_bmac1_enable(struct link_params *params,
1006                               struct link_vars *vars,
1007                               u8 is_lb)
1008 {
1009         struct bnx2x *bp = params->bp;
1010         u8 port = params->port;
1011         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012                                NIG_REG_INGRESS_BMAC0_MEM;
1013         u32 wb_data[2];
1014         u32 val;
1015
1016         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1017
1018         /* XGXS control */
1019         wb_data[0] = 0x3c;
1020         wb_data[1] = 0;
1021         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022                     wb_data, 2);
1023
1024         /* tx MAC SA */
1025         wb_data[0] = ((params->mac_addr[2] << 24) |
1026                        (params->mac_addr[3] << 16) |
1027                        (params->mac_addr[4] << 8) |
1028                         params->mac_addr[5]);
1029         wb_data[1] = ((params->mac_addr[0] << 8) |
1030                         params->mac_addr[1]);
1031         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1032
1033         /* mac control */
1034         val = 0x3;
1035         if (is_lb) {
1036                 val |= 0x4;
1037                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038         }
1039         wb_data[0] = val;
1040         wb_data[1] = 0;
1041         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1042
1043         /* set rx mtu */
1044         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045         wb_data[1] = 0;
1046         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1047
1048         bnx2x_update_pfc_bmac1(params, vars);
1049
1050         /* set tx mtu */
1051         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052         wb_data[1] = 0;
1053         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1054
1055         /* set cnt max size */
1056         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057         wb_data[1] = 0;
1058         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1059
1060         /* configure safc */
1061         wb_data[0] = 0x1000200;
1062         wb_data[1] = 0;
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064                     wb_data, 2);
1065
1066         return 0;
1067 }
1068
1069 static int bnx2x_bmac2_enable(struct link_params *params,
1070                               struct link_vars *vars,
1071                               u8 is_lb)
1072 {
1073         struct bnx2x *bp = params->bp;
1074         u8 port = params->port;
1075         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076                                NIG_REG_INGRESS_BMAC0_MEM;
1077         u32 wb_data[2];
1078
1079         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081         wb_data[0] = 0;
1082         wb_data[1] = 0;
1083         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1084         udelay(30);
1085
1086         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087         wb_data[0] = 0x3c;
1088         wb_data[1] = 0;
1089         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090                     wb_data, 2);
1091
1092         udelay(30);
1093
1094         /* tx MAC SA */
1095         wb_data[0] = ((params->mac_addr[2] << 24) |
1096                        (params->mac_addr[3] << 16) |
1097                        (params->mac_addr[4] << 8) |
1098                         params->mac_addr[5]);
1099         wb_data[1] = ((params->mac_addr[0] << 8) |
1100                         params->mac_addr[1]);
1101         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1102                     wb_data, 2);
1103
1104         udelay(30);
1105
1106         /* Configure SAFC */
1107         wb_data[0] = 0x1000200;
1108         wb_data[1] = 0;
1109         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1110                     wb_data, 2);
1111         udelay(30);
1112
1113         /* set rx mtu */
1114         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115         wb_data[1] = 0;
1116         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1117         udelay(30);
1118
1119         /* set tx mtu */
1120         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121         wb_data[1] = 0;
1122         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1123         udelay(30);
1124         /* set cnt max size */
1125         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126         wb_data[1] = 0;
1127         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1128         udelay(30);
1129         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1130
1131         return 0;
1132 }
1133
1134 static int bnx2x_bmac_enable(struct link_params *params,
1135                              struct link_vars *vars,
1136                              u8 is_lb)
1137 {
1138         int rc = 0;
1139         u8 port = params->port;
1140         struct bnx2x *bp = params->bp;
1141         u32 val;
1142         /* reset and unreset the BigMac */
1143         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1144                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1145         msleep(1);
1146
1147         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1148                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1149
1150         /* enable access for bmac registers */
1151         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1152
1153         /* Enable BMAC according to BMAC type*/
1154         if (CHIP_IS_E2(bp))
1155                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1156         else
1157                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1158         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1159         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1160         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1161         val = 0;
1162         if ((params->feature_config_flags &
1163               FEATURE_CONFIG_PFC_ENABLED) ||
1164             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1165                 val = 1;
1166         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1167         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1168         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1169         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1170         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1171         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1172
1173         vars->mac_type = MAC_TYPE_BMAC;
1174         return rc;
1175 }
1176
1177
1178 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1179 {
1180         struct bnx2x *bp = params->bp;
1181
1182         REG_WR(bp, params->shmem_base +
1183                offsetof(struct shmem_region,
1184                         port_mb[params->port].link_status), link_status);
1185 }
1186
1187 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1188 {
1189         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1190                         NIG_REG_INGRESS_BMAC0_MEM;
1191         u32 wb_data[2];
1192         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1193
1194         /* Only if the bmac is out of reset */
1195         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1196                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1197             nig_bmac_enable) {
1198
1199                 if (CHIP_IS_E2(bp)) {
1200                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1201                         REG_RD_DMAE(bp, bmac_addr +
1202                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1203                                     wb_data, 2);
1204                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1205                         REG_WR_DMAE(bp, bmac_addr +
1206                                     BIGMAC2_REGISTER_BMAC_CONTROL,
1207                                     wb_data, 2);
1208                 } else {
1209                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1210                         REG_RD_DMAE(bp, bmac_addr +
1211                                         BIGMAC_REGISTER_BMAC_CONTROL,
1212                                         wb_data, 2);
1213                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1214                         REG_WR_DMAE(bp, bmac_addr +
1215                                         BIGMAC_REGISTER_BMAC_CONTROL,
1216                                         wb_data, 2);
1217                 }
1218                 msleep(1);
1219         }
1220 }
1221
1222 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1223                             u32 line_speed)
1224 {
1225         struct bnx2x *bp = params->bp;
1226         u8 port = params->port;
1227         u32 init_crd, crd;
1228         u32 count = 1000;
1229
1230         /* disable port */
1231         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1232
1233         /* wait for init credit */
1234         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1235         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1236         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1237
1238         while ((init_crd != crd) && count) {
1239                 msleep(5);
1240
1241                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1242                 count--;
1243         }
1244         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1245         if (init_crd != crd) {
1246                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1247                           init_crd, crd);
1248                 return -EINVAL;
1249         }
1250
1251         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1252             line_speed == SPEED_10 ||
1253             line_speed == SPEED_100 ||
1254             line_speed == SPEED_1000 ||
1255             line_speed == SPEED_2500) {
1256                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1257                 /* update threshold */
1258                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1259                 /* update init credit */
1260                 init_crd = 778;         /* (800-18-4) */
1261
1262         } else {
1263                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1264                               ETH_OVREHEAD)/16;
1265                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1266                 /* update threshold */
1267                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1268                 /* update init credit */
1269                 switch (line_speed) {
1270                 case SPEED_10000:
1271                         init_crd = thresh + 553 - 22;
1272                         break;
1273
1274                 case SPEED_12000:
1275                         init_crd = thresh + 664 - 22;
1276                         break;
1277
1278                 case SPEED_13000:
1279                         init_crd = thresh + 742 - 22;
1280                         break;
1281
1282                 case SPEED_16000:
1283                         init_crd = thresh + 778 - 22;
1284                         break;
1285                 default:
1286                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1287                                   line_speed);
1288                         return -EINVAL;
1289                 }
1290         }
1291         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1292         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1293                  line_speed, init_crd);
1294
1295         /* probe the credit changes */
1296         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1297         msleep(5);
1298         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1299
1300         /* enable port */
1301         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1302         return 0;
1303 }
1304
1305 /**
1306  * bnx2x_get_emac_base - retrive emac base address
1307  *
1308  * @bp:                 driver handle
1309  * @mdc_mdio_access:    access type
1310  * @port:               port id
1311  *
1312  * This function selects the MDC/MDIO access (through emac0 or
1313  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1314  * phy has a default access mode, which could also be overridden
1315  * by nvram configuration. This parameter, whether this is the
1316  * default phy configuration, or the nvram overrun
1317  * configuration, is passed here as mdc_mdio_access and selects
1318  * the emac_base for the CL45 read/writes operations
1319  */
1320 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1321                                u32 mdc_mdio_access, u8 port)
1322 {
1323         u32 emac_base = 0;
1324         switch (mdc_mdio_access) {
1325         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1326                 break;
1327         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1328                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1329                         emac_base = GRCBASE_EMAC1;
1330                 else
1331                         emac_base = GRCBASE_EMAC0;
1332                 break;
1333         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1334                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1335                         emac_base = GRCBASE_EMAC0;
1336                 else
1337                         emac_base = GRCBASE_EMAC1;
1338                 break;
1339         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1340                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1341                 break;
1342         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1343                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1344                 break;
1345         default:
1346                 break;
1347         }
1348         return emac_base;
1349
1350 }
1351
1352 /******************************************************************/
1353 /*                      CL45 access functions                     */
1354 /******************************************************************/
1355 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1356                             u8 devad, u16 reg, u16 val)
1357 {
1358         u32 tmp, saved_mode;
1359         u8 i;
1360         int rc = 0;
1361         /*
1362          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1363          * (a value of 49==0x31) and make sure that the AUTO poll is off
1364          */
1365
1366         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1367         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1368                              EMAC_MDIO_MODE_CLOCK_CNT);
1369         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1370                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1371         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1372         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1373         udelay(40);
1374
1375         /* address */
1376
1377         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1378                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1379                EMAC_MDIO_COMM_START_BUSY);
1380         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1381
1382         for (i = 0; i < 50; i++) {
1383                 udelay(10);
1384
1385                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1386                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1387                         udelay(5);
1388                         break;
1389                 }
1390         }
1391         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1393                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1394                 rc = -EFAULT;
1395         } else {
1396                 /* data */
1397                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1398                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1399                        EMAC_MDIO_COMM_START_BUSY);
1400                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1401
1402                 for (i = 0; i < 50; i++) {
1403                         udelay(10);
1404
1405                         tmp = REG_RD(bp, phy->mdio_ctrl +
1406                                      EMAC_REG_EMAC_MDIO_COMM);
1407                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1408                                 udelay(5);
1409                                 break;
1410                         }
1411                 }
1412                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1413                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1414                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1415                         rc = -EFAULT;
1416                 }
1417         }
1418
1419         /* Restore the saved mode */
1420         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1421
1422         return rc;
1423 }
1424
1425 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1426                            u8 devad, u16 reg, u16 *ret_val)
1427 {
1428         u32 val, saved_mode;
1429         u16 i;
1430         int rc = 0;
1431         /*
1432          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1433          * (a value of 49==0x31) and make sure that the AUTO poll is off
1434          */
1435
1436         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1437         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1438                               EMAC_MDIO_MODE_CLOCK_CNT));
1439         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1440                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1441         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1442         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1443         udelay(40);
1444
1445         /* address */
1446         val = ((phy->addr << 21) | (devad << 16) | reg |
1447                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1448                EMAC_MDIO_COMM_START_BUSY);
1449         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1450
1451         for (i = 0; i < 50; i++) {
1452                 udelay(10);
1453
1454                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1455                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1456                         udelay(5);
1457                         break;
1458                 }
1459         }
1460         if (val & EMAC_MDIO_COMM_START_BUSY) {
1461                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1462                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1463                 *ret_val = 0;
1464                 rc = -EFAULT;
1465
1466         } else {
1467                 /* data */
1468                 val = ((phy->addr << 21) | (devad << 16) |
1469                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1470                        EMAC_MDIO_COMM_START_BUSY);
1471                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1472
1473                 for (i = 0; i < 50; i++) {
1474                         udelay(10);
1475
1476                         val = REG_RD(bp, phy->mdio_ctrl +
1477                                      EMAC_REG_EMAC_MDIO_COMM);
1478                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1479                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1480                                 break;
1481                         }
1482                 }
1483                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1484                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1485                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
1486                         *ret_val = 0;
1487                         rc = -EFAULT;
1488                 }
1489         }
1490
1491         /* Restore the saved mode */
1492         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1493
1494         return rc;
1495 }
1496
1497 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1498                    u8 devad, u16 reg, u16 *ret_val)
1499 {
1500         u8 phy_index;
1501         /*
1502          * Probe for the phy according to the given phy_addr, and execute
1503          * the read request on it
1504          */
1505         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1506                 if (params->phy[phy_index].addr == phy_addr) {
1507                         return bnx2x_cl45_read(params->bp,
1508                                                &params->phy[phy_index], devad,
1509                                                reg, ret_val);
1510                 }
1511         }
1512         return -EINVAL;
1513 }
1514
1515 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1516                     u8 devad, u16 reg, u16 val)
1517 {
1518         u8 phy_index;
1519         /*
1520          * Probe for the phy according to the given phy_addr, and execute
1521          * the write request on it
1522          */
1523         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1524                 if (params->phy[phy_index].addr == phy_addr) {
1525                         return bnx2x_cl45_write(params->bp,
1526                                                 &params->phy[phy_index], devad,
1527                                                 reg, val);
1528                 }
1529         }
1530         return -EINVAL;
1531 }
1532
1533 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1534                                    struct bnx2x_phy *phy)
1535 {
1536         u32 ser_lane;
1537         u16 offset, aer_val;
1538         struct bnx2x *bp = params->bp;
1539         ser_lane = ((params->lane_config &
1540                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542
1543         offset = phy->addr + ser_lane;
1544         if (CHIP_IS_E2(bp))
1545                 aer_val = 0x3800 + offset - 1;
1546         else
1547                 aer_val = 0x3800 + offset;
1548         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1549                           MDIO_AER_BLOCK_AER_REG, aer_val);
1550 }
1551 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1552                                      struct bnx2x_phy *phy)
1553 {
1554         CL22_WR_OVER_CL45(bp, phy,
1555                           MDIO_REG_BANK_AER_BLOCK,
1556                           MDIO_AER_BLOCK_AER_REG, 0x3800);
1557 }
1558
1559 /******************************************************************/
1560 /*                      Internal phy section                      */
1561 /******************************************************************/
1562
1563 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1564 {
1565         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1566
1567         /* Set Clause 22 */
1568         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1569         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1570         udelay(500);
1571         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1572         udelay(500);
1573          /* Set Clause 45 */
1574         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1575 }
1576
1577 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1578 {
1579         u32 val;
1580
1581         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1582
1583         val = SERDES_RESET_BITS << (port*16);
1584
1585         /* reset and unreset the SerDes/XGXS */
1586         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1587         udelay(500);
1588         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1589
1590         bnx2x_set_serdes_access(bp, port);
1591
1592         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1593                DEFAULT_PHY_DEV_ADDR);
1594 }
1595
1596 static void bnx2x_xgxs_deassert(struct link_params *params)
1597 {
1598         struct bnx2x *bp = params->bp;
1599         u8 port;
1600         u32 val;
1601         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1602         port = params->port;
1603
1604         val = XGXS_RESET_BITS << (port*16);
1605
1606         /* reset and unreset the SerDes/XGXS */
1607         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1608         udelay(500);
1609         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1610
1611         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1612         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1613                params->phy[INT_PHY].def_md_devad);
1614 }
1615
1616 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
1617                                      struct link_params *params, u16 *ieee_fc)
1618 {
1619         struct bnx2x *bp = params->bp;
1620         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1621         /**
1622          * resolve pause mode and advertisement Please refer to Table
1623          * 28B-3 of the 802.3ab-1999 spec
1624          */
1625
1626         switch (phy->req_flow_ctrl) {
1627         case BNX2X_FLOW_CTRL_AUTO:
1628                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
1629                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1630                 else
1631                         *ieee_fc |=
1632                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1633                 break;
1634
1635         case BNX2X_FLOW_CTRL_TX:
1636                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1637                 break;
1638
1639         case BNX2X_FLOW_CTRL_RX:
1640         case BNX2X_FLOW_CTRL_BOTH:
1641                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1642                 break;
1643
1644         case BNX2X_FLOW_CTRL_NONE:
1645         default:
1646                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1647                 break;
1648         }
1649         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
1650 }
1651
1652 static void set_phy_vars(struct link_params *params,
1653                          struct link_vars *vars)
1654 {
1655         struct bnx2x *bp = params->bp;
1656         u8 actual_phy_idx, phy_index, link_cfg_idx;
1657         u8 phy_config_swapped = params->multi_phy_config &
1658                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
1659         for (phy_index = INT_PHY; phy_index < params->num_phys;
1660               phy_index++) {
1661                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
1662                 actual_phy_idx = phy_index;
1663                 if (phy_config_swapped) {
1664                         if (phy_index == EXT_PHY1)
1665                                 actual_phy_idx = EXT_PHY2;
1666                         else if (phy_index == EXT_PHY2)
1667                                 actual_phy_idx = EXT_PHY1;
1668                 }
1669                 params->phy[actual_phy_idx].req_flow_ctrl =
1670                         params->req_flow_ctrl[link_cfg_idx];
1671
1672                 params->phy[actual_phy_idx].req_line_speed =
1673                         params->req_line_speed[link_cfg_idx];
1674
1675                 params->phy[actual_phy_idx].speed_cap_mask =
1676                         params->speed_cap_mask[link_cfg_idx];
1677
1678                 params->phy[actual_phy_idx].req_duplex =
1679                         params->req_duplex[link_cfg_idx];
1680
1681                 if (params->req_line_speed[link_cfg_idx] ==
1682                     SPEED_AUTO_NEG)
1683                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1684
1685                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
1686                            " speed_cap_mask %x\n",
1687                            params->phy[actual_phy_idx].req_flow_ctrl,
1688                            params->phy[actual_phy_idx].req_line_speed,
1689                            params->phy[actual_phy_idx].speed_cap_mask);
1690         }
1691 }
1692
1693 static void bnx2x_ext_phy_set_pause(struct link_params *params,
1694                                     struct bnx2x_phy *phy,
1695                                     struct link_vars *vars)
1696 {
1697         u16 val;
1698         struct bnx2x *bp = params->bp;
1699         /* read modify write pause advertizing */
1700         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
1701
1702         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
1703
1704         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
1705         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
1706         if ((vars->ieee_fc &
1707             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
1708             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
1709                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
1710         }
1711         if ((vars->ieee_fc &
1712             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
1713             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
1714                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
1715         }
1716         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
1717         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
1718 }
1719
1720 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1721 {                                               /*  LD      LP   */
1722         switch (pause_result) {                 /* ASYM P ASYM P */
1723         case 0xb:                               /*   1  0   1  1 */
1724                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1725                 break;
1726
1727         case 0xe:                               /*   1  1   1  0 */
1728                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1729                 break;
1730
1731         case 0x5:                               /*   0  1   0  1 */
1732         case 0x7:                               /*   0  1   1  1 */
1733         case 0xd:                               /*   1  1   0  1 */
1734         case 0xf:                               /*   1  1   1  1 */
1735                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1736                 break;
1737
1738         default:
1739                 break;
1740         }
1741         if (pause_result & (1<<0))
1742                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
1743         if (pause_result & (1<<1))
1744                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
1745 }
1746
1747 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
1748                                    struct link_params *params,
1749                                    struct link_vars *vars)
1750 {
1751         struct bnx2x *bp = params->bp;
1752         u16 ld_pause;           /* local */
1753         u16 lp_pause;           /* link partner */
1754         u16 pause_result;
1755         u8 ret = 0;
1756         /* read twice */
1757
1758         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1759
1760         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
1761                 vars->flow_ctrl = phy->req_flow_ctrl;
1762         else if (phy->req_line_speed != SPEED_AUTO_NEG)
1763                 vars->flow_ctrl = params->req_fc_auto_adv;
1764         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
1765                 ret = 1;
1766                 bnx2x_cl45_read(bp, phy,
1767                                 MDIO_AN_DEVAD,
1768                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1769                 bnx2x_cl45_read(bp, phy,
1770                                 MDIO_AN_DEVAD,
1771                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1772                 pause_result = (ld_pause &
1773                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1774                 pause_result |= (lp_pause &
1775                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1776                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
1777                    pause_result);
1778                 bnx2x_pause_resolve(vars, pause_result);
1779         }
1780         return ret;
1781 }
1782 void bnx2x_link_status_update(struct link_params *params,
1783                               struct link_vars *vars)
1784 {
1785         struct bnx2x *bp = params->bp;
1786         u8 link_10g;
1787         u8 port = params->port;
1788         u32 sync_offset, media_types;
1789         vars->link_status = REG_RD(bp, params->shmem_base +
1790                                    offsetof(struct shmem_region,
1791                                             port_mb[port].link_status));
1792
1793         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1794
1795         if (vars->link_up) {
1796                 DP(NETIF_MSG_LINK, "phy link up\n");
1797
1798                 vars->phy_link_up = 1;
1799                 vars->duplex = DUPLEX_FULL;
1800                 switch (vars->link_status &
1801                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1802                         case LINK_10THD:
1803                                 vars->duplex = DUPLEX_HALF;
1804                                 /* fall thru */
1805                         case LINK_10TFD:
1806                                 vars->line_speed = SPEED_10;
1807                                 break;
1808
1809                         case LINK_100TXHD:
1810                                 vars->duplex = DUPLEX_HALF;
1811                                 /* fall thru */
1812                         case LINK_100T4:
1813                         case LINK_100TXFD:
1814                                 vars->line_speed = SPEED_100;
1815                                 break;
1816
1817                         case LINK_1000THD:
1818                                 vars->duplex = DUPLEX_HALF;
1819                                 /* fall thru */
1820                         case LINK_1000TFD:
1821                                 vars->line_speed = SPEED_1000;
1822                                 break;
1823
1824                         case LINK_2500THD:
1825                                 vars->duplex = DUPLEX_HALF;
1826                                 /* fall thru */
1827                         case LINK_2500TFD:
1828                                 vars->line_speed = SPEED_2500;
1829                                 break;
1830
1831                         case LINK_10GTFD:
1832                                 vars->line_speed = SPEED_10000;
1833                                 break;
1834
1835                         case LINK_12GTFD:
1836                                 vars->line_speed = SPEED_12000;
1837                                 break;
1838
1839                         case LINK_12_5GTFD:
1840                                 vars->line_speed = SPEED_12500;
1841                                 break;
1842
1843                         case LINK_13GTFD:
1844                                 vars->line_speed = SPEED_13000;
1845                                 break;
1846
1847                         case LINK_15GTFD:
1848                                 vars->line_speed = SPEED_15000;
1849                                 break;
1850
1851                         case LINK_16GTFD:
1852                                 vars->line_speed = SPEED_16000;
1853                                 break;
1854
1855                         default:
1856                                 break;
1857                 }
1858                 vars->flow_ctrl = 0;
1859                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1860                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1861
1862                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1863                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1864
1865                 if (!vars->flow_ctrl)
1866                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1867
1868                 if (vars->line_speed &&
1869                     ((vars->line_speed == SPEED_10) ||
1870                      (vars->line_speed == SPEED_100))) {
1871                         vars->phy_flags |= PHY_SGMII_FLAG;
1872                 } else {
1873                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1874                 }
1875
1876                 /* anything 10 and over uses the bmac */
1877                 link_10g = ((vars->line_speed == SPEED_10000) ||
1878                             (vars->line_speed == SPEED_12000) ||
1879                             (vars->line_speed == SPEED_12500) ||
1880                             (vars->line_speed == SPEED_13000) ||
1881                             (vars->line_speed == SPEED_15000) ||
1882                             (vars->line_speed == SPEED_16000));
1883                 if (link_10g)
1884                         vars->mac_type = MAC_TYPE_BMAC;
1885                 else
1886                         vars->mac_type = MAC_TYPE_EMAC;
1887
1888         } else { /* link down */
1889                 DP(NETIF_MSG_LINK, "phy link down\n");
1890
1891                 vars->phy_link_up = 0;
1892
1893                 vars->line_speed = 0;
1894                 vars->duplex = DUPLEX_FULL;
1895                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1896
1897                 /* indicate no mac active */
1898                 vars->mac_type = MAC_TYPE_NONE;
1899         }
1900
1901         /* Sync media type */
1902         sync_offset = params->shmem_base +
1903                         offsetof(struct shmem_region,
1904                                  dev_info.port_hw_config[port].media_type);
1905         media_types = REG_RD(bp, sync_offset);
1906
1907         params->phy[INT_PHY].media_type =
1908                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
1909                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
1910         params->phy[EXT_PHY1].media_type =
1911                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
1912                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
1913         params->phy[EXT_PHY2].media_type =
1914                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
1915                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
1916         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
1917
1918         /* Sync AEU offset */
1919         sync_offset = params->shmem_base +
1920                         offsetof(struct shmem_region,
1921                                  dev_info.port_hw_config[port].aeu_int_mask);
1922
1923         vars->aeu_int_mask = REG_RD(bp, sync_offset);
1924
1925         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
1926                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
1927         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1928                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1929 }
1930
1931
1932 static void bnx2x_set_master_ln(struct link_params *params,
1933                                 struct bnx2x_phy *phy)
1934 {
1935         struct bnx2x *bp = params->bp;
1936         u16 new_master_ln, ser_lane;
1937         ser_lane = ((params->lane_config &
1938                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1939                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1940
1941         /* set the master_ln for AN */
1942         CL22_RD_OVER_CL45(bp, phy,
1943                           MDIO_REG_BANK_XGXS_BLOCK2,
1944                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1945                           &new_master_ln);
1946
1947         CL22_WR_OVER_CL45(bp, phy,
1948                           MDIO_REG_BANK_XGXS_BLOCK2 ,
1949                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1950                           (new_master_ln | ser_lane));
1951 }
1952
1953 static int bnx2x_reset_unicore(struct link_params *params,
1954                                struct bnx2x_phy *phy,
1955                                u8 set_serdes)
1956 {
1957         struct bnx2x *bp = params->bp;
1958         u16 mii_control;
1959         u16 i;
1960         CL22_RD_OVER_CL45(bp, phy,
1961                           MDIO_REG_BANK_COMBO_IEEE0,
1962                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1963
1964         /* reset the unicore */
1965         CL22_WR_OVER_CL45(bp, phy,
1966                           MDIO_REG_BANK_COMBO_IEEE0,
1967                           MDIO_COMBO_IEEE0_MII_CONTROL,
1968                           (mii_control |
1969                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1970         if (set_serdes)
1971                 bnx2x_set_serdes_access(bp, params->port);
1972
1973         /* wait for the reset to self clear */
1974         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1975                 udelay(5);
1976
1977                 /* the reset erased the previous bank value */
1978                 CL22_RD_OVER_CL45(bp, phy,
1979                                   MDIO_REG_BANK_COMBO_IEEE0,
1980                                   MDIO_COMBO_IEEE0_MII_CONTROL,
1981                                   &mii_control);
1982
1983                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1984                         udelay(5);
1985                         return 0;
1986                 }
1987         }
1988
1989         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
1990                               " Port %d\n",
1991                          params->port);
1992         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1993         return -EINVAL;
1994
1995 }
1996
1997 static void bnx2x_set_swap_lanes(struct link_params *params,
1998                                  struct bnx2x_phy *phy)
1999 {
2000         struct bnx2x *bp = params->bp;
2001         /*
2002          *  Each two bits represents a lane number:
2003          *  No swap is 0123 => 0x1b no need to enable the swap
2004          */
2005         u16 ser_lane, rx_lane_swap, tx_lane_swap;
2006
2007         ser_lane = ((params->lane_config &
2008                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2009                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2010         rx_lane_swap = ((params->lane_config &
2011                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
2012                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
2013         tx_lane_swap = ((params->lane_config &
2014                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
2015                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
2016
2017         if (rx_lane_swap != 0x1b) {
2018                 CL22_WR_OVER_CL45(bp, phy,
2019                                   MDIO_REG_BANK_XGXS_BLOCK2,
2020                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2021                                   (rx_lane_swap |
2022                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2023                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2024         } else {
2025                 CL22_WR_OVER_CL45(bp, phy,
2026                                   MDIO_REG_BANK_XGXS_BLOCK2,
2027                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2028         }
2029
2030         if (tx_lane_swap != 0x1b) {
2031                 CL22_WR_OVER_CL45(bp, phy,
2032                                   MDIO_REG_BANK_XGXS_BLOCK2,
2033                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2034                                   (tx_lane_swap |
2035                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2036         } else {
2037                 CL22_WR_OVER_CL45(bp, phy,
2038                                   MDIO_REG_BANK_XGXS_BLOCK2,
2039                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2040         }
2041 }
2042
2043 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
2044                                          struct link_params *params)
2045 {
2046         struct bnx2x *bp = params->bp;
2047         u16 control2;
2048         CL22_RD_OVER_CL45(bp, phy,
2049                           MDIO_REG_BANK_SERDES_DIGITAL,
2050                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2051                           &control2);
2052         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2053                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2054         else
2055                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2056         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
2057                 phy->speed_cap_mask, control2);
2058         CL22_WR_OVER_CL45(bp, phy,
2059                           MDIO_REG_BANK_SERDES_DIGITAL,
2060                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2061                           control2);
2062
2063         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2064              (phy->speed_cap_mask &
2065                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
2066                 DP(NETIF_MSG_LINK, "XGXS\n");
2067
2068                 CL22_WR_OVER_CL45(bp, phy,
2069                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
2070                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2071                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2072
2073                 CL22_RD_OVER_CL45(bp, phy,
2074                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2075                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2076                                   &control2);
2077
2078
2079                 control2 |=
2080                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2081
2082                 CL22_WR_OVER_CL45(bp, phy,
2083                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
2084                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2085                                   control2);
2086
2087                 /* Disable parallel detection of HiG */
2088                 CL22_WR_OVER_CL45(bp, phy,
2089                                   MDIO_REG_BANK_XGXS_BLOCK2,
2090                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2091                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2092                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2093         }
2094 }
2095
2096 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
2097                               struct link_params *params,
2098                               struct link_vars *vars,
2099                               u8 enable_cl73)
2100 {
2101         struct bnx2x *bp = params->bp;
2102         u16 reg_val;
2103
2104         /* CL37 Autoneg */
2105         CL22_RD_OVER_CL45(bp, phy,
2106                           MDIO_REG_BANK_COMBO_IEEE0,
2107                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2108
2109         /* CL37 Autoneg Enabled */
2110         if (vars->line_speed == SPEED_AUTO_NEG)
2111                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2112         else /* CL37 Autoneg Disabled */
2113                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2114                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2115
2116         CL22_WR_OVER_CL45(bp, phy,
2117                           MDIO_REG_BANK_COMBO_IEEE0,
2118                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2119
2120         /* Enable/Disable Autodetection */
2121
2122         CL22_RD_OVER_CL45(bp, phy,
2123                           MDIO_REG_BANK_SERDES_DIGITAL,
2124                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2125         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
2126                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
2127         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
2128         if (vars->line_speed == SPEED_AUTO_NEG)
2129                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2130         else
2131                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2132
2133         CL22_WR_OVER_CL45(bp, phy,
2134                           MDIO_REG_BANK_SERDES_DIGITAL,
2135                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2136
2137         /* Enable TetonII and BAM autoneg */
2138         CL22_RD_OVER_CL45(bp, phy,
2139                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2140                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2141                           &reg_val);
2142         if (vars->line_speed == SPEED_AUTO_NEG) {
2143                 /* Enable BAM aneg Mode and TetonII aneg Mode */
2144                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2145                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2146         } else {
2147                 /* TetonII and BAM Autoneg Disabled */
2148                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2149                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2150         }
2151         CL22_WR_OVER_CL45(bp, phy,
2152                           MDIO_REG_BANK_BAM_NEXT_PAGE,
2153                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2154                           reg_val);
2155
2156         if (enable_cl73) {
2157                 /* Enable Cl73 FSM status bits */
2158                 CL22_WR_OVER_CL45(bp, phy,
2159                                   MDIO_REG_BANK_CL73_USERB0,
2160                                   MDIO_CL73_USERB0_CL73_UCTRL,
2161                                   0xe);
2162
2163                 /* Enable BAM Station Manager*/
2164                 CL22_WR_OVER_CL45(bp, phy,
2165                         MDIO_REG_BANK_CL73_USERB0,
2166                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2167                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2168                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2169                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2170
2171                 /* Advertise CL73 link speeds */
2172                 CL22_RD_OVER_CL45(bp, phy,
2173                                   MDIO_REG_BANK_CL73_IEEEB1,
2174                                   MDIO_CL73_IEEEB1_AN_ADV2,
2175                                   &reg_val);
2176                 if (phy->speed_cap_mask &
2177                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2178                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2179                 if (phy->speed_cap_mask &
2180                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2181                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2182
2183                 CL22_WR_OVER_CL45(bp, phy,
2184                                   MDIO_REG_BANK_CL73_IEEEB1,
2185                                   MDIO_CL73_IEEEB1_AN_ADV2,
2186                                   reg_val);
2187
2188                 /* CL73 Autoneg Enabled */
2189                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2190
2191         } else /* CL73 Autoneg Disabled */
2192                 reg_val = 0;
2193
2194         CL22_WR_OVER_CL45(bp, phy,
2195                           MDIO_REG_BANK_CL73_IEEEB0,
2196                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2197 }
2198
2199 /* program SerDes, forced speed */
2200 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2201                                  struct link_params *params,
2202                                  struct link_vars *vars)
2203 {
2204         struct bnx2x *bp = params->bp;
2205         u16 reg_val;
2206
2207         /* program duplex, disable autoneg and sgmii*/
2208         CL22_RD_OVER_CL45(bp, phy,
2209                           MDIO_REG_BANK_COMBO_IEEE0,
2210                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2211         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2212                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2213                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2214         if (phy->req_duplex == DUPLEX_FULL)
2215                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2216         CL22_WR_OVER_CL45(bp, phy,
2217                           MDIO_REG_BANK_COMBO_IEEE0,
2218                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2219
2220         /*
2221          * program speed
2222          *  - needed only if the speed is greater than 1G (2.5G or 10G)
2223          */
2224         CL22_RD_OVER_CL45(bp, phy,
2225                           MDIO_REG_BANK_SERDES_DIGITAL,
2226                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2227         /* clearing the speed value before setting the right speed */
2228         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2229
2230         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2231                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2232
2233         if (!((vars->line_speed == SPEED_1000) ||
2234               (vars->line_speed == SPEED_100) ||
2235               (vars->line_speed == SPEED_10))) {
2236
2237                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2238                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2239                 if (vars->line_speed == SPEED_10000)
2240                         reg_val |=
2241                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2242                 if (vars->line_speed == SPEED_13000)
2243                         reg_val |=
2244                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2245         }
2246
2247         CL22_WR_OVER_CL45(bp, phy,
2248                           MDIO_REG_BANK_SERDES_DIGITAL,
2249                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
2250
2251 }
2252
2253 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
2254                                               struct link_params *params)
2255 {
2256         struct bnx2x *bp = params->bp;
2257         u16 val = 0;
2258
2259         /* configure the 48 bits for BAM AN */
2260
2261         /* set extended capabilities */
2262         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2263                 val |= MDIO_OVER_1G_UP1_2_5G;
2264         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2265                 val |= MDIO_OVER_1G_UP1_10G;
2266         CL22_WR_OVER_CL45(bp, phy,
2267                           MDIO_REG_BANK_OVER_1G,
2268                           MDIO_OVER_1G_UP1, val);
2269
2270         CL22_WR_OVER_CL45(bp, phy,
2271                           MDIO_REG_BANK_OVER_1G,
2272                           MDIO_OVER_1G_UP3, 0x400);
2273 }
2274
2275 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
2276                                               struct link_params *params,
2277                                               u16 ieee_fc)
2278 {
2279         struct bnx2x *bp = params->bp;
2280         u16 val;
2281         /* for AN, we are always publishing full duplex */
2282
2283         CL22_WR_OVER_CL45(bp, phy,
2284                           MDIO_REG_BANK_COMBO_IEEE0,
2285                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2286         CL22_RD_OVER_CL45(bp, phy,
2287                           MDIO_REG_BANK_CL73_IEEEB1,
2288                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
2289         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2290         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2291         CL22_WR_OVER_CL45(bp, phy,
2292                           MDIO_REG_BANK_CL73_IEEEB1,
2293                           MDIO_CL73_IEEEB1_AN_ADV1, val);
2294 }
2295
2296 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2297                                   struct link_params *params,
2298                                   u8 enable_cl73)
2299 {
2300         struct bnx2x *bp = params->bp;
2301         u16 mii_control;
2302
2303         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2304         /* Enable and restart BAM/CL37 aneg */
2305
2306         if (enable_cl73) {
2307                 CL22_RD_OVER_CL45(bp, phy,
2308                                   MDIO_REG_BANK_CL73_IEEEB0,
2309                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2310                                   &mii_control);
2311
2312                 CL22_WR_OVER_CL45(bp, phy,
2313                                   MDIO_REG_BANK_CL73_IEEEB0,
2314                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2315                                   (mii_control |
2316                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2317                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2318         } else {
2319
2320                 CL22_RD_OVER_CL45(bp, phy,
2321                                   MDIO_REG_BANK_COMBO_IEEE0,
2322                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2323                                   &mii_control);
2324                 DP(NETIF_MSG_LINK,
2325                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2326                          mii_control);
2327                 CL22_WR_OVER_CL45(bp, phy,
2328                                   MDIO_REG_BANK_COMBO_IEEE0,
2329                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2330                                   (mii_control |
2331                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2332                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2333         }
2334 }
2335
2336 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2337                                            struct link_params *params,
2338                                            struct link_vars *vars)
2339 {
2340         struct bnx2x *bp = params->bp;
2341         u16 control1;
2342
2343         /* in SGMII mode, the unicore is always slave */
2344
2345         CL22_RD_OVER_CL45(bp, phy,
2346                           MDIO_REG_BANK_SERDES_DIGITAL,
2347                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2348                           &control1);
2349         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2350         /* set sgmii mode (and not fiber) */
2351         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2352                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2353                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2354         CL22_WR_OVER_CL45(bp, phy,
2355                           MDIO_REG_BANK_SERDES_DIGITAL,
2356                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2357                           control1);
2358
2359         /* if forced speed */
2360         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2361                 /* set speed, disable autoneg */
2362                 u16 mii_control;
2363
2364                 CL22_RD_OVER_CL45(bp, phy,
2365                                   MDIO_REG_BANK_COMBO_IEEE0,
2366                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2367                                   &mii_control);
2368                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2369                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2370                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2371
2372                 switch (vars->line_speed) {
2373                 case SPEED_100:
2374                         mii_control |=
2375                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2376                         break;
2377                 case SPEED_1000:
2378                         mii_control |=
2379                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2380                         break;
2381                 case SPEED_10:
2382                         /* there is nothing to set for 10M */
2383                         break;
2384                 default:
2385                         /* invalid speed for SGMII */
2386                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2387                                   vars->line_speed);
2388                         break;
2389                 }
2390
2391                 /* setting the full duplex */
2392                 if (phy->req_duplex == DUPLEX_FULL)
2393                         mii_control |=
2394                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2395                 CL22_WR_OVER_CL45(bp, phy,
2396                                   MDIO_REG_BANK_COMBO_IEEE0,
2397                                   MDIO_COMBO_IEEE0_MII_CONTROL,
2398                                   mii_control);
2399
2400         } else { /* AN mode */
2401                 /* enable and restart AN */
2402                 bnx2x_restart_autoneg(phy, params, 0);
2403         }
2404 }
2405
2406
2407 /*
2408  * link management
2409  */
2410
2411 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2412                                              struct link_params *params)
2413 {
2414         struct bnx2x *bp = params->bp;
2415         u16 pd_10g, status2_1000x;
2416         if (phy->req_line_speed != SPEED_AUTO_NEG)
2417                 return 0;
2418         CL22_RD_OVER_CL45(bp, phy,
2419                           MDIO_REG_BANK_SERDES_DIGITAL,
2420                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2421                           &status2_1000x);
2422         CL22_RD_OVER_CL45(bp, phy,
2423                           MDIO_REG_BANK_SERDES_DIGITAL,
2424                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2425                           &status2_1000x);
2426         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2427                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2428                          params->port);
2429                 return 1;
2430         }
2431
2432         CL22_RD_OVER_CL45(bp, phy,
2433                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
2434                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2435                           &pd_10g);
2436
2437         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2438                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2439                          params->port);
2440                 return 1;
2441         }
2442         return 0;
2443 }
2444
2445 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2446                                     struct link_params *params,
2447                                     struct link_vars *vars,
2448                                     u32 gp_status)
2449 {
2450         struct bnx2x *bp = params->bp;
2451         u16 ld_pause;   /* local driver */
2452         u16 lp_pause;   /* link partner */
2453         u16 pause_result;
2454
2455         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2456
2457         /* resolve from gp_status in case of AN complete and not sgmii */
2458         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2459                 vars->flow_ctrl = phy->req_flow_ctrl;
2460         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2461                 vars->flow_ctrl = params->req_fc_auto_adv;
2462         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2463                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2464                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2465                         vars->flow_ctrl = params->req_fc_auto_adv;
2466                         return;
2467                 }
2468                 if ((gp_status &
2469                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2470                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2471                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2472                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2473
2474                         CL22_RD_OVER_CL45(bp, phy,
2475                                           MDIO_REG_BANK_CL73_IEEEB1,
2476                                           MDIO_CL73_IEEEB1_AN_ADV1,
2477                                           &ld_pause);
2478                         CL22_RD_OVER_CL45(bp, phy,
2479                                           MDIO_REG_BANK_CL73_IEEEB1,
2480                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
2481                                           &lp_pause);
2482                         pause_result = (ld_pause &
2483                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2484                                         >> 8;
2485                         pause_result |= (lp_pause &
2486                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2487                                         >> 10;
2488                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2489                                  pause_result);
2490                 } else {
2491                         CL22_RD_OVER_CL45(bp, phy,
2492                                           MDIO_REG_BANK_COMBO_IEEE0,
2493                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2494                                           &ld_pause);
2495                         CL22_RD_OVER_CL45(bp, phy,
2496                                 MDIO_REG_BANK_COMBO_IEEE0,
2497                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2498                                 &lp_pause);
2499                         pause_result = (ld_pause &
2500                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2501                         pause_result |= (lp_pause &
2502                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2503                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2504                                  pause_result);
2505                 }
2506                 bnx2x_pause_resolve(vars, pause_result);
2507         }
2508         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2509 }
2510
2511 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2512                                          struct link_params *params)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u16 rx_status, ustat_val, cl37_fsm_received;
2516         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2517         /* Step 1: Make sure signal is detected */
2518         CL22_RD_OVER_CL45(bp, phy,
2519                           MDIO_REG_BANK_RX0,
2520                           MDIO_RX0_RX_STATUS,
2521                           &rx_status);
2522         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2523             (MDIO_RX0_RX_STATUS_SIGDET)) {
2524                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2525                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2526                 CL22_WR_OVER_CL45(bp, phy,
2527                                   MDIO_REG_BANK_CL73_IEEEB0,
2528                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2529                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2530                 return;
2531         }
2532         /* Step 2: Check CL73 state machine */
2533         CL22_RD_OVER_CL45(bp, phy,
2534                           MDIO_REG_BANK_CL73_USERB0,
2535                           MDIO_CL73_USERB0_CL73_USTAT1,
2536                           &ustat_val);
2537         if ((ustat_val &
2538              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2539               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2540             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2541               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2542                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2543                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2544                 return;
2545         }
2546         /*
2547          * Step 3: Check CL37 Message Pages received to indicate LP
2548          * supports only CL37
2549          */
2550         CL22_RD_OVER_CL45(bp, phy,
2551                           MDIO_REG_BANK_REMOTE_PHY,
2552                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
2553                           &cl37_fsm_received);
2554         if ((cl37_fsm_received &
2555              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2556              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2557             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2558               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2559                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2560                              "misc_rx_status(0x8330) = 0x%x\n",
2561                          cl37_fsm_received);
2562                 return;
2563         }
2564         /*
2565          * The combined cl37/cl73 fsm state information indicating that
2566          * we are connected to a device which does not support cl73, but
2567          * does support cl37 BAM. In this case we disable cl73 and
2568          * restart cl37 auto-neg
2569          */
2570
2571         /* Disable CL73 */
2572         CL22_WR_OVER_CL45(bp, phy,
2573                           MDIO_REG_BANK_CL73_IEEEB0,
2574                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2575                           0);
2576         /* Restart CL37 autoneg */
2577         bnx2x_restart_autoneg(phy, params, 0);
2578         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2579 }
2580
2581 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2582                                   struct link_params *params,
2583                                   struct link_vars *vars,
2584                                   u32 gp_status)
2585 {
2586         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2587                 vars->link_status |=
2588                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2589
2590         if (bnx2x_direct_parallel_detect_used(phy, params))
2591                 vars->link_status |=
2592                         LINK_STATUS_PARALLEL_DETECTION_USED;
2593 }
2594
2595 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
2596                                       struct link_params *params,
2597                                       struct link_vars *vars)
2598 {
2599         struct bnx2x *bp = params->bp;
2600         u16 new_line_speed, gp_status;
2601         int rc = 0;
2602
2603         /* Read gp_status */
2604         CL22_RD_OVER_CL45(bp, phy,
2605                           MDIO_REG_BANK_GP_STATUS,
2606                           MDIO_GP_STATUS_TOP_AN_STATUS1,
2607                           &gp_status);
2608
2609         if (phy->req_line_speed == SPEED_AUTO_NEG)
2610                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2611         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2612                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2613                          gp_status);
2614
2615                 vars->phy_link_up = 1;
2616                 vars->link_status |= LINK_STATUS_LINK_UP;
2617
2618                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2619                         vars->duplex = DUPLEX_FULL;
2620                 else
2621                         vars->duplex = DUPLEX_HALF;
2622
2623                 if (SINGLE_MEDIA_DIRECT(params)) {
2624                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2625                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2626                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2627                                                       gp_status);
2628                 }
2629
2630                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2631                 case GP_STATUS_10M:
2632                         new_line_speed = SPEED_10;
2633                         if (vars->duplex == DUPLEX_FULL)
2634                                 vars->link_status |= LINK_10TFD;
2635                         else
2636                                 vars->link_status |= LINK_10THD;
2637                         break;
2638
2639                 case GP_STATUS_100M:
2640                         new_line_speed = SPEED_100;
2641                         if (vars->duplex == DUPLEX_FULL)
2642                                 vars->link_status |= LINK_100TXFD;
2643                         else
2644                                 vars->link_status |= LINK_100TXHD;
2645                         break;
2646
2647                 case GP_STATUS_1G:
2648                 case GP_STATUS_1G_KX:
2649                         new_line_speed = SPEED_1000;
2650                         if (vars->duplex == DUPLEX_FULL)
2651                                 vars->link_status |= LINK_1000TFD;
2652                         else
2653                                 vars->link_status |= LINK_1000THD;
2654                         break;
2655
2656                 case GP_STATUS_2_5G:
2657                         new_line_speed = SPEED_2500;
2658                         if (vars->duplex == DUPLEX_FULL)
2659                                 vars->link_status |= LINK_2500TFD;
2660                         else
2661                                 vars->link_status |= LINK_2500THD;
2662                         break;
2663
2664                 case GP_STATUS_5G:
2665                 case GP_STATUS_6G:
2666                         DP(NETIF_MSG_LINK,
2667                                  "link speed unsupported  gp_status 0x%x\n",
2668                                   gp_status);
2669                         return -EINVAL;
2670
2671                 case GP_STATUS_10G_KX4:
2672                 case GP_STATUS_10G_HIG:
2673                 case GP_STATUS_10G_CX4:
2674                         new_line_speed = SPEED_10000;
2675                         vars->link_status |= LINK_10GTFD;
2676                         break;
2677
2678                 case GP_STATUS_12G_HIG:
2679                         new_line_speed = SPEED_12000;
2680                         vars->link_status |= LINK_12GTFD;
2681                         break;
2682
2683                 case GP_STATUS_12_5G:
2684                         new_line_speed = SPEED_12500;
2685                         vars->link_status |= LINK_12_5GTFD;
2686                         break;
2687
2688                 case GP_STATUS_13G:
2689                         new_line_speed = SPEED_13000;
2690                         vars->link_status |= LINK_13GTFD;
2691                         break;
2692
2693                 case GP_STATUS_15G:
2694                         new_line_speed = SPEED_15000;
2695                         vars->link_status |= LINK_15GTFD;
2696                         break;
2697
2698                 case GP_STATUS_16G:
2699                         new_line_speed = SPEED_16000;
2700                         vars->link_status |= LINK_16GTFD;
2701                         break;
2702
2703                 default:
2704                         DP(NETIF_MSG_LINK,
2705                                   "link speed unsupported gp_status 0x%x\n",
2706                                   gp_status);
2707                         return -EINVAL;
2708                 }
2709
2710                 vars->line_speed = new_line_speed;
2711
2712         } else { /* link_down */
2713                 DP(NETIF_MSG_LINK, "phy link down\n");
2714
2715                 vars->phy_link_up = 0;
2716
2717                 vars->duplex = DUPLEX_FULL;
2718                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2719                 vars->mac_type = MAC_TYPE_NONE;
2720
2721                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2722                     SINGLE_MEDIA_DIRECT(params)) {
2723                         /* Check signal is detected */
2724                         bnx2x_check_fallback_to_cl37(phy, params);
2725                 }
2726         }
2727
2728         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2729                  gp_status, vars->phy_link_up, vars->line_speed);
2730         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2731                    vars->duplex, vars->flow_ctrl, vars->link_status);
2732         return rc;
2733 }
2734
2735 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2736 {
2737         struct bnx2x *bp = params->bp;
2738         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2739         u16 lp_up2;
2740         u16 tx_driver;
2741         u16 bank;
2742
2743         /* read precomp */
2744         CL22_RD_OVER_CL45(bp, phy,
2745                           MDIO_REG_BANK_OVER_1G,
2746                           MDIO_OVER_1G_LP_UP2, &lp_up2);
2747
2748         /* bits [10:7] at lp_up2, positioned at [15:12] */
2749         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2750                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2751                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2752
2753         if (lp_up2 == 0)
2754                 return;
2755
2756         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2757               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2758                 CL22_RD_OVER_CL45(bp, phy,
2759                                   bank,
2760                                   MDIO_TX0_TX_DRIVER, &tx_driver);
2761
2762                 /* replace tx_driver bits [15:12] */
2763                 if (lp_up2 !=
2764                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2765                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2766                         tx_driver |= lp_up2;
2767                         CL22_WR_OVER_CL45(bp, phy,
2768                                           bank,
2769                                           MDIO_TX0_TX_DRIVER, tx_driver);
2770                 }
2771         }
2772 }
2773
2774 static int bnx2x_emac_program(struct link_params *params,
2775                               struct link_vars *vars)
2776 {
2777         struct bnx2x *bp = params->bp;
2778         u8 port = params->port;
2779         u16 mode = 0;
2780
2781         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2782         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2783                        EMAC_REG_EMAC_MODE,
2784                        (EMAC_MODE_25G_MODE |
2785                         EMAC_MODE_PORT_MII_10M |
2786                         EMAC_MODE_HALF_DUPLEX));
2787         switch (vars->line_speed) {
2788         case SPEED_10:
2789                 mode |= EMAC_MODE_PORT_MII_10M;
2790                 break;
2791
2792         case SPEED_100:
2793                 mode |= EMAC_MODE_PORT_MII;
2794                 break;
2795
2796         case SPEED_1000:
2797                 mode |= EMAC_MODE_PORT_GMII;
2798                 break;
2799
2800         case SPEED_2500:
2801                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2802                 break;
2803
2804         default:
2805                 /* 10G not valid for EMAC */
2806                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2807                            vars->line_speed);
2808                 return -EINVAL;
2809         }
2810
2811         if (vars->duplex == DUPLEX_HALF)
2812                 mode |= EMAC_MODE_HALF_DUPLEX;
2813         bnx2x_bits_en(bp,
2814                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2815                       mode);
2816
2817         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2818         return 0;
2819 }
2820
2821 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2822                                   struct link_params *params)
2823 {
2824
2825         u16 bank, i = 0;
2826         struct bnx2x *bp = params->bp;
2827
2828         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2829               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2830                         CL22_WR_OVER_CL45(bp, phy,
2831                                           bank,
2832                                           MDIO_RX0_RX_EQ_BOOST,
2833                                           phy->rx_preemphasis[i]);
2834         }
2835
2836         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2837                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2838                         CL22_WR_OVER_CL45(bp, phy,
2839                                           bank,
2840                                           MDIO_TX0_TX_DRIVER,
2841                                           phy->tx_preemphasis[i]);
2842         }
2843 }
2844
2845 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2846                                     struct link_params *params,
2847                                     struct link_vars *vars)
2848 {
2849         struct bnx2x *bp = params->bp;
2850         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2851                           (params->loopback_mode == LOOPBACK_XGXS));
2852         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2853                 if (SINGLE_MEDIA_DIRECT(params) &&
2854                     (params->feature_config_flags &
2855                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2856                         bnx2x_set_preemphasis(phy, params);
2857
2858                 /* forced speed requested? */
2859                 if (vars->line_speed != SPEED_AUTO_NEG ||
2860                     (SINGLE_MEDIA_DIRECT(params) &&
2861                      params->loopback_mode == LOOPBACK_EXT)) {
2862                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2863
2864                         /* disable autoneg */
2865                         bnx2x_set_autoneg(phy, params, vars, 0);
2866
2867                         /* program speed and duplex */
2868                         bnx2x_program_serdes(phy, params, vars);
2869
2870                 } else { /* AN_mode */
2871                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2872
2873                         /* AN enabled */
2874                         bnx2x_set_brcm_cl37_advertisement(phy, params);
2875
2876                         /* program duplex & pause advertisement (for aneg) */
2877                         bnx2x_set_ieee_aneg_advertisement(phy, params,
2878                                                           vars->ieee_fc);
2879
2880                         /* enable autoneg */
2881                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2882
2883                         /* enable and restart AN */
2884                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2885                 }
2886
2887         } else { /* SGMII mode */
2888                 DP(NETIF_MSG_LINK, "SGMII\n");
2889
2890                 bnx2x_initialize_sgmii_process(phy, params, vars);
2891         }
2892 }
2893
2894 static int bnx2x_init_serdes(struct bnx2x_phy *phy,
2895                              struct link_params *params,
2896                              struct link_vars *vars)
2897 {
2898         int rc;
2899         vars->phy_flags |= PHY_SGMII_FLAG;
2900         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2901         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2902         rc = bnx2x_reset_unicore(params, phy, 1);
2903         /* reset the SerDes and wait for reset bit return low */
2904         if (rc != 0)
2905                 return rc;
2906         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2907
2908         return rc;
2909 }
2910
2911 static int bnx2x_init_xgxs(struct bnx2x_phy *phy,
2912                            struct link_params *params,
2913                            struct link_vars *vars)
2914 {
2915         int rc;
2916         vars->phy_flags = PHY_XGXS_FLAG;
2917         if ((phy->req_line_speed &&
2918              ((phy->req_line_speed == SPEED_100) ||
2919               (phy->req_line_speed == SPEED_10))) ||
2920             (!phy->req_line_speed &&
2921              (phy->speed_cap_mask >=
2922               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2923              (phy->speed_cap_mask <
2924               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2925              ))
2926                 vars->phy_flags |= PHY_SGMII_FLAG;
2927         else
2928                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2929
2930         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2931         bnx2x_set_aer_mmd_xgxs(params, phy);
2932         bnx2x_set_master_ln(params, phy);
2933
2934         rc = bnx2x_reset_unicore(params, phy, 0);
2935         /* reset the SerDes and wait for reset bit return low */
2936         if (rc != 0)
2937                 return rc;
2938
2939         bnx2x_set_aer_mmd_xgxs(params, phy);
2940
2941         /* setting the masterLn_def again after the reset */
2942         bnx2x_set_master_ln(params, phy);
2943         bnx2x_set_swap_lanes(params, phy);
2944
2945         return rc;
2946 }
2947
2948 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2949                                      struct bnx2x_phy *phy,
2950                                      struct link_params *params)
2951 {
2952         u16 cnt, ctrl;
2953         /* Wait for soft reset to get cleared up to 1 sec */
2954         for (cnt = 0; cnt < 1000; cnt++) {
2955                 bnx2x_cl45_read(bp, phy,
2956                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2957                 if (!(ctrl & (1<<15)))
2958                         break;
2959                 msleep(1);
2960         }
2961
2962         if (cnt == 1000)
2963                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
2964                                       " Port %d\n",
2965                          params->port);
2966         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2967         return cnt;
2968 }
2969
2970 static void bnx2x_link_int_enable(struct link_params *params)
2971 {
2972         u8 port = params->port;
2973         u32 mask;
2974         struct bnx2x *bp = params->bp;
2975
2976         /* Setting the status to report on link up for either XGXS or SerDes */
2977         if (params->switch_cfg == SWITCH_CFG_10G) {
2978                 mask = (NIG_MASK_XGXS0_LINK10G |
2979                         NIG_MASK_XGXS0_LINK_STATUS);
2980                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2981                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2982                         params->phy[INT_PHY].type !=
2983                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2984                         mask |= NIG_MASK_MI_INT;
2985                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2986                 }
2987
2988         } else { /* SerDes */
2989                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2990                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2991                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2992                         params->phy[INT_PHY].type !=
2993                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2994                         mask |= NIG_MASK_MI_INT;
2995                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2996                 }
2997         }
2998         bnx2x_bits_en(bp,
2999                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3000                       mask);
3001
3002         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
3003                  (params->switch_cfg == SWITCH_CFG_10G),
3004                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3005         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
3006                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3007                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3008                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
3009         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3010            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3011            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3012 }
3013
3014 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
3015                                      u8 exp_mi_int)
3016 {
3017         u32 latch_status = 0;
3018
3019         /*
3020          * Disable the MI INT ( external phy int ) by writing 1 to the
3021          * status register. Link down indication is high-active-signal,
3022          * so in this case we need to write the status to clear the XOR
3023          */
3024         /* Read Latched signals */
3025         latch_status = REG_RD(bp,
3026                                     NIG_REG_LATCH_STATUS_0 + port*8);
3027         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
3028         /* Handle only those with latched-signal=up.*/
3029         if (exp_mi_int)
3030                 bnx2x_bits_en(bp,
3031                               NIG_REG_STATUS_INTERRUPT_PORT0
3032                               + port*4,
3033                               NIG_STATUS_EMAC0_MI_INT);
3034         else
3035                 bnx2x_bits_dis(bp,
3036                                NIG_REG_STATUS_INTERRUPT_PORT0
3037                                + port*4,
3038                                NIG_STATUS_EMAC0_MI_INT);
3039
3040         if (latch_status & 1) {
3041
3042                 /* For all latched-signal=up : Re-Arm Latch signals */
3043                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
3044                        (latch_status & 0xfffe) | (latch_status & 1));
3045         }
3046         /* For all latched-signal=up,Write original_signal to status */
3047 }
3048
3049 static void bnx2x_link_int_ack(struct link_params *params,
3050                                struct link_vars *vars, u8 is_10g)
3051 {
3052         struct bnx2x *bp = params->bp;
3053         u8 port = params->port;
3054
3055         /*
3056          * First reset all status we assume only one line will be
3057          * change at a time
3058          */
3059         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3060                        (NIG_STATUS_XGXS0_LINK10G |
3061                         NIG_STATUS_XGXS0_LINK_STATUS |
3062                         NIG_STATUS_SERDES0_LINK_STATUS));
3063         if (vars->phy_link_up) {
3064                 if (is_10g) {
3065                         /*
3066                          * Disable the 10G link interrupt by writing 1 to the
3067                          * status register
3068                          */
3069                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
3070                         bnx2x_bits_en(bp,
3071                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3072                                       NIG_STATUS_XGXS0_LINK10G);
3073
3074                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
3075                         /*
3076                          * Disable the link interrupt by writing 1 to the
3077                          * relevant lane in the status register
3078                          */
3079                         u32 ser_lane = ((params->lane_config &
3080                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3081                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3082
3083                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
3084                                  vars->line_speed);
3085                         bnx2x_bits_en(bp,
3086                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3087                                       ((1 << ser_lane) <<
3088                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
3089
3090                 } else { /* SerDes */
3091                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
3092                         /*
3093                          * Disable the link interrupt by writing 1 to the status
3094                          * register
3095                          */
3096                         bnx2x_bits_en(bp,
3097                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3098                                       NIG_STATUS_SERDES0_LINK_STATUS);
3099                 }
3100
3101         }
3102 }
3103
3104 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
3105 {
3106         u8 *str_ptr = str;
3107         u32 mask = 0xf0000000;
3108         u8 shift = 8*4;
3109         u8 digit;
3110         u8 remove_leading_zeros = 1;
3111         if (*len < 10) {
3112                 /* Need more than 10chars for this format */
3113                 *str_ptr = '\0';
3114                 (*len)--;
3115                 return -EINVAL;
3116         }
3117         while (shift > 0) {
3118
3119                 shift -= 4;
3120                 digit = ((num & mask) >> shift);
3121                 if (digit == 0 && remove_leading_zeros) {
3122                         mask = mask >> 4;
3123                         continue;
3124                 } else if (digit < 0xa)
3125                         *str_ptr = digit + '0';
3126                 else
3127                         *str_ptr = digit - 0xa + 'a';
3128                 remove_leading_zeros = 0;
3129                 str_ptr++;
3130                 (*len)--;
3131                 mask = mask >> 4;
3132                 if (shift == 4*4) {
3133                         *str_ptr = '.';
3134                         str_ptr++;
3135                         (*len)--;
3136                         remove_leading_zeros = 1;
3137                 }
3138         }
3139         return 0;
3140 }
3141
3142
3143 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3144 {
3145         str[0] = '\0';
3146         (*len)--;
3147         return 0;
3148 }
3149
3150 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3151                                  u8 *version, u16 len)
3152 {
3153         struct bnx2x *bp;
3154         u32 spirom_ver = 0;
3155         int status = 0;
3156         u8 *ver_p = version;
3157         u16 remain_len = len;
3158         if (version == NULL || params == NULL)
3159                 return -EINVAL;
3160         bp = params->bp;
3161
3162         /* Extract first external phy*/
3163         version[0] = '\0';
3164         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3165
3166         if (params->phy[EXT_PHY1].format_fw_ver) {
3167                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3168                                                               ver_p,
3169                                                               &remain_len);
3170                 ver_p += (len - remain_len);
3171         }
3172         if ((params->num_phys == MAX_PHYS) &&
3173             (params->phy[EXT_PHY2].ver_addr != 0)) {
3174                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3175                 if (params->phy[EXT_PHY2].format_fw_ver) {
3176                         *ver_p = '/';
3177                         ver_p++;
3178                         remain_len--;
3179                         status |= params->phy[EXT_PHY2].format_fw_ver(
3180                                 spirom_ver,
3181                                 ver_p,
3182                                 &remain_len);
3183                         ver_p = version + (len - remain_len);
3184                 }
3185         }
3186         *ver_p = '\0';
3187         return status;
3188 }
3189
3190 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3191                                     struct link_params *params)
3192 {
3193         u8 port = params->port;
3194         struct bnx2x *bp = params->bp;
3195
3196         if (phy->req_line_speed != SPEED_1000) {
3197                 u32 md_devad;
3198
3199                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3200
3201                 /* change the uni_phy_addr in the nig */
3202                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3203                                        port*0x18));
3204
3205                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3206
3207                 bnx2x_cl45_write(bp, phy,
3208                                  5,
3209                                  (MDIO_REG_BANK_AER_BLOCK +
3210                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
3211                                  0x2800);
3212
3213                 bnx2x_cl45_write(bp, phy,
3214                                  5,
3215                                  (MDIO_REG_BANK_CL73_IEEEB0 +
3216                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3217                                  0x6041);
3218                 msleep(200);
3219                 /* set aer mmd back */
3220                 bnx2x_set_aer_mmd_xgxs(params, phy);
3221
3222                 /* and md_devad */
3223                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3224         } else {
3225                 u16 mii_ctrl;
3226                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3227                 bnx2x_cl45_read(bp, phy, 5,
3228                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3229                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3230                                 &mii_ctrl);
3231                 bnx2x_cl45_write(bp, phy, 5,
3232                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3233                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3234                                  mii_ctrl |
3235                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3236         }
3237 }
3238
3239 int bnx2x_set_led(struct link_params *params,
3240                   struct link_vars *vars, u8 mode, u32 speed)
3241 {
3242         u8 port = params->port;
3243         u16 hw_led_mode = params->hw_led_mode;
3244         int rc = 0;
3245         u8 phy_idx;
3246         u32 tmp;
3247         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3248         struct bnx2x *bp = params->bp;
3249         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3250         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3251                  speed, hw_led_mode);
3252         /* In case */
3253         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3254                 if (params->phy[phy_idx].set_link_led) {
3255                         params->phy[phy_idx].set_link_led(
3256                                 &params->phy[phy_idx], params, mode);
3257                 }
3258         }
3259
3260         switch (mode) {
3261         case LED_MODE_FRONT_PANEL_OFF:
3262         case LED_MODE_OFF:
3263                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3264                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3265                        SHARED_HW_CFG_LED_MAC1);
3266
3267                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3268                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3269                 break;
3270
3271         case LED_MODE_OPER:
3272                 /*
3273                  * For all other phys, OPER mode is same as ON, so in case
3274                  * link is down, do nothing
3275                  */
3276                 if (!vars->link_up)
3277                         break;
3278         case LED_MODE_ON:
3279                 if (((params->phy[EXT_PHY1].type ==
3280                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3281                          (params->phy[EXT_PHY1].type ==
3282                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
3283                     CHIP_IS_E2(bp) && params->num_phys == 2) {
3284                         /*
3285                          * This is a work-around for E2+8727 Configurations
3286                          */
3287                         if (mode == LED_MODE_ON ||
3288                                 speed == SPEED_10000){
3289                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3290                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3291
3292                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3293                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3294                                         (tmp | EMAC_LED_OVERRIDE));
3295                                 return rc;
3296                         }
3297                 } else if (SINGLE_MEDIA_DIRECT(params)) {
3298                         /*
3299                          * This is a work-around for HW issue found when link
3300                          * is up in CL73
3301                          */
3302                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3303                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3304                 } else {
3305                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3306                 }
3307
3308                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3309                 /* Set blinking rate to ~15.9Hz */
3310                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3311                        LED_BLINK_RATE_VAL);
3312                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3313                        port*4, 1);
3314                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3315                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3316
3317                 if (CHIP_IS_E1(bp) &&
3318                     ((speed == SPEED_2500) ||
3319                      (speed == SPEED_1000) ||
3320                      (speed == SPEED_100) ||
3321                      (speed == SPEED_10))) {
3322                         /*
3323                          * On Everest 1 Ax chip versions for speeds less than
3324                          * 10G LED scheme is different
3325                          */
3326                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3327                                + port*4, 1);
3328                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3329                                port*4, 0);
3330                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3331                                port*4, 1);
3332                 }
3333                 break;
3334
3335         default:
3336                 rc = -EINVAL;
3337                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3338                          mode);
3339                 break;
3340         }
3341         return rc;
3342
3343 }
3344
3345 /*
3346  * This function comes to reflect the actual link state read DIRECTLY from the
3347  * HW
3348  */
3349 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3350                     u8 is_serdes)
3351 {
3352         struct bnx2x *bp = params->bp;
3353         u16 gp_status = 0, phy_index = 0;
3354         u8 ext_phy_link_up = 0, serdes_phy_type;
3355         struct link_vars temp_vars;
3356
3357         CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3358                           MDIO_REG_BANK_GP_STATUS,
3359                           MDIO_GP_STATUS_TOP_AN_STATUS1,
3360                           &gp_status);
3361         /* link is up only if both local phy and external phy are up */
3362         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3363                 return -ESRCH;
3364
3365         switch (params->num_phys) {
3366         case 1:
3367                 /* No external PHY */
3368                 return 0;
3369         case 2:
3370                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3371                         &params->phy[EXT_PHY1],
3372                         params, &temp_vars);
3373                 break;
3374         case 3: /* Dual Media */
3375                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3376                       phy_index++) {
3377                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3378                                             ETH_PHY_SFP_FIBER) ||
3379                                            (params->phy[phy_index].media_type ==
3380                                             ETH_PHY_XFP_FIBER) ||
3381                                            (params->phy[phy_index].media_type ==
3382                                             ETH_PHY_DA_TWINAX));
3383
3384                         if (is_serdes != serdes_phy_type)
3385                                 continue;
3386                         if (params->phy[phy_index].read_status) {
3387                                 ext_phy_link_up |=
3388                                         params->phy[phy_index].read_status(
3389                                                 &params->phy[phy_index],
3390                                                 params, &temp_vars);
3391                         }
3392                 }
3393                 break;
3394         }
3395         if (ext_phy_link_up)
3396                 return 0;
3397         return -ESRCH;
3398 }
3399
3400 static int bnx2x_link_initialize(struct link_params *params,
3401                                  struct link_vars *vars)
3402 {
3403         int rc = 0;
3404         u8 phy_index, non_ext_phy;
3405         struct bnx2x *bp = params->bp;
3406         /*
3407          * In case of external phy existence, the line speed would be the
3408          * line speed linked up by the external phy. In case it is direct
3409          * only, then the line_speed during initialization will be
3410          * equal to the req_line_speed
3411          */
3412         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3413
3414         /*
3415          * Initialize the internal phy in case this is a direct board
3416          * (no external phys), or this board has external phy which requires
3417          * to first.
3418          */
3419
3420         if (params->phy[INT_PHY].config_init)
3421                 params->phy[INT_PHY].config_init(
3422                         &params->phy[INT_PHY],
3423                         params, vars);
3424
3425         /* init ext phy and enable link state int */
3426         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3427                        (params->loopback_mode == LOOPBACK_XGXS));
3428
3429         if (non_ext_phy ||
3430             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3431             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3432                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3433                 if (vars->line_speed == SPEED_AUTO_NEG)
3434                         bnx2x_set_parallel_detection(phy, params);
3435                 bnx2x_init_internal_phy(phy, params, vars);
3436         }
3437
3438         /* Init external phy*/
3439         if (!non_ext_phy)
3440                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3441                       phy_index++) {
3442                         /*
3443                          * No need to initialize second phy in case of first
3444                          * phy only selection. In case of second phy, we do
3445                          * need to initialize the first phy, since they are
3446                          * connected.
3447                          */
3448                         if (phy_index == EXT_PHY2 &&
3449                             (bnx2x_phy_selection(params) ==
3450                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3451                                 DP(NETIF_MSG_LINK, "Not initializing"
3452                                                 " second phy\n");
3453                                 continue;
3454                         }
3455                         params->phy[phy_index].config_init(
3456                                 &params->phy[phy_index],
3457                                 params, vars);
3458                 }
3459
3460         /* Reset the interrupt indication after phy was initialized */
3461         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3462                        params->port*4,
3463                        (NIG_STATUS_XGXS0_LINK10G |
3464                         NIG_STATUS_XGXS0_LINK_STATUS |
3465                         NIG_STATUS_SERDES0_LINK_STATUS |
3466                         NIG_MASK_MI_INT));
3467         return rc;
3468 }
3469
3470 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3471                                  struct link_params *params)
3472 {
3473         /* reset the SerDes/XGXS */
3474         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3475                (0x1ff << (params->port*16)));
3476 }
3477
3478 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3479                                         struct link_params *params)
3480 {
3481         struct bnx2x *bp = params->bp;
3482         u8 gpio_port;
3483         /* HW reset */
3484         if (CHIP_IS_E2(bp))
3485                 gpio_port = BP_PATH(bp);
3486         else
3487                 gpio_port = params->port;
3488         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3489                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3490                        gpio_port);
3491         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3492                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
3493                        gpio_port);
3494         DP(NETIF_MSG_LINK, "reset external PHY\n");
3495 }
3496
3497 static int bnx2x_update_link_down(struct link_params *params,
3498                                   struct link_vars *vars)
3499 {
3500         struct bnx2x *bp = params->bp;
3501         u8 port = params->port;
3502
3503         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3504         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3505
3506         /* indicate no mac active */
3507         vars->mac_type = MAC_TYPE_NONE;
3508
3509         /* update shared memory */
3510         vars->link_status = 0;
3511         vars->line_speed = 0;
3512         bnx2x_update_mng(params, vars->link_status);
3513
3514         /* activate nig drain */
3515         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3516
3517         /* disable emac */
3518         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3519
3520         msleep(10);
3521
3522         /* reset BigMac */
3523         bnx2x_bmac_rx_disable(bp, params->port);
3524         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3525                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3526         return 0;
3527 }
3528
3529 static int bnx2x_update_link_up(struct link_params *params,
3530                                 struct link_vars *vars,
3531                                 u8 link_10g)
3532 {
3533         struct bnx2x *bp = params->bp;
3534         u8 port = params->port;
3535         int rc = 0;
3536
3537         vars->link_status |= LINK_STATUS_LINK_UP;
3538
3539         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3540                 vars->link_status |=
3541                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3542
3543         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3544                 vars->link_status |=
3545                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3546
3547         if (link_10g) {
3548                 bnx2x_bmac_enable(params, vars, 0);
3549                 bnx2x_set_led(params, vars,
3550                               LED_MODE_OPER, SPEED_10000);
3551         } else {
3552                 rc = bnx2x_emac_program(params, vars);
3553
3554                 bnx2x_emac_enable(params, vars, 0);
3555
3556                 /* AN complete? */
3557                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3558                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3559                     SINGLE_MEDIA_DIRECT(params))
3560                         bnx2x_set_gmii_tx_driver(params);
3561         }
3562
3563         /* PBF - link up */
3564         if (!(CHIP_IS_E2(bp)))
3565                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3566                                        vars->line_speed);
3567
3568         /* disable drain */
3569         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3570
3571         /* update shared memory */
3572         bnx2x_update_mng(params, vars->link_status);
3573         msleep(20);
3574         return rc;
3575 }
3576 /*
3577  * The bnx2x_link_update function should be called upon link
3578  * interrupt.
3579  * Link is considered up as follows:
3580  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3581  *   to be up
3582  * - SINGLE_MEDIA - The link between the 577xx and the external
3583  *   phy (XGXS) need to up as well as the external link of the
3584  *   phy (PHY_EXT1)
3585  * - DUAL_MEDIA - The link between the 577xx and the first
3586  *   external phy needs to be up, and at least one of the 2
3587  *   external phy link must be up.
3588  */
3589 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3590 {
3591         struct bnx2x *bp = params->bp;
3592         struct link_vars phy_vars[MAX_PHYS];
3593         u8 port = params->port;
3594         u8 link_10g, phy_index;
3595         u8 ext_phy_link_up = 0, cur_link_up;
3596         int rc = 0;
3597         u8 is_mi_int = 0;
3598         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3599         u8 active_external_phy = INT_PHY;
3600         vars->link_status = 0;
3601         for (phy_index = INT_PHY; phy_index < params->num_phys;
3602               phy_index++) {
3603                 phy_vars[phy_index].flow_ctrl = 0;
3604                 phy_vars[phy_index].link_status = 0;
3605                 phy_vars[phy_index].line_speed = 0;
3606                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3607                 phy_vars[phy_index].phy_link_up = 0;
3608                 phy_vars[phy_index].link_up = 0;
3609                 phy_vars[phy_index].fault_detected = 0;
3610         }
3611
3612         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3613                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3614                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3615
3616         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3617                                 port*0x18) > 0);
3618         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3619                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3620                  is_mi_int,
3621                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3622
3623         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3624           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3625           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3626
3627         /* disable emac */
3628         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3629
3630         /*
3631          * Step 1:
3632          * Check external link change only for external phys, and apply
3633          * priority selection between them in case the link on both phys
3634          * is up. Note that instead of the common vars, a temporary
3635          * vars argument is used since each phy may have different link/
3636          * speed/duplex result
3637          */
3638         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3639               phy_index++) {
3640                 struct bnx2x_phy *phy = &params->phy[phy_index];
3641                 if (!phy->read_status)
3642                         continue;
3643                 /* Read link status and params of this ext phy */
3644                 cur_link_up = phy->read_status(phy, params,
3645                                                &phy_vars[phy_index]);
3646                 if (cur_link_up) {
3647                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3648                                    phy_index);
3649                 } else {
3650                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3651                                    phy_index);
3652                         continue;
3653                 }
3654
3655                 if (!ext_phy_link_up) {
3656                         ext_phy_link_up = 1;
3657                         active_external_phy = phy_index;
3658                 } else {
3659                         switch (bnx2x_phy_selection(params)) {
3660                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3661                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3662                         /*
3663                          * In this option, the first PHY makes sure to pass the
3664                          * traffic through itself only.
3665                          * Its not clear how to reset the link on the second phy
3666                          */
3667                                 active_external_phy = EXT_PHY1;
3668                                 break;
3669                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3670                         /*
3671                          * In this option, the first PHY makes sure to pass the
3672                          * traffic through the second PHY.
3673                          */
3674                                 active_external_phy = EXT_PHY2;
3675                                 break;
3676                         default:
3677                         /*
3678                          * Link indication on both PHYs with the following cases
3679                          * is invalid:
3680                          * - FIRST_PHY means that second phy wasn't initialized,
3681                          * hence its link is expected to be down
3682                          * - SECOND_PHY means that first phy should not be able
3683                          * to link up by itself (using configuration)
3684                          * - DEFAULT should be overriden during initialiazation
3685                          */
3686                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3687                                            "mpc=0x%x. DISABLING LINK !!!\n",
3688                                            params->multi_phy_config);
3689                                 ext_phy_link_up = 0;
3690                                 break;
3691                         }
3692                 }
3693         }
3694         prev_line_speed = vars->line_speed;
3695         /*
3696          * Step 2:
3697          * Read the status of the internal phy. In case of
3698          * DIRECT_SINGLE_MEDIA board, this link is the external link,
3699          * otherwise this is the link between the 577xx and the first
3700          * external phy
3701          */
3702         if (params->phy[INT_PHY].read_status)
3703                 params->phy[INT_PHY].read_status(
3704                         &params->phy[INT_PHY],
3705                         params, vars);
3706         /*
3707          * The INT_PHY flow control reside in the vars. This include the
3708          * case where the speed or flow control are not set to AUTO.
3709          * Otherwise, the active external phy flow control result is set
3710          * to the vars. The ext_phy_line_speed is needed to check if the
3711          * speed is different between the internal phy and external phy.
3712          * This case may be result of intermediate link speed change.
3713          */
3714         if (active_external_phy > INT_PHY) {
3715                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3716                 /*
3717                  * Link speed is taken from the XGXS. AN and FC result from
3718                  * the external phy.
3719                  */
3720                 vars->link_status |= phy_vars[active_external_phy].link_status;
3721
3722                 /*
3723                  * if active_external_phy is first PHY and link is up - disable
3724                  * disable TX on second external PHY
3725                  */
3726                 if (active_external_phy == EXT_PHY1) {
3727                         if (params->phy[EXT_PHY2].phy_specific_func) {
3728                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3729                                                    " EXT_PHY2\n");
3730                                 params->phy[EXT_PHY2].phy_specific_func(
3731                                         &params->phy[EXT_PHY2],
3732                                         params, DISABLE_TX);
3733                         }
3734                 }
3735
3736                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3737                 vars->duplex = phy_vars[active_external_phy].duplex;
3738                 if (params->phy[active_external_phy].supported &
3739                     SUPPORTED_FIBRE)
3740                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3741                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3742                            active_external_phy);
3743         }
3744
3745         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3746               phy_index++) {
3747                 if (params->phy[phy_index].flags &
3748                     FLAGS_REARM_LATCH_SIGNAL) {
3749                         bnx2x_rearm_latch_signal(bp, port,
3750                                                  phy_index ==
3751                                                  active_external_phy);
3752                         break;
3753                 }
3754         }
3755         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3756                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3757                    vars->link_status, ext_phy_line_speed);
3758         /*
3759          * Upon link speed change set the NIG into drain mode. Comes to
3760          * deals with possible FIFO glitch due to clk change when speed
3761          * is decreased without link down indicator
3762          */
3763
3764         if (vars->phy_link_up) {
3765                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3766                     (ext_phy_line_speed != vars->line_speed)) {
3767                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3768                                    " different than the external"
3769                                    " link speed %d\n", vars->line_speed,
3770                                    ext_phy_line_speed);
3771                         vars->phy_link_up = 0;
3772                 } else if (prev_line_speed != vars->line_speed) {
3773                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3774                                0);
3775                         msleep(1);
3776                 }
3777         }
3778
3779         /* anything 10 and over uses the bmac */
3780         link_10g = ((vars->line_speed == SPEED_10000) ||
3781                     (vars->line_speed == SPEED_12000) ||
3782                     (vars->line_speed == SPEED_12500) ||
3783                     (vars->line_speed == SPEED_13000) ||
3784                     (vars->line_speed == SPEED_15000) ||
3785                     (vars->line_speed == SPEED_16000));
3786
3787         bnx2x_link_int_ack(params, vars, link_10g);
3788
3789         /*
3790          * In case external phy link is up, and internal link is down
3791          * (not initialized yet probably after link initialization, it
3792          * needs to be initialized.
3793          * Note that after link down-up as result of cable plug, the xgxs
3794          * link would probably become up again without the need
3795          * initialize it
3796          */
3797         if (!(SINGLE_MEDIA_DIRECT(params))) {
3798                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3799                            " init_preceding = %d\n", ext_phy_link_up,
3800                            vars->phy_link_up,
3801                            params->phy[EXT_PHY1].flags &
3802                            FLAGS_INIT_XGXS_FIRST);
3803                 if (!(params->phy[EXT_PHY1].flags &
3804                       FLAGS_INIT_XGXS_FIRST)
3805                     && ext_phy_link_up && !vars->phy_link_up) {
3806                         vars->line_speed = ext_phy_line_speed;
3807                         if (vars->line_speed < SPEED_1000)
3808                                 vars->phy_flags |= PHY_SGMII_FLAG;
3809                         else
3810                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3811                         bnx2x_init_internal_phy(&params->phy[INT_PHY],
3812                                                 params,
3813                                                 vars);
3814                 }
3815         }
3816         /*
3817          * Link is up only if both local phy and external phy (in case of
3818          * non-direct board) are up and no fault detected on active PHY.
3819          */
3820         vars->link_up = (vars->phy_link_up &&
3821                          (ext_phy_link_up ||
3822                           SINGLE_MEDIA_DIRECT(params)) &&
3823                          (phy_vars[active_external_phy].fault_detected == 0));
3824
3825         if (vars->link_up)
3826                 rc = bnx2x_update_link_up(params, vars, link_10g);
3827         else
3828                 rc = bnx2x_update_link_down(params, vars);
3829
3830         return rc;
3831 }
3832
3833
3834 /*****************************************************************************/
3835 /*                          External Phy section                             */
3836 /*****************************************************************************/
3837 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3838 {
3839         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3840                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3841         msleep(1);
3842         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3843                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3844 }
3845
3846 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3847                                       u32 spirom_ver, u32 ver_addr)
3848 {
3849         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3850                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3851
3852         if (ver_addr)
3853                 REG_WR(bp, ver_addr, spirom_ver);
3854 }
3855
3856 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3857                                       struct bnx2x_phy *phy,
3858                                       u8 port)
3859 {
3860         u16 fw_ver1, fw_ver2;
3861
3862         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3863                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3864         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3865                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3866         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3867                                   phy->ver_addr);
3868 }
3869
3870 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3871                                        struct bnx2x_phy *phy,
3872                                        struct link_vars *vars)
3873 {
3874         u16 val;
3875         bnx2x_cl45_read(bp, phy,
3876                         MDIO_AN_DEVAD,
3877                         MDIO_AN_REG_STATUS, &val);
3878         bnx2x_cl45_read(bp, phy,
3879                         MDIO_AN_DEVAD,
3880                         MDIO_AN_REG_STATUS, &val);
3881         if (val & (1<<5))
3882                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3883         if ((val & (1<<0)) == 0)
3884                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3885 }
3886
3887 /******************************************************************/
3888 /*              common BCM8073/BCM8727 PHY SECTION                */
3889 /******************************************************************/
3890 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3891                                   struct link_params *params,
3892                                   struct link_vars *vars)
3893 {
3894         struct bnx2x *bp = params->bp;
3895         if (phy->req_line_speed == SPEED_10 ||
3896             phy->req_line_speed == SPEED_100) {
3897                 vars->flow_ctrl = phy->req_flow_ctrl;
3898                 return;
3899         }
3900
3901         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3902             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3903                 u16 pause_result;
3904                 u16 ld_pause;           /* local */
3905                 u16 lp_pause;           /* link partner */
3906                 bnx2x_cl45_read(bp, phy,
3907                                 MDIO_AN_DEVAD,
3908                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3909
3910                 bnx2x_cl45_read(bp, phy,
3911                                 MDIO_AN_DEVAD,
3912                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3913                 pause_result = (ld_pause &
3914                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3915                 pause_result |= (lp_pause &
3916                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3917
3918                 bnx2x_pause_resolve(vars, pause_result);
3919                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3920                            pause_result);
3921         }
3922 }
3923 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3924                                              struct bnx2x_phy *phy,
3925                                              u8 port)
3926 {
3927         u32 count = 0;
3928         u16 fw_ver1, fw_msgout;
3929         int rc = 0;
3930
3931         /* Boot port from external ROM  */
3932         /* EDC grst */
3933         bnx2x_cl45_write(bp, phy,
3934                          MDIO_PMA_DEVAD,
3935                          MDIO_PMA_REG_GEN_CTRL,
3936                          0x0001);
3937
3938         /* ucode reboot and rst */
3939         bnx2x_cl45_write(bp, phy,
3940                          MDIO_PMA_DEVAD,
3941                          MDIO_PMA_REG_GEN_CTRL,
3942                          0x008c);
3943
3944         bnx2x_cl45_write(bp, phy,
3945                          MDIO_PMA_DEVAD,
3946                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3947
3948         /* Reset internal microprocessor */
3949         bnx2x_cl45_write(bp, phy,
3950                          MDIO_PMA_DEVAD,
3951                          MDIO_PMA_REG_GEN_CTRL,
3952                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3953
3954         /* Release srst bit */
3955         bnx2x_cl45_write(bp, phy,
3956                          MDIO_PMA_DEVAD,
3957                          MDIO_PMA_REG_GEN_CTRL,
3958                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3959
3960         /* Delay 100ms per the PHY specifications */
3961         msleep(100);
3962
3963         /* 8073 sometimes taking longer to download */
3964         do {
3965                 count++;
3966                 if (count > 300) {
3967                         DP(NETIF_MSG_LINK,
3968                                  "bnx2x_8073_8727_external_rom_boot port %x:"
3969                                  "Download failed. fw version = 0x%x\n",
3970                                  port, fw_ver1);
3971                         rc = -EINVAL;
3972                         break;
3973                 }
3974
3975                 bnx2x_cl45_read(bp, phy,
3976                                 MDIO_PMA_DEVAD,
3977                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3978                 bnx2x_cl45_read(bp, phy,
3979                                 MDIO_PMA_DEVAD,
3980                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3981
3982                 msleep(1);
3983         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3984                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3985                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3986
3987         /* Clear ser_boot_ctl bit */
3988         bnx2x_cl45_write(bp, phy,
3989                          MDIO_PMA_DEVAD,
3990                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3991         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3992
3993         DP(NETIF_MSG_LINK,
3994                  "bnx2x_8073_8727_external_rom_boot port %x:"
3995                  "Download complete. fw version = 0x%x\n",
3996                  port, fw_ver1);
3997
3998         return rc;
3999 }
4000
4001 /******************************************************************/
4002 /*                      BCM8073 PHY SECTION                       */
4003 /******************************************************************/
4004 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
4005 {
4006         /* This is only required for 8073A1, version 102 only */
4007         u16 val;
4008
4009         /* Read 8073 HW revision*/
4010         bnx2x_cl45_read(bp, phy,
4011                         MDIO_PMA_DEVAD,
4012                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4013
4014         if (val != 1) {
4015                 /* No need to workaround in 8073 A1 */
4016                 return 0;
4017         }
4018
4019         bnx2x_cl45_read(bp, phy,
4020                         MDIO_PMA_DEVAD,
4021                         MDIO_PMA_REG_ROM_VER2, &val);
4022
4023         /* SNR should be applied only for version 0x102 */
4024         if (val != 0x102)
4025                 return 0;
4026
4027         return 1;
4028 }
4029
4030 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
4031 {
4032         u16 val, cnt, cnt1 ;
4033
4034         bnx2x_cl45_read(bp, phy,
4035                         MDIO_PMA_DEVAD,
4036                         MDIO_PMA_REG_8073_CHIP_REV, &val);
4037
4038         if (val > 0) {
4039                 /* No need to workaround in 8073 A1 */
4040                 return 0;
4041         }
4042         /* XAUI workaround in 8073 A0: */
4043
4044         /*
4045          * After loading the boot ROM and restarting Autoneg, poll
4046          * Dev1, Reg $C820:
4047          */
4048
4049         for (cnt = 0; cnt < 1000; cnt++) {
4050                 bnx2x_cl45_read(bp, phy,
4051                                 MDIO_PMA_DEVAD,
4052                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4053                                 &val);
4054                   /*
4055                    * If bit [14] = 0 or bit [13] = 0, continue on with
4056                    * system initialization (XAUI work-around not required, as
4057                    * these bits indicate 2.5G or 1G link up).
4058                    */
4059                 if (!(val & (1<<14)) || !(val & (1<<13))) {
4060                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4061                         return 0;
4062                 } else if (!(val & (1<<15))) {
4063                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
4064                         /*
4065                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
4066                          * MSB (bit15) goes to 1 (indicating that the XAUI
4067                          * workaround has completed), then continue on with
4068                          * system initialization.
4069                          */
4070                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4071                                 bnx2x_cl45_read(bp, phy,
4072                                         MDIO_PMA_DEVAD,
4073                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4074                                 if (val & (1<<15)) {
4075                                         DP(NETIF_MSG_LINK,
4076                                           "XAUI workaround has completed\n");
4077                                         return 0;
4078                                  }
4079                                  msleep(3);
4080                         }
4081                         break;
4082                 }
4083                 msleep(3);
4084         }
4085         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4086         return -EINVAL;
4087 }
4088
4089 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4090 {
4091         /* Force KR or KX */
4092         bnx2x_cl45_write(bp, phy,
4093                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4094         bnx2x_cl45_write(bp, phy,
4095                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4096         bnx2x_cl45_write(bp, phy,
4097                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4098         bnx2x_cl45_write(bp, phy,
4099                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4100 }
4101
4102 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4103                                       struct bnx2x_phy *phy,
4104                                       struct link_vars *vars)
4105 {
4106         u16 cl37_val;
4107         struct bnx2x *bp = params->bp;
4108         bnx2x_cl45_read(bp, phy,
4109                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4110
4111         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4112         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4113         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4114         if ((vars->ieee_fc &
4115             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4116             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4117                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4118         }
4119         if ((vars->ieee_fc &
4120             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4121             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4122                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4123         }
4124         if ((vars->ieee_fc &
4125             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4126             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4127                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4128         }
4129         DP(NETIF_MSG_LINK,
4130                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4131
4132         bnx2x_cl45_write(bp, phy,
4133                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4134         msleep(500);
4135 }
4136
4137 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
4138                                   struct link_params *params,
4139                                   struct link_vars *vars)
4140 {
4141         struct bnx2x *bp = params->bp;
4142         u16 val = 0, tmp1;
4143         u8 gpio_port;
4144         DP(NETIF_MSG_LINK, "Init 8073\n");
4145
4146         if (CHIP_IS_E2(bp))
4147                 gpio_port = BP_PATH(bp);
4148         else
4149                 gpio_port = params->port;
4150         /* Restore normal power mode*/
4151         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4152                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4153
4154         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4155                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4156
4157         /* enable LASI */
4158         bnx2x_cl45_write(bp, phy,
4159                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4160         bnx2x_cl45_write(bp, phy,
4161                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4162
4163         bnx2x_8073_set_pause_cl37(params, phy, vars);
4164
4165         bnx2x_cl45_read(bp, phy,
4166                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4167
4168         bnx2x_cl45_read(bp, phy,
4169                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4170
4171         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4172
4173         /* Swap polarity if required - Must be done only in non-1G mode */
4174         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4175                 /* Configure the 8073 to swap _P and _N of the KR lines */
4176                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4177                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4178                 bnx2x_cl45_read(bp, phy,
4179                                 MDIO_PMA_DEVAD,
4180                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4181                 bnx2x_cl45_write(bp, phy,
4182                                  MDIO_PMA_DEVAD,
4183                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4184                                  (val | (3<<9)));
4185         }
4186
4187
4188         /* Enable CL37 BAM */
4189         if (REG_RD(bp, params->shmem_base +
4190                          offsetof(struct shmem_region, dev_info.
4191                                   port_hw_config[params->port].default_cfg)) &
4192             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4193
4194                 bnx2x_cl45_read(bp, phy,
4195                                 MDIO_AN_DEVAD,
4196                                 MDIO_AN_REG_8073_BAM, &val);
4197                 bnx2x_cl45_write(bp, phy,
4198                                  MDIO_AN_DEVAD,
4199                                  MDIO_AN_REG_8073_BAM, val | 1);
4200                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4201         }
4202         if (params->loopback_mode == LOOPBACK_EXT) {
4203                 bnx2x_807x_force_10G(bp, phy);
4204                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4205                 return 0;
4206         } else {
4207                 bnx2x_cl45_write(bp, phy,
4208                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4209         }
4210         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4211                 if (phy->req_line_speed == SPEED_10000) {
4212                         val = (1<<7);
4213                 } else if (phy->req_line_speed ==  SPEED_2500) {
4214                         val = (1<<5);
4215                         /*
4216                          * Note that 2.5G works only when used with 1G
4217                          * advertisement
4218                          */
4219                 } else
4220                         val = (1<<5);
4221         } else {
4222                 val = 0;
4223                 if (phy->speed_cap_mask &
4224                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4225                         val |= (1<<7);
4226
4227                 /* Note that 2.5G works only when used with 1G advertisement */
4228                 if (phy->speed_cap_mask &
4229                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4230                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4231                         val |= (1<<5);
4232                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4233         }
4234
4235         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4236         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4237
4238         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4239              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4240             (phy->req_line_speed == SPEED_2500)) {
4241                 u16 phy_ver;
4242                 /* Allow 2.5G for A1 and above */
4243                 bnx2x_cl45_read(bp, phy,
4244                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4245                                 &phy_ver);
4246                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4247                 if (phy_ver > 0)
4248                         tmp1 |= 1;
4249                 else
4250                         tmp1 &= 0xfffe;
4251         } else {
4252                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4253                 tmp1 &= 0xfffe;
4254         }
4255
4256         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4257         /* Add support for CL37 (passive mode) II */
4258
4259         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4260         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4261                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4262                                   0x20 : 0x40)));
4263
4264         /* Add support for CL37 (passive mode) III */
4265         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4266
4267         /*
4268          * The SNR will improve about 2db by changing BW and FEE main
4269          * tap. Rest commands are executed after link is up
4270          * Change FFE main cursor to 5 in EDC register
4271          */
4272         if (bnx2x_8073_is_snr_needed(bp, phy))
4273                 bnx2x_cl45_write(bp, phy,
4274                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4275                                  0xFB0C);
4276
4277         /* Enable FEC (Forware Error Correction) Request in the AN */
4278         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4279         tmp1 |= (1<<15);
4280         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4281
4282         bnx2x_ext_phy_set_pause(params, phy, vars);
4283
4284         /* Restart autoneg */
4285         msleep(500);
4286         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4287         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4288                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4289         return 0;
4290 }
4291
4292 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4293                                  struct link_params *params,
4294                                  struct link_vars *vars)
4295 {
4296         struct bnx2x *bp = params->bp;
4297         u8 link_up = 0;
4298         u16 val1, val2;
4299         u16 link_status = 0;
4300         u16 an1000_status = 0;
4301
4302         bnx2x_cl45_read(bp, phy,
4303                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4304
4305         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4306
4307         /* clear the interrupt LASI status register */
4308         bnx2x_cl45_read(bp, phy,
4309                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4310         bnx2x_cl45_read(bp, phy,
4311                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4312         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4313         /* Clear MSG-OUT */
4314         bnx2x_cl45_read(bp, phy,
4315                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4316
4317         /* Check the LASI */
4318         bnx2x_cl45_read(bp, phy,
4319                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4320
4321         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4322
4323         /* Check the link status */
4324         bnx2x_cl45_read(bp, phy,
4325                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4326         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4327
4328         bnx2x_cl45_read(bp, phy,
4329                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4330         bnx2x_cl45_read(bp, phy,
4331                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4332         link_up = ((val1 & 4) == 4);
4333         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4334
4335         if (link_up &&
4336              ((phy->req_line_speed != SPEED_10000))) {
4337                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4338                         return 0;
4339         }
4340         bnx2x_cl45_read(bp, phy,
4341                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4342         bnx2x_cl45_read(bp, phy,
4343                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4344
4345         /* Check the link status on 1.1.2 */
4346         bnx2x_cl45_read(bp, phy,
4347                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4348         bnx2x_cl45_read(bp, phy,
4349                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4350         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4351                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4352
4353         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4354         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4355                 /*
4356                  * The SNR will improve about 2dbby changing the BW and FEE main
4357                  * tap. The 1st write to change FFE main tap is set before
4358                  * restart AN. Change PLL Bandwidth in EDC register
4359                  */
4360                 bnx2x_cl45_write(bp, phy,
4361                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4362                                  0x26BC);
4363
4364                 /* Change CDR Bandwidth in EDC register */
4365                 bnx2x_cl45_write(bp, phy,
4366                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4367                                  0x0333);
4368         }
4369         bnx2x_cl45_read(bp, phy,
4370                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4371                         &link_status);
4372
4373         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4374         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4375                 link_up = 1;
4376                 vars->line_speed = SPEED_10000;
4377                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4378                            params->port);
4379         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4380                 link_up = 1;
4381                 vars->line_speed = SPEED_2500;
4382                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4383                            params->port);
4384         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4385                 link_up = 1;
4386                 vars->line_speed = SPEED_1000;
4387                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4388                            params->port);
4389         } else {
4390                 link_up = 0;
4391                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4392                            params->port);
4393         }
4394
4395         if (link_up) {
4396                 /* Swap polarity if required */
4397                 if (params->lane_config &
4398                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4399                         /* Configure the 8073 to swap P and N of the KR lines */
4400                         bnx2x_cl45_read(bp, phy,
4401                                         MDIO_XS_DEVAD,
4402                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4403                         /*
4404                          * Set bit 3 to invert Rx in 1G mode and clear this bit
4405                          * when it`s in 10G mode.
4406                          */
4407                         if (vars->line_speed == SPEED_1000) {
4408                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4409                                               "the 8073\n");
4410                                 val1 |= (1<<3);
4411                         } else
4412                                 val1 &= ~(1<<3);
4413
4414                         bnx2x_cl45_write(bp, phy,
4415                                          MDIO_XS_DEVAD,
4416                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
4417                                          val1);
4418                 }
4419                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4420                 bnx2x_8073_resolve_fc(phy, params, vars);
4421                 vars->duplex = DUPLEX_FULL;
4422         }
4423         return link_up;
4424 }
4425
4426 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4427                                   struct link_params *params)
4428 {
4429         struct bnx2x *bp = params->bp;
4430         u8 gpio_port;
4431         if (CHIP_IS_E2(bp))
4432                 gpio_port = BP_PATH(bp);
4433         else
4434                 gpio_port = params->port;
4435         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4436            gpio_port);
4437         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4438                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
4439                        gpio_port);
4440 }
4441
4442 /******************************************************************/
4443 /*                      BCM8705 PHY SECTION                       */
4444 /******************************************************************/
4445 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
4446                                   struct link_params *params,
4447                                   struct link_vars *vars)
4448 {
4449         struct bnx2x *bp = params->bp;
4450         DP(NETIF_MSG_LINK, "init 8705\n");
4451         /* Restore normal power mode*/
4452         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4453                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4454         /* HW reset */
4455         bnx2x_ext_phy_hw_reset(bp, params->port);
4456         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4457         bnx2x_wait_reset_complete(bp, phy, params);
4458
4459         bnx2x_cl45_write(bp, phy,
4460                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4461         bnx2x_cl45_write(bp, phy,
4462                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4463         bnx2x_cl45_write(bp, phy,
4464                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4465         bnx2x_cl45_write(bp, phy,
4466                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4467         /* BCM8705 doesn't have microcode, hence the 0 */
4468         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4469         return 0;
4470 }
4471
4472 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4473                                  struct link_params *params,
4474                                  struct link_vars *vars)
4475 {
4476         u8 link_up = 0;
4477         u16 val1, rx_sd;
4478         struct bnx2x *bp = params->bp;
4479         DP(NETIF_MSG_LINK, "read status 8705\n");
4480         bnx2x_cl45_read(bp, phy,
4481                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4482         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4483
4484         bnx2x_cl45_read(bp, phy,
4485                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4486         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4487
4488         bnx2x_cl45_read(bp, phy,
4489                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4490
4491         bnx2x_cl45_read(bp, phy,
4492                       MDIO_PMA_DEVAD, 0xc809, &val1);
4493         bnx2x_cl45_read(bp, phy,
4494                       MDIO_PMA_DEVAD, 0xc809, &val1);
4495
4496         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4497         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4498         if (link_up) {
4499                 vars->line_speed = SPEED_10000;
4500                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4501         }
4502         return link_up;
4503 }
4504
4505 /******************************************************************/
4506 /*                      SFP+ module Section                       */
4507 /******************************************************************/
4508 static u8 bnx2x_get_gpio_port(struct link_params *params)
4509 {
4510         u8 gpio_port;
4511         u32 swap_val, swap_override;
4512         struct bnx2x *bp = params->bp;
4513         if (CHIP_IS_E2(bp))
4514                 gpio_port = BP_PATH(bp);
4515         else
4516                 gpio_port = params->port;
4517         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4518         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4519         return gpio_port ^ (swap_val && swap_override);
4520 }
4521 static void bnx2x_sfp_set_transmitter(struct link_params *params,
4522                                       struct bnx2x_phy *phy,
4523                                       u8 tx_en)
4524 {
4525         u16 val;
4526         u8 port = params->port;
4527         struct bnx2x *bp = params->bp;
4528         u32 tx_en_mode;
4529
4530         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4531         tx_en_mode = REG_RD(bp, params->shmem_base +
4532                             offsetof(struct shmem_region,
4533                                      dev_info.port_hw_config[port].sfp_ctrl)) &
4534                 PORT_HW_CFG_TX_LASER_MASK;
4535         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4536                            "mode = %x\n", tx_en, port, tx_en_mode);
4537         switch (tx_en_mode) {
4538         case PORT_HW_CFG_TX_LASER_MDIO:
4539
4540                 bnx2x_cl45_read(bp, phy,
4541                                 MDIO_PMA_DEVAD,
4542                                 MDIO_PMA_REG_PHY_IDENTIFIER,
4543                                 &val);
4544
4545                 if (tx_en)
4546                         val &= ~(1<<15);
4547                 else
4548                         val |= (1<<15);
4549
4550                 bnx2x_cl45_write(bp, phy,
4551                                  MDIO_PMA_DEVAD,
4552                                  MDIO_PMA_REG_PHY_IDENTIFIER,
4553                                  val);
4554         break;
4555         case PORT_HW_CFG_TX_LASER_GPIO0:
4556         case PORT_HW_CFG_TX_LASER_GPIO1:
4557         case PORT_HW_CFG_TX_LASER_GPIO2:
4558         case PORT_HW_CFG_TX_LASER_GPIO3:
4559         {
4560                 u16 gpio_pin;
4561                 u8 gpio_port, gpio_mode;
4562                 if (tx_en)
4563                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4564                 else
4565                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4566
4567                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4568                 gpio_port = bnx2x_get_gpio_port(params);
4569                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4570                 break;
4571         }
4572         default:
4573                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4574                 break;
4575         }
4576 }
4577
4578 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4579                                              struct link_params *params,
4580                                              u16 addr, u8 byte_cnt, u8 *o_buf)
4581 {
4582         struct bnx2x *bp = params->bp;
4583         u16 val = 0;
4584         u16 i;
4585         if (byte_cnt > 16) {
4586                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4587                             " is limited to 0xf\n");
4588                 return -EINVAL;
4589         }
4590         /* Set the read command byte count */
4591         bnx2x_cl45_write(bp, phy,
4592                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4593                          (byte_cnt | 0xa000));
4594
4595         /* Set the read command address */
4596         bnx2x_cl45_write(bp, phy,
4597                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4598                          addr);
4599
4600         /* Activate read command */
4601         bnx2x_cl45_write(bp, phy,
4602                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4603                          0x2c0f);
4604
4605         /* Wait up to 500us for command complete status */
4606         for (i = 0; i < 100; i++) {
4607                 bnx2x_cl45_read(bp, phy,
4608                                 MDIO_PMA_DEVAD,
4609                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4610                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4611                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4612                         break;
4613                 udelay(5);
4614         }
4615
4616         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4617                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4618                 DP(NETIF_MSG_LINK,
4619                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4620                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4621                 return -EINVAL;
4622         }
4623
4624         /* Read the buffer */
4625         for (i = 0; i < byte_cnt; i++) {
4626                 bnx2x_cl45_read(bp, phy,
4627                                 MDIO_PMA_DEVAD,
4628                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4629                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4630         }
4631
4632         for (i = 0; i < 100; i++) {
4633                 bnx2x_cl45_read(bp, phy,
4634                                 MDIO_PMA_DEVAD,
4635                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4636                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4637                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4638                         return 0;
4639                 msleep(1);
4640         }
4641         return -EINVAL;
4642 }
4643
4644 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4645                                              struct link_params *params,
4646                                              u16 addr, u8 byte_cnt, u8 *o_buf)
4647 {
4648         struct bnx2x *bp = params->bp;
4649         u16 val, i;
4650
4651         if (byte_cnt > 16) {
4652                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4653                             " is limited to 0xf\n");
4654                 return -EINVAL;
4655         }
4656
4657         /* Need to read from 1.8000 to clear it */
4658         bnx2x_cl45_read(bp, phy,
4659                         MDIO_PMA_DEVAD,
4660                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4661                         &val);
4662
4663         /* Set the read command byte count */
4664         bnx2x_cl45_write(bp, phy,
4665                          MDIO_PMA_DEVAD,
4666                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4667                          ((byte_cnt < 2) ? 2 : byte_cnt));
4668
4669         /* Set the read command address */
4670         bnx2x_cl45_write(bp, phy,
4671                          MDIO_PMA_DEVAD,
4672                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4673                          addr);
4674         /* Set the destination address */
4675         bnx2x_cl45_write(bp, phy,
4676                          MDIO_PMA_DEVAD,
4677                          0x8004,
4678                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4679
4680         /* Activate read command */
4681         bnx2x_cl45_write(bp, phy,
4682                          MDIO_PMA_DEVAD,
4683                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4684                          0x8002);
4685         /*
4686          * Wait appropriate time for two-wire command to finish before
4687          * polling the status register
4688          */
4689         msleep(1);
4690
4691         /* Wait up to 500us for command complete status */
4692         for (i = 0; i < 100; i++) {
4693                 bnx2x_cl45_read(bp, phy,
4694                                 MDIO_PMA_DEVAD,
4695                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4696                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4697                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4698                         break;
4699                 udelay(5);
4700         }
4701
4702         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4703                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4704                 DP(NETIF_MSG_LINK,
4705                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4706                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4707                 return -EFAULT;
4708         }
4709
4710         /* Read the buffer */
4711         for (i = 0; i < byte_cnt; i++) {
4712                 bnx2x_cl45_read(bp, phy,
4713                                 MDIO_PMA_DEVAD,
4714                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4715                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4716         }
4717
4718         for (i = 0; i < 100; i++) {
4719                 bnx2x_cl45_read(bp, phy,
4720                                 MDIO_PMA_DEVAD,
4721                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4722                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4723                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4724                         return 0;
4725                 msleep(1);
4726         }
4727
4728         return -EINVAL;
4729 }
4730
4731 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4732                                  struct link_params *params, u16 addr,
4733                                  u8 byte_cnt, u8 *o_buf)
4734 {
4735         int rc = -EINVAL;
4736         switch (phy->type) {
4737         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4738                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4739                                                        byte_cnt, o_buf);
4740         break;
4741         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4742         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4743                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4744                                                        byte_cnt, o_buf);
4745         break;
4746         }
4747         return rc;
4748 }
4749
4750 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4751                               struct link_params *params,
4752                               u16 *edc_mode)
4753 {
4754         struct bnx2x *bp = params->bp;
4755         u32 sync_offset = 0, phy_idx, media_types;
4756         u8 val, check_limiting_mode = 0;
4757         *edc_mode = EDC_MODE_LIMITING;
4758
4759         phy->media_type = ETH_PHY_UNSPECIFIED;
4760         /* First check for copper cable */
4761         if (bnx2x_read_sfp_module_eeprom(phy,
4762                                          params,
4763                                          SFP_EEPROM_CON_TYPE_ADDR,
4764                                          1,
4765                                          &val) != 0) {
4766                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4767                 return -EINVAL;
4768         }
4769
4770         switch (val) {
4771         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4772         {
4773                 u8 copper_module_type;
4774                 phy->media_type = ETH_PHY_DA_TWINAX;
4775                 /*
4776                  * Check if its active cable (includes SFP+ module)
4777                  * of passive cable
4778                  */
4779                 if (bnx2x_read_sfp_module_eeprom(phy,
4780                                                params,
4781                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4782                                                1,
4783                                                &copper_module_type) != 0) {
4784                         DP(NETIF_MSG_LINK,
4785                                 "Failed to read copper-cable-type"
4786                                 " from SFP+ EEPROM\n");
4787                         return -EINVAL;
4788                 }
4789
4790                 if (copper_module_type &
4791                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4792                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4793                         check_limiting_mode = 1;
4794                 } else if (copper_module_type &
4795                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4796                                 DP(NETIF_MSG_LINK, "Passive Copper"
4797                                             " cable detected\n");
4798                                 *edc_mode =
4799                                       EDC_MODE_PASSIVE_DAC;
4800                 } else {
4801                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4802                                      "type 0x%x !!!\n", copper_module_type);
4803                         return -EINVAL;
4804                 }
4805                 break;
4806         }
4807         case SFP_EEPROM_CON_TYPE_VAL_LC:
4808                 phy->media_type = ETH_PHY_SFP_FIBER;
4809                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4810                 check_limiting_mode = 1;
4811                 break;
4812         default:
4813                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4814                          val);
4815                 return -EINVAL;
4816         }
4817         sync_offset = params->shmem_base +
4818                 offsetof(struct shmem_region,
4819                          dev_info.port_hw_config[params->port].media_type);
4820         media_types = REG_RD(bp, sync_offset);
4821         /* Update media type for non-PMF sync */
4822         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
4823                 if (&(params->phy[phy_idx]) == phy) {
4824                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
4825                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4826                         media_types |= ((phy->media_type &
4827                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
4828                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4829                         break;
4830                 }
4831         }
4832         REG_WR(bp, sync_offset, media_types);
4833         if (check_limiting_mode) {
4834                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4835                 if (bnx2x_read_sfp_module_eeprom(phy,
4836                                                  params,
4837                                                  SFP_EEPROM_OPTIONS_ADDR,
4838                                                  SFP_EEPROM_OPTIONS_SIZE,
4839                                                  options) != 0) {
4840                         DP(NETIF_MSG_LINK, "Failed to read Option"
4841                                 " field from module EEPROM\n");
4842                         return -EINVAL;
4843                 }
4844                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4845                         *edc_mode = EDC_MODE_LINEAR;
4846                 else
4847                         *edc_mode = EDC_MODE_LIMITING;
4848         }
4849         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4850         return 0;
4851 }
4852 /*
4853  * This function read the relevant field from the module (SFP+), and verify it
4854  * is compliant with this board
4855  */
4856 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4857                                    struct link_params *params)
4858 {
4859         struct bnx2x *bp = params->bp;
4860         u32 val, cmd;
4861         u32 fw_resp, fw_cmd_param;
4862         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4863         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4864         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4865         val = REG_RD(bp, params->shmem_base +
4866                          offsetof(struct shmem_region, dev_info.
4867                                   port_feature_config[params->port].config));
4868         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4869             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4870                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4871                 return 0;
4872         }
4873
4874         if (params->feature_config_flags &
4875             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4876                 /* Use specific phy request */
4877                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4878         } else if (params->feature_config_flags &
4879                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4880                 /* Use first phy request only in case of non-dual media*/
4881                 if (DUAL_MEDIA(params)) {
4882                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4883                            "verification\n");
4884                         return -EINVAL;
4885                 }
4886                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4887         } else {
4888                 /* No support in OPT MDL detection */
4889                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4890                           "verification\n");
4891                 return -EINVAL;
4892         }
4893
4894         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4895         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4896         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4897                 DP(NETIF_MSG_LINK, "Approved module\n");
4898                 return 0;
4899         }
4900
4901         /* format the warning message */
4902         if (bnx2x_read_sfp_module_eeprom(phy,
4903                                          params,
4904                                          SFP_EEPROM_VENDOR_NAME_ADDR,
4905                                          SFP_EEPROM_VENDOR_NAME_SIZE,
4906                                          (u8 *)vendor_name))
4907                 vendor_name[0] = '\0';
4908         else
4909                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4910         if (bnx2x_read_sfp_module_eeprom(phy,
4911                                          params,
4912                                          SFP_EEPROM_PART_NO_ADDR,
4913                                          SFP_EEPROM_PART_NO_SIZE,
4914                                          (u8 *)vendor_pn))
4915                 vendor_pn[0] = '\0';
4916         else
4917                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4918
4919         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
4920                               " Port %d from %s part number %s\n",
4921                          params->port, vendor_name, vendor_pn);
4922         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4923         return -EINVAL;
4924 }
4925
4926 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4927                                                  struct link_params *params)
4928
4929 {
4930         u8 val;
4931         struct bnx2x *bp = params->bp;
4932         u16 timeout;
4933         /*
4934          * Initialization time after hot-plug may take up to 300ms for
4935          * some phys type ( e.g. JDSU )
4936          */
4937
4938         for (timeout = 0; timeout < 60; timeout++) {
4939                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4940                     == 0) {
4941                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4942                                      "took %d ms\n", timeout * 5);
4943                         return 0;
4944                 }
4945                 msleep(5);
4946         }
4947         return -EINVAL;
4948 }
4949
4950 static void bnx2x_8727_power_module(struct bnx2x *bp,
4951                                     struct bnx2x_phy *phy,
4952                                     u8 is_power_up) {
4953         /* Make sure GPIOs are not using for LED mode */
4954         u16 val;
4955         /*
4956          * In the GPIO register, bit 4 is use to determine if the GPIOs are
4957          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4958          * output
4959          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4960          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4961          * where the 1st bit is the over-current(only input), and 2nd bit is
4962          * for power( only output )
4963          *
4964          * In case of NOC feature is disabled and power is up, set GPIO control
4965          *  as input to enable listening of over-current indication
4966          */
4967         if (phy->flags & FLAGS_NOC)
4968                 return;
4969         if (is_power_up)
4970                 val = (1<<4);
4971         else
4972                 /*
4973                  * Set GPIO control to OUTPUT, and set the power bit
4974                  * to according to the is_power_up
4975                  */
4976                 val = (1<<1);
4977
4978         bnx2x_cl45_write(bp, phy,
4979                          MDIO_PMA_DEVAD,
4980                          MDIO_PMA_REG_8727_GPIO_CTRL,
4981                          val);
4982 }
4983
4984 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4985                                         struct bnx2x_phy *phy,
4986                                         u16 edc_mode)
4987 {
4988         u16 cur_limiting_mode;
4989
4990         bnx2x_cl45_read(bp, phy,
4991                         MDIO_PMA_DEVAD,
4992                         MDIO_PMA_REG_ROM_VER2,
4993                         &cur_limiting_mode);
4994         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4995                  cur_limiting_mode);
4996
4997         if (edc_mode == EDC_MODE_LIMITING) {
4998                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
4999                 bnx2x_cl45_write(bp, phy,
5000                                  MDIO_PMA_DEVAD,
5001                                  MDIO_PMA_REG_ROM_VER2,
5002                                  EDC_MODE_LIMITING);
5003         } else { /* LRM mode ( default )*/
5004
5005                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
5006
5007                 /*
5008                  * Changing to LRM mode takes quite few seconds. So do it only
5009                  * if current mode is limiting (default is LRM)
5010                  */
5011                 if (cur_limiting_mode != EDC_MODE_LIMITING)
5012                         return 0;
5013
5014                 bnx2x_cl45_write(bp, phy,
5015                                  MDIO_PMA_DEVAD,
5016                                  MDIO_PMA_REG_LRM_MODE,
5017                                  0);
5018                 bnx2x_cl45_write(bp, phy,
5019                                  MDIO_PMA_DEVAD,
5020                                  MDIO_PMA_REG_ROM_VER2,
5021                                  0x128);
5022                 bnx2x_cl45_write(bp, phy,
5023                                  MDIO_PMA_DEVAD,
5024                                  MDIO_PMA_REG_MISC_CTRL0,
5025                                  0x4008);
5026                 bnx2x_cl45_write(bp, phy,
5027                                  MDIO_PMA_DEVAD,
5028                                  MDIO_PMA_REG_LRM_MODE,
5029                                  0xaaaa);
5030         }
5031         return 0;
5032 }
5033
5034 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
5035                                         struct bnx2x_phy *phy,
5036                                         u16 edc_mode)
5037 {
5038         u16 phy_identifier;
5039         u16 rom_ver2_val;
5040         bnx2x_cl45_read(bp, phy,
5041                         MDIO_PMA_DEVAD,
5042                         MDIO_PMA_REG_PHY_IDENTIFIER,
5043                         &phy_identifier);
5044
5045         bnx2x_cl45_write(bp, phy,
5046                          MDIO_PMA_DEVAD,
5047                          MDIO_PMA_REG_PHY_IDENTIFIER,
5048                          (phy_identifier & ~(1<<9)));
5049
5050         bnx2x_cl45_read(bp, phy,
5051                         MDIO_PMA_DEVAD,
5052                         MDIO_PMA_REG_ROM_VER2,
5053                         &rom_ver2_val);
5054         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
5055         bnx2x_cl45_write(bp, phy,
5056                          MDIO_PMA_DEVAD,
5057                          MDIO_PMA_REG_ROM_VER2,
5058                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
5059
5060         bnx2x_cl45_write(bp, phy,
5061                          MDIO_PMA_DEVAD,
5062                          MDIO_PMA_REG_PHY_IDENTIFIER,
5063                          (phy_identifier | (1<<9)));
5064
5065         return 0;
5066 }
5067
5068 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
5069                                      struct link_params *params,
5070                                      u32 action)
5071 {
5072         struct bnx2x *bp = params->bp;
5073
5074         switch (action) {
5075         case DISABLE_TX:
5076                 bnx2x_sfp_set_transmitter(params, phy, 0);
5077                 break;
5078         case ENABLE_TX:
5079                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
5080                         bnx2x_sfp_set_transmitter(params, phy, 1);
5081                 break;
5082         default:
5083                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5084                    action);
5085                 return;
5086         }
5087 }
5088
5089 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5090                                            u8 gpio_mode)
5091 {
5092         struct bnx2x *bp = params->bp;
5093
5094         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5095                             offsetof(struct shmem_region,
5096                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
5097                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5098         switch (fault_led_gpio) {
5099         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5100                 return;
5101         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5102         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5103         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5104         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5105         {
5106                 u8 gpio_port = bnx2x_get_gpio_port(params);
5107                 u16 gpio_pin = fault_led_gpio -
5108                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5109                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5110                                    "pin %x port %x mode %x\n",
5111                                gpio_pin, gpio_port, gpio_mode);
5112                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5113         }
5114         break;
5115         default:
5116                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5117                                fault_led_gpio);
5118         }
5119 }
5120
5121 static void bnx2x_power_sfp_module(struct link_params *params,
5122                                    struct bnx2x_phy *phy,
5123                                    u8 power)
5124 {
5125         struct bnx2x *bp = params->bp;
5126         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5127
5128         switch (phy->type) {
5129         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5130         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5131                 bnx2x_8727_power_module(params->bp, phy, power);
5132                 break;
5133         default:
5134                 break;
5135         }
5136 }
5137
5138 static void bnx2x_set_limiting_mode(struct link_params *params,
5139                                     struct bnx2x_phy *phy,
5140                                     u16 edc_mode)
5141 {
5142         switch (phy->type) {
5143         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5144                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5145                 break;
5146         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5147         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5148                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5149                 break;
5150         }
5151 }
5152
5153 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5154                                struct link_params *params)
5155 {
5156         struct bnx2x *bp = params->bp;
5157         u16 edc_mode;
5158         int rc = 0;
5159
5160         u32 val = REG_RD(bp, params->shmem_base +
5161                              offsetof(struct shmem_region, dev_info.
5162                                      port_feature_config[params->port].config));
5163
5164         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5165                  params->port);
5166         /* Power up module */
5167         bnx2x_power_sfp_module(params, phy, 1);
5168         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5169                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5170                 return -EINVAL;
5171         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5172                 /* check SFP+ module compatibility */
5173                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5174                 rc = -EINVAL;
5175                 /* Turn on fault module-detected led */
5176                 bnx2x_set_sfp_module_fault_led(params,
5177                                                MISC_REGISTERS_GPIO_HIGH);
5178
5179                 /* Check if need to power down the SFP+ module */
5180                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5181                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
5182                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5183                         bnx2x_power_sfp_module(params, phy, 0);
5184                         return rc;
5185                 }
5186         } else {
5187                 /* Turn off fault module-detected led */
5188                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5189         }
5190
5191         /*
5192          * Check and set limiting mode / LRM mode on 8726. On 8727 it
5193          * is done automatically
5194          */
5195         bnx2x_set_limiting_mode(params, phy, edc_mode);
5196
5197         /*
5198          * Enable transmit for this module if the module is approved, or
5199          * if unapproved modules should also enable the Tx laser
5200          */
5201         if (rc == 0 ||
5202             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5203             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5204                 bnx2x_sfp_set_transmitter(params, phy, 1);
5205         else
5206                 bnx2x_sfp_set_transmitter(params, phy, 0);
5207
5208         return rc;
5209 }
5210
5211 void bnx2x_handle_module_detect_int(struct link_params *params)
5212 {
5213         struct bnx2x *bp = params->bp;
5214         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5215         u32 gpio_val;
5216         u8 port = params->port;
5217
5218         /* Set valid module led off */
5219         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5220
5221         /* Get current gpio val reflecting module plugged in / out*/
5222         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5223
5224         /* Call the handling function in case module is detected */
5225         if (gpio_val == 0) {
5226                 bnx2x_power_sfp_module(params, phy, 1);
5227                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5228                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5229                                    port);
5230
5231                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5232                         bnx2x_sfp_module_detection(phy, params);
5233                 else
5234                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5235         } else {
5236                 u32 val = REG_RD(bp, params->shmem_base +
5237                                  offsetof(struct shmem_region, dev_info.
5238                                           port_feature_config[params->port].
5239                                           config));
5240
5241                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5242                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5243                                    port);
5244                 /*
5245                  * Module was plugged out.
5246                  * Disable transmit for this module
5247                  */
5248                 phy->media_type = ETH_PHY_NOT_PRESENT;
5249                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5250                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5251                         bnx2x_sfp_set_transmitter(params, phy, 0);
5252         }
5253 }
5254
5255 /******************************************************************/
5256 /*              Used by 8706 and 8727                             */
5257 /******************************************************************/
5258 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
5259                                  struct bnx2x_phy *phy,
5260                                  u16 alarm_status_offset,
5261                                  u16 alarm_ctrl_offset)
5262 {
5263         u16 alarm_status, val;
5264         bnx2x_cl45_read(bp, phy,
5265                         MDIO_PMA_DEVAD, alarm_status_offset,
5266                         &alarm_status);
5267         bnx2x_cl45_read(bp, phy,
5268                         MDIO_PMA_DEVAD, alarm_status_offset,
5269                         &alarm_status);
5270         /* Mask or enable the fault event. */
5271         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
5272         if (alarm_status & (1<<0))
5273                 val &= ~(1<<0);
5274         else
5275                 val |= (1<<0);
5276         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
5277 }
5278 /******************************************************************/
5279 /*              common BCM8706/BCM8726 PHY SECTION                */
5280 /******************************************************************/
5281 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5282                                       struct link_params *params,
5283                                       struct link_vars *vars)
5284 {
5285         u8 link_up = 0;
5286         u16 val1, val2, rx_sd, pcs_status;
5287         struct bnx2x *bp = params->bp;
5288         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5289         /* Clear RX Alarm*/
5290         bnx2x_cl45_read(bp, phy,
5291                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5292
5293         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5294                              MDIO_PMA_REG_TX_ALARM_CTRL);
5295
5296         /* clear LASI indication*/
5297         bnx2x_cl45_read(bp, phy,
5298                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5299         bnx2x_cl45_read(bp, phy,
5300                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5301         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5302
5303         bnx2x_cl45_read(bp, phy,
5304                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5305         bnx2x_cl45_read(bp, phy,
5306                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5307         bnx2x_cl45_read(bp, phy,
5308                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5309         bnx2x_cl45_read(bp, phy,
5310                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5311
5312         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5313                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5314         /*
5315          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5316          * are set, or if the autoneg bit 1 is set
5317          */
5318         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5319         if (link_up) {
5320                 if (val2 & (1<<1))
5321                         vars->line_speed = SPEED_1000;
5322                 else
5323                         vars->line_speed = SPEED_10000;
5324                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5325                 vars->duplex = DUPLEX_FULL;
5326         }
5327
5328         /* Capture 10G link fault. Read twice to clear stale value. */
5329         if (vars->line_speed == SPEED_10000) {
5330                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5331                             MDIO_PMA_REG_TX_ALARM, &val1);
5332                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5333                             MDIO_PMA_REG_TX_ALARM, &val1);
5334                 if (val1 & (1<<0))
5335                         vars->fault_detected = 1;
5336         }
5337
5338         return link_up;
5339 }
5340
5341 /******************************************************************/
5342 /*                      BCM8706 PHY SECTION                       */
5343 /******************************************************************/
5344 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5345                                  struct link_params *params,
5346                                  struct link_vars *vars)
5347 {
5348         u32 tx_en_mode;
5349         u16 cnt, val, tmp1;
5350         struct bnx2x *bp = params->bp;
5351         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5352                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5353         /* HW reset */
5354         bnx2x_ext_phy_hw_reset(bp, params->port);
5355         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5356         bnx2x_wait_reset_complete(bp, phy, params);
5357
5358         /* Wait until fw is loaded */
5359         for (cnt = 0; cnt < 100; cnt++) {
5360                 bnx2x_cl45_read(bp, phy,
5361                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5362                 if (val)
5363                         break;
5364                 msleep(10);
5365         }
5366         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5367         if ((params->feature_config_flags &
5368              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5369                 u8 i;
5370                 u16 reg;
5371                 for (i = 0; i < 4; i++) {
5372                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5373                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5374                                    MDIO_XS_8706_REG_BANK_RX0);
5375                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5376                         /* Clear first 3 bits of the control */
5377                         val &= ~0x7;
5378                         /* Set control bits according to configuration */
5379                         val |= (phy->rx_preemphasis[i] & 0x7);
5380                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5381                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5382                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5383                 }
5384         }
5385         /* Force speed */
5386         if (phy->req_line_speed == SPEED_10000) {
5387                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5388
5389                 bnx2x_cl45_write(bp, phy,
5390                                  MDIO_PMA_DEVAD,
5391                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5392                 bnx2x_cl45_write(bp, phy,
5393                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5394                                  0);
5395                 /* Arm LASI for link and Tx fault. */
5396                 bnx2x_cl45_write(bp, phy,
5397                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 3);
5398         } else {
5399                 /* Force 1Gbps using autoneg with 1G advertisement */
5400
5401                 /* Allow CL37 through CL73 */
5402                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5403                 bnx2x_cl45_write(bp, phy,
5404                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5405
5406                 /* Enable Full-Duplex advertisement on CL37 */
5407                 bnx2x_cl45_write(bp, phy,
5408                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5409                 /* Enable CL37 AN */
5410                 bnx2x_cl45_write(bp, phy,
5411                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5412                 /* 1G support */
5413                 bnx2x_cl45_write(bp, phy,
5414                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5415
5416                 /* Enable clause 73 AN */
5417                 bnx2x_cl45_write(bp, phy,
5418                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5419                 bnx2x_cl45_write(bp, phy,
5420                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5421                                  0x0400);
5422                 bnx2x_cl45_write(bp, phy,
5423                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5424                                  0x0004);
5425         }
5426         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5427
5428         /*
5429          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5430          * power mode, if TX Laser is disabled
5431          */
5432
5433         tx_en_mode = REG_RD(bp, params->shmem_base +
5434                             offsetof(struct shmem_region,
5435                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5436                         & PORT_HW_CFG_TX_LASER_MASK;
5437
5438         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5439                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5440                 bnx2x_cl45_read(bp, phy,
5441                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5442                 tmp1 |= 0x1;
5443                 bnx2x_cl45_write(bp, phy,
5444                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5445         }
5446
5447         return 0;
5448 }
5449
5450 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
5451                                   struct link_params *params,
5452                                   struct link_vars *vars)
5453 {
5454         return bnx2x_8706_8726_read_status(phy, params, vars);
5455 }
5456
5457 /******************************************************************/
5458 /*                      BCM8726 PHY SECTION                       */
5459 /******************************************************************/
5460 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5461                                        struct link_params *params)
5462 {
5463         struct bnx2x *bp = params->bp;
5464         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5465         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5466 }
5467
5468 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5469                                          struct link_params *params)
5470 {
5471         struct bnx2x *bp = params->bp;
5472         /* Need to wait 100ms after reset */
5473         msleep(100);
5474
5475         /* Micro controller re-boot */
5476         bnx2x_cl45_write(bp, phy,
5477                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5478
5479         /* Set soft reset */
5480         bnx2x_cl45_write(bp, phy,
5481                          MDIO_PMA_DEVAD,
5482                          MDIO_PMA_REG_GEN_CTRL,
5483                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5484
5485         bnx2x_cl45_write(bp, phy,
5486                          MDIO_PMA_DEVAD,
5487                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5488
5489         bnx2x_cl45_write(bp, phy,
5490                          MDIO_PMA_DEVAD,
5491                          MDIO_PMA_REG_GEN_CTRL,
5492                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5493
5494         /* wait for 150ms for microcode load */
5495         msleep(150);
5496
5497         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5498         bnx2x_cl45_write(bp, phy,
5499                          MDIO_PMA_DEVAD,
5500                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5501
5502         msleep(200);
5503         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5504 }
5505
5506 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5507                                  struct link_params *params,
5508                                  struct link_vars *vars)
5509 {
5510         struct bnx2x *bp = params->bp;
5511         u16 val1;
5512         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5513         if (link_up) {
5514                 bnx2x_cl45_read(bp, phy,
5515                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5516                                 &val1);
5517                 if (val1 & (1<<15)) {
5518                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5519                         link_up = 0;
5520                         vars->line_speed = 0;
5521                 }
5522         }
5523         return link_up;
5524 }
5525
5526
5527 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
5528                                   struct link_params *params,
5529                                   struct link_vars *vars)
5530 {
5531         struct bnx2x *bp = params->bp;
5532         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5533
5534         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5535         bnx2x_wait_reset_complete(bp, phy, params);
5536
5537         bnx2x_8726_external_rom_boot(phy, params);
5538
5539         /*
5540          * Need to call module detected on initialization since the module
5541          * detection triggered by actual module insertion might occur before
5542          * driver is loaded, and when driver is loaded, it reset all
5543          * registers, including the transmitter
5544          */
5545         bnx2x_sfp_module_detection(phy, params);
5546
5547         if (phy->req_line_speed == SPEED_1000) {
5548                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5549                 bnx2x_cl45_write(bp, phy,
5550                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5551                 bnx2x_cl45_write(bp, phy,
5552                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5553                 bnx2x_cl45_write(bp, phy,
5554                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5555                 bnx2x_cl45_write(bp, phy,
5556                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5557                                  0x400);
5558         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5559                    (phy->speed_cap_mask &
5560                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5561                    ((phy->speed_cap_mask &
5562                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5563                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5564                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5565                 /* Set Flow control */
5566                 bnx2x_ext_phy_set_pause(params, phy, vars);
5567                 bnx2x_cl45_write(bp, phy,
5568                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5569                 bnx2x_cl45_write(bp, phy,
5570                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5571                 bnx2x_cl45_write(bp, phy,
5572                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5573                 bnx2x_cl45_write(bp, phy,
5574                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5575                 bnx2x_cl45_write(bp, phy,
5576                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5577                 /*
5578                  * Enable RX-ALARM control to receive interrupt for 1G speed
5579                  * change
5580                  */
5581                 bnx2x_cl45_write(bp, phy,
5582                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5583                 bnx2x_cl45_write(bp, phy,
5584                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5585                                  0x400);
5586
5587         } else { /* Default 10G. Set only LASI control */
5588                 bnx2x_cl45_write(bp, phy,
5589                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5590         }
5591
5592         /* Set TX PreEmphasis if needed */
5593         if ((params->feature_config_flags &
5594              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5595                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5596                          "TX_CTRL2 0x%x\n",
5597                          phy->tx_preemphasis[0],
5598                          phy->tx_preemphasis[1]);
5599                 bnx2x_cl45_write(bp, phy,
5600                                  MDIO_PMA_DEVAD,
5601                                  MDIO_PMA_REG_8726_TX_CTRL1,
5602                                  phy->tx_preemphasis[0]);
5603
5604                 bnx2x_cl45_write(bp, phy,
5605                                  MDIO_PMA_DEVAD,
5606                                  MDIO_PMA_REG_8726_TX_CTRL2,
5607                                  phy->tx_preemphasis[1]);
5608         }
5609
5610         return 0;
5611
5612 }
5613
5614 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5615                                   struct link_params *params)
5616 {
5617         struct bnx2x *bp = params->bp;
5618         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5619         /* Set serial boot control for external load */
5620         bnx2x_cl45_write(bp, phy,
5621                          MDIO_PMA_DEVAD,
5622                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
5623 }
5624
5625 /******************************************************************/
5626 /*                      BCM8727 PHY SECTION                       */
5627 /******************************************************************/
5628
5629 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5630                                     struct link_params *params, u8 mode)
5631 {
5632         struct bnx2x *bp = params->bp;
5633         u16 led_mode_bitmask = 0;
5634         u16 gpio_pins_bitmask = 0;
5635         u16 val;
5636         /* Only NOC flavor requires to set the LED specifically */
5637         if (!(phy->flags & FLAGS_NOC))
5638                 return;
5639         switch (mode) {
5640         case LED_MODE_FRONT_PANEL_OFF:
5641         case LED_MODE_OFF:
5642                 led_mode_bitmask = 0;
5643                 gpio_pins_bitmask = 0x03;
5644                 break;
5645         case LED_MODE_ON:
5646                 led_mode_bitmask = 0;
5647                 gpio_pins_bitmask = 0x02;
5648                 break;
5649         case LED_MODE_OPER:
5650                 led_mode_bitmask = 0x60;
5651                 gpio_pins_bitmask = 0x11;
5652                 break;
5653         }
5654         bnx2x_cl45_read(bp, phy,
5655                         MDIO_PMA_DEVAD,
5656                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5657                         &val);
5658         val &= 0xff8f;
5659         val |= led_mode_bitmask;
5660         bnx2x_cl45_write(bp, phy,
5661                          MDIO_PMA_DEVAD,
5662                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5663                          val);
5664         bnx2x_cl45_read(bp, phy,
5665                         MDIO_PMA_DEVAD,
5666                         MDIO_PMA_REG_8727_GPIO_CTRL,
5667                         &val);
5668         val &= 0xffe0;
5669         val |= gpio_pins_bitmask;
5670         bnx2x_cl45_write(bp, phy,
5671                          MDIO_PMA_DEVAD,
5672                          MDIO_PMA_REG_8727_GPIO_CTRL,
5673                          val);
5674 }
5675 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5676                                 struct link_params *params) {
5677         u32 swap_val, swap_override;
5678         u8 port;
5679         /*
5680          * The PHY reset is controlled by GPIO 1. Fake the port number
5681          * to cancel the swap done in set_gpio()
5682          */
5683         struct bnx2x *bp = params->bp;
5684         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5685         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5686         port = (swap_val && swap_override) ^ 1;
5687         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5688                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5689 }
5690
5691 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
5692                                   struct link_params *params,
5693                                   struct link_vars *vars)
5694 {
5695         u32 tx_en_mode;
5696         u16 tmp1, val, mod_abs, tmp2;
5697         u16 rx_alarm_ctrl_val;
5698         u16 lasi_ctrl_val;
5699         struct bnx2x *bp = params->bp;
5700         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5701
5702         bnx2x_wait_reset_complete(bp, phy, params);
5703         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5704         /* Should be 0x6 to enable XS on Tx side. */
5705         lasi_ctrl_val = 0x0006;
5706
5707         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5708         /* enable LASI */
5709         bnx2x_cl45_write(bp, phy,
5710                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5711                          rx_alarm_ctrl_val);
5712         bnx2x_cl45_write(bp, phy,
5713                          MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5714                          0);
5715         bnx2x_cl45_write(bp, phy,
5716                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5717
5718         /*
5719          * Initially configure MOD_ABS to interrupt when module is
5720          * presence( bit 8)
5721          */
5722         bnx2x_cl45_read(bp, phy,
5723                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5724         /*
5725          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5726          * When the EDC is off it locks onto a reference clock and avoids
5727          * becoming 'lost'
5728          */
5729         mod_abs &= ~(1<<8);
5730         if (!(phy->flags & FLAGS_NOC))
5731                 mod_abs &= ~(1<<9);
5732         bnx2x_cl45_write(bp, phy,
5733                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5734
5735
5736         /* Make MOD_ABS give interrupt on change */
5737         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5738                         &val);
5739         val |= (1<<12);
5740         if (phy->flags & FLAGS_NOC)
5741                 val |= (3<<5);
5742
5743         /*
5744          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5745          * status which reflect SFP+ module over-current
5746          */
5747         if (!(phy->flags & FLAGS_NOC))
5748                 val &= 0xff8f; /* Reset bits 4-6 */
5749         bnx2x_cl45_write(bp, phy,
5750                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5751
5752         bnx2x_8727_power_module(bp, phy, 1);
5753
5754         bnx2x_cl45_read(bp, phy,
5755                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5756
5757         bnx2x_cl45_read(bp, phy,
5758                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5759
5760         /* Set option 1G speed */
5761         if (phy->req_line_speed == SPEED_1000) {
5762                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5763                 bnx2x_cl45_write(bp, phy,
5764                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5765                 bnx2x_cl45_write(bp, phy,
5766                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5767                 bnx2x_cl45_read(bp, phy,
5768                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5769                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5770                 /*
5771                  * Power down the XAUI until link is up in case of dual-media
5772                  * and 1G
5773                  */
5774                 if (DUAL_MEDIA(params)) {
5775                         bnx2x_cl45_read(bp, phy,
5776                                         MDIO_PMA_DEVAD,
5777                                         MDIO_PMA_REG_8727_PCS_GP, &val);
5778                         val |= (3<<10);
5779                         bnx2x_cl45_write(bp, phy,
5780                                          MDIO_PMA_DEVAD,
5781                                          MDIO_PMA_REG_8727_PCS_GP, val);
5782                 }
5783         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5784                    ((phy->speed_cap_mask &
5785                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5786                    ((phy->speed_cap_mask &
5787                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5788                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5789
5790                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5791                 bnx2x_cl45_write(bp, phy,
5792                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5793                 bnx2x_cl45_write(bp, phy,
5794                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5795         } else {
5796                 /*
5797                  * Since the 8727 has only single reset pin, need to set the 10G
5798                  * registers although it is default
5799                  */
5800                 bnx2x_cl45_write(bp, phy,
5801                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5802                                  0x0020);
5803                 bnx2x_cl45_write(bp, phy,
5804                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5805                 bnx2x_cl45_write(bp, phy,
5806                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5807                 bnx2x_cl45_write(bp, phy,
5808                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5809                                  0x0008);
5810         }
5811
5812         /*
5813          * Set 2-wire transfer rate of SFP+ module EEPROM
5814          * to 100Khz since some DACs(direct attached cables) do
5815          * not work at 400Khz.
5816          */
5817         bnx2x_cl45_write(bp, phy,
5818                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5819                          0xa001);
5820
5821         /* Set TX PreEmphasis if needed */
5822         if ((params->feature_config_flags &
5823              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5824                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5825                            phy->tx_preemphasis[0],
5826                            phy->tx_preemphasis[1]);
5827                 bnx2x_cl45_write(bp, phy,
5828                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5829                                  phy->tx_preemphasis[0]);
5830
5831                 bnx2x_cl45_write(bp, phy,
5832                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5833                                  phy->tx_preemphasis[1]);
5834         }
5835
5836         /*
5837          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5838          * power mode, if TX Laser is disabled
5839          */
5840         tx_en_mode = REG_RD(bp, params->shmem_base +
5841                             offsetof(struct shmem_region,
5842                                 dev_info.port_hw_config[params->port].sfp_ctrl))
5843                         & PORT_HW_CFG_TX_LASER_MASK;
5844
5845         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5846
5847                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5848                 bnx2x_cl45_read(bp, phy,
5849                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5850                 tmp2 |= 0x1000;
5851                 tmp2 &= 0xFFEF;
5852                 bnx2x_cl45_write(bp, phy,
5853                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5854         }
5855
5856         return 0;
5857 }
5858
5859 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5860                                       struct link_params *params)
5861 {
5862         struct bnx2x *bp = params->bp;
5863         u16 mod_abs, rx_alarm_status;
5864         u32 val = REG_RD(bp, params->shmem_base +
5865                              offsetof(struct shmem_region, dev_info.
5866                                       port_feature_config[params->port].
5867                                       config));
5868         bnx2x_cl45_read(bp, phy,
5869                         MDIO_PMA_DEVAD,
5870                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5871         if (mod_abs & (1<<8)) {
5872
5873                 /* Module is absent */
5874                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5875                             "show module is absent\n");
5876                 phy->media_type = ETH_PHY_NOT_PRESENT;
5877                 /*
5878                  * 1. Set mod_abs to detect next module
5879                  *    presence event
5880                  * 2. Set EDC off by setting OPTXLOS signal input to low
5881                  *    (bit 9).
5882                  *    When the EDC is off it locks onto a reference clock and
5883                  *    avoids becoming 'lost'.
5884                  */
5885                 mod_abs &= ~(1<<8);
5886                 if (!(phy->flags & FLAGS_NOC))
5887                         mod_abs &= ~(1<<9);
5888                 bnx2x_cl45_write(bp, phy,
5889                                  MDIO_PMA_DEVAD,
5890                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5891
5892                 /*
5893                  * Clear RX alarm since it stays up as long as
5894                  * the mod_abs wasn't changed
5895                  */
5896                 bnx2x_cl45_read(bp, phy,
5897                                 MDIO_PMA_DEVAD,
5898                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5899
5900         } else {
5901                 /* Module is present */
5902                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5903                             "show module is present\n");
5904                 /*
5905                  * First disable transmitter, and if the module is ok, the
5906                  * module_detection will enable it
5907                  * 1. Set mod_abs to detect next module absent event ( bit 8)
5908                  * 2. Restore the default polarity of the OPRXLOS signal and
5909                  * this signal will then correctly indicate the presence or
5910                  * absence of the Rx signal. (bit 9)
5911                  */
5912                 mod_abs |= (1<<8);
5913                 if (!(phy->flags & FLAGS_NOC))
5914                         mod_abs |= (1<<9);
5915                 bnx2x_cl45_write(bp, phy,
5916                                  MDIO_PMA_DEVAD,
5917                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5918
5919                 /*
5920                  * Clear RX alarm since it stays up as long as the mod_abs
5921                  * wasn't changed. This is need to be done before calling the
5922                  * module detection, otherwise it will clear* the link update
5923                  * alarm
5924                  */
5925                 bnx2x_cl45_read(bp, phy,
5926                                 MDIO_PMA_DEVAD,
5927                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5928
5929
5930                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5931                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5932                         bnx2x_sfp_set_transmitter(params, phy, 0);
5933
5934                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5935                         bnx2x_sfp_module_detection(phy, params);
5936                 else
5937                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5938         }
5939
5940         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5941                    rx_alarm_status);
5942         /* No need to check link status in case of module plugged in/out */
5943 }
5944
5945 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5946                                  struct link_params *params,
5947                                  struct link_vars *vars)
5948
5949 {
5950         struct bnx2x *bp = params->bp;
5951         u8 link_up = 0, oc_port = params->port;
5952         u16 link_status = 0;
5953         u16 rx_alarm_status, lasi_ctrl, val1;
5954
5955         /* If PHY is not initialized, do not check link status */
5956         bnx2x_cl45_read(bp, phy,
5957                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5958                         &lasi_ctrl);
5959         if (!lasi_ctrl)
5960                 return 0;
5961
5962         /* Check the LASI on Rx */
5963         bnx2x_cl45_read(bp, phy,
5964                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5965                         &rx_alarm_status);
5966         vars->line_speed = 0;
5967         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
5968
5969         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5970                              MDIO_PMA_REG_TX_ALARM_CTRL);
5971
5972         bnx2x_cl45_read(bp, phy,
5973                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5974
5975         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5976
5977         /* Clear MSG-OUT */
5978         bnx2x_cl45_read(bp, phy,
5979                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5980
5981         /*
5982          * If a module is present and there is need to check
5983          * for over current
5984          */
5985         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5986                 /* Check over-current using 8727 GPIO0 input*/
5987                 bnx2x_cl45_read(bp, phy,
5988                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5989                                 &val1);
5990
5991                 if ((val1 & (1<<8)) == 0) {
5992                         if (!CHIP_IS_E1x(bp))
5993                                 oc_port = BP_PATH(bp) + (params->port << 1);
5994                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5995                                        " on port %d\n", oc_port);
5996                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
5997                                             " been detected and the power to "
5998                                             "that SFP+ module has been removed"
5999                                             " to prevent failure of the card."
6000                                             " Please remove the SFP+ module and"
6001                                             " restart the system to clear this"
6002                                             " error.\n",
6003                          oc_port);
6004                         /* Disable all RX_ALARMs except for mod_abs */
6005                         bnx2x_cl45_write(bp, phy,
6006                                          MDIO_PMA_DEVAD,
6007                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
6008
6009                         bnx2x_cl45_read(bp, phy,
6010                                         MDIO_PMA_DEVAD,
6011                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6012                         /* Wait for module_absent_event */
6013                         val1 |= (1<<8);
6014                         bnx2x_cl45_write(bp, phy,
6015                                          MDIO_PMA_DEVAD,
6016                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
6017                         /* Clear RX alarm */
6018                         bnx2x_cl45_read(bp, phy,
6019                                 MDIO_PMA_DEVAD,
6020                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
6021                         return 0;
6022                 }
6023         } /* Over current check */
6024
6025         /* When module absent bit is set, check module */
6026         if (rx_alarm_status & (1<<5)) {
6027                 bnx2x_8727_handle_mod_abs(phy, params);
6028                 /* Enable all mod_abs and link detection bits */
6029                 bnx2x_cl45_write(bp, phy,
6030                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6031                                  ((1<<5) | (1<<2)));
6032         }
6033         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
6034         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
6035         /* If transmitter is disabled, ignore false link up indication */
6036         bnx2x_cl45_read(bp, phy,
6037                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6038         if (val1 & (1<<15)) {
6039                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
6040                 return 0;
6041         }
6042
6043         bnx2x_cl45_read(bp, phy,
6044                         MDIO_PMA_DEVAD,
6045                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
6046
6047         /*
6048          * Bits 0..2 --> speed detected,
6049          * Bits 13..15--> link is down
6050          */
6051         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
6052                 link_up = 1;
6053                 vars->line_speed = SPEED_10000;
6054                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
6055                            params->port);
6056         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
6057                 link_up = 1;
6058                 vars->line_speed = SPEED_1000;
6059                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
6060                            params->port);
6061         } else {
6062                 link_up = 0;
6063                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
6064                            params->port);
6065         }
6066
6067         /* Capture 10G link fault. */
6068         if (vars->line_speed == SPEED_10000) {
6069                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6070                             MDIO_PMA_REG_TX_ALARM, &val1);
6071
6072                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6073                             MDIO_PMA_REG_TX_ALARM, &val1);
6074
6075                 if (val1 & (1<<0)) {
6076                         vars->fault_detected = 1;
6077                 }
6078         }
6079
6080         if (link_up) {
6081                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6082                 vars->duplex = DUPLEX_FULL;
6083                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
6084         }
6085
6086         if ((DUAL_MEDIA(params)) &&
6087             (phy->req_line_speed == SPEED_1000)) {
6088                 bnx2x_cl45_read(bp, phy,
6089                                 MDIO_PMA_DEVAD,
6090                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
6091                 /*
6092                  * In case of dual-media board and 1G, power up the XAUI side,
6093                  * otherwise power it down. For 10G it is done automatically
6094                  */
6095                 if (link_up)
6096                         val1 &= ~(3<<10);
6097                 else
6098                         val1 |= (3<<10);
6099                 bnx2x_cl45_write(bp, phy,
6100                                  MDIO_PMA_DEVAD,
6101                                  MDIO_PMA_REG_8727_PCS_GP, val1);
6102         }
6103         return link_up;
6104 }
6105
6106 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
6107                                   struct link_params *params)
6108 {
6109         struct bnx2x *bp = params->bp;
6110         /* Disable Transmitter */
6111         bnx2x_sfp_set_transmitter(params, phy, 0);
6112         /* Clear LASI */
6113         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
6114
6115 }
6116
6117 /******************************************************************/
6118 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
6119 /******************************************************************/
6120 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
6121                                            struct link_params *params)
6122 {
6123         u16 val, fw_ver1, fw_ver2, cnt;
6124         u8 port;
6125         struct bnx2x *bp = params->bp;
6126
6127         port = params->port;
6128
6129         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6130         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
6131         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
6132         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6133         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
6134         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
6135         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
6136
6137         for (cnt = 0; cnt < 100; cnt++) {
6138                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6139                 if (val & 1)
6140                         break;
6141                 udelay(5);
6142         }
6143         if (cnt == 100) {
6144                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6145                 bnx2x_save_spirom_version(bp, port, 0,
6146                                           phy->ver_addr);
6147                 return;
6148         }
6149
6150
6151         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
6152         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
6153         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
6154         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
6155         for (cnt = 0; cnt < 100; cnt++) {
6156                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
6157                 if (val & 1)
6158                         break;
6159                 udelay(5);
6160         }
6161         if (cnt == 100) {
6162                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6163                 bnx2x_save_spirom_version(bp, port, 0,
6164                                           phy->ver_addr);
6165                 return;
6166         }
6167
6168         /* lower 16 bits of the register SPI_FW_STATUS */
6169         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
6170         /* upper 16 bits of register SPI_FW_STATUS */
6171         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
6172
6173         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
6174                                   phy->ver_addr);
6175 }
6176
6177 static void bnx2x_848xx_set_led(struct bnx2x *bp,
6178                                 struct bnx2x_phy *phy)
6179 {
6180         u16 val;
6181
6182         /* PHYC_CTL_LED_CTL */
6183         bnx2x_cl45_read(bp, phy,
6184                         MDIO_PMA_DEVAD,
6185                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
6186         val &= 0xFE00;
6187         val |= 0x0092;
6188
6189         bnx2x_cl45_write(bp, phy,
6190                          MDIO_PMA_DEVAD,
6191                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
6192
6193         bnx2x_cl45_write(bp, phy,
6194                          MDIO_PMA_DEVAD,
6195                          MDIO_PMA_REG_8481_LED1_MASK,
6196                          0x80);
6197
6198         bnx2x_cl45_write(bp, phy,
6199                          MDIO_PMA_DEVAD,
6200                          MDIO_PMA_REG_8481_LED2_MASK,
6201                          0x18);
6202
6203         /* Select activity source by Tx and Rx, as suggested by PHY AE */
6204         bnx2x_cl45_write(bp, phy,
6205                          MDIO_PMA_DEVAD,
6206                          MDIO_PMA_REG_8481_LED3_MASK,
6207                          0x0006);
6208
6209         /* Select the closest activity blink rate to that in 10/100/1000 */
6210         bnx2x_cl45_write(bp, phy,
6211                         MDIO_PMA_DEVAD,
6212                         MDIO_PMA_REG_8481_LED3_BLINK,
6213                         0);
6214
6215         bnx2x_cl45_read(bp, phy,
6216                         MDIO_PMA_DEVAD,
6217                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
6218         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6219
6220         bnx2x_cl45_write(bp, phy,
6221                          MDIO_PMA_DEVAD,
6222                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
6223
6224         /* 'Interrupt Mask' */
6225         bnx2x_cl45_write(bp, phy,
6226                          MDIO_AN_DEVAD,
6227                          0xFFFB, 0xFFFD);
6228 }
6229
6230 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
6231                                        struct link_params *params,
6232                                        struct link_vars *vars)
6233 {
6234         struct bnx2x *bp = params->bp;
6235         u16 autoneg_val, an_1000_val, an_10_100_val;
6236         u16 tmp_req_line_speed;
6237
6238         tmp_req_line_speed = phy->req_line_speed;
6239         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6240                 if (phy->req_line_speed == SPEED_10000)
6241                         phy->req_line_speed = SPEED_AUTO_NEG;
6242
6243         /*
6244          * This phy uses the NIG latch mechanism since link indication
6245          * arrives through its LED4 and not via its LASI signal, so we
6246          * get steady signal instead of clear on read
6247          */
6248         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6249                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
6250
6251         bnx2x_cl45_write(bp, phy,
6252                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6253
6254         bnx2x_848xx_set_led(bp, phy);
6255
6256         /* set 1000 speed advertisement */
6257         bnx2x_cl45_read(bp, phy,
6258                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6259                         &an_1000_val);
6260
6261         bnx2x_ext_phy_set_pause(params, phy, vars);
6262         bnx2x_cl45_read(bp, phy,
6263                         MDIO_AN_DEVAD,
6264                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
6265                         &an_10_100_val);
6266         bnx2x_cl45_read(bp, phy,
6267                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6268                         &autoneg_val);
6269         /* Disable forced speed */
6270         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6271         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6272
6273         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6274              (phy->speed_cap_mask &
6275              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6276             (phy->req_line_speed == SPEED_1000)) {
6277                 an_1000_val |= (1<<8);
6278                 autoneg_val |= (1<<9 | 1<<12);
6279                 if (phy->req_duplex == DUPLEX_FULL)
6280                         an_1000_val |= (1<<9);
6281                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6282         } else
6283                 an_1000_val &= ~((1<<8) | (1<<9));
6284
6285         bnx2x_cl45_write(bp, phy,
6286                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6287                          an_1000_val);
6288
6289         /* set 10 speed advertisement */
6290         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6291              (phy->speed_cap_mask &
6292              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6293               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6294                 an_10_100_val |= (1<<7);
6295                 /* Enable autoneg and restart autoneg for legacy speeds */
6296                 autoneg_val |= (1<<9 | 1<<12);
6297
6298                 if (phy->req_duplex == DUPLEX_FULL)
6299                         an_10_100_val |= (1<<8);
6300                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6301         }
6302         /* set 10 speed advertisement */
6303         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6304             (phy->speed_cap_mask &
6305           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6306            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6307                 an_10_100_val |= (1<<5);
6308                 autoneg_val |= (1<<9 | 1<<12);
6309                 if (phy->req_duplex == DUPLEX_FULL)
6310                         an_10_100_val |= (1<<6);
6311                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6312         }
6313
6314         /* Only 10/100 are allowed to work in FORCE mode */
6315         if (phy->req_line_speed == SPEED_100) {
6316                 autoneg_val |= (1<<13);
6317                 /* Enabled AUTO-MDIX when autoneg is disabled */
6318                 bnx2x_cl45_write(bp, phy,
6319                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6320                                  (1<<15 | 1<<9 | 7<<0));
6321                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6322         }
6323         if (phy->req_line_speed == SPEED_10) {
6324                 /* Enabled AUTO-MDIX when autoneg is disabled */
6325                 bnx2x_cl45_write(bp, phy,
6326                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6327                                  (1<<15 | 1<<9 | 7<<0));
6328                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6329         }
6330
6331         bnx2x_cl45_write(bp, phy,
6332                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6333                          an_10_100_val);
6334
6335         if (phy->req_duplex == DUPLEX_FULL)
6336                 autoneg_val |= (1<<8);
6337
6338         bnx2x_cl45_write(bp, phy,
6339                          MDIO_AN_DEVAD,
6340                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6341
6342         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6343             (phy->speed_cap_mask &
6344              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6345                 (phy->req_line_speed == SPEED_10000)) {
6346                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
6347                         /* Restart autoneg for 10G*/
6348
6349                         bnx2x_cl45_write(bp, phy,
6350                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6351                                  0x3200);
6352         } else if (phy->req_line_speed != SPEED_10 &&
6353                    phy->req_line_speed != SPEED_100) {
6354                 bnx2x_cl45_write(bp, phy,
6355                                  MDIO_AN_DEVAD,
6356                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6357                                  1);
6358         }
6359         /* Save spirom version */
6360         bnx2x_save_848xx_spirom_version(phy, params);
6361
6362         phy->req_line_speed = tmp_req_line_speed;
6363
6364         return 0;
6365 }
6366
6367 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
6368                                   struct link_params *params,
6369                                   struct link_vars *vars)
6370 {
6371         struct bnx2x *bp = params->bp;
6372         /* Restore normal power mode*/
6373         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6374                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6375
6376         /* HW reset */
6377         bnx2x_ext_phy_hw_reset(bp, params->port);
6378         bnx2x_wait_reset_complete(bp, phy, params);
6379
6380         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6381         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6382 }
6383
6384
6385 #define PHY84833_HDSHK_WAIT 300
6386 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
6387                                    struct link_params *params,
6388                                    struct link_vars *vars)
6389 {
6390         u32 idx;
6391         u16 val;
6392         u16 data = 0x01b1;
6393         struct bnx2x *bp = params->bp;
6394         /* Do pair swap */
6395
6396
6397         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
6398         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6399                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
6400                         PHY84833_CMD_OPEN_OVERRIDE);
6401         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
6402                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6403                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
6404                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
6405                         break;
6406                 msleep(1);
6407         }
6408         if (idx >= PHY84833_HDSHK_WAIT) {
6409                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
6410                 return -EINVAL;
6411         }
6412
6413         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6414                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
6415                         data);
6416         /* Issue pair swap command */
6417         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6418                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
6419                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
6420         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
6421                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6422                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
6423                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
6424                         (val == PHY84833_CMD_COMPLETE_ERROR))
6425                         break;
6426                 msleep(1);
6427         }
6428         if ((idx >= PHY84833_HDSHK_WAIT) ||
6429                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
6430                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
6431                 return -EINVAL;
6432         }
6433         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6434                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
6435                         PHY84833_CMD_CLEAR_COMPLETE);
6436         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
6437         return 0;
6438 }
6439
6440 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6441                                    struct link_params *params,
6442                                    struct link_vars *vars)
6443 {
6444         struct bnx2x *bp = params->bp;
6445         u8 port, initialize = 1;
6446         u16 val;
6447         u16 temp;
6448         u32 actual_phy_selection, cms_enable;
6449         int rc = 0;
6450
6451         msleep(1);
6452
6453         if (!(CHIP_IS_E1(bp)))
6454                 port = BP_PATH(bp);
6455         else
6456                 port = params->port;
6457
6458         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
6459                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6460                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6461                                port);
6462         } else {
6463                 bnx2x_cl45_write(bp, phy,
6464                                 MDIO_PMA_DEVAD,
6465                                 MDIO_PMA_REG_CTRL, 0x8000);
6466         }
6467
6468         bnx2x_wait_reset_complete(bp, phy, params);
6469         /* Wait for GPHY to come out of reset */
6470         msleep(50);
6471
6472         /* Bring PHY out of super isolate mode */
6473         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
6474                 bnx2x_cl45_read(bp, phy,
6475                                 MDIO_CTL_DEVAD,
6476                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
6477                 val &= ~MDIO_84833_SUPER_ISOLATE;
6478                 bnx2x_cl45_write(bp, phy,
6479                                 MDIO_CTL_DEVAD,
6480                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
6481                 bnx2x_wait_reset_complete(bp, phy, params);
6482         }
6483
6484         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6485                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
6486
6487         /*
6488          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6489          */
6490         temp = vars->line_speed;
6491         vars->line_speed = SPEED_10000;
6492         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6493         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6494         vars->line_speed = temp;
6495
6496         /* Set dual-media configuration according to configuration */
6497
6498         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6499                         MDIO_CTL_REG_84823_MEDIA, &val);
6500         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6501                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6502                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6503                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6504                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6505         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6506                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6507
6508         actual_phy_selection = bnx2x_phy_selection(params);
6509
6510         switch (actual_phy_selection) {
6511         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6512                 /* Do nothing. Essentially this is like the priority copper */
6513                 break;
6514         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6515                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6516                 break;
6517         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6518                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6519                 break;
6520         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6521                 /* Do nothing here. The first PHY won't be initialized at all */
6522                 break;
6523         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6524                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6525                 initialize = 0;
6526                 break;
6527         }
6528         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6529                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6530
6531         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6532                          MDIO_CTL_REG_84823_MEDIA, val);
6533         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6534                    params->multi_phy_config, val);
6535
6536         if (initialize)
6537                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6538         else
6539                 bnx2x_save_848xx_spirom_version(phy, params);
6540         cms_enable = REG_RD(bp, params->shmem_base +
6541                         offsetof(struct shmem_region,
6542                         dev_info.port_hw_config[params->port].default_cfg)) &
6543                         PORT_HW_CFG_ENABLE_CMS_MASK;
6544
6545         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6546                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6547         if (cms_enable)
6548                 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6549         else
6550                 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6551         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6552                 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6553
6554
6555         return rc;
6556 }
6557
6558 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6559                                   struct link_params *params,
6560                                   struct link_vars *vars)
6561 {
6562         struct bnx2x *bp = params->bp;
6563         u16 val, val1, val2;
6564         u8 link_up = 0;
6565
6566
6567         /* Check 10G-BaseT link status */
6568         /* Check PMD signal ok */
6569         bnx2x_cl45_read(bp, phy,
6570                         MDIO_AN_DEVAD, 0xFFFA, &val1);
6571         bnx2x_cl45_read(bp, phy,
6572                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6573                         &val2);
6574         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6575
6576         /* Check link 10G */
6577         if (val2 & (1<<11)) {
6578                 vars->line_speed = SPEED_10000;
6579                 vars->duplex = DUPLEX_FULL;
6580                 link_up = 1;
6581                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6582         } else { /* Check Legacy speed link */
6583                 u16 legacy_status, legacy_speed;
6584
6585                 /* Enable expansion register 0x42 (Operation mode status) */
6586                 bnx2x_cl45_write(bp, phy,
6587                                  MDIO_AN_DEVAD,
6588                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6589
6590                 /* Get legacy speed operation status */
6591                 bnx2x_cl45_read(bp, phy,
6592                                 MDIO_AN_DEVAD,
6593                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6594                                 &legacy_status);
6595
6596                 DP(NETIF_MSG_LINK, "Legacy speed status"
6597                              " = 0x%x\n", legacy_status);
6598                 link_up = ((legacy_status & (1<<11)) == (1<<11));
6599                 if (link_up) {
6600                         legacy_speed = (legacy_status & (3<<9));
6601                         if (legacy_speed == (0<<9))
6602                                 vars->line_speed = SPEED_10;
6603                         else if (legacy_speed == (1<<9))
6604                                 vars->line_speed = SPEED_100;
6605                         else if (legacy_speed == (2<<9))
6606                                 vars->line_speed = SPEED_1000;
6607                         else /* Should not happen */
6608                                 vars->line_speed = 0;
6609
6610                         if (legacy_status & (1<<8))
6611                                 vars->duplex = DUPLEX_FULL;
6612                         else
6613                                 vars->duplex = DUPLEX_HALF;
6614
6615                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6616                                    " is_duplex_full= %d\n", vars->line_speed,
6617                                    (vars->duplex == DUPLEX_FULL));
6618                         /* Check legacy speed AN resolution */
6619                         bnx2x_cl45_read(bp, phy,
6620                                         MDIO_AN_DEVAD,
6621                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6622                                         &val);
6623                         if (val & (1<<5))
6624                                 vars->link_status |=
6625                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6626                         bnx2x_cl45_read(bp, phy,
6627                                         MDIO_AN_DEVAD,
6628                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6629                                         &val);
6630                         if ((val & (1<<0)) == 0)
6631                                 vars->link_status |=
6632                                         LINK_STATUS_PARALLEL_DETECTION_USED;
6633                 }
6634         }
6635         if (link_up) {
6636                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6637                            vars->line_speed);
6638                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6639         }
6640
6641         return link_up;
6642 }
6643
6644
6645 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6646 {
6647         int status = 0;
6648         u32 spirom_ver;
6649         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6650         status = bnx2x_format_ver(spirom_ver, str, len);
6651         return status;
6652 }
6653
6654 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6655                                 struct link_params *params)
6656 {
6657         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6658                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6659         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6660                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6661 }
6662
6663 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6664                                         struct link_params *params)
6665 {
6666         bnx2x_cl45_write(params->bp, phy,
6667                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6668         bnx2x_cl45_write(params->bp, phy,
6669                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6670 }
6671
6672 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6673                                    struct link_params *params)
6674 {
6675         struct bnx2x *bp = params->bp;
6676         u8 port;
6677
6678         if (!(CHIP_IS_E1(bp)))
6679                 port = BP_PATH(bp);
6680         else
6681                 port = params->port;
6682
6683         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
6684                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6685                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
6686                                port);
6687         } else {
6688                 bnx2x_cl45_write(bp, phy,
6689                                 MDIO_PMA_DEVAD,
6690                                 MDIO_PMA_REG_CTRL, 0x800);
6691         }
6692 }
6693
6694 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6695                                      struct link_params *params, u8 mode)
6696 {
6697         struct bnx2x *bp = params->bp;
6698         u16 val;
6699         u8 port;
6700
6701         if (!(CHIP_IS_E1(bp)))
6702                 port = BP_PATH(bp);
6703         else
6704                 port = params->port;
6705
6706         switch (mode) {
6707         case LED_MODE_OFF:
6708
6709                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
6710
6711                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6712                     SHARED_HW_CFG_LED_EXTPHY1) {
6713
6714                         /* Set LED masks */
6715                         bnx2x_cl45_write(bp, phy,
6716                                         MDIO_PMA_DEVAD,
6717                                         MDIO_PMA_REG_8481_LED1_MASK,
6718                                         0x0);
6719
6720                         bnx2x_cl45_write(bp, phy,
6721                                         MDIO_PMA_DEVAD,
6722                                         MDIO_PMA_REG_8481_LED2_MASK,
6723                                         0x0);
6724
6725                         bnx2x_cl45_write(bp, phy,
6726                                         MDIO_PMA_DEVAD,
6727                                         MDIO_PMA_REG_8481_LED3_MASK,
6728                                         0x0);
6729
6730                         bnx2x_cl45_write(bp, phy,
6731                                         MDIO_PMA_DEVAD,
6732                                         MDIO_PMA_REG_8481_LED5_MASK,
6733                                         0x0);
6734
6735                 } else {
6736                         bnx2x_cl45_write(bp, phy,
6737                                          MDIO_PMA_DEVAD,
6738                                          MDIO_PMA_REG_8481_LED1_MASK,
6739                                          0x0);
6740                 }
6741                 break;
6742         case LED_MODE_FRONT_PANEL_OFF:
6743
6744                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6745                    port);
6746
6747                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6748                     SHARED_HW_CFG_LED_EXTPHY1) {
6749
6750                         /* Set LED masks */
6751                         bnx2x_cl45_write(bp, phy,
6752                                          MDIO_PMA_DEVAD,
6753                                          MDIO_PMA_REG_8481_LED1_MASK,
6754                                          0x0);
6755
6756                         bnx2x_cl45_write(bp, phy,
6757                                          MDIO_PMA_DEVAD,
6758                                          MDIO_PMA_REG_8481_LED2_MASK,
6759                                          0x0);
6760
6761                         bnx2x_cl45_write(bp, phy,
6762                                          MDIO_PMA_DEVAD,
6763                                          MDIO_PMA_REG_8481_LED3_MASK,
6764                                          0x0);
6765
6766                         bnx2x_cl45_write(bp, phy,
6767                                          MDIO_PMA_DEVAD,
6768                                          MDIO_PMA_REG_8481_LED5_MASK,
6769                                          0x20);
6770
6771                 } else {
6772                         bnx2x_cl45_write(bp, phy,
6773                                          MDIO_PMA_DEVAD,
6774                                          MDIO_PMA_REG_8481_LED1_MASK,
6775                                          0x0);
6776                 }
6777                 break;
6778         case LED_MODE_ON:
6779
6780                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
6781
6782                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6783                     SHARED_HW_CFG_LED_EXTPHY1) {
6784                         /* Set control reg */
6785                         bnx2x_cl45_read(bp, phy,
6786                                         MDIO_PMA_DEVAD,
6787                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6788                                         &val);
6789                         val &= 0x8000;
6790                         val |= 0x2492;
6791
6792                         bnx2x_cl45_write(bp, phy,
6793                                          MDIO_PMA_DEVAD,
6794                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6795                                          val);
6796
6797                         /* Set LED masks */
6798                         bnx2x_cl45_write(bp, phy,
6799                                          MDIO_PMA_DEVAD,
6800                                          MDIO_PMA_REG_8481_LED1_MASK,
6801                                          0x0);
6802
6803                         bnx2x_cl45_write(bp, phy,
6804                                          MDIO_PMA_DEVAD,
6805                                          MDIO_PMA_REG_8481_LED2_MASK,
6806                                          0x20);
6807
6808                         bnx2x_cl45_write(bp, phy,
6809                                          MDIO_PMA_DEVAD,
6810                                          MDIO_PMA_REG_8481_LED3_MASK,
6811                                          0x20);
6812
6813                         bnx2x_cl45_write(bp, phy,
6814                                          MDIO_PMA_DEVAD,
6815                                          MDIO_PMA_REG_8481_LED5_MASK,
6816                                          0x0);
6817                 } else {
6818                         bnx2x_cl45_write(bp, phy,
6819                                          MDIO_PMA_DEVAD,
6820                                          MDIO_PMA_REG_8481_LED1_MASK,
6821                                          0x20);
6822                 }
6823                 break;
6824
6825         case LED_MODE_OPER:
6826
6827                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
6828
6829                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6830                     SHARED_HW_CFG_LED_EXTPHY1) {
6831
6832                         /* Set control reg */
6833                         bnx2x_cl45_read(bp, phy,
6834                                         MDIO_PMA_DEVAD,
6835                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6836                                         &val);
6837
6838                         if (!((val &
6839                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6840                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
6841                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
6842                                 bnx2x_cl45_write(bp, phy,
6843                                                  MDIO_PMA_DEVAD,
6844                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
6845                                                  0xa492);
6846                         }
6847
6848                         /* Set LED masks */
6849                         bnx2x_cl45_write(bp, phy,
6850                                          MDIO_PMA_DEVAD,
6851                                          MDIO_PMA_REG_8481_LED1_MASK,
6852                                          0x10);
6853
6854                         bnx2x_cl45_write(bp, phy,
6855                                          MDIO_PMA_DEVAD,
6856                                          MDIO_PMA_REG_8481_LED2_MASK,
6857                                          0x80);
6858
6859                         bnx2x_cl45_write(bp, phy,
6860                                          MDIO_PMA_DEVAD,
6861                                          MDIO_PMA_REG_8481_LED3_MASK,
6862                                          0x98);
6863
6864                         bnx2x_cl45_write(bp, phy,
6865                                          MDIO_PMA_DEVAD,
6866                                          MDIO_PMA_REG_8481_LED5_MASK,
6867                                          0x40);
6868
6869                 } else {
6870                         bnx2x_cl45_write(bp, phy,
6871                                          MDIO_PMA_DEVAD,
6872                                          MDIO_PMA_REG_8481_LED1_MASK,
6873                                          0x80);
6874
6875                         /* Tell LED3 to blink on source */
6876                         bnx2x_cl45_read(bp, phy,
6877                                         MDIO_PMA_DEVAD,
6878                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6879                                         &val);
6880                         val &= ~(7<<6);
6881                         val |= (1<<6); /* A83B[8:6]= 1 */
6882                         bnx2x_cl45_write(bp, phy,
6883                                          MDIO_PMA_DEVAD,
6884                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
6885                                          val);
6886                 }
6887                 break;
6888         }
6889 }
6890 /******************************************************************/
6891 /*                      SFX7101 PHY SECTION                       */
6892 /******************************************************************/
6893 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6894                                        struct link_params *params)
6895 {
6896         struct bnx2x *bp = params->bp;
6897         /* SFX7101_XGXS_TEST1 */
6898         bnx2x_cl45_write(bp, phy,
6899                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6900 }
6901
6902 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
6903                                   struct link_params *params,
6904                                   struct link_vars *vars)
6905 {
6906         u16 fw_ver1, fw_ver2, val;
6907         struct bnx2x *bp = params->bp;
6908         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6909
6910         /* Restore normal power mode*/
6911         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6912                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6913         /* HW reset */
6914         bnx2x_ext_phy_hw_reset(bp, params->port);
6915         bnx2x_wait_reset_complete(bp, phy, params);
6916
6917         bnx2x_cl45_write(bp, phy,
6918                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6919         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6920         bnx2x_cl45_write(bp, phy,
6921                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6922
6923         bnx2x_ext_phy_set_pause(params, phy, vars);
6924         /* Restart autoneg */
6925         bnx2x_cl45_read(bp, phy,
6926                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6927         val |= 0x200;
6928         bnx2x_cl45_write(bp, phy,
6929                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6930
6931         /* Save spirom version */
6932         bnx2x_cl45_read(bp, phy,
6933                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6934
6935         bnx2x_cl45_read(bp, phy,
6936                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6937         bnx2x_save_spirom_version(bp, params->port,
6938                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6939         return 0;
6940 }
6941
6942 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6943                                  struct link_params *params,
6944                                  struct link_vars *vars)
6945 {
6946         struct bnx2x *bp = params->bp;
6947         u8 link_up;
6948         u16 val1, val2;
6949         bnx2x_cl45_read(bp, phy,
6950                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6951         bnx2x_cl45_read(bp, phy,
6952                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6953         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6954                    val2, val1);
6955         bnx2x_cl45_read(bp, phy,
6956                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6957         bnx2x_cl45_read(bp, phy,
6958                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6959         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6960                    val2, val1);
6961         link_up = ((val1 & 4) == 4);
6962         /* if link is up print the AN outcome of the SFX7101 PHY */
6963         if (link_up) {
6964                 bnx2x_cl45_read(bp, phy,
6965                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6966                                 &val2);
6967                 vars->line_speed = SPEED_10000;
6968                 vars->duplex = DUPLEX_FULL;
6969                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6970                            val2, (val2 & (1<<14)));
6971                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6972                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6973         }
6974         return link_up;
6975 }
6976
6977 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6978 {
6979         if (*len < 5)
6980                 return -EINVAL;
6981         str[0] = (spirom_ver & 0xFF);
6982         str[1] = (spirom_ver & 0xFF00) >> 8;
6983         str[2] = (spirom_ver & 0xFF0000) >> 16;
6984         str[3] = (spirom_ver & 0xFF000000) >> 24;
6985         str[4] = '\0';
6986         *len -= 5;
6987         return 0;
6988 }
6989
6990 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6991 {
6992         u16 val, cnt;
6993
6994         bnx2x_cl45_read(bp, phy,
6995                         MDIO_PMA_DEVAD,
6996                         MDIO_PMA_REG_7101_RESET, &val);
6997
6998         for (cnt = 0; cnt < 10; cnt++) {
6999                 msleep(50);
7000                 /* Writes a self-clearing reset */
7001                 bnx2x_cl45_write(bp, phy,
7002                                  MDIO_PMA_DEVAD,
7003                                  MDIO_PMA_REG_7101_RESET,
7004                                  (val | (1<<15)));
7005                 /* Wait for clear */
7006                 bnx2x_cl45_read(bp, phy,
7007                                 MDIO_PMA_DEVAD,
7008                                 MDIO_PMA_REG_7101_RESET, &val);
7009
7010                 if ((val & (1<<15)) == 0)
7011                         break;
7012         }
7013 }
7014
7015 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
7016                                 struct link_params *params) {
7017         /* Low power mode is controlled by GPIO 2 */
7018         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
7019                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7020         /* The PHY reset is controlled by GPIO 1 */
7021         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
7022                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
7023 }
7024
7025 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
7026                                     struct link_params *params, u8 mode)
7027 {
7028         u16 val = 0;
7029         struct bnx2x *bp = params->bp;
7030         switch (mode) {
7031         case LED_MODE_FRONT_PANEL_OFF:
7032         case LED_MODE_OFF:
7033                 val = 2;
7034                 break;
7035         case LED_MODE_ON:
7036                 val = 1;
7037                 break;
7038         case LED_MODE_OPER:
7039                 val = 0;
7040                 break;
7041         }
7042         bnx2x_cl45_write(bp, phy,
7043                          MDIO_PMA_DEVAD,
7044                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
7045                          val);
7046 }
7047
7048 /******************************************************************/
7049 /*                      STATIC PHY DECLARATION                    */
7050 /******************************************************************/
7051
7052 static struct bnx2x_phy phy_null = {
7053         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
7054         .addr           = 0,
7055         .def_md_devad   = 0,
7056         .flags          = FLAGS_INIT_XGXS_FIRST,
7057         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7058         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7059         .mdio_ctrl      = 0,
7060         .supported      = 0,
7061         .media_type     = ETH_PHY_NOT_PRESENT,
7062         .ver_addr       = 0,
7063         .req_flow_ctrl  = 0,
7064         .req_line_speed = 0,
7065         .speed_cap_mask = 0,
7066         .req_duplex     = 0,
7067         .rsrv           = 0,
7068         .config_init    = (config_init_t)NULL,
7069         .read_status    = (read_status_t)NULL,
7070         .link_reset     = (link_reset_t)NULL,
7071         .config_loopback = (config_loopback_t)NULL,
7072         .format_fw_ver  = (format_fw_ver_t)NULL,
7073         .hw_reset       = (hw_reset_t)NULL,
7074         .set_link_led   = (set_link_led_t)NULL,
7075         .phy_specific_func = (phy_specific_func_t)NULL
7076 };
7077
7078 static struct bnx2x_phy phy_serdes = {
7079         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
7080         .addr           = 0xff,
7081         .def_md_devad   = 0,
7082         .flags          = 0,
7083         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7084         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7085         .mdio_ctrl      = 0,
7086         .supported      = (SUPPORTED_10baseT_Half |
7087                            SUPPORTED_10baseT_Full |
7088                            SUPPORTED_100baseT_Half |
7089                            SUPPORTED_100baseT_Full |
7090                            SUPPORTED_1000baseT_Full |
7091                            SUPPORTED_2500baseX_Full |
7092                            SUPPORTED_TP |
7093                            SUPPORTED_Autoneg |
7094                            SUPPORTED_Pause |
7095                            SUPPORTED_Asym_Pause),
7096         .media_type     = ETH_PHY_BASE_T,
7097         .ver_addr       = 0,
7098         .req_flow_ctrl  = 0,
7099         .req_line_speed = 0,
7100         .speed_cap_mask = 0,
7101         .req_duplex     = 0,
7102         .rsrv           = 0,
7103         .config_init    = (config_init_t)bnx2x_init_serdes,
7104         .read_status    = (read_status_t)bnx2x_link_settings_status,
7105         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7106         .config_loopback = (config_loopback_t)NULL,
7107         .format_fw_ver  = (format_fw_ver_t)NULL,
7108         .hw_reset       = (hw_reset_t)NULL,
7109         .set_link_led   = (set_link_led_t)NULL,
7110         .phy_specific_func = (phy_specific_func_t)NULL
7111 };
7112
7113 static struct bnx2x_phy phy_xgxs = {
7114         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
7115         .addr           = 0xff,
7116         .def_md_devad   = 0,
7117         .flags          = 0,
7118         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7119         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7120         .mdio_ctrl      = 0,
7121         .supported      = (SUPPORTED_10baseT_Half |
7122                            SUPPORTED_10baseT_Full |
7123                            SUPPORTED_100baseT_Half |
7124                            SUPPORTED_100baseT_Full |
7125                            SUPPORTED_1000baseT_Full |
7126                            SUPPORTED_2500baseX_Full |
7127                            SUPPORTED_10000baseT_Full |
7128                            SUPPORTED_FIBRE |
7129                            SUPPORTED_Autoneg |
7130                            SUPPORTED_Pause |
7131                            SUPPORTED_Asym_Pause),
7132         .media_type     = ETH_PHY_CX4,
7133         .ver_addr       = 0,
7134         .req_flow_ctrl  = 0,
7135         .req_line_speed = 0,
7136         .speed_cap_mask = 0,
7137         .req_duplex     = 0,
7138         .rsrv           = 0,
7139         .config_init    = (config_init_t)bnx2x_init_xgxs,
7140         .read_status    = (read_status_t)bnx2x_link_settings_status,
7141         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
7142         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
7143         .format_fw_ver  = (format_fw_ver_t)NULL,
7144         .hw_reset       = (hw_reset_t)NULL,
7145         .set_link_led   = (set_link_led_t)NULL,
7146         .phy_specific_func = (phy_specific_func_t)NULL
7147 };
7148
7149 static struct bnx2x_phy phy_7101 = {
7150         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7151         .addr           = 0xff,
7152         .def_md_devad   = 0,
7153         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7154         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7155         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7156         .mdio_ctrl      = 0,
7157         .supported      = (SUPPORTED_10000baseT_Full |
7158                            SUPPORTED_TP |
7159                            SUPPORTED_Autoneg |
7160                            SUPPORTED_Pause |
7161                            SUPPORTED_Asym_Pause),
7162         .media_type     = ETH_PHY_BASE_T,
7163         .ver_addr       = 0,
7164         .req_flow_ctrl  = 0,
7165         .req_line_speed = 0,
7166         .speed_cap_mask = 0,
7167         .req_duplex     = 0,
7168         .rsrv           = 0,
7169         .config_init    = (config_init_t)bnx2x_7101_config_init,
7170         .read_status    = (read_status_t)bnx2x_7101_read_status,
7171         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7172         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
7173         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
7174         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
7175         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
7176         .phy_specific_func = (phy_specific_func_t)NULL
7177 };
7178 static struct bnx2x_phy phy_8073 = {
7179         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
7180         .addr           = 0xff,
7181         .def_md_devad   = 0,
7182         .flags          = FLAGS_HW_LOCK_REQUIRED,
7183         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7184         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7185         .mdio_ctrl      = 0,
7186         .supported      = (SUPPORTED_10000baseT_Full |
7187                            SUPPORTED_2500baseX_Full |
7188                            SUPPORTED_1000baseT_Full |
7189                            SUPPORTED_FIBRE |
7190                            SUPPORTED_Autoneg |
7191                            SUPPORTED_Pause |
7192                            SUPPORTED_Asym_Pause),
7193         .media_type     = ETH_PHY_KR,
7194         .ver_addr       = 0,
7195         .req_flow_ctrl  = 0,
7196         .req_line_speed = 0,
7197         .speed_cap_mask = 0,
7198         .req_duplex     = 0,
7199         .rsrv           = 0,
7200         .config_init    = (config_init_t)bnx2x_8073_config_init,
7201         .read_status    = (read_status_t)bnx2x_8073_read_status,
7202         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
7203         .config_loopback = (config_loopback_t)NULL,
7204         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7205         .hw_reset       = (hw_reset_t)NULL,
7206         .set_link_led   = (set_link_led_t)NULL,
7207         .phy_specific_func = (phy_specific_func_t)NULL
7208 };
7209 static struct bnx2x_phy phy_8705 = {
7210         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
7211         .addr           = 0xff,
7212         .def_md_devad   = 0,
7213         .flags          = FLAGS_INIT_XGXS_FIRST,
7214         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7215         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7216         .mdio_ctrl      = 0,
7217         .supported      = (SUPPORTED_10000baseT_Full |
7218                            SUPPORTED_FIBRE |
7219                            SUPPORTED_Pause |
7220                            SUPPORTED_Asym_Pause),
7221         .media_type     = ETH_PHY_XFP_FIBER,
7222         .ver_addr       = 0,
7223         .req_flow_ctrl  = 0,
7224         .req_line_speed = 0,
7225         .speed_cap_mask = 0,
7226         .req_duplex     = 0,
7227         .rsrv           = 0,
7228         .config_init    = (config_init_t)bnx2x_8705_config_init,
7229         .read_status    = (read_status_t)bnx2x_8705_read_status,
7230         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7231         .config_loopback = (config_loopback_t)NULL,
7232         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
7233         .hw_reset       = (hw_reset_t)NULL,
7234         .set_link_led   = (set_link_led_t)NULL,
7235         .phy_specific_func = (phy_specific_func_t)NULL
7236 };
7237 static struct bnx2x_phy phy_8706 = {
7238         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7239         .addr           = 0xff,
7240         .def_md_devad   = 0,
7241         .flags          = FLAGS_INIT_XGXS_FIRST,
7242         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7243         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7244         .mdio_ctrl      = 0,
7245         .supported      = (SUPPORTED_10000baseT_Full |
7246                            SUPPORTED_1000baseT_Full |
7247                            SUPPORTED_FIBRE |
7248                            SUPPORTED_Pause |
7249                            SUPPORTED_Asym_Pause),
7250         .media_type     = ETH_PHY_SFP_FIBER,
7251         .ver_addr       = 0,
7252         .req_flow_ctrl  = 0,
7253         .req_line_speed = 0,
7254         .speed_cap_mask = 0,
7255         .req_duplex     = 0,
7256         .rsrv           = 0,
7257         .config_init    = (config_init_t)bnx2x_8706_config_init,
7258         .read_status    = (read_status_t)bnx2x_8706_read_status,
7259         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
7260         .config_loopback = (config_loopback_t)NULL,
7261         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7262         .hw_reset       = (hw_reset_t)NULL,
7263         .set_link_led   = (set_link_led_t)NULL,
7264         .phy_specific_func = (phy_specific_func_t)NULL
7265 };
7266
7267 static struct bnx2x_phy phy_8726 = {
7268         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7269         .addr           = 0xff,
7270         .def_md_devad   = 0,
7271         .flags          = (FLAGS_HW_LOCK_REQUIRED |
7272                            FLAGS_INIT_XGXS_FIRST),
7273         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7274         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7275         .mdio_ctrl      = 0,
7276         .supported      = (SUPPORTED_10000baseT_Full |
7277                            SUPPORTED_1000baseT_Full |
7278                            SUPPORTED_Autoneg |
7279                            SUPPORTED_FIBRE |
7280                            SUPPORTED_Pause |
7281                            SUPPORTED_Asym_Pause),
7282         .media_type     = ETH_PHY_NOT_PRESENT,
7283         .ver_addr       = 0,
7284         .req_flow_ctrl  = 0,
7285         .req_line_speed = 0,
7286         .speed_cap_mask = 0,
7287         .req_duplex     = 0,
7288         .rsrv           = 0,
7289         .config_init    = (config_init_t)bnx2x_8726_config_init,
7290         .read_status    = (read_status_t)bnx2x_8726_read_status,
7291         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
7292         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7293         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7294         .hw_reset       = (hw_reset_t)NULL,
7295         .set_link_led   = (set_link_led_t)NULL,
7296         .phy_specific_func = (phy_specific_func_t)NULL
7297 };
7298
7299 static struct bnx2x_phy phy_8727 = {
7300         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7301         .addr           = 0xff,
7302         .def_md_devad   = 0,
7303         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
7304         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7305         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7306         .mdio_ctrl      = 0,
7307         .supported      = (SUPPORTED_10000baseT_Full |
7308                            SUPPORTED_1000baseT_Full |
7309                            SUPPORTED_FIBRE |
7310                            SUPPORTED_Pause |
7311                            SUPPORTED_Asym_Pause),
7312         .media_type     = ETH_PHY_NOT_PRESENT,
7313         .ver_addr       = 0,
7314         .req_flow_ctrl  = 0,
7315         .req_line_speed = 0,
7316         .speed_cap_mask = 0,
7317         .req_duplex     = 0,
7318         .rsrv           = 0,
7319         .config_init    = (config_init_t)bnx2x_8727_config_init,
7320         .read_status    = (read_status_t)bnx2x_8727_read_status,
7321         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
7322         .config_loopback = (config_loopback_t)NULL,
7323         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
7324         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
7325         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
7326         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
7327 };
7328 static struct bnx2x_phy phy_8481 = {
7329         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7330         .addr           = 0xff,
7331         .def_md_devad   = 0,
7332         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7333                           FLAGS_REARM_LATCH_SIGNAL,
7334         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7335         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7336         .mdio_ctrl      = 0,
7337         .supported      = (SUPPORTED_10baseT_Half |
7338                            SUPPORTED_10baseT_Full |
7339                            SUPPORTED_100baseT_Half |
7340                            SUPPORTED_100baseT_Full |
7341                            SUPPORTED_1000baseT_Full |
7342                            SUPPORTED_10000baseT_Full |
7343                            SUPPORTED_TP |
7344                            SUPPORTED_Autoneg |
7345                            SUPPORTED_Pause |
7346                            SUPPORTED_Asym_Pause),
7347         .media_type     = ETH_PHY_BASE_T,
7348         .ver_addr       = 0,
7349         .req_flow_ctrl  = 0,
7350         .req_line_speed = 0,
7351         .speed_cap_mask = 0,
7352         .req_duplex     = 0,
7353         .rsrv           = 0,
7354         .config_init    = (config_init_t)bnx2x_8481_config_init,
7355         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7356         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
7357         .config_loopback = (config_loopback_t)NULL,
7358         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7359         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
7360         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7361         .phy_specific_func = (phy_specific_func_t)NULL
7362 };
7363
7364 static struct bnx2x_phy phy_84823 = {
7365         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7366         .addr           = 0xff,
7367         .def_md_devad   = 0,
7368         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7369                           FLAGS_REARM_LATCH_SIGNAL,
7370         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7371         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7372         .mdio_ctrl      = 0,
7373         .supported      = (SUPPORTED_10baseT_Half |
7374                            SUPPORTED_10baseT_Full |
7375                            SUPPORTED_100baseT_Half |
7376                            SUPPORTED_100baseT_Full |
7377                            SUPPORTED_1000baseT_Full |
7378                            SUPPORTED_10000baseT_Full |
7379                            SUPPORTED_TP |
7380                            SUPPORTED_Autoneg |
7381                            SUPPORTED_Pause |
7382                            SUPPORTED_Asym_Pause),
7383         .media_type     = ETH_PHY_BASE_T,
7384         .ver_addr       = 0,
7385         .req_flow_ctrl  = 0,
7386         .req_line_speed = 0,
7387         .speed_cap_mask = 0,
7388         .req_duplex     = 0,
7389         .rsrv           = 0,
7390         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7391         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7392         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7393         .config_loopback = (config_loopback_t)NULL,
7394         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7395         .hw_reset       = (hw_reset_t)NULL,
7396         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7397         .phy_specific_func = (phy_specific_func_t)NULL
7398 };
7399
7400 static struct bnx2x_phy phy_84833 = {
7401         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7402         .addr           = 0xff,
7403         .def_md_devad   = 0,
7404         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
7405                             FLAGS_REARM_LATCH_SIGNAL,
7406         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7407         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7408         .mdio_ctrl      = 0,
7409         .supported      = (SUPPORTED_10baseT_Half |
7410                            SUPPORTED_10baseT_Full |
7411                            SUPPORTED_100baseT_Half |
7412                            SUPPORTED_100baseT_Full |
7413                            SUPPORTED_1000baseT_Full |
7414                            SUPPORTED_10000baseT_Full |
7415                            SUPPORTED_TP |
7416                            SUPPORTED_Autoneg |
7417                            SUPPORTED_Pause |
7418                            SUPPORTED_Asym_Pause),
7419         .media_type     = ETH_PHY_BASE_T,
7420         .ver_addr       = 0,
7421         .req_flow_ctrl  = 0,
7422         .req_line_speed = 0,
7423         .speed_cap_mask = 0,
7424         .req_duplex     = 0,
7425         .rsrv           = 0,
7426         .config_init    = (config_init_t)bnx2x_848x3_config_init,
7427         .read_status    = (read_status_t)bnx2x_848xx_read_status,
7428         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
7429         .config_loopback = (config_loopback_t)NULL,
7430         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
7431         .hw_reset       = (hw_reset_t)NULL,
7432         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
7433         .phy_specific_func = (phy_specific_func_t)NULL
7434 };
7435
7436 /*****************************************************************/
7437 /*                                                               */
7438 /* Populate the phy according. Main function: bnx2x_populate_phy   */
7439 /*                                                               */
7440 /*****************************************************************/
7441
7442 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7443                                      struct bnx2x_phy *phy, u8 port,
7444                                      u8 phy_index)
7445 {
7446         /* Get the 4 lanes xgxs config rx and tx */
7447         u32 rx = 0, tx = 0, i;
7448         for (i = 0; i < 2; i++) {
7449                 /*
7450                  * INT_PHY and EXT_PHY1 share the same value location in the
7451                  * shmem. When num_phys is greater than 1, than this value
7452                  * applies only to EXT_PHY1
7453                  */
7454                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7455                         rx = REG_RD(bp, shmem_base +
7456                                     offsetof(struct shmem_region,
7457                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7458
7459                         tx = REG_RD(bp, shmem_base +
7460                                     offsetof(struct shmem_region,
7461                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7462                 } else {
7463                         rx = REG_RD(bp, shmem_base +
7464                                     offsetof(struct shmem_region,
7465                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7466
7467                         tx = REG_RD(bp, shmem_base +
7468                                     offsetof(struct shmem_region,
7469                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7470                 }
7471
7472                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7473                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7474
7475                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7476                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7477         }
7478 }
7479
7480 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7481                                     u8 phy_index, u8 port)
7482 {
7483         u32 ext_phy_config = 0;
7484         switch (phy_index) {
7485         case EXT_PHY1:
7486                 ext_phy_config = REG_RD(bp, shmem_base +
7487                                               offsetof(struct shmem_region,
7488                         dev_info.port_hw_config[port].external_phy_config));
7489                 break;
7490         case EXT_PHY2:
7491                 ext_phy_config = REG_RD(bp, shmem_base +
7492                                               offsetof(struct shmem_region,
7493                         dev_info.port_hw_config[port].external_phy_config2));
7494                 break;
7495         default:
7496                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7497                 return -EINVAL;
7498         }
7499
7500         return ext_phy_config;
7501 }
7502 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7503                                   struct bnx2x_phy *phy)
7504 {
7505         u32 phy_addr;
7506         u32 chip_id;
7507         u32 switch_cfg = (REG_RD(bp, shmem_base +
7508                                        offsetof(struct shmem_region,
7509                         dev_info.port_feature_config[port].link_config)) &
7510                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
7511         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7512         switch (switch_cfg) {
7513         case SWITCH_CFG_1G:
7514                 phy_addr = REG_RD(bp,
7515                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
7516                                         port * 0x10);
7517                 *phy = phy_serdes;
7518                 break;
7519         case SWITCH_CFG_10G:
7520                 phy_addr = REG_RD(bp,
7521                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
7522                                         port * 0x18);
7523                 *phy = phy_xgxs;
7524                 break;
7525         default:
7526                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7527                 return -EINVAL;
7528         }
7529         phy->addr = (u8)phy_addr;
7530         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7531                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7532                                             port);
7533         if (CHIP_IS_E2(bp))
7534                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7535         else
7536                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7537
7538         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7539                    port, phy->addr, phy->mdio_ctrl);
7540
7541         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7542         return 0;
7543 }
7544
7545 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
7546                                   u8 phy_index,
7547                                   u32 shmem_base,
7548                                   u32 shmem2_base,
7549                                   u8 port,
7550                                   struct bnx2x_phy *phy)
7551 {
7552         u32 ext_phy_config, phy_type, config2;
7553         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7554         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7555                                                   phy_index, port);
7556         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7557         /* Select the phy type */
7558         switch (phy_type) {
7559         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7560                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7561                 *phy = phy_8073;
7562                 break;
7563         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7564                 *phy = phy_8705;
7565                 break;
7566         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7567                 *phy = phy_8706;
7568                 break;
7569         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7570                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7571                 *phy = phy_8726;
7572                 break;
7573         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7574                 /* BCM8727_NOC => BCM8727 no over current */
7575                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7576                 *phy = phy_8727;
7577                 phy->flags |= FLAGS_NOC;
7578                 break;
7579         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7580         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7581                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7582                 *phy = phy_8727;
7583                 break;
7584         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7585                 *phy = phy_8481;
7586                 break;
7587         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7588                 *phy = phy_84823;
7589                 break;
7590         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7591                 *phy = phy_84833;
7592                 break;
7593         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7594                 *phy = phy_7101;
7595                 break;
7596         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7597                 *phy = phy_null;
7598                 return -EINVAL;
7599         default:
7600                 *phy = phy_null;
7601                 return 0;
7602         }
7603
7604         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7605         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7606
7607         /*
7608          * The shmem address of the phy version is located on different
7609          * structures. In case this structure is too old, do not set
7610          * the address
7611          */
7612         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7613                                         dev_info.shared_hw_config.config2));
7614         if (phy_index == EXT_PHY1) {
7615                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7616                                 port_mb[port].ext_phy_fw_version);
7617
7618                 /* Check specific mdc mdio settings */
7619                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7620                         mdc_mdio_access = config2 &
7621                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7622         } else {
7623                 u32 size = REG_RD(bp, shmem2_base);
7624
7625                 if (size >
7626                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7627                         phy->ver_addr = shmem2_base +
7628                             offsetof(struct shmem2_region,
7629                                      ext_phy_fw_version2[port]);
7630                 }
7631                 /* Check specific mdc mdio settings */
7632                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7633                         mdc_mdio_access = (config2 &
7634                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7635                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7636                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7637         }
7638         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7639
7640         /*
7641          * In case mdc/mdio_access of the external phy is different than the
7642          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7643          * to prevent one port interfere with another port's CL45 operations.
7644          */
7645         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7646                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7647         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7648                    phy_type, port, phy_index);
7649         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
7650                    phy->addr, phy->mdio_ctrl);
7651         return 0;
7652 }
7653
7654 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7655                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7656 {
7657         int status = 0;
7658         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7659         if (phy_index == INT_PHY)
7660                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7661         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7662                                         port, phy);
7663         return status;
7664 }
7665
7666 static void bnx2x_phy_def_cfg(struct link_params *params,
7667                               struct bnx2x_phy *phy,
7668                               u8 phy_index)
7669 {
7670         struct bnx2x *bp = params->bp;
7671         u32 link_config;
7672         /* Populate the default phy configuration for MF mode */
7673         if (phy_index == EXT_PHY2) {
7674                 link_config = REG_RD(bp, params->shmem_base +
7675                                      offsetof(struct shmem_region, dev_info.
7676                         port_feature_config[params->port].link_config2));
7677                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7678                                              offsetof(struct shmem_region,
7679                                                       dev_info.
7680                         port_hw_config[params->port].speed_capability_mask2));
7681         } else {
7682                 link_config = REG_RD(bp, params->shmem_base +
7683                                      offsetof(struct shmem_region, dev_info.
7684                                 port_feature_config[params->port].link_config));
7685                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7686                                              offsetof(struct shmem_region,
7687                                                       dev_info.
7688                         port_hw_config[params->port].speed_capability_mask));
7689         }
7690         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7691                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7692
7693         phy->req_duplex = DUPLEX_FULL;
7694         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
7695         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7696                 phy->req_duplex = DUPLEX_HALF;
7697         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7698                 phy->req_line_speed = SPEED_10;
7699                 break;
7700         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7701                 phy->req_duplex = DUPLEX_HALF;
7702         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7703                 phy->req_line_speed = SPEED_100;
7704                 break;
7705         case PORT_FEATURE_LINK_SPEED_1G:
7706                 phy->req_line_speed = SPEED_1000;
7707                 break;
7708         case PORT_FEATURE_LINK_SPEED_2_5G:
7709                 phy->req_line_speed = SPEED_2500;
7710                 break;
7711         case PORT_FEATURE_LINK_SPEED_10G_CX4:
7712                 phy->req_line_speed = SPEED_10000;
7713                 break;
7714         default:
7715                 phy->req_line_speed = SPEED_AUTO_NEG;
7716                 break;
7717         }
7718
7719         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
7720         case PORT_FEATURE_FLOW_CONTROL_AUTO:
7721                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7722                 break;
7723         case PORT_FEATURE_FLOW_CONTROL_TX:
7724                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7725                 break;
7726         case PORT_FEATURE_FLOW_CONTROL_RX:
7727                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7728                 break;
7729         case PORT_FEATURE_FLOW_CONTROL_BOTH:
7730                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7731                 break;
7732         default:
7733                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7734                 break;
7735         }
7736 }
7737
7738 u32 bnx2x_phy_selection(struct link_params *params)
7739 {
7740         u32 phy_config_swapped, prio_cfg;
7741         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7742
7743         phy_config_swapped = params->multi_phy_config &
7744                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7745
7746         prio_cfg = params->multi_phy_config &
7747                         PORT_HW_CFG_PHY_SELECTION_MASK;
7748
7749         if (phy_config_swapped) {
7750                 switch (prio_cfg) {
7751                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7752                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7753                      break;
7754                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7755                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7756                      break;
7757                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7758                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7759                      break;
7760                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7761                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7762                      break;
7763                 }
7764         } else
7765                 return_cfg = prio_cfg;
7766
7767         return return_cfg;
7768 }
7769
7770
7771 int bnx2x_phy_probe(struct link_params *params)
7772 {
7773         u8 phy_index, actual_phy_idx, link_cfg_idx;
7774         u32 phy_config_swapped, sync_offset, media_types;
7775         struct bnx2x *bp = params->bp;
7776         struct bnx2x_phy *phy;
7777         params->num_phys = 0;
7778         DP(NETIF_MSG_LINK, "Begin phy probe\n");
7779         phy_config_swapped = params->multi_phy_config &
7780                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7781
7782         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7783               phy_index++) {
7784                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7785                 actual_phy_idx = phy_index;
7786                 if (phy_config_swapped) {
7787                         if (phy_index == EXT_PHY1)
7788                                 actual_phy_idx = EXT_PHY2;
7789                         else if (phy_index == EXT_PHY2)
7790                                 actual_phy_idx = EXT_PHY1;
7791                 }
7792                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7793                                " actual_phy_idx %x\n", phy_config_swapped,
7794                            phy_index, actual_phy_idx);
7795                 phy = &params->phy[actual_phy_idx];
7796                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7797                                        params->shmem2_base, params->port,
7798                                        phy) != 0) {
7799                         params->num_phys = 0;
7800                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7801                                    phy_index);
7802                         for (phy_index = INT_PHY;
7803                               phy_index < MAX_PHYS;
7804                               phy_index++)
7805                                 *phy = phy_null;
7806                         return -EINVAL;
7807                 }
7808                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7809                         break;
7810
7811                 sync_offset = params->shmem_base +
7812                         offsetof(struct shmem_region,
7813                         dev_info.port_hw_config[params->port].media_type);
7814                 media_types = REG_RD(bp, sync_offset);
7815
7816                 /*
7817                  * Update media type for non-PMF sync only for the first time
7818                  * In case the media type changes afterwards, it will be updated
7819                  * using the update_status function
7820                  */
7821                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7822                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7823                                      actual_phy_idx))) == 0) {
7824                         media_types |= ((phy->media_type &
7825                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7826                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7827                                  actual_phy_idx));
7828                 }
7829                 REG_WR(bp, sync_offset, media_types);
7830
7831                 bnx2x_phy_def_cfg(params, phy, phy_index);
7832                 params->num_phys++;
7833         }
7834
7835         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7836         return 0;
7837 }
7838
7839 void bnx2x_init_bmac_loopback(struct link_params *params,
7840                               struct link_vars *vars)
7841 {
7842         struct bnx2x *bp = params->bp;
7843                 vars->link_up = 1;
7844                 vars->line_speed = SPEED_10000;
7845                 vars->duplex = DUPLEX_FULL;
7846                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7847                 vars->mac_type = MAC_TYPE_BMAC;
7848
7849                 vars->phy_flags = PHY_XGXS_FLAG;
7850
7851                 bnx2x_xgxs_deassert(params);
7852
7853                 /* set bmac loopback */
7854                 bnx2x_bmac_enable(params, vars, 1);
7855
7856                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7857 }
7858
7859 void bnx2x_init_emac_loopback(struct link_params *params,
7860                               struct link_vars *vars)
7861 {
7862         struct bnx2x *bp = params->bp;
7863                 vars->link_up = 1;
7864                 vars->line_speed = SPEED_1000;
7865                 vars->duplex = DUPLEX_FULL;
7866                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7867                 vars->mac_type = MAC_TYPE_EMAC;
7868
7869                 vars->phy_flags = PHY_XGXS_FLAG;
7870
7871                 bnx2x_xgxs_deassert(params);
7872                 /* set bmac loopback */
7873                 bnx2x_emac_enable(params, vars, 1);
7874                 bnx2x_emac_program(params, vars);
7875                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7876 }
7877
7878 void bnx2x_init_xgxs_loopback(struct link_params *params,
7879                               struct link_vars *vars)
7880 {
7881         struct bnx2x *bp = params->bp;
7882                 vars->link_up = 1;
7883                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7884                 vars->duplex = DUPLEX_FULL;
7885         if (params->req_line_speed[0] == SPEED_1000)
7886                         vars->line_speed = SPEED_1000;
7887         else
7888                         vars->line_speed = SPEED_10000;
7889
7890
7891         bnx2x_xgxs_deassert(params);
7892         bnx2x_link_initialize(params, vars);
7893
7894         if (params->req_line_speed[0] == SPEED_1000) {
7895                 bnx2x_emac_program(params, vars);
7896                 bnx2x_emac_enable(params, vars, 0);
7897
7898         } else
7899                 bnx2x_bmac_enable(params, vars, 0);
7900
7901
7902                 if (params->loopback_mode == LOOPBACK_XGXS) {
7903                         /* set 10G XGXS loopback */
7904                         params->phy[INT_PHY].config_loopback(
7905                                 &params->phy[INT_PHY],
7906                                 params);
7907
7908                 } else {
7909                         /* set external phy loopback */
7910                         u8 phy_index;
7911                         for (phy_index = EXT_PHY1;
7912                               phy_index < params->num_phys; phy_index++) {
7913                                 if (params->phy[phy_index].config_loopback)
7914                                         params->phy[phy_index].config_loopback(
7915                                                 &params->phy[phy_index],
7916                                                 params);
7917                         }
7918                 }
7919                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7920
7921         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
7922 }
7923
7924 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7925 {
7926         struct bnx2x *bp = params->bp;
7927         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7928         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7929                    params->req_line_speed[0], params->req_flow_ctrl[0]);
7930         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7931                    params->req_line_speed[1], params->req_flow_ctrl[1]);
7932         vars->link_status = 0;
7933         vars->phy_link_up = 0;
7934         vars->link_up = 0;
7935         vars->line_speed = 0;
7936         vars->duplex = DUPLEX_FULL;
7937         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7938         vars->mac_type = MAC_TYPE_NONE;
7939         vars->phy_flags = 0;
7940
7941         /* disable attentions */
7942         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7943                        (NIG_MASK_XGXS0_LINK_STATUS |
7944                         NIG_MASK_XGXS0_LINK10G |
7945                         NIG_MASK_SERDES0_LINK_STATUS |
7946                         NIG_MASK_MI_INT));
7947
7948         bnx2x_emac_init(params, vars);
7949
7950         if (params->num_phys == 0) {
7951                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7952                 return -EINVAL;
7953         }
7954         set_phy_vars(params, vars);
7955
7956         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7957         switch (params->loopback_mode) {
7958         case LOOPBACK_BMAC:
7959                 bnx2x_init_bmac_loopback(params, vars);
7960                 break;
7961         case LOOPBACK_EMAC:
7962                 bnx2x_init_emac_loopback(params, vars);
7963                 break;
7964         case LOOPBACK_XGXS:
7965         case LOOPBACK_EXT_PHY:
7966                 bnx2x_init_xgxs_loopback(params, vars);
7967                 break;
7968         default:
7969                 /* No loopback */
7970                 if (params->switch_cfg == SWITCH_CFG_10G)
7971                         bnx2x_xgxs_deassert(params);
7972                 else
7973                         bnx2x_serdes_deassert(bp, params->port);
7974
7975                 bnx2x_link_initialize(params, vars);
7976                 msleep(30);
7977                 bnx2x_link_int_enable(params);
7978                 break;
7979         }
7980         return 0;
7981 }
7982
7983 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7984                      u8 reset_ext_phy)
7985 {
7986         struct bnx2x *bp = params->bp;
7987         u8 phy_index, port = params->port, clear_latch_ind = 0;
7988         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7989         /* disable attentions */
7990         vars->link_status = 0;
7991         bnx2x_update_mng(params, vars->link_status);
7992         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7993                        (NIG_MASK_XGXS0_LINK_STATUS |
7994                         NIG_MASK_XGXS0_LINK10G |
7995                         NIG_MASK_SERDES0_LINK_STATUS |
7996                         NIG_MASK_MI_INT));
7997
7998         /* activate nig drain */
7999         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
8000
8001         /* disable nig egress interface */
8002         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8003         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8004
8005         /* Stop BigMac rx */
8006         bnx2x_bmac_rx_disable(bp, port);
8007
8008         /* disable emac */
8009         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
8010
8011         msleep(10);
8012         /* The PHY reset is controlled by GPIO 1
8013          * Hold it as vars low
8014          */
8015          /* clear link led */
8016         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
8017
8018         if (reset_ext_phy) {
8019                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
8020                       phy_index++) {
8021                         if (params->phy[phy_index].link_reset)
8022                                 params->phy[phy_index].link_reset(
8023                                         &params->phy[phy_index],
8024                                         params);
8025                         if (params->phy[phy_index].flags &
8026                             FLAGS_REARM_LATCH_SIGNAL)
8027                                 clear_latch_ind = 1;
8028                 }
8029         }
8030
8031         if (clear_latch_ind) {
8032                 /* Clear latching indication */
8033                 bnx2x_rearm_latch_signal(bp, port, 0);
8034                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
8035                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
8036         }
8037         if (params->phy[INT_PHY].link_reset)
8038                 params->phy[INT_PHY].link_reset(
8039                         &params->phy[INT_PHY], params);
8040         /* reset BigMac */
8041         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8042                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
8043
8044         /* disable nig ingress interface */
8045         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
8046         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
8047         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
8048         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
8049         vars->link_up = 0;
8050         return 0;
8051 }
8052
8053 /****************************************************************************/
8054 /*                              Common function                             */
8055 /****************************************************************************/
8056 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
8057                                       u32 shmem_base_path[],
8058                                       u32 shmem2_base_path[], u8 phy_index,
8059                                       u32 chip_id)
8060 {
8061         struct bnx2x_phy phy[PORT_MAX];
8062         struct bnx2x_phy *phy_blk[PORT_MAX];
8063         u16 val;
8064         s8 port = 0;
8065         s8 port_of_path = 0;
8066         u32 swap_val, swap_override;
8067         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
8068         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
8069         port ^= (swap_val && swap_override);
8070         bnx2x_ext_phy_hw_reset(bp, port);
8071         /* PART1 - Reset both phys */
8072         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8073                 u32 shmem_base, shmem2_base;
8074                 /* In E2, same phy is using for port0 of the two paths */
8075                 if (CHIP_IS_E2(bp)) {
8076                         shmem_base = shmem_base_path[port];
8077                         shmem2_base = shmem2_base_path[port];
8078                         port_of_path = 0;
8079                 } else {
8080                         shmem_base = shmem_base_path[0];
8081                         shmem2_base = shmem2_base_path[0];
8082                         port_of_path = port;
8083                 }
8084
8085                 /* Extract the ext phy address for the port */
8086                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8087                                        port_of_path, &phy[port]) !=
8088                     0) {
8089                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
8090                         return -EINVAL;
8091                 }
8092                 /* disable attentions */
8093                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8094                                port_of_path*4,
8095                                (NIG_MASK_XGXS0_LINK_STATUS |
8096                                 NIG_MASK_XGXS0_LINK10G |
8097                                 NIG_MASK_SERDES0_LINK_STATUS |
8098                                 NIG_MASK_MI_INT));
8099
8100                 /* Need to take the phy out of low power mode in order
8101                         to write to access its registers */
8102                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8103                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8104                                port);
8105
8106                 /* Reset the phy */
8107                 bnx2x_cl45_write(bp, &phy[port],
8108                                  MDIO_PMA_DEVAD,
8109                                  MDIO_PMA_REG_CTRL,
8110                                  1<<15);
8111         }
8112
8113         /* Add delay of 150ms after reset */
8114         msleep(150);
8115
8116         if (phy[PORT_0].addr & 0x1) {
8117                 phy_blk[PORT_0] = &(phy[PORT_1]);
8118                 phy_blk[PORT_1] = &(phy[PORT_0]);
8119         } else {
8120                 phy_blk[PORT_0] = &(phy[PORT_0]);
8121                 phy_blk[PORT_1] = &(phy[PORT_1]);
8122         }
8123
8124         /* PART2 - Download firmware to both phys */
8125         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8126                 if (CHIP_IS_E2(bp))
8127                         port_of_path = 0;
8128                 else
8129                         port_of_path = port;
8130
8131                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8132                            phy_blk[port]->addr);
8133                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8134                                                       port_of_path))
8135                         return -EINVAL;
8136
8137                 /* Only set bit 10 = 1 (Tx power down) */
8138                 bnx2x_cl45_read(bp, phy_blk[port],
8139                                 MDIO_PMA_DEVAD,
8140                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8141
8142                 /* Phase1 of TX_POWER_DOWN reset */
8143                 bnx2x_cl45_write(bp, phy_blk[port],
8144                                  MDIO_PMA_DEVAD,
8145                                  MDIO_PMA_REG_TX_POWER_DOWN,
8146                                  (val | 1<<10));
8147         }
8148
8149         /*
8150          * Toggle Transmitter: Power down and then up with 600ms delay
8151          * between
8152          */
8153         msleep(600);
8154
8155         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
8156         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8157                 /* Phase2 of POWER_DOWN_RESET */
8158                 /* Release bit 10 (Release Tx power down) */
8159                 bnx2x_cl45_read(bp, phy_blk[port],
8160                                 MDIO_PMA_DEVAD,
8161                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8162
8163                 bnx2x_cl45_write(bp, phy_blk[port],
8164                                 MDIO_PMA_DEVAD,
8165                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
8166                 msleep(15);
8167
8168                 /* Read modify write the SPI-ROM version select register */
8169                 bnx2x_cl45_read(bp, phy_blk[port],
8170                                 MDIO_PMA_DEVAD,
8171                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
8172                 bnx2x_cl45_write(bp, phy_blk[port],
8173                                  MDIO_PMA_DEVAD,
8174                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
8175
8176                 /* set GPIO2 back to LOW */
8177                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8178                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8179         }
8180         return 0;
8181 }
8182 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
8183                                       u32 shmem_base_path[],
8184                                       u32 shmem2_base_path[], u8 phy_index,
8185                                       u32 chip_id)
8186 {
8187         u32 val;
8188         s8 port;
8189         struct bnx2x_phy phy;
8190         /* Use port1 because of the static port-swap */
8191         /* Enable the module detection interrupt */
8192         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8193         val |= ((1<<MISC_REGISTERS_GPIO_3)|
8194                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
8195         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8196
8197         bnx2x_ext_phy_hw_reset(bp, 0);
8198         msleep(5);
8199         for (port = 0; port < PORT_MAX; port++) {
8200                 u32 shmem_base, shmem2_base;
8201
8202                 /* In E2, same phy is using for port0 of the two paths */
8203                 if (CHIP_IS_E2(bp)) {
8204                         shmem_base = shmem_base_path[port];
8205                         shmem2_base = shmem2_base_path[port];
8206                 } else {
8207                         shmem_base = shmem_base_path[0];
8208                         shmem2_base = shmem2_base_path[0];
8209                 }
8210                 /* Extract the ext phy address for the port */
8211                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8212                                        port, &phy) !=
8213                     0) {
8214                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8215                         return -EINVAL;
8216                 }
8217
8218                 /* Reset phy*/
8219                 bnx2x_cl45_write(bp, &phy,
8220                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8221
8222
8223                 /* Set fault module detected LED on */
8224                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8225                                MISC_REGISTERS_GPIO_HIGH,
8226                                port);
8227         }
8228
8229         return 0;
8230 }
8231 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8232                                          u8 *io_gpio, u8 *io_port)
8233 {
8234
8235         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8236                                           offsetof(struct shmem_region,
8237                                 dev_info.port_hw_config[PORT_0].default_cfg));
8238         switch (phy_gpio_reset) {
8239         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8240                 *io_gpio = 0;
8241                 *io_port = 0;
8242                 break;
8243         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8244                 *io_gpio = 1;
8245                 *io_port = 0;
8246                 break;
8247         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8248                 *io_gpio = 2;
8249                 *io_port = 0;
8250                 break;
8251         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8252                 *io_gpio = 3;
8253                 *io_port = 0;
8254                 break;
8255         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8256                 *io_gpio = 0;
8257                 *io_port = 1;
8258                 break;
8259         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8260                 *io_gpio = 1;
8261                 *io_port = 1;
8262                 break;
8263         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8264                 *io_gpio = 2;
8265                 *io_port = 1;
8266                 break;
8267         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8268                 *io_gpio = 3;
8269                 *io_port = 1;
8270                 break;
8271         default:
8272                 /* Don't override the io_gpio and io_port */
8273                 break;
8274         }
8275 }
8276
8277 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
8278                                       u32 shmem_base_path[],
8279                                       u32 shmem2_base_path[], u8 phy_index,
8280                                       u32 chip_id)
8281 {
8282         s8 port, reset_gpio;
8283         u32 swap_val, swap_override;
8284         struct bnx2x_phy phy[PORT_MAX];
8285         struct bnx2x_phy *phy_blk[PORT_MAX];
8286         s8 port_of_path;
8287         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8288         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8289
8290         reset_gpio = MISC_REGISTERS_GPIO_1;
8291         port = 1;
8292
8293         /*
8294          * Retrieve the reset gpio/port which control the reset.
8295          * Default is GPIO1, PORT1
8296          */
8297         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8298                                      (u8 *)&reset_gpio, (u8 *)&port);
8299
8300         /* Calculate the port based on port swap */
8301         port ^= (swap_val && swap_override);
8302
8303         /* Initiate PHY reset*/
8304         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8305                        port);
8306         msleep(1);
8307         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8308                        port);
8309
8310         msleep(5);
8311
8312         /* PART1 - Reset both phys */
8313         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8314                 u32 shmem_base, shmem2_base;
8315
8316                 /* In E2, same phy is using for port0 of the two paths */
8317                 if (CHIP_IS_E2(bp)) {
8318                         shmem_base = shmem_base_path[port];
8319                         shmem2_base = shmem2_base_path[port];
8320                         port_of_path = 0;
8321                 } else {
8322                         shmem_base = shmem_base_path[0];
8323                         shmem2_base = shmem2_base_path[0];
8324                         port_of_path = port;
8325                 }
8326
8327                 /* Extract the ext phy address for the port */
8328                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8329                                        port_of_path, &phy[port]) !=
8330                                        0) {
8331                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8332                         return -EINVAL;
8333                 }
8334                 /* disable attentions */
8335                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8336                                port_of_path*4,
8337                                (NIG_MASK_XGXS0_LINK_STATUS |
8338                                 NIG_MASK_XGXS0_LINK10G |
8339                                 NIG_MASK_SERDES0_LINK_STATUS |
8340                                 NIG_MASK_MI_INT));
8341
8342
8343                 /* Reset the phy */
8344                 bnx2x_cl45_write(bp, &phy[port],
8345                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8346         }
8347
8348         /* Add delay of 150ms after reset */
8349         msleep(150);
8350         if (phy[PORT_0].addr & 0x1) {
8351                 phy_blk[PORT_0] = &(phy[PORT_1]);
8352                 phy_blk[PORT_1] = &(phy[PORT_0]);
8353         } else {
8354                 phy_blk[PORT_0] = &(phy[PORT_0]);
8355                 phy_blk[PORT_1] = &(phy[PORT_1]);
8356         }
8357         /* PART2 - Download firmware to both phys */
8358         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8359                 if (CHIP_IS_E2(bp))
8360                         port_of_path = 0;
8361                 else
8362                         port_of_path = port;
8363                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8364                            phy_blk[port]->addr);
8365                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8366                                                       port_of_path))
8367                         return -EINVAL;
8368
8369         }
8370         return 0;
8371 }
8372
8373 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8374                                      u32 shmem2_base_path[], u8 phy_index,
8375                                      u32 ext_phy_type, u32 chip_id)
8376 {
8377         int rc = 0;
8378
8379         switch (ext_phy_type) {
8380         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8381                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8382                                                 shmem2_base_path,
8383                                                 phy_index, chip_id);
8384                 break;
8385         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8386         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8387         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
8388                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8389                                                 shmem2_base_path,
8390                                                 phy_index, chip_id);
8391                 break;
8392
8393         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8394                 /*
8395                  * GPIO1 affects both ports, so there's need to pull
8396                  * it for single port alone
8397                  */
8398                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8399                                                 shmem2_base_path,
8400                                                 phy_index, chip_id);
8401                 break;
8402         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8403                 rc = -EINVAL;
8404                 break;
8405         default:
8406                 DP(NETIF_MSG_LINK,
8407                            "ext_phy 0x%x common init not required\n",
8408                            ext_phy_type);
8409                 break;
8410         }
8411
8412         if (rc != 0)
8413                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
8414                                       " Port %d\n",
8415                          0);
8416         return rc;
8417 }
8418
8419 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8420                           u32 shmem2_base_path[], u32 chip_id)
8421 {
8422         int rc = 0;
8423         u32 phy_ver;
8424         u8 phy_index;
8425         u32 ext_phy_type, ext_phy_config;
8426         DP(NETIF_MSG_LINK, "Begin common phy init\n");
8427
8428         /* Check if common init was already done */
8429         phy_ver = REG_RD(bp, shmem_base_path[0] +
8430                          offsetof(struct shmem_region,
8431                                   port_mb[PORT_0].ext_phy_fw_version));
8432         if (phy_ver) {
8433                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8434                                phy_ver);
8435                 return 0;
8436         }
8437
8438         /* Read the ext_phy_type for arbitrary port(0) */
8439         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8440               phy_index++) {
8441                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
8442                                                           shmem_base_path[0],
8443                                                           phy_index, 0);
8444                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8445                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8446                                                 shmem2_base_path,
8447                                                 phy_index, ext_phy_type,
8448                                                 chip_id);
8449         }
8450         return rc;
8451 }
8452
8453 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
8454 {
8455         u8 phy_index;
8456         struct bnx2x_phy phy;
8457         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8458               phy_index++) {
8459                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8460                                        0, &phy) != 0) {
8461                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8462                         return 0;
8463                 }
8464
8465                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8466                         return 1;
8467         }
8468         return 0;
8469 }
8470
8471 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8472                              u32 shmem_base,
8473                              u32 shmem2_base,
8474                              u8 port)
8475 {
8476         u8 phy_index, fan_failure_det_req = 0;
8477         struct bnx2x_phy phy;
8478         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8479               phy_index++) {
8480                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8481                                        port, &phy)
8482                     != 0) {
8483                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8484                         return 0;
8485                 }
8486                 fan_failure_det_req |= (phy.flags &
8487                                         FLAGS_FAN_FAILURE_DET_REQ);
8488         }
8489         return fan_failure_det_req;
8490 }
8491
8492 void bnx2x_hw_reset_phy(struct link_params *params)
8493 {
8494         u8 phy_index;
8495         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8496               phy_index++) {
8497                 if (params->phy[phy_index].hw_reset) {
8498                         params->phy[phy_index].hw_reset(
8499                                 &params->phy[phy_index],
8500                                 params);
8501                         params->phy[phy_index] = phy_null;
8502                 }
8503         }
8504 }
8505
8506 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
8507                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
8508                             u8 port)
8509 {
8510         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
8511         u32 val;
8512         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
8513
8514         {
8515                 struct bnx2x_phy phy;
8516                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8517                       phy_index++) {
8518                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
8519                                                shmem2_base, port, &phy)
8520                             != 0) {
8521                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
8522                                 return;
8523                         }
8524                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
8525                                 gpio_num = MISC_REGISTERS_GPIO_3;
8526                                 gpio_port = port;
8527                                 break;
8528                         }
8529                 }
8530         }
8531
8532         if (gpio_num == 0xff)
8533                 return;
8534
8535         /* Set GPIO3 to trigger SFP+ module insertion/removal */
8536         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
8537
8538         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8539         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8540         gpio_port ^= (swap_val && swap_override);
8541
8542         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
8543                 (gpio_num + (gpio_port << 2));
8544
8545         sync_offset = shmem_base +
8546                 offsetof(struct shmem_region,
8547                          dev_info.port_hw_config[port].aeu_int_mask);
8548         REG_WR(bp, sync_offset, vars->aeu_int_mask);
8549
8550         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
8551                        gpio_num, gpio_port, vars->aeu_int_mask);
8552
8553         if (port == 0)
8554                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8555         else
8556                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
8557
8558         /* Open appropriate AEU for interrupts */
8559         aeu_mask = REG_RD(bp, offset);
8560         aeu_mask |= vars->aeu_int_mask;
8561         REG_WR(bp, offset, aeu_mask);
8562
8563         /* Enable the GPIO to trigger interrupt */
8564         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8565         val |= 1 << (gpio_num + (gpio_port << 2));
8566         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8567 }