1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
31 /********************************************************/
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
41 #define I2C_SWITCH_WIDTH 2
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
48 /***********************************************************/
49 /* Shortcut definitions */
50 /***********************************************************/
52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
54 #define NIG_STATUS_EMAC0_MI_INT \
55 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
56 #define NIG_STATUS_XGXS0_LINK10G \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
58 #define NIG_STATUS_XGXS0_LINK_STATUS \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
62 #define NIG_STATUS_SERDES0_LINK_STATUS \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
64 #define NIG_MASK_MI_INT \
65 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
66 #define NIG_MASK_XGXS0_LINK10G \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
68 #define NIG_MASK_XGXS0_LINK_STATUS \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
70 #define NIG_MASK_SERDES0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
73 #define MDIO_AN_CL73_OR_37_COMPLETE \
74 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
75 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
77 #define XGXS_RESET_BITS \
78 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
84 #define SERDES_RESET_BITS \
85 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
90 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
91 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
92 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
93 #define AUTONEG_PARALLEL \
94 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
95 #define AUTONEG_SGMII_FIBER_AUTODET \
96 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
97 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
103 #define GP_STATUS_SPEED_MASK \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
105 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
106 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
107 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
108 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
109 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
110 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
111 #define GP_STATUS_10G_HIG \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
113 #define GP_STATUS_10G_CX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
116 #define GP_STATUS_10G_KX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
119 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
121 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
122 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
123 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
124 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
125 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
126 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
127 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
128 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
129 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
130 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
131 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
132 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
133 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
134 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
135 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
136 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB thresholds for E2*/
165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
177 /* BRB thresholds for E3A0 */
178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
191 /* BRB thresholds for E3B0 2 port mode*/
192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
208 /* Lossy +Lossless GUARANTIED == GUART */
209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
210 /* Lossless +Lossless*/
211 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
217 /* Lossless +Lossless*/
218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
226 /* BRB thresholds for E3B0 4 port mode */
227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
243 #define PFC_E3B0_4P_LB_GUART 120
245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
251 #define DCBX_INVALID_COS (0xFF)
253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
254 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
257 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
259 #define MAX_PACKET_SIZE (9700)
260 #define WC_UC_TIMEOUT 100
262 /**********************************************************/
264 /**********************************************************/
266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
267 bnx2x_cl45_write(_bp, _phy, \
268 (_phy)->def_md_devad, \
269 (_bank + (_addr & 0xf)), \
272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
273 bnx2x_cl45_read(_bp, _phy, \
274 (_phy)->def_md_devad, \
275 (_bank + (_addr & 0xf)), \
278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
280 u32 val = REG_RD(bp, reg);
283 REG_WR(bp, reg, val);
287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
289 u32 val = REG_RD(bp, reg);
292 REG_WR(bp, reg, val);
296 /******************************************************************/
297 /* EPIO/GPIO section */
298 /******************************************************************/
299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
301 u32 epio_mask, gp_oenable;
305 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
309 epio_mask = 1 << epio_pin;
310 /* Set this EPIO to output */
311 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
312 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
314 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
318 u32 epio_mask, gp_output, gp_oenable;
322 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
325 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
326 epio_mask = 1 << epio_pin;
327 /* Set this EPIO to output */
328 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
330 gp_output |= epio_mask;
332 gp_output &= ~epio_mask;
334 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
336 /* Set the value for this EPIO */
337 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
338 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
343 if (pin_cfg == PIN_CFG_NA)
345 if (pin_cfg >= PIN_CFG_EPIO0) {
346 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
348 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
349 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
350 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
356 if (pin_cfg == PIN_CFG_NA)
358 if (pin_cfg >= PIN_CFG_EPIO0) {
359 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
361 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
362 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
363 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
368 /******************************************************************/
370 /******************************************************************/
371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
373 /* ETS disabled configuration*/
374 struct bnx2x *bp = params->bp;
376 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
379 * mapping between entry priority to client number (0,1,2 -debug and
380 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
382 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
383 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
386 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
388 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
389 * as strict. Bits 0,1,2 - debug and management entries, 3 -
390 * COS0 entry, 4 - COS1 entry.
391 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
392 * bit4 bit3 bit2 bit1 bit0
393 * MCP and debug are strict
396 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
397 /* defines which entries (clients) are subjected to WFQ arbitration */
398 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
400 * For strict priority entries defines the number of consecutive
401 * slots for the highest priority.
403 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
405 * mapping between the CREDIT_WEIGHT registers and actual client
408 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
409 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
410 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
412 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
413 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
414 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
415 /* ETS mode disable */
416 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
418 * If ETS mode is enabled (there is no strict priority) defines a WFQ
419 * weight for COS0/COS1.
421 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
422 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
423 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
424 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
425 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
426 /* Defines the number of consecutive slots for the strict priority */
427 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
429 /******************************************************************************
431 * Getting min_w_val will be set according to line speed .
433 ******************************************************************************/
434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
437 /* Calculate min_w_val.*/
439 if (SPEED_20000 == vars->line_speed)
440 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
442 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
444 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
446 * If the link isn't up (static configuration for example ) The
447 * link will be according to 20GBPS.
451 /******************************************************************************
453 * Getting credit upper bound form min_w_val.
455 ******************************************************************************/
456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
458 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
460 return credit_upper_bound;
462 /******************************************************************************
464 * Set credit upper bound for NIG.
466 ******************************************************************************/
467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
468 const struct link_params *params,
471 struct bnx2x *bp = params->bp;
472 const u8 port = params->port;
473 const u32 credit_upper_bound =
474 bnx2x_ets_get_credit_upper_bound(min_w_val);
476 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
477 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
478 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
479 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
480 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
481 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
482 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
483 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
484 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
485 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
486 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
487 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
490 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
492 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
494 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
498 /******************************************************************************
500 * Will return the NIG ETS registers to init values.Except
501 * credit_upper_bound.
502 * That isn't used in this configuration (No WFQ is enabled) and will be
503 * configured acording to spec
505 ******************************************************************************/
506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
507 const struct link_vars *vars)
509 struct bnx2x *bp = params->bp;
510 const u8 port = params->port;
511 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
513 * mapping between entry priority to client number (0,1,2 -debug and
514 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
515 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
516 * reset value or init tool
519 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
520 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
522 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
526 * For strict priority entries defines the number of consecutive
527 * slots for the highest priority.
529 /* TODO_ETS - Should be done by reset value or init tool */
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
531 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
533 * mapping between the CREDIT_WEIGHT registers and actual client
536 /* TODO_ETS - Should be done by reset value or init tool */
539 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
540 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
549 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
550 * as strict. Bits 0,1,2 - debug and management entries, 3 -
551 * COS0 entry, 4 - COS1 entry.
552 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
553 * bit4 bit3 bit2 bit1 bit0
554 * MCP and debug are strict
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
560 /* defines which entries (clients) are subjected to WFQ arbitration */
561 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
562 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
565 * Please notice the register address are note continuous and a
566 * for here is note appropriate.In 2 port mode port0 only COS0-5
567 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
568 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
569 * are never used for WFQ
571 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
572 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
573 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
574 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
575 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
578 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
579 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
581 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
582 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
584 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
586 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
589 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
591 /******************************************************************************
593 * Set credit upper bound for PBF.
595 ******************************************************************************/
596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
597 const struct link_params *params,
600 struct bnx2x *bp = params->bp;
601 const u32 credit_upper_bound =
602 bnx2x_ets_get_credit_upper_bound(min_w_val);
603 const u8 port = params->port;
604 u32 base_upper_bound = 0;
608 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
609 * port mode port1 has COS0-2 that can be used for WFQ.
612 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
613 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
615 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
616 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
619 for (i = 0; i < max_cos; i++)
620 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
623 /******************************************************************************
625 * Will return the PBF ETS registers to init values.Except
626 * credit_upper_bound.
627 * That isn't used in this configuration (No WFQ is enabled) and will be
628 * configured acording to spec
630 ******************************************************************************/
631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
633 struct bnx2x *bp = params->bp;
634 const u8 port = params->port;
635 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
641 * mapping between entry priority to client number 0 - COS0
642 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
643 * TODO_ETS - Should be done by reset value or init tool
646 /* 0x688 (|011|0 10|00 1|000) */
647 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
649 /* (10 1|100 |011|0 10|00 1|000) */
650 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
652 /* TODO_ETS - Should be done by reset value or init tool */
654 /* 0x688 (|011|0 10|00 1|000)*/
655 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
657 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
658 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
660 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
661 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
664 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
665 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
667 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
668 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
670 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
671 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
674 base_weight = PBF_REG_COS0_WEIGHT_P0;
675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
677 base_weight = PBF_REG_COS0_WEIGHT_P1;
678 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
681 for (i = 0; i < max_cos; i++)
682 REG_WR(bp, base_weight + (0x4 * i), 0);
684 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
686 /******************************************************************************
688 * E3B0 disable will return basicly the values to init values.
690 ******************************************************************************/
691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
692 const struct link_vars *vars)
694 struct bnx2x *bp = params->bp;
696 if (!CHIP_IS_E3B0(bp)) {
697 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
702 bnx2x_ets_e3b0_nig_disabled(params, vars);
704 bnx2x_ets_e3b0_pbf_disabled(params);
709 /******************************************************************************
711 * Disable will return basicly the values to init values.
713 ******************************************************************************/
714 int bnx2x_ets_disabled(struct link_params *params,
715 struct link_vars *vars)
717 struct bnx2x *bp = params->bp;
718 int bnx2x_status = 0;
720 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
721 bnx2x_ets_e2e3a0_disabled(params);
722 else if (CHIP_IS_E3B0(bp))
723 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
725 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
732 /******************************************************************************
734 * Set the COS mappimg to SP and BW until this point all the COS are not
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
738 const struct bnx2x_ets_params *ets_params,
739 const u8 cos_sp_bitmap,
740 const u8 cos_bw_bitmap)
742 struct bnx2x *bp = params->bp;
743 const u8 port = params->port;
744 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
745 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
746 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
747 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
749 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
750 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
752 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
753 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
755 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
756 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
757 nig_cli_subject2wfq_bitmap);
759 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
760 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
761 pbf_cli_subject2wfq_bitmap);
766 /******************************************************************************
768 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
769 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
770 ******************************************************************************/
771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
773 const u32 min_w_val_nig,
774 const u32 min_w_val_pbf,
779 u32 nig_reg_adress_crd_weight = 0;
780 u32 pbf_reg_adress_crd_weight = 0;
781 /* Calculate and set BW for this COS*/
782 const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
783 const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
787 nig_reg_adress_crd_weight =
788 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
789 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
790 pbf_reg_adress_crd_weight = (port) ?
791 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
794 nig_reg_adress_crd_weight = (port) ?
795 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
796 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
797 pbf_reg_adress_crd_weight = (port) ?
798 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
801 nig_reg_adress_crd_weight = (port) ?
802 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
803 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
805 pbf_reg_adress_crd_weight = (port) ?
806 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
811 nig_reg_adress_crd_weight =
812 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
813 pbf_reg_adress_crd_weight =
814 PBF_REG_COS3_WEIGHT_P0;
819 nig_reg_adress_crd_weight =
820 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
821 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
826 nig_reg_adress_crd_weight =
827 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
828 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
832 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
834 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
838 /******************************************************************************
840 * Calculate the total BW.A value of 0 isn't legal.
842 ******************************************************************************/
843 static int bnx2x_ets_e3b0_get_total_bw(
844 const struct link_params *params,
845 const struct bnx2x_ets_params *ets_params,
848 struct bnx2x *bp = params->bp;
852 /* Calculate total BW requested */
853 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
854 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
856 if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
857 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
862 ets_params->cos[cos_idx].params.bw_params.bw;
866 /*Check taotl BW is valid */
867 if ((100 != *total_bw) || (0 == *total_bw)) {
868 if (0 == *total_bw) {
869 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
873 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
876 * We can handle a case whre the BW isn't 100 this can happen
877 * if the TC are joined.
883 /******************************************************************************
885 * Invalidate all the sp_pri_to_cos.
887 ******************************************************************************/
888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
891 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
892 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
894 /******************************************************************************
896 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
897 * according to sp_pri_to_cos.
899 ******************************************************************************/
900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
901 u8 *sp_pri_to_cos, const u8 pri,
904 struct bnx2x *bp = params->bp;
905 const u8 port = params->port;
906 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
907 DCBX_E3B0_MAX_NUM_COS_PORT0;
909 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
910 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
911 "parameter There can't be two COS's with"
912 "the same strict pri\n");
916 if (pri > max_num_of_cos) {
917 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
918 "parameter Illegal strict priority\n");
922 sp_pri_to_cos[pri] = cos_entry;
927 /******************************************************************************
929 * Returns the correct value according to COS and priority in
930 * the sp_pri_cli register.
932 ******************************************************************************/
933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
939 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
940 (pri_set + pri_offset));
944 /******************************************************************************
946 * Returns the correct value according to COS and priority in the
947 * sp_pri_cli register for NIG.
949 ******************************************************************************/
950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
952 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
953 const u8 nig_cos_offset = 3;
954 const u8 nig_pri_offset = 3;
956 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
960 /******************************************************************************
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for PBF.
965 ******************************************************************************/
966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
968 const u8 pbf_cos_offset = 0;
969 const u8 pbf_pri_offset = 0;
971 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
976 /******************************************************************************
978 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
979 * according to sp_pri_to_cos.(which COS has higher priority)
981 ******************************************************************************/
982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
985 struct bnx2x *bp = params->bp;
987 const u8 port = params->port;
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
989 u64 pri_cli_nig = 0x210;
990 u32 pri_cli_pbf = 0x0;
993 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
994 DCBX_E3B0_MAX_NUM_COS_PORT0;
996 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
998 /* Set all the strict priority first */
999 for (i = 0; i < max_num_of_cos; i++) {
1000 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1003 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004 "invalid cos entry\n");
1008 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009 sp_pri_to_cos[i], pri_set);
1011 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012 sp_pri_to_cos[i], pri_set);
1013 pri_bitmask = 1 << sp_pri_to_cos[i];
1014 /* COS is used remove it from bitmap.*/
1015 if (0 == (pri_bitmask & cos_bit_to_set)) {
1017 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018 "invalid There can't be two COS's with"
1019 " the same strict pri\n");
1022 cos_bit_to_set &= ~pri_bitmask;
1027 /* Set all the Non strict priority i= COS*/
1028 for (i = 0; i < max_num_of_cos; i++) {
1029 pri_bitmask = 1 << i;
1030 /* Check if COS was already used for SP */
1031 if (pri_bitmask & cos_bit_to_set) {
1032 /* COS wasn't used for SP */
1033 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1036 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1038 /* COS is used remove it from bitmap.*/
1039 cos_bit_to_set &= ~pri_bitmask;
1044 if (pri_set != max_num_of_cos) {
1045 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046 "entries were set\n");
1051 /* Only 6 usable clients*/
1052 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1055 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1057 /* Only 9 usable clients*/
1058 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1061 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1063 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1066 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1071 /******************************************************************************
1073 * Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076 const struct link_vars *vars,
1077 const struct bnx2x_ets_params *ets_params)
1079 struct bnx2x *bp = params->bp;
1080 int bnx2x_status = 0;
1081 const u8 port = params->port;
1083 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085 u8 cos_bw_bitmap = 0;
1086 u8 cos_sp_bitmap = 0;
1087 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089 DCBX_E3B0_MAX_NUM_COS_PORT0;
1092 if (!CHIP_IS_E3B0(bp)) {
1093 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1098 if ((ets_params->num_of_cos > max_num_of_cos)) {
1099 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100 "isn't supported\n");
1104 /* Prepare sp strict priority parameters*/
1105 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1107 /* Prepare BW parameters*/
1108 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1110 if (0 != bnx2x_status) {
1111 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1117 * Upper bound is set according to current link speed (min_w_val
1118 * should be the same for upper bound and COS credit val).
1120 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1124 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126 cos_bw_bitmap |= (1 << cos_entry);
1128 * The function also sets the BW in HW(not the mappin
1131 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1134 ets_params->cos[cos_entry].params.bw_params.bw,
1136 } else if (bnx2x_cos_state_strict ==
1137 ets_params->cos[cos_entry].state){
1138 cos_sp_bitmap |= (1 << cos_entry);
1140 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1143 ets_params->cos[cos_entry].params.sp_params.pri,
1147 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1151 if (0 != bnx2x_status) {
1152 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1154 return bnx2x_status;
1158 /* Set SP register (which COS has higher priority) */
1159 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1162 if (0 != bnx2x_status) {
1163 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1165 return bnx2x_status;
1168 /* Set client mapping of BW and strict */
1169 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1173 if (0 != bnx2x_status) {
1174 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175 return bnx2x_status;
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1181 /* ETS disabled configuration */
1182 struct bnx2x *bp = params->bp;
1183 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1185 * defines which entries (clients) are subjected to WFQ arbitration
1189 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1191 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192 * client numbers (WEIGHT_0 does not actually have to represent
1194 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1195 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1197 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1199 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1204 /* ETS mode enabled*/
1205 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1207 /* Defines the number of consecutive slots for the strict priority */
1208 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1210 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1212 * entry, 4 - COS1 entry.
1213 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214 * bit4 bit3 bit2 bit1 bit0
1215 * MCP and debug are strict
1217 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1219 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1229 /* ETS disabled configuration*/
1230 struct bnx2x *bp = params->bp;
1231 const u32 total_bw = cos0_bw + cos1_bw;
1232 u32 cos0_credit_weight = 0;
1233 u32 cos1_credit_weight = 0;
1235 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1237 if ((0 == total_bw) ||
1240 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1244 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1246 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1249 bnx2x_ets_bw_limit_common(params);
1251 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1254 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1260 /* ETS disabled configuration*/
1261 struct bnx2x *bp = params->bp;
1264 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1266 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267 * as strict. Bits 0,1,2 - debug and management entries,
1268 * 3 - COS0 entry, 4 - COS1 entry.
1269 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270 * bit4 bit3 bit2 bit1 bit0
1271 * MCP and debug are strict
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1275 * For strict priority entries defines the number of consecutive slots
1276 * for the highest priority.
1278 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279 /* ETS mode disable */
1280 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281 /* Defines the number of consecutive slots for the strict priority */
1282 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1284 /* Defines the number of consecutive slots for the strict priority */
1285 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1288 * mapping between entry priority to client number (0,1,2 -debug and
1289 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1291 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1292 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1293 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1295 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1300 /******************************************************************/
1302 /******************************************************************/
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305 struct link_vars *vars,
1308 struct bnx2x *bp = params->bp;
1310 u32 pause_val, pfc0_val, pfc1_val;
1312 /* XMAC base adrr */
1313 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1315 /* Initialize pause and pfc registers */
1316 pause_val = 0x18000;
1317 pfc0_val = 0xFFFF8000;
1320 /* No PFC support */
1321 if (!(params->feature_config_flags &
1322 FEATURE_CONFIG_PFC_ENABLED)) {
1325 * RX flow control - Process pause frame in receive direction
1327 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1331 * TX flow control - Send pause packet when buffer is full
1333 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335 } else {/* PFC support */
1336 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1342 /* Write pause and PFC registers */
1343 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1348 /* Set MAC address for source TX Pause/PFC frames */
1349 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350 ((params->mac_addr[2] << 24) |
1351 (params->mac_addr[3] << 16) |
1352 (params->mac_addr[4] << 8) |
1353 (params->mac_addr[5])));
1354 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355 ((params->mac_addr[0] << 8) |
1356 (params->mac_addr[1])));
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363 u32 pfc_frames_sent[2],
1364 u32 pfc_frames_received[2])
1366 /* Read pfc statistic */
1367 struct bnx2x *bp = params->bp;
1368 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1372 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1374 /* PFC received frames */
1375 val_xoff = REG_RD(bp, emac_base +
1376 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1381 pfc_frames_received[0] = val_xon + val_xoff;
1383 /* PFC received sent */
1384 val_xoff = REG_RD(bp, emac_base +
1385 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1390 pfc_frames_sent[0] = val_xon + val_xoff;
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395 u32 pfc_frames_sent[2],
1396 u32 pfc_frames_received[2])
1398 /* Read pfc statistic */
1399 struct bnx2x *bp = params->bp;
1401 DP(NETIF_MSG_LINK, "pfc statistic\n");
1406 if (MAC_TYPE_EMAC == vars->mac_type) {
1407 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409 pfc_frames_received);
1412 /******************************************************************/
1413 /* MAC/PBF section */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1417 u32 mode, emac_base;
1419 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420 * (a value of 49==0x31) and make sure that the AUTO poll is off
1424 emac_base = GRCBASE_EMAC0;
1426 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429 EMAC_MDIO_MODE_CLOCK_CNT);
1430 if (USES_WARPCORE(bp))
1431 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1433 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1435 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1441 static void bnx2x_emac_init(struct link_params *params,
1442 struct link_vars *vars)
1444 /* reset and unreset the emac core */
1445 struct bnx2x *bp = params->bp;
1446 u8 port = params->port;
1447 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1451 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1457 /* init emac - use read-modify-write */
1458 /* self clear reset */
1459 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1464 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1467 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1471 } while (val & EMAC_MODE_RESET);
1472 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473 /* Set mac address */
1474 val = ((params->mac_addr[0] << 8) |
1475 params->mac_addr[1]);
1476 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1478 val = ((params->mac_addr[2] << 24) |
1479 (params->mac_addr[3] << 16) |
1480 (params->mac_addr[4] << 8) |
1481 params->mac_addr[5]);
1482 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1489 struct bnx2x *bp = params->bp;
1491 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1493 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1495 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1499 static void bnx2x_umac_enable(struct link_params *params,
1500 struct link_vars *vars, u8 lb)
1503 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504 struct bnx2x *bp = params->bp;
1506 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508 usleep_range(1000, 1000);
1510 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1513 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1516 * This register determines on which events the MAC will assert
1517 * error on the i/f to the NIG along w/ EOP.
1521 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522 * params->port*0x14, 0xfffff.
1524 /* This register opens the gate for the UMAC despite its name */
1525 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1527 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531 switch (vars->line_speed) {
1545 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1549 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1552 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1553 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1554 ((params->mac_addr[2] << 24) |
1555 (params->mac_addr[3] << 16) |
1556 (params->mac_addr[4] << 8) |
1557 (params->mac_addr[5])));
1558 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1559 ((params->mac_addr[0] << 8) |
1560 (params->mac_addr[1])));
1562 /* Enable RX and TX */
1563 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1564 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1565 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1566 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1569 /* Remove SW Reset */
1570 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1572 /* Check loopback mode */
1574 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1575 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1578 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1579 * length used by the MAC receive logic to check frames.
1581 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1582 bnx2x_set_xumac_nig(params,
1583 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1584 vars->mac_type = MAC_TYPE_UMAC;
1588 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1590 u32 port4mode_ovwr_val;
1591 /* Check 4-port override enabled */
1592 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1593 if (port4mode_ovwr_val & (1<<0)) {
1594 /* Return 4-port mode override value */
1595 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1597 /* Return 4-port mode from input pin */
1598 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1601 /* Define the XMAC mode */
1602 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1604 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1607 * In 4-port mode, need to set the mode only once, so if XMAC is
1608 * already out of reset, it means the mode has already been set,
1609 * and it must not* reset the XMAC again, since it controls both
1613 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1614 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1615 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1616 " in 4-port mode\n");
1621 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1622 MISC_REGISTERS_RESET_REG_2_XMAC);
1623 usleep_range(1000, 1000);
1625 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1626 MISC_REGISTERS_RESET_REG_2_XMAC);
1628 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1630 /* Set the number of ports on the system side to up to 2 */
1631 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1633 /* Set the number of ports on the Warp Core to 10G */
1634 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1636 /* Set the number of ports on the system side to 1 */
1637 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1638 if (max_speed == SPEED_10000) {
1639 DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1640 " port per path\n");
1641 /* Set the number of ports on the Warp Core to 10G */
1642 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1644 DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1646 /* Set the number of ports on the Warp Core to 20G */
1647 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1651 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1652 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1653 usleep_range(1000, 1000);
1655 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1656 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1660 static void bnx2x_xmac_disable(struct link_params *params)
1662 u8 port = params->port;
1663 struct bnx2x *bp = params->bp;
1664 u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1666 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1667 MISC_REGISTERS_RESET_REG_2_XMAC) {
1668 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1669 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1670 usleep_range(1000, 1000);
1671 bnx2x_set_xumac_nig(params, 0, 0);
1672 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1673 XMAC_CTRL_REG_SOFT_RESET);
1677 static int bnx2x_xmac_enable(struct link_params *params,
1678 struct link_vars *vars, u8 lb)
1681 struct bnx2x *bp = params->bp;
1682 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1684 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1686 bnx2x_xmac_init(bp, vars->line_speed);
1689 * This register determines on which events the MAC will assert
1690 * error on the i/f to the NIG along w/ EOP.
1694 * This register tells the NIG whether to send traffic to UMAC
1697 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1699 /* Set Max packet size */
1700 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1702 /* CRC append for Tx packets */
1703 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1706 bnx2x_update_pfc_xmac(params, vars, 0);
1708 /* Enable TX and RX */
1709 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1711 /* Check loopback mode */
1713 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1714 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1715 bnx2x_set_xumac_nig(params,
1716 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1718 vars->mac_type = MAC_TYPE_XMAC;
1722 static int bnx2x_emac_enable(struct link_params *params,
1723 struct link_vars *vars, u8 lb)
1725 struct bnx2x *bp = params->bp;
1726 u8 port = params->port;
1727 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1730 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1732 /* enable emac and not bmac */
1733 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1736 if (vars->phy_flags & PHY_XGXS_FLAG) {
1737 u32 ser_lane = ((params->lane_config &
1738 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1739 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1741 DP(NETIF_MSG_LINK, "XGXS\n");
1742 /* select the master lanes (out of 0-3) */
1743 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1745 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1747 } else { /* SerDes */
1748 DP(NETIF_MSG_LINK, "SerDes\n");
1750 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1753 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1754 EMAC_RX_MODE_RESET);
1755 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1756 EMAC_TX_MODE_RESET);
1758 if (CHIP_REV_IS_SLOW(bp)) {
1759 /* config GMII mode */
1760 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1761 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1763 /* pause enable/disable */
1764 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1765 EMAC_RX_MODE_FLOW_EN);
1767 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1768 (EMAC_TX_MODE_EXT_PAUSE_EN |
1769 EMAC_TX_MODE_FLOW_EN));
1770 if (!(params->feature_config_flags &
1771 FEATURE_CONFIG_PFC_ENABLED)) {
1772 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1773 bnx2x_bits_en(bp, emac_base +
1774 EMAC_REG_EMAC_RX_MODE,
1775 EMAC_RX_MODE_FLOW_EN);
1777 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1778 bnx2x_bits_en(bp, emac_base +
1779 EMAC_REG_EMAC_TX_MODE,
1780 (EMAC_TX_MODE_EXT_PAUSE_EN |
1781 EMAC_TX_MODE_FLOW_EN));
1783 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1784 EMAC_TX_MODE_FLOW_EN);
1787 /* KEEP_VLAN_TAG, promiscuous */
1788 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1789 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1792 * Setting this bit causes MAC control frames (except for pause
1793 * frames) to be passed on for processing. This setting has no
1794 * affect on the operation of the pause frames. This bit effects
1795 * all packets regardless of RX Parser packet sorting logic.
1796 * Turn the PFC off to make sure we are in Xon state before
1799 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1800 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1801 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1802 /* Enable PFC again */
1803 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1804 EMAC_REG_RX_PFC_MODE_RX_EN |
1805 EMAC_REG_RX_PFC_MODE_TX_EN |
1806 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1808 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1810 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1812 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1813 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1815 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1818 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1823 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1826 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1828 /* enable emac for jumbo packets */
1829 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1830 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1831 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1834 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1836 /* disable the NIG in/out to the bmac */
1837 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1838 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1839 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1841 /* enable the NIG in/out to the emac */
1842 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1844 if ((params->feature_config_flags &
1845 FEATURE_CONFIG_PFC_ENABLED) ||
1846 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1849 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1850 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1852 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1854 vars->mac_type = MAC_TYPE_EMAC;
1858 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1859 struct link_vars *vars)
1862 struct bnx2x *bp = params->bp;
1863 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1864 NIG_REG_INGRESS_BMAC0_MEM;
1867 if ((!(params->feature_config_flags &
1868 FEATURE_CONFIG_PFC_ENABLED)) &&
1869 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1870 /* Enable BigMAC to react on received Pause packets */
1874 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1878 if (!(params->feature_config_flags &
1879 FEATURE_CONFIG_PFC_ENABLED) &&
1880 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1884 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1887 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1888 struct link_vars *vars,
1892 * Set rx control: Strip CRC and enable BigMAC to relay
1893 * control packets to the system as well
1896 struct bnx2x *bp = params->bp;
1897 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1898 NIG_REG_INGRESS_BMAC0_MEM;
1901 if ((!(params->feature_config_flags &
1902 FEATURE_CONFIG_PFC_ENABLED)) &&
1903 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1904 /* Enable BigMAC to react on received Pause packets */
1908 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1913 if (!(params->feature_config_flags &
1914 FEATURE_CONFIG_PFC_ENABLED) &&
1915 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1919 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1921 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923 /* Enable PFC RX & TX & STATS and set 8 COS */
1925 wb_data[0] |= (1<<0); /* RX */
1926 wb_data[0] |= (1<<1); /* TX */
1927 wb_data[0] |= (1<<2); /* Force initial Xon */
1928 wb_data[0] |= (1<<3); /* 8 cos */
1929 wb_data[0] |= (1<<5); /* STATS */
1931 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1933 /* Clear the force Xon */
1934 wb_data[0] &= ~(1<<2);
1936 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1937 /* disable PFC RX & TX & STATS and set 8 COS */
1942 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1945 * Set Time (based unit is 512 bit time) between automatic
1946 * re-sending of PP packets amd enable automatic re-send of
1947 * Per-Priroity Packet as long as pp_gen is asserted and
1948 * pp_disable is low.
1951 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1952 val |= (1<<16); /* enable automatic re-send */
1956 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1960 val = 0x3; /* Enable RX and TX */
1962 val |= 0x4; /* Local loopback */
1963 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1965 /* When PFC enabled, Pass pause frames towards the NIG. */
1966 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1967 val |= ((1<<6)|(1<<5));
1971 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1975 /* PFC BRB internal port configuration params */
1976 struct bnx2x_pfc_brb_threshold_val {
1983 struct bnx2x_pfc_brb_e3b0_val {
1984 u32 full_lb_xoff_th;
1985 u32 full_lb_xon_threshold;
1987 u32 mac_0_class_t_guarantied;
1988 u32 mac_0_class_t_guarantied_hyst;
1989 u32 mac_1_class_t_guarantied;
1990 u32 mac_1_class_t_guarantied_hyst;
1993 struct bnx2x_pfc_brb_th_val {
1994 struct bnx2x_pfc_brb_threshold_val pauseable_th;
1995 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1997 static int bnx2x_pfc_brb_get_config_params(
1998 struct link_params *params,
1999 struct bnx2x_pfc_brb_th_val *config_val)
2001 struct bnx2x *bp = params->bp;
2002 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2003 if (CHIP_IS_E2(bp)) {
2004 config_val->pauseable_th.pause_xoff =
2005 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2006 config_val->pauseable_th.pause_xon =
2007 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2008 config_val->pauseable_th.full_xoff =
2009 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2010 config_val->pauseable_th.full_xon =
2011 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2013 config_val->non_pauseable_th.pause_xoff =
2014 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2015 config_val->non_pauseable_th.pause_xon =
2016 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2017 config_val->non_pauseable_th.full_xoff =
2018 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2019 config_val->non_pauseable_th.full_xon =
2020 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2021 } else if (CHIP_IS_E3A0(bp)) {
2022 config_val->pauseable_th.pause_xoff =
2023 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2024 config_val->pauseable_th.pause_xon =
2025 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2026 config_val->pauseable_th.full_xoff =
2027 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2028 config_val->pauseable_th.full_xon =
2029 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2031 config_val->non_pauseable_th.pause_xoff =
2032 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2033 config_val->non_pauseable_th.pause_xon =
2034 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2035 config_val->non_pauseable_th.full_xoff =
2036 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2037 config_val->non_pauseable_th.full_xon =
2038 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2039 } else if (CHIP_IS_E3B0(bp)) {
2040 if (params->phy[INT_PHY].flags &
2041 FLAGS_4_PORT_MODE) {
2042 config_val->pauseable_th.pause_xoff =
2043 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2044 config_val->pauseable_th.pause_xon =
2045 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2046 config_val->pauseable_th.full_xoff =
2047 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2048 config_val->pauseable_th.full_xon =
2049 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2051 config_val->non_pauseable_th.pause_xoff =
2052 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2053 config_val->non_pauseable_th.pause_xon =
2054 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2055 config_val->non_pauseable_th.full_xoff =
2056 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2057 config_val->non_pauseable_th.full_xon =
2058 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2060 config_val->pauseable_th.pause_xoff =
2061 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2062 config_val->pauseable_th.pause_xon =
2063 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2064 config_val->pauseable_th.full_xoff =
2065 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2066 config_val->pauseable_th.full_xon =
2067 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2069 config_val->non_pauseable_th.pause_xoff =
2070 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2071 config_val->non_pauseable_th.pause_xon =
2072 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2073 config_val->non_pauseable_th.full_xoff =
2074 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2075 config_val->non_pauseable_th.full_xon =
2076 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2085 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2086 struct bnx2x_pfc_brb_e3b0_val
2091 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2092 e3b0_val->full_lb_xoff_th =
2093 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2094 e3b0_val->full_lb_xon_threshold =
2095 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2096 e3b0_val->lb_guarantied =
2097 PFC_E3B0_4P_LB_GUART;
2098 e3b0_val->mac_0_class_t_guarantied =
2099 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2100 e3b0_val->mac_0_class_t_guarantied_hyst =
2101 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2102 e3b0_val->mac_1_class_t_guarantied =
2103 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2104 e3b0_val->mac_1_class_t_guarantied_hyst =
2105 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2107 e3b0_val->full_lb_xoff_th =
2108 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2109 e3b0_val->full_lb_xon_threshold =
2110 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2111 e3b0_val->mac_0_class_t_guarantied_hyst =
2112 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2113 e3b0_val->mac_1_class_t_guarantied =
2114 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2115 e3b0_val->mac_1_class_t_guarantied_hyst =
2116 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2118 if (cos0_pauseable != cos1_pauseable) {
2119 /* nonpauseable= Lossy + pauseable = Lossless*/
2120 e3b0_val->lb_guarantied =
2121 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2122 e3b0_val->mac_0_class_t_guarantied =
2123 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2124 } else if (cos0_pauseable) {
2125 /* Lossless +Lossless*/
2126 e3b0_val->lb_guarantied =
2127 PFC_E3B0_2P_PAUSE_LB_GUART;
2128 e3b0_val->mac_0_class_t_guarantied =
2129 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2132 e3b0_val->lb_guarantied =
2133 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2134 e3b0_val->mac_0_class_t_guarantied =
2135 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2139 static int bnx2x_update_pfc_brb(struct link_params *params,
2140 struct link_vars *vars,
2141 struct bnx2x_nig_brb_pfc_port_params
2144 struct bnx2x *bp = params->bp;
2145 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2146 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2147 &config_val.pauseable_th;
2148 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2149 int set_pfc = params->feature_config_flags &
2150 FEATURE_CONFIG_PFC_ENABLED;
2151 int bnx2x_status = 0;
2152 u8 port = params->port;
2154 /* default - pause configuration */
2155 reg_th_config = &config_val.pauseable_th;
2156 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2157 if (0 != bnx2x_status)
2158 return bnx2x_status;
2160 if (set_pfc && pfc_params)
2162 if (!pfc_params->cos0_pauseable)
2163 reg_th_config = &config_val.non_pauseable_th;
2165 * The number of free blocks below which the pause signal to class 0
2166 * of MAC #n is asserted. n=0,1
2168 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2169 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2170 reg_th_config->pause_xoff);
2172 * The number of free blocks above which the pause signal to class 0
2173 * of MAC #n is de-asserted. n=0,1
2175 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2176 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2178 * The number of free blocks below which the full signal to class 0
2179 * of MAC #n is asserted. n=0,1
2181 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2182 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2184 * The number of free blocks above which the full signal to class 0
2185 * of MAC #n is de-asserted. n=0,1
2187 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2188 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2190 if (set_pfc && pfc_params) {
2192 if (pfc_params->cos1_pauseable)
2193 reg_th_config = &config_val.pauseable_th;
2195 reg_th_config = &config_val.non_pauseable_th;
2197 * The number of free blocks below which the pause signal to
2198 * class 1 of MAC #n is asserted. n=0,1
2200 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2201 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2202 reg_th_config->pause_xoff);
2204 * The number of free blocks above which the pause signal to
2205 * class 1 of MAC #n is de-asserted. n=0,1
2207 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2208 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2209 reg_th_config->pause_xon);
2211 * The number of free blocks below which the full signal to
2212 * class 1 of MAC #n is asserted. n=0,1
2214 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2215 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2216 reg_th_config->full_xoff);
2218 * The number of free blocks above which the full signal to
2219 * class 1 of MAC #n is de-asserted. n=0,1
2221 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2222 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2223 reg_th_config->full_xon);
2226 if (CHIP_IS_E3B0(bp)) {
2227 /*Should be done by init tool */
2229 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2235 * The hysteresis on the guarantied buffer space for the Lb port
2236 * before signaling XON.
2238 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2240 bnx2x_pfc_brb_get_e3b0_config_params(
2243 pfc_params->cos0_pauseable,
2244 pfc_params->cos1_pauseable);
2246 * The number of free blocks below which the full signal to the
2247 * LB port is asserted.
2249 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2250 e3b0_val.full_lb_xoff_th);
2252 * The number of free blocks above which the full signal to the
2253 * LB port is de-asserted.
2255 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2256 e3b0_val.full_lb_xon_threshold);
2258 * The number of blocks guarantied for the MAC #n port. n=0,1
2261 /*The number of blocks guarantied for the LB port.*/
2262 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2263 e3b0_val.lb_guarantied);
2266 * The number of blocks guarantied for the MAC #n port.
2268 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2269 2 * e3b0_val.mac_0_class_t_guarantied);
2270 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2271 2 * e3b0_val.mac_1_class_t_guarantied);
2273 * The number of blocks guarantied for class #t in MAC0. t=0,1
2275 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2276 e3b0_val.mac_0_class_t_guarantied);
2277 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2278 e3b0_val.mac_0_class_t_guarantied);
2280 * The hysteresis on the guarantied buffer space for class in
2283 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2284 e3b0_val.mac_0_class_t_guarantied_hyst);
2285 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2286 e3b0_val.mac_0_class_t_guarantied_hyst);
2289 * The number of blocks guarantied for class #t in MAC1.t=0,1
2291 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2292 e3b0_val.mac_1_class_t_guarantied);
2293 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2294 e3b0_val.mac_1_class_t_guarantied);
2296 * The hysteresis on the guarantied buffer space for class #t
2299 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2300 e3b0_val.mac_1_class_t_guarantied_hyst);
2301 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2302 e3b0_val.mac_1_class_t_guarantied_hyst);
2308 return bnx2x_status;
2311 /******************************************************************************
2313 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2314 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2315 ******************************************************************************/
2316 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2318 u32 priority_mask, u8 port)
2320 u32 nig_reg_rx_priority_mask_add = 0;
2322 switch (cos_entry) {
2324 nig_reg_rx_priority_mask_add = (port) ?
2325 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2326 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2329 nig_reg_rx_priority_mask_add = (port) ?
2330 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2331 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2334 nig_reg_rx_priority_mask_add = (port) ?
2335 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2336 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2341 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2346 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2351 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2355 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2359 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2361 struct bnx2x *bp = params->bp;
2363 REG_WR(bp, params->shmem_base +
2364 offsetof(struct shmem_region,
2365 port_mb[params->port].link_status), link_status);
2368 static void bnx2x_update_pfc_nig(struct link_params *params,
2369 struct link_vars *vars,
2370 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2372 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2373 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2374 u32 pkt_priority_to_cos = 0;
2375 struct bnx2x *bp = params->bp;
2376 u8 port = params->port;
2378 int set_pfc = params->feature_config_flags &
2379 FEATURE_CONFIG_PFC_ENABLED;
2380 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2383 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2384 * MAC control frames (that are not pause packets)
2385 * will be forwarded to the XCM.
2387 xcm_mask = REG_RD(bp,
2388 port ? NIG_REG_LLH1_XCM_MASK :
2389 NIG_REG_LLH0_XCM_MASK);
2391 * nig params will override non PFC params, since it's possible to
2392 * do transition from PFC to SAFC
2402 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2403 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2405 p0_hwpfc_enable = 1;
2408 llfc_out_en = nig_params->llfc_out_en;
2409 llfc_enable = nig_params->llfc_enable;
2410 pause_enable = nig_params->pause_enable;
2411 } else /*defaul non PFC mode - PAUSE */
2414 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2415 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2420 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2421 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2422 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2423 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2424 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2425 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2426 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2427 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2429 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2430 NIG_REG_PPP_ENABLE_0, ppp_enable);
2432 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2433 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2435 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2437 /* output enable for RX_XCM # IF */
2438 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2440 /* HW PFC TX enable */
2441 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2445 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2447 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2448 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2449 nig_params->rx_cos_priority_mask[i], port);
2451 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2452 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2453 nig_params->llfc_high_priority_classes);
2455 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2456 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2457 nig_params->llfc_low_priority_classes);
2459 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2460 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2461 pkt_priority_to_cos);
2464 int bnx2x_update_pfc(struct link_params *params,
2465 struct link_vars *vars,
2466 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2469 * The PFC and pause are orthogonal to one another, meaning when
2470 * PFC is enabled, the pause are disabled, and when PFC is
2471 * disabled, pause are set according to the pause result.
2474 struct bnx2x *bp = params->bp;
2475 int bnx2x_status = 0;
2476 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2478 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2479 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2481 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2483 bnx2x_update_mng(params, vars->link_status);
2485 /* update NIG params */
2486 bnx2x_update_pfc_nig(params, vars, pfc_params);
2488 /* update BRB params */
2489 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2490 if (0 != bnx2x_status)
2491 return bnx2x_status;
2494 return bnx2x_status;
2496 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2498 bnx2x_update_pfc_xmac(params, vars, 0);
2500 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2502 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2504 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2505 bnx2x_emac_enable(params, vars, 0);
2506 return bnx2x_status;
2510 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2512 bnx2x_update_pfc_bmac1(params, vars);
2515 if ((params->feature_config_flags &
2516 FEATURE_CONFIG_PFC_ENABLED) ||
2517 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2519 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2521 return bnx2x_status;
2525 static int bnx2x_bmac1_enable(struct link_params *params,
2526 struct link_vars *vars,
2529 struct bnx2x *bp = params->bp;
2530 u8 port = params->port;
2531 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2532 NIG_REG_INGRESS_BMAC0_MEM;
2536 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2541 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2545 wb_data[0] = ((params->mac_addr[2] << 24) |
2546 (params->mac_addr[3] << 16) |
2547 (params->mac_addr[4] << 8) |
2548 params->mac_addr[5]);
2549 wb_data[1] = ((params->mac_addr[0] << 8) |
2550 params->mac_addr[1]);
2551 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2557 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2561 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2564 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2566 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2568 bnx2x_update_pfc_bmac1(params, vars);
2571 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2573 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2575 /* set cnt max size */
2576 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2578 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2580 /* configure safc */
2581 wb_data[0] = 0x1000200;
2583 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2586 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2587 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2595 static int bnx2x_bmac2_enable(struct link_params *params,
2596 struct link_vars *vars,
2599 struct bnx2x *bp = params->bp;
2600 u8 port = params->port;
2601 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2602 NIG_REG_INGRESS_BMAC0_MEM;
2605 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2609 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2612 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2615 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2621 wb_data[0] = ((params->mac_addr[2] << 24) |
2622 (params->mac_addr[3] << 16) |
2623 (params->mac_addr[4] << 8) |
2624 params->mac_addr[5]);
2625 wb_data[1] = ((params->mac_addr[0] << 8) |
2626 params->mac_addr[1]);
2627 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2632 /* Configure SAFC */
2633 wb_data[0] = 0x1000200;
2635 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2640 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2642 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2646 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2648 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2650 /* set cnt max size */
2651 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2653 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2655 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2657 if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2658 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2660 if (wb_data[0] > 0) {
2661 DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2670 static int bnx2x_bmac_enable(struct link_params *params,
2671 struct link_vars *vars,
2675 u8 port = params->port;
2676 struct bnx2x *bp = params->bp;
2678 /* reset and unreset the BigMac */
2679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2680 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2684 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2686 /* enable access for bmac registers */
2687 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2689 /* Enable BMAC according to BMAC type*/
2691 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2693 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2694 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2695 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2696 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2698 if ((params->feature_config_flags &
2699 FEATURE_CONFIG_PFC_ENABLED) ||
2700 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2702 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2703 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2704 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2705 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2706 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2707 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2709 vars->mac_type = MAC_TYPE_BMAC;
2713 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2715 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2716 NIG_REG_INGRESS_BMAC0_MEM;
2718 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2720 /* Only if the bmac is out of reset */
2721 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2722 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2725 if (CHIP_IS_E2(bp)) {
2726 /* Clear Rx Enable bit in BMAC_CONTROL register */
2727 REG_RD_DMAE(bp, bmac_addr +
2728 BIGMAC2_REGISTER_BMAC_CONTROL,
2730 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2731 REG_WR_DMAE(bp, bmac_addr +
2732 BIGMAC2_REGISTER_BMAC_CONTROL,
2735 /* Clear Rx Enable bit in BMAC_CONTROL register */
2736 REG_RD_DMAE(bp, bmac_addr +
2737 BIGMAC_REGISTER_BMAC_CONTROL,
2739 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2740 REG_WR_DMAE(bp, bmac_addr +
2741 BIGMAC_REGISTER_BMAC_CONTROL,
2748 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2751 struct bnx2x *bp = params->bp;
2752 u8 port = params->port;
2757 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2759 /* wait for init credit */
2760 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2761 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2762 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2764 while ((init_crd != crd) && count) {
2767 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2770 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2771 if (init_crd != crd) {
2772 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2777 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2778 line_speed == SPEED_10 ||
2779 line_speed == SPEED_100 ||
2780 line_speed == SPEED_1000 ||
2781 line_speed == SPEED_2500) {
2782 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2783 /* update threshold */
2784 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2785 /* update init credit */
2786 init_crd = 778; /* (800-18-4) */
2789 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2791 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2792 /* update threshold */
2793 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2794 /* update init credit */
2795 switch (line_speed) {
2797 init_crd = thresh + 553 - 22;
2800 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2805 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2806 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2807 line_speed, init_crd);
2809 /* probe the credit changes */
2810 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2812 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2815 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2820 * bnx2x_get_emac_base - retrive emac base address
2822 * @bp: driver handle
2823 * @mdc_mdio_access: access type
2826 * This function selects the MDC/MDIO access (through emac0 or
2827 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2828 * phy has a default access mode, which could also be overridden
2829 * by nvram configuration. This parameter, whether this is the
2830 * default phy configuration, or the nvram overrun
2831 * configuration, is passed here as mdc_mdio_access and selects
2832 * the emac_base for the CL45 read/writes operations
2834 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2835 u32 mdc_mdio_access, u8 port)
2838 switch (mdc_mdio_access) {
2839 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2841 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2842 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2843 emac_base = GRCBASE_EMAC1;
2845 emac_base = GRCBASE_EMAC0;
2847 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2848 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2849 emac_base = GRCBASE_EMAC0;
2851 emac_base = GRCBASE_EMAC1;
2853 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2854 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2856 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2857 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2866 /******************************************************************/
2867 /* CL22 access functions */
2868 /******************************************************************/
2869 static int bnx2x_cl22_write(struct bnx2x *bp,
2870 struct bnx2x_phy *phy,
2876 /* Switch to CL22 */
2877 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2878 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2879 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2882 tmp = ((phy->addr << 21) | (reg << 16) | val |
2883 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2884 EMAC_MDIO_COMM_START_BUSY);
2885 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2887 for (i = 0; i < 50; i++) {
2890 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2891 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2896 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2897 DP(NETIF_MSG_LINK, "write phy register failed\n");
2900 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2904 static int bnx2x_cl22_read(struct bnx2x *bp,
2905 struct bnx2x_phy *phy,
2906 u16 reg, u16 *ret_val)
2912 /* Switch to CL22 */
2913 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2914 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2915 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2918 val = ((phy->addr << 21) | (reg << 16) |
2919 EMAC_MDIO_COMM_COMMAND_READ_22 |
2920 EMAC_MDIO_COMM_START_BUSY);
2921 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2923 for (i = 0; i < 50; i++) {
2926 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2927 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2928 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2933 if (val & EMAC_MDIO_COMM_START_BUSY) {
2934 DP(NETIF_MSG_LINK, "read phy register failed\n");
2939 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2943 /******************************************************************/
2944 /* CL45 access functions */
2945 /******************************************************************/
2946 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2947 u8 devad, u16 reg, u16 *ret_val)
2954 val = ((phy->addr << 21) | (devad << 16) | reg |
2955 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2956 EMAC_MDIO_COMM_START_BUSY);
2957 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2959 for (i = 0; i < 50; i++) {
2962 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2963 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2968 if (val & EMAC_MDIO_COMM_START_BUSY) {
2969 DP(NETIF_MSG_LINK, "read phy register failed\n");
2970 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2975 val = ((phy->addr << 21) | (devad << 16) |
2976 EMAC_MDIO_COMM_COMMAND_READ_45 |
2977 EMAC_MDIO_COMM_START_BUSY);
2978 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2980 for (i = 0; i < 50; i++) {
2983 val = REG_RD(bp, phy->mdio_ctrl +
2984 EMAC_REG_EMAC_MDIO_COMM);
2985 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2986 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2990 if (val & EMAC_MDIO_COMM_START_BUSY) {
2991 DP(NETIF_MSG_LINK, "read phy register failed\n");
2992 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2997 /* Work around for E3 A0 */
2998 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2999 phy->flags ^= FLAGS_DUMMY_READ;
3000 if (phy->flags & FLAGS_DUMMY_READ) {
3002 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3009 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3010 u8 devad, u16 reg, u16 val)
3018 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3019 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3020 EMAC_MDIO_COMM_START_BUSY);
3021 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3023 for (i = 0; i < 50; i++) {
3026 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3027 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3032 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3033 DP(NETIF_MSG_LINK, "write phy register failed\n");
3034 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3039 tmp = ((phy->addr << 21) | (devad << 16) | val |
3040 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3041 EMAC_MDIO_COMM_START_BUSY);
3042 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3044 for (i = 0; i < 50; i++) {
3047 tmp = REG_RD(bp, phy->mdio_ctrl +
3048 EMAC_REG_EMAC_MDIO_COMM);
3049 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3054 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3055 DP(NETIF_MSG_LINK, "write phy register failed\n");
3056 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3060 /* Work around for E3 A0 */
3061 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3062 phy->flags ^= FLAGS_DUMMY_READ;
3063 if (phy->flags & FLAGS_DUMMY_READ) {
3065 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3073 /******************************************************************/
3074 /* BSC access functions from E3 */
3075 /******************************************************************/
3076 static void bnx2x_bsc_module_sel(struct link_params *params)
3079 u32 board_cfg, sfp_ctrl;
3080 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3081 struct bnx2x *bp = params->bp;
3082 u8 port = params->port;
3083 /* Read I2C output PINs */
3084 board_cfg = REG_RD(bp, params->shmem_base +
3085 offsetof(struct shmem_region,
3086 dev_info.shared_hw_config.board));
3087 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3088 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3089 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3091 /* Read I2C output value */
3092 sfp_ctrl = REG_RD(bp, params->shmem_base +
3093 offsetof(struct shmem_region,
3094 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3095 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3096 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3097 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3098 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3099 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3102 static int bnx2x_bsc_read(struct link_params *params,
3103 struct bnx2x_phy *phy,
3112 struct bnx2x *bp = params->bp;
3114 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3115 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3119 if (xfer_cnt > 16) {
3120 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3124 bnx2x_bsc_module_sel(params);
3126 xfer_cnt = 16 - lc_addr;
3128 /* enable the engine */
3129 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3130 val |= MCPR_IMC_COMMAND_ENABLE;
3131 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3133 /* program slave device ID */
3134 val = (sl_devid << 16) | sl_addr;
3135 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3137 /* start xfer with 0 byte to update the address pointer ???*/
3138 val = (MCPR_IMC_COMMAND_ENABLE) |
3139 (MCPR_IMC_COMMAND_WRITE_OP <<
3140 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3141 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3142 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3144 /* poll for completion */
3146 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3147 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3149 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3151 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3160 /* start xfer with read op */
3161 val = (MCPR_IMC_COMMAND_ENABLE) |
3162 (MCPR_IMC_COMMAND_READ_OP <<
3163 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3164 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3166 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3168 /* poll for completion */
3170 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3171 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3173 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3175 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3183 for (i = (lc_addr >> 2); i < 4; i++) {
3184 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3186 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3187 ((data_array[i] & 0x0000ff00) << 8) |
3188 ((data_array[i] & 0x00ff0000) >> 8) |
3189 ((data_array[i] & 0xff000000) >> 24);
3195 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3196 u8 devad, u16 reg, u16 or_val)
3199 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3200 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3203 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3204 u8 devad, u16 reg, u16 *ret_val)
3208 * Probe for the phy according to the given phy_addr, and execute
3209 * the read request on it
3211 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3212 if (params->phy[phy_index].addr == phy_addr) {
3213 return bnx2x_cl45_read(params->bp,
3214 ¶ms->phy[phy_index], devad,
3221 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3222 u8 devad, u16 reg, u16 val)
3226 * Probe for the phy according to the given phy_addr, and execute
3227 * the write request on it
3229 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3230 if (params->phy[phy_index].addr == phy_addr) {
3231 return bnx2x_cl45_write(params->bp,
3232 ¶ms->phy[phy_index], devad,
3238 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3239 struct link_params *params)
3242 struct bnx2x *bp = params->bp;
3243 u32 path_swap, path_swap_ovr;
3247 port = params->port;
3249 if (bnx2x_is_4_port_mode(bp)) {
3250 u32 port_swap, port_swap_ovr;
3252 /*figure out path swap value */
3253 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3254 if (path_swap_ovr & 0x1)
3255 path_swap = (path_swap_ovr & 0x2);
3257 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3262 /*figure out port swap value */
3263 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3264 if (port_swap_ovr & 0x1)
3265 port_swap = (port_swap_ovr & 0x2);
3267 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3272 lane = (port<<1) + path;
3273 } else { /* two port mode - no port swap */
3275 /*figure out path swap value */
3277 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3278 if (path_swap_ovr & 0x1) {
3279 path_swap = (path_swap_ovr & 0x2);
3282 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3292 static void bnx2x_set_aer_mmd(struct link_params *params,
3293 struct bnx2x_phy *phy)
3296 u16 offset, aer_val;
3297 struct bnx2x *bp = params->bp;
3298 ser_lane = ((params->lane_config &
3299 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3300 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3302 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3303 (phy->addr + ser_lane) : 0;
3305 if (USES_WARPCORE(bp)) {
3306 aer_val = bnx2x_get_warpcore_lane(phy, params);
3308 * In Dual-lane mode, two lanes are joined together,
3309 * so in order to configure them, the AER broadcast method is
3311 * 0x200 is the broadcast address for lanes 0,1
3312 * 0x201 is the broadcast address for lanes 2,3
3314 if (phy->flags & FLAGS_WC_DUAL_MODE)
3315 aer_val = (aer_val >> 1) | 0x200;
3316 } else if (CHIP_IS_E2(bp))
3317 aer_val = 0x3800 + offset - 1;
3319 aer_val = 0x3800 + offset;
3320 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3321 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3322 MDIO_AER_BLOCK_AER_REG, aer_val);
3326 /******************************************************************/
3327 /* Internal phy section */
3328 /******************************************************************/
3330 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3332 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3335 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3336 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3338 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3344 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3348 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3350 val = SERDES_RESET_BITS << (port*16);
3352 /* reset and unreset the SerDes/XGXS */
3353 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3355 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3357 bnx2x_set_serdes_access(bp, port);
3359 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3360 DEFAULT_PHY_DEV_ADDR);
3363 static void bnx2x_xgxs_deassert(struct link_params *params)
3365 struct bnx2x *bp = params->bp;
3368 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3369 port = params->port;
3371 val = XGXS_RESET_BITS << (port*16);
3373 /* reset and unreset the SerDes/XGXS */
3374 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3379 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3380 params->phy[INT_PHY].def_md_devad);
3383 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3384 struct link_params *params, u16 *ieee_fc)
3386 struct bnx2x *bp = params->bp;
3387 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3389 * resolve pause mode and advertisement Please refer to Table
3390 * 28B-3 of the 802.3ab-1999 spec
3393 switch (phy->req_flow_ctrl) {
3394 case BNX2X_FLOW_CTRL_AUTO:
3395 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3396 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3399 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3402 case BNX2X_FLOW_CTRL_TX:
3403 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3406 case BNX2X_FLOW_CTRL_RX:
3407 case BNX2X_FLOW_CTRL_BOTH:
3408 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3411 case BNX2X_FLOW_CTRL_NONE:
3413 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3416 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3419 static void set_phy_vars(struct link_params *params,
3420 struct link_vars *vars)
3422 struct bnx2x *bp = params->bp;
3423 u8 actual_phy_idx, phy_index, link_cfg_idx;
3424 u8 phy_config_swapped = params->multi_phy_config &
3425 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3426 for (phy_index = INT_PHY; phy_index < params->num_phys;
3428 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3429 actual_phy_idx = phy_index;
3430 if (phy_config_swapped) {
3431 if (phy_index == EXT_PHY1)
3432 actual_phy_idx = EXT_PHY2;
3433 else if (phy_index == EXT_PHY2)
3434 actual_phy_idx = EXT_PHY1;
3436 params->phy[actual_phy_idx].req_flow_ctrl =
3437 params->req_flow_ctrl[link_cfg_idx];
3439 params->phy[actual_phy_idx].req_line_speed =
3440 params->req_line_speed[link_cfg_idx];
3442 params->phy[actual_phy_idx].speed_cap_mask =
3443 params->speed_cap_mask[link_cfg_idx];
3445 params->phy[actual_phy_idx].req_duplex =
3446 params->req_duplex[link_cfg_idx];
3448 if (params->req_line_speed[link_cfg_idx] ==
3450 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3452 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3453 " speed_cap_mask %x\n",
3454 params->phy[actual_phy_idx].req_flow_ctrl,
3455 params->phy[actual_phy_idx].req_line_speed,
3456 params->phy[actual_phy_idx].speed_cap_mask);
3460 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3461 struct bnx2x_phy *phy,
3462 struct link_vars *vars)
3465 struct bnx2x *bp = params->bp;
3466 /* read modify write pause advertizing */
3467 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3469 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3471 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3472 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3473 if ((vars->ieee_fc &
3474 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3476 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3478 if ((vars->ieee_fc &
3479 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3480 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3481 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3483 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3487 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3489 switch (pause_result) { /* ASYM P ASYM P */
3490 case 0xb: /* 1 0 1 1 */
3491 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3494 case 0xe: /* 1 1 1 0 */
3495 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3498 case 0x5: /* 0 1 0 1 */
3499 case 0x7: /* 0 1 1 1 */
3500 case 0xd: /* 1 1 0 1 */
3501 case 0xf: /* 1 1 1 1 */
3502 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3508 if (pause_result & (1<<0))
3509 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3510 if (pause_result & (1<<1))
3511 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3514 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3515 struct link_params *params,
3516 struct link_vars *vars)
3518 struct bnx2x *bp = params->bp;
3519 u16 ld_pause; /* local */
3520 u16 lp_pause; /* link partner */
3525 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3527 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3528 vars->flow_ctrl = phy->req_flow_ctrl;
3529 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3530 vars->flow_ctrl = params->req_fc_auto_adv;
3531 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3533 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3534 bnx2x_cl22_read(bp, phy,
3536 bnx2x_cl22_read(bp, phy,
3539 bnx2x_cl45_read(bp, phy,
3541 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3542 bnx2x_cl45_read(bp, phy,
3544 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3546 pause_result = (ld_pause &
3547 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3548 pause_result |= (lp_pause &
3549 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3550 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3552 bnx2x_pause_resolve(vars, pause_result);
3556 /******************************************************************/
3557 /* Warpcore section */
3558 /******************************************************************/
3559 /* The init_internal_warpcore should mirror the xgxs,
3560 * i.e. reset the lane (if needed), set aer for the
3561 * init configuration, and set/clear SGMII flag. Internal
3562 * phy init is done purely in phy_init stage.
3564 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3565 struct link_params *params,
3566 struct link_vars *vars) {
3567 u16 val16 = 0, lane, bam37 = 0;
3568 struct bnx2x *bp = params->bp;
3569 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3570 /* Check adding advertisement for 1G KX */
3571 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3572 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3573 (vars->line_speed == SPEED_1000)) {
3577 /* Enable CL37 1G Parallel Detect */
3578 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3579 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3580 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3581 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3582 (sd_digital | 0x1));
3584 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3586 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3587 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3588 (vars->line_speed == SPEED_10000)) {
3589 /* Check adding advertisement for 10G KR */
3591 /* Enable 10G Parallel Detect */
3592 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3593 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3595 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3598 /* Set Transmit PMD settings */
3599 lane = bnx2x_get_warpcore_lane(phy, params);
3600 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3601 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3602 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3603 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3604 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3605 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3606 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3608 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3609 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3611 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3612 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3615 /* Advertised speeds */
3616 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3617 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3619 /* Enable CL37 BAM */
3620 if (REG_RD(bp, params->shmem_base +
3621 offsetof(struct shmem_region, dev_info.
3622 port_hw_config[params->port].default_cfg)) &
3623 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3624 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3625 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3626 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3627 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3628 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3631 /* Advertise pause */
3632 bnx2x_ext_phy_set_pause(params, phy, vars);
3634 /* Enable Autoneg */
3635 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3636 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3638 /* Over 1G - AN local device user page 1 */
3639 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3640 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3642 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3643 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3645 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3646 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3649 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3650 struct link_params *params,
3651 struct link_vars *vars)
3653 struct bnx2x *bp = params->bp;
3656 /* Disable Autoneg */
3657 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3658 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3660 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3661 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3663 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3664 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3666 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3667 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3669 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3670 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3672 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3673 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3675 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3676 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3678 /* Disable CL36 PCS Tx */
3679 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3680 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3682 /* Double Wide Single Data Rate @ pll rate */
3683 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3684 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3686 /* Leave cl72 training enable, needed for KR */
3687 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3688 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3691 /* Leave CL72 enabled */
3692 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3693 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3695 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3696 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3699 /* Set speed via PMA/PMD register */
3700 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3701 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3703 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3704 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3706 /*Enable encoded forced speed */
3707 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3708 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3710 /* Turn TX scramble payload only the 64/66 scrambler */
3711 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3712 MDIO_WC_REG_TX66_CONTROL, 0x9);
3714 /* Turn RX scramble payload only the 64/66 scrambler */
3715 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3716 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3718 /* set and clear loopback to cause a reset to 64/66 decoder */
3719 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3720 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3721 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3726 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3727 struct link_params *params,
3730 struct bnx2x *bp = params->bp;
3731 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3732 /* Hold rxSeqStart */
3733 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3734 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3735 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3738 /* Hold tx_fifo_reset */
3739 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3740 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3741 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3742 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3744 /* Disable CL73 AN */
3745 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3747 /* Disable 100FX Enable and Auto-Detect */
3748 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3749 MDIO_WC_REG_FX100_CTRL1, &val);
3750 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3751 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3753 /* Disable 100FX Idle detect */
3754 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3755 MDIO_WC_REG_FX100_CTRL3, &val);
3756 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3757 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3759 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3760 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3761 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3762 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3765 /* Turn off auto-detect & fiber mode */
3766 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3767 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3768 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3769 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3772 /* Set filter_force_link, disable_false_link and parallel_detect */
3773 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3774 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3775 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3777 ((val | 0x0006) & 0xFFFE));
3780 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3783 misc1_val &= ~(0x1f);
3787 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3788 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3789 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3791 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3792 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3793 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3797 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3798 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3799 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3801 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3802 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3803 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3805 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3806 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3808 /* Set Transmit PMD settings */
3809 lane = bnx2x_get_warpcore_lane(phy, params);
3810 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3811 MDIO_WC_REG_TX_FIR_TAP,
3812 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3813 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3817 /* Enable fiber mode, enable and invert sig_det */
3818 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3819 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3820 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3821 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3823 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3824 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3825 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3826 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3829 /* 10G XFI Full Duplex */
3830 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3831 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3833 /* Release tx_fifo_reset */
3834 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3835 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3836 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3839 /* Release rxSeqStart */
3840 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3842 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3843 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3846 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3847 struct bnx2x_phy *phy)
3849 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3852 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3853 struct bnx2x_phy *phy,
3856 /* Rx0 anaRxControl1G */
3857 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3858 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3860 /* Rx2 anaRxControl1G */
3861 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3862 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3864 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3865 MDIO_WC_REG_RX66_SCW0, 0xE070);
3867 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3868 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3870 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3873 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3874 MDIO_WC_REG_RX66_SCW3, 0x8090);
3876 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3879 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3882 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3883 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3885 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3886 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3888 /* Serdes Digital Misc1 */
3889 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3890 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3892 /* Serdes Digital4 Misc3 */
3893 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3896 /* Set Transmit PMD settings */
3897 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3898 MDIO_WC_REG_TX_FIR_TAP,
3899 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3900 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3901 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3902 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3905 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3906 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3907 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3910 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3911 struct link_params *params,
3914 struct bnx2x *bp = params->bp;
3915 u16 val16, digctrl_kx1, digctrl_kx2;
3918 lane = bnx2x_get_warpcore_lane(phy, params);
3920 /* Clear XFI clock comp in non-10G single lane mode. */
3921 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3922 MDIO_WC_REG_RX66_CONTROL, &val16);
3923 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3924 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3926 if (phy->req_line_speed == SPEED_AUTO_NEG) {
3928 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3929 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3930 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3933 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3935 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3938 switch (phy->req_line_speed) {
3948 DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3949 "\n", phy->req_line_speed);
3953 if (phy->req_duplex == DUPLEX_FULL)
3956 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3959 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3960 phy->req_line_speed);
3961 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3962 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3963 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
3966 /* SGMII Slave mode and disable signal detect */
3967 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3968 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3972 digctrl_kx1 &= 0xff4a;
3974 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3975 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3978 /* Turn off parallel detect */
3979 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3980 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3981 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3982 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3983 (digctrl_kx2 & ~(1<<2)));
3985 /* Re-enable parallel detect */
3986 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3987 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3988 (digctrl_kx2 | (1<<2)));
3990 /* Enable autodet */
3991 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3993 (digctrl_kx1 | 0x10));
3996 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
3997 struct bnx2x_phy *phy,
4001 /* Take lane out of reset after configuration is finished */
4002 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4003 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4008 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4009 MDIO_WC_REG_DIGITAL5_MISC6, val);
4010 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4011 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4015 /* Clear SFI/XFI link settings registers */
4016 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4017 struct link_params *params,
4020 struct bnx2x *bp = params->bp;
4023 /* Set XFI clock comp as default. */
4024 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025 MDIO_WC_REG_RX66_CONTROL, &val16);
4026 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4027 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4029 bnx2x_warpcore_reset_lane(bp, phy, 1);
4030 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4031 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4033 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4034 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4035 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4037 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4038 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4039 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4041 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4042 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4043 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4045 lane = bnx2x_get_warpcore_lane(phy, params);
4046 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4048 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4049 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4050 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4052 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4053 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4054 bnx2x_warpcore_reset_lane(bp, phy, 0);
4057 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4059 u32 shmem_base, u8 port,
4060 u8 *gpio_num, u8 *gpio_port)
4065 if (CHIP_IS_E3(bp)) {
4066 cfg_pin = (REG_RD(bp, shmem_base +
4067 offsetof(struct shmem_region,
4068 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4069 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4070 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4073 * Should not happen. This function called upon interrupt
4074 * triggered by GPIO ( since EPIO can only generate interrupts
4076 * So if this function was called and none of the GPIOs was set,
4077 * it means the shit hit the fan.
4079 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4080 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4081 DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4082 "module detect indication\n",
4087 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4088 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4090 *gpio_num = MISC_REGISTERS_GPIO_3;
4093 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4097 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4098 struct link_params *params)
4100 struct bnx2x *bp = params->bp;
4101 u8 gpio_num, gpio_port;
4103 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4104 params->shmem_base, params->port,
4105 &gpio_num, &gpio_port) != 0)
4107 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4109 /* Call the handling function in case module is detected */
4116 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4117 struct link_params *params,
4118 struct link_vars *vars)
4120 struct bnx2x *bp = params->bp;
4123 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4124 serdes_net_if = (REG_RD(bp, params->shmem_base +
4125 offsetof(struct shmem_region, dev_info.
4126 port_hw_config[params->port].default_cfg)) &
4127 PORT_HW_CFG_NET_SERDES_IF_MASK);
4128 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4129 "serdes_net_if = 0x%x\n",
4130 vars->line_speed, serdes_net_if);
4131 bnx2x_set_aer_mmd(params, phy);
4133 vars->phy_flags |= PHY_XGXS_FLAG;
4134 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4135 (phy->req_line_speed &&
4136 ((phy->req_line_speed == SPEED_100) ||
4137 (phy->req_line_speed == SPEED_10)))) {
4138 vars->phy_flags |= PHY_SGMII_FLAG;
4139 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4140 bnx2x_warpcore_clear_regs(phy, params, lane);
4141 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4143 switch (serdes_net_if) {
4144 case PORT_HW_CFG_NET_SERDES_IF_KR:
4145 /* Enable KR Auto Neg */
4146 if (params->loopback_mode == LOOPBACK_NONE)
4147 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4149 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4150 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4154 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4155 bnx2x_warpcore_clear_regs(phy, params, lane);
4156 if (vars->line_speed == SPEED_10000) {
4157 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4158 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4160 if (SINGLE_MEDIA_DIRECT(params)) {
4161 DP(NETIF_MSG_LINK, "1G Fiber\n");
4164 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4167 bnx2x_warpcore_set_sgmii_speed(phy,
4174 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4176 bnx2x_warpcore_clear_regs(phy, params, lane);
4177 if (vars->line_speed == SPEED_10000) {
4178 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4179 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4180 } else if (vars->line_speed == SPEED_1000) {
4181 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4182 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4184 /* Issue Module detection */
4185 if (bnx2x_is_sfp_module_plugged(phy, params))
4186 bnx2x_sfp_module_detection(phy, params);
4189 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4190 if (vars->line_speed != SPEED_20000) {
4191 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4194 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4195 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4196 /* Issue Module detection */
4198 bnx2x_sfp_module_detection(phy, params);
4201 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4202 if (vars->line_speed != SPEED_20000) {
4203 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4206 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4207 bnx2x_warpcore_set_20G_KR2(bp, phy);
4211 DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4212 "0x%x\n", serdes_net_if);
4217 /* Take lane out of reset after configuration is finished */
4218 bnx2x_warpcore_reset_lane(bp, phy, 0);
4219 DP(NETIF_MSG_LINK, "Exit config init\n");
4222 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4223 struct bnx2x_phy *phy,
4226 struct bnx2x *bp = params->bp;
4228 u8 port = params->port;
4230 cfg_pin = REG_RD(bp, params->shmem_base +
4231 offsetof(struct shmem_region,
4232 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4233 PORT_HW_CFG_TX_LASER_MASK;
4234 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4235 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4236 /* For 20G, the expected pin to be used is 3 pins after the current */
4238 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4239 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4240 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4243 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4244 struct link_params *params)
4246 struct bnx2x *bp = params->bp;
4248 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4249 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4250 bnx2x_set_aer_mmd(params, phy);
4251 /* Global register */
4252 bnx2x_warpcore_reset_lane(bp, phy, 1);
4254 /* Clear loopback settings (if any) */
4256 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4257 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4258 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4262 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4263 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4264 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4267 /* Update those 1-copy registers */
4268 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4269 MDIO_AER_BLOCK_AER_REG, 0);
4270 /* Enable 1G MDIO (1-copy) */
4271 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4272 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4274 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4275 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4278 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4279 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4280 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4281 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4286 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4287 struct link_params *params)
4289 struct bnx2x *bp = params->bp;
4292 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4293 params->loopback_mode, phy->req_line_speed);
4295 if (phy->req_line_speed < SPEED_10000) {
4298 /* Update those 1-copy registers */
4299 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4300 MDIO_AER_BLOCK_AER_REG, 0);
4301 /* Enable 1G MDIO (1-copy) */
4302 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4303 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4305 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4306 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4308 /* Set 1G loopback based on lane (1-copy) */
4309 lane = bnx2x_get_warpcore_lane(phy, params);
4310 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4311 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4312 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4313 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4316 /* Switch back to 4-copy registers */
4317 bnx2x_set_aer_mmd(params, phy);
4318 /* Global loopback, not recommended. */
4319 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4320 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4321 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4322 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4326 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4327 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4328 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4329 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4332 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4333 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4334 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4335 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4340 void bnx2x_link_status_update(struct link_params *params,
4341 struct link_vars *vars)
4343 struct bnx2x *bp = params->bp;
4345 u8 port = params->port;
4346 u32 sync_offset, media_types;
4347 /* Update PHY configuration */
4348 set_phy_vars(params, vars);
4350 vars->link_status = REG_RD(bp, params->shmem_base +
4351 offsetof(struct shmem_region,
4352 port_mb[port].link_status));
4354 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4355 vars->phy_flags = PHY_XGXS_FLAG;
4356 if (vars->link_up) {
4357 DP(NETIF_MSG_LINK, "phy link up\n");
4359 vars->phy_link_up = 1;
4360 vars->duplex = DUPLEX_FULL;
4361 switch (vars->link_status &
4362 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4364 vars->duplex = DUPLEX_HALF;
4367 vars->line_speed = SPEED_10;
4371 vars->duplex = DUPLEX_HALF;
4375 vars->line_speed = SPEED_100;
4379 vars->duplex = DUPLEX_HALF;
4382 vars->line_speed = SPEED_1000;
4386 vars->duplex = DUPLEX_HALF;
4389 vars->line_speed = SPEED_2500;
4393 vars->line_speed = SPEED_10000;
4396 vars->line_speed = SPEED_20000;
4401 vars->flow_ctrl = 0;
4402 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4403 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4405 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4406 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4408 if (!vars->flow_ctrl)
4409 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4411 if (vars->line_speed &&
4412 ((vars->line_speed == SPEED_10) ||
4413 (vars->line_speed == SPEED_100))) {
4414 vars->phy_flags |= PHY_SGMII_FLAG;
4416 vars->phy_flags &= ~PHY_SGMII_FLAG;
4418 if (vars->line_speed &&
4419 USES_WARPCORE(bp) &&
4420 (vars->line_speed == SPEED_1000))
4421 vars->phy_flags |= PHY_SGMII_FLAG;
4422 /* anything 10 and over uses the bmac */
4423 link_10g_plus = (vars->line_speed >= SPEED_10000);
4425 if (link_10g_plus) {
4426 if (USES_WARPCORE(bp))
4427 vars->mac_type = MAC_TYPE_XMAC;
4429 vars->mac_type = MAC_TYPE_BMAC;
4431 if (USES_WARPCORE(bp))
4432 vars->mac_type = MAC_TYPE_UMAC;
4434 vars->mac_type = MAC_TYPE_EMAC;
4436 } else { /* link down */
4437 DP(NETIF_MSG_LINK, "phy link down\n");
4439 vars->phy_link_up = 0;
4441 vars->line_speed = 0;
4442 vars->duplex = DUPLEX_FULL;
4443 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4445 /* indicate no mac active */
4446 vars->mac_type = MAC_TYPE_NONE;
4449 /* Sync media type */
4450 sync_offset = params->shmem_base +
4451 offsetof(struct shmem_region,
4452 dev_info.port_hw_config[port].media_type);
4453 media_types = REG_RD(bp, sync_offset);
4455 params->phy[INT_PHY].media_type =
4456 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4457 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4458 params->phy[EXT_PHY1].media_type =
4459 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4460 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4461 params->phy[EXT_PHY2].media_type =
4462 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4463 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4464 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4466 /* Sync AEU offset */
4467 sync_offset = params->shmem_base +
4468 offsetof(struct shmem_region,
4469 dev_info.port_hw_config[port].aeu_int_mask);
4471 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4473 /* Sync PFC status */
4474 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4475 params->feature_config_flags |=
4476 FEATURE_CONFIG_PFC_ENABLED;
4478 params->feature_config_flags &=
4479 ~FEATURE_CONFIG_PFC_ENABLED;
4481 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4482 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4483 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4484 vars->line_speed, vars->duplex, vars->flow_ctrl);
4488 static void bnx2x_set_master_ln(struct link_params *params,
4489 struct bnx2x_phy *phy)
4491 struct bnx2x *bp = params->bp;
4492 u16 new_master_ln, ser_lane;
4493 ser_lane = ((params->lane_config &
4494 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4495 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4497 /* set the master_ln for AN */
4498 CL22_RD_OVER_CL45(bp, phy,
4499 MDIO_REG_BANK_XGXS_BLOCK2,
4500 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4503 CL22_WR_OVER_CL45(bp, phy,
4504 MDIO_REG_BANK_XGXS_BLOCK2 ,
4505 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4506 (new_master_ln | ser_lane));
4509 static int bnx2x_reset_unicore(struct link_params *params,
4510 struct bnx2x_phy *phy,
4513 struct bnx2x *bp = params->bp;
4516 CL22_RD_OVER_CL45(bp, phy,
4517 MDIO_REG_BANK_COMBO_IEEE0,
4518 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4520 /* reset the unicore */
4521 CL22_WR_OVER_CL45(bp, phy,
4522 MDIO_REG_BANK_COMBO_IEEE0,
4523 MDIO_COMBO_IEEE0_MII_CONTROL,
4525 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4527 bnx2x_set_serdes_access(bp, params->port);
4529 /* wait for the reset to self clear */
4530 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4533 /* the reset erased the previous bank value */
4534 CL22_RD_OVER_CL45(bp, phy,
4535 MDIO_REG_BANK_COMBO_IEEE0,
4536 MDIO_COMBO_IEEE0_MII_CONTROL,
4539 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4545 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4548 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4553 static void bnx2x_set_swap_lanes(struct link_params *params,
4554 struct bnx2x_phy *phy)
4556 struct bnx2x *bp = params->bp;
4558 * Each two bits represents a lane number:
4559 * No swap is 0123 => 0x1b no need to enable the swap
4561 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4563 ser_lane = ((params->lane_config &
4564 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4565 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4566 rx_lane_swap = ((params->lane_config &
4567 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4568 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4569 tx_lane_swap = ((params->lane_config &
4570 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4571 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4573 if (rx_lane_swap != 0x1b) {
4574 CL22_WR_OVER_CL45(bp, phy,
4575 MDIO_REG_BANK_XGXS_BLOCK2,
4576 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4578 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4579 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4581 CL22_WR_OVER_CL45(bp, phy,
4582 MDIO_REG_BANK_XGXS_BLOCK2,
4583 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4586 if (tx_lane_swap != 0x1b) {
4587 CL22_WR_OVER_CL45(bp, phy,
4588 MDIO_REG_BANK_XGXS_BLOCK2,
4589 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4591 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4593 CL22_WR_OVER_CL45(bp, phy,
4594 MDIO_REG_BANK_XGXS_BLOCK2,
4595 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4599 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4600 struct link_params *params)
4602 struct bnx2x *bp = params->bp;
4604 CL22_RD_OVER_CL45(bp, phy,
4605 MDIO_REG_BANK_SERDES_DIGITAL,
4606 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4608 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4609 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4611 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4612 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4613 phy->speed_cap_mask, control2);
4614 CL22_WR_OVER_CL45(bp, phy,
4615 MDIO_REG_BANK_SERDES_DIGITAL,
4616 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4619 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4620 (phy->speed_cap_mask &
4621 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4622 DP(NETIF_MSG_LINK, "XGXS\n");
4624 CL22_WR_OVER_CL45(bp, phy,
4625 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4626 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4627 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4629 CL22_RD_OVER_CL45(bp, phy,
4630 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4631 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4636 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4638 CL22_WR_OVER_CL45(bp, phy,
4639 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4640 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4643 /* Disable parallel detection of HiG */
4644 CL22_WR_OVER_CL45(bp, phy,
4645 MDIO_REG_BANK_XGXS_BLOCK2,
4646 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4647 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4648 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4652 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4653 struct link_params *params,
4654 struct link_vars *vars,
4657 struct bnx2x *bp = params->bp;
4661 CL22_RD_OVER_CL45(bp, phy,
4662 MDIO_REG_BANK_COMBO_IEEE0,
4663 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4665 /* CL37 Autoneg Enabled */
4666 if (vars->line_speed == SPEED_AUTO_NEG)
4667 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4668 else /* CL37 Autoneg Disabled */
4669 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4670 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4672 CL22_WR_OVER_CL45(bp, phy,
4673 MDIO_REG_BANK_COMBO_IEEE0,
4674 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4676 /* Enable/Disable Autodetection */
4678 CL22_RD_OVER_CL45(bp, phy,
4679 MDIO_REG_BANK_SERDES_DIGITAL,
4680 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4681 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4682 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4683 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4684 if (vars->line_speed == SPEED_AUTO_NEG)
4685 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4687 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4689 CL22_WR_OVER_CL45(bp, phy,
4690 MDIO_REG_BANK_SERDES_DIGITAL,
4691 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4693 /* Enable TetonII and BAM autoneg */
4694 CL22_RD_OVER_CL45(bp, phy,
4695 MDIO_REG_BANK_BAM_NEXT_PAGE,
4696 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4698 if (vars->line_speed == SPEED_AUTO_NEG) {
4699 /* Enable BAM aneg Mode and TetonII aneg Mode */
4700 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4701 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4703 /* TetonII and BAM Autoneg Disabled */
4704 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4705 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4707 CL22_WR_OVER_CL45(bp, phy,
4708 MDIO_REG_BANK_BAM_NEXT_PAGE,
4709 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4713 /* Enable Cl73 FSM status bits */
4714 CL22_WR_OVER_CL45(bp, phy,
4715 MDIO_REG_BANK_CL73_USERB0,
4716 MDIO_CL73_USERB0_CL73_UCTRL,
4719 /* Enable BAM Station Manager*/
4720 CL22_WR_OVER_CL45(bp, phy,
4721 MDIO_REG_BANK_CL73_USERB0,
4722 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4723 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4724 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4725 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4727 /* Advertise CL73 link speeds */
4728 CL22_RD_OVER_CL45(bp, phy,
4729 MDIO_REG_BANK_CL73_IEEEB1,
4730 MDIO_CL73_IEEEB1_AN_ADV2,
4732 if (phy->speed_cap_mask &
4733 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4734 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4735 if (phy->speed_cap_mask &
4736 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4737 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4739 CL22_WR_OVER_CL45(bp, phy,
4740 MDIO_REG_BANK_CL73_IEEEB1,
4741 MDIO_CL73_IEEEB1_AN_ADV2,
4744 /* CL73 Autoneg Enabled */
4745 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4747 } else /* CL73 Autoneg Disabled */
4750 CL22_WR_OVER_CL45(bp, phy,
4751 MDIO_REG_BANK_CL73_IEEEB0,
4752 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4755 /* program SerDes, forced speed */
4756 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4757 struct link_params *params,
4758 struct link_vars *vars)
4760 struct bnx2x *bp = params->bp;
4763 /* program duplex, disable autoneg and sgmii*/
4764 CL22_RD_OVER_CL45(bp, phy,
4765 MDIO_REG_BANK_COMBO_IEEE0,
4766 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4767 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4768 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4769 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4770 if (phy->req_duplex == DUPLEX_FULL)
4771 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4772 CL22_WR_OVER_CL45(bp, phy,
4773 MDIO_REG_BANK_COMBO_IEEE0,
4774 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4778 * - needed only if the speed is greater than 1G (2.5G or 10G)
4780 CL22_RD_OVER_CL45(bp, phy,
4781 MDIO_REG_BANK_SERDES_DIGITAL,
4782 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4783 /* clearing the speed value before setting the right speed */
4784 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4786 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4787 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4789 if (!((vars->line_speed == SPEED_1000) ||
4790 (vars->line_speed == SPEED_100) ||
4791 (vars->line_speed == SPEED_10))) {
4793 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4794 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4795 if (vars->line_speed == SPEED_10000)
4797 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4800 CL22_WR_OVER_CL45(bp, phy,
4801 MDIO_REG_BANK_SERDES_DIGITAL,
4802 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4806 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4807 struct link_params *params)
4809 struct bnx2x *bp = params->bp;
4812 /* configure the 48 bits for BAM AN */
4814 /* set extended capabilities */
4815 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4816 val |= MDIO_OVER_1G_UP1_2_5G;
4817 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4818 val |= MDIO_OVER_1G_UP1_10G;
4819 CL22_WR_OVER_CL45(bp, phy,
4820 MDIO_REG_BANK_OVER_1G,
4821 MDIO_OVER_1G_UP1, val);
4823 CL22_WR_OVER_CL45(bp, phy,
4824 MDIO_REG_BANK_OVER_1G,
4825 MDIO_OVER_1G_UP3, 0x400);
4828 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4829 struct link_params *params,
4832 struct bnx2x *bp = params->bp;
4834 /* for AN, we are always publishing full duplex */
4836 CL22_WR_OVER_CL45(bp, phy,
4837 MDIO_REG_BANK_COMBO_IEEE0,
4838 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4839 CL22_RD_OVER_CL45(bp, phy,
4840 MDIO_REG_BANK_CL73_IEEEB1,
4841 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4842 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4843 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4844 CL22_WR_OVER_CL45(bp, phy,
4845 MDIO_REG_BANK_CL73_IEEEB1,
4846 MDIO_CL73_IEEEB1_AN_ADV1, val);
4849 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4850 struct link_params *params,
4853 struct bnx2x *bp = params->bp;
4856 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4857 /* Enable and restart BAM/CL37 aneg */
4860 CL22_RD_OVER_CL45(bp, phy,
4861 MDIO_REG_BANK_CL73_IEEEB0,
4862 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4865 CL22_WR_OVER_CL45(bp, phy,
4866 MDIO_REG_BANK_CL73_IEEEB0,
4867 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4869 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4870 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4873 CL22_RD_OVER_CL45(bp, phy,
4874 MDIO_REG_BANK_COMBO_IEEE0,
4875 MDIO_COMBO_IEEE0_MII_CONTROL,
4878 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4880 CL22_WR_OVER_CL45(bp, phy,
4881 MDIO_REG_BANK_COMBO_IEEE0,
4882 MDIO_COMBO_IEEE0_MII_CONTROL,
4884 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4885 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4889 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4890 struct link_params *params,
4891 struct link_vars *vars)
4893 struct bnx2x *bp = params->bp;
4896 /* in SGMII mode, the unicore is always slave */
4898 CL22_RD_OVER_CL45(bp, phy,
4899 MDIO_REG_BANK_SERDES_DIGITAL,
4900 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4902 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4903 /* set sgmii mode (and not fiber) */
4904 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4905 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4906 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4907 CL22_WR_OVER_CL45(bp, phy,
4908 MDIO_REG_BANK_SERDES_DIGITAL,
4909 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4912 /* if forced speed */
4913 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4914 /* set speed, disable autoneg */
4917 CL22_RD_OVER_CL45(bp, phy,
4918 MDIO_REG_BANK_COMBO_IEEE0,
4919 MDIO_COMBO_IEEE0_MII_CONTROL,
4921 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4922 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4923 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4925 switch (vars->line_speed) {
4928 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4932 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4935 /* there is nothing to set for 10M */
4938 /* invalid speed for SGMII */
4939 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4944 /* setting the full duplex */
4945 if (phy->req_duplex == DUPLEX_FULL)
4947 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4948 CL22_WR_OVER_CL45(bp, phy,
4949 MDIO_REG_BANK_COMBO_IEEE0,
4950 MDIO_COMBO_IEEE0_MII_CONTROL,
4953 } else { /* AN mode */
4954 /* enable and restart AN */
4955 bnx2x_restart_autoneg(phy, params, 0);
4964 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4965 struct link_params *params)
4967 struct bnx2x *bp = params->bp;
4968 u16 pd_10g, status2_1000x;
4969 if (phy->req_line_speed != SPEED_AUTO_NEG)
4971 CL22_RD_OVER_CL45(bp, phy,
4972 MDIO_REG_BANK_SERDES_DIGITAL,
4973 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4975 CL22_RD_OVER_CL45(bp, phy,
4976 MDIO_REG_BANK_SERDES_DIGITAL,
4977 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4979 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4980 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4985 CL22_RD_OVER_CL45(bp, phy,
4986 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4987 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4990 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4991 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
4998 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
4999 struct link_params *params,
5000 struct link_vars *vars,
5003 struct bnx2x *bp = params->bp;
5004 u16 ld_pause; /* local driver */
5005 u16 lp_pause; /* link partner */
5008 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5010 /* resolve from gp_status in case of AN complete and not sgmii */
5011 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5012 vars->flow_ctrl = phy->req_flow_ctrl;
5013 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5014 vars->flow_ctrl = params->req_fc_auto_adv;
5015 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5016 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5017 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5018 vars->flow_ctrl = params->req_fc_auto_adv;
5022 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5023 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5024 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5025 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5027 CL22_RD_OVER_CL45(bp, phy,
5028 MDIO_REG_BANK_CL73_IEEEB1,
5029 MDIO_CL73_IEEEB1_AN_ADV1,
5031 CL22_RD_OVER_CL45(bp, phy,
5032 MDIO_REG_BANK_CL73_IEEEB1,
5033 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5035 pause_result = (ld_pause &
5036 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5038 pause_result |= (lp_pause &
5039 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5041 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5044 CL22_RD_OVER_CL45(bp, phy,
5045 MDIO_REG_BANK_COMBO_IEEE0,
5046 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5048 CL22_RD_OVER_CL45(bp, phy,
5049 MDIO_REG_BANK_COMBO_IEEE0,
5050 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5052 pause_result = (ld_pause &
5053 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5054 pause_result |= (lp_pause &
5055 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5056 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5059 bnx2x_pause_resolve(vars, pause_result);
5061 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5064 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5065 struct link_params *params)
5067 struct bnx2x *bp = params->bp;
5068 u16 rx_status, ustat_val, cl37_fsm_received;
5069 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5070 /* Step 1: Make sure signal is detected */
5071 CL22_RD_OVER_CL45(bp, phy,
5075 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5076 (MDIO_RX0_RX_STATUS_SIGDET)) {
5077 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5078 "rx_status(0x80b0) = 0x%x\n", rx_status);
5079 CL22_WR_OVER_CL45(bp, phy,
5080 MDIO_REG_BANK_CL73_IEEEB0,
5081 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5082 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5085 /* Step 2: Check CL73 state machine */
5086 CL22_RD_OVER_CL45(bp, phy,
5087 MDIO_REG_BANK_CL73_USERB0,
5088 MDIO_CL73_USERB0_CL73_USTAT1,
5091 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5092 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5093 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5094 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5095 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5096 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5100 * Step 3: Check CL37 Message Pages received to indicate LP
5101 * supports only CL37
5103 CL22_RD_OVER_CL45(bp, phy,
5104 MDIO_REG_BANK_REMOTE_PHY,
5105 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5106 &cl37_fsm_received);
5107 if ((cl37_fsm_received &
5108 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5109 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5110 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5111 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5112 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5113 "misc_rx_status(0x8330) = 0x%x\n",
5118 * The combined cl37/cl73 fsm state information indicating that
5119 * we are connected to a device which does not support cl73, but
5120 * does support cl37 BAM. In this case we disable cl73 and
5121 * restart cl37 auto-neg
5125 CL22_WR_OVER_CL45(bp, phy,
5126 MDIO_REG_BANK_CL73_IEEEB0,
5127 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5129 /* Restart CL37 autoneg */
5130 bnx2x_restart_autoneg(phy, params, 0);
5131 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5134 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5135 struct link_params *params,
5136 struct link_vars *vars,
5139 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5140 vars->link_status |=
5141 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5143 if (bnx2x_direct_parallel_detect_used(phy, params))
5144 vars->link_status |=
5145 LINK_STATUS_PARALLEL_DETECTION_USED;
5147 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5148 struct link_params *params,
5149 struct link_vars *vars,
5154 struct bnx2x *bp = params->bp;
5155 if (phy->req_line_speed == SPEED_AUTO_NEG)
5156 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5158 DP(NETIF_MSG_LINK, "phy link up\n");
5160 vars->phy_link_up = 1;
5161 vars->link_status |= LINK_STATUS_LINK_UP;
5163 switch (speed_mask) {
5165 vars->line_speed = SPEED_10;
5166 if (vars->duplex == DUPLEX_FULL)
5167 vars->link_status |= LINK_10TFD;
5169 vars->link_status |= LINK_10THD;
5172 case GP_STATUS_100M:
5173 vars->line_speed = SPEED_100;
5174 if (vars->duplex == DUPLEX_FULL)
5175 vars->link_status |= LINK_100TXFD;
5177 vars->link_status |= LINK_100TXHD;
5181 case GP_STATUS_1G_KX:
5182 vars->line_speed = SPEED_1000;
5183 if (vars->duplex == DUPLEX_FULL)
5184 vars->link_status |= LINK_1000TFD;
5186 vars->link_status |= LINK_1000THD;
5189 case GP_STATUS_2_5G:
5190 vars->line_speed = SPEED_2500;
5191 if (vars->duplex == DUPLEX_FULL)
5192 vars->link_status |= LINK_2500TFD;
5194 vars->link_status |= LINK_2500THD;
5200 "link speed unsupported gp_status 0x%x\n",
5204 case GP_STATUS_10G_KX4:
5205 case GP_STATUS_10G_HIG:
5206 case GP_STATUS_10G_CX4:
5207 case GP_STATUS_10G_KR:
5208 case GP_STATUS_10G_SFI:
5209 case GP_STATUS_10G_XFI:
5210 vars->line_speed = SPEED_10000;
5211 vars->link_status |= LINK_10GTFD;
5213 case GP_STATUS_20G_DXGXS:
5214 vars->line_speed = SPEED_20000;
5215 vars->link_status |= LINK_20GTFD;
5219 "link speed unsupported gp_status 0x%x\n",
5223 } else { /* link_down */
5224 DP(NETIF_MSG_LINK, "phy link down\n");
5226 vars->phy_link_up = 0;
5228 vars->duplex = DUPLEX_FULL;
5229 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5230 vars->mac_type = MAC_TYPE_NONE;
5232 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5233 vars->phy_link_up, vars->line_speed);
5237 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5238 struct link_params *params,
5239 struct link_vars *vars)
5242 struct bnx2x *bp = params->bp;
5244 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5247 /* Read gp_status */
5248 CL22_RD_OVER_CL45(bp, phy,
5249 MDIO_REG_BANK_GP_STATUS,
5250 MDIO_GP_STATUS_TOP_AN_STATUS1,
5252 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5253 duplex = DUPLEX_FULL;
5254 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5256 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5257 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5258 gp_status, link_up, speed_mask);
5259 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5264 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5265 if (SINGLE_MEDIA_DIRECT(params)) {
5266 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5267 if (phy->req_line_speed == SPEED_AUTO_NEG)
5268 bnx2x_xgxs_an_resolve(phy, params, vars,
5271 } else { /* link_down */
5272 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5273 SINGLE_MEDIA_DIRECT(params)) {
5274 /* Check signal is detected */
5275 bnx2x_check_fallback_to_cl37(phy, params);
5279 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5280 vars->duplex, vars->flow_ctrl, vars->link_status);
5284 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5285 struct link_params *params,
5286 struct link_vars *vars)
5289 struct bnx2x *bp = params->bp;
5292 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5294 lane = bnx2x_get_warpcore_lane(phy, params);
5295 /* Read gp_status */
5296 if (phy->req_line_speed > SPEED_10000) {
5298 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5300 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5302 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5303 temp_link_up, link_up);
5306 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5308 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5309 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5310 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5311 /* Check for either KR or generic link up. */
5312 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5313 ((gp_status1 >> 12) & 0xf);
5314 link_up = gp_status1 & (1 << lane);
5315 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5317 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5318 /* Check Autoneg complete */
5319 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5320 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5322 if (gp_status4 & ((1<<12)<<lane))
5323 vars->link_status |=
5324 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5326 /* Check parallel detect used */
5327 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5328 MDIO_WC_REG_PAR_DET_10G_STATUS,
5331 vars->link_status |=
5332 LINK_STATUS_PARALLEL_DETECTION_USED;
5334 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5339 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5340 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5342 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5343 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5345 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5347 if ((lane & 1) == 0)
5352 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5355 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5356 vars->duplex, vars->flow_ctrl, vars->link_status);
5359 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5361 struct bnx2x *bp = params->bp;
5362 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5368 CL22_RD_OVER_CL45(bp, phy,
5369 MDIO_REG_BANK_OVER_1G,
5370 MDIO_OVER_1G_LP_UP2, &lp_up2);
5372 /* bits [10:7] at lp_up2, positioned at [15:12] */
5373 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5374 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5375 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5380 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5381 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5382 CL22_RD_OVER_CL45(bp, phy,
5384 MDIO_TX0_TX_DRIVER, &tx_driver);
5386 /* replace tx_driver bits [15:12] */
5388 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5389 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5390 tx_driver |= lp_up2;
5391 CL22_WR_OVER_CL45(bp, phy,
5393 MDIO_TX0_TX_DRIVER, tx_driver);
5398 static int bnx2x_emac_program(struct link_params *params,
5399 struct link_vars *vars)
5401 struct bnx2x *bp = params->bp;
5402 u8 port = params->port;
5405 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5406 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5408 (EMAC_MODE_25G_MODE |
5409 EMAC_MODE_PORT_MII_10M |
5410 EMAC_MODE_HALF_DUPLEX));
5411 switch (vars->line_speed) {
5413 mode |= EMAC_MODE_PORT_MII_10M;
5417 mode |= EMAC_MODE_PORT_MII;
5421 mode |= EMAC_MODE_PORT_GMII;
5425 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5429 /* 10G not valid for EMAC */
5430 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5435 if (vars->duplex == DUPLEX_HALF)
5436 mode |= EMAC_MODE_HALF_DUPLEX;
5438 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5441 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5445 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5446 struct link_params *params)
5450 struct bnx2x *bp = params->bp;
5452 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5453 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5454 CL22_WR_OVER_CL45(bp, phy,
5456 MDIO_RX0_RX_EQ_BOOST,
5457 phy->rx_preemphasis[i]);
5460 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5461 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5462 CL22_WR_OVER_CL45(bp, phy,
5465 phy->tx_preemphasis[i]);
5469 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5470 struct link_params *params,
5471 struct link_vars *vars)
5473 struct bnx2x *bp = params->bp;
5474 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5475 (params->loopback_mode == LOOPBACK_XGXS));
5476 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5477 if (SINGLE_MEDIA_DIRECT(params) &&
5478 (params->feature_config_flags &
5479 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5480 bnx2x_set_preemphasis(phy, params);
5482 /* forced speed requested? */
5483 if (vars->line_speed != SPEED_AUTO_NEG ||
5484 (SINGLE_MEDIA_DIRECT(params) &&
5485 params->loopback_mode == LOOPBACK_EXT)) {
5486 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5488 /* disable autoneg */
5489 bnx2x_set_autoneg(phy, params, vars, 0);
5491 /* program speed and duplex */
5492 bnx2x_program_serdes(phy, params, vars);
5494 } else { /* AN_mode */
5495 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5498 bnx2x_set_brcm_cl37_advertisement(phy, params);
5500 /* program duplex & pause advertisement (for aneg) */
5501 bnx2x_set_ieee_aneg_advertisement(phy, params,
5504 /* enable autoneg */
5505 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5507 /* enable and restart AN */
5508 bnx2x_restart_autoneg(phy, params, enable_cl73);
5511 } else { /* SGMII mode */
5512 DP(NETIF_MSG_LINK, "SGMII\n");
5514 bnx2x_initialize_sgmii_process(phy, params, vars);
5518 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5519 struct link_params *params,
5520 struct link_vars *vars)
5523 vars->phy_flags |= PHY_XGXS_FLAG;
5524 if ((phy->req_line_speed &&
5525 ((phy->req_line_speed == SPEED_100) ||
5526 (phy->req_line_speed == SPEED_10))) ||
5527 (!phy->req_line_speed &&
5528 (phy->speed_cap_mask >=
5529 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5530 (phy->speed_cap_mask <
5531 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5532 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5533 vars->phy_flags |= PHY_SGMII_FLAG;
5535 vars->phy_flags &= ~PHY_SGMII_FLAG;
5537 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5538 bnx2x_set_aer_mmd(params, phy);
5539 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5540 bnx2x_set_master_ln(params, phy);
5542 rc = bnx2x_reset_unicore(params, phy, 0);
5543 /* reset the SerDes and wait for reset bit return low */
5547 bnx2x_set_aer_mmd(params, phy);
5548 /* setting the masterLn_def again after the reset */
5549 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5550 bnx2x_set_master_ln(params, phy);
5551 bnx2x_set_swap_lanes(params, phy);
5557 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5558 struct bnx2x_phy *phy,
5559 struct link_params *params)
5562 /* Wait for soft reset to get cleared up to 1 sec */
5563 for (cnt = 0; cnt < 1000; cnt++) {
5564 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5565 bnx2x_cl22_read(bp, phy,
5566 MDIO_PMA_REG_CTRL, &ctrl);
5568 bnx2x_cl45_read(bp, phy,
5570 MDIO_PMA_REG_CTRL, &ctrl);
5571 if (!(ctrl & (1<<15)))
5577 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5580 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5584 static void bnx2x_link_int_enable(struct link_params *params)
5586 u8 port = params->port;
5588 struct bnx2x *bp = params->bp;
5590 /* Setting the status to report on link up for either XGXS or SerDes */
5591 if (CHIP_IS_E3(bp)) {
5592 mask = NIG_MASK_XGXS0_LINK_STATUS;
5593 if (!(SINGLE_MEDIA_DIRECT(params)))
5594 mask |= NIG_MASK_MI_INT;
5595 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5596 mask = (NIG_MASK_XGXS0_LINK10G |
5597 NIG_MASK_XGXS0_LINK_STATUS);
5598 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5599 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5600 params->phy[INT_PHY].type !=
5601 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5602 mask |= NIG_MASK_MI_INT;
5603 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5606 } else { /* SerDes */
5607 mask = NIG_MASK_SERDES0_LINK_STATUS;
5608 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5609 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5610 params->phy[INT_PHY].type !=
5611 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5612 mask |= NIG_MASK_MI_INT;
5613 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5617 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5620 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5621 (params->switch_cfg == SWITCH_CFG_10G),
5622 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5623 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5624 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5625 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5626 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5627 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5628 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5629 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5632 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5635 u32 latch_status = 0;
5638 * Disable the MI INT ( external phy int ) by writing 1 to the
5639 * status register. Link down indication is high-active-signal,
5640 * so in this case we need to write the status to clear the XOR
5642 /* Read Latched signals */
5643 latch_status = REG_RD(bp,
5644 NIG_REG_LATCH_STATUS_0 + port*8);
5645 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5646 /* Handle only those with latched-signal=up.*/
5649 NIG_REG_STATUS_INTERRUPT_PORT0
5651 NIG_STATUS_EMAC0_MI_INT);
5654 NIG_REG_STATUS_INTERRUPT_PORT0
5656 NIG_STATUS_EMAC0_MI_INT);
5658 if (latch_status & 1) {
5660 /* For all latched-signal=up : Re-Arm Latch signals */
5661 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5662 (latch_status & 0xfffe) | (latch_status & 1));
5664 /* For all latched-signal=up,Write original_signal to status */
5667 static void bnx2x_link_int_ack(struct link_params *params,
5668 struct link_vars *vars, u8 is_10g_plus)
5670 struct bnx2x *bp = params->bp;
5671 u8 port = params->port;
5674 * First reset all status we assume only one line will be
5677 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5678 (NIG_STATUS_XGXS0_LINK10G |
5679 NIG_STATUS_XGXS0_LINK_STATUS |
5680 NIG_STATUS_SERDES0_LINK_STATUS));
5681 if (vars->phy_link_up) {
5682 if (USES_WARPCORE(bp))
5683 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5686 mask = NIG_STATUS_XGXS0_LINK10G;
5687 else if (params->switch_cfg == SWITCH_CFG_10G) {
5689 * Disable the link interrupt by writing 1 to
5690 * the relevant lane in the status register
5693 ((params->lane_config &
5694 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5695 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5696 mask = ((1 << ser_lane) <<
5697 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5699 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5701 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5704 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5709 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5712 u32 mask = 0xf0000000;
5715 u8 remove_leading_zeros = 1;
5717 /* Need more than 10chars for this format */
5725 digit = ((num & mask) >> shift);
5726 if (digit == 0 && remove_leading_zeros) {
5729 } else if (digit < 0xa)
5730 *str_ptr = digit + '0';
5732 *str_ptr = digit - 0xa + 'a';
5733 remove_leading_zeros = 0;
5741 remove_leading_zeros = 1;
5748 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5755 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5756 u8 *version, u16 len)
5761 u8 *ver_p = version;
5762 u16 remain_len = len;
5763 if (version == NULL || params == NULL)
5767 /* Extract first external phy*/
5769 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5771 if (params->phy[EXT_PHY1].format_fw_ver) {
5772 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5775 ver_p += (len - remain_len);
5777 if ((params->num_phys == MAX_PHYS) &&
5778 (params->phy[EXT_PHY2].ver_addr != 0)) {
5779 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5780 if (params->phy[EXT_PHY2].format_fw_ver) {
5784 status |= params->phy[EXT_PHY2].format_fw_ver(
5788 ver_p = version + (len - remain_len);
5795 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5796 struct link_params *params)
5798 u8 port = params->port;
5799 struct bnx2x *bp = params->bp;
5801 if (phy->req_line_speed != SPEED_1000) {
5804 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5806 if (!CHIP_IS_E3(bp)) {
5807 /* change the uni_phy_addr in the nig */
5808 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5811 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5815 bnx2x_cl45_write(bp, phy,
5817 (MDIO_REG_BANK_AER_BLOCK +
5818 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5821 bnx2x_cl45_write(bp, phy,
5823 (MDIO_REG_BANK_CL73_IEEEB0 +
5824 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5827 /* set aer mmd back */
5828 bnx2x_set_aer_mmd(params, phy);
5830 if (!CHIP_IS_E3(bp)) {
5832 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5837 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5838 bnx2x_cl45_read(bp, phy, 5,
5839 (MDIO_REG_BANK_COMBO_IEEE0 +
5840 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5842 bnx2x_cl45_write(bp, phy, 5,
5843 (MDIO_REG_BANK_COMBO_IEEE0 +
5844 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5846 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5850 int bnx2x_set_led(struct link_params *params,
5851 struct link_vars *vars, u8 mode, u32 speed)
5853 u8 port = params->port;
5854 u16 hw_led_mode = params->hw_led_mode;
5858 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5859 struct bnx2x *bp = params->bp;
5860 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5861 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5862 speed, hw_led_mode);
5864 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5865 if (params->phy[phy_idx].set_link_led) {
5866 params->phy[phy_idx].set_link_led(
5867 ¶ms->phy[phy_idx], params, mode);
5872 case LED_MODE_FRONT_PANEL_OFF:
5874 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5875 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5876 SHARED_HW_CFG_LED_MAC1);
5878 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5879 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5884 * For all other phys, OPER mode is same as ON, so in case
5885 * link is down, do nothing
5890 if (((params->phy[EXT_PHY1].type ==
5891 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5892 (params->phy[EXT_PHY1].type ==
5893 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5894 CHIP_IS_E2(bp) && params->num_phys == 2) {
5896 * This is a work-around for E2+8727 Configurations
5898 if (mode == LED_MODE_ON ||
5899 speed == SPEED_10000){
5900 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5901 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5903 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5904 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5905 (tmp | EMAC_LED_OVERRIDE));
5908 } else if (SINGLE_MEDIA_DIRECT(params) &&
5912 * This is a work-around for HW issue found when link
5915 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5916 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5918 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5921 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5922 /* Set blinking rate to ~15.9Hz */
5923 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5924 LED_BLINK_RATE_VAL);
5925 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5927 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5928 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5930 if (CHIP_IS_E1(bp) &&
5931 ((speed == SPEED_2500) ||
5932 (speed == SPEED_1000) ||
5933 (speed == SPEED_100) ||
5934 (speed == SPEED_10))) {
5936 * On Everest 1 Ax chip versions for speeds less than
5937 * 10G LED scheme is different
5939 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5941 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5943 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5950 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5959 * This function comes to reflect the actual link state read DIRECTLY from the
5962 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5965 struct bnx2x *bp = params->bp;
5966 u16 gp_status = 0, phy_index = 0;
5967 u8 ext_phy_link_up = 0, serdes_phy_type;
5968 struct link_vars temp_vars;
5969 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
5971 if (CHIP_IS_E3(bp)) {
5973 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5975 /* Check 20G link */
5976 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5978 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5982 /* Check 10G link and below*/
5983 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5984 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5985 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5987 gp_status = ((gp_status >> 8) & 0xf) |
5988 ((gp_status >> 12) & 0xf);
5989 link_up = gp_status & (1 << lane);
5994 CL22_RD_OVER_CL45(bp, int_phy,
5995 MDIO_REG_BANK_GP_STATUS,
5996 MDIO_GP_STATUS_TOP_AN_STATUS1,
5998 /* link is up only if both local phy and external phy are up */
5999 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6002 /* In XGXS loopback mode, do not check external PHY */
6003 if (params->loopback_mode == LOOPBACK_XGXS)
6006 switch (params->num_phys) {
6008 /* No external PHY */
6011 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6012 ¶ms->phy[EXT_PHY1],
6013 params, &temp_vars);
6015 case 3: /* Dual Media */
6016 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6018 serdes_phy_type = ((params->phy[phy_index].media_type ==
6019 ETH_PHY_SFP_FIBER) ||
6020 (params->phy[phy_index].media_type ==
6021 ETH_PHY_XFP_FIBER) ||
6022 (params->phy[phy_index].media_type ==
6023 ETH_PHY_DA_TWINAX));
6025 if (is_serdes != serdes_phy_type)
6027 if (params->phy[phy_index].read_status) {
6029 params->phy[phy_index].read_status(
6030 ¶ms->phy[phy_index],
6031 params, &temp_vars);
6036 if (ext_phy_link_up)
6041 static int bnx2x_link_initialize(struct link_params *params,
6042 struct link_vars *vars)
6045 u8 phy_index, non_ext_phy;
6046 struct bnx2x *bp = params->bp;
6048 * In case of external phy existence, the line speed would be the
6049 * line speed linked up by the external phy. In case it is direct
6050 * only, then the line_speed during initialization will be
6051 * equal to the req_line_speed
6053 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6056 * Initialize the internal phy in case this is a direct board
6057 * (no external phys), or this board has external phy which requires
6060 if (!USES_WARPCORE(bp))
6061 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6062 /* init ext phy and enable link state int */
6063 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6064 (params->loopback_mode == LOOPBACK_XGXS));
6067 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6068 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6069 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6070 if (vars->line_speed == SPEED_AUTO_NEG &&
6073 bnx2x_set_parallel_detection(phy, params);
6074 if (params->phy[INT_PHY].config_init)
6075 params->phy[INT_PHY].config_init(phy,
6080 /* Init external phy*/
6082 if (params->phy[INT_PHY].supported &
6084 vars->link_status |= LINK_STATUS_SERDES_LINK;
6086 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6089 * No need to initialize second phy in case of first
6090 * phy only selection. In case of second phy, we do
6091 * need to initialize the first phy, since they are
6094 if (params->phy[phy_index].supported &
6096 vars->link_status |= LINK_STATUS_SERDES_LINK;
6098 if (phy_index == EXT_PHY2 &&
6099 (bnx2x_phy_selection(params) ==
6100 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6101 DP(NETIF_MSG_LINK, "Not initializing"
6105 params->phy[phy_index].config_init(
6106 ¶ms->phy[phy_index],
6110 /* Reset the interrupt indication after phy was initialized */
6111 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6113 (NIG_STATUS_XGXS0_LINK10G |
6114 NIG_STATUS_XGXS0_LINK_STATUS |
6115 NIG_STATUS_SERDES0_LINK_STATUS |
6117 bnx2x_update_mng(params, vars->link_status);
6121 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6122 struct link_params *params)
6124 /* reset the SerDes/XGXS */
6125 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6126 (0x1ff << (params->port*16)));
6129 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6130 struct link_params *params)
6132 struct bnx2x *bp = params->bp;
6136 gpio_port = BP_PATH(bp);
6138 gpio_port = params->port;
6139 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6140 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6142 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6143 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6145 DP(NETIF_MSG_LINK, "reset external PHY\n");
6148 static int bnx2x_update_link_down(struct link_params *params,
6149 struct link_vars *vars)
6151 struct bnx2x *bp = params->bp;
6152 u8 port = params->port;
6154 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6155 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6156 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6157 /* indicate no mac active */
6158 vars->mac_type = MAC_TYPE_NONE;
6160 /* update shared memory */
6161 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6162 LINK_STATUS_LINK_UP |
6163 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6164 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6165 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6166 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6167 vars->line_speed = 0;
6168 bnx2x_update_mng(params, vars->link_status);
6170 /* activate nig drain */
6171 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6174 if (!CHIP_IS_E3(bp))
6175 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6178 /* reset BigMac/Xmac */
6179 if (CHIP_IS_E1x(bp) ||
6181 bnx2x_bmac_rx_disable(bp, params->port);
6182 REG_WR(bp, GRCBASE_MISC +
6183 MISC_REGISTERS_RESET_REG_2_CLEAR,
6184 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6187 bnx2x_xmac_disable(params);
6192 static int bnx2x_update_link_up(struct link_params *params,
6193 struct link_vars *vars,
6196 struct bnx2x *bp = params->bp;
6197 u8 port = params->port;
6200 vars->link_status |= LINK_STATUS_LINK_UP;
6201 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6203 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6204 vars->link_status |=
6205 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6207 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6208 vars->link_status |=
6209 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6210 if (USES_WARPCORE(bp)) {
6212 if (bnx2x_xmac_enable(params, vars, 0) ==
6214 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6216 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6217 vars->link_status &= ~LINK_STATUS_LINK_UP;
6220 bnx2x_umac_enable(params, vars, 0);
6221 bnx2x_set_led(params, vars,
6222 LED_MODE_OPER, vars->line_speed);
6224 if ((CHIP_IS_E1x(bp) ||
6227 if (bnx2x_bmac_enable(params, vars, 0) ==
6229 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6231 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6232 vars->link_status &= ~LINK_STATUS_LINK_UP;
6235 bnx2x_set_led(params, vars,
6236 LED_MODE_OPER, SPEED_10000);
6238 rc = bnx2x_emac_program(params, vars);
6239 bnx2x_emac_enable(params, vars, 0);
6242 if ((vars->link_status &
6243 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6244 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6245 SINGLE_MEDIA_DIRECT(params))
6246 bnx2x_set_gmii_tx_driver(params);
6251 if (CHIP_IS_E1x(bp))
6252 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6256 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6258 /* update shared memory */
6259 bnx2x_update_mng(params, vars->link_status);
6264 * The bnx2x_link_update function should be called upon link
6266 * Link is considered up as follows:
6267 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6269 * - SINGLE_MEDIA - The link between the 577xx and the external
6270 * phy (XGXS) need to up as well as the external link of the
6272 * - DUAL_MEDIA - The link between the 577xx and the first
6273 * external phy needs to be up, and at least one of the 2
6274 * external phy link must be up.
6276 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6278 struct bnx2x *bp = params->bp;
6279 struct link_vars phy_vars[MAX_PHYS];
6280 u8 port = params->port;
6281 u8 link_10g_plus, phy_index;
6282 u8 ext_phy_link_up = 0, cur_link_up;
6285 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6286 u8 active_external_phy = INT_PHY;
6287 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6288 for (phy_index = INT_PHY; phy_index < params->num_phys;
6290 phy_vars[phy_index].flow_ctrl = 0;
6291 phy_vars[phy_index].link_status = 0;
6292 phy_vars[phy_index].line_speed = 0;
6293 phy_vars[phy_index].duplex = DUPLEX_FULL;
6294 phy_vars[phy_index].phy_link_up = 0;
6295 phy_vars[phy_index].link_up = 0;
6296 phy_vars[phy_index].fault_detected = 0;
6299 if (USES_WARPCORE(bp))
6300 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6302 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6303 port, (vars->phy_flags & PHY_XGXS_FLAG),
6304 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6306 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6308 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6309 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6311 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6313 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6314 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6315 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6318 if (!CHIP_IS_E3(bp))
6319 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6323 * Check external link change only for external phys, and apply
6324 * priority selection between them in case the link on both phys
6325 * is up. Note that instead of the common vars, a temporary
6326 * vars argument is used since each phy may have different link/
6327 * speed/duplex result
6329 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6331 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6332 if (!phy->read_status)
6334 /* Read link status and params of this ext phy */
6335 cur_link_up = phy->read_status(phy, params,
6336 &phy_vars[phy_index]);
6338 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6341 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6346 if (!ext_phy_link_up) {
6347 ext_phy_link_up = 1;
6348 active_external_phy = phy_index;
6350 switch (bnx2x_phy_selection(params)) {
6351 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6352 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6354 * In this option, the first PHY makes sure to pass the
6355 * traffic through itself only.
6356 * Its not clear how to reset the link on the second phy
6358 active_external_phy = EXT_PHY1;
6360 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6362 * In this option, the first PHY makes sure to pass the
6363 * traffic through the second PHY.
6365 active_external_phy = EXT_PHY2;
6369 * Link indication on both PHYs with the following cases
6371 * - FIRST_PHY means that second phy wasn't initialized,
6372 * hence its link is expected to be down
6373 * - SECOND_PHY means that first phy should not be able
6374 * to link up by itself (using configuration)
6375 * - DEFAULT should be overriden during initialiazation
6377 DP(NETIF_MSG_LINK, "Invalid link indication"
6378 "mpc=0x%x. DISABLING LINK !!!\n",
6379 params->multi_phy_config);
6380 ext_phy_link_up = 0;
6385 prev_line_speed = vars->line_speed;
6388 * Read the status of the internal phy. In case of
6389 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6390 * otherwise this is the link between the 577xx and the first
6393 if (params->phy[INT_PHY].read_status)
6394 params->phy[INT_PHY].read_status(
6395 ¶ms->phy[INT_PHY],
6398 * The INT_PHY flow control reside in the vars. This include the
6399 * case where the speed or flow control are not set to AUTO.
6400 * Otherwise, the active external phy flow control result is set
6401 * to the vars. The ext_phy_line_speed is needed to check if the
6402 * speed is different between the internal phy and external phy.
6403 * This case may be result of intermediate link speed change.
6405 if (active_external_phy > INT_PHY) {
6406 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6408 * Link speed is taken from the XGXS. AN and FC result from
6411 vars->link_status |= phy_vars[active_external_phy].link_status;
6414 * if active_external_phy is first PHY and link is up - disable
6415 * disable TX on second external PHY
6417 if (active_external_phy == EXT_PHY1) {
6418 if (params->phy[EXT_PHY2].phy_specific_func) {
6419 DP(NETIF_MSG_LINK, "Disabling TX on"
6421 params->phy[EXT_PHY2].phy_specific_func(
6422 ¶ms->phy[EXT_PHY2],
6423 params, DISABLE_TX);
6427 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6428 vars->duplex = phy_vars[active_external_phy].duplex;
6429 if (params->phy[active_external_phy].supported &
6431 vars->link_status |= LINK_STATUS_SERDES_LINK;
6433 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6434 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6435 active_external_phy);
6438 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6440 if (params->phy[phy_index].flags &
6441 FLAGS_REARM_LATCH_SIGNAL) {
6442 bnx2x_rearm_latch_signal(bp, port,
6444 active_external_phy);
6448 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6449 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6450 vars->link_status, ext_phy_line_speed);
6452 * Upon link speed change set the NIG into drain mode. Comes to
6453 * deals with possible FIFO glitch due to clk change when speed
6454 * is decreased without link down indicator
6457 if (vars->phy_link_up) {
6458 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6459 (ext_phy_line_speed != vars->line_speed)) {
6460 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6461 " different than the external"
6462 " link speed %d\n", vars->line_speed,
6463 ext_phy_line_speed);
6464 vars->phy_link_up = 0;
6465 } else if (prev_line_speed != vars->line_speed) {
6466 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6472 /* anything 10 and over uses the bmac */
6473 link_10g_plus = (vars->line_speed >= SPEED_10000);
6475 bnx2x_link_int_ack(params, vars, link_10g_plus);
6478 * In case external phy link is up, and internal link is down
6479 * (not initialized yet probably after link initialization, it
6480 * needs to be initialized.
6481 * Note that after link down-up as result of cable plug, the xgxs
6482 * link would probably become up again without the need
6485 if (!(SINGLE_MEDIA_DIRECT(params))) {
6486 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6487 " init_preceding = %d\n", ext_phy_link_up,
6489 params->phy[EXT_PHY1].flags &
6490 FLAGS_INIT_XGXS_FIRST);
6491 if (!(params->phy[EXT_PHY1].flags &
6492 FLAGS_INIT_XGXS_FIRST)
6493 && ext_phy_link_up && !vars->phy_link_up) {
6494 vars->line_speed = ext_phy_line_speed;
6495 if (vars->line_speed < SPEED_1000)
6496 vars->phy_flags |= PHY_SGMII_FLAG;
6498 vars->phy_flags &= ~PHY_SGMII_FLAG;
6500 if (params->phy[INT_PHY].config_init)
6501 params->phy[INT_PHY].config_init(
6502 ¶ms->phy[INT_PHY], params,
6507 * Link is up only if both local phy and external phy (in case of
6508 * non-direct board) are up and no fault detected on active PHY.
6510 vars->link_up = (vars->phy_link_up &&
6512 SINGLE_MEDIA_DIRECT(params)) &&
6513 (phy_vars[active_external_phy].fault_detected == 0));
6516 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6518 rc = bnx2x_update_link_down(params, vars);
6524 /*****************************************************************************/
6525 /* External Phy section */
6526 /*****************************************************************************/
6527 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6529 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6530 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6532 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6533 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6536 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6537 u32 spirom_ver, u32 ver_addr)
6539 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6540 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6543 REG_WR(bp, ver_addr, spirom_ver);
6546 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6547 struct bnx2x_phy *phy,
6550 u16 fw_ver1, fw_ver2;
6552 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6553 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6554 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6555 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6556 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6560 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6561 struct bnx2x_phy *phy,
6562 struct link_vars *vars)
6565 bnx2x_cl45_read(bp, phy,
6567 MDIO_AN_REG_STATUS, &val);
6568 bnx2x_cl45_read(bp, phy,
6570 MDIO_AN_REG_STATUS, &val);
6572 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6573 if ((val & (1<<0)) == 0)
6574 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6577 /******************************************************************/
6578 /* common BCM8073/BCM8727 PHY SECTION */
6579 /******************************************************************/
6580 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6581 struct link_params *params,
6582 struct link_vars *vars)
6584 struct bnx2x *bp = params->bp;
6585 if (phy->req_line_speed == SPEED_10 ||
6586 phy->req_line_speed == SPEED_100) {
6587 vars->flow_ctrl = phy->req_flow_ctrl;
6591 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6592 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6594 u16 ld_pause; /* local */
6595 u16 lp_pause; /* link partner */
6596 bnx2x_cl45_read(bp, phy,
6598 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6600 bnx2x_cl45_read(bp, phy,
6602 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6603 pause_result = (ld_pause &
6604 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6605 pause_result |= (lp_pause &
6606 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6608 bnx2x_pause_resolve(vars, pause_result);
6609 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6613 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6614 struct bnx2x_phy *phy,
6618 u16 fw_ver1, fw_msgout;
6621 /* Boot port from external ROM */
6623 bnx2x_cl45_write(bp, phy,
6625 MDIO_PMA_REG_GEN_CTRL,
6628 /* ucode reboot and rst */
6629 bnx2x_cl45_write(bp, phy,
6631 MDIO_PMA_REG_GEN_CTRL,
6634 bnx2x_cl45_write(bp, phy,
6636 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6638 /* Reset internal microprocessor */
6639 bnx2x_cl45_write(bp, phy,
6641 MDIO_PMA_REG_GEN_CTRL,
6642 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6644 /* Release srst bit */
6645 bnx2x_cl45_write(bp, phy,
6647 MDIO_PMA_REG_GEN_CTRL,
6648 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6650 /* Delay 100ms per the PHY specifications */
6653 /* 8073 sometimes taking longer to download */
6658 "bnx2x_8073_8727_external_rom_boot port %x:"
6659 "Download failed. fw version = 0x%x\n",
6665 bnx2x_cl45_read(bp, phy,
6667 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6668 bnx2x_cl45_read(bp, phy,
6670 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6673 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6674 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6675 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6677 /* Clear ser_boot_ctl bit */
6678 bnx2x_cl45_write(bp, phy,
6680 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6681 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6684 "bnx2x_8073_8727_external_rom_boot port %x:"
6685 "Download complete. fw version = 0x%x\n",
6691 /******************************************************************/
6692 /* BCM8073 PHY SECTION */
6693 /******************************************************************/
6694 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6696 /* This is only required for 8073A1, version 102 only */
6699 /* Read 8073 HW revision*/
6700 bnx2x_cl45_read(bp, phy,
6702 MDIO_PMA_REG_8073_CHIP_REV, &val);
6705 /* No need to workaround in 8073 A1 */
6709 bnx2x_cl45_read(bp, phy,
6711 MDIO_PMA_REG_ROM_VER2, &val);
6713 /* SNR should be applied only for version 0x102 */
6720 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6722 u16 val, cnt, cnt1 ;
6724 bnx2x_cl45_read(bp, phy,
6726 MDIO_PMA_REG_8073_CHIP_REV, &val);
6729 /* No need to workaround in 8073 A1 */
6732 /* XAUI workaround in 8073 A0: */
6735 * After loading the boot ROM and restarting Autoneg, poll
6739 for (cnt = 0; cnt < 1000; cnt++) {
6740 bnx2x_cl45_read(bp, phy,
6742 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6745 * If bit [14] = 0 or bit [13] = 0, continue on with
6746 * system initialization (XAUI work-around not required, as
6747 * these bits indicate 2.5G or 1G link up).
6749 if (!(val & (1<<14)) || !(val & (1<<13))) {
6750 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6752 } else if (!(val & (1<<15))) {
6753 DP(NETIF_MSG_LINK, "bit 15 went off\n");
6755 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6756 * MSB (bit15) goes to 1 (indicating that the XAUI
6757 * workaround has completed), then continue on with
6758 * system initialization.
6760 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6761 bnx2x_cl45_read(bp, phy,
6763 MDIO_PMA_REG_8073_XAUI_WA, &val);
6764 if (val & (1<<15)) {
6766 "XAUI workaround has completed\n");
6775 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6779 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6781 /* Force KR or KX */
6782 bnx2x_cl45_write(bp, phy,
6783 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6784 bnx2x_cl45_write(bp, phy,
6785 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6786 bnx2x_cl45_write(bp, phy,
6787 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6788 bnx2x_cl45_write(bp, phy,
6789 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6792 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6793 struct bnx2x_phy *phy,
6794 struct link_vars *vars)
6797 struct bnx2x *bp = params->bp;
6798 bnx2x_cl45_read(bp, phy,
6799 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6801 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6802 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6803 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6804 if ((vars->ieee_fc &
6805 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6806 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6807 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6809 if ((vars->ieee_fc &
6810 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6811 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6812 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6814 if ((vars->ieee_fc &
6815 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6816 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6817 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6820 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6822 bnx2x_cl45_write(bp, phy,
6823 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6827 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6828 struct link_params *params,
6829 struct link_vars *vars)
6831 struct bnx2x *bp = params->bp;
6834 DP(NETIF_MSG_LINK, "Init 8073\n");
6837 gpio_port = BP_PATH(bp);
6839 gpio_port = params->port;
6840 /* Restore normal power mode*/
6841 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6842 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6844 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6845 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6848 bnx2x_cl45_write(bp, phy,
6849 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6850 bnx2x_cl45_write(bp, phy,
6851 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
6853 bnx2x_8073_set_pause_cl37(params, phy, vars);
6855 bnx2x_cl45_read(bp, phy,
6856 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6858 bnx2x_cl45_read(bp, phy,
6859 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6861 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6863 /* Swap polarity if required - Must be done only in non-1G mode */
6864 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6865 /* Configure the 8073 to swap _P and _N of the KR lines */
6866 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6867 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6868 bnx2x_cl45_read(bp, phy,
6870 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6871 bnx2x_cl45_write(bp, phy,
6873 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6878 /* Enable CL37 BAM */
6879 if (REG_RD(bp, params->shmem_base +
6880 offsetof(struct shmem_region, dev_info.
6881 port_hw_config[params->port].default_cfg)) &
6882 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6884 bnx2x_cl45_read(bp, phy,
6886 MDIO_AN_REG_8073_BAM, &val);
6887 bnx2x_cl45_write(bp, phy,
6889 MDIO_AN_REG_8073_BAM, val | 1);
6890 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6892 if (params->loopback_mode == LOOPBACK_EXT) {
6893 bnx2x_807x_force_10G(bp, phy);
6894 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6897 bnx2x_cl45_write(bp, phy,
6898 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6900 if (phy->req_line_speed != SPEED_AUTO_NEG) {
6901 if (phy->req_line_speed == SPEED_10000) {
6903 } else if (phy->req_line_speed == SPEED_2500) {
6906 * Note that 2.5G works only when used with 1G
6913 if (phy->speed_cap_mask &
6914 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6917 /* Note that 2.5G works only when used with 1G advertisement */
6918 if (phy->speed_cap_mask &
6919 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6920 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6922 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6925 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6926 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6928 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6929 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6930 (phy->req_line_speed == SPEED_2500)) {
6932 /* Allow 2.5G for A1 and above */
6933 bnx2x_cl45_read(bp, phy,
6934 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6936 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6942 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6946 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6947 /* Add support for CL37 (passive mode) II */
6949 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6950 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6951 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6954 /* Add support for CL37 (passive mode) III */
6955 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6958 * The SNR will improve about 2db by changing BW and FEE main
6959 * tap. Rest commands are executed after link is up
6960 * Change FFE main cursor to 5 in EDC register
6962 if (bnx2x_8073_is_snr_needed(bp, phy))
6963 bnx2x_cl45_write(bp, phy,
6964 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6967 /* Enable FEC (Forware Error Correction) Request in the AN */
6968 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6970 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6972 bnx2x_ext_phy_set_pause(params, phy, vars);
6974 /* Restart autoneg */
6976 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6977 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6978 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6982 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6983 struct link_params *params,
6984 struct link_vars *vars)
6986 struct bnx2x *bp = params->bp;
6989 u16 link_status = 0;
6990 u16 an1000_status = 0;
6992 bnx2x_cl45_read(bp, phy,
6993 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6995 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
6997 /* clear the interrupt LASI status register */
6998 bnx2x_cl45_read(bp, phy,
6999 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7000 bnx2x_cl45_read(bp, phy,
7001 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7002 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7004 bnx2x_cl45_read(bp, phy,
7005 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7007 /* Check the LASI */
7008 bnx2x_cl45_read(bp, phy,
7009 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7011 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7013 /* Check the link status */
7014 bnx2x_cl45_read(bp, phy,
7015 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7016 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7018 bnx2x_cl45_read(bp, phy,
7019 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7020 bnx2x_cl45_read(bp, phy,
7021 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7022 link_up = ((val1 & 4) == 4);
7023 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7026 ((phy->req_line_speed != SPEED_10000))) {
7027 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7030 bnx2x_cl45_read(bp, phy,
7031 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7032 bnx2x_cl45_read(bp, phy,
7033 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7035 /* Check the link status on 1.1.2 */
7036 bnx2x_cl45_read(bp, phy,
7037 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7038 bnx2x_cl45_read(bp, phy,
7039 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7040 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7041 "an_link_status=0x%x\n", val2, val1, an1000_status);
7043 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7044 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7046 * The SNR will improve about 2dbby changing the BW and FEE main
7047 * tap. The 1st write to change FFE main tap is set before
7048 * restart AN. Change PLL Bandwidth in EDC register
7050 bnx2x_cl45_write(bp, phy,
7051 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7054 /* Change CDR Bandwidth in EDC register */
7055 bnx2x_cl45_write(bp, phy,
7056 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7059 bnx2x_cl45_read(bp, phy,
7060 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7063 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7064 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7066 vars->line_speed = SPEED_10000;
7067 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7069 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7071 vars->line_speed = SPEED_2500;
7072 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7074 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7076 vars->line_speed = SPEED_1000;
7077 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7081 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7086 /* Swap polarity if required */
7087 if (params->lane_config &
7088 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7089 /* Configure the 8073 to swap P and N of the KR lines */
7090 bnx2x_cl45_read(bp, phy,
7092 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7094 * Set bit 3 to invert Rx in 1G mode and clear this bit
7095 * when it`s in 10G mode.
7097 if (vars->line_speed == SPEED_1000) {
7098 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7104 bnx2x_cl45_write(bp, phy,
7106 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7109 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7110 bnx2x_8073_resolve_fc(phy, params, vars);
7111 vars->duplex = DUPLEX_FULL;
7116 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7117 struct link_params *params)
7119 struct bnx2x *bp = params->bp;
7122 gpio_port = BP_PATH(bp);
7124 gpio_port = params->port;
7125 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7127 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7128 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7132 /******************************************************************/
7133 /* BCM8705 PHY SECTION */
7134 /******************************************************************/
7135 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7136 struct link_params *params,
7137 struct link_vars *vars)
7139 struct bnx2x *bp = params->bp;
7140 DP(NETIF_MSG_LINK, "init 8705\n");
7141 /* Restore normal power mode*/
7142 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7143 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7145 bnx2x_ext_phy_hw_reset(bp, params->port);
7146 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7147 bnx2x_wait_reset_complete(bp, phy, params);
7149 bnx2x_cl45_write(bp, phy,
7150 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7151 bnx2x_cl45_write(bp, phy,
7152 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7153 bnx2x_cl45_write(bp, phy,
7154 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7155 bnx2x_cl45_write(bp, phy,
7156 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7157 /* BCM8705 doesn't have microcode, hence the 0 */
7158 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7162 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7163 struct link_params *params,
7164 struct link_vars *vars)
7168 struct bnx2x *bp = params->bp;
7169 DP(NETIF_MSG_LINK, "read status 8705\n");
7170 bnx2x_cl45_read(bp, phy,
7171 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7172 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7174 bnx2x_cl45_read(bp, phy,
7175 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7176 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7178 bnx2x_cl45_read(bp, phy,
7179 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7181 bnx2x_cl45_read(bp, phy,
7182 MDIO_PMA_DEVAD, 0xc809, &val1);
7183 bnx2x_cl45_read(bp, phy,
7184 MDIO_PMA_DEVAD, 0xc809, &val1);
7186 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7187 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7189 vars->line_speed = SPEED_10000;
7190 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7195 /******************************************************************/
7196 /* SFP+ module Section */
7197 /******************************************************************/
7198 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7199 struct bnx2x_phy *phy,
7202 struct bnx2x *bp = params->bp;
7204 * Disable transmitter only for bootcodes which can enable it afterwards
7208 if (params->feature_config_flags &
7209 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7210 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7212 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7216 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7217 bnx2x_cl45_write(bp, phy,
7219 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7222 static u8 bnx2x_get_gpio_port(struct link_params *params)
7225 u32 swap_val, swap_override;
7226 struct bnx2x *bp = params->bp;
7228 gpio_port = BP_PATH(bp);
7230 gpio_port = params->port;
7231 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7232 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7233 return gpio_port ^ (swap_val && swap_override);
7236 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7237 struct bnx2x_phy *phy,
7241 u8 port = params->port;
7242 struct bnx2x *bp = params->bp;
7245 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7246 tx_en_mode = REG_RD(bp, params->shmem_base +
7247 offsetof(struct shmem_region,
7248 dev_info.port_hw_config[port].sfp_ctrl)) &
7249 PORT_HW_CFG_TX_LASER_MASK;
7250 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7251 "mode = %x\n", tx_en, port, tx_en_mode);
7252 switch (tx_en_mode) {
7253 case PORT_HW_CFG_TX_LASER_MDIO:
7255 bnx2x_cl45_read(bp, phy,
7257 MDIO_PMA_REG_PHY_IDENTIFIER,
7265 bnx2x_cl45_write(bp, phy,
7267 MDIO_PMA_REG_PHY_IDENTIFIER,
7270 case PORT_HW_CFG_TX_LASER_GPIO0:
7271 case PORT_HW_CFG_TX_LASER_GPIO1:
7272 case PORT_HW_CFG_TX_LASER_GPIO2:
7273 case PORT_HW_CFG_TX_LASER_GPIO3:
7276 u8 gpio_port, gpio_mode;
7278 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7280 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7282 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7283 gpio_port = bnx2x_get_gpio_port(params);
7284 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7288 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7293 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7294 struct bnx2x_phy *phy,
7297 struct bnx2x *bp = params->bp;
7298 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7300 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7302 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7305 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7306 struct link_params *params,
7307 u16 addr, u8 byte_cnt, u8 *o_buf)
7309 struct bnx2x *bp = params->bp;
7312 if (byte_cnt > 16) {
7313 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7314 " is limited to 0xf\n");
7317 /* Set the read command byte count */
7318 bnx2x_cl45_write(bp, phy,
7319 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7320 (byte_cnt | 0xa000));
7322 /* Set the read command address */
7323 bnx2x_cl45_write(bp, phy,
7324 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7327 /* Activate read command */
7328 bnx2x_cl45_write(bp, phy,
7329 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7332 /* Wait up to 500us for command complete status */
7333 for (i = 0; i < 100; i++) {
7334 bnx2x_cl45_read(bp, phy,
7336 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7337 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7338 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7343 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7344 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7346 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7347 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7351 /* Read the buffer */
7352 for (i = 0; i < byte_cnt; i++) {
7353 bnx2x_cl45_read(bp, phy,
7355 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7356 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7359 for (i = 0; i < 100; i++) {
7360 bnx2x_cl45_read(bp, phy,
7362 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7363 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7364 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7371 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7372 struct link_params *params,
7373 u16 addr, u8 byte_cnt,
7377 u8 i, j = 0, cnt = 0;
7380 struct bnx2x *bp = params->bp;
7381 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7382 " addr %d, cnt %d\n",
7384 if (byte_cnt > 16) {
7385 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7386 " is limited to 16 bytes\n");
7390 /* 4 byte aligned address */
7391 addr32 = addr & (~0x3);
7393 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7395 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7398 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7399 o_buf[j] = *((u8 *)data_array + i);
7407 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7408 struct link_params *params,
7409 u16 addr, u8 byte_cnt, u8 *o_buf)
7411 struct bnx2x *bp = params->bp;
7414 if (byte_cnt > 16) {
7415 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7416 " is limited to 0xf\n");
7420 /* Need to read from 1.8000 to clear it */
7421 bnx2x_cl45_read(bp, phy,
7423 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7426 /* Set the read command byte count */
7427 bnx2x_cl45_write(bp, phy,
7429 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7430 ((byte_cnt < 2) ? 2 : byte_cnt));
7432 /* Set the read command address */
7433 bnx2x_cl45_write(bp, phy,
7435 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7437 /* Set the destination address */
7438 bnx2x_cl45_write(bp, phy,
7441 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7443 /* Activate read command */
7444 bnx2x_cl45_write(bp, phy,
7446 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7449 * Wait appropriate time for two-wire command to finish before
7450 * polling the status register
7454 /* Wait up to 500us for command complete status */
7455 for (i = 0; i < 100; i++) {
7456 bnx2x_cl45_read(bp, phy,
7458 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7459 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7460 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7465 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7466 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7468 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7469 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7473 /* Read the buffer */
7474 for (i = 0; i < byte_cnt; i++) {
7475 bnx2x_cl45_read(bp, phy,
7477 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7478 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7481 for (i = 0; i < 100; i++) {
7482 bnx2x_cl45_read(bp, phy,
7484 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7485 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7486 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7494 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7495 struct link_params *params, u16 addr,
7496 u8 byte_cnt, u8 *o_buf)
7499 switch (phy->type) {
7500 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7501 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7504 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7505 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7506 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7509 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7510 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7517 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7518 struct link_params *params,
7521 struct bnx2x *bp = params->bp;
7522 u32 sync_offset = 0, phy_idx, media_types;
7523 u8 val, check_limiting_mode = 0;
7524 *edc_mode = EDC_MODE_LIMITING;
7526 phy->media_type = ETH_PHY_UNSPECIFIED;
7527 /* First check for copper cable */
7528 if (bnx2x_read_sfp_module_eeprom(phy,
7530 SFP_EEPROM_CON_TYPE_ADDR,
7533 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7538 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7540 u8 copper_module_type;
7541 phy->media_type = ETH_PHY_DA_TWINAX;
7543 * Check if its active cable (includes SFP+ module)
7546 if (bnx2x_read_sfp_module_eeprom(phy,
7548 SFP_EEPROM_FC_TX_TECH_ADDR,
7550 &copper_module_type) != 0) {
7552 "Failed to read copper-cable-type"
7553 " from SFP+ EEPROM\n");
7557 if (copper_module_type &
7558 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7559 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7560 check_limiting_mode = 1;
7561 } else if (copper_module_type &
7562 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7563 DP(NETIF_MSG_LINK, "Passive Copper"
7564 " cable detected\n");
7566 EDC_MODE_PASSIVE_DAC;
7568 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7569 "type 0x%x !!!\n", copper_module_type);
7574 case SFP_EEPROM_CON_TYPE_VAL_LC:
7575 phy->media_type = ETH_PHY_SFP_FIBER;
7576 DP(NETIF_MSG_LINK, "Optic module detected\n");
7577 check_limiting_mode = 1;
7580 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7584 sync_offset = params->shmem_base +
7585 offsetof(struct shmem_region,
7586 dev_info.port_hw_config[params->port].media_type);
7587 media_types = REG_RD(bp, sync_offset);
7588 /* Update media type for non-PMF sync */
7589 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7590 if (&(params->phy[phy_idx]) == phy) {
7591 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7592 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7593 media_types |= ((phy->media_type &
7594 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7595 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7599 REG_WR(bp, sync_offset, media_types);
7600 if (check_limiting_mode) {
7601 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7602 if (bnx2x_read_sfp_module_eeprom(phy,
7604 SFP_EEPROM_OPTIONS_ADDR,
7605 SFP_EEPROM_OPTIONS_SIZE,
7607 DP(NETIF_MSG_LINK, "Failed to read Option"
7608 " field from module EEPROM\n");
7611 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7612 *edc_mode = EDC_MODE_LINEAR;
7614 *edc_mode = EDC_MODE_LIMITING;
7616 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7620 * This function read the relevant field from the module (SFP+), and verify it
7621 * is compliant with this board
7623 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7624 struct link_params *params)
7626 struct bnx2x *bp = params->bp;
7628 u32 fw_resp, fw_cmd_param;
7629 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7630 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7631 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7632 val = REG_RD(bp, params->shmem_base +
7633 offsetof(struct shmem_region, dev_info.
7634 port_feature_config[params->port].config));
7635 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7636 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7637 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7641 if (params->feature_config_flags &
7642 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7643 /* Use specific phy request */
7644 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7645 } else if (params->feature_config_flags &
7646 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7647 /* Use first phy request only in case of non-dual media*/
7648 if (DUAL_MEDIA(params)) {
7649 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7653 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7655 /* No support in OPT MDL detection */
7656 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7661 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7662 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7663 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7664 DP(NETIF_MSG_LINK, "Approved module\n");
7668 /* format the warning message */
7669 if (bnx2x_read_sfp_module_eeprom(phy,
7671 SFP_EEPROM_VENDOR_NAME_ADDR,
7672 SFP_EEPROM_VENDOR_NAME_SIZE,
7674 vendor_name[0] = '\0';
7676 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7677 if (bnx2x_read_sfp_module_eeprom(phy,
7679 SFP_EEPROM_PART_NO_ADDR,
7680 SFP_EEPROM_PART_NO_SIZE,
7682 vendor_pn[0] = '\0';
7684 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7686 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7687 " Port %d from %s part number %s\n",
7688 params->port, vendor_name, vendor_pn);
7689 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7693 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7694 struct link_params *params)
7698 struct bnx2x *bp = params->bp;
7701 * Initialization time after hot-plug may take up to 300ms for
7702 * some phys type ( e.g. JDSU )
7705 for (timeout = 0; timeout < 60; timeout++) {
7706 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7708 DP(NETIF_MSG_LINK, "SFP+ module initialization "
7709 "took %d ms\n", timeout * 5);
7717 static void bnx2x_8727_power_module(struct bnx2x *bp,
7718 struct bnx2x_phy *phy,
7720 /* Make sure GPIOs are not using for LED mode */
7723 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7724 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7726 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7727 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7728 * where the 1st bit is the over-current(only input), and 2nd bit is
7729 * for power( only output )
7731 * In case of NOC feature is disabled and power is up, set GPIO control
7732 * as input to enable listening of over-current indication
7734 if (phy->flags & FLAGS_NOC)
7740 * Set GPIO control to OUTPUT, and set the power bit
7741 * to according to the is_power_up
7745 bnx2x_cl45_write(bp, phy,
7747 MDIO_PMA_REG_8727_GPIO_CTRL,
7751 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7752 struct bnx2x_phy *phy,
7755 u16 cur_limiting_mode;
7757 bnx2x_cl45_read(bp, phy,
7759 MDIO_PMA_REG_ROM_VER2,
7760 &cur_limiting_mode);
7761 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7764 if (edc_mode == EDC_MODE_LIMITING) {
7765 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7766 bnx2x_cl45_write(bp, phy,
7768 MDIO_PMA_REG_ROM_VER2,
7770 } else { /* LRM mode ( default )*/
7772 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7775 * Changing to LRM mode takes quite few seconds. So do it only
7776 * if current mode is limiting (default is LRM)
7778 if (cur_limiting_mode != EDC_MODE_LIMITING)
7781 bnx2x_cl45_write(bp, phy,
7783 MDIO_PMA_REG_LRM_MODE,
7785 bnx2x_cl45_write(bp, phy,
7787 MDIO_PMA_REG_ROM_VER2,
7789 bnx2x_cl45_write(bp, phy,
7791 MDIO_PMA_REG_MISC_CTRL0,
7793 bnx2x_cl45_write(bp, phy,
7795 MDIO_PMA_REG_LRM_MODE,
7801 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7802 struct bnx2x_phy *phy,
7807 bnx2x_cl45_read(bp, phy,
7809 MDIO_PMA_REG_PHY_IDENTIFIER,
7812 bnx2x_cl45_write(bp, phy,
7814 MDIO_PMA_REG_PHY_IDENTIFIER,
7815 (phy_identifier & ~(1<<9)));
7817 bnx2x_cl45_read(bp, phy,
7819 MDIO_PMA_REG_ROM_VER2,
7821 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7822 bnx2x_cl45_write(bp, phy,
7824 MDIO_PMA_REG_ROM_VER2,
7825 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7827 bnx2x_cl45_write(bp, phy,
7829 MDIO_PMA_REG_PHY_IDENTIFIER,
7830 (phy_identifier | (1<<9)));
7835 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7836 struct link_params *params,
7839 struct bnx2x *bp = params->bp;
7843 bnx2x_sfp_set_transmitter(params, phy, 0);
7846 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7847 bnx2x_sfp_set_transmitter(params, phy, 1);
7850 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7856 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7859 struct bnx2x *bp = params->bp;
7861 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7862 offsetof(struct shmem_region,
7863 dev_info.port_hw_config[params->port].sfp_ctrl)) &
7864 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7865 switch (fault_led_gpio) {
7866 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7868 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7869 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7870 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7871 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7873 u8 gpio_port = bnx2x_get_gpio_port(params);
7874 u16 gpio_pin = fault_led_gpio -
7875 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7876 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7877 "pin %x port %x mode %x\n",
7878 gpio_pin, gpio_port, gpio_mode);
7879 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7883 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7888 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7892 u8 port = params->port;
7893 struct bnx2x *bp = params->bp;
7894 pin_cfg = (REG_RD(bp, params->shmem_base +
7895 offsetof(struct shmem_region,
7896 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7897 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7898 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7899 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7900 gpio_mode, pin_cfg);
7901 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7904 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7907 struct bnx2x *bp = params->bp;
7908 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7909 if (CHIP_IS_E3(bp)) {
7911 * Low ==> if SFP+ module is supported otherwise
7912 * High ==> if SFP+ module is not on the approved vendor list
7914 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7916 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7919 static void bnx2x_warpcore_power_module(struct link_params *params,
7920 struct bnx2x_phy *phy,
7924 struct bnx2x *bp = params->bp;
7926 pin_cfg = (REG_RD(bp, params->shmem_base +
7927 offsetof(struct shmem_region,
7928 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7929 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7930 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7932 if (pin_cfg == PIN_CFG_NA)
7934 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7937 * Low ==> corresponding SFP+ module is powered
7938 * high ==> the SFP+ module is powered down
7940 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7943 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7944 struct link_params *params)
7946 bnx2x_warpcore_power_module(params, phy, 0);
7949 static void bnx2x_power_sfp_module(struct link_params *params,
7950 struct bnx2x_phy *phy,
7953 struct bnx2x *bp = params->bp;
7954 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7956 switch (phy->type) {
7957 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7959 bnx2x_8727_power_module(params->bp, phy, power);
7961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7962 bnx2x_warpcore_power_module(params, phy, power);
7968 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7969 struct bnx2x_phy *phy,
7973 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7974 struct bnx2x *bp = params->bp;
7976 u8 lane = bnx2x_get_warpcore_lane(phy, params);
7977 /* This is a global register which controls all lanes */
7978 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7979 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7980 val &= ~(0xf << (lane << 2));
7983 case EDC_MODE_LINEAR:
7984 case EDC_MODE_LIMITING:
7985 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7987 case EDC_MODE_PASSIVE_DAC:
7988 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
7994 val |= (mode << (lane << 2));
7995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
7996 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
7998 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7999 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8004 static void bnx2x_set_limiting_mode(struct link_params *params,
8005 struct bnx2x_phy *phy,
8008 switch (phy->type) {
8009 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8010 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8012 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8014 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8016 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8017 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8022 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8023 struct link_params *params)
8025 struct bnx2x *bp = params->bp;
8029 u32 val = REG_RD(bp, params->shmem_base +
8030 offsetof(struct shmem_region, dev_info.
8031 port_feature_config[params->port].config));
8033 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8035 /* Power up module */
8036 bnx2x_power_sfp_module(params, phy, 1);
8037 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8038 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8040 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8041 /* check SFP+ module compatibility */
8042 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8044 /* Turn on fault module-detected led */
8045 bnx2x_set_sfp_module_fault_led(params,
8046 MISC_REGISTERS_GPIO_HIGH);
8048 /* Check if need to power down the SFP+ module */
8049 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8050 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8051 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8052 bnx2x_power_sfp_module(params, phy, 0);
8056 /* Turn off fault module-detected led */
8057 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8061 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8062 * is done automatically
8064 bnx2x_set_limiting_mode(params, phy, edc_mode);
8067 * Enable transmit for this module if the module is approved, or
8068 * if unapproved modules should also enable the Tx laser
8071 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8072 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8073 bnx2x_sfp_set_transmitter(params, phy, 1);
8075 bnx2x_sfp_set_transmitter(params, phy, 0);
8080 void bnx2x_handle_module_detect_int(struct link_params *params)
8082 struct bnx2x *bp = params->bp;
8083 struct bnx2x_phy *phy;
8085 u8 gpio_num, gpio_port;
8087 phy = ¶ms->phy[INT_PHY];
8089 phy = ¶ms->phy[EXT_PHY1];
8091 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8092 params->port, &gpio_num, &gpio_port) ==
8094 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8098 /* Set valid module led off */
8099 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8101 /* Get current gpio val reflecting module plugged in / out*/
8102 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8104 /* Call the handling function in case module is detected */
8105 if (gpio_val == 0) {
8106 bnx2x_power_sfp_module(params, phy, 1);
8107 bnx2x_set_gpio_int(bp, gpio_num,
8108 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8110 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8111 bnx2x_sfp_module_detection(phy, params);
8113 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8115 u32 val = REG_RD(bp, params->shmem_base +
8116 offsetof(struct shmem_region, dev_info.
8117 port_feature_config[params->port].
8120 bnx2x_set_gpio_int(bp, gpio_num,
8121 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8124 * Module was plugged out.
8125 * Disable transmit for this module
8127 phy->media_type = ETH_PHY_NOT_PRESENT;
8128 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8129 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8130 bnx2x_sfp_set_transmitter(params, phy, 0);
8134 /******************************************************************/
8135 /* Used by 8706 and 8727 */
8136 /******************************************************************/
8137 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8138 struct bnx2x_phy *phy,
8139 u16 alarm_status_offset,
8140 u16 alarm_ctrl_offset)
8142 u16 alarm_status, val;
8143 bnx2x_cl45_read(bp, phy,
8144 MDIO_PMA_DEVAD, alarm_status_offset,
8146 bnx2x_cl45_read(bp, phy,
8147 MDIO_PMA_DEVAD, alarm_status_offset,
8149 /* Mask or enable the fault event. */
8150 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8151 if (alarm_status & (1<<0))
8155 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8157 /******************************************************************/
8158 /* common BCM8706/BCM8726 PHY SECTION */
8159 /******************************************************************/
8160 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8161 struct link_params *params,
8162 struct link_vars *vars)
8165 u16 val1, val2, rx_sd, pcs_status;
8166 struct bnx2x *bp = params->bp;
8167 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8169 bnx2x_cl45_read(bp, phy,
8170 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8172 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8173 MDIO_PMA_LASI_TXCTRL);
8175 /* clear LASI indication*/
8176 bnx2x_cl45_read(bp, phy,
8177 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8178 bnx2x_cl45_read(bp, phy,
8179 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8180 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8182 bnx2x_cl45_read(bp, phy,
8183 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8184 bnx2x_cl45_read(bp, phy,
8185 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8186 bnx2x_cl45_read(bp, phy,
8187 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8188 bnx2x_cl45_read(bp, phy,
8189 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8191 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8192 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8194 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8195 * are set, or if the autoneg bit 1 is set
8197 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8200 vars->line_speed = SPEED_1000;
8202 vars->line_speed = SPEED_10000;
8203 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8204 vars->duplex = DUPLEX_FULL;
8207 /* Capture 10G link fault. Read twice to clear stale value. */
8208 if (vars->line_speed == SPEED_10000) {
8209 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8210 MDIO_PMA_LASI_TXSTAT, &val1);
8211 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8212 MDIO_PMA_LASI_TXSTAT, &val1);
8214 vars->fault_detected = 1;
8220 /******************************************************************/
8221 /* BCM8706 PHY SECTION */
8222 /******************************************************************/
8223 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8224 struct link_params *params,
8225 struct link_vars *vars)
8229 struct bnx2x *bp = params->bp;
8231 /* SPF+ PHY: Set flag to check for Tx error */
8232 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8234 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8235 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8237 bnx2x_ext_phy_hw_reset(bp, params->port);
8238 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8239 bnx2x_wait_reset_complete(bp, phy, params);
8241 /* Wait until fw is loaded */
8242 for (cnt = 0; cnt < 100; cnt++) {
8243 bnx2x_cl45_read(bp, phy,
8244 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8249 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8250 if ((params->feature_config_flags &
8251 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8254 for (i = 0; i < 4; i++) {
8255 reg = MDIO_XS_8706_REG_BANK_RX0 +
8256 i*(MDIO_XS_8706_REG_BANK_RX1 -
8257 MDIO_XS_8706_REG_BANK_RX0);
8258 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8259 /* Clear first 3 bits of the control */
8261 /* Set control bits according to configuration */
8262 val |= (phy->rx_preemphasis[i] & 0x7);
8263 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8264 " reg 0x%x <-- val 0x%x\n", reg, val);
8265 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8269 if (phy->req_line_speed == SPEED_10000) {
8270 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8272 bnx2x_cl45_write(bp, phy,
8274 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8275 bnx2x_cl45_write(bp, phy,
8276 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8278 /* Arm LASI for link and Tx fault. */
8279 bnx2x_cl45_write(bp, phy,
8280 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8282 /* Force 1Gbps using autoneg with 1G advertisement */
8284 /* Allow CL37 through CL73 */
8285 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8286 bnx2x_cl45_write(bp, phy,
8287 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8289 /* Enable Full-Duplex advertisement on CL37 */
8290 bnx2x_cl45_write(bp, phy,
8291 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8292 /* Enable CL37 AN */
8293 bnx2x_cl45_write(bp, phy,
8294 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8296 bnx2x_cl45_write(bp, phy,
8297 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8299 /* Enable clause 73 AN */
8300 bnx2x_cl45_write(bp, phy,
8301 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8302 bnx2x_cl45_write(bp, phy,
8303 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8305 bnx2x_cl45_write(bp, phy,
8306 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8309 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8312 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8313 * power mode, if TX Laser is disabled
8316 tx_en_mode = REG_RD(bp, params->shmem_base +
8317 offsetof(struct shmem_region,
8318 dev_info.port_hw_config[params->port].sfp_ctrl))
8319 & PORT_HW_CFG_TX_LASER_MASK;
8321 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8322 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8323 bnx2x_cl45_read(bp, phy,
8324 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8326 bnx2x_cl45_write(bp, phy,
8327 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8333 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8334 struct link_params *params,
8335 struct link_vars *vars)
8337 return bnx2x_8706_8726_read_status(phy, params, vars);
8340 /******************************************************************/
8341 /* BCM8726 PHY SECTION */
8342 /******************************************************************/
8343 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8344 struct link_params *params)
8346 struct bnx2x *bp = params->bp;
8347 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8348 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8351 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8352 struct link_params *params)
8354 struct bnx2x *bp = params->bp;
8355 /* Need to wait 100ms after reset */
8358 /* Micro controller re-boot */
8359 bnx2x_cl45_write(bp, phy,
8360 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8362 /* Set soft reset */
8363 bnx2x_cl45_write(bp, phy,
8365 MDIO_PMA_REG_GEN_CTRL,
8366 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8368 bnx2x_cl45_write(bp, phy,
8370 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8372 bnx2x_cl45_write(bp, phy,
8374 MDIO_PMA_REG_GEN_CTRL,
8375 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8377 /* wait for 150ms for microcode load */
8380 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8381 bnx2x_cl45_write(bp, phy,
8383 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8386 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8389 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8390 struct link_params *params,
8391 struct link_vars *vars)
8393 struct bnx2x *bp = params->bp;
8395 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8397 bnx2x_cl45_read(bp, phy,
8398 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8400 if (val1 & (1<<15)) {
8401 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8403 vars->line_speed = 0;
8410 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8411 struct link_params *params,
8412 struct link_vars *vars)
8414 struct bnx2x *bp = params->bp;
8415 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8417 /* SPF+ PHY: Set flag to check for Tx error */
8418 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8420 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8421 bnx2x_wait_reset_complete(bp, phy, params);
8423 bnx2x_8726_external_rom_boot(phy, params);
8426 * Need to call module detected on initialization since the module
8427 * detection triggered by actual module insertion might occur before
8428 * driver is loaded, and when driver is loaded, it reset all
8429 * registers, including the transmitter
8431 bnx2x_sfp_module_detection(phy, params);
8433 if (phy->req_line_speed == SPEED_1000) {
8434 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8435 bnx2x_cl45_write(bp, phy,
8436 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8437 bnx2x_cl45_write(bp, phy,
8438 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8439 bnx2x_cl45_write(bp, phy,
8440 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8441 bnx2x_cl45_write(bp, phy,
8442 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8444 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8445 (phy->speed_cap_mask &
8446 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8447 ((phy->speed_cap_mask &
8448 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8449 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8450 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8451 /* Set Flow control */
8452 bnx2x_ext_phy_set_pause(params, phy, vars);
8453 bnx2x_cl45_write(bp, phy,
8454 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8455 bnx2x_cl45_write(bp, phy,
8456 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8457 bnx2x_cl45_write(bp, phy,
8458 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8459 bnx2x_cl45_write(bp, phy,
8460 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8461 bnx2x_cl45_write(bp, phy,
8462 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8464 * Enable RX-ALARM control to receive interrupt for 1G speed
8467 bnx2x_cl45_write(bp, phy,
8468 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8469 bnx2x_cl45_write(bp, phy,
8470 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8473 } else { /* Default 10G. Set only LASI control */
8474 bnx2x_cl45_write(bp, phy,
8475 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8478 /* Set TX PreEmphasis if needed */
8479 if ((params->feature_config_flags &
8480 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8481 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8483 phy->tx_preemphasis[0],
8484 phy->tx_preemphasis[1]);
8485 bnx2x_cl45_write(bp, phy,
8487 MDIO_PMA_REG_8726_TX_CTRL1,
8488 phy->tx_preemphasis[0]);
8490 bnx2x_cl45_write(bp, phy,
8492 MDIO_PMA_REG_8726_TX_CTRL2,
8493 phy->tx_preemphasis[1]);
8500 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8501 struct link_params *params)
8503 struct bnx2x *bp = params->bp;
8504 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8505 /* Set serial boot control for external load */
8506 bnx2x_cl45_write(bp, phy,
8508 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8511 /******************************************************************/
8512 /* BCM8727 PHY SECTION */
8513 /******************************************************************/
8515 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8516 struct link_params *params, u8 mode)
8518 struct bnx2x *bp = params->bp;
8519 u16 led_mode_bitmask = 0;
8520 u16 gpio_pins_bitmask = 0;
8522 /* Only NOC flavor requires to set the LED specifically */
8523 if (!(phy->flags & FLAGS_NOC))
8526 case LED_MODE_FRONT_PANEL_OFF:
8528 led_mode_bitmask = 0;
8529 gpio_pins_bitmask = 0x03;
8532 led_mode_bitmask = 0;
8533 gpio_pins_bitmask = 0x02;
8536 led_mode_bitmask = 0x60;
8537 gpio_pins_bitmask = 0x11;
8540 bnx2x_cl45_read(bp, phy,
8542 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8545 val |= led_mode_bitmask;
8546 bnx2x_cl45_write(bp, phy,
8548 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8550 bnx2x_cl45_read(bp, phy,
8552 MDIO_PMA_REG_8727_GPIO_CTRL,
8555 val |= gpio_pins_bitmask;
8556 bnx2x_cl45_write(bp, phy,
8558 MDIO_PMA_REG_8727_GPIO_CTRL,
8561 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8562 struct link_params *params) {
8563 u32 swap_val, swap_override;
8566 * The PHY reset is controlled by GPIO 1. Fake the port number
8567 * to cancel the swap done in set_gpio()
8569 struct bnx2x *bp = params->bp;
8570 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8571 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8572 port = (swap_val && swap_override) ^ 1;
8573 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8574 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8577 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8578 struct link_params *params,
8579 struct link_vars *vars)
8582 u16 tmp1, val, mod_abs, tmp2;
8583 u16 rx_alarm_ctrl_val;
8585 struct bnx2x *bp = params->bp;
8586 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8588 /* SPF+ PHY: Set flag to check for Tx error */
8589 vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8591 bnx2x_wait_reset_complete(bp, phy, params);
8592 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8593 /* Should be 0x6 to enable XS on Tx side. */
8594 lasi_ctrl_val = 0x0006;
8596 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8598 bnx2x_cl45_write(bp, phy,
8599 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8601 bnx2x_cl45_write(bp, phy,
8602 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8604 bnx2x_cl45_write(bp, phy,
8605 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8608 * Initially configure MOD_ABS to interrupt when module is
8611 bnx2x_cl45_read(bp, phy,
8612 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8614 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8615 * When the EDC is off it locks onto a reference clock and avoids
8619 if (!(phy->flags & FLAGS_NOC))
8621 bnx2x_cl45_write(bp, phy,
8622 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8625 /* Enable/Disable PHY transmitter output */
8626 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8628 /* Make MOD_ABS give interrupt on change */
8629 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8632 if (phy->flags & FLAGS_NOC)
8636 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8637 * status which reflect SFP+ module over-current
8639 if (!(phy->flags & FLAGS_NOC))
8640 val &= 0xff8f; /* Reset bits 4-6 */
8641 bnx2x_cl45_write(bp, phy,
8642 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8644 bnx2x_8727_power_module(bp, phy, 1);
8646 bnx2x_cl45_read(bp, phy,
8647 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8649 bnx2x_cl45_read(bp, phy,
8650 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8652 /* Set option 1G speed */
8653 if (phy->req_line_speed == SPEED_1000) {
8654 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8655 bnx2x_cl45_write(bp, phy,
8656 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8657 bnx2x_cl45_write(bp, phy,
8658 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8659 bnx2x_cl45_read(bp, phy,
8660 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8661 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8663 * Power down the XAUI until link is up in case of dual-media
8666 if (DUAL_MEDIA(params)) {
8667 bnx2x_cl45_read(bp, phy,
8669 MDIO_PMA_REG_8727_PCS_GP, &val);
8671 bnx2x_cl45_write(bp, phy,
8673 MDIO_PMA_REG_8727_PCS_GP, val);
8675 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8676 ((phy->speed_cap_mask &
8677 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8678 ((phy->speed_cap_mask &
8679 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8680 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8682 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8683 bnx2x_cl45_write(bp, phy,
8684 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8685 bnx2x_cl45_write(bp, phy,
8686 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8689 * Since the 8727 has only single reset pin, need to set the 10G
8690 * registers although it is default
8692 bnx2x_cl45_write(bp, phy,
8693 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8695 bnx2x_cl45_write(bp, phy,
8696 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8697 bnx2x_cl45_write(bp, phy,
8698 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8699 bnx2x_cl45_write(bp, phy,
8700 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8705 * Set 2-wire transfer rate of SFP+ module EEPROM
8706 * to 100Khz since some DACs(direct attached cables) do
8707 * not work at 400Khz.
8709 bnx2x_cl45_write(bp, phy,
8710 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8713 /* Set TX PreEmphasis if needed */
8714 if ((params->feature_config_flags &
8715 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8716 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8717 phy->tx_preemphasis[0],
8718 phy->tx_preemphasis[1]);
8719 bnx2x_cl45_write(bp, phy,
8720 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8721 phy->tx_preemphasis[0]);
8723 bnx2x_cl45_write(bp, phy,
8724 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8725 phy->tx_preemphasis[1]);
8729 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8730 * power mode, if TX Laser is disabled
8732 tx_en_mode = REG_RD(bp, params->shmem_base +
8733 offsetof(struct shmem_region,
8734 dev_info.port_hw_config[params->port].sfp_ctrl))
8735 & PORT_HW_CFG_TX_LASER_MASK;
8737 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8739 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8740 bnx2x_cl45_read(bp, phy,
8741 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8744 bnx2x_cl45_write(bp, phy,
8745 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8751 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8752 struct link_params *params)
8754 struct bnx2x *bp = params->bp;
8755 u16 mod_abs, rx_alarm_status;
8756 u32 val = REG_RD(bp, params->shmem_base +
8757 offsetof(struct shmem_region, dev_info.
8758 port_feature_config[params->port].
8760 bnx2x_cl45_read(bp, phy,
8762 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8763 if (mod_abs & (1<<8)) {
8765 /* Module is absent */
8766 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8767 "show module is absent\n");
8768 phy->media_type = ETH_PHY_NOT_PRESENT;
8770 * 1. Set mod_abs to detect next module
8772 * 2. Set EDC off by setting OPTXLOS signal input to low
8774 * When the EDC is off it locks onto a reference clock and
8775 * avoids becoming 'lost'.
8778 if (!(phy->flags & FLAGS_NOC))
8780 bnx2x_cl45_write(bp, phy,
8782 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8785 * Clear RX alarm since it stays up as long as
8786 * the mod_abs wasn't changed
8788 bnx2x_cl45_read(bp, phy,
8790 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8793 /* Module is present */
8794 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8795 "show module is present\n");
8797 * First disable transmitter, and if the module is ok, the
8798 * module_detection will enable it
8799 * 1. Set mod_abs to detect next module absent event ( bit 8)
8800 * 2. Restore the default polarity of the OPRXLOS signal and
8801 * this signal will then correctly indicate the presence or
8802 * absence of the Rx signal. (bit 9)
8805 if (!(phy->flags & FLAGS_NOC))
8807 bnx2x_cl45_write(bp, phy,
8809 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8812 * Clear RX alarm since it stays up as long as the mod_abs
8813 * wasn't changed. This is need to be done before calling the
8814 * module detection, otherwise it will clear* the link update
8817 bnx2x_cl45_read(bp, phy,
8819 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8822 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8823 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8824 bnx2x_sfp_set_transmitter(params, phy, 0);
8826 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8827 bnx2x_sfp_module_detection(phy, params);
8829 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8832 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8834 /* No need to check link status in case of module plugged in/out */
8837 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8838 struct link_params *params,
8839 struct link_vars *vars)
8842 struct bnx2x *bp = params->bp;
8843 u8 link_up = 0, oc_port = params->port;
8844 u16 link_status = 0;
8845 u16 rx_alarm_status, lasi_ctrl, val1;
8847 /* If PHY is not initialized, do not check link status */
8848 bnx2x_cl45_read(bp, phy,
8849 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8854 /* Check the LASI on Rx */
8855 bnx2x_cl45_read(bp, phy,
8856 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8858 vars->line_speed = 0;
8859 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
8861 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8862 MDIO_PMA_LASI_TXCTRL);
8864 bnx2x_cl45_read(bp, phy,
8865 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8867 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8870 bnx2x_cl45_read(bp, phy,
8871 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8874 * If a module is present and there is need to check
8877 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8878 /* Check over-current using 8727 GPIO0 input*/
8879 bnx2x_cl45_read(bp, phy,
8880 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8883 if ((val1 & (1<<8)) == 0) {
8884 if (!CHIP_IS_E1x(bp))
8885 oc_port = BP_PATH(bp) + (params->port << 1);
8886 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8887 " on port %d\n", oc_port);
8888 netdev_err(bp->dev, "Error: Power fault on Port %d has"
8889 " been detected and the power to "
8890 "that SFP+ module has been removed"
8891 " to prevent failure of the card."
8892 " Please remove the SFP+ module and"
8893 " restart the system to clear this"
8896 /* Disable all RX_ALARMs except for mod_abs */
8897 bnx2x_cl45_write(bp, phy,
8899 MDIO_PMA_LASI_RXCTRL, (1<<5));
8901 bnx2x_cl45_read(bp, phy,
8903 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8904 /* Wait for module_absent_event */
8906 bnx2x_cl45_write(bp, phy,
8908 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8909 /* Clear RX alarm */
8910 bnx2x_cl45_read(bp, phy,
8912 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8915 } /* Over current check */
8917 /* When module absent bit is set, check module */
8918 if (rx_alarm_status & (1<<5)) {
8919 bnx2x_8727_handle_mod_abs(phy, params);
8920 /* Enable all mod_abs and link detection bits */
8921 bnx2x_cl45_write(bp, phy,
8922 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8925 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8926 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8927 /* If transmitter is disabled, ignore false link up indication */
8928 bnx2x_cl45_read(bp, phy,
8929 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8930 if (val1 & (1<<15)) {
8931 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8935 bnx2x_cl45_read(bp, phy,
8937 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8940 * Bits 0..2 --> speed detected,
8941 * Bits 13..15--> link is down
8943 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8945 vars->line_speed = SPEED_10000;
8946 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8948 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8950 vars->line_speed = SPEED_1000;
8951 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8955 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8959 /* Capture 10G link fault. */
8960 if (vars->line_speed == SPEED_10000) {
8961 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8962 MDIO_PMA_LASI_TXSTAT, &val1);
8964 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8965 MDIO_PMA_LASI_TXSTAT, &val1);
8967 if (val1 & (1<<0)) {
8968 vars->fault_detected = 1;
8973 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8974 vars->duplex = DUPLEX_FULL;
8975 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8978 if ((DUAL_MEDIA(params)) &&
8979 (phy->req_line_speed == SPEED_1000)) {
8980 bnx2x_cl45_read(bp, phy,
8982 MDIO_PMA_REG_8727_PCS_GP, &val1);
8984 * In case of dual-media board and 1G, power up the XAUI side,
8985 * otherwise power it down. For 10G it is done automatically
8991 bnx2x_cl45_write(bp, phy,
8993 MDIO_PMA_REG_8727_PCS_GP, val1);
8998 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
8999 struct link_params *params)
9001 struct bnx2x *bp = params->bp;
9003 /* Enable/Disable PHY transmitter output */
9004 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9006 /* Disable Transmitter */
9007 bnx2x_sfp_set_transmitter(params, phy, 0);
9009 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9013 /******************************************************************/
9014 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9015 /******************************************************************/
9016 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9017 struct link_params *params)
9019 u16 val, fw_ver1, fw_ver2, cnt;
9021 struct bnx2x *bp = params->bp;
9023 port = params->port;
9025 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9026 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9027 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9028 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9029 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9030 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9031 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9033 for (cnt = 0; cnt < 100; cnt++) {
9034 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9040 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9041 bnx2x_save_spirom_version(bp, port, 0,
9047 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9048 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9049 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9050 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9051 for (cnt = 0; cnt < 100; cnt++) {
9052 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9058 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9059 bnx2x_save_spirom_version(bp, port, 0,
9064 /* lower 16 bits of the register SPI_FW_STATUS */
9065 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9066 /* upper 16 bits of register SPI_FW_STATUS */
9067 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9069 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9073 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9074 struct bnx2x_phy *phy)
9078 /* PHYC_CTL_LED_CTL */
9079 bnx2x_cl45_read(bp, phy,
9081 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9085 bnx2x_cl45_write(bp, phy,
9087 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9089 bnx2x_cl45_write(bp, phy,
9091 MDIO_PMA_REG_8481_LED1_MASK,
9094 bnx2x_cl45_write(bp, phy,
9096 MDIO_PMA_REG_8481_LED2_MASK,
9099 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9100 bnx2x_cl45_write(bp, phy,
9102 MDIO_PMA_REG_8481_LED3_MASK,
9105 /* Select the closest activity blink rate to that in 10/100/1000 */
9106 bnx2x_cl45_write(bp, phy,
9108 MDIO_PMA_REG_8481_LED3_BLINK,
9111 bnx2x_cl45_read(bp, phy,
9113 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9114 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9116 bnx2x_cl45_write(bp, phy,
9118 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9120 /* 'Interrupt Mask' */
9121 bnx2x_cl45_write(bp, phy,
9126 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9127 struct link_params *params,
9128 struct link_vars *vars)
9130 struct bnx2x *bp = params->bp;
9131 u16 autoneg_val, an_1000_val, an_10_100_val;
9132 u16 tmp_req_line_speed;
9134 tmp_req_line_speed = phy->req_line_speed;
9135 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9136 if (phy->req_line_speed == SPEED_10000)
9137 phy->req_line_speed = SPEED_AUTO_NEG;
9140 * This phy uses the NIG latch mechanism since link indication
9141 * arrives through its LED4 and not via its LASI signal, so we
9142 * get steady signal instead of clear on read
9144 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9145 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9147 bnx2x_cl45_write(bp, phy,
9148 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9150 bnx2x_848xx_set_led(bp, phy);
9152 /* set 1000 speed advertisement */
9153 bnx2x_cl45_read(bp, phy,
9154 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9157 bnx2x_ext_phy_set_pause(params, phy, vars);
9158 bnx2x_cl45_read(bp, phy,
9160 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9162 bnx2x_cl45_read(bp, phy,
9163 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9165 /* Disable forced speed */
9166 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9167 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9169 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9170 (phy->speed_cap_mask &
9171 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9172 (phy->req_line_speed == SPEED_1000)) {
9173 an_1000_val |= (1<<8);
9174 autoneg_val |= (1<<9 | 1<<12);
9175 if (phy->req_duplex == DUPLEX_FULL)
9176 an_1000_val |= (1<<9);
9177 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9179 an_1000_val &= ~((1<<8) | (1<<9));
9181 bnx2x_cl45_write(bp, phy,
9182 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9185 /* set 100 speed advertisement */
9186 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9187 (phy->speed_cap_mask &
9188 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9189 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9191 (SUPPORTED_100baseT_Half |
9192 SUPPORTED_100baseT_Full)))) {
9193 an_10_100_val |= (1<<7);
9194 /* Enable autoneg and restart autoneg for legacy speeds */
9195 autoneg_val |= (1<<9 | 1<<12);
9197 if (phy->req_duplex == DUPLEX_FULL)
9198 an_10_100_val |= (1<<8);
9199 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9201 /* set 10 speed advertisement */
9202 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9203 (phy->speed_cap_mask &
9204 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9205 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9207 (SUPPORTED_10baseT_Half |
9208 SUPPORTED_10baseT_Full)))) {
9209 an_10_100_val |= (1<<5);
9210 autoneg_val |= (1<<9 | 1<<12);
9211 if (phy->req_duplex == DUPLEX_FULL)
9212 an_10_100_val |= (1<<6);
9213 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9216 /* Only 10/100 are allowed to work in FORCE mode */
9217 if ((phy->req_line_speed == SPEED_100) &&
9219 (SUPPORTED_100baseT_Half |
9220 SUPPORTED_100baseT_Full))) {
9221 autoneg_val |= (1<<13);
9222 /* Enabled AUTO-MDIX when autoneg is disabled */
9223 bnx2x_cl45_write(bp, phy,
9224 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9225 (1<<15 | 1<<9 | 7<<0));
9226 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9228 if ((phy->req_line_speed == SPEED_10) &&
9230 (SUPPORTED_10baseT_Half |
9231 SUPPORTED_10baseT_Full))) {
9232 /* Enabled AUTO-MDIX when autoneg is disabled */
9233 bnx2x_cl45_write(bp, phy,
9234 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9235 (1<<15 | 1<<9 | 7<<0));
9236 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9239 bnx2x_cl45_write(bp, phy,
9240 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9243 if (phy->req_duplex == DUPLEX_FULL)
9244 autoneg_val |= (1<<8);
9246 bnx2x_cl45_write(bp, phy,
9248 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9250 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9251 (phy->speed_cap_mask &
9252 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9253 (phy->req_line_speed == SPEED_10000)) {
9254 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9255 /* Restart autoneg for 10G*/
9257 bnx2x_cl45_write(bp, phy,
9258 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9260 } else if (phy->req_line_speed != SPEED_10 &&
9261 phy->req_line_speed != SPEED_100) {
9262 bnx2x_cl45_write(bp, phy,
9264 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9267 /* Save spirom version */
9268 bnx2x_save_848xx_spirom_version(phy, params);
9270 phy->req_line_speed = tmp_req_line_speed;
9275 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9276 struct link_params *params,
9277 struct link_vars *vars)
9279 struct bnx2x *bp = params->bp;
9280 /* Restore normal power mode*/
9281 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9282 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9285 bnx2x_ext_phy_hw_reset(bp, params->port);
9286 bnx2x_wait_reset_complete(bp, phy, params);
9288 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9289 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9293 #define PHY84833_HDSHK_WAIT 300
9294 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9295 struct link_params *params,
9296 struct link_vars *vars)
9302 struct bnx2x *bp = params->bp;
9305 /* Check for configuration. */
9306 pair_swap = REG_RD(bp, params->shmem_base +
9307 offsetof(struct shmem_region,
9308 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9309 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9314 data = (u16)pair_swap;
9316 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9317 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9318 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9319 PHY84833_CMD_OPEN_OVERRIDE);
9320 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9321 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9322 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9323 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9327 if (idx >= PHY84833_HDSHK_WAIT) {
9328 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9332 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9333 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9335 /* Issue pair swap command */
9336 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9337 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9338 PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9339 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9340 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9341 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9342 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9343 (val == PHY84833_CMD_COMPLETE_ERROR))
9347 if ((idx >= PHY84833_HDSHK_WAIT) ||
9348 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9349 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9352 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9353 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9354 PHY84833_CMD_CLEAR_COMPLETE);
9355 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9360 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9361 u32 shmem_base_path[],
9367 if (CHIP_IS_E3(bp)) {
9368 /* Assume that these will be GPIOs, not EPIOs. */
9369 for (idx = 0; idx < 2; idx++) {
9370 /* Map config param to register bit. */
9371 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9372 offsetof(struct shmem_region,
9373 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9374 reset_pin[idx] = (reset_pin[idx] &
9375 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9376 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9377 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9378 reset_pin[idx] = (1 << reset_pin[idx]);
9380 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9382 /* E2, look from diff place of shmem. */
9383 for (idx = 0; idx < 2; idx++) {
9384 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9385 offsetof(struct shmem_region,
9386 dev_info.port_hw_config[0].default_cfg));
9387 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9388 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9389 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9390 reset_pin[idx] = (1 << reset_pin[idx]);
9392 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9398 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9399 struct link_params *params)
9401 struct bnx2x *bp = params->bp;
9403 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9404 offsetof(struct shmem2_region,
9405 other_shmem_base_addr));
9407 u32 shmem_base_path[2];
9408 shmem_base_path[0] = params->shmem_base;
9409 shmem_base_path[1] = other_shmem_base_addr;
9411 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9414 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9416 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9422 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9423 u32 shmem_base_path[],
9428 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9430 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9432 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9434 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9440 #define PHY84833_CONSTANT_LATENCY 1193
9441 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9442 struct link_params *params,
9443 struct link_vars *vars)
9445 struct bnx2x *bp = params->bp;
9446 u8 port, initialize = 1;
9449 u32 actual_phy_selection, cms_enable, idx;
9454 if (!(CHIP_IS_E1(bp)))
9457 port = params->port;
9459 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9460 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9461 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9465 bnx2x_cl45_write(bp, phy,
9467 MDIO_PMA_REG_CTRL, 0x8000);
9468 /* Bring PHY out of super isolate mode */
9469 bnx2x_cl45_read(bp, phy,
9471 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9472 val &= ~MDIO_84833_SUPER_ISOLATE;
9473 bnx2x_cl45_write(bp, phy,
9475 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9478 bnx2x_wait_reset_complete(bp, phy, params);
9480 /* Wait for GPHY to come out of reset */
9483 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9484 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9487 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9489 temp = vars->line_speed;
9490 vars->line_speed = SPEED_10000;
9491 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
9492 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
9493 vars->line_speed = temp;
9495 /* Set dual-media configuration according to configuration */
9497 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9498 MDIO_CTL_REG_84823_MEDIA, &val);
9499 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9500 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9501 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9502 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9503 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9505 if (CHIP_IS_E3(bp)) {
9506 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9507 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9509 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9510 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9513 actual_phy_selection = bnx2x_phy_selection(params);
9515 switch (actual_phy_selection) {
9516 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9517 /* Do nothing. Essentially this is like the priority copper */
9519 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9520 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9522 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9523 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9525 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9526 /* Do nothing here. The first PHY won't be initialized at all */
9528 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9529 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9533 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9534 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9536 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9537 MDIO_CTL_REG_84823_MEDIA, val);
9538 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9539 params->multi_phy_config, val);
9542 if (params->feature_config_flags &
9543 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9544 /* Ensure that f/w is ready */
9545 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9546 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9547 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9548 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9550 usleep_range(1000, 1000);
9552 if (idx >= PHY84833_HDSHK_WAIT) {
9553 DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9557 /* Select EEE mode */
9558 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9559 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9562 /* Set Idle and Latency */
9563 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9564 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9565 PHY84833_CONSTANT_LATENCY + 1);
9567 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9568 MDIO_84833_TOP_CFG_DATA3_REG,
9569 PHY84833_CONSTANT_LATENCY + 1);
9571 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9572 MDIO_84833_TOP_CFG_DATA4_REG,
9573 PHY84833_CONSTANT_LATENCY);
9575 /* Send EEE instruction to command register */
9576 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9577 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9578 PHY84833_DIAG_CMD_SET_EEE_MODE);
9580 /* Ensure that the command has completed */
9581 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9582 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9583 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9584 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9585 (val == PHY84833_CMD_COMPLETE_ERROR))
9587 usleep_range(1000, 1000);
9589 if ((idx >= PHY84833_HDSHK_WAIT) ||
9590 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9591 DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9595 /* Reset command handler */
9596 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9597 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9598 PHY84833_CMD_CLEAR_COMPLETE);
9602 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9604 bnx2x_save_848xx_spirom_version(phy, params);
9605 /* 84833 PHY has a better feature and doesn't need to support this. */
9606 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9607 cms_enable = REG_RD(bp, params->shmem_base +
9608 offsetof(struct shmem_region,
9609 dev_info.port_hw_config[params->port].default_cfg)) &
9610 PORT_HW_CFG_ENABLE_CMS_MASK;
9612 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9613 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9615 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9617 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9618 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9619 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9625 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9626 struct link_params *params,
9627 struct link_vars *vars)
9629 struct bnx2x *bp = params->bp;
9630 u16 val, val1, val2;
9634 /* Check 10G-BaseT link status */
9635 /* Check PMD signal ok */
9636 bnx2x_cl45_read(bp, phy,
9637 MDIO_AN_DEVAD, 0xFFFA, &val1);
9638 bnx2x_cl45_read(bp, phy,
9639 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9641 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9643 /* Check link 10G */
9644 if (val2 & (1<<11)) {
9645 vars->line_speed = SPEED_10000;
9646 vars->duplex = DUPLEX_FULL;
9648 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9649 } else { /* Check Legacy speed link */
9650 u16 legacy_status, legacy_speed;
9652 /* Enable expansion register 0x42 (Operation mode status) */
9653 bnx2x_cl45_write(bp, phy,
9655 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9657 /* Get legacy speed operation status */
9658 bnx2x_cl45_read(bp, phy,
9660 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9663 DP(NETIF_MSG_LINK, "Legacy speed status"
9664 " = 0x%x\n", legacy_status);
9665 link_up = ((legacy_status & (1<<11)) == (1<<11));
9667 legacy_speed = (legacy_status & (3<<9));
9668 if (legacy_speed == (0<<9))
9669 vars->line_speed = SPEED_10;
9670 else if (legacy_speed == (1<<9))
9671 vars->line_speed = SPEED_100;
9672 else if (legacy_speed == (2<<9))
9673 vars->line_speed = SPEED_1000;
9674 else /* Should not happen */
9675 vars->line_speed = 0;
9677 if (legacy_status & (1<<8))
9678 vars->duplex = DUPLEX_FULL;
9680 vars->duplex = DUPLEX_HALF;
9682 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9683 " is_duplex_full= %d\n", vars->line_speed,
9684 (vars->duplex == DUPLEX_FULL));
9685 /* Check legacy speed AN resolution */
9686 bnx2x_cl45_read(bp, phy,
9688 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9691 vars->link_status |=
9692 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9693 bnx2x_cl45_read(bp, phy,
9695 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9697 if ((val & (1<<0)) == 0)
9698 vars->link_status |=
9699 LINK_STATUS_PARALLEL_DETECTION_USED;
9703 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9705 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9712 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9716 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9717 status = bnx2x_format_ver(spirom_ver, str, len);
9721 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9722 struct link_params *params)
9724 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9725 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9726 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9727 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9730 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9731 struct link_params *params)
9733 bnx2x_cl45_write(params->bp, phy,
9734 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9735 bnx2x_cl45_write(params->bp, phy,
9736 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9739 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9740 struct link_params *params)
9742 struct bnx2x *bp = params->bp;
9746 if (!(CHIP_IS_E1(bp)))
9749 port = params->port;
9751 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9752 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9753 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9756 bnx2x_cl45_read(bp, phy,
9759 /* Put to low power mode on newer FW */
9760 if ((val16 & 0x303f) > 0x1009)
9761 bnx2x_cl45_write(bp, phy,
9763 MDIO_PMA_REG_CTRL, 0x800);
9767 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9768 struct link_params *params, u8 mode)
9770 struct bnx2x *bp = params->bp;
9774 if (!(CHIP_IS_E1(bp)))
9777 port = params->port;
9782 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9784 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9785 SHARED_HW_CFG_LED_EXTPHY1) {
9788 bnx2x_cl45_write(bp, phy,
9790 MDIO_PMA_REG_8481_LED1_MASK,
9793 bnx2x_cl45_write(bp, phy,
9795 MDIO_PMA_REG_8481_LED2_MASK,
9798 bnx2x_cl45_write(bp, phy,
9800 MDIO_PMA_REG_8481_LED3_MASK,
9803 bnx2x_cl45_write(bp, phy,
9805 MDIO_PMA_REG_8481_LED5_MASK,
9809 bnx2x_cl45_write(bp, phy,
9811 MDIO_PMA_REG_8481_LED1_MASK,
9815 case LED_MODE_FRONT_PANEL_OFF:
9817 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9820 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9821 SHARED_HW_CFG_LED_EXTPHY1) {
9824 bnx2x_cl45_write(bp, phy,
9826 MDIO_PMA_REG_8481_LED1_MASK,
9829 bnx2x_cl45_write(bp, phy,
9831 MDIO_PMA_REG_8481_LED2_MASK,
9834 bnx2x_cl45_write(bp, phy,
9836 MDIO_PMA_REG_8481_LED3_MASK,
9839 bnx2x_cl45_write(bp, phy,
9841 MDIO_PMA_REG_8481_LED5_MASK,
9845 bnx2x_cl45_write(bp, phy,
9847 MDIO_PMA_REG_8481_LED1_MASK,
9853 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9855 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9856 SHARED_HW_CFG_LED_EXTPHY1) {
9857 /* Set control reg */
9858 bnx2x_cl45_read(bp, phy,
9860 MDIO_PMA_REG_8481_LINK_SIGNAL,
9865 bnx2x_cl45_write(bp, phy,
9867 MDIO_PMA_REG_8481_LINK_SIGNAL,
9871 bnx2x_cl45_write(bp, phy,
9873 MDIO_PMA_REG_8481_LED1_MASK,
9876 bnx2x_cl45_write(bp, phy,
9878 MDIO_PMA_REG_8481_LED2_MASK,
9881 bnx2x_cl45_write(bp, phy,
9883 MDIO_PMA_REG_8481_LED3_MASK,
9886 bnx2x_cl45_write(bp, phy,
9888 MDIO_PMA_REG_8481_LED5_MASK,
9891 bnx2x_cl45_write(bp, phy,
9893 MDIO_PMA_REG_8481_LED1_MASK,
9900 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9902 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9903 SHARED_HW_CFG_LED_EXTPHY1) {
9905 /* Set control reg */
9906 bnx2x_cl45_read(bp, phy,
9908 MDIO_PMA_REG_8481_LINK_SIGNAL,
9912 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9913 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9914 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9915 bnx2x_cl45_write(bp, phy,
9917 MDIO_PMA_REG_8481_LINK_SIGNAL,
9922 bnx2x_cl45_write(bp, phy,
9924 MDIO_PMA_REG_8481_LED1_MASK,
9927 bnx2x_cl45_write(bp, phy,
9929 MDIO_PMA_REG_8481_LED2_MASK,
9932 bnx2x_cl45_write(bp, phy,
9934 MDIO_PMA_REG_8481_LED3_MASK,
9937 bnx2x_cl45_write(bp, phy,
9939 MDIO_PMA_REG_8481_LED5_MASK,
9943 bnx2x_cl45_write(bp, phy,
9945 MDIO_PMA_REG_8481_LED1_MASK,
9948 /* Tell LED3 to blink on source */
9949 bnx2x_cl45_read(bp, phy,
9951 MDIO_PMA_REG_8481_LINK_SIGNAL,
9954 val |= (1<<6); /* A83B[8:6]= 1 */
9955 bnx2x_cl45_write(bp, phy,
9957 MDIO_PMA_REG_8481_LINK_SIGNAL,
9964 * This is a workaround for E3+84833 until autoneg
9965 * restart is fixed in f/w
9967 if (CHIP_IS_E3(bp)) {
9968 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9969 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9973 /******************************************************************/
9974 /* 54618SE PHY SECTION */
9975 /******************************************************************/
9976 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
9977 struct link_params *params,
9978 struct link_vars *vars)
9980 struct bnx2x *bp = params->bp;
9982 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9985 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
9986 usleep_range(1000, 1000);
9988 /* This works with E3 only, no need to check the chip
9989 before determining the port. */
9990 port = params->port;
9992 cfg_pin = (REG_RD(bp, params->shmem_base +
9993 offsetof(struct shmem_region,
9994 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9995 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9996 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9998 /* Drive pin high to bring the GPHY out of reset. */
9999 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10001 /* wait for GPHY to reset */
10005 bnx2x_cl22_write(bp, phy,
10006 MDIO_PMA_REG_CTRL, 0x8000);
10007 bnx2x_wait_reset_complete(bp, phy, params);
10009 /*wait for GPHY to reset */
10012 /* Configure LED4: set to INTR (0x6). */
10013 /* Accessing shadow register 0xe. */
10014 bnx2x_cl22_write(bp, phy,
10015 MDIO_REG_GPHY_SHADOW,
10016 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10017 bnx2x_cl22_read(bp, phy,
10018 MDIO_REG_GPHY_SHADOW,
10020 temp &= ~(0xf << 4);
10021 temp |= (0x6 << 4);
10022 bnx2x_cl22_write(bp, phy,
10023 MDIO_REG_GPHY_SHADOW,
10024 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10025 /* Configure INTR based on link status change. */
10026 bnx2x_cl22_write(bp, phy,
10027 MDIO_REG_INTR_MASK,
10028 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10030 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10031 bnx2x_cl22_write(bp, phy,
10032 MDIO_REG_GPHY_SHADOW,
10033 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10034 bnx2x_cl22_read(bp, phy,
10035 MDIO_REG_GPHY_SHADOW,
10037 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10038 bnx2x_cl22_write(bp, phy,
10039 MDIO_REG_GPHY_SHADOW,
10040 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10043 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10044 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10046 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10048 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10050 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10051 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10052 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10054 /* read all advertisement */
10055 bnx2x_cl22_read(bp, phy,
10059 bnx2x_cl22_read(bp, phy,
10063 bnx2x_cl22_read(bp, phy,
10067 /* Disable forced speed */
10068 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10069 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10072 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10073 (phy->speed_cap_mask &
10074 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10075 (phy->req_line_speed == SPEED_1000)) {
10076 an_1000_val |= (1<<8);
10077 autoneg_val |= (1<<9 | 1<<12);
10078 if (phy->req_duplex == DUPLEX_FULL)
10079 an_1000_val |= (1<<9);
10080 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10082 an_1000_val &= ~((1<<8) | (1<<9));
10084 bnx2x_cl22_write(bp, phy,
10087 bnx2x_cl22_read(bp, phy,
10091 /* set 100 speed advertisement */
10092 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10093 (phy->speed_cap_mask &
10094 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10095 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10096 an_10_100_val |= (1<<7);
10097 /* Enable autoneg and restart autoneg for legacy speeds */
10098 autoneg_val |= (1<<9 | 1<<12);
10100 if (phy->req_duplex == DUPLEX_FULL)
10101 an_10_100_val |= (1<<8);
10102 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10105 /* set 10 speed advertisement */
10106 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10107 (phy->speed_cap_mask &
10108 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10109 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10110 an_10_100_val |= (1<<5);
10111 autoneg_val |= (1<<9 | 1<<12);
10112 if (phy->req_duplex == DUPLEX_FULL)
10113 an_10_100_val |= (1<<6);
10114 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10117 /* Only 10/100 are allowed to work in FORCE mode */
10118 if (phy->req_line_speed == SPEED_100) {
10119 autoneg_val |= (1<<13);
10120 /* Enabled AUTO-MDIX when autoneg is disabled */
10121 bnx2x_cl22_write(bp, phy,
10123 (1<<15 | 1<<9 | 7<<0));
10124 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10126 if (phy->req_line_speed == SPEED_10) {
10127 /* Enabled AUTO-MDIX when autoneg is disabled */
10128 bnx2x_cl22_write(bp, phy,
10130 (1<<15 | 1<<9 | 7<<0));
10131 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10134 /* Check if we should turn on Auto-GrEEEn */
10135 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10136 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10137 if (params->feature_config_flags &
10138 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10140 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10143 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10145 bnx2x_cl22_write(bp, phy,
10146 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10147 bnx2x_cl22_write(bp, phy,
10148 MDIO_REG_GPHY_CL45_DATA_REG,
10149 MDIO_REG_GPHY_EEE_ADV);
10150 bnx2x_cl22_write(bp, phy,
10151 MDIO_REG_GPHY_CL45_ADDR_REG,
10152 (0x1 << 14) | MDIO_AN_DEVAD);
10153 bnx2x_cl22_write(bp, phy,
10154 MDIO_REG_GPHY_CL45_DATA_REG,
10158 bnx2x_cl22_write(bp, phy,
10160 an_10_100_val | fc_val);
10162 if (phy->req_duplex == DUPLEX_FULL)
10163 autoneg_val |= (1<<8);
10165 bnx2x_cl22_write(bp, phy,
10166 MDIO_PMA_REG_CTRL, autoneg_val);
10171 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10172 struct link_params *params, u8 mode)
10174 struct bnx2x *bp = params->bp;
10175 DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10177 case LED_MODE_FRONT_PANEL_OFF:
10179 case LED_MODE_OPER:
10187 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10188 struct link_params *params)
10190 struct bnx2x *bp = params->bp;
10194 /* This works with E3 only, no need to check the chip
10195 before determining the port. */
10196 port = params->port;
10197 cfg_pin = (REG_RD(bp, params->shmem_base +
10198 offsetof(struct shmem_region,
10199 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10200 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10201 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10203 /* Drive pin low to put GPHY in reset. */
10204 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10207 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10208 struct link_params *params,
10209 struct link_vars *vars)
10211 struct bnx2x *bp = params->bp;
10214 u16 legacy_status, legacy_speed;
10216 /* Get speed operation status */
10217 bnx2x_cl22_read(bp, phy,
10220 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10222 /* Read status to clear the PHY interrupt. */
10223 bnx2x_cl22_read(bp, phy,
10224 MDIO_REG_INTR_STATUS,
10227 link_up = ((legacy_status & (1<<2)) == (1<<2));
10230 legacy_speed = (legacy_status & (7<<8));
10231 if (legacy_speed == (7<<8)) {
10232 vars->line_speed = SPEED_1000;
10233 vars->duplex = DUPLEX_FULL;
10234 } else if (legacy_speed == (6<<8)) {
10235 vars->line_speed = SPEED_1000;
10236 vars->duplex = DUPLEX_HALF;
10237 } else if (legacy_speed == (5<<8)) {
10238 vars->line_speed = SPEED_100;
10239 vars->duplex = DUPLEX_FULL;
10241 /* Omitting 100Base-T4 for now */
10242 else if (legacy_speed == (3<<8)) {
10243 vars->line_speed = SPEED_100;
10244 vars->duplex = DUPLEX_HALF;
10245 } else if (legacy_speed == (2<<8)) {
10246 vars->line_speed = SPEED_10;
10247 vars->duplex = DUPLEX_FULL;
10248 } else if (legacy_speed == (1<<8)) {
10249 vars->line_speed = SPEED_10;
10250 vars->duplex = DUPLEX_HALF;
10251 } else /* Should not happen */
10252 vars->line_speed = 0;
10254 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10255 " is_duplex_full= %d\n", vars->line_speed,
10256 (vars->duplex == DUPLEX_FULL));
10258 /* Check legacy speed AN resolution */
10259 bnx2x_cl22_read(bp, phy,
10263 vars->link_status |=
10264 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10265 bnx2x_cl22_read(bp, phy,
10268 if ((val & (1<<0)) == 0)
10269 vars->link_status |=
10270 LINK_STATUS_PARALLEL_DETECTION_USED;
10272 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10275 /* Report whether EEE is resolved. */
10276 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10277 if (val == MDIO_REG_GPHY_ID_54618SE) {
10278 if (vars->link_status &
10279 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10282 bnx2x_cl22_write(bp, phy,
10283 MDIO_REG_GPHY_CL45_ADDR_REG,
10285 bnx2x_cl22_write(bp, phy,
10286 MDIO_REG_GPHY_CL45_DATA_REG,
10287 MDIO_REG_GPHY_EEE_RESOLVED);
10288 bnx2x_cl22_write(bp, phy,
10289 MDIO_REG_GPHY_CL45_ADDR_REG,
10290 (0x1 << 14) | MDIO_AN_DEVAD);
10291 bnx2x_cl22_read(bp, phy,
10292 MDIO_REG_GPHY_CL45_DATA_REG,
10295 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10298 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10303 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10304 struct link_params *params)
10306 struct bnx2x *bp = params->bp;
10308 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10310 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10312 /* Enable master/slave manual mmode and set to master */
10313 /* mii write 9 [bits set 11 12] */
10314 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10316 /* forced 1G and disable autoneg */
10317 /* set val [mii read 0] */
10318 /* set val [expr $val & [bits clear 6 12 13]] */
10319 /* set val [expr $val | [bits set 6 8]] */
10320 /* mii write 0 $val */
10321 bnx2x_cl22_read(bp, phy, 0x00, &val);
10322 val &= ~((1<<6) | (1<<12) | (1<<13));
10323 val |= (1<<6) | (1<<8);
10324 bnx2x_cl22_write(bp, phy, 0x00, val);
10326 /* Set external loopback and Tx using 6dB coding */
10327 /* mii write 0x18 7 */
10328 /* set val [mii read 0x18] */
10329 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10330 bnx2x_cl22_write(bp, phy, 0x18, 7);
10331 bnx2x_cl22_read(bp, phy, 0x18, &val);
10332 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10334 /* This register opens the gate for the UMAC despite its name */
10335 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10338 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10339 * length used by the MAC receive logic to check frames.
10341 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10344 /******************************************************************/
10345 /* SFX7101 PHY SECTION */
10346 /******************************************************************/
10347 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10348 struct link_params *params)
10350 struct bnx2x *bp = params->bp;
10351 /* SFX7101_XGXS_TEST1 */
10352 bnx2x_cl45_write(bp, phy,
10353 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10356 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10357 struct link_params *params,
10358 struct link_vars *vars)
10360 u16 fw_ver1, fw_ver2, val;
10361 struct bnx2x *bp = params->bp;
10362 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10364 /* Restore normal power mode*/
10365 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10366 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10368 bnx2x_ext_phy_hw_reset(bp, params->port);
10369 bnx2x_wait_reset_complete(bp, phy, params);
10371 bnx2x_cl45_write(bp, phy,
10372 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10373 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10374 bnx2x_cl45_write(bp, phy,
10375 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10377 bnx2x_ext_phy_set_pause(params, phy, vars);
10378 /* Restart autoneg */
10379 bnx2x_cl45_read(bp, phy,
10380 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10382 bnx2x_cl45_write(bp, phy,
10383 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10385 /* Save spirom version */
10386 bnx2x_cl45_read(bp, phy,
10387 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10389 bnx2x_cl45_read(bp, phy,
10390 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10391 bnx2x_save_spirom_version(bp, params->port,
10392 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10396 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10397 struct link_params *params,
10398 struct link_vars *vars)
10400 struct bnx2x *bp = params->bp;
10403 bnx2x_cl45_read(bp, phy,
10404 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10405 bnx2x_cl45_read(bp, phy,
10406 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10407 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10409 bnx2x_cl45_read(bp, phy,
10410 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10411 bnx2x_cl45_read(bp, phy,
10412 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10413 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10415 link_up = ((val1 & 4) == 4);
10416 /* if link is up print the AN outcome of the SFX7101 PHY */
10418 bnx2x_cl45_read(bp, phy,
10419 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10421 vars->line_speed = SPEED_10000;
10422 vars->duplex = DUPLEX_FULL;
10423 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10424 val2, (val2 & (1<<14)));
10425 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10426 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10431 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10435 str[0] = (spirom_ver & 0xFF);
10436 str[1] = (spirom_ver & 0xFF00) >> 8;
10437 str[2] = (spirom_ver & 0xFF0000) >> 16;
10438 str[3] = (spirom_ver & 0xFF000000) >> 24;
10444 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10448 bnx2x_cl45_read(bp, phy,
10450 MDIO_PMA_REG_7101_RESET, &val);
10452 for (cnt = 0; cnt < 10; cnt++) {
10454 /* Writes a self-clearing reset */
10455 bnx2x_cl45_write(bp, phy,
10457 MDIO_PMA_REG_7101_RESET,
10459 /* Wait for clear */
10460 bnx2x_cl45_read(bp, phy,
10462 MDIO_PMA_REG_7101_RESET, &val);
10464 if ((val & (1<<15)) == 0)
10469 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10470 struct link_params *params) {
10471 /* Low power mode is controlled by GPIO 2 */
10472 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10473 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10474 /* The PHY reset is controlled by GPIO 1 */
10475 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10476 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10479 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10480 struct link_params *params, u8 mode)
10483 struct bnx2x *bp = params->bp;
10485 case LED_MODE_FRONT_PANEL_OFF:
10492 case LED_MODE_OPER:
10496 bnx2x_cl45_write(bp, phy,
10498 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10502 /******************************************************************/
10503 /* STATIC PHY DECLARATION */
10504 /******************************************************************/
10506 static struct bnx2x_phy phy_null = {
10507 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10510 .flags = FLAGS_INIT_XGXS_FIRST,
10511 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10512 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10515 .media_type = ETH_PHY_NOT_PRESENT,
10517 .req_flow_ctrl = 0,
10518 .req_line_speed = 0,
10519 .speed_cap_mask = 0,
10522 .config_init = (config_init_t)NULL,
10523 .read_status = (read_status_t)NULL,
10524 .link_reset = (link_reset_t)NULL,
10525 .config_loopback = (config_loopback_t)NULL,
10526 .format_fw_ver = (format_fw_ver_t)NULL,
10527 .hw_reset = (hw_reset_t)NULL,
10528 .set_link_led = (set_link_led_t)NULL,
10529 .phy_specific_func = (phy_specific_func_t)NULL
10532 static struct bnx2x_phy phy_serdes = {
10533 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10537 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10538 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10540 .supported = (SUPPORTED_10baseT_Half |
10541 SUPPORTED_10baseT_Full |
10542 SUPPORTED_100baseT_Half |
10543 SUPPORTED_100baseT_Full |
10544 SUPPORTED_1000baseT_Full |
10545 SUPPORTED_2500baseX_Full |
10547 SUPPORTED_Autoneg |
10549 SUPPORTED_Asym_Pause),
10550 .media_type = ETH_PHY_BASE_T,
10552 .req_flow_ctrl = 0,
10553 .req_line_speed = 0,
10554 .speed_cap_mask = 0,
10557 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10558 .read_status = (read_status_t)bnx2x_link_settings_status,
10559 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10560 .config_loopback = (config_loopback_t)NULL,
10561 .format_fw_ver = (format_fw_ver_t)NULL,
10562 .hw_reset = (hw_reset_t)NULL,
10563 .set_link_led = (set_link_led_t)NULL,
10564 .phy_specific_func = (phy_specific_func_t)NULL
10567 static struct bnx2x_phy phy_xgxs = {
10568 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10572 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10573 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10575 .supported = (SUPPORTED_10baseT_Half |
10576 SUPPORTED_10baseT_Full |
10577 SUPPORTED_100baseT_Half |
10578 SUPPORTED_100baseT_Full |
10579 SUPPORTED_1000baseT_Full |
10580 SUPPORTED_2500baseX_Full |
10581 SUPPORTED_10000baseT_Full |
10583 SUPPORTED_Autoneg |
10585 SUPPORTED_Asym_Pause),
10586 .media_type = ETH_PHY_CX4,
10588 .req_flow_ctrl = 0,
10589 .req_line_speed = 0,
10590 .speed_cap_mask = 0,
10593 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10594 .read_status = (read_status_t)bnx2x_link_settings_status,
10595 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10596 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10597 .format_fw_ver = (format_fw_ver_t)NULL,
10598 .hw_reset = (hw_reset_t)NULL,
10599 .set_link_led = (set_link_led_t)NULL,
10600 .phy_specific_func = (phy_specific_func_t)NULL
10602 static struct bnx2x_phy phy_warpcore = {
10603 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10606 .flags = FLAGS_HW_LOCK_REQUIRED,
10607 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10608 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10610 .supported = (SUPPORTED_10baseT_Half |
10611 SUPPORTED_10baseT_Full |
10612 SUPPORTED_100baseT_Half |
10613 SUPPORTED_100baseT_Full |
10614 SUPPORTED_1000baseT_Full |
10615 SUPPORTED_10000baseT_Full |
10616 SUPPORTED_20000baseKR2_Full |
10617 SUPPORTED_20000baseMLD2_Full |
10619 SUPPORTED_Autoneg |
10621 SUPPORTED_Asym_Pause),
10622 .media_type = ETH_PHY_UNSPECIFIED,
10624 .req_flow_ctrl = 0,
10625 .req_line_speed = 0,
10626 .speed_cap_mask = 0,
10627 /* req_duplex = */0,
10629 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10630 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10631 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10632 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10633 .format_fw_ver = (format_fw_ver_t)NULL,
10634 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10635 .set_link_led = (set_link_led_t)NULL,
10636 .phy_specific_func = (phy_specific_func_t)NULL
10640 static struct bnx2x_phy phy_7101 = {
10641 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10644 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10645 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10646 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10648 .supported = (SUPPORTED_10000baseT_Full |
10650 SUPPORTED_Autoneg |
10652 SUPPORTED_Asym_Pause),
10653 .media_type = ETH_PHY_BASE_T,
10655 .req_flow_ctrl = 0,
10656 .req_line_speed = 0,
10657 .speed_cap_mask = 0,
10660 .config_init = (config_init_t)bnx2x_7101_config_init,
10661 .read_status = (read_status_t)bnx2x_7101_read_status,
10662 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10663 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10664 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10665 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10666 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10667 .phy_specific_func = (phy_specific_func_t)NULL
10669 static struct bnx2x_phy phy_8073 = {
10670 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10673 .flags = FLAGS_HW_LOCK_REQUIRED,
10674 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10675 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10677 .supported = (SUPPORTED_10000baseT_Full |
10678 SUPPORTED_2500baseX_Full |
10679 SUPPORTED_1000baseT_Full |
10681 SUPPORTED_Autoneg |
10683 SUPPORTED_Asym_Pause),
10684 .media_type = ETH_PHY_KR,
10686 .req_flow_ctrl = 0,
10687 .req_line_speed = 0,
10688 .speed_cap_mask = 0,
10691 .config_init = (config_init_t)bnx2x_8073_config_init,
10692 .read_status = (read_status_t)bnx2x_8073_read_status,
10693 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10694 .config_loopback = (config_loopback_t)NULL,
10695 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10696 .hw_reset = (hw_reset_t)NULL,
10697 .set_link_led = (set_link_led_t)NULL,
10698 .phy_specific_func = (phy_specific_func_t)NULL
10700 static struct bnx2x_phy phy_8705 = {
10701 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10704 .flags = FLAGS_INIT_XGXS_FIRST,
10705 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10706 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10708 .supported = (SUPPORTED_10000baseT_Full |
10711 SUPPORTED_Asym_Pause),
10712 .media_type = ETH_PHY_XFP_FIBER,
10714 .req_flow_ctrl = 0,
10715 .req_line_speed = 0,
10716 .speed_cap_mask = 0,
10719 .config_init = (config_init_t)bnx2x_8705_config_init,
10720 .read_status = (read_status_t)bnx2x_8705_read_status,
10721 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10722 .config_loopback = (config_loopback_t)NULL,
10723 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10724 .hw_reset = (hw_reset_t)NULL,
10725 .set_link_led = (set_link_led_t)NULL,
10726 .phy_specific_func = (phy_specific_func_t)NULL
10728 static struct bnx2x_phy phy_8706 = {
10729 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10732 .flags = FLAGS_INIT_XGXS_FIRST,
10733 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10734 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10736 .supported = (SUPPORTED_10000baseT_Full |
10737 SUPPORTED_1000baseT_Full |
10740 SUPPORTED_Asym_Pause),
10741 .media_type = ETH_PHY_SFP_FIBER,
10743 .req_flow_ctrl = 0,
10744 .req_line_speed = 0,
10745 .speed_cap_mask = 0,
10748 .config_init = (config_init_t)bnx2x_8706_config_init,
10749 .read_status = (read_status_t)bnx2x_8706_read_status,
10750 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10751 .config_loopback = (config_loopback_t)NULL,
10752 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10753 .hw_reset = (hw_reset_t)NULL,
10754 .set_link_led = (set_link_led_t)NULL,
10755 .phy_specific_func = (phy_specific_func_t)NULL
10758 static struct bnx2x_phy phy_8726 = {
10759 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10762 .flags = (FLAGS_HW_LOCK_REQUIRED |
10763 FLAGS_INIT_XGXS_FIRST),
10764 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10765 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10767 .supported = (SUPPORTED_10000baseT_Full |
10768 SUPPORTED_1000baseT_Full |
10769 SUPPORTED_Autoneg |
10772 SUPPORTED_Asym_Pause),
10773 .media_type = ETH_PHY_NOT_PRESENT,
10775 .req_flow_ctrl = 0,
10776 .req_line_speed = 0,
10777 .speed_cap_mask = 0,
10780 .config_init = (config_init_t)bnx2x_8726_config_init,
10781 .read_status = (read_status_t)bnx2x_8726_read_status,
10782 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
10783 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10784 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10785 .hw_reset = (hw_reset_t)NULL,
10786 .set_link_led = (set_link_led_t)NULL,
10787 .phy_specific_func = (phy_specific_func_t)NULL
10790 static struct bnx2x_phy phy_8727 = {
10791 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10794 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10795 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10796 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10798 .supported = (SUPPORTED_10000baseT_Full |
10799 SUPPORTED_1000baseT_Full |
10802 SUPPORTED_Asym_Pause),
10803 .media_type = ETH_PHY_NOT_PRESENT,
10805 .req_flow_ctrl = 0,
10806 .req_line_speed = 0,
10807 .speed_cap_mask = 0,
10810 .config_init = (config_init_t)bnx2x_8727_config_init,
10811 .read_status = (read_status_t)bnx2x_8727_read_status,
10812 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
10813 .config_loopback = (config_loopback_t)NULL,
10814 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10815 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
10816 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
10817 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10819 static struct bnx2x_phy phy_8481 = {
10820 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10823 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10824 FLAGS_REARM_LATCH_SIGNAL,
10825 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10826 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10828 .supported = (SUPPORTED_10baseT_Half |
10829 SUPPORTED_10baseT_Full |
10830 SUPPORTED_100baseT_Half |
10831 SUPPORTED_100baseT_Full |
10832 SUPPORTED_1000baseT_Full |
10833 SUPPORTED_10000baseT_Full |
10835 SUPPORTED_Autoneg |
10837 SUPPORTED_Asym_Pause),
10838 .media_type = ETH_PHY_BASE_T,
10840 .req_flow_ctrl = 0,
10841 .req_line_speed = 0,
10842 .speed_cap_mask = 0,
10845 .config_init = (config_init_t)bnx2x_8481_config_init,
10846 .read_status = (read_status_t)bnx2x_848xx_read_status,
10847 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
10848 .config_loopback = (config_loopback_t)NULL,
10849 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10850 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
10851 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10852 .phy_specific_func = (phy_specific_func_t)NULL
10855 static struct bnx2x_phy phy_84823 = {
10856 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10859 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10860 FLAGS_REARM_LATCH_SIGNAL,
10861 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10862 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10864 .supported = (SUPPORTED_10baseT_Half |
10865 SUPPORTED_10baseT_Full |
10866 SUPPORTED_100baseT_Half |
10867 SUPPORTED_100baseT_Full |
10868 SUPPORTED_1000baseT_Full |
10869 SUPPORTED_10000baseT_Full |
10871 SUPPORTED_Autoneg |
10873 SUPPORTED_Asym_Pause),
10874 .media_type = ETH_PHY_BASE_T,
10876 .req_flow_ctrl = 0,
10877 .req_line_speed = 0,
10878 .speed_cap_mask = 0,
10881 .config_init = (config_init_t)bnx2x_848x3_config_init,
10882 .read_status = (read_status_t)bnx2x_848xx_read_status,
10883 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10884 .config_loopback = (config_loopback_t)NULL,
10885 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10886 .hw_reset = (hw_reset_t)NULL,
10887 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10888 .phy_specific_func = (phy_specific_func_t)NULL
10891 static struct bnx2x_phy phy_84833 = {
10892 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10895 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10896 FLAGS_REARM_LATCH_SIGNAL,
10897 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10898 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10900 .supported = (SUPPORTED_100baseT_Half |
10901 SUPPORTED_100baseT_Full |
10902 SUPPORTED_1000baseT_Full |
10903 SUPPORTED_10000baseT_Full |
10905 SUPPORTED_Autoneg |
10907 SUPPORTED_Asym_Pause),
10908 .media_type = ETH_PHY_BASE_T,
10910 .req_flow_ctrl = 0,
10911 .req_line_speed = 0,
10912 .speed_cap_mask = 0,
10915 .config_init = (config_init_t)bnx2x_848x3_config_init,
10916 .read_status = (read_status_t)bnx2x_848xx_read_status,
10917 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10918 .config_loopback = (config_loopback_t)NULL,
10919 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10920 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10921 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10922 .phy_specific_func = (phy_specific_func_t)NULL
10925 static struct bnx2x_phy phy_54618se = {
10926 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10929 .flags = FLAGS_INIT_XGXS_FIRST,
10930 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10931 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10933 .supported = (SUPPORTED_10baseT_Half |
10934 SUPPORTED_10baseT_Full |
10935 SUPPORTED_100baseT_Half |
10936 SUPPORTED_100baseT_Full |
10937 SUPPORTED_1000baseT_Full |
10939 SUPPORTED_Autoneg |
10941 SUPPORTED_Asym_Pause),
10942 .media_type = ETH_PHY_BASE_T,
10944 .req_flow_ctrl = 0,
10945 .req_line_speed = 0,
10946 .speed_cap_mask = 0,
10947 /* req_duplex = */0,
10949 .config_init = (config_init_t)bnx2x_54618se_config_init,
10950 .read_status = (read_status_t)bnx2x_54618se_read_status,
10951 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
10952 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10953 .format_fw_ver = (format_fw_ver_t)NULL,
10954 .hw_reset = (hw_reset_t)NULL,
10955 .set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led,
10956 .phy_specific_func = (phy_specific_func_t)NULL
10958 /*****************************************************************/
10960 /* Populate the phy according. Main function: bnx2x_populate_phy */
10962 /*****************************************************************/
10964 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10965 struct bnx2x_phy *phy, u8 port,
10968 /* Get the 4 lanes xgxs config rx and tx */
10969 u32 rx = 0, tx = 0, i;
10970 for (i = 0; i < 2; i++) {
10972 * INT_PHY and EXT_PHY1 share the same value location in the
10973 * shmem. When num_phys is greater than 1, than this value
10974 * applies only to EXT_PHY1
10976 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10977 rx = REG_RD(bp, shmem_base +
10978 offsetof(struct shmem_region,
10979 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10981 tx = REG_RD(bp, shmem_base +
10982 offsetof(struct shmem_region,
10983 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10985 rx = REG_RD(bp, shmem_base +
10986 offsetof(struct shmem_region,
10987 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10989 tx = REG_RD(bp, shmem_base +
10990 offsetof(struct shmem_region,
10991 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10994 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
10995 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
10997 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
10998 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11002 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11003 u8 phy_index, u8 port)
11005 u32 ext_phy_config = 0;
11006 switch (phy_index) {
11008 ext_phy_config = REG_RD(bp, shmem_base +
11009 offsetof(struct shmem_region,
11010 dev_info.port_hw_config[port].external_phy_config));
11013 ext_phy_config = REG_RD(bp, shmem_base +
11014 offsetof(struct shmem_region,
11015 dev_info.port_hw_config[port].external_phy_config2));
11018 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11022 return ext_phy_config;
11024 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11025 struct bnx2x_phy *phy)
11029 u32 switch_cfg = (REG_RD(bp, shmem_base +
11030 offsetof(struct shmem_region,
11031 dev_info.port_feature_config[port].link_config)) &
11032 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11033 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11034 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11035 if (USES_WARPCORE(bp)) {
11037 phy_addr = REG_RD(bp,
11038 MISC_REG_WC0_CTRL_PHY_ADDR);
11039 *phy = phy_warpcore;
11040 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11041 phy->flags |= FLAGS_4_PORT_MODE;
11043 phy->flags &= ~FLAGS_4_PORT_MODE;
11044 /* Check Dual mode */
11045 serdes_net_if = (REG_RD(bp, shmem_base +
11046 offsetof(struct shmem_region, dev_info.
11047 port_hw_config[port].default_cfg)) &
11048 PORT_HW_CFG_NET_SERDES_IF_MASK);
11050 * Set the appropriate supported and flags indications per
11051 * interface type of the chip
11053 switch (serdes_net_if) {
11054 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11055 phy->supported &= (SUPPORTED_10baseT_Half |
11056 SUPPORTED_10baseT_Full |
11057 SUPPORTED_100baseT_Half |
11058 SUPPORTED_100baseT_Full |
11059 SUPPORTED_1000baseT_Full |
11061 SUPPORTED_Autoneg |
11063 SUPPORTED_Asym_Pause);
11064 phy->media_type = ETH_PHY_BASE_T;
11066 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11067 phy->media_type = ETH_PHY_XFP_FIBER;
11069 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11070 phy->supported &= (SUPPORTED_1000baseT_Full |
11071 SUPPORTED_10000baseT_Full |
11074 SUPPORTED_Asym_Pause);
11075 phy->media_type = ETH_PHY_SFP_FIBER;
11077 case PORT_HW_CFG_NET_SERDES_IF_KR:
11078 phy->media_type = ETH_PHY_KR;
11079 phy->supported &= (SUPPORTED_1000baseT_Full |
11080 SUPPORTED_10000baseT_Full |
11082 SUPPORTED_Autoneg |
11084 SUPPORTED_Asym_Pause);
11086 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11087 phy->media_type = ETH_PHY_KR;
11088 phy->flags |= FLAGS_WC_DUAL_MODE;
11089 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11092 SUPPORTED_Asym_Pause);
11094 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11095 phy->media_type = ETH_PHY_KR;
11096 phy->flags |= FLAGS_WC_DUAL_MODE;
11097 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11100 SUPPORTED_Asym_Pause);
11103 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11109 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11110 * was not set as expected. For B0, ECO will be enabled so there
11111 * won't be an issue there
11113 if (CHIP_REV(bp) == CHIP_REV_Ax)
11114 phy->flags |= FLAGS_MDC_MDIO_WA;
11116 switch (switch_cfg) {
11117 case SWITCH_CFG_1G:
11118 phy_addr = REG_RD(bp,
11119 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11123 case SWITCH_CFG_10G:
11124 phy_addr = REG_RD(bp,
11125 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11130 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11134 phy->addr = (u8)phy_addr;
11135 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11136 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11138 if (CHIP_IS_E2(bp))
11139 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11141 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11143 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11144 port, phy->addr, phy->mdio_ctrl);
11146 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11150 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11155 struct bnx2x_phy *phy)
11157 u32 ext_phy_config, phy_type, config2;
11158 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11159 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11161 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11162 /* Select the phy type */
11163 switch (phy_type) {
11164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11165 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11168 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11175 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11178 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11179 /* BCM8727_NOC => BCM8727 no over current */
11180 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11182 phy->flags |= FLAGS_NOC;
11184 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11185 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11186 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11189 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11195 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11198 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11199 *phy = phy_54618se;
11201 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11204 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11212 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11213 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11216 * The shmem address of the phy version is located on different
11217 * structures. In case this structure is too old, do not set
11220 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11221 dev_info.shared_hw_config.config2));
11222 if (phy_index == EXT_PHY1) {
11223 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11224 port_mb[port].ext_phy_fw_version);
11226 /* Check specific mdc mdio settings */
11227 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11228 mdc_mdio_access = config2 &
11229 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11231 u32 size = REG_RD(bp, shmem2_base);
11234 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11235 phy->ver_addr = shmem2_base +
11236 offsetof(struct shmem2_region,
11237 ext_phy_fw_version2[port]);
11239 /* Check specific mdc mdio settings */
11240 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11241 mdc_mdio_access = (config2 &
11242 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11243 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11244 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11246 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11249 * In case mdc/mdio_access of the external phy is different than the
11250 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11251 * to prevent one port interfere with another port's CL45 operations.
11253 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11254 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11255 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11256 phy_type, port, phy_index);
11257 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11258 phy->addr, phy->mdio_ctrl);
11262 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11263 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11266 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11267 if (phy_index == INT_PHY)
11268 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11269 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11274 static void bnx2x_phy_def_cfg(struct link_params *params,
11275 struct bnx2x_phy *phy,
11278 struct bnx2x *bp = params->bp;
11280 /* Populate the default phy configuration for MF mode */
11281 if (phy_index == EXT_PHY2) {
11282 link_config = REG_RD(bp, params->shmem_base +
11283 offsetof(struct shmem_region, dev_info.
11284 port_feature_config[params->port].link_config2));
11285 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11286 offsetof(struct shmem_region,
11288 port_hw_config[params->port].speed_capability_mask2));
11290 link_config = REG_RD(bp, params->shmem_base +
11291 offsetof(struct shmem_region, dev_info.
11292 port_feature_config[params->port].link_config));
11293 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11294 offsetof(struct shmem_region,
11296 port_hw_config[params->port].speed_capability_mask));
11298 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11299 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11301 phy->req_duplex = DUPLEX_FULL;
11302 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11303 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11304 phy->req_duplex = DUPLEX_HALF;
11305 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11306 phy->req_line_speed = SPEED_10;
11308 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11309 phy->req_duplex = DUPLEX_HALF;
11310 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11311 phy->req_line_speed = SPEED_100;
11313 case PORT_FEATURE_LINK_SPEED_1G:
11314 phy->req_line_speed = SPEED_1000;
11316 case PORT_FEATURE_LINK_SPEED_2_5G:
11317 phy->req_line_speed = SPEED_2500;
11319 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11320 phy->req_line_speed = SPEED_10000;
11323 phy->req_line_speed = SPEED_AUTO_NEG;
11327 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11328 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11329 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11331 case PORT_FEATURE_FLOW_CONTROL_TX:
11332 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11334 case PORT_FEATURE_FLOW_CONTROL_RX:
11335 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11337 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11338 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11341 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11346 u32 bnx2x_phy_selection(struct link_params *params)
11348 u32 phy_config_swapped, prio_cfg;
11349 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11351 phy_config_swapped = params->multi_phy_config &
11352 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11354 prio_cfg = params->multi_phy_config &
11355 PORT_HW_CFG_PHY_SELECTION_MASK;
11357 if (phy_config_swapped) {
11358 switch (prio_cfg) {
11359 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11360 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11362 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11363 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11365 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11366 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11368 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11369 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11373 return_cfg = prio_cfg;
11379 int bnx2x_phy_probe(struct link_params *params)
11381 u8 phy_index, actual_phy_idx, link_cfg_idx;
11382 u32 phy_config_swapped, sync_offset, media_types;
11383 struct bnx2x *bp = params->bp;
11384 struct bnx2x_phy *phy;
11385 params->num_phys = 0;
11386 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11387 phy_config_swapped = params->multi_phy_config &
11388 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11390 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11392 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11393 actual_phy_idx = phy_index;
11394 if (phy_config_swapped) {
11395 if (phy_index == EXT_PHY1)
11396 actual_phy_idx = EXT_PHY2;
11397 else if (phy_index == EXT_PHY2)
11398 actual_phy_idx = EXT_PHY1;
11400 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11401 " actual_phy_idx %x\n", phy_config_swapped,
11402 phy_index, actual_phy_idx);
11403 phy = ¶ms->phy[actual_phy_idx];
11404 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11405 params->shmem2_base, params->port,
11407 params->num_phys = 0;
11408 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11410 for (phy_index = INT_PHY;
11411 phy_index < MAX_PHYS;
11416 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11419 sync_offset = params->shmem_base +
11420 offsetof(struct shmem_region,
11421 dev_info.port_hw_config[params->port].media_type);
11422 media_types = REG_RD(bp, sync_offset);
11425 * Update media type for non-PMF sync only for the first time
11426 * In case the media type changes afterwards, it will be updated
11427 * using the update_status function
11429 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11430 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11431 actual_phy_idx))) == 0) {
11432 media_types |= ((phy->media_type &
11433 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11434 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11437 REG_WR(bp, sync_offset, media_types);
11439 bnx2x_phy_def_cfg(params, phy, phy_index);
11440 params->num_phys++;
11443 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11447 void bnx2x_init_bmac_loopback(struct link_params *params,
11448 struct link_vars *vars)
11450 struct bnx2x *bp = params->bp;
11452 vars->line_speed = SPEED_10000;
11453 vars->duplex = DUPLEX_FULL;
11454 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11455 vars->mac_type = MAC_TYPE_BMAC;
11457 vars->phy_flags = PHY_XGXS_FLAG;
11459 bnx2x_xgxs_deassert(params);
11461 /* set bmac loopback */
11462 bnx2x_bmac_enable(params, vars, 1);
11464 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11467 void bnx2x_init_emac_loopback(struct link_params *params,
11468 struct link_vars *vars)
11470 struct bnx2x *bp = params->bp;
11472 vars->line_speed = SPEED_1000;
11473 vars->duplex = DUPLEX_FULL;
11474 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11475 vars->mac_type = MAC_TYPE_EMAC;
11477 vars->phy_flags = PHY_XGXS_FLAG;
11479 bnx2x_xgxs_deassert(params);
11480 /* set bmac loopback */
11481 bnx2x_emac_enable(params, vars, 1);
11482 bnx2x_emac_program(params, vars);
11483 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11486 void bnx2x_init_xmac_loopback(struct link_params *params,
11487 struct link_vars *vars)
11489 struct bnx2x *bp = params->bp;
11491 if (!params->req_line_speed[0])
11492 vars->line_speed = SPEED_10000;
11494 vars->line_speed = params->req_line_speed[0];
11495 vars->duplex = DUPLEX_FULL;
11496 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11497 vars->mac_type = MAC_TYPE_XMAC;
11498 vars->phy_flags = PHY_XGXS_FLAG;
11500 * Set WC to loopback mode since link is required to provide clock
11501 * to the XMAC in 20G mode
11503 if (vars->line_speed == SPEED_20000) {
11504 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
11505 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
11506 params->phy[INT_PHY].config_loopback(
11507 ¶ms->phy[INT_PHY],
11510 bnx2x_xmac_enable(params, vars, 1);
11511 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11514 void bnx2x_init_umac_loopback(struct link_params *params,
11515 struct link_vars *vars)
11517 struct bnx2x *bp = params->bp;
11519 vars->line_speed = SPEED_1000;
11520 vars->duplex = DUPLEX_FULL;
11521 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11522 vars->mac_type = MAC_TYPE_UMAC;
11523 vars->phy_flags = PHY_XGXS_FLAG;
11524 bnx2x_umac_enable(params, vars, 1);
11526 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11529 void bnx2x_init_xgxs_loopback(struct link_params *params,
11530 struct link_vars *vars)
11532 struct bnx2x *bp = params->bp;
11534 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11535 vars->duplex = DUPLEX_FULL;
11536 if (params->req_line_speed[0] == SPEED_1000)
11537 vars->line_speed = SPEED_1000;
11539 vars->line_speed = SPEED_10000;
11541 if (!USES_WARPCORE(bp))
11542 bnx2x_xgxs_deassert(params);
11543 bnx2x_link_initialize(params, vars);
11545 if (params->req_line_speed[0] == SPEED_1000) {
11546 if (USES_WARPCORE(bp))
11547 bnx2x_umac_enable(params, vars, 0);
11549 bnx2x_emac_program(params, vars);
11550 bnx2x_emac_enable(params, vars, 0);
11553 if (USES_WARPCORE(bp))
11554 bnx2x_xmac_enable(params, vars, 0);
11556 bnx2x_bmac_enable(params, vars, 0);
11559 if (params->loopback_mode == LOOPBACK_XGXS) {
11560 /* set 10G XGXS loopback */
11561 params->phy[INT_PHY].config_loopback(
11562 ¶ms->phy[INT_PHY],
11566 /* set external phy loopback */
11568 for (phy_index = EXT_PHY1;
11569 phy_index < params->num_phys; phy_index++) {
11570 if (params->phy[phy_index].config_loopback)
11571 params->phy[phy_index].config_loopback(
11572 ¶ms->phy[phy_index],
11576 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11578 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11581 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11583 struct bnx2x *bp = params->bp;
11584 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11585 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11586 params->req_line_speed[0], params->req_flow_ctrl[0]);
11587 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11588 params->req_line_speed[1], params->req_flow_ctrl[1]);
11589 vars->link_status = 0;
11590 vars->phy_link_up = 0;
11592 vars->line_speed = 0;
11593 vars->duplex = DUPLEX_FULL;
11594 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11595 vars->mac_type = MAC_TYPE_NONE;
11596 vars->phy_flags = 0;
11598 /* disable attentions */
11599 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11600 (NIG_MASK_XGXS0_LINK_STATUS |
11601 NIG_MASK_XGXS0_LINK10G |
11602 NIG_MASK_SERDES0_LINK_STATUS |
11605 bnx2x_emac_init(params, vars);
11607 if (params->num_phys == 0) {
11608 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11611 set_phy_vars(params, vars);
11613 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11614 switch (params->loopback_mode) {
11615 case LOOPBACK_BMAC:
11616 bnx2x_init_bmac_loopback(params, vars);
11618 case LOOPBACK_EMAC:
11619 bnx2x_init_emac_loopback(params, vars);
11621 case LOOPBACK_XMAC:
11622 bnx2x_init_xmac_loopback(params, vars);
11624 case LOOPBACK_UMAC:
11625 bnx2x_init_umac_loopback(params, vars);
11627 case LOOPBACK_XGXS:
11628 case LOOPBACK_EXT_PHY:
11629 bnx2x_init_xgxs_loopback(params, vars);
11632 if (!CHIP_IS_E3(bp)) {
11633 if (params->switch_cfg == SWITCH_CFG_10G)
11634 bnx2x_xgxs_deassert(params);
11636 bnx2x_serdes_deassert(bp, params->port);
11638 bnx2x_link_initialize(params, vars);
11640 bnx2x_link_int_enable(params);
11646 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11649 struct bnx2x *bp = params->bp;
11650 u8 phy_index, port = params->port, clear_latch_ind = 0;
11651 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11652 /* disable attentions */
11653 vars->link_status = 0;
11654 bnx2x_update_mng(params, vars->link_status);
11655 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11656 (NIG_MASK_XGXS0_LINK_STATUS |
11657 NIG_MASK_XGXS0_LINK10G |
11658 NIG_MASK_SERDES0_LINK_STATUS |
11661 /* activate nig drain */
11662 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11664 /* disable nig egress interface */
11665 if (!CHIP_IS_E3(bp)) {
11666 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11667 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11670 /* Stop BigMac rx */
11671 if (!CHIP_IS_E3(bp))
11672 bnx2x_bmac_rx_disable(bp, port);
11674 bnx2x_xmac_disable(params);
11676 if (!CHIP_IS_E3(bp))
11677 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11680 /* The PHY reset is controlled by GPIO 1
11681 * Hold it as vars low
11683 /* clear link led */
11684 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11686 if (reset_ext_phy) {
11687 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11689 if (params->phy[phy_index].link_reset)
11690 params->phy[phy_index].link_reset(
11691 ¶ms->phy[phy_index],
11693 if (params->phy[phy_index].flags &
11694 FLAGS_REARM_LATCH_SIGNAL)
11695 clear_latch_ind = 1;
11699 if (clear_latch_ind) {
11700 /* Clear latching indication */
11701 bnx2x_rearm_latch_signal(bp, port, 0);
11702 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11703 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11705 if (params->phy[INT_PHY].link_reset)
11706 params->phy[INT_PHY].link_reset(
11707 ¶ms->phy[INT_PHY], params);
11709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11710 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11712 /* disable nig ingress interface */
11713 if (!CHIP_IS_E3(bp)) {
11714 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11715 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11718 vars->phy_flags = 0;
11722 /****************************************************************************/
11723 /* Common function */
11724 /****************************************************************************/
11725 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11726 u32 shmem_base_path[],
11727 u32 shmem2_base_path[], u8 phy_index,
11730 struct bnx2x_phy phy[PORT_MAX];
11731 struct bnx2x_phy *phy_blk[PORT_MAX];
11734 s8 port_of_path = 0;
11735 u32 swap_val, swap_override;
11736 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11737 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11738 port ^= (swap_val && swap_override);
11739 bnx2x_ext_phy_hw_reset(bp, port);
11740 /* PART1 - Reset both phys */
11741 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11742 u32 shmem_base, shmem2_base;
11743 /* In E2, same phy is using for port0 of the two paths */
11744 if (CHIP_IS_E1x(bp)) {
11745 shmem_base = shmem_base_path[0];
11746 shmem2_base = shmem2_base_path[0];
11747 port_of_path = port;
11749 shmem_base = shmem_base_path[port];
11750 shmem2_base = shmem2_base_path[port];
11754 /* Extract the ext phy address for the port */
11755 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11756 port_of_path, &phy[port]) !=
11758 DP(NETIF_MSG_LINK, "populate_phy failed\n");
11761 /* disable attentions */
11762 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11764 (NIG_MASK_XGXS0_LINK_STATUS |
11765 NIG_MASK_XGXS0_LINK10G |
11766 NIG_MASK_SERDES0_LINK_STATUS |
11769 /* Need to take the phy out of low power mode in order
11770 to write to access its registers */
11771 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11772 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11775 /* Reset the phy */
11776 bnx2x_cl45_write(bp, &phy[port],
11782 /* Add delay of 150ms after reset */
11785 if (phy[PORT_0].addr & 0x1) {
11786 phy_blk[PORT_0] = &(phy[PORT_1]);
11787 phy_blk[PORT_1] = &(phy[PORT_0]);
11789 phy_blk[PORT_0] = &(phy[PORT_0]);
11790 phy_blk[PORT_1] = &(phy[PORT_1]);
11793 /* PART2 - Download firmware to both phys */
11794 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11795 if (CHIP_IS_E1x(bp))
11796 port_of_path = port;
11800 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11801 phy_blk[port]->addr);
11802 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11806 /* Only set bit 10 = 1 (Tx power down) */
11807 bnx2x_cl45_read(bp, phy_blk[port],
11809 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11811 /* Phase1 of TX_POWER_DOWN reset */
11812 bnx2x_cl45_write(bp, phy_blk[port],
11814 MDIO_PMA_REG_TX_POWER_DOWN,
11819 * Toggle Transmitter: Power down and then up with 600ms delay
11824 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11825 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11826 /* Phase2 of POWER_DOWN_RESET */
11827 /* Release bit 10 (Release Tx power down) */
11828 bnx2x_cl45_read(bp, phy_blk[port],
11830 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11832 bnx2x_cl45_write(bp, phy_blk[port],
11834 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11837 /* Read modify write the SPI-ROM version select register */
11838 bnx2x_cl45_read(bp, phy_blk[port],
11840 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11841 bnx2x_cl45_write(bp, phy_blk[port],
11843 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11845 /* set GPIO2 back to LOW */
11846 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11847 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11851 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11852 u32 shmem_base_path[],
11853 u32 shmem2_base_path[], u8 phy_index,
11858 struct bnx2x_phy phy;
11859 /* Use port1 because of the static port-swap */
11860 /* Enable the module detection interrupt */
11861 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11862 val |= ((1<<MISC_REGISTERS_GPIO_3)|
11863 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11864 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11866 bnx2x_ext_phy_hw_reset(bp, 0);
11868 for (port = 0; port < PORT_MAX; port++) {
11869 u32 shmem_base, shmem2_base;
11871 /* In E2, same phy is using for port0 of the two paths */
11872 if (CHIP_IS_E1x(bp)) {
11873 shmem_base = shmem_base_path[0];
11874 shmem2_base = shmem2_base_path[0];
11876 shmem_base = shmem_base_path[port];
11877 shmem2_base = shmem2_base_path[port];
11879 /* Extract the ext phy address for the port */
11880 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11883 DP(NETIF_MSG_LINK, "populate phy failed\n");
11888 bnx2x_cl45_write(bp, &phy,
11889 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11892 /* Set fault module detected LED on */
11893 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11894 MISC_REGISTERS_GPIO_HIGH,
11900 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11901 u8 *io_gpio, u8 *io_port)
11904 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11905 offsetof(struct shmem_region,
11906 dev_info.port_hw_config[PORT_0].default_cfg));
11907 switch (phy_gpio_reset) {
11908 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11912 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11916 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11920 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11924 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11928 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11932 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11936 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11941 /* Don't override the io_gpio and io_port */
11946 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11947 u32 shmem_base_path[],
11948 u32 shmem2_base_path[], u8 phy_index,
11951 s8 port, reset_gpio;
11952 u32 swap_val, swap_override;
11953 struct bnx2x_phy phy[PORT_MAX];
11954 struct bnx2x_phy *phy_blk[PORT_MAX];
11956 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11957 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11959 reset_gpio = MISC_REGISTERS_GPIO_1;
11963 * Retrieve the reset gpio/port which control the reset.
11964 * Default is GPIO1, PORT1
11966 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11967 (u8 *)&reset_gpio, (u8 *)&port);
11969 /* Calculate the port based on port swap */
11970 port ^= (swap_val && swap_override);
11972 /* Initiate PHY reset*/
11973 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11976 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11981 /* PART1 - Reset both phys */
11982 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11983 u32 shmem_base, shmem2_base;
11985 /* In E2, same phy is using for port0 of the two paths */
11986 if (CHIP_IS_E1x(bp)) {
11987 shmem_base = shmem_base_path[0];
11988 shmem2_base = shmem2_base_path[0];
11989 port_of_path = port;
11991 shmem_base = shmem_base_path[port];
11992 shmem2_base = shmem2_base_path[port];
11996 /* Extract the ext phy address for the port */
11997 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11998 port_of_path, &phy[port]) !=
12000 DP(NETIF_MSG_LINK, "populate phy failed\n");
12003 /* disable attentions */
12004 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12006 (NIG_MASK_XGXS0_LINK_STATUS |
12007 NIG_MASK_XGXS0_LINK10G |
12008 NIG_MASK_SERDES0_LINK_STATUS |
12012 /* Reset the phy */
12013 bnx2x_cl45_write(bp, &phy[port],
12014 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12017 /* Add delay of 150ms after reset */
12019 if (phy[PORT_0].addr & 0x1) {
12020 phy_blk[PORT_0] = &(phy[PORT_1]);
12021 phy_blk[PORT_1] = &(phy[PORT_0]);
12023 phy_blk[PORT_0] = &(phy[PORT_0]);
12024 phy_blk[PORT_1] = &(phy[PORT_1]);
12026 /* PART2 - Download firmware to both phys */
12027 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12028 if (CHIP_IS_E1x(bp))
12029 port_of_path = port;
12032 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12033 phy_blk[port]->addr);
12034 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12037 /* Disable PHY transmitter output */
12038 bnx2x_cl45_write(bp, phy_blk[port],
12040 MDIO_PMA_REG_TX_DISABLE, 1);
12046 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12047 u32 shmem2_base_path[], u8 phy_index,
12048 u32 ext_phy_type, u32 chip_id)
12052 switch (ext_phy_type) {
12053 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12054 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12056 phy_index, chip_id);
12058 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12059 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12060 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12061 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12063 phy_index, chip_id);
12066 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12068 * GPIO1 affects both ports, so there's need to pull
12069 * it for single port alone
12071 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12073 phy_index, chip_id);
12075 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12077 * GPIO3's are linked, and so both need to be toggled
12078 * to obtain required 2us pulse.
12080 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12082 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12087 "ext_phy 0x%x common init not required\n",
12093 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12099 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12100 u32 shmem2_base_path[], u32 chip_id)
12105 u32 ext_phy_type, ext_phy_config;
12106 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12107 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12108 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12109 if (CHIP_IS_E3(bp)) {
12111 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12112 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12114 /* Check if common init was already done */
12115 phy_ver = REG_RD(bp, shmem_base_path[0] +
12116 offsetof(struct shmem_region,
12117 port_mb[PORT_0].ext_phy_fw_version));
12119 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12124 /* Read the ext_phy_type for arbitrary port(0) */
12125 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12127 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12128 shmem_base_path[0],
12130 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12131 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12133 phy_index, ext_phy_type,
12139 static void bnx2x_check_over_curr(struct link_params *params,
12140 struct link_vars *vars)
12142 struct bnx2x *bp = params->bp;
12144 u8 port = params->port;
12147 cfg_pin = (REG_RD(bp, params->shmem_base +
12148 offsetof(struct shmem_region,
12149 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12150 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12151 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12153 /* Ignore check if no external input PIN available */
12154 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12158 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12159 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12160 " been detected and the power to "
12161 "that SFP+ module has been removed"
12162 " to prevent failure of the card."
12163 " Please remove the SFP+ module and"
12164 " restart the system to clear this"
12167 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12170 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12173 static void bnx2x_analyze_link_error(struct link_params *params,
12174 struct link_vars *vars, u32 lss_status)
12176 struct bnx2x *bp = params->bp;
12177 /* Compare new value with previous value */
12179 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12181 /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
12183 half_open_conn, lss_status);*/
12185 if ((lss_status ^ half_open_conn) == 0)
12188 /* If values differ */
12189 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12190 half_open_conn, lss_status);
12193 * a. Update shmem->link_status accordingly
12194 * b. Update link_vars->link_up
12197 vars->link_status &= ~LINK_STATUS_LINK_UP;
12199 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12201 * Set LED mode to off since the PHY doesn't know about these
12204 led_mode = LED_MODE_OFF;
12206 vars->link_status |= LINK_STATUS_LINK_UP;
12208 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12209 led_mode = LED_MODE_OPER;
12211 /* Update the LED according to the link state */
12212 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12214 /* Update link status in the shared memory */
12215 bnx2x_update_mng(params, vars->link_status);
12217 /* C. Trigger General Attention */
12218 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12219 bnx2x_notify_link_changed(bp);
12222 static void bnx2x_check_half_open_conn(struct link_params *params,
12223 struct link_vars *vars)
12225 struct bnx2x *bp = params->bp;
12226 u32 lss_status = 0;
12228 /* In case link status is physically up @ 10G do */
12229 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12232 if (!CHIP_IS_E3(bp) &&
12233 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12234 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12235 /* Check E1X / E2 BMAC */
12236 u32 lss_status_reg;
12238 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12239 NIG_REG_INGRESS_BMAC0_MEM;
12240 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12241 if (CHIP_IS_E2(bp))
12242 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12244 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12246 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12247 lss_status = (wb_data[0] > 0);
12249 bnx2x_analyze_link_error(params, vars, lss_status);
12253 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12255 struct bnx2x *bp = params->bp;
12257 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12260 /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12261 RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12262 REG_RD(bp, MISC_REG_RESET_REG_2)); */
12263 bnx2x_check_half_open_conn(params, vars);
12264 if (CHIP_IS_E3(bp))
12265 bnx2x_check_over_curr(params, vars);
12268 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12271 struct bnx2x_phy phy;
12272 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12274 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12276 DP(NETIF_MSG_LINK, "populate phy failed\n");
12280 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12286 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12291 u8 phy_index, fan_failure_det_req = 0;
12292 struct bnx2x_phy phy;
12293 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12295 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12298 DP(NETIF_MSG_LINK, "populate phy failed\n");
12301 fan_failure_det_req |= (phy.flags &
12302 FLAGS_FAN_FAILURE_DET_REQ);
12304 return fan_failure_det_req;
12307 void bnx2x_hw_reset_phy(struct link_params *params)
12310 struct bnx2x *bp = params->bp;
12311 bnx2x_update_mng(params, 0);
12312 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12313 (NIG_MASK_XGXS0_LINK_STATUS |
12314 NIG_MASK_XGXS0_LINK10G |
12315 NIG_MASK_SERDES0_LINK_STATUS |
12318 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12320 if (params->phy[phy_index].hw_reset) {
12321 params->phy[phy_index].hw_reset(
12322 ¶ms->phy[phy_index],
12324 params->phy[phy_index] = phy_null;
12329 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12330 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12333 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12335 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12336 if (CHIP_IS_E3(bp)) {
12337 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12344 struct bnx2x_phy phy;
12345 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12347 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12348 shmem2_base, port, &phy)
12350 DP(NETIF_MSG_LINK, "populate phy failed\n");
12353 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12354 gpio_num = MISC_REGISTERS_GPIO_3;
12361 if (gpio_num == 0xff)
12364 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12365 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12367 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12368 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12369 gpio_port ^= (swap_val && swap_override);
12371 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12372 (gpio_num + (gpio_port << 2));
12374 sync_offset = shmem_base +
12375 offsetof(struct shmem_region,
12376 dev_info.port_hw_config[port].aeu_int_mask);
12377 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12379 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12380 gpio_num, gpio_port, vars->aeu_int_mask);
12383 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12385 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12387 /* Open appropriate AEU for interrupts */
12388 aeu_mask = REG_RD(bp, offset);
12389 aeu_mask |= vars->aeu_int_mask;
12390 REG_WR(bp, offset, aeu_mask);
12392 /* Enable the GPIO to trigger interrupt */
12393 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12394 val |= 1 << (gpio_num + (gpio_port << 2));
12395 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);