1 /* Copyright 2008-2011 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
22 /***********************************************************/
24 /***********************************************************/
25 #define DEFAULT_PHY_DEV_ADDR 3
26 #define E2_DEFAULT_PHY_DEV_ADDR 5
30 #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31 #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32 #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33 #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34 #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
36 #define SPEED_AUTO_NEG 0
37 #define SPEED_12000 12000
38 #define SPEED_12500 12500
39 #define SPEED_13000 13000
40 #define SPEED_15000 15000
41 #define SPEED_16000 16000
43 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
44 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
45 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
46 #define SFP_EEPROM_VENDOR_OUI_SIZE 3
47 #define SFP_EEPROM_PART_NO_ADDR 0x28
48 #define SFP_EEPROM_PART_NO_SIZE 16
49 #define PWR_FLT_ERR_MSG_LEN 250
51 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
52 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
53 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
54 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
55 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
56 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
57 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
59 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
60 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
61 /* Single Media board contains single external phy */
62 #define SINGLE_MEDIA(params) (params->num_phys == 2)
63 /* Dual Media board contains two external phy with different media */
64 #define DUAL_MEDIA(params) (params->num_phys == 3)
65 #define FW_PARAM_MDIO_CTRL_OFFSET 16
66 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
67 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
70 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
71 #define PFC_BRB_FULL_LB_XON_THRESHOLD 250
73 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
74 /***********************************************************/
76 /***********************************************************/
82 /* Same configuration is shared between the XGXS and the first external phy */
83 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
84 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
86 /***********************************************************/
87 /* bnx2x_phy struct */
88 /* Defines the required arguments and function per phy */
89 /***********************************************************/
94 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
95 struct link_vars *vars);
96 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
97 struct link_vars *vars);
98 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
99 struct link_params *params);
100 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
101 struct link_params *params);
102 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
103 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
104 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
105 struct link_params *params, u8 mode);
106 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
107 struct link_params *params, u32 action);
112 /* Loaded during init */
116 /* Require HW lock */
117 #define FLAGS_HW_LOCK_REQUIRED (1<<0)
118 /* No Over-Current detection */
119 #define FLAGS_NOC (1<<1)
120 /* Fan failure detection required */
121 #define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
122 /* Initialize first the XGXS and only then the phy itself */
123 #define FLAGS_INIT_XGXS_FIRST (1<<3)
124 #define FLAGS_4_PORT_MODE (1<<5)
125 #define FLAGS_REARM_LATCH_SIGNAL (1<<6)
126 #define FLAGS_SFP_NOT_APPROVED (1<<7)
128 /* preemphasis values for the rx side */
129 u16 rx_preemphasis[4];
131 /* preemphasis values for the tx side */
132 u16 tx_preemphasis[4];
134 /* EMAC address for access MDIO */
140 #define ETH_PHY_UNSPECIFIED 0x0
141 #define ETH_PHY_SFP_FIBER 0x1
142 #define ETH_PHY_XFP_FIBER 0x2
143 #define ETH_PHY_DA_TWINAX 0x3
144 #define ETH_PHY_BASE_T 0x4
145 #define ETH_PHY_KR 0xf0
146 #define ETH_PHY_CX4 0xf1
147 #define ETH_PHY_NOT_PRESENT 0xff
149 /* The address in which version is located*/
160 /* Called per phy/port init, and it configures LASI, speed, autoneg,
161 duplex, flow control negotiation, etc. */
162 config_init_t config_init;
164 /* Called due to interrupt. It determines the link, speed */
165 read_status_t read_status;
167 /* Called when driver is unloading. Should reset the phy */
168 link_reset_t link_reset;
170 /* Set the loopback configuration for the phy */
171 config_loopback_t config_loopback;
173 /* Format the given raw number into str up to len */
174 format_fw_ver_t format_fw_ver;
176 /* Reset the phy (both ports) */
179 /* Set link led mode (on/off/oper)*/
180 set_link_led_t set_link_led;
182 /* PHY Specific tasks */
183 phy_specific_func_t phy_specific_func;
188 /* Inputs parameters to the CLC */
193 /* Default / User Configuration */
195 #define LOOPBACK_NONE 0
196 #define LOOPBACK_EMAC 1
197 #define LOOPBACK_BMAC 2
198 #define LOOPBACK_XGXS 3
199 #define LOOPBACK_EXT_PHY 4
200 #define LOOPBACK_EXT 5
201 #define LOOPBACK_UMAC 6
202 #define LOOPBACK_XMAC 7
204 /* Device parameters */
207 u16 req_duplex[LINK_CONFIG_SIZE];
208 u16 req_flow_ctrl[LINK_CONFIG_SIZE];
210 u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
212 /* shmem parameters */
215 u32 speed_cap_mask[LINK_CONFIG_SIZE];
217 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
218 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
219 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
223 /* Phy register parameter */
227 u32 feature_config_flags;
228 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
229 #define FEATURE_CONFIG_PFC_ENABLED (1<<1)
230 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
231 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
232 /* Will be populated during common init */
233 struct bnx2x_phy phy[MAX_PHYS];
235 /* Will be populated during common init */
239 u16 hw_led_mode; /* part of the hw_config read from the shmem */
240 u32 multi_phy_config;
242 /* Device pointer passed to all callback functions */
244 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
245 req_flow_ctrl is set to AUTO */
248 /* Output parameters */
253 #define MAC_TYPE_NONE 0
254 #define MAC_TYPE_EMAC 1
255 #define MAC_TYPE_BMAC 2
256 #define MAC_TYPE_UMAC 3
257 #define MAC_TYPE_XMAC 4
259 u8 phy_link_up; /* internal phy link indication */
268 /* The same definitions as the shmem parameter */
276 /***********************************************************/
278 /***********************************************************/
279 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
281 /* Reset the link. Should be called when driver or interface goes down
282 Before calling phy firmware upgrade, the reset_ext_phy should be set
284 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
287 /* bnx2x_link_update should be called upon link interrupt */
288 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
290 /* use the following phy functions to read/write from external_phy
291 In order to use it to read/write internal phy registers, use
292 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
294 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
295 u8 devad, u16 reg, u16 *ret_val);
297 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
298 u8 devad, u16 reg, u16 val);
300 /* Reads the link_status from the shmem,
301 and update the link vars accordingly */
302 void bnx2x_link_status_update(struct link_params *input,
303 struct link_vars *output);
304 /* returns string representing the fw_version of the external phy */
305 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
306 u8 *version, u16 len);
309 Basically, the CLC takes care of the led for the link, but in case one needs
310 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
311 blink the led, and LED_MODE_OFF to set the led off.*/
312 int bnx2x_set_led(struct link_params *params,
313 struct link_vars *vars, u8 mode, u32 speed);
314 #define LED_MODE_OFF 0
315 #define LED_MODE_ON 1
316 #define LED_MODE_OPER 2
317 #define LED_MODE_FRONT_PANEL_OFF 3
319 /* bnx2x_handle_module_detect_int should be called upon module detection
321 void bnx2x_handle_module_detect_int(struct link_params *params);
323 /* Get the actual link status. In case it returns 0, link is up,
324 otherwise link is down*/
325 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
328 /* One-time initialization for external phy after power up */
329 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
330 u32 shmem2_base_path[], u32 chip_id);
332 /* Reset the external PHY using GPIO */
333 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
335 /* Reset the external of SFX7101 */
336 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
338 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
339 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
340 struct link_params *params, u16 addr,
341 u8 byte_cnt, u8 *o_buf);
343 void bnx2x_hw_reset_phy(struct link_params *params);
345 /* Checks if HW lock is required for this phy/board type */
346 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
349 /* Check swap bit and adjust PHY order */
350 u32 bnx2x_phy_selection(struct link_params *params);
352 /* Probe the phys on board, and populate them in "params" */
353 int bnx2x_phy_probe(struct link_params *params);
355 /* Checks if fan failure detection is required on one of the phys on board */
356 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
357 u32 shmem2_base, u8 port);
363 /* Number of maximum COS per chip */
364 #define DCBX_E2E3_MAX_NUM_COS (2)
365 #define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
366 #define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
367 #define DCBX_E3B0_MAX_NUM_COS ( \
368 MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
369 DCBX_E3B0_MAX_NUM_COS_PORT1))
371 #define DCBX_MAX_NUM_COS ( \
372 MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
373 DCBX_E2E3_MAX_NUM_COS))
375 /* PFC port configuration params */
376 struct bnx2x_nig_brb_pfc_port_params {
381 u32 pkt_priority_to_cos;
382 u8 num_of_rx_cos_priority_mask;
383 u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
384 u32 llfc_high_priority_classes;
385 u32 llfc_low_priority_classes;
392 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
393 * when link is already up
395 int bnx2x_update_pfc(struct link_params *params,
396 struct link_vars *vars,
397 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
400 /* Used to configure the ETS to disable */
401 void bnx2x_ets_disabled(struct link_params *params);
403 /* Used to configure the ETS to BW limited */
404 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
407 /* Used to configure the ETS to strict */
408 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
410 /* Read pfc statistic*/
411 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
412 u32 pfc_frames_sent[2],
413 u32 pfc_frames_received[2]);
414 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
415 u32 chip_id, u32 shmem_base, u32 shmem2_base,
417 #endif /* BNX2X_LINK_H */