1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
52 #include <linux/stringify.h>
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
61 #include <linux/firmware.h>
62 #include "bnx2x_fw_file_hdr.h"
64 #define FW_FILE_VERSION \
65 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
66 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
67 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
68 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
69 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
73 /* Time in jiffies before concluding the transmitter is hung */
74 #define TX_TIMEOUT (5*HZ)
76 static char version[] __devinitdata =
77 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
78 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80 MODULE_AUTHOR("Eliezer Tamir");
81 MODULE_DESCRIPTION("Broadcom NetXtreme II "
82 "BCM57710/57711/57711E/"
83 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
84 "57840/57840_MF Driver");
85 MODULE_LICENSE("GPL");
86 MODULE_VERSION(DRV_MODULE_VERSION);
87 MODULE_FIRMWARE(FW_FILE_NAME_E1);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
89 MODULE_FIRMWARE(FW_FILE_NAME_E2);
91 static int multi_mode = 1;
92 module_param(multi_mode, int, 0);
93 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
94 "(0 Disable; 1 Enable (default))");
97 module_param(num_queues, int, 0);
98 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
99 " (default is as a number of CPUs)");
101 static int disable_tpa;
102 module_param(disable_tpa, int, 0);
103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105 #define INT_MODE_INTx 1
106 #define INT_MODE_MSI 2
108 module_param(int_mode, int, 0);
109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 static int dropless_fc;
113 module_param(dropless_fc, int, 0);
114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117 module_param(poll, int, 0);
118 MODULE_PARM_DESC(poll, " Use polling (for debug)");
120 static int mrrs = -1;
121 module_param(mrrs, int, 0);
122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
125 module_param(debug, int, 0);
126 MODULE_PARM_DESC(debug, " Default debug msglevel");
130 struct workqueue_struct *bnx2x_wq;
132 enum bnx2x_board_type {
146 /* indexed by board_type, above */
149 } board_info[] __devinitdata = {
150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
164 #ifndef PCI_DEVICE_ID_NX2_57710
165 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167 #ifndef PCI_DEVICE_ID_NX2_57711
168 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170 #ifndef PCI_DEVICE_ID_NX2_57711E
171 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173 #ifndef PCI_DEVICE_ID_NX2_57712
174 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176 #ifndef PCI_DEVICE_ID_NX2_57712_MF
177 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179 #ifndef PCI_DEVICE_ID_NX2_57800
180 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182 #ifndef PCI_DEVICE_ID_NX2_57800_MF
183 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185 #ifndef PCI_DEVICE_ID_NX2_57810
186 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188 #ifndef PCI_DEVICE_ID_NX2_57810_MF
189 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191 #ifndef PCI_DEVICE_ID_NX2_57840
192 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194 #ifndef PCI_DEVICE_ID_NX2_57840_MF
195 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
198 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
212 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214 /****************************************************************************
215 * General service functions
216 ****************************************************************************/
218 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
219 u32 addr, dma_addr_t mapping)
221 REG_WR(bp, addr, U64_LO(mapping));
222 REG_WR(bp, addr + 4, U64_HI(mapping));
225 static inline void storm_memset_spq_addr(struct bnx2x *bp,
226 dma_addr_t mapping, u16 abs_fid)
228 u32 addr = XSEM_REG_FAST_MEMORY +
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231 __storm_memset_dma_mapping(bp, addr, mapping);
234 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
237 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
247 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
250 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
260 static inline void storm_memset_eq_data(struct bnx2x *bp,
261 struct event_ring_data *eq_data,
264 size_t size = sizeof(struct event_ring_data);
266 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
271 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
274 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
275 REG_WR16(bp, addr, eq_prod);
279 * locking is done by mcp
281 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
283 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
286 PCICFG_VENDOR_ID_OFFSET);
289 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
293 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
294 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
295 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
296 PCICFG_VENDOR_ID_OFFSET);
301 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305 #define DMAE_DP_DST_NONE "dst_addr [none]"
307 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
310 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312 switch (dmae->opcode & DMAE_COMMAND_DST) {
313 case DMAE_CMD_DST_PCI:
314 if (src_type == DMAE_CMD_SRC_PCI)
315 DP(msglvl, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
319 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
320 dmae->comp_addr_hi, dmae->comp_addr_lo,
323 DP(msglvl, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae->opcode, dmae->src_addr_lo >> 2,
327 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
328 dmae->comp_addr_hi, dmae->comp_addr_lo,
331 case DMAE_CMD_DST_GRC:
332 if (src_type == DMAE_CMD_SRC_PCI)
333 DP(msglvl, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
337 dmae->len, dmae->dst_addr_lo >> 2,
338 dmae->comp_addr_hi, dmae->comp_addr_lo,
341 DP(msglvl, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae->opcode, dmae->src_addr_lo >> 2,
345 dmae->len, dmae->dst_addr_lo >> 2,
346 dmae->comp_addr_hi, dmae->comp_addr_lo,
350 if (src_type == DMAE_CMD_SRC_PCI)
351 DP(msglvl, "DMAE: opcode 0x%08x\n"
352 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
355 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
356 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
359 DP(msglvl, "DMAE: opcode 0x%08x\n"
360 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
363 dmae->opcode, dmae->src_addr_lo >> 2,
364 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
371 /* copy command into DMAE command memory and set DMAE command go */
372 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
377 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
378 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
379 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
382 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
384 REG_WR(bp, dmae_reg_go_c[idx], 1);
387 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
389 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
393 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395 return opcode & ~DMAE_CMD_SRC_RESET;
398 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
399 bool with_comp, u8 comp_type)
403 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
404 (dst_type << DMAE_COMMAND_DST_SHIFT));
406 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
409 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
410 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
411 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
414 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
416 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
419 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
423 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
424 struct dmae_command *dmae,
425 u8 src_type, u8 dst_type)
427 memset(dmae, 0, sizeof(struct dmae_command));
430 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
431 true, DMAE_COMP_PCI);
433 /* fill in the completion parameters */
434 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
435 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_val = DMAE_COMP_VAL;
439 /* issue a dmae command over the init-channel and wailt for completion */
440 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
441 struct dmae_command *dmae)
443 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
444 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
447 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
448 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
449 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
452 * Lock the dmae channel. Disable BHs to prevent a dead-lock
453 * as long as this code is called both from syscall context and
454 * from ndo_set_rx_mode() flow that may be called from BH.
456 spin_lock_bh(&bp->dmae_lock);
458 /* reset completion */
461 /* post the command on the channel used for initializations */
462 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
464 /* wait for completion */
466 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
467 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
470 BNX2X_ERR("DMAE timeout!\n");
477 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
478 BNX2X_ERR("DMAE PCI error!\n");
482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
487 spin_unlock_bh(&bp->dmae_lock);
491 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
494 struct dmae_command dmae;
496 if (!bp->dmae_ready) {
497 u32 *data = bnx2x_sp(bp, wb_data[0]);
499 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
500 " using indirect\n", dst_addr, len32);
501 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
505 /* set opcode and fixed command fields */
506 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508 /* fill in addresses and len */
509 dmae.src_addr_lo = U64_LO(dma_addr);
510 dmae.src_addr_hi = U64_HI(dma_addr);
511 dmae.dst_addr_lo = dst_addr >> 2;
512 dmae.dst_addr_hi = 0;
515 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517 /* issue the command and wait for completion */
518 bnx2x_issue_dmae_with_comp(bp, &dmae);
521 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
523 struct dmae_command dmae;
525 if (!bp->dmae_ready) {
526 u32 *data = bnx2x_sp(bp, wb_data[0]);
529 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
530 " using indirect\n", src_addr, len32);
531 for (i = 0; i < len32; i++)
532 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
536 /* set opcode and fixed command fields */
537 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
539 /* fill in addresses and len */
540 dmae.src_addr_lo = src_addr >> 2;
541 dmae.src_addr_hi = 0;
542 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
543 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
546 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
548 /* issue the command and wait for completion */
549 bnx2x_issue_dmae_with_comp(bp, &dmae);
552 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
555 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
558 while (len > dmae_wr_max) {
559 bnx2x_write_dmae(bp, phys_addr + offset,
560 addr + offset, dmae_wr_max);
561 offset += dmae_wr_max * 4;
565 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
568 /* used only for slowpath so not inlined */
569 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
573 wb_write[0] = val_hi;
574 wb_write[1] = val_lo;
575 REG_WR_DMAE(bp, reg, wb_write, 2);
579 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
583 REG_RD_DMAE(bp, reg, wb_data, 2);
585 return HILO_U64(wb_data[0], wb_data[1]);
589 static int bnx2x_mc_assert(struct bnx2x *bp)
593 u32 row0, row1, row2, row3;
596 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
597 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601 /* print the asserts */
602 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
605 XSTORM_ASSERT_LIST_OFFSET(i));
606 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
607 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
608 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
609 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
610 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
611 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
614 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
615 " 0x%08x 0x%08x 0x%08x\n",
616 i, row3, row2, row1, row0);
624 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
625 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629 /* print the asserts */
630 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
633 TSTORM_ASSERT_LIST_OFFSET(i));
634 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
635 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
636 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
637 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
638 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
639 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
642 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
643 " 0x%08x 0x%08x 0x%08x\n",
644 i, row3, row2, row1, row0);
652 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
653 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657 /* print the asserts */
658 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
661 CSTORM_ASSERT_LIST_OFFSET(i));
662 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
663 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
664 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
665 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
666 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
667 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
670 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
671 " 0x%08x 0x%08x 0x%08x\n",
672 i, row3, row2, row1, row0);
680 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
681 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685 /* print the asserts */
686 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
689 USTORM_ASSERT_LIST_OFFSET(i));
690 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
691 USTORM_ASSERT_LIST_OFFSET(i) + 4);
692 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
693 USTORM_ASSERT_LIST_OFFSET(i) + 8);
694 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
695 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
698 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
699 " 0x%08x 0x%08x 0x%08x\n",
700 i, row3, row2, row1, row0);
710 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
716 u32 trace_shmem_base;
718 BNX2X_ERR("NO MCP - can not dump\n");
721 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
722 (bp->common.bc_ver & 0xff0000) >> 16,
723 (bp->common.bc_ver & 0xff00) >> 8,
724 (bp->common.bc_ver & 0xff));
726 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
727 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
728 printk("%s" "MCP PC at 0x%x\n", lvl, val);
730 if (BP_PATH(bp) == 0)
731 trace_shmem_base = bp->common.shmem_base;
733 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
734 addr = trace_shmem_base - 0x0800 + 4;
735 mark = REG_RD(bp, addr);
736 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
737 + ((mark + 0x3) & ~0x3) - 0x08000000;
738 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
741 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
742 for (word = 0; word < 8; word++)
743 data[word] = htonl(REG_RD(bp, offset + 4*word));
745 pr_cont("%s", (char *)data);
747 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
748 for (word = 0; word < 8; word++)
749 data[word] = htonl(REG_RD(bp, offset + 4*word));
751 pr_cont("%s", (char *)data);
753 printk("%s" "end of fw dump\n", lvl);
756 static inline void bnx2x_fw_dump(struct bnx2x *bp)
758 bnx2x_fw_dump_lvl(bp, KERN_ERR);
761 void bnx2x_panic_dump(struct bnx2x *bp)
765 struct hc_sp_status_block_data sp_sb_data;
766 int func = BP_FUNC(bp);
767 #ifdef BNX2X_STOP_ON_ERROR
768 u16 start = 0, end = 0;
771 bp->stats_state = STATS_STATE_DISABLED;
772 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
774 BNX2X_ERR("begin crash dump -----------------\n");
778 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
779 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
780 bp->def_idx, bp->def_att_idx, bp->attn_state,
781 bp->spq_prod_idx, bp->stats_counter);
782 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
783 bp->def_status_blk->atten_status_block.attn_bits,
784 bp->def_status_blk->atten_status_block.attn_bits_ack,
785 bp->def_status_blk->atten_status_block.status_block_id,
786 bp->def_status_blk->atten_status_block.attn_bits_index);
788 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
790 bp->def_status_blk->sp_sb.index_values[i],
791 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
794 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
799 "pf_id(0x%x) vnic_id(0x%x) "
800 "vf_id(0x%x) vf_valid (0x%x) "
802 sp_sb_data.igu_sb_id,
803 sp_sb_data.igu_seg_id,
804 sp_sb_data.p_func.pf_id,
805 sp_sb_data.p_func.vnic_id,
806 sp_sb_data.p_func.vf_id,
807 sp_sb_data.p_func.vf_valid,
811 for_each_eth_queue(bp, i) {
812 struct bnx2x_fastpath *fp = &bp->fp[i];
814 struct hc_status_block_data_e2 sb_data_e2;
815 struct hc_status_block_data_e1x sb_data_e1x;
816 struct hc_status_block_sm *hc_sm_p =
818 sb_data_e1x.common.state_machine :
819 sb_data_e2.common.state_machine;
820 struct hc_index_data *hc_index_p =
822 sb_data_e1x.index_data :
823 sb_data_e2.index_data;
828 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
829 " rx_comp_prod(0x%x)"
830 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
831 i, fp->rx_bd_prod, fp->rx_bd_cons,
833 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
834 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
835 " fp_hc_idx(0x%x)\n",
836 fp->rx_sge_prod, fp->last_max_sge,
837 le16_to_cpu(fp->fp_hc_idx));
840 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
841 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
842 " *tx_cons_sb(0x%x)\n",
843 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
844 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
846 loop = CHIP_IS_E1x(bp) ?
847 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
855 BNX2X_ERR(" run indexes (");
856 for (j = 0; j < HC_SB_MAX_SM; j++)
858 fp->sb_running_index[j],
859 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
861 BNX2X_ERR(" indexes (");
862 for (j = 0; j < loop; j++)
864 fp->sb_index_values[j],
865 (j == loop - 1) ? ")" : " ");
867 data_size = CHIP_IS_E1x(bp) ?
868 sizeof(struct hc_status_block_data_e1x) :
869 sizeof(struct hc_status_block_data_e2);
870 data_size /= sizeof(u32);
871 sb_data_p = CHIP_IS_E1x(bp) ?
872 (u32 *)&sb_data_e1x :
874 /* copy sb data in here */
875 for (j = 0; j < data_size; j++)
876 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
877 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
880 if (!CHIP_IS_E1x(bp)) {
881 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
882 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
884 sb_data_e2.common.p_func.pf_id,
885 sb_data_e2.common.p_func.vf_id,
886 sb_data_e2.common.p_func.vf_valid,
887 sb_data_e2.common.p_func.vnic_id,
888 sb_data_e2.common.same_igu_sb_1b,
889 sb_data_e2.common.state);
891 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
892 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
894 sb_data_e1x.common.p_func.pf_id,
895 sb_data_e1x.common.p_func.vf_id,
896 sb_data_e1x.common.p_func.vf_valid,
897 sb_data_e1x.common.p_func.vnic_id,
898 sb_data_e1x.common.same_igu_sb_1b,
899 sb_data_e1x.common.state);
903 for (j = 0; j < HC_SB_MAX_SM; j++) {
904 pr_cont("SM[%d] __flags (0x%x) "
905 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
906 "time_to_expire (0x%x) "
907 "timer_value(0x%x)\n", j,
909 hc_sm_p[j].igu_sb_id,
910 hc_sm_p[j].igu_seg_id,
911 hc_sm_p[j].time_to_expire,
912 hc_sm_p[j].timer_value);
916 for (j = 0; j < loop; j++) {
917 pr_cont("INDEX[%d] flags (0x%x) "
918 "timeout (0x%x)\n", j,
920 hc_index_p[j].timeout);
924 #ifdef BNX2X_STOP_ON_ERROR
927 for_each_rx_queue(bp, i) {
928 struct bnx2x_fastpath *fp = &bp->fp[i];
930 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
931 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
932 for (j = start; j != end; j = RX_BD(j + 1)) {
933 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
934 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
936 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
937 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
940 start = RX_SGE(fp->rx_sge_prod);
941 end = RX_SGE(fp->last_max_sge);
942 for (j = start; j != end; j = RX_SGE(j + 1)) {
943 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
944 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
946 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
947 i, j, rx_sge[1], rx_sge[0], sw_page->page);
950 start = RCQ_BD(fp->rx_comp_cons - 10);
951 end = RCQ_BD(fp->rx_comp_cons + 503);
952 for (j = start; j != end; j = RCQ_BD(j + 1)) {
953 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
955 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
956 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
961 for_each_tx_queue(bp, i) {
962 struct bnx2x_fastpath *fp = &bp->fp[i];
964 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
965 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
966 for (j = start; j != end; j = TX_BD(j + 1)) {
967 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
969 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
970 i, j, sw_bd->skb, sw_bd->first_bd);
973 start = TX_BD(fp->tx_bd_cons - 10);
974 end = TX_BD(fp->tx_bd_cons + 254);
975 for (j = start; j != end; j = TX_BD(j + 1)) {
976 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
978 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
979 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
985 BNX2X_ERR("end crash dump -----------------\n");
991 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
994 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
995 #define FLR_WAIT_INTERAVAL 50 /* usec */
996 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
998 struct pbf_pN_buf_regs {
1005 struct pbf_pN_cmd_regs {
1011 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1012 struct pbf_pN_buf_regs *regs,
1015 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1016 u32 cur_cnt = poll_count;
1018 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1019 crd = crd_start = REG_RD(bp, regs->crd);
1020 init_crd = REG_RD(bp, regs->init_crd);
1022 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1023 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1024 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1026 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1027 (init_crd - crd_start))) {
1029 udelay(FLR_WAIT_INTERAVAL);
1030 crd = REG_RD(bp, regs->crd);
1031 crd_freed = REG_RD(bp, regs->crd_freed);
1033 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1035 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1037 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1038 regs->pN, crd_freed);
1042 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1043 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1046 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1047 struct pbf_pN_cmd_regs *regs,
1050 u32 occup, to_free, freed, freed_start;
1051 u32 cur_cnt = poll_count;
1053 occup = to_free = REG_RD(bp, regs->lines_occup);
1054 freed = freed_start = REG_RD(bp, regs->lines_freed);
1056 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1057 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1059 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1061 udelay(FLR_WAIT_INTERAVAL);
1062 occup = REG_RD(bp, regs->lines_occup);
1063 freed = REG_RD(bp, regs->lines_freed);
1065 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1067 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1069 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1074 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1075 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1078 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1079 u32 expected, u32 poll_count)
1081 u32 cur_cnt = poll_count;
1084 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1085 udelay(FLR_WAIT_INTERAVAL);
1090 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1091 char *msg, u32 poll_cnt)
1093 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1095 BNX2X_ERR("%s usage count=%d\n", msg, val);
1101 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1103 /* adjust polling timeout */
1104 if (CHIP_REV_IS_EMUL(bp))
1105 return FLR_POLL_CNT * 2000;
1107 if (CHIP_REV_IS_FPGA(bp))
1108 return FLR_POLL_CNT * 120;
1110 return FLR_POLL_CNT;
1113 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1115 struct pbf_pN_cmd_regs cmd_regs[] = {
1116 {0, (CHIP_IS_E3B0(bp)) ?
1117 PBF_REG_TQ_OCCUPANCY_Q0 :
1118 PBF_REG_P0_TQ_OCCUPANCY,
1119 (CHIP_IS_E3B0(bp)) ?
1120 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1121 PBF_REG_P0_TQ_LINES_FREED_CNT},
1122 {1, (CHIP_IS_E3B0(bp)) ?
1123 PBF_REG_TQ_OCCUPANCY_Q1 :
1124 PBF_REG_P1_TQ_OCCUPANCY,
1125 (CHIP_IS_E3B0(bp)) ?
1126 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1127 PBF_REG_P1_TQ_LINES_FREED_CNT},
1128 {4, (CHIP_IS_E3B0(bp)) ?
1129 PBF_REG_TQ_OCCUPANCY_LB_Q :
1130 PBF_REG_P4_TQ_OCCUPANCY,
1131 (CHIP_IS_E3B0(bp)) ?
1132 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1133 PBF_REG_P4_TQ_LINES_FREED_CNT}
1136 struct pbf_pN_buf_regs buf_regs[] = {
1137 {0, (CHIP_IS_E3B0(bp)) ?
1138 PBF_REG_INIT_CRD_Q0 :
1139 PBF_REG_P0_INIT_CRD ,
1140 (CHIP_IS_E3B0(bp)) ?
1143 (CHIP_IS_E3B0(bp)) ?
1144 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1145 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1146 {1, (CHIP_IS_E3B0(bp)) ?
1147 PBF_REG_INIT_CRD_Q1 :
1148 PBF_REG_P1_INIT_CRD,
1149 (CHIP_IS_E3B0(bp)) ?
1152 (CHIP_IS_E3B0(bp)) ?
1153 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1154 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1155 {4, (CHIP_IS_E3B0(bp)) ?
1156 PBF_REG_INIT_CRD_LB_Q :
1157 PBF_REG_P4_INIT_CRD,
1158 (CHIP_IS_E3B0(bp)) ?
1159 PBF_REG_CREDIT_LB_Q :
1161 (CHIP_IS_E3B0(bp)) ?
1162 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1163 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1168 /* Verify the command queues are flushed P0, P1, P4 */
1169 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1170 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1173 /* Verify the transmission buffers are flushed P0, P1, P4 */
1174 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1175 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1178 #define OP_GEN_PARAM(param) \
1179 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1181 #define OP_GEN_TYPE(type) \
1182 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1184 #define OP_GEN_AGG_VECT(index) \
1185 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1188 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1191 struct sdm_op_gen op_gen = {0};
1193 u32 comp_addr = BAR_CSTRORM_INTMEM +
1194 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1197 if (REG_RD(bp, comp_addr)) {
1198 BNX2X_ERR("Cleanup complete is not 0\n");
1202 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1203 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1204 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1205 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1207 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1208 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1210 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1211 BNX2X_ERR("FW final cleanup did not succeed\n");
1214 /* Zero completion for nxt FLR */
1215 REG_WR(bp, comp_addr, 0);
1220 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1225 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1229 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1230 return status & PCI_EXP_DEVSTA_TRPND;
1233 /* PF FLR specific routines
1235 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1238 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1239 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1240 CFC_REG_NUM_LCIDS_INSIDE_PF,
1241 "CFC PF usage counter timed out",
1246 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1247 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1248 DORQ_REG_PF_USAGE_CNT,
1249 "DQ PF usage counter timed out",
1253 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1255 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1256 "QM PF usage counter timed out",
1260 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1261 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1262 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1263 "Timers VNIC usage counter timed out",
1266 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1267 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1268 "Timers NUM_SCANS usage counter timed out",
1272 /* Wait DMAE PF usage counter to zero */
1273 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1274 dmae_reg_go_c[INIT_DMAE_C(bp)],
1275 "DMAE dommand register timed out",
1282 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1286 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1287 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1289 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1290 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1292 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1293 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1295 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1296 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1298 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1299 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1301 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1302 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1304 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1305 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1307 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1308 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1312 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1314 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1316 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1318 /* Re-enable PF target read access */
1319 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1321 /* Poll HW usage counters */
1322 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1325 /* Zero the igu 'trailing edge' and 'leading edge' */
1327 /* Send the FW cleanup command */
1328 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1333 /* Verify TX hw is flushed */
1334 bnx2x_tx_hw_flushed(bp, poll_cnt);
1336 /* Wait 100ms (not adjusted according to platform) */
1339 /* Verify no pending pci transactions */
1340 if (bnx2x_is_pcie_pending(bp->pdev))
1341 BNX2X_ERR("PCIE Transactions still pending\n");
1344 bnx2x_hw_enable_status(bp);
1347 * Master enable - Due to WB DMAE writes performed before this
1348 * register is re-initialized as part of the regular function init
1350 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1355 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1357 int port = BP_PORT(bp);
1358 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1359 u32 val = REG_RD(bp, addr);
1360 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1361 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1364 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1365 HC_CONFIG_0_REG_INT_LINE_EN_0);
1366 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1367 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1369 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1370 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1371 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1372 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1374 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1375 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1376 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1377 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1379 if (!CHIP_IS_E1(bp)) {
1380 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1383 REG_WR(bp, addr, val);
1385 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1390 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1392 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1393 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1395 REG_WR(bp, addr, val);
1397 * Ensure that HC_CONFIG is written before leading/trailing edge config
1402 if (!CHIP_IS_E1(bp)) {
1403 /* init leading/trailing edge */
1405 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1407 /* enable nig and gpio3 attention */
1412 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1413 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1416 /* Make sure that interrupts are indeed enabled from here on */
1420 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1423 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1424 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1426 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1429 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1430 IGU_PF_CONF_SINGLE_ISR_EN);
1431 val |= (IGU_PF_CONF_FUNC_EN |
1432 IGU_PF_CONF_MSI_MSIX_EN |
1433 IGU_PF_CONF_ATTN_BIT_EN);
1435 val &= ~IGU_PF_CONF_INT_LINE_EN;
1436 val |= (IGU_PF_CONF_FUNC_EN |
1437 IGU_PF_CONF_MSI_MSIX_EN |
1438 IGU_PF_CONF_ATTN_BIT_EN |
1439 IGU_PF_CONF_SINGLE_ISR_EN);
1441 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1442 val |= (IGU_PF_CONF_FUNC_EN |
1443 IGU_PF_CONF_INT_LINE_EN |
1444 IGU_PF_CONF_ATTN_BIT_EN |
1445 IGU_PF_CONF_SINGLE_ISR_EN);
1448 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1449 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1451 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1455 /* init leading/trailing edge */
1457 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1459 /* enable nig and gpio3 attention */
1464 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1465 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1467 /* Make sure that interrupts are indeed enabled from here on */
1471 void bnx2x_int_enable(struct bnx2x *bp)
1473 if (bp->common.int_block == INT_BLOCK_HC)
1474 bnx2x_hc_int_enable(bp);
1476 bnx2x_igu_int_enable(bp);
1479 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1481 int port = BP_PORT(bp);
1482 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1483 u32 val = REG_RD(bp, addr);
1486 * in E1 we must use only PCI configuration space to disable
1487 * MSI/MSIX capablility
1488 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1490 if (CHIP_IS_E1(bp)) {
1491 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1492 * Use mask register to prevent from HC sending interrupts
1493 * after we exit the function
1495 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1497 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1498 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1501 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1502 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1503 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1506 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1509 /* flush all outstanding writes */
1512 REG_WR(bp, addr, val);
1513 if (REG_RD(bp, addr) != val)
1514 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1517 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1519 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1521 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1522 IGU_PF_CONF_INT_LINE_EN |
1523 IGU_PF_CONF_ATTN_BIT_EN);
1525 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1527 /* flush all outstanding writes */
1530 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1531 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1532 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1535 static void bnx2x_int_disable(struct bnx2x *bp)
1537 if (bp->common.int_block == INT_BLOCK_HC)
1538 bnx2x_hc_int_disable(bp);
1540 bnx2x_igu_int_disable(bp);
1543 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1545 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1549 /* prevent the HW from sending interrupts */
1550 bnx2x_int_disable(bp);
1552 /* make sure all ISRs are done */
1554 synchronize_irq(bp->msix_table[0].vector);
1559 for_each_eth_queue(bp, i)
1560 synchronize_irq(bp->msix_table[offset++].vector);
1562 synchronize_irq(bp->pdev->irq);
1564 /* make sure sp_task is not running */
1565 cancel_delayed_work(&bp->sp_task);
1566 flush_workqueue(bnx2x_wq);
1572 * General service functions
1575 /* Return true if succeeded to acquire the lock */
1576 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1579 u32 resource_bit = (1 << resource);
1580 int func = BP_FUNC(bp);
1581 u32 hw_lock_control_reg;
1583 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1585 /* Validating that the resource is within range */
1586 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1588 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1589 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1594 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1596 hw_lock_control_reg =
1597 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1599 /* Try to acquire the lock */
1600 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1601 lock_status = REG_RD(bp, hw_lock_control_reg);
1602 if (lock_status & resource_bit)
1605 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1610 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1612 * @bp: driver handle
1614 * Returns the recovery leader resource id according to the engine this function
1615 * belongs to. Currently only only 2 engines is supported.
1617 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1620 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1622 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1626 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1628 * @bp: driver handle
1630 * Tries to aquire a leader lock for cuurent engine.
1632 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1634 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1638 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1641 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1643 struct bnx2x *bp = fp->bp;
1644 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1645 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1646 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1647 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1650 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1651 fp->index, cid, command, bp->state,
1652 rr_cqe->ramrod_cqe.ramrod_type);
1655 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1656 DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
1657 drv_cmd = BNX2X_Q_CMD_UPDATE;
1659 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1660 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1661 drv_cmd = BNX2X_Q_CMD_SETUP;
1664 case (RAMROD_CMD_ID_ETH_HALT):
1665 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1666 drv_cmd = BNX2X_Q_CMD_HALT;
1669 case (RAMROD_CMD_ID_ETH_TERMINATE):
1670 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1671 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1674 case (RAMROD_CMD_ID_ETH_EMPTY):
1675 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
1676 drv_cmd = BNX2X_Q_CMD_EMPTY;
1680 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1681 command, fp->index);
1685 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1686 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1687 /* q_obj->complete_cmd() failure means that this was
1688 * an unexpected completion.
1690 * In this case we don't want to increase the bp->spq_left
1691 * because apparently we haven't sent this command the first
1694 #ifdef BNX2X_STOP_ON_ERROR
1700 smp_mb__before_atomic_inc();
1701 atomic_inc(&bp->cq_spq_left);
1702 /* push the change in bp->spq_left and towards the memory */
1703 smp_mb__after_atomic_inc();
1708 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1709 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1711 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1713 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1717 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1719 struct bnx2x *bp = netdev_priv(dev_instance);
1720 u16 status = bnx2x_ack_int(bp);
1724 /* Return here if interrupt is shared and it's not for us */
1725 if (unlikely(status == 0)) {
1726 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1729 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1731 #ifdef BNX2X_STOP_ON_ERROR
1732 if (unlikely(bp->panic))
1736 for_each_eth_queue(bp, i) {
1737 struct bnx2x_fastpath *fp = &bp->fp[i];
1739 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1740 if (status & mask) {
1741 /* Handle Rx or Tx according to SB id */
1742 prefetch(fp->rx_cons_sb);
1743 prefetch(fp->tx_cons_sb);
1744 prefetch(&fp->sb_running_index[SM_RX_ID]);
1745 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1752 if (status & (mask | 0x1)) {
1753 struct cnic_ops *c_ops = NULL;
1755 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1757 c_ops = rcu_dereference(bp->cnic_ops);
1759 c_ops->cnic_handler(bp->cnic_data, NULL);
1767 if (unlikely(status & 0x1)) {
1768 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1775 if (unlikely(status))
1776 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1785 * General service functions
1788 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1791 u32 resource_bit = (1 << resource);
1792 int func = BP_FUNC(bp);
1793 u32 hw_lock_control_reg;
1796 /* Validating that the resource is within range */
1797 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1799 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1800 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1805 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1807 hw_lock_control_reg =
1808 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1811 /* Validating that the resource is not already taken */
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit) {
1814 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1815 lock_status, resource_bit);
1819 /* Try for 5 second every 5ms */
1820 for (cnt = 0; cnt < 1000; cnt++) {
1821 /* Try to acquire the lock */
1822 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1823 lock_status = REG_RD(bp, hw_lock_control_reg);
1824 if (lock_status & resource_bit)
1829 DP(NETIF_MSG_HW, "Timeout\n");
1833 int bnx2x_release_leader_lock(struct bnx2x *bp)
1835 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1838 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1841 u32 resource_bit = (1 << resource);
1842 int func = BP_FUNC(bp);
1843 u32 hw_lock_control_reg;
1845 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1847 /* Validating that the resource is within range */
1848 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1850 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1851 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1856 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1858 hw_lock_control_reg =
1859 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1862 /* Validating that the resource is currently taken */
1863 lock_status = REG_RD(bp, hw_lock_control_reg);
1864 if (!(lock_status & resource_bit)) {
1865 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1866 lock_status, resource_bit);
1870 REG_WR(bp, hw_lock_control_reg, resource_bit);
1875 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1877 /* The GPIO should be swapped if swap register is set and active */
1878 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1879 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1880 int gpio_shift = gpio_num +
1881 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1882 u32 gpio_mask = (1 << gpio_shift);
1886 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1887 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1891 /* read GPIO value */
1892 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1894 /* get the requested pin value */
1895 if ((gpio_reg & gpio_mask) == gpio_mask)
1900 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1905 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1907 /* The GPIO should be swapped if swap register is set and active */
1908 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1909 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1910 int gpio_shift = gpio_num +
1911 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1912 u32 gpio_mask = (1 << gpio_shift);
1915 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1916 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1920 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1921 /* read GPIO and mask except the float bits */
1922 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1925 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1926 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1927 gpio_num, gpio_shift);
1928 /* clear FLOAT and set CLR */
1929 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1930 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1933 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1934 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1935 gpio_num, gpio_shift);
1936 /* clear FLOAT and set SET */
1937 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1938 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1941 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1942 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1943 gpio_num, gpio_shift);
1945 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1952 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1953 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1958 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1963 /* Any port swapping should be handled by caller. */
1965 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1966 /* read GPIO and mask except the float bits */
1967 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1968 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1969 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1970 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1973 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1974 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1976 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1979 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1980 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1982 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1985 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1986 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1988 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1992 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1998 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2000 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2005 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2007 /* The GPIO should be swapped if swap register is set and active */
2008 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2009 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2010 int gpio_shift = gpio_num +
2011 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2012 u32 gpio_mask = (1 << gpio_shift);
2015 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2016 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2020 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2022 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2025 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2026 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2027 "output low\n", gpio_num, gpio_shift);
2028 /* clear SET and set CLR */
2029 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2030 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2033 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2034 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2035 "output high\n", gpio_num, gpio_shift);
2036 /* clear CLR and set SET */
2037 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2038 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2045 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2046 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2051 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2053 u32 spio_mask = (1 << spio_num);
2056 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2057 (spio_num > MISC_REGISTERS_SPIO_7)) {
2058 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2062 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2063 /* read SPIO and mask except the float bits */
2064 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2067 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2068 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2069 /* clear FLOAT and set CLR */
2070 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2071 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2074 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2075 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2076 /* clear FLOAT and set SET */
2077 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2078 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2081 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2082 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2084 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2091 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2092 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2097 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2099 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2100 switch (bp->link_vars.ieee_fc &
2101 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2102 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2103 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2107 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2108 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2112 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2113 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2117 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2123 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2125 if (!BP_NOMCP(bp)) {
2127 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2128 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2129 /* Initialize link parameters structure variables */
2130 /* It is recommended to turn off RX FC for jumbo frames
2131 for better performance */
2132 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
2133 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2135 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2137 bnx2x_acquire_phy_lock(bp);
2139 if (load_mode == LOAD_DIAG) {
2140 bp->link_params.loopback_mode = LOOPBACK_XGXS;
2141 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
2144 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2146 bnx2x_release_phy_lock(bp);
2148 bnx2x_calc_fc_adv(bp);
2150 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2151 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2152 bnx2x_link_report(bp);
2154 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2157 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2161 void bnx2x_link_set(struct bnx2x *bp)
2163 if (!BP_NOMCP(bp)) {
2164 bnx2x_acquire_phy_lock(bp);
2165 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2166 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2167 bnx2x_release_phy_lock(bp);
2169 bnx2x_calc_fc_adv(bp);
2171 BNX2X_ERR("Bootcode is missing - can not set link\n");
2174 static void bnx2x__link_reset(struct bnx2x *bp)
2176 if (!BP_NOMCP(bp)) {
2177 bnx2x_acquire_phy_lock(bp);
2178 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2179 bnx2x_release_phy_lock(bp);
2181 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2184 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2188 if (!BP_NOMCP(bp)) {
2189 bnx2x_acquire_phy_lock(bp);
2190 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2192 bnx2x_release_phy_lock(bp);
2194 BNX2X_ERR("Bootcode is missing - can not test link\n");
2199 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2201 u32 r_param = bp->link_vars.line_speed / 8;
2202 u32 fair_periodic_timeout_usec;
2205 memset(&(bp->cmng.rs_vars), 0,
2206 sizeof(struct rate_shaping_vars_per_port));
2207 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2209 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2210 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2212 /* this is the threshold below which no timer arming will occur
2213 1.25 coefficient is for the threshold to be a little bigger
2214 than the real time, to compensate for timer in-accuracy */
2215 bp->cmng.rs_vars.rs_threshold =
2216 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2218 /* resolution of fairness timer */
2219 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2220 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2221 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2223 /* this is the threshold below which we won't arm the timer anymore */
2224 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2226 /* we multiply by 1e3/8 to get bytes/msec.
2227 We don't want the credits to pass a credit
2228 of the t_fair*FAIR_MEM (algorithm resolution) */
2229 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2230 /* since each tick is 4 usec */
2231 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2234 /* Calculates the sum of vn_min_rates.
2235 It's needed for further normalizing of the min_rates.
2237 sum of vn_min_rates.
2239 0 - if all the min_rates are 0.
2240 In the later case fainess algorithm should be deactivated.
2241 If not all min_rates are zero then those that are zeroes will be set to 1.
2243 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2248 bp->vn_weight_sum = 0;
2249 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2250 u32 vn_cfg = bp->mf_config[vn];
2251 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2252 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2254 /* Skip hidden vns */
2255 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2258 /* If min rate is zero - set it to 1 */
2260 vn_min_rate = DEF_MIN_RATE;
2264 bp->vn_weight_sum += vn_min_rate;
2267 /* if ETS or all min rates are zeros - disable fairness */
2268 if (BNX2X_IS_ETS_ENABLED(bp)) {
2269 bp->cmng.flags.cmng_enables &=
2270 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2271 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2272 } else if (all_zero) {
2273 bp->cmng.flags.cmng_enables &=
2274 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2275 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2276 " fairness will be disabled\n");
2278 bp->cmng.flags.cmng_enables |=
2279 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2282 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2284 struct rate_shaping_vars_per_vn m_rs_vn;
2285 struct fairness_vars_per_vn m_fair_vn;
2286 u32 vn_cfg = bp->mf_config[vn];
2287 int func = 2*vn + BP_PORT(bp);
2288 u16 vn_min_rate, vn_max_rate;
2291 /* If function is hidden - set min and max to zeroes */
2292 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2297 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2299 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2300 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2301 /* If fairness is enabled (not all min rates are zeroes) and
2302 if current min rate is zero - set it to 1.
2303 This is a requirement of the algorithm. */
2304 if (bp->vn_weight_sum && (vn_min_rate == 0))
2305 vn_min_rate = DEF_MIN_RATE;
2308 /* maxCfg in percents of linkspeed */
2309 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2311 /* maxCfg is absolute in 100Mb units */
2312 vn_max_rate = maxCfg * 100;
2316 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2317 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2319 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2320 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2322 /* global vn counter - maximal Mbps for this vn */
2323 m_rs_vn.vn_counter.rate = vn_max_rate;
2325 /* quota - number of bytes transmitted in this period */
2326 m_rs_vn.vn_counter.quota =
2327 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2329 if (bp->vn_weight_sum) {
2330 /* credit for each period of the fairness algorithm:
2331 number of bytes in T_FAIR (the vn share the port rate).
2332 vn_weight_sum should not be larger than 10000, thus
2333 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2335 m_fair_vn.vn_credit_delta =
2336 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2337 (8 * bp->vn_weight_sum))),
2338 (bp->cmng.fair_vars.fair_threshold +
2340 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2341 m_fair_vn.vn_credit_delta);
2344 /* Store it to internal memory */
2345 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2346 REG_WR(bp, BAR_XSTRORM_INTMEM +
2347 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2348 ((u32 *)(&m_rs_vn))[i]);
2350 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2351 REG_WR(bp, BAR_XSTRORM_INTMEM +
2352 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2353 ((u32 *)(&m_fair_vn))[i]);
2356 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2358 if (CHIP_REV_IS_SLOW(bp))
2359 return CMNG_FNS_NONE;
2361 return CMNG_FNS_MINMAX;
2363 return CMNG_FNS_NONE;
2366 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2368 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2371 return; /* what should be the default bvalue in this case */
2373 /* For 2 port configuration the absolute function number formula
2375 * abs_func = 2 * vn + BP_PORT + BP_PATH
2377 * and there are 4 functions per port
2379 * For 4 port configuration it is
2380 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2382 * and there are 2 functions per port
2384 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2385 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2387 if (func >= E1H_FUNC_MAX)
2391 MF_CFG_RD(bp, func_mf_config[func].config);
2395 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2398 if (cmng_type == CMNG_FNS_MINMAX) {
2401 /* clear cmng_enables */
2402 bp->cmng.flags.cmng_enables = 0;
2404 /* read mf conf from shmem */
2406 bnx2x_read_mf_cfg(bp);
2408 /* Init rate shaping and fairness contexts */
2409 bnx2x_init_port_minmax(bp);
2411 /* vn_weight_sum and enable fairness if not 0 */
2412 bnx2x_calc_vn_weight_sum(bp);
2414 /* calculate and set min-max rate for each vn */
2416 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2417 bnx2x_init_vn_minmax(bp, vn);
2419 /* always enable rate shaping and fairness */
2420 bp->cmng.flags.cmng_enables |=
2421 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2422 if (!bp->vn_weight_sum)
2423 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2424 " fairness will be disabled\n");
2428 /* rate shaping and fairness are disabled */
2430 "rate shaping and fairness are disabled\n");
2433 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2435 int port = BP_PORT(bp);
2439 /* Set the attention towards other drivers on the same port */
2440 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2441 if (vn == BP_E1HVN(bp))
2444 func = ((vn << 1) | port);
2445 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2446 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2450 /* This function is called upon link interrupt */
2451 static void bnx2x_link_attn(struct bnx2x *bp)
2453 /* Make sure that we are synced with the current statistics */
2454 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2456 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2458 if (bp->link_vars.link_up) {
2460 /* dropless flow control */
2461 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2462 int port = BP_PORT(bp);
2463 u32 pause_enabled = 0;
2465 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2468 REG_WR(bp, BAR_USTRORM_INTMEM +
2469 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2473 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2474 struct host_port_stats *pstats;
2476 pstats = bnx2x_sp(bp, port_stats);
2477 /* reset old mac stats */
2478 memset(&(pstats->mac_stx[0]), 0,
2479 sizeof(struct mac_stx));
2481 if (bp->state == BNX2X_STATE_OPEN)
2482 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2485 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2486 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2488 if (cmng_fns != CMNG_FNS_NONE) {
2489 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2490 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2492 /* rate shaping and fairness are disabled */
2494 "single function mode without fairness\n");
2497 __bnx2x_link_report(bp);
2500 bnx2x_link_sync_notify(bp);
2503 void bnx2x__link_status_update(struct bnx2x *bp)
2505 if (bp->state != BNX2X_STATE_OPEN)
2508 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2510 if (bp->link_vars.link_up)
2511 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2513 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2515 /* indicate link status */
2516 bnx2x_link_report(bp);
2519 static void bnx2x_pmf_update(struct bnx2x *bp)
2521 int port = BP_PORT(bp);
2525 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2527 bnx2x_dcbx_pmf_update(bp);
2529 /* enable nig attention */
2530 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2531 if (bp->common.int_block == INT_BLOCK_HC) {
2532 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2533 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2534 } else if (!CHIP_IS_E1x(bp)) {
2535 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2536 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2539 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2547 * General service functions
2550 /* send the MCP a request, block until there is a reply */
2551 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2553 int mb_idx = BP_FW_MB_IDX(bp);
2557 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2559 mutex_lock(&bp->fw_mb_mutex);
2561 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2562 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2564 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2565 (command | seq), param);
2568 /* let the FW do it's magic ... */
2571 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2573 /* Give the FW up to 5 second (500*10ms) */
2574 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2576 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2577 cnt*delay, rc, seq);
2579 /* is this a reply to our command? */
2580 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2581 rc &= FW_MSG_CODE_MASK;
2584 BNX2X_ERR("FW failed to respond!\n");
2588 mutex_unlock(&bp->fw_mb_mutex);
2593 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2596 /* Statistics are not supported for CNIC Clients at the moment */
2603 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2605 if (CHIP_IS_E1x(bp)) {
2606 struct tstorm_eth_function_common_config tcfg = {0};
2608 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2611 /* Enable the function in the FW */
2612 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2613 storm_memset_func_en(bp, p->func_id, 1);
2616 if (p->func_flgs & FUNC_FLG_SPQ) {
2617 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2618 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2619 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2623 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2624 struct bnx2x_fastpath *fp,
2627 unsigned long flags = 0;
2629 /* PF driver will always initialize the Queue to an ACTIVE state */
2630 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2632 /* calculate other queue flags */
2634 __set_bit(BNX2X_Q_FLG_OV, &flags);
2637 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2639 if (!fp->disable_tpa)
2640 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2642 if (stat_counter_valid(bp, fp)) {
2643 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2644 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2648 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2649 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2652 /* Always set HW VLAN stripping */
2653 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2658 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2659 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init)
2661 gen_init->stat_id = bnx2x_stats_id(fp);
2662 gen_init->spcl_id = fp->cl_id;
2664 /* Always use mini-jumbo MTU for FCoE L2 ring */
2666 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2668 gen_init->mtu = bp->dev->mtu;
2671 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2672 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2673 struct bnx2x_rxq_setup_params *rxq_init)
2677 u16 tpa_agg_size = 0;
2679 if (!fp->disable_tpa) {
2680 pause->sge_th_hi = 250;
2681 pause->sge_th_lo = 150;
2682 tpa_agg_size = min_t(u32,
2683 (min_t(u32, 8, MAX_SKB_FRAGS) *
2684 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2685 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2687 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2688 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2689 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2693 /* pause - not for e1 */
2694 if (!CHIP_IS_E1(bp)) {
2695 pause->bd_th_hi = 350;
2696 pause->bd_th_lo = 250;
2697 pause->rcq_th_hi = 350;
2698 pause->rcq_th_lo = 250;
2704 rxq_init->dscr_map = fp->rx_desc_mapping;
2705 rxq_init->sge_map = fp->rx_sge_mapping;
2706 rxq_init->rcq_map = fp->rx_comp_mapping;
2707 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2709 /* This should be a maximum number of data bytes that may be
2710 * placed on the BD (not including paddings).
2712 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2713 IP_HEADER_ALIGNMENT_PADDING;
2715 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2716 rxq_init->tpa_agg_sz = tpa_agg_size;
2717 rxq_init->sge_buf_sz = sge_sz;
2718 rxq_init->max_sges_pkt = max_sge;
2719 rxq_init->rss_engine_id = BP_FUNC(bp);
2721 /* Maximum number or simultaneous TPA aggregation for this Queue.
2723 * For PF Clients it should be the maximum avaliable number.
2724 * VF driver(s) may want to define it to a smaller value.
2726 rxq_init->max_tpa_queues =
2727 (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
2728 ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
2730 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2731 rxq_init->fw_sb_id = fp->fw_sb_id;
2734 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2736 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2739 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2740 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init)
2742 txq_init->dscr_map = fp->tx_desc_mapping;
2743 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2744 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2745 txq_init->fw_sb_id = fp->fw_sb_id;
2748 * set the tss leading client id for TX classfication ==
2749 * leading RSS client id
2751 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2753 if (IS_FCOE_FP(fp)) {
2754 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2755 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2759 static void bnx2x_pf_init(struct bnx2x *bp)
2761 struct bnx2x_func_init_params func_init = {0};
2762 struct event_ring_data eq_data = { {0} };
2765 if (!CHIP_IS_E1x(bp)) {
2766 /* reset IGU PF statistics: MSIX + ATTN */
2768 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2769 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2770 (CHIP_MODE_IS_4_PORT(bp) ?
2771 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2773 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2774 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2775 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2776 (CHIP_MODE_IS_4_PORT(bp) ?
2777 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2780 /* function setup flags */
2781 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2783 /* This flag is relevant for E1x only.
2784 * E2 doesn't have a TPA configuration in a function level.
2786 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2788 func_init.func_flgs = flags;
2789 func_init.pf_id = BP_FUNC(bp);
2790 func_init.func_id = BP_FUNC(bp);
2791 func_init.spq_map = bp->spq_mapping;
2792 func_init.spq_prod = bp->spq_prod_idx;
2794 bnx2x_func_init(bp, &func_init);
2796 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2799 * Congestion management values depend on the link rate
2800 * There is no active link so initial link rate is set to 10 Gbps.
2801 * When the link comes up The congestion management values are
2802 * re-calculated according to the actual link rate.
2804 bp->link_vars.line_speed = SPEED_10000;
2805 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2807 /* Only the PMF sets the HW */
2809 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2811 /* init Event Queue */
2812 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2813 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2814 eq_data.producer = bp->eq_prod;
2815 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2816 eq_data.sb_id = DEF_SB_ID;
2817 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2821 static void bnx2x_e1h_disable(struct bnx2x *bp)
2823 int port = BP_PORT(bp);
2825 bnx2x_tx_disable(bp);
2827 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2830 static void bnx2x_e1h_enable(struct bnx2x *bp)
2832 int port = BP_PORT(bp);
2834 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2836 /* Tx queue should be only reenabled */
2837 netif_tx_wake_all_queues(bp->dev);
2840 * Should not call netif_carrier_on since it will be called if the link
2841 * is up when checking for link state
2845 /* called due to MCP event (on pmf):
2846 * reread new bandwidth configuration
2848 * notify others function about the change
2850 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2852 if (bp->link_vars.link_up) {
2853 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2854 bnx2x_link_sync_notify(bp);
2856 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2859 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2861 bnx2x_config_mf_bw(bp);
2862 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2865 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2867 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2869 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2872 * This is the only place besides the function initialization
2873 * where the bp->flags can change so it is done without any
2876 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2877 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2878 bp->flags |= MF_FUNC_DIS;
2880 bnx2x_e1h_disable(bp);
2882 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2883 bp->flags &= ~MF_FUNC_DIS;
2885 bnx2x_e1h_enable(bp);
2887 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2889 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2890 bnx2x_config_mf_bw(bp);
2891 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2894 /* Report results to MCP */
2896 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2898 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2901 /* must be called under the spq lock */
2902 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2904 struct eth_spe *next_spe = bp->spq_prod_bd;
2906 if (bp->spq_prod_bd == bp->spq_last_bd) {
2907 bp->spq_prod_bd = bp->spq;
2908 bp->spq_prod_idx = 0;
2909 DP(NETIF_MSG_TIMER, "end of spq\n");
2917 /* must be called under the spq lock */
2918 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2920 int func = BP_FUNC(bp);
2922 /* Make sure that BD data is updated before writing the producer */
2925 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2931 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
2933 * @cmd: command to check
2934 * @cmd_type: command type
2936 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
2938 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2939 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2940 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2941 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2942 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2943 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
2952 * bnx2x_sp_post - place a single command on an SP ring
2954 * @bp: driver handle
2955 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2956 * @cid: SW CID the command is related to
2957 * @data_hi: command private data address (high 32 bits)
2958 * @data_lo: command private data address (low 32 bits)
2959 * @cmd_type: command type (e.g. NONE, ETH)
2961 * SP data is handled as if it's always an address pair, thus data fields are
2962 * not swapped to little endian in upper functions. Instead this function swaps
2963 * data as if it's two u32 fields.
2965 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2966 u32 data_hi, u32 data_lo, int cmd_type)
2968 struct eth_spe *spe;
2970 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
2972 #ifdef BNX2X_STOP_ON_ERROR
2973 if (unlikely(bp->panic))
2977 spin_lock_bh(&bp->spq_lock);
2980 if (!atomic_read(&bp->eq_spq_left)) {
2981 BNX2X_ERR("BUG! EQ ring full!\n");
2982 spin_unlock_bh(&bp->spq_lock);
2986 } else if (!atomic_read(&bp->cq_spq_left)) {
2987 BNX2X_ERR("BUG! SPQ ring full!\n");
2988 spin_unlock_bh(&bp->spq_lock);
2993 spe = bnx2x_sp_get_next(bp);
2995 /* CID needs port number to be encoded int it */
2996 spe->hdr.conn_and_cmd_data =
2997 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3000 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3002 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3003 SPE_HDR_FUNCTION_ID);
3005 spe->hdr.type = cpu_to_le16(type);
3007 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3008 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3010 /* stats ramrod has it's own slot on the spq */
3011 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
3013 * It's ok if the actual decrement is issued towards the memory
3014 * somewhere between the spin_lock and spin_unlock. Thus no
3015 * more explict memory barrier is needed.
3018 atomic_dec(&bp->eq_spq_left);
3020 atomic_dec(&bp->cq_spq_left);
3024 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3025 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
3026 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
3027 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3028 (u32)(U64_LO(bp->spq_mapping) +
3029 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
3030 HW_CID(bp, cid), data_hi, data_lo, type,
3031 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3033 bnx2x_sp_prod_update(bp);
3034 spin_unlock_bh(&bp->spq_lock);
3038 /* acquire split MCP access lock register */
3039 static int bnx2x_acquire_alr(struct bnx2x *bp)
3045 for (j = 0; j < 1000; j++) {
3047 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3048 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3049 if (val & (1L << 31))
3054 if (!(val & (1L << 31))) {
3055 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3062 /* release split MCP access lock register */
3063 static void bnx2x_release_alr(struct bnx2x *bp)
3065 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3068 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3069 #define BNX2X_DEF_SB_IDX 0x0002
3071 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3073 struct host_sp_status_block *def_sb = bp->def_status_blk;
3076 barrier(); /* status block is written to by the chip */
3077 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3078 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3079 rc |= BNX2X_DEF_SB_ATT_IDX;
3082 if (bp->def_idx != def_sb->sp_sb.running_index) {
3083 bp->def_idx = def_sb->sp_sb.running_index;
3084 rc |= BNX2X_DEF_SB_IDX;
3087 /* Do not reorder: indecies reading should complete before handling */
3093 * slow path service functions
3096 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3098 int port = BP_PORT(bp);
3099 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3100 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3101 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3102 NIG_REG_MASK_INTERRUPT_PORT0;
3107 if (bp->attn_state & asserted)
3108 BNX2X_ERR("IGU ERROR\n");
3110 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3111 aeu_mask = REG_RD(bp, aeu_addr);
3113 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3114 aeu_mask, asserted);
3115 aeu_mask &= ~(asserted & 0x3ff);
3116 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3118 REG_WR(bp, aeu_addr, aeu_mask);
3119 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3121 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3122 bp->attn_state |= asserted;
3123 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3125 if (asserted & ATTN_HARD_WIRED_MASK) {
3126 if (asserted & ATTN_NIG_FOR_FUNC) {
3128 bnx2x_acquire_phy_lock(bp);
3130 /* save nig interrupt mask */
3131 nig_mask = REG_RD(bp, nig_int_mask_addr);
3133 /* If nig_mask is not set, no need to call the update
3137 REG_WR(bp, nig_int_mask_addr, 0);
3139 bnx2x_link_attn(bp);
3142 /* handle unicore attn? */
3144 if (asserted & ATTN_SW_TIMER_4_FUNC)
3145 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3147 if (asserted & GPIO_2_FUNC)
3148 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3150 if (asserted & GPIO_3_FUNC)
3151 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3153 if (asserted & GPIO_4_FUNC)
3154 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3157 if (asserted & ATTN_GENERAL_ATTN_1) {
3158 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3159 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3161 if (asserted & ATTN_GENERAL_ATTN_2) {
3162 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3163 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3165 if (asserted & ATTN_GENERAL_ATTN_3) {
3166 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3167 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3170 if (asserted & ATTN_GENERAL_ATTN_4) {
3171 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3172 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3174 if (asserted & ATTN_GENERAL_ATTN_5) {
3175 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3176 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3178 if (asserted & ATTN_GENERAL_ATTN_6) {
3179 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3180 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3184 } /* if hardwired */
3186 if (bp->common.int_block == INT_BLOCK_HC)
3187 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3188 COMMAND_REG_ATTN_BITS_SET);
3190 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3192 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3193 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3194 REG_WR(bp, reg_addr, asserted);
3196 /* now set back the mask */
3197 if (asserted & ATTN_NIG_FOR_FUNC) {
3198 REG_WR(bp, nig_int_mask_addr, nig_mask);
3199 bnx2x_release_phy_lock(bp);
3203 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3205 int port = BP_PORT(bp);
3207 /* mark the failure */
3210 dev_info.port_hw_config[port].external_phy_config);
3212 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3213 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3214 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3217 /* log the failure */
3218 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3219 " the driver to shutdown the card to prevent permanent"
3220 " damage. Please contact OEM Support for assistance\n");
3223 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3225 int port = BP_PORT(bp);
3229 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3230 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3232 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3234 val = REG_RD(bp, reg_offset);
3235 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3236 REG_WR(bp, reg_offset, val);
3238 BNX2X_ERR("SPIO5 hw attention\n");
3240 /* Fan failure attention */
3241 bnx2x_hw_reset_phy(&bp->link_params);
3242 bnx2x_fan_failure(bp);
3245 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3246 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3247 bnx2x_acquire_phy_lock(bp);
3248 bnx2x_handle_module_detect_int(&bp->link_params);
3249 bnx2x_release_phy_lock(bp);
3252 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3254 val = REG_RD(bp, reg_offset);
3255 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3256 REG_WR(bp, reg_offset, val);
3258 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3259 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3264 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3268 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3270 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3271 BNX2X_ERR("DB hw attention 0x%x\n", val);
3272 /* DORQ discard attention */
3274 BNX2X_ERR("FATAL error from DORQ\n");
3277 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3279 int port = BP_PORT(bp);
3282 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3283 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3285 val = REG_RD(bp, reg_offset);
3286 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3287 REG_WR(bp, reg_offset, val);
3289 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3290 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3295 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3299 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3301 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3302 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3303 /* CFC error attention */
3305 BNX2X_ERR("FATAL error from CFC\n");
3308 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3309 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3310 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3311 /* RQ_USDMDP_FIFO_OVERFLOW */
3313 BNX2X_ERR("FATAL error from PXP\n");
3315 if (!CHIP_IS_E1x(bp)) {
3316 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3317 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3321 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3323 int port = BP_PORT(bp);
3326 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3327 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3329 val = REG_RD(bp, reg_offset);
3330 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3331 REG_WR(bp, reg_offset, val);
3333 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3334 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3339 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3343 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3345 if (attn & BNX2X_PMF_LINK_ASSERT) {
3346 int func = BP_FUNC(bp);
3348 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3349 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3350 func_mf_config[BP_ABS_FUNC(bp)].config);
3352 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3353 if (val & DRV_STATUS_DCC_EVENT_MASK)
3355 (val & DRV_STATUS_DCC_EVENT_MASK));
3357 if (val & DRV_STATUS_SET_MF_BW)
3358 bnx2x_set_mf_bw(bp);
3360 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3361 bnx2x_pmf_update(bp);
3363 /* Always call it here: bnx2x_link_report() will
3364 * prevent the link indication duplication.
3366 bnx2x__link_status_update(bp);
3369 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3370 bp->dcbx_enabled > 0)
3371 /* start dcbx state machine */
3372 bnx2x_dcbx_set_params(bp,
3373 BNX2X_DCBX_STATE_NEG_RECEIVED);
3374 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3376 BNX2X_ERR("MC assert!\n");
3377 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3378 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3379 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3380 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3383 } else if (attn & BNX2X_MCP_ASSERT) {
3385 BNX2X_ERR("MCP assert!\n");
3386 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3390 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3393 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3394 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3395 if (attn & BNX2X_GRC_TIMEOUT) {
3396 val = CHIP_IS_E1(bp) ? 0 :
3397 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3398 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3400 if (attn & BNX2X_GRC_RSV) {
3401 val = CHIP_IS_E1(bp) ? 0 :
3402 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3403 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3405 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3411 * 0-7 - Engine0 load counter.
3412 * 8-15 - Engine1 load counter.
3413 * 16 - Engine0 RESET_IN_PROGRESS bit.
3414 * 17 - Engine1 RESET_IN_PROGRESS bit.
3415 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3417 * 19 - Engine1 ONE_IS_LOADED.
3418 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3419 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3420 * just the one belonging to its engine).
3423 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3425 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3426 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3427 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3428 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3429 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3430 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3431 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3434 * Set the GLOBAL_RESET bit.
3436 * Should be run under rtnl lock
3438 void bnx2x_set_reset_global(struct bnx2x *bp)
3440 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3442 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3448 * Clear the GLOBAL_RESET bit.
3450 * Should be run under rtnl lock
3452 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3454 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3456 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3462 * Checks the GLOBAL_RESET bit.
3464 * should be run under rtnl lock
3466 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3468 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3470 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3471 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3475 * Clear RESET_IN_PROGRESS bit for the current engine.
3477 * Should be run under rtnl lock
3479 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3481 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3482 u32 bit = BP_PATH(bp) ?
3483 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3487 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3493 * Set RESET_IN_PROGRESS for the current engine.
3495 * should be run under rtnl lock
3497 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3499 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3500 u32 bit = BP_PATH(bp) ?
3501 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3505 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3511 * Checks the RESET_IN_PROGRESS bit for the given engine.
3512 * should be run under rtnl lock
3514 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3516 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3518 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3520 /* return false if bit is set */
3521 return (val & bit) ? false : true;
3525 * Increment the load counter for the current engine.
3527 * should be run under rtnl lock
3529 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3531 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3532 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3533 BNX2X_PATH0_LOAD_CNT_MASK;
3534 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3535 BNX2X_PATH0_LOAD_CNT_SHIFT;
3537 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3539 /* get the current counter value */
3540 val1 = (val & mask) >> shift;
3545 /* clear the old value */
3548 /* set the new one */
3549 val |= ((val1 << shift) & mask);
3551 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3557 * bnx2x_dec_load_cnt - decrement the load counter
3559 * @bp: driver handle
3561 * Should be run under rtnl lock.
3562 * Decrements the load counter for the current engine. Returns
3563 * the new counter value.
3565 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3567 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3568 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3569 BNX2X_PATH0_LOAD_CNT_MASK;
3570 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3571 BNX2X_PATH0_LOAD_CNT_SHIFT;
3573 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3575 /* get the current counter value */
3576 val1 = (val & mask) >> shift;
3581 /* clear the old value */
3584 /* set the new one */
3585 val |= ((val1 << shift) & mask);
3587 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3595 * Read the load counter for the current engine.
3597 * should be run under rtnl lock
3599 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3601 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3602 BNX2X_PATH0_LOAD_CNT_MASK);
3603 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3604 BNX2X_PATH0_LOAD_CNT_SHIFT);
3605 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3607 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3609 val = (val & mask) >> shift;
3611 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3617 * Reset the load counter for the current engine.
3619 * should be run under rtnl lock
3621 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3623 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3624 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3625 BNX2X_PATH0_LOAD_CNT_MASK);
3627 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3630 static inline void _print_next_block(int idx, const char *blk)
3637 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3642 for (i = 0; sig; i++) {
3643 cur_bit = ((u32)0x1 << i);
3644 if (sig & cur_bit) {
3646 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3648 _print_next_block(par_num++, "BRB");
3650 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3652 _print_next_block(par_num++, "PARSER");
3654 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3656 _print_next_block(par_num++, "TSDM");
3658 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3660 _print_next_block(par_num++,
3663 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3665 _print_next_block(par_num++, "TCM");
3667 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3669 _print_next_block(par_num++, "TSEMI");
3671 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3673 _print_next_block(par_num++, "XPB");
3685 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3686 bool *global, bool print)
3690 for (i = 0; sig; i++) {
3691 cur_bit = ((u32)0x1 << i);
3692 if (sig & cur_bit) {
3694 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3696 _print_next_block(par_num++, "PBF");
3698 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3700 _print_next_block(par_num++, "QM");
3702 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3704 _print_next_block(par_num++, "TM");
3706 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3708 _print_next_block(par_num++, "XSDM");
3710 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3712 _print_next_block(par_num++, "XCM");
3714 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3716 _print_next_block(par_num++, "XSEMI");
3718 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3720 _print_next_block(par_num++,
3723 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3725 _print_next_block(par_num++, "NIG");
3727 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3729 _print_next_block(par_num++,
3733 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3735 _print_next_block(par_num++, "DEBUG");
3737 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3739 _print_next_block(par_num++, "USDM");
3741 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3743 _print_next_block(par_num++, "USEMI");
3745 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3747 _print_next_block(par_num++, "UPB");
3749 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3751 _print_next_block(par_num++, "CSDM");
3763 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3768 for (i = 0; sig; i++) {
3769 cur_bit = ((u32)0x1 << i);
3770 if (sig & cur_bit) {
3772 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3774 _print_next_block(par_num++, "CSEMI");
3776 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3778 _print_next_block(par_num++, "PXP");
3780 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3782 _print_next_block(par_num++,
3783 "PXPPCICLOCKCLIENT");
3785 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3787 _print_next_block(par_num++, "CFC");
3789 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3791 _print_next_block(par_num++, "CDU");
3793 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3795 _print_next_block(par_num++, "DMAE");
3797 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3799 _print_next_block(par_num++, "IGU");
3801 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3803 _print_next_block(par_num++, "MISC");
3815 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3816 bool *global, bool print)
3820 for (i = 0; sig; i++) {
3821 cur_bit = ((u32)0x1 << i);
3822 if (sig & cur_bit) {
3824 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3826 _print_next_block(par_num++, "MCP ROM");
3829 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3831 _print_next_block(par_num++,
3835 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3837 _print_next_block(par_num++,
3841 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3843 _print_next_block(par_num++,
3857 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3858 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
3860 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3861 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3863 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3864 "[0]:0x%08x [1]:0x%08x "
3865 "[2]:0x%08x [3]:0x%08x\n",
3866 sig0 & HW_PRTY_ASSERT_SET_0,
3867 sig1 & HW_PRTY_ASSERT_SET_1,
3868 sig2 & HW_PRTY_ASSERT_SET_2,
3869 sig3 & HW_PRTY_ASSERT_SET_3);
3872 "Parity errors detected in blocks: ");
3873 par_num = bnx2x_check_blocks_with_parity0(
3874 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3875 par_num = bnx2x_check_blocks_with_parity1(
3876 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3877 par_num = bnx2x_check_blocks_with_parity2(
3878 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3879 par_num = bnx2x_check_blocks_with_parity3(
3880 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3889 * bnx2x_chk_parity_attn - checks for parity attentions.
3891 * @bp: driver handle
3892 * @global: true if there was a global attention
3893 * @print: show parity attention in syslog
3895 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
3897 struct attn_route attn;
3898 int port = BP_PORT(bp);
3900 attn.sig[0] = REG_RD(bp,
3901 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3903 attn.sig[1] = REG_RD(bp,
3904 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3906 attn.sig[2] = REG_RD(bp,
3907 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3909 attn.sig[3] = REG_RD(bp,
3910 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3913 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3914 attn.sig[2], attn.sig[3]);
3918 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3921 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3923 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3924 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3925 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3926 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3928 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3929 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3930 "INCORRECT_RCV_BEHAVIOR\n");
3931 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3932 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3933 "WAS_ERROR_ATTN\n");
3934 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3935 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3936 "VF_LENGTH_VIOLATION_ATTN\n");
3938 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3939 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3940 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3942 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3943 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3944 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3945 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3946 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3947 "TCPL_ERROR_ATTN\n");
3948 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3949 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3950 "TCPL_IN_TWO_RCBS_ATTN\n");
3951 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3952 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3953 "CSSNOOP_FIFO_OVERFLOW\n");
3955 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3956 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3957 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3958 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3959 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3960 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3961 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3962 "_ATC_TCPL_TO_NOT_PEND\n");
3963 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3964 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3965 "ATC_GPA_MULTIPLE_HITS\n");
3966 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3967 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3968 "ATC_RCPL_TO_EMPTY_CNT\n");
3969 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3970 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3971 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3972 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3973 "ATC_IREQ_LESS_THAN_STU\n");
3976 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3977 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3978 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3979 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3980 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3985 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3987 struct attn_route attn, *group_mask;
3988 int port = BP_PORT(bp);
3993 bool global = false;
3995 /* need to take HW lock because MCP or other port might also
3996 try to handle this event */
3997 bnx2x_acquire_alr(bp);
3999 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4000 #ifndef BNX2X_STOP_ON_ERROR
4001 bp->recovery_state = BNX2X_RECOVERY_INIT;
4002 schedule_delayed_work(&bp->reset_task, 0);
4003 /* Disable HW interrupts */
4004 bnx2x_int_disable(bp);
4005 /* In case of parity errors don't handle attentions so that
4006 * other function would "see" parity errors.
4011 bnx2x_release_alr(bp);
4015 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4016 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4017 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4018 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4019 if (!CHIP_IS_E1x(bp))
4021 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4025 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4026 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4028 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4029 if (deasserted & (1 << index)) {
4030 group_mask = &bp->attn_group[index];
4032 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4035 group_mask->sig[0], group_mask->sig[1],
4036 group_mask->sig[2], group_mask->sig[3],
4037 group_mask->sig[4]);
4039 bnx2x_attn_int_deasserted4(bp,
4040 attn.sig[4] & group_mask->sig[4]);
4041 bnx2x_attn_int_deasserted3(bp,
4042 attn.sig[3] & group_mask->sig[3]);
4043 bnx2x_attn_int_deasserted1(bp,
4044 attn.sig[1] & group_mask->sig[1]);
4045 bnx2x_attn_int_deasserted2(bp,
4046 attn.sig[2] & group_mask->sig[2]);
4047 bnx2x_attn_int_deasserted0(bp,
4048 attn.sig[0] & group_mask->sig[0]);
4052 bnx2x_release_alr(bp);
4054 if (bp->common.int_block == INT_BLOCK_HC)
4055 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4056 COMMAND_REG_ATTN_BITS_CLR);
4058 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4061 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4062 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4063 REG_WR(bp, reg_addr, val);
4065 if (~bp->attn_state & deasserted)
4066 BNX2X_ERR("IGU ERROR\n");
4068 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4069 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4071 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4072 aeu_mask = REG_RD(bp, reg_addr);
4074 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4075 aeu_mask, deasserted);
4076 aeu_mask |= (deasserted & 0x3ff);
4077 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4079 REG_WR(bp, reg_addr, aeu_mask);
4080 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4082 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4083 bp->attn_state &= ~deasserted;
4084 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4087 static void bnx2x_attn_int(struct bnx2x *bp)
4089 /* read local copy of bits */
4090 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4092 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4094 u32 attn_state = bp->attn_state;
4096 /* look for changed bits */
4097 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4098 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4101 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4102 attn_bits, attn_ack, asserted, deasserted);
4104 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4105 BNX2X_ERR("BAD attention state\n");
4107 /* handle bits that were raised */
4109 bnx2x_attn_int_asserted(bp, asserted);
4112 bnx2x_attn_int_deasserted(bp, deasserted);
4115 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4116 u16 index, u8 op, u8 update)
4118 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4120 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4124 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4126 /* No memory barriers */
4127 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4128 mmiowb(); /* keep prod updates ordered */
4132 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4133 union event_ring_elem *elem)
4135 u8 err = elem->message.error;
4137 if (!bp->cnic_eth_dev.starting_cid ||
4138 (cid < bp->cnic_eth_dev.starting_cid &&
4139 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4142 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4144 if (unlikely(err)) {
4146 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4148 bnx2x_panic_dump(bp);
4150 bnx2x_cnic_cfc_comp(bp, cid, err);
4155 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4157 struct bnx2x_mcast_ramrod_params rparam;
4160 memset(&rparam, 0, sizeof(rparam));
4162 rparam.mcast_obj = &bp->mcast_obj;
4164 netif_addr_lock_bh(bp->dev);
4166 /* Clear pending state for the last command */
4167 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4169 /* If there are pending mcast commands - send them */
4170 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4171 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4173 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4177 netif_addr_unlock_bh(bp->dev);
4180 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4181 union event_ring_elem *elem)
4183 unsigned long ramrod_flags = 0;
4185 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4186 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4188 /* Always push next commands out, don't wait here */
4189 __set_bit(RAMROD_CONT, &ramrod_flags);
4191 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4192 case BNX2X_FILTER_MAC_PENDING:
4194 if (cid == BNX2X_ISCSI_ETH_CID)
4195 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4198 vlan_mac_obj = &bp->fp[cid].mac_obj;
4201 vlan_mac_obj = &bp->fp[cid].mac_obj;
4203 case BNX2X_FILTER_MCAST_PENDING:
4204 /* This is only relevant for 57710 where multicast MACs are
4205 * configured as unicast MACs using the same ramrod.
4207 bnx2x_handle_mcast_eqe(bp);
4210 BNX2X_ERR("Unsupported classification command: %d\n",
4211 elem->message.data.eth_event.echo);
4215 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4218 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4220 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4225 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4228 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4230 netif_addr_lock_bh(bp->dev);
4232 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4234 /* Send rx_mode command again if was requested */
4235 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4236 bnx2x_set_storm_rx_mode(bp);
4238 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4240 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4241 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4243 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4246 netif_addr_unlock_bh(bp->dev);
4249 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4250 struct bnx2x *bp, u32 cid)
4253 if (cid == BNX2X_FCOE_ETH_CID)
4254 return &bnx2x_fcoe(bp, q_obj);
4257 return &bnx2x_fp(bp, cid, q_obj);
4260 static void bnx2x_eq_int(struct bnx2x *bp)
4262 u16 hw_cons, sw_cons, sw_prod;
4263 union event_ring_elem *elem;
4267 struct bnx2x_queue_sp_obj *q_obj;
4268 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4269 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4271 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4273 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4274 * when we get the the next-page we nned to adjust so the loop
4275 * condition below will be met. The next element is the size of a
4276 * regular element and hence incrementing by 1
4278 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4281 /* This function may never run in parallel with itself for a
4282 * specific bp, thus there is no need in "paired" read memory
4285 sw_cons = bp->eq_cons;
4286 sw_prod = bp->eq_prod;
4288 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
4289 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4291 for (; sw_cons != hw_cons;
4292 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4295 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4297 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4298 opcode = elem->message.opcode;
4301 /* handle eq element */
4303 case EVENT_RING_OPCODE_STAT_QUERY:
4304 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4306 /* nothing to do with stats comp */
4309 case EVENT_RING_OPCODE_CFC_DEL:
4310 /* handle according to cid range */
4312 * we may want to verify here that the bp state is
4315 DP(NETIF_MSG_IFDOWN,
4316 "got delete ramrod for MULTI[%d]\n", cid);
4318 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4321 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4323 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4330 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4331 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
4332 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4335 case EVENT_RING_OPCODE_START_TRAFFIC:
4336 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
4337 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4339 case EVENT_RING_OPCODE_FUNCTION_START:
4340 DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
4341 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4346 case EVENT_RING_OPCODE_FUNCTION_STOP:
4347 DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
4348 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4354 switch (opcode | bp->state) {
4355 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4357 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4358 BNX2X_STATE_OPENING_WAIT4_PORT):
4359 cid = elem->message.data.eth_event.echo &
4361 DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
4363 rss_raw->clear_pending(rss_raw);
4366 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4367 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4368 case (EVENT_RING_OPCODE_SET_MAC |
4369 BNX2X_STATE_CLOSING_WAIT4_HALT):
4370 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4372 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4374 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4375 BNX2X_STATE_CLOSING_WAIT4_HALT):
4376 DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
4377 bnx2x_handle_classification_eqe(bp, elem);
4380 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4382 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4384 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4385 BNX2X_STATE_CLOSING_WAIT4_HALT):
4386 DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
4387 bnx2x_handle_mcast_eqe(bp);
4390 case (EVENT_RING_OPCODE_FILTERS_RULES |
4392 case (EVENT_RING_OPCODE_FILTERS_RULES |
4394 case (EVENT_RING_OPCODE_FILTERS_RULES |
4395 BNX2X_STATE_CLOSING_WAIT4_HALT):
4396 DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
4397 bnx2x_handle_rx_mode_eqe(bp);
4400 /* unknown event log error and continue */
4401 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4402 elem->message.opcode, bp->state);
4408 smp_mb__before_atomic_inc();
4409 atomic_add(spqe_cnt, &bp->eq_spq_left);
4411 bp->eq_cons = sw_cons;
4412 bp->eq_prod = sw_prod;
4413 /* Make sure that above mem writes were issued towards the memory */
4416 /* update producer */
4417 bnx2x_update_eq_prod(bp, bp->eq_prod);
4420 static void bnx2x_sp_task(struct work_struct *work)
4422 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4425 status = bnx2x_update_dsb_idx(bp);
4426 /* if (status == 0) */
4427 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4429 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4432 if (status & BNX2X_DEF_SB_ATT_IDX) {
4434 status &= ~BNX2X_DEF_SB_ATT_IDX;
4437 /* SP events: STAT_QUERY and others */
4438 if (status & BNX2X_DEF_SB_IDX) {
4440 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4442 if ((!NO_FCOE(bp)) &&
4443 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
4444 napi_schedule(&bnx2x_fcoe(bp, napi));
4446 /* Handle EQ completions */
4449 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4450 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4452 status &= ~BNX2X_DEF_SB_IDX;
4455 if (unlikely(status))
4456 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4459 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4460 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4463 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4465 struct net_device *dev = dev_instance;
4466 struct bnx2x *bp = netdev_priv(dev);
4468 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4469 IGU_INT_DISABLE, 0);
4471 #ifdef BNX2X_STOP_ON_ERROR
4472 if (unlikely(bp->panic))
4478 struct cnic_ops *c_ops;
4481 c_ops = rcu_dereference(bp->cnic_ops);
4483 c_ops->cnic_handler(bp->cnic_data, NULL);
4487 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4492 /* end of slow path */
4495 void bnx2x_drv_pulse(struct bnx2x *bp)
4497 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4498 bp->fw_drv_pulse_wr_seq);
4502 static void bnx2x_timer(unsigned long data)
4504 struct bnx2x *bp = (struct bnx2x *) data;
4506 if (!netif_running(bp->dev))
4510 struct bnx2x_fastpath *fp = &bp->fp[0];
4513 bnx2x_rx_int(fp, 1000);
4516 if (!BP_NOMCP(bp)) {
4517 int mb_idx = BP_FW_MB_IDX(bp);
4521 ++bp->fw_drv_pulse_wr_seq;
4522 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4523 /* TBD - add SYSTEM_TIME */
4524 drv_pulse = bp->fw_drv_pulse_wr_seq;
4525 bnx2x_drv_pulse(bp);
4527 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4528 MCP_PULSE_SEQ_MASK);
4529 /* The delta between driver pulse and mcp response
4530 * should be 1 (before mcp response) or 0 (after mcp response)
4532 if ((drv_pulse != mcp_pulse) &&
4533 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4534 /* someone lost a heartbeat... */
4535 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4536 drv_pulse, mcp_pulse);
4540 if (bp->state == BNX2X_STATE_OPEN)
4541 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4543 mod_timer(&bp->timer, jiffies + bp->current_interval);
4546 /* end of Statistics */
4551 * nic init service functions
4554 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4557 if (!(len%4) && !(addr%4))
4558 for (i = 0; i < len; i += 4)
4559 REG_WR(bp, addr + i, fill);
4561 for (i = 0; i < len; i++)
4562 REG_WR8(bp, addr + i, fill);
4566 /* helper: writes FP SP data to FW - data_size in dwords */
4567 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4573 for (index = 0; index < data_size; index++)
4574 REG_WR(bp, BAR_CSTRORM_INTMEM +
4575 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4577 *(sb_data_p + index));
4580 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4584 struct hc_status_block_data_e2 sb_data_e2;
4585 struct hc_status_block_data_e1x sb_data_e1x;
4587 /* disable the function first */
4588 if (!CHIP_IS_E1x(bp)) {
4589 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4590 sb_data_e2.common.state = SB_DISABLED;
4591 sb_data_e2.common.p_func.vf_valid = false;
4592 sb_data_p = (u32 *)&sb_data_e2;
4593 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4595 memset(&sb_data_e1x, 0,
4596 sizeof(struct hc_status_block_data_e1x));
4597 sb_data_e1x.common.state = SB_DISABLED;
4598 sb_data_e1x.common.p_func.vf_valid = false;
4599 sb_data_p = (u32 *)&sb_data_e1x;
4600 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4602 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4604 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4605 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4606 CSTORM_STATUS_BLOCK_SIZE);
4607 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4608 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4609 CSTORM_SYNC_BLOCK_SIZE);
4612 /* helper: writes SP SB data to FW */
4613 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4614 struct hc_sp_status_block_data *sp_sb_data)
4616 int func = BP_FUNC(bp);
4618 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4619 REG_WR(bp, BAR_CSTRORM_INTMEM +
4620 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4622 *((u32 *)sp_sb_data + i));
4625 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4627 int func = BP_FUNC(bp);
4628 struct hc_sp_status_block_data sp_sb_data;
4629 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4631 sp_sb_data.state = SB_DISABLED;
4632 sp_sb_data.p_func.vf_valid = false;
4634 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4636 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4637 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4638 CSTORM_SP_STATUS_BLOCK_SIZE);
4639 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4640 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4641 CSTORM_SP_SYNC_BLOCK_SIZE);
4647 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4648 int igu_sb_id, int igu_seg_id)
4650 hc_sm->igu_sb_id = igu_sb_id;
4651 hc_sm->igu_seg_id = igu_seg_id;
4652 hc_sm->timer_value = 0xFF;
4653 hc_sm->time_to_expire = 0xFFFFFFFF;
4656 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4657 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4661 struct hc_status_block_data_e2 sb_data_e2;
4662 struct hc_status_block_data_e1x sb_data_e1x;
4663 struct hc_status_block_sm *hc_sm_p;
4667 if (CHIP_INT_MODE_IS_BC(bp))
4668 igu_seg_id = HC_SEG_ACCESS_NORM;
4670 igu_seg_id = IGU_SEG_ACCESS_NORM;
4672 bnx2x_zero_fp_sb(bp, fw_sb_id);
4674 if (!CHIP_IS_E1x(bp)) {
4675 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4676 sb_data_e2.common.state = SB_ENABLED;
4677 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4678 sb_data_e2.common.p_func.vf_id = vfid;
4679 sb_data_e2.common.p_func.vf_valid = vf_valid;
4680 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4681 sb_data_e2.common.same_igu_sb_1b = true;
4682 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4683 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4684 hc_sm_p = sb_data_e2.common.state_machine;
4685 sb_data_p = (u32 *)&sb_data_e2;
4686 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4688 memset(&sb_data_e1x, 0,
4689 sizeof(struct hc_status_block_data_e1x));
4690 sb_data_e1x.common.state = SB_ENABLED;
4691 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4692 sb_data_e1x.common.p_func.vf_id = 0xff;
4693 sb_data_e1x.common.p_func.vf_valid = false;
4694 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4695 sb_data_e1x.common.same_igu_sb_1b = true;
4696 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4697 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4698 hc_sm_p = sb_data_e1x.common.state_machine;
4699 sb_data_p = (u32 *)&sb_data_e1x;
4700 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4703 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4704 igu_sb_id, igu_seg_id);
4705 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4706 igu_sb_id, igu_seg_id);
4708 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4710 /* write indecies to HW */
4711 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4714 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4715 u16 tx_usec, u16 rx_usec)
4717 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4719 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4723 static void bnx2x_init_def_sb(struct bnx2x *bp)
4725 struct host_sp_status_block *def_sb = bp->def_status_blk;
4726 dma_addr_t mapping = bp->def_status_blk_mapping;
4727 int igu_sp_sb_index;
4729 int port = BP_PORT(bp);
4730 int func = BP_FUNC(bp);
4734 struct hc_sp_status_block_data sp_sb_data;
4735 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4737 if (CHIP_INT_MODE_IS_BC(bp)) {
4738 igu_sp_sb_index = DEF_SB_IGU_ID;
4739 igu_seg_id = HC_SEG_ACCESS_DEF;
4741 igu_sp_sb_index = bp->igu_dsb_id;
4742 igu_seg_id = IGU_SEG_ACCESS_DEF;
4746 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4747 atten_status_block);
4748 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4752 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4753 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4754 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4756 /* take care of sig[0]..sig[4] */
4757 for (sindex = 0; sindex < 4; sindex++)
4758 bp->attn_group[index].sig[sindex] =
4759 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4761 if (!CHIP_IS_E1x(bp))
4763 * enable5 is separate from the rest of the registers,
4764 * and therefore the address skip is 4
4765 * and not 16 between the different groups
4767 bp->attn_group[index].sig[4] = REG_RD(bp,
4768 reg_offset + 0x10 + 0x4*index);
4770 bp->attn_group[index].sig[4] = 0;
4773 if (bp->common.int_block == INT_BLOCK_HC) {
4774 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4775 HC_REG_ATTN_MSG0_ADDR_L);
4777 REG_WR(bp, reg_offset, U64_LO(section));
4778 REG_WR(bp, reg_offset + 4, U64_HI(section));
4779 } else if (!CHIP_IS_E1x(bp)) {
4780 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4781 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4784 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4787 bnx2x_zero_sp_sb(bp);
4789 sp_sb_data.state = SB_ENABLED;
4790 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4791 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4792 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4793 sp_sb_data.igu_seg_id = igu_seg_id;
4794 sp_sb_data.p_func.pf_id = func;
4795 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4796 sp_sb_data.p_func.vf_id = 0xff;
4798 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4800 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4803 void bnx2x_update_coalesce(struct bnx2x *bp)
4807 for_each_eth_queue(bp, i)
4808 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4809 bp->tx_ticks, bp->rx_ticks);
4812 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4814 spin_lock_init(&bp->spq_lock);
4815 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4817 bp->spq_prod_idx = 0;
4818 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4819 bp->spq_prod_bd = bp->spq;
4820 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4823 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4826 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4827 union event_ring_elem *elem =
4828 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4830 elem->next_page.addr.hi =
4831 cpu_to_le32(U64_HI(bp->eq_mapping +
4832 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4833 elem->next_page.addr.lo =
4834 cpu_to_le32(U64_LO(bp->eq_mapping +
4835 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4838 bp->eq_prod = NUM_EQ_DESC;
4839 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4840 /* we want a warning message before it gets rought... */
4841 atomic_set(&bp->eq_spq_left,
4842 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4846 /* called with netif_addr_lock_bh() */
4847 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
4848 unsigned long rx_mode_flags,
4849 unsigned long rx_accept_flags,
4850 unsigned long tx_accept_flags,
4851 unsigned long ramrod_flags)
4853 struct bnx2x_rx_mode_ramrod_params ramrod_param;
4856 memset(&ramrod_param, 0, sizeof(ramrod_param));
4858 /* Prepare ramrod parameters */
4859 ramrod_param.cid = 0;
4860 ramrod_param.cl_id = cl_id;
4861 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
4862 ramrod_param.func_id = BP_FUNC(bp);
4864 ramrod_param.pstate = &bp->sp_state;
4865 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
4867 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
4868 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
4870 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4872 ramrod_param.ramrod_flags = ramrod_flags;
4873 ramrod_param.rx_mode_flags = rx_mode_flags;
4875 ramrod_param.rx_accept_flags = rx_accept_flags;
4876 ramrod_param.tx_accept_flags = tx_accept_flags;
4878 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
4880 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
4885 /* called with netif_addr_lock_bh() */
4886 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4888 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
4889 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
4894 /* Configure rx_mode of FCoE Queue */
4895 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
4898 switch (bp->rx_mode) {
4899 case BNX2X_RX_MODE_NONE:
4901 * 'drop all' supersedes any accept flags that may have been
4902 * passed to the function.
4905 case BNX2X_RX_MODE_NORMAL:
4906 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4907 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
4908 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4910 /* internal switching mode */
4911 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4912 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
4913 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4916 case BNX2X_RX_MODE_ALLMULTI:
4917 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4918 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4919 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4921 /* internal switching mode */
4922 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4923 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4924 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4927 case BNX2X_RX_MODE_PROMISC:
4928 /* According to deffinition of SI mode, iface in promisc mode
4929 * should receive matched and unmatched (in resolution of port)
4932 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
4933 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
4934 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
4935 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
4937 /* internal switching mode */
4938 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
4939 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
4942 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
4944 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
4948 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
4952 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
4953 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
4954 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
4957 __set_bit(RAMROD_RX, &ramrod_flags);
4958 __set_bit(RAMROD_TX, &ramrod_flags);
4960 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
4961 tx_accept_flags, ramrod_flags);
4964 static void bnx2x_init_internal_common(struct bnx2x *bp)
4970 * In switch independent mode, the TSTORM needs to accept
4971 * packets that failed classification, since approximate match
4972 * mac addresses aren't written to NIG LLH
4974 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4975 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4976 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
4977 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4978 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
4980 /* Zero this manually as its initialization is
4981 currently missing in the initTool */
4982 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4983 REG_WR(bp, BAR_USTRORM_INTMEM +
4984 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4985 if (!CHIP_IS_E1x(bp)) {
4986 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4987 CHIP_INT_MODE_IS_BC(bp) ?
4988 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4992 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4994 switch (load_code) {
4995 case FW_MSG_CODE_DRV_LOAD_COMMON:
4996 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4997 bnx2x_init_internal_common(bp);
5000 case FW_MSG_CODE_DRV_LOAD_PORT:
5004 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5005 /* internal memory per function is
5006 initialized inside bnx2x_pf_init */
5010 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5015 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5017 return fp->bp->igu_base_sb + fp->index + CNIC_CONTEXT_USE;
5020 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5022 return fp->bp->base_fw_ndsb + fp->index + CNIC_CONTEXT_USE;
5025 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5027 if (CHIP_IS_E1x(fp->bp))
5028 return BP_L_ID(fp->bp) + fp->index;
5029 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5030 return bnx2x_fp_igu_sb_id(fp);
5033 static void bnx2x_init_fp(struct bnx2x *bp, int fp_idx)
5035 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5036 unsigned long q_type = 0;
5039 fp->cl_id = bnx2x_fp_cl_id(fp);
5040 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5041 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5042 /* qZone id equals to FW (per path) client id */
5043 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5046 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5047 /* Setup SB indicies */
5048 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5049 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
5051 /* Configure Queue State object */
5052 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5053 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5054 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, fp->cid, BP_FUNC(bp),
5055 bnx2x_sp(bp, q_rdata), bnx2x_sp_mapping(bp, q_rdata),
5059 * Configure classification DBs: Always enable Tx switching
5061 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5063 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5064 "cl_id %d fw_sb %d igu_sb %d\n",
5065 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5067 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5068 fp->fw_sb_id, fp->igu_sb_id);
5070 bnx2x_update_fpsb_idx(fp);
5073 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5077 for_each_eth_queue(bp, i)
5078 bnx2x_init_fp(bp, i);
5081 bnx2x_init_fcoe_fp(bp);
5083 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5084 BNX2X_VF_ID_INVALID, false,
5085 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5089 /* Initialize MOD_ABS interrupts */
5090 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5091 bp->common.shmem_base, bp->common.shmem2_base,
5093 /* ensure status block indices were read */
5096 bnx2x_init_def_sb(bp);
5097 bnx2x_update_dsb_idx(bp);
5098 bnx2x_init_rx_rings(bp);
5099 bnx2x_init_tx_rings(bp);
5100 bnx2x_init_sp_ring(bp);
5101 bnx2x_init_eq_ring(bp);
5102 bnx2x_init_internal(bp, load_code);
5104 bnx2x_stats_init(bp);
5106 /* flush all before enabling interrupts */
5110 bnx2x_int_enable(bp);
5112 /* Check for SPIO5 */
5113 bnx2x_attn_int_deasserted0(bp,
5114 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5115 AEU_INPUTS_ATTN_BITS_SPIO5);
5118 /* end of nic init */
5121 * gzip service functions
5124 static int bnx2x_gunzip_init(struct bnx2x *bp)
5126 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5127 &bp->gunzip_mapping, GFP_KERNEL);
5128 if (bp->gunzip_buf == NULL)
5131 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5132 if (bp->strm == NULL)
5135 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
5137 if (bp->strm->workspace == NULL)
5147 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5148 bp->gunzip_mapping);
5149 bp->gunzip_buf = NULL;
5152 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5153 " un-compression\n");
5157 static void bnx2x_gunzip_end(struct bnx2x *bp)
5160 kfree(bp->strm->workspace);
5165 if (bp->gunzip_buf) {
5166 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5167 bp->gunzip_mapping);
5168 bp->gunzip_buf = NULL;
5172 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5176 /* check gzip header */
5177 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5178 BNX2X_ERR("Bad gzip header\n");
5186 if (zbuf[3] & FNAME)
5187 while ((zbuf[n++] != 0) && (n < len));
5189 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5190 bp->strm->avail_in = len - n;
5191 bp->strm->next_out = bp->gunzip_buf;
5192 bp->strm->avail_out = FW_BUF_SIZE;
5194 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5198 rc = zlib_inflate(bp->strm, Z_FINISH);
5199 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5200 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5203 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5204 if (bp->gunzip_outlen & 0x3)
5205 netdev_err(bp->dev, "Firmware decompression error:"
5206 " gunzip_outlen (%d) not aligned\n",
5208 bp->gunzip_outlen >>= 2;
5210 zlib_inflateEnd(bp->strm);
5212 if (rc == Z_STREAM_END)
5218 /* nic load/unload */
5221 * General service functions
5224 /* send a NIG loopback debug packet */
5225 static void bnx2x_lb_pckt(struct bnx2x *bp)
5229 /* Ethernet source and destination addresses */
5230 wb_write[0] = 0x55555555;
5231 wb_write[1] = 0x55555555;
5232 wb_write[2] = 0x20; /* SOP */
5233 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5235 /* NON-IP protocol */
5236 wb_write[0] = 0x09000000;
5237 wb_write[1] = 0x55555555;
5238 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5239 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5242 /* some of the internal memories
5243 * are not directly readable from the driver
5244 * to test them we send debug packets
5246 static int bnx2x_int_mem_test(struct bnx2x *bp)
5252 if (CHIP_REV_IS_FPGA(bp))
5254 else if (CHIP_REV_IS_EMUL(bp))
5259 /* Disable inputs of parser neighbor blocks */
5260 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5261 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5262 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5263 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5265 /* Write 0 to parser credits for CFC search request */
5266 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5268 /* send Ethernet packet */
5271 /* TODO do i reset NIG statistic? */
5272 /* Wait until NIG register shows 1 packet of size 0x10 */
5273 count = 1000 * factor;
5276 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5277 val = *bnx2x_sp(bp, wb_data[0]);
5285 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5289 /* Wait until PRS register shows 1 packet */
5290 count = 1000 * factor;
5292 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5300 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5304 /* Reset and init BRB, PRS */
5305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5307 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5309 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5310 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5312 DP(NETIF_MSG_HW, "part2\n");
5314 /* Disable inputs of parser neighbor blocks */
5315 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5316 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5317 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5318 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5320 /* Write 0 to parser credits for CFC search request */
5321 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5323 /* send 10 Ethernet packets */
5324 for (i = 0; i < 10; i++)
5327 /* Wait until NIG register shows 10 + 1
5328 packets of size 11*0x10 = 0xb0 */
5329 count = 1000 * factor;
5332 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5333 val = *bnx2x_sp(bp, wb_data[0]);
5341 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5345 /* Wait until PRS register shows 2 packets */
5346 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5348 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5350 /* Write 1 to parser credits for CFC search request */
5351 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5353 /* Wait until PRS register shows 3 packets */
5354 msleep(10 * factor);
5355 /* Wait until NIG register shows 1 packet of size 0x10 */
5356 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5358 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5360 /* clear NIG EOP FIFO */
5361 for (i = 0; i < 11; i++)
5362 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5363 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5365 BNX2X_ERR("clear of NIG failed\n");
5369 /* Reset and init BRB, PRS, NIG */
5370 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5372 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5374 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5375 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5378 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5381 /* Enable inputs of parser neighbor blocks */
5382 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5383 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5384 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5385 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5387 DP(NETIF_MSG_HW, "done\n");
5392 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5394 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5395 if (!CHIP_IS_E1x(bp))
5396 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5398 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5399 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5400 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5402 * mask read length error interrupts in brb for parser
5403 * (parsing unit and 'checksum and crc' unit)
5404 * these errors are legal (PU reads fixed length and CAC can cause
5405 * read length error on truncated packets)
5407 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5408 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5409 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5410 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5411 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5412 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5413 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5414 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5415 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5416 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5417 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5418 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5419 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5420 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5421 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5422 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5423 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5424 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5425 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5427 if (CHIP_REV_IS_FPGA(bp))
5428 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5429 else if (!CHIP_IS_E1x(bp))
5430 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5431 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5432 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5433 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5434 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5435 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5437 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5438 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5439 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5440 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5441 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5443 if (!CHIP_IS_E1x(bp))
5444 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5445 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5447 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5448 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5449 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5450 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5453 static void bnx2x_reset_common(struct bnx2x *bp)
5458 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5461 if (CHIP_IS_E3(bp)) {
5462 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5463 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5466 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5469 static void bnx2x_setup_dmae(struct bnx2x *bp)
5472 spin_lock_init(&bp->dmae_lock);
5475 static void bnx2x_init_pxp(struct bnx2x *bp)
5478 int r_order, w_order;
5480 pci_read_config_word(bp->pdev,
5481 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
5482 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5483 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5485 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5487 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5491 bnx2x_init_pxp_arb(bp, r_order, w_order);
5494 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5504 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5505 SHARED_HW_CFG_FAN_FAILURE_MASK;
5507 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5511 * The fan failure mechanism is usually related to the PHY type since
5512 * the power consumption of the board is affected by the PHY. Currently,
5513 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5515 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5516 for (port = PORT_0; port < PORT_MAX; port++) {
5518 bnx2x_fan_failure_det_req(
5520 bp->common.shmem_base,
5521 bp->common.shmem2_base,
5525 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5527 if (is_required == 0)
5530 /* Fan failure is indicated by SPIO 5 */
5531 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5532 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5534 /* set to active low mode */
5535 val = REG_RD(bp, MISC_REG_SPIO_INT);
5536 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5537 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5538 REG_WR(bp, MISC_REG_SPIO_INT, val);
5540 /* enable interrupt to signal the IGU */
5541 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5542 val |= (1 << MISC_REGISTERS_SPIO_5);
5543 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5546 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5552 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5555 switch (BP_ABS_FUNC(bp)) {
5557 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5560 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5563 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5566 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5569 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5572 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5575 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5578 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5584 REG_WR(bp, offset, pretend_func_num);
5586 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5589 void bnx2x_pf_disable(struct bnx2x *bp)
5591 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5592 val &= ~IGU_PF_CONF_FUNC_EN;
5594 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5595 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5596 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5599 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5601 u32 shmem_base[2], shmem2_base[2];
5602 shmem_base[0] = bp->common.shmem_base;
5603 shmem2_base[0] = bp->common.shmem2_base;
5604 if (!CHIP_IS_E1x(bp)) {
5606 SHMEM2_RD(bp, other_shmem_base_addr);
5608 SHMEM2_RD(bp, other_shmem2_base_addr);
5610 bnx2x_acquire_phy_lock(bp);
5611 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5612 bp->common.chip_id);
5613 bnx2x_release_phy_lock(bp);
5617 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5619 * @bp: driver handle
5621 static int bnx2x_init_hw_common(struct bnx2x *bp)
5625 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5627 bnx2x_reset_common(bp);
5628 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5631 if (CHIP_IS_E3(bp)) {
5632 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5633 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5635 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5637 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5639 if (!CHIP_IS_E1x(bp)) {
5643 * 4-port mode or 2-port mode we need to turn of master-enable
5644 * for everyone, after that, turn it back on for self.
5645 * so, we disregard multi-function or not, and always disable
5646 * for all functions on the given path, this means 0,2,4,6 for
5647 * path 0 and 1,3,5,7 for path 1
5649 for (abs_func_id = BP_PATH(bp);
5650 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5651 if (abs_func_id == BP_ABS_FUNC(bp)) {
5653 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5658 bnx2x_pretend_func(bp, abs_func_id);
5659 /* clear pf enable */
5660 bnx2x_pf_disable(bp);
5661 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5665 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5666 if (CHIP_IS_E1(bp)) {
5667 /* enable HW interrupt from PXP on USDM overflow
5668 bit 16 on INT_MASK_0 */
5669 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5672 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5676 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5677 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5678 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5679 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5680 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5681 /* make sure this value is 0 */
5682 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5684 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5685 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5686 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5687 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5688 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5691 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5693 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5694 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5696 /* let the HW do it's magic ... */
5698 /* finish PXP init */
5699 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5701 BNX2X_ERR("PXP2 CFG failed\n");
5704 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5706 BNX2X_ERR("PXP2 RD_INIT failed\n");
5710 /* Timers bug workaround E2 only. We need to set the entire ILT to
5711 * have entries with value "0" and valid bit on.
5712 * This needs to be done by the first PF that is loaded in a path
5713 * (i.e. common phase)
5715 if (!CHIP_IS_E1x(bp)) {
5716 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5717 * (i.e. vnic3) to start even if it is marked as "scan-off".
5718 * This occurs when a different function (func2,3) is being marked
5719 * as "scan-off". Real-life scenario for example: if a driver is being
5720 * load-unloaded while func6,7 are down. This will cause the timer to access
5721 * the ilt, translate to a logical address and send a request to read/write.
5722 * Since the ilt for the function that is down is not valid, this will cause
5723 * a translation error which is unrecoverable.
5724 * The Workaround is intended to make sure that when this happens nothing fatal
5725 * will occur. The workaround:
5726 * 1. First PF driver which loads on a path will:
5727 * a. After taking the chip out of reset, by using pretend,
5728 * it will write "0" to the following registers of
5730 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5731 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5732 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5733 * And for itself it will write '1' to
5734 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5735 * dmae-operations (writing to pram for example.)
5736 * note: can be done for only function 6,7 but cleaner this
5738 * b. Write zero+valid to the entire ILT.
5739 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5740 * VNIC3 (of that port). The range allocated will be the
5741 * entire ILT. This is needed to prevent ILT range error.
5742 * 2. Any PF driver load flow:
5743 * a. ILT update with the physical addresses of the allocated
5745 * b. Wait 20msec. - note that this timeout is needed to make
5746 * sure there are no requests in one of the PXP internal
5747 * queues with "old" ILT addresses.
5748 * c. PF enable in the PGLC.
5749 * d. Clear the was_error of the PF in the PGLC. (could have
5750 * occured while driver was down)
5751 * e. PF enable in the CFC (WEAK + STRONG)
5752 * f. Timers scan enable
5753 * 3. PF driver unload flow:
5754 * a. Clear the Timers scan_en.
5755 * b. Polling for scan_on=0 for that PF.
5756 * c. Clear the PF enable bit in the PXP.
5757 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5758 * e. Write zero+valid to all ILT entries (The valid bit must
5760 * f. If this is VNIC 3 of a port then also init
5761 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5762 * to the last enrty in the ILT.
5765 * Currently the PF error in the PGLC is non recoverable.
5766 * In the future the there will be a recovery routine for this error.
5767 * Currently attention is masked.
5768 * Having an MCP lock on the load/unload process does not guarantee that
5769 * there is no Timer disable during Func6/7 enable. This is because the
5770 * Timers scan is currently being cleared by the MCP on FLR.
5771 * Step 2.d can be done only for PF6/7 and the driver can also check if
5772 * there is error before clearing it. But the flow above is simpler and
5774 * All ILT entries are written by zero+valid and not just PF6/7
5775 * ILT entries since in the future the ILT entries allocation for
5776 * PF-s might be dynamic.
5778 struct ilt_client_info ilt_cli;
5779 struct bnx2x_ilt ilt;
5780 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5781 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5783 /* initialize dummy TM client */
5785 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5786 ilt_cli.client_num = ILT_CLIENT_TM;
5788 /* Step 1: set zeroes to all ilt page entries with valid bit on
5789 * Step 2: set the timers first/last ilt entry to point
5790 * to the entire range to prevent ILT range error for 3rd/4th
5791 * vnic (this code assumes existance of the vnic)
5793 * both steps performed by call to bnx2x_ilt_client_init_op()
5794 * with dummy TM client
5796 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5797 * and his brother are split registers
5799 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5800 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5801 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5803 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5804 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5805 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5809 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5810 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5812 if (!CHIP_IS_E1x(bp)) {
5813 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5814 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5815 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
5817 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
5819 /* let the HW do it's magic ... */
5822 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5823 } while (factor-- && (val != 1));
5826 BNX2X_ERR("ATC_INIT failed\n");
5831 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
5833 /* clean the DMAE memory */
5835 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
5837 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
5839 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
5841 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
5843 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
5845 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5846 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5847 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5848 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5850 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
5853 /* QM queues pointers table */
5854 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5856 /* soft reset pulse */
5857 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5858 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5861 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
5864 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
5865 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5866 if (!CHIP_REV_IS_SLOW(bp))
5867 /* enable hw interrupt from doorbell Q */
5868 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5870 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5872 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5873 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5875 if (!CHIP_IS_E1(bp))
5876 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
5878 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
5879 /* Bit-map indicating which L2 hdrs may appear
5880 * after the basic Ethernet header
5882 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
5883 bp->path_has_ovlan ? 7 : 6);
5885 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
5886 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
5887 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
5888 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
5890 if (!CHIP_IS_E1x(bp)) {
5891 /* reset VFC memories */
5892 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5893 VFC_MEMORIES_RST_REG_CAM_RST |
5894 VFC_MEMORIES_RST_REG_RAM_RST);
5895 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
5896 VFC_MEMORIES_RST_REG_CAM_RST |
5897 VFC_MEMORIES_RST_REG_RAM_RST);
5902 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
5903 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
5904 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
5905 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
5908 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5910 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5913 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
5914 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
5915 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
5917 if (!CHIP_IS_E1x(bp))
5918 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
5919 bp->path_has_ovlan ? 7 : 6);
5921 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5923 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
5926 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5927 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5928 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5929 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5930 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5931 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5932 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5933 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5934 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5935 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5937 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5939 if (sizeof(union cdu_context) != 1024)
5940 /* we currently assume that a context is 1024 bytes */
5941 dev_alert(&bp->pdev->dev, "please adjust the size "
5942 "of cdu_context(%ld)\n",
5943 (long)sizeof(union cdu_context));
5945 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
5946 val = (4 << 24) + (0 << 12) + 1024;
5947 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5949 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
5950 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5951 /* enable context validation interrupt from CFC */
5952 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5954 /* set the thresholds to prevent CFC/CDU race */
5955 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5957 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
5959 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
5960 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5962 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
5963 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
5965 /* Reset PCIE errors for debug */
5966 REG_WR(bp, 0x2814, 0xffffffff);
5967 REG_WR(bp, 0x3820, 0xffffffff);
5969 if (!CHIP_IS_E1x(bp)) {
5970 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5971 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5972 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5973 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5974 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5975 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5976 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5977 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5978 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5979 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5980 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5983 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
5984 if (!CHIP_IS_E1(bp)) {
5985 /* in E3 this done in per-port section */
5986 if (!CHIP_IS_E3(bp))
5987 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5989 if (CHIP_IS_E1H(bp))
5990 /* not applicable for E2 (and above ...) */
5991 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5993 if (CHIP_REV_IS_SLOW(bp))
5996 /* finish CFC init */
5997 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5999 BNX2X_ERR("CFC LL_INIT failed\n");
6002 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6004 BNX2X_ERR("CFC AC_INIT failed\n");
6007 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6009 BNX2X_ERR("CFC CAM_INIT failed\n");
6012 REG_WR(bp, CFC_REG_DEBUG0, 0);
6014 if (CHIP_IS_E1(bp)) {
6015 /* read NIG statistic
6016 to see if this is our first up since powerup */
6017 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6018 val = *bnx2x_sp(bp, wb_data[0]);
6020 /* do internal memory self test */
6021 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6022 BNX2X_ERR("internal mem self test failed\n");
6027 bnx2x_setup_fan_failure_detection(bp);
6029 /* clear PXP2 attentions */
6030 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6032 bnx2x_enable_blocks_attention(bp);
6033 bnx2x_enable_blocks_parity(bp);
6035 if (!BP_NOMCP(bp)) {
6036 if (CHIP_IS_E1x(bp))
6037 bnx2x__common_init_phy(bp);
6039 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6045 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6047 * @bp: driver handle
6049 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6051 int rc = bnx2x_init_hw_common(bp);
6056 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6058 bnx2x__common_init_phy(bp);
6063 static int bnx2x_init_hw_port(struct bnx2x *bp)
6065 int port = BP_PORT(bp);
6066 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6070 bnx2x__link_reset(bp);
6072 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6074 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6076 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6077 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6078 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6080 /* Timers bug workaround: disables the pf_master bit in pglue at
6081 * common phase, we need to enable it here before any dmae access are
6082 * attempted. Therefore we manually added the enable-master to the
6083 * port phase (it also happens in the function phase)
6085 if (!CHIP_IS_E1x(bp))
6086 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6088 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6089 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6090 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6091 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6093 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6094 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6095 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6096 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6098 /* QM cid (connection) count */
6099 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6102 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6103 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6104 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6107 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6109 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6110 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6113 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6114 else if (bp->dev->mtu > 4096) {
6115 if (bp->flags & ONE_PORT_FLAG)
6119 /* (24*1024 + val*4)/256 */
6120 low = 96 + (val/64) +
6121 ((val % 64) ? 1 : 0);
6124 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6125 high = low + 56; /* 14*1024/256 */
6126 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6127 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6130 if (CHIP_MODE_IS_4_PORT(bp))
6131 REG_WR(bp, (BP_PORT(bp) ?
6132 BRB1_REG_MAC_GUARANTIED_1 :
6133 BRB1_REG_MAC_GUARANTIED_0), 40);
6136 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6137 if (CHIP_IS_E3B0(bp))
6138 /* Ovlan exists only if we are in multi-function +
6139 * switch-dependent mode, in switch-independent there
6140 * is no ovlan headers
6142 REG_WR(bp, BP_PORT(bp) ?
6143 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6144 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6145 (bp->path_has_ovlan ? 7 : 6));
6147 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6148 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6149 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6150 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6152 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6153 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6154 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6155 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6157 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6158 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6160 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6162 if (CHIP_IS_E1x(bp)) {
6163 /* configure PBF to work without PAUSE mtu 9000 */
6164 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6166 /* update threshold */
6167 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6168 /* update init credit */
6169 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6172 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6174 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6178 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6180 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6181 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6183 if (CHIP_IS_E1(bp)) {
6184 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6185 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6187 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6189 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6191 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6192 /* init aeu_mask_attn_func_0/1:
6193 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6194 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6195 * bits 4-7 are used for "per vn group attention" */
6196 val = IS_MF(bp) ? 0xF7 : 0x7;
6197 /* Enable DCBX attention for all but E1 */
6198 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6199 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6201 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6203 if (!CHIP_IS_E1x(bp)) {
6204 /* Bit-map indicating which L2 hdrs may appear after the
6205 * basic Ethernet header
6207 REG_WR(bp, BP_PORT(bp) ?
6208 NIG_REG_P1_HDRS_AFTER_BASIC :
6209 NIG_REG_P0_HDRS_AFTER_BASIC,
6210 IS_MF_SD(bp) ? 7 : 6);
6213 REG_WR(bp, BP_PORT(bp) ?
6214 NIG_REG_LLH1_MF_MODE :
6215 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6217 if (!CHIP_IS_E3(bp))
6218 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6220 if (!CHIP_IS_E1(bp)) {
6221 /* 0x2 disable mf_ov, 0x1 enable */
6222 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6223 (IS_MF_SD(bp) ? 0x1 : 0x2));
6225 if (!CHIP_IS_E1x(bp)) {
6227 switch (bp->mf_mode) {
6228 case MULTI_FUNCTION_SD:
6231 case MULTI_FUNCTION_SI:
6236 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6237 NIG_REG_LLH0_CLS_TYPE), val);
6240 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6241 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6242 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6247 /* If SPIO5 is set to generate interrupts, enable it for this port */
6248 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6249 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6250 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6251 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6252 val = REG_RD(bp, reg_addr);
6253 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6254 REG_WR(bp, reg_addr, val);
6260 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6265 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6267 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6269 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6272 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6274 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6277 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6279 u32 i, base = FUNC_ILT_BASE(func);
6280 for (i = base; i < base + ILT_PER_FUNC; i++)
6281 bnx2x_ilt_wr(bp, i, 0);
6284 static int bnx2x_init_hw_func(struct bnx2x *bp)
6286 int port = BP_PORT(bp);
6287 int func = BP_FUNC(bp);
6288 int init_phase = PHASE_PF0 + func;
6289 struct bnx2x_ilt *ilt = BP_ILT(bp);
6292 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6293 int i, main_mem_width;
6295 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6297 /* FLR cleanup - hmmm */
6298 if (!CHIP_IS_E1x(bp))
6299 bnx2x_pf_flr_clnup(bp);
6301 /* set MSI reconfigure capability */
6302 if (bp->common.int_block == INT_BLOCK_HC) {
6303 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6304 val = REG_RD(bp, addr);
6305 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6306 REG_WR(bp, addr, val);
6309 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6310 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6313 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6315 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6316 ilt->lines[cdu_ilt_start + i].page =
6317 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6318 ilt->lines[cdu_ilt_start + i].page_mapping =
6319 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6320 /* cdu ilt pages are allocated manually so there's no need to
6323 bnx2x_ilt_init_op(bp, INITOP_SET);
6326 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6328 /* T1 hash bits value determines the T1 number of entries */
6329 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6334 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6335 #endif /* BCM_CNIC */
6337 if (!CHIP_IS_E1x(bp)) {
6338 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6340 /* Turn on a single ISR mode in IGU if driver is going to use
6343 if (!(bp->flags & USING_MSIX_FLAG))
6344 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6346 * Timers workaround bug: function init part.
6347 * Need to wait 20msec after initializing ILT,
6348 * needed to make sure there are no requests in
6349 * one of the PXP internal queues with "old" ILT addresses
6353 * Master enable - Due to WB DMAE writes performed before this
6354 * register is re-initialized as part of the regular function
6357 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6358 /* Enable the function in IGU */
6359 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6364 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6366 if (!CHIP_IS_E1x(bp))
6367 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6369 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6370 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6371 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6372 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6373 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6374 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6375 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6376 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6377 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6378 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6379 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6380 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6381 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6383 if (!CHIP_IS_E1x(bp))
6384 REG_WR(bp, QM_REG_PF_EN, 1);
6386 if (!CHIP_IS_E1x(bp)) {
6387 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6388 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6389 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6390 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6392 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6394 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6395 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6396 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6397 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6398 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6399 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6400 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6401 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6402 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6403 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6404 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6405 if (!CHIP_IS_E1x(bp))
6406 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6408 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6410 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6412 if (!CHIP_IS_E1x(bp))
6413 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6416 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6417 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6420 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6422 /* HC init per function */
6423 if (bp->common.int_block == INT_BLOCK_HC) {
6424 if (CHIP_IS_E1H(bp)) {
6425 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6427 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6428 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6430 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6433 int num_segs, sb_idx, prod_offset;
6435 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6437 if (!CHIP_IS_E1x(bp)) {
6438 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6439 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6442 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6444 if (!CHIP_IS_E1x(bp)) {
6448 * E2 mode: address 0-135 match to the mapping memory;
6449 * 136 - PF0 default prod; 137 - PF1 default prod;
6450 * 138 - PF2 default prod; 139 - PF3 default prod;
6451 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6452 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6455 * E1.5 mode - In backward compatible mode;
6456 * for non default SB; each even line in the memory
6457 * holds the U producer and each odd line hold
6458 * the C producer. The first 128 producers are for
6459 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6460 * producers are for the DSB for each PF.
6461 * Each PF has five segments: (the order inside each
6462 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6463 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6464 * 144-147 attn prods;
6466 /* non-default-status-blocks */
6467 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6468 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6469 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6470 prod_offset = (bp->igu_base_sb + sb_idx) *
6473 for (i = 0; i < num_segs; i++) {
6474 addr = IGU_REG_PROD_CONS_MEMORY +
6475 (prod_offset + i) * 4;
6476 REG_WR(bp, addr, 0);
6478 /* send consumer update with value 0 */
6479 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6480 USTORM_ID, 0, IGU_INT_NOP, 1);
6481 bnx2x_igu_clear_sb(bp,
6482 bp->igu_base_sb + sb_idx);
6485 /* default-status-blocks */
6486 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6487 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6489 if (CHIP_MODE_IS_4_PORT(bp))
6490 dsb_idx = BP_FUNC(bp);
6492 dsb_idx = BP_E1HVN(bp);
6494 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6495 IGU_BC_BASE_DSB_PROD + dsb_idx :
6496 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6498 for (i = 0; i < (num_segs * E1HVN_MAX);
6500 addr = IGU_REG_PROD_CONS_MEMORY +
6501 (prod_offset + i)*4;
6502 REG_WR(bp, addr, 0);
6504 /* send consumer update with 0 */
6505 if (CHIP_INT_MODE_IS_BC(bp)) {
6506 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6507 USTORM_ID, 0, IGU_INT_NOP, 1);
6508 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6509 CSTORM_ID, 0, IGU_INT_NOP, 1);
6510 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6511 XSTORM_ID, 0, IGU_INT_NOP, 1);
6512 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6513 TSTORM_ID, 0, IGU_INT_NOP, 1);
6514 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6515 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6517 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6518 USTORM_ID, 0, IGU_INT_NOP, 1);
6519 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6520 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6522 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6524 /* !!! these should become driver const once
6525 rf-tool supports split-68 const */
6526 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6527 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6528 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6529 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6530 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6531 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6535 /* Reset PCIE errors for debug */
6536 REG_WR(bp, 0x2114, 0xffffffff);
6537 REG_WR(bp, 0x2120, 0xffffffff);
6539 if (CHIP_IS_E1x(bp)) {
6540 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6541 main_mem_base = HC_REG_MAIN_MEMORY +
6542 BP_PORT(bp) * (main_mem_size * 4);
6543 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6546 val = REG_RD(bp, main_mem_prty_clr);
6548 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6550 "function init (0x%x)!\n", val);
6552 /* Clear "false" parity errors in MSI-X table */
6553 for (i = main_mem_base;
6554 i < main_mem_base + main_mem_size * 4;
6555 i += main_mem_width) {
6556 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6557 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6558 i, main_mem_width / 4);
6560 /* Clear HC parity attention */
6561 REG_RD(bp, main_mem_prty_clr);
6564 #ifdef BNX2X_STOP_ON_ERROR
6565 /* Enable STORMs SP logging */
6566 REG_WR8(bp, BAR_USTRORM_INTMEM +
6567 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6568 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6569 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6570 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6571 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6572 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6573 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6576 bnx2x_phy_probe(&bp->link_params);
6582 void bnx2x_free_mem(struct bnx2x *bp)
6585 bnx2x_free_fp_mem(bp);
6586 /* end of fastpath */
6588 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6589 sizeof(struct host_sp_status_block));
6591 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6592 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6594 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6595 sizeof(struct bnx2x_slowpath));
6597 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6600 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6602 BNX2X_FREE(bp->ilt->lines);
6605 if (!CHIP_IS_E1x(bp))
6606 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6607 sizeof(struct host_hc_status_block_e2));
6609 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6610 sizeof(struct host_hc_status_block_e1x));
6612 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6615 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6617 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6618 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6621 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6625 /* number of eth_queues */
6626 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6628 /* Total number of FW statistics requests =
6629 * 1 for port stats + 1 for PF stats + num_eth_queues */
6630 bp->fw_stats_num = 2 + num_queue_stats;
6633 /* Request is built from stats_query_header and an array of
6634 * stats_query_cmd_group each of which contains
6635 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6636 * configured in the stats_query_header.
6638 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6639 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6641 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6642 num_groups * sizeof(struct stats_query_cmd_group);
6644 /* Data for statistics requests + stats_conter
6646 * stats_counter holds per-STORM counters that are incremented
6647 * when STORM has finished with the current request.
6649 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6650 sizeof(struct per_pf_stats) +
6651 sizeof(struct per_queue_stats) * num_queue_stats +
6652 sizeof(struct stats_counter);
6654 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6655 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6658 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6659 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6661 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6662 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6664 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6665 bp->fw_stats_req_sz;
6669 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6670 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6675 int bnx2x_alloc_mem(struct bnx2x *bp)
6678 if (!CHIP_IS_E1x(bp))
6679 /* size = the status block + ramrod buffers */
6680 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6681 sizeof(struct host_hc_status_block_e2));
6683 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6684 sizeof(struct host_hc_status_block_e1x));
6686 /* allocate searcher T2 table */
6687 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6691 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6692 sizeof(struct host_sp_status_block));
6694 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6695 sizeof(struct bnx2x_slowpath));
6697 /* Allocated memory for FW statistics */
6698 if (bnx2x_alloc_fw_stats_mem(bp))
6701 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6703 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6706 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6708 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6711 /* Slow path ring */
6712 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6715 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6716 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6720 /* need to be done at the end, since it's self adjusting to amount
6721 * of memory available for RSS queues
6723 if (bnx2x_alloc_fp_mem(bp))
6733 * Init service functions
6736 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6737 struct bnx2x_vlan_mac_obj *obj, bool set,
6738 int mac_type, unsigned long *ramrod_flags)
6741 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6743 memset(&ramrod_param, 0, sizeof(ramrod_param));
6745 /* Fill general parameters */
6746 ramrod_param.vlan_mac_obj = obj;
6747 ramrod_param.ramrod_flags = *ramrod_flags;
6749 /* Fill a user request section if needed */
6750 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6751 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6753 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6755 /* Set the command: ADD or DEL */
6757 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6759 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6762 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6764 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6768 int bnx2x_del_all_macs(struct bnx2x *bp,
6769 struct bnx2x_vlan_mac_obj *mac_obj,
6770 int mac_type, bool wait_for_comp)
6773 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6775 /* Wait for completion of requested */
6777 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6779 /* Set the mac type of addresses we want to clear */
6780 __set_bit(mac_type, &vlan_mac_flags);
6782 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6784 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6789 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6791 unsigned long ramrod_flags = 0;
6793 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
6795 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6796 /* Eth MAC is set on RSS leading client (fp[0]) */
6797 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
6798 BNX2X_ETH_MAC, &ramrod_flags);
6801 int bnx2x_setup_leading(struct bnx2x *bp)
6803 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
6807 * bnx2x_set_int_mode - configure interrupt mode
6809 * @bp: driver handle
6811 * In case of MSI-X it will also try to enable MSI-X.
6813 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6817 bnx2x_enable_msi(bp);
6818 /* falling through... */
6820 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6821 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6824 /* Set number of queues according to bp->multi_mode value */
6825 bnx2x_set_num_queues(bp);
6827 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6830 /* if we can't use MSI-X we only need one fp,
6831 * so try to enable MSI-X with the requested number of fp's
6832 * and fallback to MSI or legacy INTx with one fp
6834 if (bnx2x_enable_msix(bp)) {
6835 /* failed to enable MSI-X */
6838 "Multi requested but failed to "
6839 "enable MSI-X (%d), "
6840 "set number of queues to %d\n",
6842 1 + NONE_ETH_CONTEXT_USE);
6843 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6845 /* Try to enable MSI */
6846 if (!(bp->flags & DISABLE_MSI_FLAG))
6847 bnx2x_enable_msi(bp);
6853 /* must be called prioir to any HW initializations */
6854 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6856 return L2_ILT_LINES(bp);
6859 void bnx2x_ilt_set_info(struct bnx2x *bp)
6861 struct ilt_client_info *ilt_client;
6862 struct bnx2x_ilt *ilt = BP_ILT(bp);
6865 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6866 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6869 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6870 ilt_client->client_num = ILT_CLIENT_CDU;
6871 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6872 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6873 ilt_client->start = line;
6874 line += bnx2x_cid_ilt_lines(bp);
6876 line += CNIC_ILT_LINES;
6878 ilt_client->end = line - 1;
6880 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6881 "flags 0x%x, hw psz %d\n",
6884 ilt_client->page_size,
6886 ilog2(ilt_client->page_size >> 12));
6889 if (QM_INIT(bp->qm_cid_count)) {
6890 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6891 ilt_client->client_num = ILT_CLIENT_QM;
6892 ilt_client->page_size = QM_ILT_PAGE_SZ;
6893 ilt_client->flags = 0;
6894 ilt_client->start = line;
6896 /* 4 bytes for each cid */
6897 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6900 ilt_client->end = line - 1;
6902 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6903 "flags 0x%x, hw psz %d\n",
6906 ilt_client->page_size,
6908 ilog2(ilt_client->page_size >> 12));
6912 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6914 ilt_client->client_num = ILT_CLIENT_SRC;
6915 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6916 ilt_client->flags = 0;
6917 ilt_client->start = line;
6918 line += SRC_ILT_LINES;
6919 ilt_client->end = line - 1;
6921 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6922 "flags 0x%x, hw psz %d\n",
6925 ilt_client->page_size,
6927 ilog2(ilt_client->page_size >> 12));
6930 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6934 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6936 ilt_client->client_num = ILT_CLIENT_TM;
6937 ilt_client->page_size = TM_ILT_PAGE_SZ;
6938 ilt_client->flags = 0;
6939 ilt_client->start = line;
6940 line += TM_ILT_LINES;
6941 ilt_client->end = line - 1;
6943 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6944 "flags 0x%x, hw psz %d\n",
6947 ilt_client->page_size,
6949 ilog2(ilt_client->page_size >> 12));
6952 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6954 BUG_ON(line > ILT_MAX_LINES);
6958 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
6960 * @bp: driver handle
6961 * @fp: pointer to fastpath
6962 * @init_params: pointer to parameters structure
6964 * parameters configured:
6965 * - HC configuration
6966 * - Queue's CDU context
6968 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
6969 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
6971 /* FCoE Queue uses Default SB, thus has no HC capabilities */
6972 if (!IS_FCOE_FP(fp)) {
6973 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
6974 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
6976 /* If HC is supporterd, enable host coalescing in the transition
6979 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
6980 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
6983 init_params->rx.hc_rate = bp->rx_ticks ?
6984 (1000000 / bp->rx_ticks) : 0;
6985 init_params->tx.hc_rate = bp->tx_ticks ?
6986 (1000000 / bp->tx_ticks) : 0;
6989 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
6993 * CQ index among the SB indices: FCoE clients uses the default
6994 * SB, therefore it's different.
6996 init_params->rx.sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
6997 init_params->tx.sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
7000 init_params->cxt = &bp->context.vcxt[fp->cid].eth;
7004 * bnx2x_setup_queue - setup queue
7006 * @bp: driver handle
7007 * @fp: pointer to fastpath
7008 * @leading: is leading
7010 * This function performs 2 steps in a Queue state machine
7011 * actually: 1) RESET->INIT 2) INIT->SETUP
7014 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7017 struct bnx2x_queue_state_params q_params = {0};
7018 struct bnx2x_queue_setup_params *setup_params =
7019 &q_params.params.setup;
7022 /* reset IGU state skip FCoE L2 queue */
7023 if (!IS_FCOE_FP(fp))
7024 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7027 q_params.q_obj = &fp->q_obj;
7028 /* We want to wait for completion in this context */
7029 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7031 /* Prepare the INIT parameters */
7032 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7034 /* Set the command */
7035 q_params.cmd = BNX2X_Q_CMD_INIT;
7037 /* Change the state to INIT */
7038 rc = bnx2x_queue_state_change(bp, &q_params);
7040 BNX2X_ERR("Queue INIT failed\n");
7044 /* Now move the Queue to the SETUP state... */
7045 memset(setup_params, 0, sizeof(*setup_params));
7047 /* Set QUEUE flags */
7048 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7050 /* Set general SETUP parameters */
7051 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params);
7053 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause,
7054 &setup_params->rxq_params);
7056 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params);
7058 /* Set the command */
7059 q_params.cmd = BNX2X_Q_CMD_SETUP;
7061 /* Change the state to SETUP */
7062 rc = bnx2x_queue_state_change(bp, &q_params);
7064 BNX2X_ERR("Queue SETUP failed\n");
7069 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7071 struct bnx2x_fastpath *fp = &bp->fp[index];
7072 struct bnx2x_queue_state_params q_params = {0};
7075 q_params.q_obj = &fp->q_obj;
7076 /* We want to wait for completion in this context */
7077 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7079 /* halt the connection */
7080 q_params.cmd = BNX2X_Q_CMD_HALT;
7081 rc = bnx2x_queue_state_change(bp, &q_params);
7085 /* terminate the connection */
7086 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7087 rc = bnx2x_queue_state_change(bp, &q_params);
7091 /* delete cfc entry */
7092 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7093 return bnx2x_queue_state_change(bp, &q_params);
7097 static void bnx2x_reset_func(struct bnx2x *bp)
7099 int port = BP_PORT(bp);
7100 int func = BP_FUNC(bp);
7103 /* Disable the function in the FW */
7104 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7105 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7106 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7107 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7110 for_each_eth_queue(bp, i) {
7111 struct bnx2x_fastpath *fp = &bp->fp[i];
7112 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7113 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7119 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7120 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7124 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7125 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7128 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7129 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7133 if (bp->common.int_block == INT_BLOCK_HC) {
7134 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7135 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7137 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7138 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7142 /* Disable Timer scan */
7143 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7145 * Wait for at least 10ms and up to 2 second for the timers scan to
7148 for (i = 0; i < 200; i++) {
7150 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7155 bnx2x_clear_func_ilt(bp, func);
7157 /* Timers workaround bug for E2: if this is vnic-3,
7158 * we need to set the entire ilt range for this timers.
7160 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7161 struct ilt_client_info ilt_cli;
7162 /* use dummy TM client */
7163 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7165 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7166 ilt_cli.client_num = ILT_CLIENT_TM;
7168 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7171 /* this assumes that reset_port() called before reset_func()*/
7172 if (!CHIP_IS_E1x(bp))
7173 bnx2x_pf_disable(bp);
7178 static void bnx2x_reset_port(struct bnx2x *bp)
7180 int port = BP_PORT(bp);
7183 /* Reset physical Link */
7184 bnx2x__link_reset(bp);
7186 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7188 /* Do not rcv packets to BRB */
7189 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7190 /* Do not direct rcv packets that are not for MCP to the BRB */
7191 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7192 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7195 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7198 /* Check for BRB port occupancy */
7199 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7201 DP(NETIF_MSG_IFDOWN,
7202 "BRB1 is not empty %d blocks are occupied\n", val);
7204 /* TODO: Close Doorbell port? */
7207 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7209 struct bnx2x_func_state_params func_params = {0};
7211 /* Prepare parameters for function state transitions */
7212 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7214 func_params.f_obj = &bp->func_obj;
7215 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7217 func_params.params.hw_init.load_phase = load_code;
7219 return bnx2x_func_state_change(bp, &func_params);
7222 static inline int bnx2x_func_stop(struct bnx2x *bp)
7224 struct bnx2x_func_state_params func_params = {0};
7227 /* Prepare parameters for function state transitions */
7228 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7229 func_params.f_obj = &bp->func_obj;
7230 func_params.cmd = BNX2X_F_CMD_STOP;
7233 * Try to stop the function the 'good way'. If fails (in case
7234 * of a parity error during bnx2x_chip_cleanup()) and we are
7235 * not in a debug mode, perform a state transaction in order to
7236 * enable further HW_RESET transaction.
7238 rc = bnx2x_func_state_change(bp, &func_params);
7240 #ifdef BNX2X_STOP_ON_ERROR
7243 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7245 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7246 return bnx2x_func_state_change(bp, &func_params);
7254 * bnx2x_send_unload_req - request unload mode from the MCP.
7256 * @bp: driver handle
7257 * @unload_mode: requested function's unload mode
7259 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7261 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7264 int port = BP_PORT(bp);
7266 /* Select the UNLOAD request mode */
7267 if (unload_mode == UNLOAD_NORMAL)
7268 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7270 else if (bp->flags & NO_WOL_FLAG)
7271 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7274 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7275 u8 *mac_addr = bp->dev->dev_addr;
7277 /* The mac address is written to entries 1-4 to
7278 preserve entry 0 which is used by the PMF */
7279 u8 entry = (BP_E1HVN(bp) + 1)*8;
7281 val = (mac_addr[0] << 8) | mac_addr[1];
7282 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7284 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7285 (mac_addr[4] << 8) | mac_addr[5];
7286 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7288 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7291 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7293 /* Send the request to the MCP */
7295 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7297 int path = BP_PATH(bp);
7299 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7301 path, load_count[path][0], load_count[path][1],
7302 load_count[path][2]);
7303 load_count[path][0]--;
7304 load_count[path][1 + port]--;
7305 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7307 path, load_count[path][0], load_count[path][1],
7308 load_count[path][2]);
7309 if (load_count[path][0] == 0)
7310 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7311 else if (load_count[path][1 + port] == 0)
7312 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7314 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7321 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7323 * @bp: driver handle
7325 void bnx2x_send_unload_done(struct bnx2x *bp)
7327 /* Report UNLOAD_DONE to MCP */
7329 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7332 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7334 int port = BP_PORT(bp);
7336 struct bnx2x_mcast_ramrod_params rparam = {0};
7339 /* Wait until tx fastpath tasks complete */
7340 for_each_tx_queue(bp, i) {
7341 struct bnx2x_fastpath *fp = &bp->fp[i];
7343 rc = bnx2x_clean_tx_queue(bp, fp);
7344 #ifdef BNX2X_STOP_ON_ERROR
7350 /* Give HW time to discard old tx messages */
7351 usleep_range(1000, 1000);
7353 /* Clean all ETH MACs */
7354 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7356 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7358 /* Clean up UC list */
7359 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7362 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7366 if (!CHIP_IS_E1(bp))
7367 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7369 /* Set "drop all" (stop Rx).
7370 * We need to take a netif_addr_lock() here in order to prevent
7371 * a race between the completion code and this code.
7373 netif_addr_lock_bh(bp->dev);
7374 /* Schedule the rx_mode command */
7375 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7376 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7378 bnx2x_set_storm_rx_mode(bp);
7380 /* Cleanup multicast configuration */
7381 rparam.mcast_obj = &bp->mcast_obj;
7382 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7384 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7386 netif_addr_unlock_bh(bp->dev);
7389 /* Close multi and leading connections
7390 * Completions for ramrods are collected in a synchronous way
7392 for_each_queue(bp, i)
7393 if (bnx2x_stop_queue(bp, i))
7394 #ifdef BNX2X_STOP_ON_ERROR
7399 /* If SP settings didn't get completed so far - something
7400 * very wrong has happen.
7402 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7403 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7405 #ifndef BNX2X_STOP_ON_ERROR
7408 rc = bnx2x_func_stop(bp);
7410 BNX2X_ERR("Function stop failed!\n");
7411 #ifdef BNX2X_STOP_ON_ERROR
7417 * Send the UNLOAD_REQUEST to the MCP. This will return if
7418 * this function should perform FUNC, PORT or COMMON HW
7421 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7423 /* Disable HW interrupts, NAPI */
7424 bnx2x_netif_stop(bp, 1);
7429 /* Reset the chip */
7430 rc = bnx2x_reset_hw(bp, reset_code);
7432 BNX2X_ERR("HW_RESET failed\n");
7435 /* Report UNLOAD_DONE to MCP */
7436 bnx2x_send_unload_done(bp);
7439 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7443 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7445 if (CHIP_IS_E1(bp)) {
7446 int port = BP_PORT(bp);
7447 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7448 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7450 val = REG_RD(bp, addr);
7452 REG_WR(bp, addr, val);
7454 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7455 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7456 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7457 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7461 /* Close gates #2, #3 and #4: */
7462 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7466 /* Gates #2 and #4a are closed/opened for "not E1" only */
7467 if (!CHIP_IS_E1(bp)) {
7469 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7471 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7475 if (CHIP_IS_E1x(bp)) {
7476 /* Prevent interrupts from HC on both ports */
7477 val = REG_RD(bp, HC_REG_CONFIG_1);
7478 REG_WR(bp, HC_REG_CONFIG_1,
7479 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7480 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7482 val = REG_RD(bp, HC_REG_CONFIG_0);
7483 REG_WR(bp, HC_REG_CONFIG_0,
7484 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7485 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7487 /* Prevent incomming interrupts in IGU */
7488 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7490 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7492 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7493 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7496 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7497 close ? "closing" : "opening");
7501 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7503 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7505 /* Do some magic... */
7506 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7507 *magic_val = val & SHARED_MF_CLP_MAGIC;
7508 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7512 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7514 * @bp: driver handle
7515 * @magic_val: old value of the `magic' bit.
7517 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7519 /* Restore the `magic' bit value... */
7520 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7521 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7522 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7526 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7528 * @bp: driver handle
7529 * @magic_val: old value of 'magic' bit.
7531 * Takes care of CLP configurations.
7533 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7536 u32 validity_offset;
7538 DP(NETIF_MSG_HW, "Starting\n");
7540 /* Set `magic' bit in order to save MF config */
7541 if (!CHIP_IS_E1(bp))
7542 bnx2x_clp_reset_prep(bp, magic_val);
7544 /* Get shmem offset */
7545 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7546 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7548 /* Clear validity map flags */
7550 REG_WR(bp, shmem + validity_offset, 0);
7553 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7554 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7557 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7559 * @bp: driver handle
7561 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7563 /* special handling for emulation and FPGA,
7564 wait 10 times longer */
7565 if (CHIP_REV_IS_SLOW(bp))
7566 msleep(MCP_ONE_TIMEOUT*10);
7568 msleep(MCP_ONE_TIMEOUT);
7572 * initializes bp->common.shmem_base and waits for validity signature to appear
7574 static int bnx2x_init_shmem(struct bnx2x *bp)
7580 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7581 if (bp->common.shmem_base) {
7582 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7583 if (val & SHR_MEM_VALIDITY_MB)
7587 bnx2x_mcp_wait_one(bp);
7589 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7591 BNX2X_ERR("BAD MCP validity signature\n");
7596 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7598 int rc = bnx2x_init_shmem(bp);
7600 /* Restore the `magic' bit value */
7601 if (!CHIP_IS_E1(bp))
7602 bnx2x_clp_reset_done(bp, magic_val);
7607 static void bnx2x_pxp_prep(struct bnx2x *bp)
7609 if (!CHIP_IS_E1(bp)) {
7610 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7611 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7617 * Reset the whole chip except for:
7619 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7622 * - MISC (including AEU)
7626 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7628 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7632 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7633 * (per chip) blocks.
7636 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7637 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7640 MISC_REGISTERS_RESET_REG_1_RST_HC |
7641 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7642 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7645 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
7646 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7647 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7648 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7649 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7650 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7651 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7652 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7654 reset_mask1 = 0xffffffff;
7657 reset_mask2 = 0xffff;
7659 reset_mask2 = 0x1ffff;
7661 if (CHIP_IS_E3(bp)) {
7662 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7663 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7666 /* Don't reset global blocks unless we need to */
7668 reset_mask2 &= ~global_bits2;
7671 * In case of attention in the QM, we need to reset PXP
7672 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7673 * because otherwise QM reset would release 'close the gates' shortly
7674 * before resetting the PXP, then the PSWRQ would send a write
7675 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7676 * read the payload data from PSWWR, but PSWWR would not
7677 * respond. The write queue in PGLUE would stuck, dmae commands
7678 * would not return. Therefore it's important to reset the second
7679 * reset register (containing the
7680 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7681 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7684 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7685 reset_mask2 & (~not_reset_mask2));
7687 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7688 reset_mask1 & (~not_reset_mask1));
7693 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7694 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7699 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
7700 * It should get cleared in no more than 1s.
7702 * @bp: driver handle
7704 * It should get cleared in no more than 1s. Returns 0 if
7705 * pending writes bit gets cleared.
7707 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
7713 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
7718 usleep_range(1000, 1000);
7719 } while (cnt-- > 0);
7722 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
7730 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
7734 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7737 /* Empty the Tetris buffer, wait for 1s */
7739 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7740 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7741 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7742 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7743 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7744 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7745 ((port_is_idle_0 & 0x1) == 0x1) &&
7746 ((port_is_idle_1 & 0x1) == 0x1) &&
7747 (pgl_exp_rom2 == 0xffffffff))
7749 usleep_range(1000, 1000);
7750 } while (cnt-- > 0);
7753 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7755 " outstanding read requests after 1s!\n");
7756 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7757 " port_is_idle_0=0x%08x,"
7758 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7759 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7766 /* Close gates #2, #3 and #4 */
7767 bnx2x_set_234_gates(bp, true);
7769 /* Poll for IGU VQs for 57712 and newer chips */
7770 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
7774 /* TBD: Indicate that "process kill" is in progress to MCP */
7776 /* Clear "unprepared" bit */
7777 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7780 /* Make sure all is written to the chip before the reset */
7783 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7784 * PSWHST, GRC and PSWRD Tetris buffer.
7786 usleep_range(1000, 1000);
7788 /* Prepare to chip reset: */
7791 bnx2x_reset_mcp_prep(bp, &val);
7797 /* reset the chip */
7798 bnx2x_process_kill_chip_reset(bp, global);
7801 /* Recover after reset: */
7803 if (global && bnx2x_reset_mcp_comp(bp, val))
7806 /* TBD: Add resetting the NO_MCP mode DB here */
7811 /* Open the gates #2, #3 and #4 */
7812 bnx2x_set_234_gates(bp, false);
7814 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7815 * reset state, re-enable attentions. */
7820 int bnx2x_leader_reset(struct bnx2x *bp)
7823 bool global = bnx2x_reset_is_global(bp);
7825 /* Try to recover after the failure */
7826 if (bnx2x_process_kill(bp, global)) {
7827 netdev_err(bp->dev, "Something bad had happen on engine %d! "
7828 "Aii!\n", BP_PATH(bp));
7830 goto exit_leader_reset;
7834 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
7837 bnx2x_set_reset_done(bp);
7839 bnx2x_clear_reset_global(bp);
7843 bnx2x_release_leader_lock(bp);
7848 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
7850 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
7852 /* Disconnect this device */
7853 netif_device_detach(bp->dev);
7856 * Block ifup for all function on this engine until "process kill"
7859 bnx2x_set_reset_in_progress(bp);
7861 /* Shut down the power */
7862 bnx2x_set_power_state(bp, PCI_D3hot);
7864 bp->recovery_state = BNX2X_RECOVERY_FAILED;
7870 * Assumption: runs under rtnl lock. This together with the fact
7871 * that it's called only from bnx2x_reset_task() ensure that it
7872 * will never be called when netif_running(bp->dev) is false.
7874 static void bnx2x_parity_recover(struct bnx2x *bp)
7876 bool global = false;
7878 DP(NETIF_MSG_HW, "Handling parity\n");
7880 switch (bp->recovery_state) {
7881 case BNX2X_RECOVERY_INIT:
7882 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7883 bnx2x_chk_parity_attn(bp, &global, false);
7885 /* Try to get a LEADER_LOCK HW lock */
7886 if (bnx2x_trylock_leader_lock(bp)) {
7887 bnx2x_set_reset_in_progress(bp);
7889 * Check if there is a global attention and if
7890 * there was a global attention, set the global
7895 bnx2x_set_reset_global(bp);
7900 /* Stop the driver */
7901 /* If interface has been removed - break */
7902 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7905 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7908 * Reset MCP command sequence number and MCP mail box
7909 * sequence as we are going to reset the MCP.
7913 bp->fw_drv_pulse_wr_seq = 0;
7916 /* Ensure "is_leader", MCP command sequence and
7917 * "recovery_state" update values are seen on other
7923 case BNX2X_RECOVERY_WAIT:
7924 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7925 if (bp->is_leader) {
7926 int other_engine = BP_PATH(bp) ? 0 : 1;
7927 u32 other_load_counter =
7928 bnx2x_get_load_cnt(bp, other_engine);
7930 bnx2x_get_load_cnt(bp, BP_PATH(bp));
7931 global = bnx2x_reset_is_global(bp);
7934 * In case of a parity in a global block, let
7935 * the first leader that performs a
7936 * leader_reset() reset the global blocks in
7937 * order to clear global attentions. Otherwise
7938 * the the gates will remain closed for that
7942 (global && other_load_counter)) {
7943 /* Wait until all other functions get
7946 schedule_delayed_work(&bp->reset_task,
7950 /* If all other functions got down -
7951 * try to bring the chip back to
7952 * normal. In any case it's an exit
7953 * point for a leader.
7955 if (bnx2x_leader_reset(bp)) {
7956 bnx2x_recovery_failed(bp);
7960 /* If we are here, means that the
7961 * leader has succeeded and doesn't
7962 * want to be a leader any more. Try
7963 * to continue as a none-leader.
7967 } else { /* non-leader */
7968 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
7969 /* Try to get a LEADER_LOCK HW lock as
7970 * long as a former leader may have
7971 * been unloaded by the user or
7972 * released a leadership by another
7975 if (bnx2x_trylock_leader_lock(bp)) {
7976 /* I'm a leader now! Restart a
7983 schedule_delayed_work(&bp->reset_task,
7989 * If there was a global attention, wait
7990 * for it to be cleared.
7992 if (bnx2x_reset_is_global(bp)) {
7993 schedule_delayed_work(
7994 &bp->reset_task, HZ/10);
7998 if (bnx2x_nic_load(bp, LOAD_NORMAL))
7999 bnx2x_recovery_failed(bp);
8001 bp->recovery_state =
8002 BNX2X_RECOVERY_DONE;
8015 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8016 * scheduled on a general queue in order to prevent a dead lock.
8018 static void bnx2x_reset_task(struct work_struct *work)
8020 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
8022 #ifdef BNX2X_STOP_ON_ERROR
8023 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
8024 " so reset not done to allow debug dump,\n"
8025 KERN_ERR " you will need to reboot when done\n");
8031 if (!netif_running(bp->dev))
8032 goto reset_task_exit;
8034 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
8035 bnx2x_parity_recover(bp);
8037 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8038 bnx2x_nic_load(bp, LOAD_NORMAL);
8045 /* end of nic load/unload */
8048 * Init service functions
8051 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8053 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8054 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8055 return base + (BP_ABS_FUNC(bp)) * stride;
8058 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8060 u32 reg = bnx2x_get_pretend_reg(bp);
8062 /* Flush all outstanding writes */
8065 /* Pretend to be function 0 */
8067 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8069 /* From now we are in the "like-E1" mode */
8070 bnx2x_int_disable(bp);
8072 /* Flush all outstanding writes */
8075 /* Restore the original function */
8076 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8080 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8083 bnx2x_int_disable(bp);
8085 bnx2x_undi_int_disable_e1h(bp);
8088 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8092 /* Check if there is any driver already loaded */
8093 val = REG_RD(bp, MISC_REG_UNPREPARED);
8095 /* Check if it is the UNDI driver
8096 * UNDI driver initializes CID offset for normal bell to 0x7
8098 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8099 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8101 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8102 /* save our pf_num */
8103 int orig_pf_num = bp->pf_num;
8105 u32 swap_en, swap_val, value;
8107 /* clear the UNDI indication */
8108 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8110 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8112 /* try unload UNDI on port 0 */
8115 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8116 DRV_MSG_SEQ_NUMBER_MASK);
8117 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8119 /* if UNDI is loaded on the other port */
8120 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8122 /* send "DONE" for previous unload */
8123 bnx2x_fw_command(bp,
8124 DRV_MSG_CODE_UNLOAD_DONE, 0);
8126 /* unload UNDI on port 1 */
8129 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8130 DRV_MSG_SEQ_NUMBER_MASK);
8131 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8133 bnx2x_fw_command(bp, reset_code, 0);
8136 /* now it's safe to release the lock */
8137 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8139 bnx2x_undi_int_disable(bp);
8142 /* close input traffic and wait for it */
8143 /* Do not rcv packets to BRB */
8144 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8145 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8146 /* Do not direct rcv packets that are not for MCP to
8148 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8149 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8151 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8152 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8155 /* save NIG port swap info */
8156 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8157 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8160 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8164 if (CHIP_IS_E3(bp)) {
8165 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8166 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8170 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8173 /* take the NIG out of reset and restore swap values */
8175 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8176 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8177 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8178 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8180 /* send unload done to the MCP */
8181 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8183 /* restore our func and fw_seq */
8184 bp->pf_num = orig_pf_num;
8186 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8187 DRV_MSG_SEQ_NUMBER_MASK);
8189 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8193 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8195 u32 val, val2, val3, val4, id;
8198 /* Get the chip revision id and number. */
8199 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8200 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8201 id = ((val & 0xffff) << 16);
8202 val = REG_RD(bp, MISC_REG_CHIP_REV);
8203 id |= ((val & 0xf) << 12);
8204 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8205 id |= ((val & 0xff) << 4);
8206 val = REG_RD(bp, MISC_REG_BOND_ID);
8208 bp->common.chip_id = id;
8210 /* Set doorbell size */
8211 bp->db_size = (1 << BNX2X_DB_SHIFT);
8213 if (!CHIP_IS_E1x(bp)) {
8214 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8216 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8218 val = (val >> 1) & 1;
8219 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8221 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8224 if (CHIP_MODE_IS_4_PORT(bp))
8225 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8227 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8229 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8230 bp->pfid = bp->pf_num; /* 0..7 */
8233 bp->link_params.chip_id = bp->common.chip_id;
8234 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8236 val = (REG_RD(bp, 0x2874) & 0x55);
8237 if ((bp->common.chip_id & 0x1) ||
8238 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8239 bp->flags |= ONE_PORT_FLAG;
8240 BNX2X_DEV_INFO("single port device\n");
8243 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8244 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8245 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8246 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8247 bp->common.flash_size, bp->common.flash_size);
8249 bnx2x_init_shmem(bp);
8253 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8254 MISC_REG_GENERIC_CR_1 :
8255 MISC_REG_GENERIC_CR_0));
8257 bp->link_params.shmem_base = bp->common.shmem_base;
8258 bp->link_params.shmem2_base = bp->common.shmem2_base;
8259 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8260 bp->common.shmem_base, bp->common.shmem2_base);
8262 if (!bp->common.shmem_base) {
8263 BNX2X_DEV_INFO("MCP not active\n");
8264 bp->flags |= NO_MCP_FLAG;
8268 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8269 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8271 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8272 SHARED_HW_CFG_LED_MODE_MASK) >>
8273 SHARED_HW_CFG_LED_MODE_SHIFT);
8275 bp->link_params.feature_config_flags = 0;
8276 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8277 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8278 bp->link_params.feature_config_flags |=
8279 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8281 bp->link_params.feature_config_flags &=
8282 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8284 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8285 bp->common.bc_ver = val;
8286 BNX2X_DEV_INFO("bc_ver %X\n", val);
8287 if (val < BNX2X_BC_VER) {
8288 /* for now only warn
8289 * later we might need to enforce this */
8290 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8291 "please upgrade BC\n", BNX2X_BC_VER, val);
8293 bp->link_params.feature_config_flags |=
8294 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8295 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8297 bp->link_params.feature_config_flags |=
8298 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8299 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8301 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8302 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8304 BNX2X_DEV_INFO("%sWoL capable\n",
8305 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8307 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8308 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8309 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8310 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8312 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8313 val, val2, val3, val4);
8316 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8317 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8319 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8321 int pfid = BP_FUNC(bp);
8322 int vn = BP_E1HVN(bp);
8327 bp->igu_base_sb = 0xff;
8329 if (CHIP_INT_MODE_IS_BC(bp)) {
8330 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8331 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8333 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8336 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8337 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8342 /* IGU in normal mode - read CAM */
8343 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8345 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8346 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8349 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8350 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8352 if (IGU_VEC(val) == 0)
8353 /* default status block */
8354 bp->igu_dsb_id = igu_sb_id;
8356 if (bp->igu_base_sb == 0xff)
8357 bp->igu_base_sb = igu_sb_id;
8363 /* It's expected that number of CAM entries for this
8364 * functions is equal to the MSI-X table size (which was a
8365 * used during bp->l2_cid_count value calculation.
8366 * We want a harsh warning if these values are different!
8368 WARN_ON(bp->igu_sb_cnt != NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8370 if (bp->igu_sb_cnt == 0)
8371 BNX2X_ERR("CAM configuration error\n");
8374 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8377 int cfg_size = 0, idx, port = BP_PORT(bp);
8379 /* Aggregation of supported attributes of all external phys */
8380 bp->port.supported[0] = 0;
8381 bp->port.supported[1] = 0;
8382 switch (bp->link_params.num_phys) {
8384 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8388 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8392 if (bp->link_params.multi_phy_config &
8393 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8394 bp->port.supported[1] =
8395 bp->link_params.phy[EXT_PHY1].supported;
8396 bp->port.supported[0] =
8397 bp->link_params.phy[EXT_PHY2].supported;
8399 bp->port.supported[0] =
8400 bp->link_params.phy[EXT_PHY1].supported;
8401 bp->port.supported[1] =
8402 bp->link_params.phy[EXT_PHY2].supported;
8408 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8409 BNX2X_ERR("NVRAM config error. BAD phy config."
8410 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8412 dev_info.port_hw_config[port].external_phy_config),
8414 dev_info.port_hw_config[port].external_phy_config2));
8419 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8421 switch (switch_cfg) {
8423 bp->port.phy_addr = REG_RD(
8424 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8426 case SWITCH_CFG_10G:
8427 bp->port.phy_addr = REG_RD(
8428 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8431 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8432 bp->port.link_config[0]);
8436 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8437 /* mask what we support according to speed_cap_mask per configuration */
8438 for (idx = 0; idx < cfg_size; idx++) {
8439 if (!(bp->link_params.speed_cap_mask[idx] &
8440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8441 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8443 if (!(bp->link_params.speed_cap_mask[idx] &
8444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8445 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8447 if (!(bp->link_params.speed_cap_mask[idx] &
8448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8449 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8451 if (!(bp->link_params.speed_cap_mask[idx] &
8452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8453 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8455 if (!(bp->link_params.speed_cap_mask[idx] &
8456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8457 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8458 SUPPORTED_1000baseT_Full);
8460 if (!(bp->link_params.speed_cap_mask[idx] &
8461 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8462 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8464 if (!(bp->link_params.speed_cap_mask[idx] &
8465 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8466 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8470 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8471 bp->port.supported[1]);
8474 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8476 u32 link_config, idx, cfg_size = 0;
8477 bp->port.advertising[0] = 0;
8478 bp->port.advertising[1] = 0;
8479 switch (bp->link_params.num_phys) {
8488 for (idx = 0; idx < cfg_size; idx++) {
8489 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8490 link_config = bp->port.link_config[idx];
8491 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8492 case PORT_FEATURE_LINK_SPEED_AUTO:
8493 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8494 bp->link_params.req_line_speed[idx] =
8496 bp->port.advertising[idx] |=
8497 bp->port.supported[idx];
8499 /* force 10G, no AN */
8500 bp->link_params.req_line_speed[idx] =
8502 bp->port.advertising[idx] |=
8503 (ADVERTISED_10000baseT_Full |
8509 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8510 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8511 bp->link_params.req_line_speed[idx] =
8513 bp->port.advertising[idx] |=
8514 (ADVERTISED_10baseT_Full |
8517 BNX2X_ERR("NVRAM config error. "
8518 "Invalid link_config 0x%x"
8519 " speed_cap_mask 0x%x\n",
8521 bp->link_params.speed_cap_mask[idx]);
8526 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8527 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8528 bp->link_params.req_line_speed[idx] =
8530 bp->link_params.req_duplex[idx] =
8532 bp->port.advertising[idx] |=
8533 (ADVERTISED_10baseT_Half |
8536 BNX2X_ERR("NVRAM config error. "
8537 "Invalid link_config 0x%x"
8538 " speed_cap_mask 0x%x\n",
8540 bp->link_params.speed_cap_mask[idx]);
8545 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8546 if (bp->port.supported[idx] &
8547 SUPPORTED_100baseT_Full) {
8548 bp->link_params.req_line_speed[idx] =
8550 bp->port.advertising[idx] |=
8551 (ADVERTISED_100baseT_Full |
8554 BNX2X_ERR("NVRAM config error. "
8555 "Invalid link_config 0x%x"
8556 " speed_cap_mask 0x%x\n",
8558 bp->link_params.speed_cap_mask[idx]);
8563 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8564 if (bp->port.supported[idx] &
8565 SUPPORTED_100baseT_Half) {
8566 bp->link_params.req_line_speed[idx] =
8568 bp->link_params.req_duplex[idx] =
8570 bp->port.advertising[idx] |=
8571 (ADVERTISED_100baseT_Half |
8574 BNX2X_ERR("NVRAM config error. "
8575 "Invalid link_config 0x%x"
8576 " speed_cap_mask 0x%x\n",
8578 bp->link_params.speed_cap_mask[idx]);
8583 case PORT_FEATURE_LINK_SPEED_1G:
8584 if (bp->port.supported[idx] &
8585 SUPPORTED_1000baseT_Full) {
8586 bp->link_params.req_line_speed[idx] =
8588 bp->port.advertising[idx] |=
8589 (ADVERTISED_1000baseT_Full |
8592 BNX2X_ERR("NVRAM config error. "
8593 "Invalid link_config 0x%x"
8594 " speed_cap_mask 0x%x\n",
8596 bp->link_params.speed_cap_mask[idx]);
8601 case PORT_FEATURE_LINK_SPEED_2_5G:
8602 if (bp->port.supported[idx] &
8603 SUPPORTED_2500baseX_Full) {
8604 bp->link_params.req_line_speed[idx] =
8606 bp->port.advertising[idx] |=
8607 (ADVERTISED_2500baseX_Full |
8610 BNX2X_ERR("NVRAM config error. "
8611 "Invalid link_config 0x%x"
8612 " speed_cap_mask 0x%x\n",
8614 bp->link_params.speed_cap_mask[idx]);
8619 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8620 if (bp->port.supported[idx] &
8621 SUPPORTED_10000baseT_Full) {
8622 bp->link_params.req_line_speed[idx] =
8624 bp->port.advertising[idx] |=
8625 (ADVERTISED_10000baseT_Full |
8628 BNX2X_ERR("NVRAM config error. "
8629 "Invalid link_config 0x%x"
8630 " speed_cap_mask 0x%x\n",
8632 bp->link_params.speed_cap_mask[idx]);
8636 case PORT_FEATURE_LINK_SPEED_20G:
8637 bp->link_params.req_line_speed[idx] = SPEED_20000;
8641 BNX2X_ERR("NVRAM config error. "
8642 "BAD link speed link_config 0x%x\n",
8644 bp->link_params.req_line_speed[idx] =
8646 bp->port.advertising[idx] =
8647 bp->port.supported[idx];
8651 bp->link_params.req_flow_ctrl[idx] = (link_config &
8652 PORT_FEATURE_FLOW_CONTROL_MASK);
8653 if ((bp->link_params.req_flow_ctrl[idx] ==
8654 BNX2X_FLOW_CTRL_AUTO) &&
8655 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8656 bp->link_params.req_flow_ctrl[idx] =
8657 BNX2X_FLOW_CTRL_NONE;
8660 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8661 " 0x%x advertising 0x%x\n",
8662 bp->link_params.req_line_speed[idx],
8663 bp->link_params.req_duplex[idx],
8664 bp->link_params.req_flow_ctrl[idx],
8665 bp->port.advertising[idx]);
8669 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8671 mac_hi = cpu_to_be16(mac_hi);
8672 mac_lo = cpu_to_be32(mac_lo);
8673 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8674 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8677 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8679 int port = BP_PORT(bp);
8681 u32 ext_phy_type, ext_phy_config;
8683 bp->link_params.bp = bp;
8684 bp->link_params.port = port;
8686 bp->link_params.lane_config =
8687 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8689 bp->link_params.speed_cap_mask[0] =
8691 dev_info.port_hw_config[port].speed_capability_mask);
8692 bp->link_params.speed_cap_mask[1] =
8694 dev_info.port_hw_config[port].speed_capability_mask2);
8695 bp->port.link_config[0] =
8696 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8698 bp->port.link_config[1] =
8699 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8701 bp->link_params.multi_phy_config =
8702 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8703 /* If the device is capable of WoL, set the default state according
8706 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8707 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8708 (config & PORT_FEATURE_WOL_ENABLED));
8710 BNX2X_DEV_INFO("lane_config 0x%08x "
8711 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8712 bp->link_params.lane_config,
8713 bp->link_params.speed_cap_mask[0],
8714 bp->port.link_config[0]);
8716 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8717 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8718 bnx2x_phy_probe(&bp->link_params);
8719 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8721 bnx2x_link_settings_requested(bp);
8724 * If connected directly, work with the internal PHY, otherwise, work
8725 * with the external PHY
8729 dev_info.port_hw_config[port].external_phy_config);
8730 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8731 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8732 bp->mdio.prtad = bp->port.phy_addr;
8734 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8735 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8737 XGXS_EXT_PHY_ADDR(ext_phy_config);
8740 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8741 * In MF mode, it is set to cover self test cases
8744 bp->port.need_hw_lock = 1;
8746 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8747 bp->common.shmem_base,
8748 bp->common.shmem2_base);
8752 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8754 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8755 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8756 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8757 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8759 /* Get the number of maximum allowed iSCSI and FCoE connections */
8760 bp->cnic_eth_dev.max_iscsi_conn =
8761 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8762 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8764 bp->cnic_eth_dev.max_fcoe_conn =
8765 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8766 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8768 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8769 bp->cnic_eth_dev.max_iscsi_conn,
8770 bp->cnic_eth_dev.max_fcoe_conn);
8772 /* If mamimum allowed number of connections is zero -
8773 * disable the feature.
8775 if (!bp->cnic_eth_dev.max_iscsi_conn)
8776 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8778 if (!bp->cnic_eth_dev.max_fcoe_conn)
8779 bp->flags |= NO_FCOE_FLAG;
8783 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8786 int func = BP_ABS_FUNC(bp);
8787 int port = BP_PORT(bp);
8789 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8790 u8 *fip_mac = bp->fip_mac;
8793 /* Zero primary MAC configuration */
8794 memset(bp->dev->dev_addr, 0, ETH_ALEN);
8797 BNX2X_ERROR("warning: random MAC workaround active\n");
8798 random_ether_addr(bp->dev->dev_addr);
8799 } else if (IS_MF(bp)) {
8800 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8801 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8802 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8803 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8804 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8807 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8808 * FCoE MAC then the appropriate feature should be disabled.
8811 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8812 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8813 val2 = MF_CFG_RD(bp, func_ext_config[func].
8814 iscsi_mac_addr_upper);
8815 val = MF_CFG_RD(bp, func_ext_config[func].
8816 iscsi_mac_addr_lower);
8817 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8818 BNX2X_DEV_INFO("Read iSCSI MAC: "
8820 BNX2X_MAC_PRN_LIST(iscsi_mac));
8822 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8824 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8825 val2 = MF_CFG_RD(bp, func_ext_config[func].
8826 fcoe_mac_addr_upper);
8827 val = MF_CFG_RD(bp, func_ext_config[func].
8828 fcoe_mac_addr_lower);
8829 bnx2x_set_mac_buf(fip_mac, val, val2);
8830 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
8832 BNX2X_MAC_PRN_LIST(fip_mac));
8835 bp->flags |= NO_FCOE_FLAG;
8839 /* in SF read MACs from port configuration */
8840 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8841 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8842 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8845 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8847 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8849 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8853 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8854 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8857 /* Set the FCoE MAC in modes other then MF_SI */
8858 if (!CHIP_IS_E1x(bp)) {
8860 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8861 else if (!IS_MF(bp))
8862 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8865 /* Disable iSCSI if MAC configuration is
8868 if (!is_valid_ether_addr(iscsi_mac)) {
8869 bp->flags |= NO_ISCSI_FLAG;
8870 memset(iscsi_mac, 0, ETH_ALEN);
8873 /* Disable FCoE if MAC configuration is
8876 if (!is_valid_ether_addr(fip_mac)) {
8877 bp->flags |= NO_FCOE_FLAG;
8878 memset(bp->fip_mac, 0, ETH_ALEN);
8882 if (!is_valid_ether_addr(bp->dev->dev_addr))
8883 dev_err(&bp->pdev->dev,
8884 "bad Ethernet MAC address configuration: "
8885 BNX2X_MAC_FMT", change it manually before bringing up "
8886 "the appropriate network interface\n",
8887 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
8890 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8892 int /*abs*/func = BP_ABS_FUNC(bp);
8897 bnx2x_get_common_hwinfo(bp);
8899 if (CHIP_IS_E1x(bp)) {
8900 bp->common.int_block = INT_BLOCK_HC;
8902 bp->igu_dsb_id = DEF_SB_IGU_ID;
8903 bp->igu_base_sb = 0;
8904 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8905 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8907 bp->common.int_block = INT_BLOCK_IGU;
8908 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8910 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8913 BNX2X_DEV_INFO("FORCING Normal Mode\n");
8915 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8916 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
8917 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
8919 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8921 usleep_range(1000, 1000);
8924 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
8925 dev_err(&bp->pdev->dev,
8926 "FORCING Normal Mode failed!!!\n");
8931 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8932 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
8933 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8935 BNX2X_DEV_INFO("IGU Normal Mode\n");
8937 bnx2x_get_igu_cam_info(bp);
8942 * set base FW non-default (fast path) status block id, this value is
8943 * used to initialize the fw_sb_id saved on the fp/queue structure to
8944 * determine the id used by the FW.
8946 if (CHIP_IS_E1x(bp))
8947 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
8949 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
8950 * the same queue are indicated on the same IGU SB). So we prefer
8951 * FW and IGU SBs to be the same value.
8953 bp->base_fw_ndsb = bp->igu_base_sb;
8955 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
8956 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
8957 bp->igu_sb_cnt, bp->base_fw_ndsb);
8960 * Initialize MF configuration
8967 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8968 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
8969 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8970 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8972 if (SHMEM2_HAS(bp, mf_cfg_addr))
8973 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8975 bp->common.mf_cfg_base = bp->common.shmem_base +
8976 offsetof(struct shmem_region, func_mb) +
8977 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8979 * get mf configuration:
8980 * 1. existence of MF configuration
8981 * 2. MAC address must be legal (check only upper bytes)
8982 * for Switch-Independent mode;
8983 * OVLAN must be legal for Switch-Dependent mode
8984 * 3. SF_MODE configures specific MF mode
8986 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8987 /* get mf configuration */
8989 dev_info.shared_feature_config.config);
8990 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8993 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8994 val = MF_CFG_RD(bp, func_mf_config[func].
8996 /* check for legal mac (upper bytes)*/
8997 if (val != 0xffff) {
8998 bp->mf_mode = MULTI_FUNCTION_SI;
8999 bp->mf_config[vn] = MF_CFG_RD(bp,
9000 func_mf_config[func].config);
9002 BNX2X_DEV_INFO("illegal MAC address "
9005 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9006 /* get OV configuration */
9008 func_mf_config[FUNC_0].e1hov_tag);
9009 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9011 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9012 bp->mf_mode = MULTI_FUNCTION_SD;
9013 bp->mf_config[vn] = MF_CFG_RD(bp,
9014 func_mf_config[func].config);
9016 BNX2X_DEV_INFO("illegal OV for SD\n");
9019 /* Unknown configuration: reset mf_config */
9020 bp->mf_config[vn] = 0;
9021 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9025 BNX2X_DEV_INFO("%s function mode\n",
9026 IS_MF(bp) ? "multi" : "single");
9028 switch (bp->mf_mode) {
9029 case MULTI_FUNCTION_SD:
9030 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9031 FUNC_MF_CFG_E1HOV_TAG_MASK;
9032 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9034 bp->path_has_ovlan = true;
9036 BNX2X_DEV_INFO("MF OV for func %d is %d "
9037 "(0x%04x)\n", func, bp->mf_ov,
9040 dev_err(&bp->pdev->dev,
9041 "No valid MF OV for func %d, "
9042 "aborting\n", func);
9046 case MULTI_FUNCTION_SI:
9047 BNX2X_DEV_INFO("func %d is in MF "
9048 "switch-independent mode\n", func);
9052 dev_err(&bp->pdev->dev,
9053 "VN %d is in a single function mode, "
9060 /* check if other port on the path needs ovlan:
9061 * Since MF configuration is shared between ports
9062 * Possible mixed modes are only
9063 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9065 if (CHIP_MODE_IS_4_PORT(bp) &&
9066 !bp->path_has_ovlan &&
9068 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9069 u8 other_port = !BP_PORT(bp);
9070 u8 other_func = BP_PATH(bp) + 2*other_port;
9072 func_mf_config[other_func].e1hov_tag);
9073 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9074 bp->path_has_ovlan = true;
9078 /* adjust igu_sb_cnt to MF for E1x */
9079 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9080 bp->igu_sb_cnt /= E1HVN_MAX;
9083 bnx2x_get_port_hwinfo(bp);
9085 if (!BP_NOMCP(bp)) {
9087 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9088 DRV_MSG_SEQ_NUMBER_MASK);
9089 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9092 /* Get MAC addresses */
9093 bnx2x_get_mac_hwinfo(bp);
9096 bnx2x_get_cnic_info(bp);
9099 /* Get current FW pulse sequence */
9100 if (!BP_NOMCP(bp)) {
9101 int mb_idx = BP_FW_MB_IDX(bp);
9103 bp->fw_drv_pulse_wr_seq =
9104 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9105 DRV_PULSE_SEQ_MASK);
9106 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9112 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9114 int cnt, i, block_end, rodi;
9115 char vpd_data[BNX2X_VPD_LEN+1];
9116 char str_id_reg[VENDOR_ID_LEN+1];
9117 char str_id_cap[VENDOR_ID_LEN+1];
9120 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9121 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9123 if (cnt < BNX2X_VPD_LEN)
9126 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9127 PCI_VPD_LRDT_RO_DATA);
9132 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9133 pci_vpd_lrdt_size(&vpd_data[i]);
9135 i += PCI_VPD_LRDT_TAG_SIZE;
9137 if (block_end > BNX2X_VPD_LEN)
9140 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9141 PCI_VPD_RO_KEYWORD_MFR_ID);
9145 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9147 if (len != VENDOR_ID_LEN)
9150 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9152 /* vendor specific info */
9153 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9154 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9155 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9156 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9158 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9159 PCI_VPD_RO_KEYWORD_VENDOR0);
9161 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9163 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9165 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9166 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9167 bp->fw_ver[len] = ' ';
9176 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9180 if (CHIP_REV_IS_FPGA(bp))
9181 SET_FLAGS(flags, MODE_FPGA);
9182 else if (CHIP_REV_IS_EMUL(bp))
9183 SET_FLAGS(flags, MODE_EMUL);
9185 SET_FLAGS(flags, MODE_ASIC);
9187 if (CHIP_MODE_IS_4_PORT(bp))
9188 SET_FLAGS(flags, MODE_PORT4);
9190 SET_FLAGS(flags, MODE_PORT2);
9193 SET_FLAGS(flags, MODE_E2);
9194 else if (CHIP_IS_E3(bp)) {
9195 SET_FLAGS(flags, MODE_E3);
9196 if (CHIP_REV(bp) == CHIP_REV_Ax)
9197 SET_FLAGS(flags, MODE_E3_A0);
9198 else {/*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9199 SET_FLAGS(flags, MODE_E3_B0);
9200 SET_FLAGS(flags, MODE_COS_BC);
9205 SET_FLAGS(flags, MODE_MF);
9206 switch (bp->mf_mode) {
9207 case MULTI_FUNCTION_SD:
9208 SET_FLAGS(flags, MODE_MF_SD);
9210 case MULTI_FUNCTION_SI:
9211 SET_FLAGS(flags, MODE_MF_SI);
9215 SET_FLAGS(flags, MODE_SF);
9217 #if defined(__LITTLE_ENDIAN)
9218 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9219 #else /*(__BIG_ENDIAN)*/
9220 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9222 INIT_MODE_FLAGS(bp) = flags;
9225 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9231 mutex_init(&bp->port.phy_mutex);
9232 mutex_init(&bp->fw_mb_mutex);
9233 spin_lock_init(&bp->stats_lock);
9235 mutex_init(&bp->cnic_mutex);
9238 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9239 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
9241 rc = bnx2x_get_hwinfo(bp);
9245 bnx2x_set_modes_bitmap(bp);
9247 rc = bnx2x_alloc_mem_bp(bp);
9251 bnx2x_read_fwinfo(bp);
9255 /* need to reset chip if undi was active */
9257 bnx2x_undi_unload(bp);
9259 if (CHIP_REV_IS_FPGA(bp))
9260 dev_err(&bp->pdev->dev, "FPGA detected\n");
9262 if (BP_NOMCP(bp) && (func == 0))
9263 dev_err(&bp->pdev->dev, "MCP disabled, "
9264 "must load devices in order!\n");
9266 bp->multi_mode = multi_mode;
9270 bp->flags &= ~TPA_ENABLE_FLAG;
9271 bp->dev->features &= ~NETIF_F_LRO;
9273 bp->flags |= TPA_ENABLE_FLAG;
9274 bp->dev->features |= NETIF_F_LRO;
9276 bp->disable_tpa = disable_tpa;
9279 bp->dropless_fc = 0;
9281 bp->dropless_fc = dropless_fc;
9285 bp->tx_ring_size = MAX_TX_AVAIL;
9287 /* make sure that the numbers are in the right granularity */
9288 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9289 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9291 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9292 bp->current_interval = (poll ? poll : timer_interval);
9294 init_timer(&bp->timer);
9295 bp->timer.expires = jiffies + bp->current_interval;
9296 bp->timer.data = (unsigned long) bp;
9297 bp->timer.function = bnx2x_timer;
9299 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9300 bnx2x_dcbx_init_params(bp);
9303 if (CHIP_IS_E1x(bp))
9304 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9306 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9313 /****************************************************************************
9314 * General service functions
9315 ****************************************************************************/
9318 * net_device service functions
9321 /* called with rtnl_lock */
9322 static int bnx2x_open(struct net_device *dev)
9324 struct bnx2x *bp = netdev_priv(dev);
9325 bool global = false;
9326 int other_engine = BP_PATH(bp) ? 0 : 1;
9327 u32 other_load_counter, load_counter;
9329 netif_carrier_off(dev);
9331 bnx2x_set_power_state(bp, PCI_D0);
9333 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9334 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9337 * If parity had happen during the unload, then attentions
9338 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9339 * want the first function loaded on the current engine to
9340 * complete the recovery.
9342 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9343 bnx2x_chk_parity_attn(bp, &global, true))
9346 * If there are attentions and they are in a global
9347 * blocks, set the GLOBAL_RESET bit regardless whether
9348 * it will be this function that will complete the
9352 bnx2x_set_reset_global(bp);
9355 * Only the first function on the current engine should
9356 * try to recover in open. In case of attentions in
9357 * global blocks only the first in the chip should try
9360 if ((!load_counter &&
9361 (!global || !other_load_counter)) &&
9362 bnx2x_trylock_leader_lock(bp) &&
9363 !bnx2x_leader_reset(bp)) {
9364 netdev_info(bp->dev, "Recovered in open\n");
9368 /* recovery has failed... */
9369 bnx2x_set_power_state(bp, PCI_D3hot);
9370 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9372 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9373 " completed yet. Try again later. If u still see this"
9374 " message after a few retries then power cycle is"
9380 bp->recovery_state = BNX2X_RECOVERY_DONE;
9381 return bnx2x_nic_load(bp, LOAD_OPEN);
9384 /* called with rtnl_lock */
9385 static int bnx2x_close(struct net_device *dev)
9387 struct bnx2x *bp = netdev_priv(dev);
9389 /* Unload the driver, release IRQs */
9390 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9393 bnx2x_set_power_state(bp, PCI_D3hot);
9398 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9399 struct bnx2x_mcast_ramrod_params *p)
9401 int mc_count = netdev_mc_count(bp->dev);
9402 struct bnx2x_mcast_list_elem *mc_mac =
9403 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9404 struct netdev_hw_addr *ha;
9409 INIT_LIST_HEAD(&p->mcast_list);
9411 netdev_for_each_mc_addr(ha, bp->dev) {
9412 mc_mac->mac = bnx2x_mc_addr(ha);
9413 list_add_tail(&mc_mac->link, &p->mcast_list);
9417 p->mcast_list_len = mc_count;
9422 static inline void bnx2x_free_mcast_macs_list(
9423 struct bnx2x_mcast_ramrod_params *p)
9425 struct bnx2x_mcast_list_elem *mc_mac =
9426 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9434 * bnx2x_set_uc_list - configure a new unicast MACs list.
9436 * @bp: driver handle
9438 * We will use zero (0) as a MAC type for these MACs.
9440 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9443 struct net_device *dev = bp->dev;
9444 struct netdev_hw_addr *ha;
9445 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9446 unsigned long ramrod_flags = 0;
9448 /* First schedule a cleanup up of old configuration */
9449 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9451 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9455 netdev_for_each_uc_addr(ha, dev) {
9456 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9457 BNX2X_UC_LIST_MAC, &ramrod_flags);
9459 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
9465 /* Execute the pending commands */
9466 __set_bit(RAMROD_CONT, &ramrod_flags);
9467 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
9468 BNX2X_UC_LIST_MAC, &ramrod_flags);
9471 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9473 struct net_device *dev = bp->dev;
9474 struct bnx2x_mcast_ramrod_params rparam = {0};
9477 rparam.mcast_obj = &bp->mcast_obj;
9479 /* first, clear all configured multicast MACs */
9480 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9482 BNX2X_ERR("Failed to clear multicast "
9483 "configuration: %d\n", rc);
9487 /* then, configure a new MACs list */
9488 if (netdev_mc_count(dev)) {
9489 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
9491 BNX2X_ERR("Failed to create multicast MACs "
9496 /* Now add the new MACs */
9497 rc = bnx2x_config_mcast(bp, &rparam,
9498 BNX2X_MCAST_CMD_ADD);
9500 BNX2X_ERR("Failed to set a new multicast "
9501 "configuration: %d\n", rc);
9503 bnx2x_free_mcast_macs_list(&rparam);
9510 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
9511 void bnx2x_set_rx_mode(struct net_device *dev)
9513 struct bnx2x *bp = netdev_priv(dev);
9514 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9516 if (bp->state != BNX2X_STATE_OPEN) {
9517 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9521 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
9523 if (dev->flags & IFF_PROMISC)
9524 rx_mode = BNX2X_RX_MODE_PROMISC;
9525 else if ((dev->flags & IFF_ALLMULTI) ||
9526 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
9528 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9530 /* some multicasts */
9531 if (bnx2x_set_mc_list(bp) < 0)
9532 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9534 if (bnx2x_set_uc_list(bp) < 0)
9535 rx_mode = BNX2X_RX_MODE_PROMISC;
9538 bp->rx_mode = rx_mode;
9540 /* Schedule the rx_mode command */
9541 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
9542 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9546 bnx2x_set_storm_rx_mode(bp);
9549 /* called with rtnl_lock */
9550 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9551 int devad, u16 addr)
9553 struct bnx2x *bp = netdev_priv(netdev);
9557 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9558 prtad, devad, addr);
9560 /* The HW expects different devad if CL22 is used */
9561 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9563 bnx2x_acquire_phy_lock(bp);
9564 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9565 bnx2x_release_phy_lock(bp);
9566 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9573 /* called with rtnl_lock */
9574 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9575 u16 addr, u16 value)
9577 struct bnx2x *bp = netdev_priv(netdev);
9580 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9581 " value 0x%x\n", prtad, devad, addr, value);
9583 /* The HW expects different devad if CL22 is used */
9584 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9586 bnx2x_acquire_phy_lock(bp);
9587 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9588 bnx2x_release_phy_lock(bp);
9592 /* called with rtnl_lock */
9593 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9595 struct bnx2x *bp = netdev_priv(dev);
9596 struct mii_ioctl_data *mdio = if_mii(ifr);
9598 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9599 mdio->phy_id, mdio->reg_num, mdio->val_in);
9601 if (!netif_running(dev))
9604 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9607 #ifdef CONFIG_NET_POLL_CONTROLLER
9608 static void poll_bnx2x(struct net_device *dev)
9610 struct bnx2x *bp = netdev_priv(dev);
9612 disable_irq(bp->pdev->irq);
9613 bnx2x_interrupt(bp->pdev->irq, dev);
9614 enable_irq(bp->pdev->irq);
9618 static const struct net_device_ops bnx2x_netdev_ops = {
9619 .ndo_open = bnx2x_open,
9620 .ndo_stop = bnx2x_close,
9621 .ndo_start_xmit = bnx2x_start_xmit,
9622 .ndo_select_queue = bnx2x_select_queue,
9623 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9624 .ndo_set_mac_address = bnx2x_change_mac_addr,
9625 .ndo_validate_addr = eth_validate_addr,
9626 .ndo_do_ioctl = bnx2x_ioctl,
9627 .ndo_change_mtu = bnx2x_change_mtu,
9628 .ndo_fix_features = bnx2x_fix_features,
9629 .ndo_set_features = bnx2x_set_features,
9630 .ndo_tx_timeout = bnx2x_tx_timeout,
9631 #ifdef CONFIG_NET_POLL_CONTROLLER
9632 .ndo_poll_controller = poll_bnx2x,
9636 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
9638 struct device *dev = &bp->pdev->dev;
9640 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
9641 bp->flags |= USING_DAC_FLAG;
9642 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
9643 dev_err(dev, "dma_set_coherent_mask failed, "
9647 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
9648 dev_err(dev, "System does not support DMA, aborting\n");
9655 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9656 struct net_device *dev,
9657 unsigned long board_type)
9662 SET_NETDEV_DEV(dev, &pdev->dev);
9663 bp = netdev_priv(dev);
9668 bp->pf_num = PCI_FUNC(pdev->devfn);
9670 rc = pci_enable_device(pdev);
9672 dev_err(&bp->pdev->dev,
9673 "Cannot enable PCI device, aborting\n");
9677 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9678 dev_err(&bp->pdev->dev,
9679 "Cannot find PCI device base address, aborting\n");
9681 goto err_out_disable;
9684 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9685 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9686 " base address, aborting\n");
9688 goto err_out_disable;
9691 if (atomic_read(&pdev->enable_cnt) == 1) {
9692 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9694 dev_err(&bp->pdev->dev,
9695 "Cannot obtain PCI resources, aborting\n");
9696 goto err_out_disable;
9699 pci_set_master(pdev);
9700 pci_save_state(pdev);
9703 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9704 if (bp->pm_cap == 0) {
9705 dev_err(&bp->pdev->dev,
9706 "Cannot find power management capability, aborting\n");
9708 goto err_out_release;
9711 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9712 if (bp->pcie_cap == 0) {
9713 dev_err(&bp->pdev->dev,
9714 "Cannot find PCI Express capability, aborting\n");
9716 goto err_out_release;
9719 rc = bnx2x_set_coherency_mask(bp);
9721 goto err_out_release;
9723 dev->mem_start = pci_resource_start(pdev, 0);
9724 dev->base_addr = dev->mem_start;
9725 dev->mem_end = pci_resource_end(pdev, 0);
9727 dev->irq = pdev->irq;
9729 bp->regview = pci_ioremap_bar(pdev, 0);
9731 dev_err(&bp->pdev->dev,
9732 "Cannot map register space, aborting\n");
9734 goto err_out_release;
9737 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9738 min_t(u64, BNX2X_DB_SIZE(bp),
9739 pci_resource_len(pdev, 2)));
9740 if (!bp->doorbells) {
9741 dev_err(&bp->pdev->dev,
9742 "Cannot map doorbell space, aborting\n");
9747 bnx2x_set_power_state(bp, PCI_D0);
9749 /* clean indirect addresses */
9750 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9751 PCICFG_VENDOR_ID_OFFSET);
9752 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9753 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9754 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9755 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9758 * Enable internal target-read (in case we are probed after PF FLR).
9759 * Must be done prior to any BAR read access
9761 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
9763 /* Reset the load counter */
9764 bnx2x_clear_load_cnt(bp);
9766 dev->watchdog_timeo = TX_TIMEOUT;
9768 dev->netdev_ops = &bnx2x_netdev_ops;
9769 bnx2x_set_ethtool_ops(dev);
9771 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9772 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9773 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9775 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9776 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9778 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
9779 if (bp->flags & USING_DAC_FLAG)
9780 dev->features |= NETIF_F_HIGHDMA;
9782 /* Add Loopback capability to the device */
9783 dev->hw_features |= NETIF_F_LOOPBACK;
9786 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9789 /* get_port_hwinfo() will set prtad and mmds properly */
9790 bp->mdio.prtad = MDIO_PRTAD_NONE;
9792 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9794 bp->mdio.mdio_read = bnx2x_mdio_read;
9795 bp->mdio.mdio_write = bnx2x_mdio_write;
9801 iounmap(bp->regview);
9804 if (bp->doorbells) {
9805 iounmap(bp->doorbells);
9806 bp->doorbells = NULL;
9810 if (atomic_read(&pdev->enable_cnt) == 1)
9811 pci_release_regions(pdev);
9814 pci_disable_device(pdev);
9815 pci_set_drvdata(pdev, NULL);
9821 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9822 int *width, int *speed)
9824 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9826 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9828 /* return value of 1=2.5GHz 2=5GHz */
9829 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9832 static int bnx2x_check_firmware(struct bnx2x *bp)
9834 const struct firmware *firmware = bp->firmware;
9835 struct bnx2x_fw_file_hdr *fw_hdr;
9836 struct bnx2x_fw_file_section *sections;
9837 u32 offset, len, num_ops;
9842 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9845 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9846 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9848 /* Make sure none of the offsets and sizes make us read beyond
9849 * the end of the firmware data */
9850 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9851 offset = be32_to_cpu(sections[i].offset);
9852 len = be32_to_cpu(sections[i].len);
9853 if (offset + len > firmware->size) {
9854 dev_err(&bp->pdev->dev,
9855 "Section %d length is out of bounds\n", i);
9860 /* Likewise for the init_ops offsets */
9861 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9862 ops_offsets = (u16 *)(firmware->data + offset);
9863 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9865 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9866 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9867 dev_err(&bp->pdev->dev,
9868 "Section offset %d is out of bounds\n", i);
9873 /* Check FW version */
9874 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9875 fw_ver = firmware->data + offset;
9876 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9877 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9878 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9879 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9880 dev_err(&bp->pdev->dev,
9881 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9882 fw_ver[0], fw_ver[1], fw_ver[2],
9883 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9884 BCM_5710_FW_MINOR_VERSION,
9885 BCM_5710_FW_REVISION_VERSION,
9886 BCM_5710_FW_ENGINEERING_VERSION);
9893 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9895 const __be32 *source = (const __be32 *)_source;
9896 u32 *target = (u32 *)_target;
9899 for (i = 0; i < n/4; i++)
9900 target[i] = be32_to_cpu(source[i]);
9904 Ops array is stored in the following format:
9905 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9907 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9909 const __be32 *source = (const __be32 *)_source;
9910 struct raw_op *target = (struct raw_op *)_target;
9913 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9914 tmp = be32_to_cpu(source[j]);
9915 target[i].op = (tmp >> 24) & 0xff;
9916 target[i].offset = tmp & 0xffffff;
9917 target[i].raw_data = be32_to_cpu(source[j + 1]);
9922 * IRO array is stored in the following format:
9923 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9925 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9927 const __be32 *source = (const __be32 *)_source;
9928 struct iro *target = (struct iro *)_target;
9931 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9932 target[i].base = be32_to_cpu(source[j]);
9934 tmp = be32_to_cpu(source[j]);
9935 target[i].m1 = (tmp >> 16) & 0xffff;
9936 target[i].m2 = tmp & 0xffff;
9938 tmp = be32_to_cpu(source[j]);
9939 target[i].m3 = (tmp >> 16) & 0xffff;
9940 target[i].size = tmp & 0xffff;
9945 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9947 const __be16 *source = (const __be16 *)_source;
9948 u16 *target = (u16 *)_target;
9951 for (i = 0; i < n/2; i++)
9952 target[i] = be16_to_cpu(source[i]);
9955 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9957 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9958 bp->arr = kmalloc(len, GFP_KERNEL); \
9960 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9963 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9964 (u8 *)bp->arr, len); \
9967 int bnx2x_init_firmware(struct bnx2x *bp)
9969 const char *fw_file_name;
9970 struct bnx2x_fw_file_hdr *fw_hdr;
9974 fw_file_name = FW_FILE_NAME_E1;
9975 else if (CHIP_IS_E1H(bp))
9976 fw_file_name = FW_FILE_NAME_E1H;
9977 else if (!CHIP_IS_E1x(bp))
9978 fw_file_name = FW_FILE_NAME_E2;
9980 BNX2X_ERR("Unsupported chip revision\n");
9984 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9986 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9988 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9989 goto request_firmware_exit;
9992 rc = bnx2x_check_firmware(bp);
9994 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9995 goto request_firmware_exit;
9998 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10000 /* Initialize the pointers to the init arrays */
10002 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10005 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10008 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10011 /* STORMs firmware */
10012 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10013 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10014 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10015 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10016 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10017 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10018 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10019 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10020 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10021 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10022 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10023 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10024 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10025 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10026 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10027 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10029 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10034 kfree(bp->init_ops_offsets);
10035 init_offsets_alloc_err:
10036 kfree(bp->init_ops);
10037 init_ops_alloc_err:
10038 kfree(bp->init_data);
10039 request_firmware_exit:
10040 release_firmware(bp->firmware);
10045 static void bnx2x_release_firmware(struct bnx2x *bp)
10047 kfree(bp->init_ops_offsets);
10048 kfree(bp->init_ops);
10049 kfree(bp->init_data);
10050 release_firmware(bp->firmware);
10054 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10055 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10056 .init_hw_cmn = bnx2x_init_hw_common,
10057 .init_hw_port = bnx2x_init_hw_port,
10058 .init_hw_func = bnx2x_init_hw_func,
10060 .reset_hw_cmn = bnx2x_reset_common,
10061 .reset_hw_port = bnx2x_reset_port,
10062 .reset_hw_func = bnx2x_reset_func,
10064 .gunzip_init = bnx2x_gunzip_init,
10065 .gunzip_end = bnx2x_gunzip_end,
10067 .init_fw = bnx2x_init_firmware,
10068 .release_fw = bnx2x_release_firmware,
10071 void bnx2x__init_func_obj(struct bnx2x *bp)
10073 /* Prepare DMAE related driver resources */
10074 bnx2x_setup_dmae(bp);
10076 bnx2x_init_func_obj(bp, &bp->func_obj,
10077 bnx2x_sp(bp, func_rdata),
10078 bnx2x_sp_mapping(bp, func_rdata),
10079 &bnx2x_func_sp_drv);
10082 /* must be called after sriov-enable */
10083 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
10085 int cid_count = L2_FP_COUNT(l2_cid_count);
10088 cid_count += CNIC_CID_MAX;
10090 return roundup(cid_count, QM_CID_ROUND);
10094 * bnx2x_pci_msix_table_size - get the size of the MSI-X table.
10099 static inline int bnx2x_pci_msix_table_size(struct pci_dev *pdev)
10104 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10108 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10109 return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
10112 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10113 const struct pci_device_id *ent)
10115 struct net_device *dev = NULL;
10117 int pcie_width, pcie_speed;
10120 switch (ent->driver_data) {
10132 /* The size requested for the MSI-X table corresponds to the
10133 * actual amount of avaliable IGU/HC status blocks. It includes
10134 * the default SB vector but we want cid_count to contain the
10135 * amount of only non-default SBs, that's what '-1' stands for.
10137 cid_count = bnx2x_pci_msix_table_size(pdev) - 1;
10139 /* do not allow initial cid_count grow above 16
10140 * since Special CIDs starts from this number
10141 * use old FP_SB_MAX_E1x define for this matter
10143 cid_count = min_t(int, FP_SB_MAX_E1x, cid_count);
10145 WARN_ON(!cid_count);
10149 pr_err("Unknown board_type (%ld), aborting\n",
10154 cid_count += FCOE_CONTEXT_USE;
10156 /* dev zeroed in init_etherdev */
10157 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
10159 dev_err(&pdev->dev, "Cannot allocate net device\n");
10163 /* We don't need a Tx queue for a CNIC and an OOO Rx-only ring,
10164 * so update a cid_count after a netdev allocation.
10166 cid_count += CNIC_CONTEXT_USE;
10168 bp = netdev_priv(dev);
10169 bp->msg_enable = debug;
10171 pci_set_drvdata(pdev, dev);
10173 bp->l2_cid_count = cid_count;
10175 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10181 BNX2X_DEV_INFO("cid_count=%d\n", cid_count);
10183 rc = bnx2x_init_bp(bp);
10185 goto init_one_exit;
10187 /* calc qm_cid_count */
10188 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
10191 /* disable FCOE L2 queue for E1x*/
10192 if (CHIP_IS_E1x(bp))
10193 bp->flags |= NO_FCOE_FLAG;
10197 /* Configure interrupt mode: try to enable MSI-X/MSI if
10198 * needed, set bp->num_queues appropriately.
10200 bnx2x_set_int_mode(bp);
10202 /* Add all NAPI objects */
10203 bnx2x_add_all_napi(bp);
10205 rc = register_netdev(dev);
10207 dev_err(&pdev->dev, "Cannot register net device\n");
10208 goto init_one_exit;
10212 if (!NO_FCOE(bp)) {
10213 /* Add storage MAC address */
10215 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10220 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10222 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10223 " IRQ %d, ", board_info[ent->driver_data].name,
10224 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10226 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10227 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10228 "5GHz (Gen2)" : "2.5GHz",
10229 dev->base_addr, bp->pdev->irq);
10230 pr_cont("node addr %pM\n", dev->dev_addr);
10236 iounmap(bp->regview);
10239 iounmap(bp->doorbells);
10243 if (atomic_read(&pdev->enable_cnt) == 1)
10244 pci_release_regions(pdev);
10246 pci_disable_device(pdev);
10247 pci_set_drvdata(pdev, NULL);
10252 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10254 struct net_device *dev = pci_get_drvdata(pdev);
10258 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10261 bp = netdev_priv(dev);
10264 /* Delete storage MAC address */
10265 if (!NO_FCOE(bp)) {
10267 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10273 /* Delete app tlvs from dcbnl */
10274 bnx2x_dcbnl_update_applist(bp, true);
10277 unregister_netdev(dev);
10279 /* Delete all NAPI objects */
10280 bnx2x_del_all_napi(bp);
10282 /* Power on: we can't let PCI layer write to us while we are in D3 */
10283 bnx2x_set_power_state(bp, PCI_D0);
10285 /* Disable MSI/MSI-X */
10286 bnx2x_disable_msi(bp);
10289 bnx2x_set_power_state(bp, PCI_D3hot);
10291 /* Make sure RESET task is not scheduled before continuing */
10292 cancel_delayed_work_sync(&bp->reset_task);
10295 iounmap(bp->regview);
10298 iounmap(bp->doorbells);
10300 bnx2x_free_mem_bp(bp);
10304 if (atomic_read(&pdev->enable_cnt) == 1)
10305 pci_release_regions(pdev);
10307 pci_disable_device(pdev);
10308 pci_set_drvdata(pdev, NULL);
10311 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10315 bp->state = BNX2X_STATE_ERROR;
10317 bp->rx_mode = BNX2X_RX_MODE_NONE;
10320 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10323 bnx2x_tx_disable(bp);
10325 bnx2x_netif_stop(bp, 0);
10327 del_timer_sync(&bp->timer);
10329 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10332 bnx2x_free_irq(bp);
10334 /* Free SKBs, SGEs, TPA pool and driver internals */
10335 bnx2x_free_skbs(bp);
10337 for_each_rx_queue(bp, i)
10338 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10340 bnx2x_free_mem(bp);
10342 bp->state = BNX2X_STATE_CLOSED;
10344 netif_carrier_off(bp->dev);
10349 static void bnx2x_eeh_recover(struct bnx2x *bp)
10353 mutex_init(&bp->port.phy_mutex);
10355 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10356 bp->link_params.shmem_base = bp->common.shmem_base;
10357 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10359 if (!bp->common.shmem_base ||
10360 (bp->common.shmem_base < 0xA0000) ||
10361 (bp->common.shmem_base >= 0xC0000)) {
10362 BNX2X_DEV_INFO("MCP not active\n");
10363 bp->flags |= NO_MCP_FLAG;
10367 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10368 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10369 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10370 BNX2X_ERR("BAD MCP validity signature\n");
10372 if (!BP_NOMCP(bp)) {
10374 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10375 DRV_MSG_SEQ_NUMBER_MASK);
10376 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10381 * bnx2x_io_error_detected - called when PCI error is detected
10382 * @pdev: Pointer to PCI device
10383 * @state: The current pci connection state
10385 * This function is called after a PCI bus error affecting
10386 * this device has been detected.
10388 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10389 pci_channel_state_t state)
10391 struct net_device *dev = pci_get_drvdata(pdev);
10392 struct bnx2x *bp = netdev_priv(dev);
10396 netif_device_detach(dev);
10398 if (state == pci_channel_io_perm_failure) {
10400 return PCI_ERS_RESULT_DISCONNECT;
10403 if (netif_running(dev))
10404 bnx2x_eeh_nic_unload(bp);
10406 pci_disable_device(pdev);
10410 /* Request a slot reset */
10411 return PCI_ERS_RESULT_NEED_RESET;
10415 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10416 * @pdev: Pointer to PCI device
10418 * Restart the card from scratch, as if from a cold-boot.
10420 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10422 struct net_device *dev = pci_get_drvdata(pdev);
10423 struct bnx2x *bp = netdev_priv(dev);
10427 if (pci_enable_device(pdev)) {
10428 dev_err(&pdev->dev,
10429 "Cannot re-enable PCI device after reset\n");
10431 return PCI_ERS_RESULT_DISCONNECT;
10434 pci_set_master(pdev);
10435 pci_restore_state(pdev);
10437 if (netif_running(dev))
10438 bnx2x_set_power_state(bp, PCI_D0);
10442 return PCI_ERS_RESULT_RECOVERED;
10446 * bnx2x_io_resume - called when traffic can start flowing again
10447 * @pdev: Pointer to PCI device
10449 * This callback is called when the error recovery driver tells us that
10450 * its OK to resume normal operation.
10452 static void bnx2x_io_resume(struct pci_dev *pdev)
10454 struct net_device *dev = pci_get_drvdata(pdev);
10455 struct bnx2x *bp = netdev_priv(dev);
10457 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
10458 netdev_err(bp->dev, "Handling parity error recovery. "
10459 "Try again later\n");
10465 bnx2x_eeh_recover(bp);
10467 if (netif_running(dev))
10468 bnx2x_nic_load(bp, LOAD_NORMAL);
10470 netif_device_attach(dev);
10475 static struct pci_error_handlers bnx2x_err_handler = {
10476 .error_detected = bnx2x_io_error_detected,
10477 .slot_reset = bnx2x_io_slot_reset,
10478 .resume = bnx2x_io_resume,
10481 static struct pci_driver bnx2x_pci_driver = {
10482 .name = DRV_MODULE_NAME,
10483 .id_table = bnx2x_pci_tbl,
10484 .probe = bnx2x_init_one,
10485 .remove = __devexit_p(bnx2x_remove_one),
10486 .suspend = bnx2x_suspend,
10487 .resume = bnx2x_resume,
10488 .err_handler = &bnx2x_err_handler,
10491 static int __init bnx2x_init(void)
10495 pr_info("%s", version);
10497 bnx2x_wq = create_singlethread_workqueue("bnx2x");
10498 if (bnx2x_wq == NULL) {
10499 pr_err("Cannot create workqueue\n");
10503 ret = pci_register_driver(&bnx2x_pci_driver);
10505 pr_err("Cannot register driver\n");
10506 destroy_workqueue(bnx2x_wq);
10511 static void __exit bnx2x_cleanup(void)
10513 pci_unregister_driver(&bnx2x_pci_driver);
10515 destroy_workqueue(bnx2x_wq);
10518 module_init(bnx2x_init);
10519 module_exit(bnx2x_cleanup);
10523 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
10525 * @bp: driver handle
10526 * @set: set or clear the CAM entry
10528 * This function will wait until the ramdord completion returns.
10529 * Return 0 if success, -ENODEV if ramrod doesn't return.
10531 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
10533 unsigned long ramrod_flags = 0;
10535 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
10536 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
10537 &bp->iscsi_l2_mac_obj, true,
10538 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
10541 /* count denotes the number of new completions we have seen */
10542 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
10544 struct eth_spe *spe;
10546 #ifdef BNX2X_STOP_ON_ERROR
10547 if (unlikely(bp->panic))
10551 spin_lock_bh(&bp->spq_lock);
10552 BUG_ON(bp->cnic_spq_pending < count);
10553 bp->cnic_spq_pending -= count;
10556 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
10557 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
10558 & SPE_HDR_CONN_TYPE) >>
10559 SPE_HDR_CONN_TYPE_SHIFT;
10560 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
10561 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
10563 /* Set validation for iSCSI L2 client before sending SETUP
10566 if (type == ETH_CONNECTION_TYPE) {
10567 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
10568 bnx2x_set_ctx_validation(bp, &bp->context.
10569 vcxt[BNX2X_ISCSI_ETH_CID].eth,
10570 BNX2X_ISCSI_ETH_CID);
10574 * There may be not more than 8 L2, not more than 8 L5 SPEs
10575 * and in the air. We also check that number of outstanding
10576 * COMMON ramrods is not more than the EQ and SPQ can
10579 if (type == ETH_CONNECTION_TYPE) {
10580 if (!atomic_read(&bp->cq_spq_left))
10583 atomic_dec(&bp->cq_spq_left);
10584 } else if (type == NONE_CONNECTION_TYPE) {
10585 if (!atomic_read(&bp->eq_spq_left))
10588 atomic_dec(&bp->eq_spq_left);
10589 } else if ((type == ISCSI_CONNECTION_TYPE) ||
10590 (type == FCOE_CONNECTION_TYPE)) {
10591 if (bp->cnic_spq_pending >=
10592 bp->cnic_eth_dev.max_kwqe_pending)
10595 bp->cnic_spq_pending++;
10597 BNX2X_ERR("Unknown SPE type: %d\n", type);
10602 spe = bnx2x_sp_get_next(bp);
10603 *spe = *bp->cnic_kwq_cons;
10605 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
10606 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
10608 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
10609 bp->cnic_kwq_cons = bp->cnic_kwq;
10611 bp->cnic_kwq_cons++;
10613 bnx2x_sp_prod_update(bp);
10614 spin_unlock_bh(&bp->spq_lock);
10617 static int bnx2x_cnic_sp_queue(struct net_device *dev,
10618 struct kwqe_16 *kwqes[], u32 count)
10620 struct bnx2x *bp = netdev_priv(dev);
10623 #ifdef BNX2X_STOP_ON_ERROR
10624 if (unlikely(bp->panic))
10628 spin_lock_bh(&bp->spq_lock);
10630 for (i = 0; i < count; i++) {
10631 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10633 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10636 *bp->cnic_kwq_prod = *spe;
10638 bp->cnic_kwq_pending++;
10640 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10641 spe->hdr.conn_and_cmd_data, spe->hdr.type,
10642 spe->data.update_data_addr.hi,
10643 spe->data.update_data_addr.lo,
10644 bp->cnic_kwq_pending);
10646 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10647 bp->cnic_kwq_prod = bp->cnic_kwq;
10649 bp->cnic_kwq_prod++;
10652 spin_unlock_bh(&bp->spq_lock);
10654 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10655 bnx2x_cnic_sp_post(bp, 0);
10660 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10662 struct cnic_ops *c_ops;
10665 mutex_lock(&bp->cnic_mutex);
10666 c_ops = rcu_dereference_protected(bp->cnic_ops,
10667 lockdep_is_held(&bp->cnic_mutex));
10669 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10670 mutex_unlock(&bp->cnic_mutex);
10675 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10677 struct cnic_ops *c_ops;
10681 c_ops = rcu_dereference(bp->cnic_ops);
10683 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10690 * for commands that have no data
10692 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
10694 struct cnic_ctl_info ctl = {0};
10698 return bnx2x_cnic_ctl_send(bp, &ctl);
10701 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
10703 struct cnic_ctl_info ctl = {0};
10705 /* first we tell CNIC and only then we count this as a completion */
10706 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10707 ctl.data.comp.cid = cid;
10708 ctl.data.comp.error = err;
10710 bnx2x_cnic_ctl_send_bh(bp, &ctl);
10711 bnx2x_cnic_sp_post(bp, 0);
10715 /* Called with netif_addr_lock_bh() taken.
10716 * Sets an rx_mode config for an iSCSI ETH client.
10718 * Completion should be checked outside.
10720 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
10722 unsigned long accept_flags = 0, ramrod_flags = 0;
10723 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
10724 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
10727 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10728 * because it's the only way for UIO Queue to accept
10729 * multicasts (in non-promiscuous mode only one Queue per
10730 * function will receive multicast packets (leading in our
10733 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
10734 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
10735 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
10736 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
10738 /* Clear STOP_PENDING bit if START is requested */
10739 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
10741 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
10743 /* Clear START_PENDING bit if STOP is requested */
10744 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
10746 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
10747 set_bit(sched_state, &bp->sp_state);
10749 __set_bit(RAMROD_RX, &ramrod_flags);
10750 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
10756 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10758 struct bnx2x *bp = netdev_priv(dev);
10761 switch (ctl->cmd) {
10762 case DRV_CTL_CTXTBL_WR_CMD: {
10763 u32 index = ctl->data.io.offset;
10764 dma_addr_t addr = ctl->data.io.dma_addr;
10766 bnx2x_ilt_wr(bp, index, addr);
10770 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10771 int count = ctl->data.credit.credit_count;
10773 bnx2x_cnic_sp_post(bp, count);
10777 /* rtnl_lock is held. */
10778 case DRV_CTL_START_L2_CMD: {
10779 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10780 unsigned long sp_bits = 0;
10782 /* Configure the iSCSI classification object */
10783 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
10784 cp->iscsi_l2_client_id,
10785 cp->iscsi_l2_cid, BP_FUNC(bp),
10786 bnx2x_sp(bp, mac_rdata),
10787 bnx2x_sp_mapping(bp, mac_rdata),
10788 BNX2X_FILTER_MAC_PENDING,
10789 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
10792 /* Set iSCSI MAC address */
10793 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
10800 /* Start accepting on iSCSI L2 ring */
10802 netif_addr_lock_bh(dev);
10803 bnx2x_set_iscsi_eth_rx_mode(bp, true);
10804 netif_addr_unlock_bh(dev);
10806 /* bits to wait on */
10807 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10808 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
10810 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10811 BNX2X_ERR("rx_mode completion timed out!\n");
10816 /* rtnl_lock is held. */
10817 case DRV_CTL_STOP_L2_CMD: {
10818 unsigned long sp_bits = 0;
10820 /* Stop accepting on iSCSI L2 ring */
10821 netif_addr_lock_bh(dev);
10822 bnx2x_set_iscsi_eth_rx_mode(bp, false);
10823 netif_addr_unlock_bh(dev);
10825 /* bits to wait on */
10826 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
10827 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
10829 if (!bnx2x_wait_sp_comp(bp, sp_bits))
10830 BNX2X_ERR("rx_mode completion timed out!\n");
10835 /* Unset iSCSI L2 MAC */
10836 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
10837 BNX2X_ISCSI_ETH_MAC, true);
10840 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10841 int count = ctl->data.credit.credit_count;
10843 smp_mb__before_atomic_inc();
10844 atomic_add(count, &bp->cq_spq_left);
10845 smp_mb__after_atomic_inc();
10850 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10857 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10859 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10861 if (bp->flags & USING_MSIX_FLAG) {
10862 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10863 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10864 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10866 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10867 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10869 if (!CHIP_IS_E1x(bp))
10870 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10872 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10874 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
10875 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
10876 cp->irq_arr[1].status_blk = bp->def_status_blk;
10877 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10878 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10883 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10886 struct bnx2x *bp = netdev_priv(dev);
10887 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10892 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10896 bp->cnic_kwq_cons = bp->cnic_kwq;
10897 bp->cnic_kwq_prod = bp->cnic_kwq;
10898 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10900 bp->cnic_spq_pending = 0;
10901 bp->cnic_kwq_pending = 0;
10903 bp->cnic_data = data;
10906 cp->drv_state |= CNIC_DRV_STATE_REGD;
10907 cp->iro_arr = bp->iro_arr;
10909 bnx2x_setup_cnic_irq_info(bp);
10911 rcu_assign_pointer(bp->cnic_ops, ops);
10916 static int bnx2x_unregister_cnic(struct net_device *dev)
10918 struct bnx2x *bp = netdev_priv(dev);
10919 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10921 mutex_lock(&bp->cnic_mutex);
10923 rcu_assign_pointer(bp->cnic_ops, NULL);
10924 mutex_unlock(&bp->cnic_mutex);
10926 kfree(bp->cnic_kwq);
10927 bp->cnic_kwq = NULL;
10932 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10934 struct bnx2x *bp = netdev_priv(dev);
10935 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10937 /* If both iSCSI and FCoE are disabled - return NULL in
10938 * order to indicate CNIC that it should not try to work
10939 * with this device.
10941 if (NO_ISCSI(bp) && NO_FCOE(bp))
10944 cp->drv_owner = THIS_MODULE;
10945 cp->chip_id = CHIP_ID(bp);
10946 cp->pdev = bp->pdev;
10947 cp->io_base = bp->regview;
10948 cp->io_base2 = bp->doorbells;
10949 cp->max_kwqe_pending = 8;
10950 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10951 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10952 bnx2x_cid_ilt_lines(bp);
10953 cp->ctx_tbl_len = CNIC_ILT_LINES;
10954 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10955 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10956 cp->drv_ctl = bnx2x_drv_ctl;
10957 cp->drv_register_cnic = bnx2x_register_cnic;
10958 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10959 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10960 cp->iscsi_l2_client_id =
10961 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
10962 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10964 if (NO_ISCSI_OOO(bp))
10965 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10968 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10971 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10973 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10974 "starting cid %d\n",
10976 cp->ctx_tbl_offset,
10981 EXPORT_SYMBOL(bnx2x_cnic_probe);
10983 #endif /* BCM_CNIC */