1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
51 #include <linux/stringify.h>
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
123 static struct workqueue_struct *bnx2x_wq;
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
129 enum bnx2x_board_type {
137 /* indexed by board_type, above */
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
148 #ifndef PCI_DEVICE_ID_NX2_57712
149 #define PCI_DEVICE_ID_NX2_57712 0x1662
151 #ifndef PCI_DEVICE_ID_NX2_57712E
152 #define PCI_DEVICE_ID_NX2_57712E 0x1663
155 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
156 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
157 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
158 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
159 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
160 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
164 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
166 /****************************************************************************
167 * General service functions
168 ****************************************************************************/
170 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
171 u32 addr, dma_addr_t mapping)
173 REG_WR(bp, addr, U64_LO(mapping));
174 REG_WR(bp, addr + 4, U64_HI(mapping));
177 static inline void __storm_memset_fill(struct bnx2x *bp,
178 u32 addr, size_t size, u32 val)
181 for (i = 0; i < size/4; i++)
182 REG_WR(bp, addr + (i * 4), val);
185 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
186 u8 port, u16 stat_id)
188 size_t size = sizeof(struct ustorm_per_client_stats);
190 u32 addr = BAR_USTRORM_INTMEM +
191 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
193 __storm_memset_fill(bp, addr, size, 0);
196 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
197 u8 port, u16 stat_id)
199 size_t size = sizeof(struct tstorm_per_client_stats);
201 u32 addr = BAR_TSTRORM_INTMEM +
202 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
204 __storm_memset_fill(bp, addr, size, 0);
207 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
208 u8 port, u16 stat_id)
210 size_t size = sizeof(struct xstorm_per_client_stats);
212 u32 addr = BAR_XSTRORM_INTMEM +
213 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
215 __storm_memset_fill(bp, addr, size, 0);
219 static inline void storm_memset_spq_addr(struct bnx2x *bp,
220 dma_addr_t mapping, u16 abs_fid)
222 u32 addr = XSEM_REG_FAST_MEMORY +
223 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
225 __storm_memset_dma_mapping(bp, addr, mapping);
228 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
230 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
233 static inline void storm_memset_func_cfg(struct bnx2x *bp,
234 struct tstorm_eth_function_common_config *tcfg,
237 size_t size = sizeof(struct tstorm_eth_function_common_config);
239 u32 addr = BAR_TSTRORM_INTMEM +
240 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
242 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
245 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
246 struct stats_indication_flags *flags,
249 size_t size = sizeof(struct stats_indication_flags);
251 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
253 __storm_memset_struct(bp, addr, size, (u32 *)flags);
256 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
257 struct stats_indication_flags *flags,
260 size_t size = sizeof(struct stats_indication_flags);
262 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
264 __storm_memset_struct(bp, addr, size, (u32 *)flags);
267 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
268 struct stats_indication_flags *flags,
271 size_t size = sizeof(struct stats_indication_flags);
273 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
275 __storm_memset_struct(bp, addr, size, (u32 *)flags);
278 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
279 struct stats_indication_flags *flags,
282 size_t size = sizeof(struct stats_indication_flags);
284 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
286 __storm_memset_struct(bp, addr, size, (u32 *)flags);
289 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
290 dma_addr_t mapping, u16 abs_fid)
292 u32 addr = BAR_XSTRORM_INTMEM +
293 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
295 __storm_memset_dma_mapping(bp, addr, mapping);
298 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
299 dma_addr_t mapping, u16 abs_fid)
301 u32 addr = BAR_TSTRORM_INTMEM +
302 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
304 __storm_memset_dma_mapping(bp, addr, mapping);
307 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
310 u32 addr = BAR_USTRORM_INTMEM +
311 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
313 __storm_memset_dma_mapping(bp, addr, mapping);
316 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
317 dma_addr_t mapping, u16 abs_fid)
319 u32 addr = BAR_CSTRORM_INTMEM +
320 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
322 __storm_memset_dma_mapping(bp, addr, mapping);
325 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
338 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
341 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
343 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
345 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
347 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
351 static inline void storm_memset_eq_data(struct bnx2x *bp,
352 struct event_ring_data *eq_data,
355 size_t size = sizeof(struct event_ring_data);
357 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
359 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
362 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
365 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
366 REG_WR16(bp, addr, eq_prod);
369 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
370 u16 fw_sb_id, u8 sb_index,
374 int index_offset = CHIP_IS_E2(bp) ?
375 offsetof(struct hc_status_block_data_e2, index_data) :
376 offsetof(struct hc_status_block_data_e1x, index_data);
377 u32 addr = BAR_CSTRORM_INTMEM +
378 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
380 sizeof(struct hc_index_data)*sb_index +
381 offsetof(struct hc_index_data, timeout);
382 REG_WR8(bp, addr, ticks);
383 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
384 port, fw_sb_id, sb_index, ticks);
386 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
387 u16 fw_sb_id, u8 sb_index,
390 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
391 int index_offset = CHIP_IS_E2(bp) ?
392 offsetof(struct hc_status_block_data_e2, index_data) :
393 offsetof(struct hc_status_block_data_e1x, index_data);
394 u32 addr = BAR_CSTRORM_INTMEM +
395 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
397 sizeof(struct hc_index_data)*sb_index +
398 offsetof(struct hc_index_data, flags);
399 u16 flags = REG_RD16(bp, addr);
401 flags &= ~HC_INDEX_DATA_HC_ENABLED;
402 flags |= enable_flag;
403 REG_WR16(bp, addr, flags);
404 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
405 port, fw_sb_id, sb_index, disable);
409 * locking is done by mcp
411 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
413 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
414 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
415 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
416 PCICFG_VENDOR_ID_OFFSET);
419 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
423 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
424 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
425 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
426 PCICFG_VENDOR_ID_OFFSET);
431 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
432 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
433 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
434 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
435 #define DMAE_DP_DST_NONE "dst_addr [none]"
437 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
440 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
442 switch (dmae->opcode & DMAE_COMMAND_DST) {
443 case DMAE_CMD_DST_PCI:
444 if (src_type == DMAE_CMD_SRC_PCI)
445 DP(msglvl, "DMAE: opcode 0x%08x\n"
446 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
447 "comp_addr [%x:%08x], comp_val 0x%08x\n",
448 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
449 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
450 dmae->comp_addr_hi, dmae->comp_addr_lo,
453 DP(msglvl, "DMAE: opcode 0x%08x\n"
454 "src [%08x], len [%d*4], dst [%x:%08x]\n"
455 "comp_addr [%x:%08x], comp_val 0x%08x\n",
456 dmae->opcode, dmae->src_addr_lo >> 2,
457 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
458 dmae->comp_addr_hi, dmae->comp_addr_lo,
461 case DMAE_CMD_DST_GRC:
462 if (src_type == DMAE_CMD_SRC_PCI)
463 DP(msglvl, "DMAE: opcode 0x%08x\n"
464 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
465 "comp_addr [%x:%08x], comp_val 0x%08x\n",
466 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
467 dmae->len, dmae->dst_addr_lo >> 2,
468 dmae->comp_addr_hi, dmae->comp_addr_lo,
471 DP(msglvl, "DMAE: opcode 0x%08x\n"
472 "src [%08x], len [%d*4], dst [%08x]\n"
473 "comp_addr [%x:%08x], comp_val 0x%08x\n",
474 dmae->opcode, dmae->src_addr_lo >> 2,
475 dmae->len, dmae->dst_addr_lo >> 2,
476 dmae->comp_addr_hi, dmae->comp_addr_lo,
480 if (src_type == DMAE_CMD_SRC_PCI)
481 DP(msglvl, "DMAE: opcode 0x%08x\n"
482 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
484 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
485 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
486 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
489 DP(msglvl, "DMAE: opcode 0x%08x\n"
490 DP_LEVEL "src_addr [%08x] len [%d * 4] "
492 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
493 dmae->opcode, dmae->src_addr_lo >> 2,
494 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
501 const u32 dmae_reg_go_c[] = {
502 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
503 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
504 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
505 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
508 /* copy command into DMAE command memory and set DMAE command go */
509 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
514 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
515 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
516 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
518 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
519 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
521 REG_WR(bp, dmae_reg_go_c[idx], 1);
524 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
526 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
530 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
532 return opcode & ~DMAE_CMD_SRC_RESET;
535 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
536 bool with_comp, u8 comp_type)
540 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
541 (dst_type << DMAE_COMMAND_DST_SHIFT));
543 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
545 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
546 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
547 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
548 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
551 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
553 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
556 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
560 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
561 struct dmae_command *dmae,
562 u8 src_type, u8 dst_type)
564 memset(dmae, 0, sizeof(struct dmae_command));
567 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
568 true, DMAE_COMP_PCI);
570 /* fill in the completion parameters */
571 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
572 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
573 dmae->comp_val = DMAE_COMP_VAL;
576 /* issue a dmae command over the init-channel and wailt for completion */
577 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
578 struct dmae_command *dmae)
580 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
581 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 40;
584 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
585 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
586 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
588 /* lock the dmae channel */
589 mutex_lock(&bp->dmae_mutex);
591 /* reset completion */
594 /* post the command on the channel used for initializations */
595 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
597 /* wait for completion */
599 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
600 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
603 BNX2X_ERR("DMAE timeout!\n");
610 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
611 BNX2X_ERR("DMAE PCI error!\n");
615 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
616 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
617 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
620 mutex_unlock(&bp->dmae_mutex);
624 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
627 struct dmae_command dmae;
629 if (!bp->dmae_ready) {
630 u32 *data = bnx2x_sp(bp, wb_data[0]);
632 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
633 " using indirect\n", dst_addr, len32);
634 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
641 /* fill in addresses and len */
642 dmae.src_addr_lo = U64_LO(dma_addr);
643 dmae.src_addr_hi = U64_HI(dma_addr);
644 dmae.dst_addr_lo = dst_addr >> 2;
645 dmae.dst_addr_hi = 0;
648 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
650 /* issue the command and wait for completion */
651 bnx2x_issue_dmae_with_comp(bp, &dmae);
654 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
656 struct dmae_command dmae;
658 if (!bp->dmae_ready) {
659 u32 *data = bnx2x_sp(bp, wb_data[0]);
662 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
663 " using indirect\n", src_addr, len32);
664 for (i = 0; i < len32; i++)
665 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
669 /* set opcode and fixed command fields */
670 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
672 /* fill in addresses and len */
673 dmae.src_addr_lo = src_addr >> 2;
674 dmae.src_addr_hi = 0;
675 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
676 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
679 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
681 /* issue the command and wait for completion */
682 bnx2x_issue_dmae_with_comp(bp, &dmae);
685 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
688 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
691 while (len > dmae_wr_max) {
692 bnx2x_write_dmae(bp, phys_addr + offset,
693 addr + offset, dmae_wr_max);
694 offset += dmae_wr_max * 4;
698 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
701 /* used only for slowpath so not inlined */
702 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
706 wb_write[0] = val_hi;
707 wb_write[1] = val_lo;
708 REG_WR_DMAE(bp, reg, wb_write, 2);
712 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
716 REG_RD_DMAE(bp, reg, wb_data, 2);
718 return HILO_U64(wb_data[0], wb_data[1]);
722 static int bnx2x_mc_assert(struct bnx2x *bp)
726 u32 row0, row1, row2, row3;
729 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
730 XSTORM_ASSERT_LIST_INDEX_OFFSET);
732 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
734 /* print the asserts */
735 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
737 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
738 XSTORM_ASSERT_LIST_OFFSET(i));
739 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
740 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
741 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
742 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
743 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
744 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
746 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
747 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
748 " 0x%08x 0x%08x 0x%08x\n",
749 i, row3, row2, row1, row0);
757 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
758 TSTORM_ASSERT_LIST_INDEX_OFFSET);
760 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
762 /* print the asserts */
763 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
765 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
766 TSTORM_ASSERT_LIST_OFFSET(i));
767 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
768 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
769 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
770 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
771 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
772 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
774 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
775 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
776 " 0x%08x 0x%08x 0x%08x\n",
777 i, row3, row2, row1, row0);
785 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
786 CSTORM_ASSERT_LIST_INDEX_OFFSET);
788 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
790 /* print the asserts */
791 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
793 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
794 CSTORM_ASSERT_LIST_OFFSET(i));
795 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
796 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
797 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
798 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
799 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
800 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
802 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
803 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
804 " 0x%08x 0x%08x 0x%08x\n",
805 i, row3, row2, row1, row0);
813 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
814 USTORM_ASSERT_LIST_INDEX_OFFSET);
816 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
818 /* print the asserts */
819 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
821 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
822 USTORM_ASSERT_LIST_OFFSET(i));
823 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
824 USTORM_ASSERT_LIST_OFFSET(i) + 4);
825 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
826 USTORM_ASSERT_LIST_OFFSET(i) + 8);
827 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
828 USTORM_ASSERT_LIST_OFFSET(i) + 12);
830 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
831 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
832 " 0x%08x 0x%08x 0x%08x\n",
833 i, row3, row2, row1, row0);
843 static void bnx2x_fw_dump(struct bnx2x *bp)
849 u32 trace_shmem_base;
851 BNX2X_ERR("NO MCP - can not dump\n");
855 if (BP_PATH(bp) == 0)
856 trace_shmem_base = bp->common.shmem_base;
858 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
859 addr = trace_shmem_base - 0x0800 + 4;
860 mark = REG_RD(bp, addr);
861 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
862 + ((mark + 0x3) & ~0x3) - 0x08000000;
863 pr_err("begin fw dump (mark 0x%x)\n", mark);
866 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
867 for (word = 0; word < 8; word++)
868 data[word] = htonl(REG_RD(bp, offset + 4*word));
870 pr_cont("%s", (char *)data);
872 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
873 for (word = 0; word < 8; word++)
874 data[word] = htonl(REG_RD(bp, offset + 4*word));
876 pr_cont("%s", (char *)data);
878 pr_err("end of fw dump\n");
881 void bnx2x_panic_dump(struct bnx2x *bp)
885 struct hc_sp_status_block_data sp_sb_data;
886 int func = BP_FUNC(bp);
887 #ifdef BNX2X_STOP_ON_ERROR
888 u16 start = 0, end = 0;
891 bp->stats_state = STATS_STATE_DISABLED;
892 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
894 BNX2X_ERR("begin crash dump -----------------\n");
898 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
899 " spq_prod_idx(0x%x)\n",
900 bp->def_idx, bp->def_att_idx,
901 bp->attn_state, bp->spq_prod_idx);
902 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
903 bp->def_status_blk->atten_status_block.attn_bits,
904 bp->def_status_blk->atten_status_block.attn_bits_ack,
905 bp->def_status_blk->atten_status_block.status_block_id,
906 bp->def_status_blk->atten_status_block.attn_bits_index);
908 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
910 bp->def_status_blk->sp_sb.index_values[i],
911 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
913 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
914 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
918 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
919 "pf_id(0x%x) vnic_id(0x%x) "
920 "vf_id(0x%x) vf_valid (0x%x)\n",
921 sp_sb_data.igu_sb_id,
922 sp_sb_data.igu_seg_id,
923 sp_sb_data.p_func.pf_id,
924 sp_sb_data.p_func.vnic_id,
925 sp_sb_data.p_func.vf_id,
926 sp_sb_data.p_func.vf_valid);
929 for_each_eth_queue(bp, i) {
930 struct bnx2x_fastpath *fp = &bp->fp[i];
932 struct hc_status_block_data_e2 sb_data_e2;
933 struct hc_status_block_data_e1x sb_data_e1x;
934 struct hc_status_block_sm *hc_sm_p =
936 sb_data_e2.common.state_machine :
937 sb_data_e1x.common.state_machine;
938 struct hc_index_data *hc_index_p =
940 sb_data_e2.index_data :
941 sb_data_e1x.index_data;
946 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
947 " rx_comp_prod(0x%x)"
948 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
949 i, fp->rx_bd_prod, fp->rx_bd_cons,
951 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
952 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
953 " fp_hc_idx(0x%x)\n",
954 fp->rx_sge_prod, fp->last_max_sge,
955 le16_to_cpu(fp->fp_hc_idx));
958 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
959 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
960 " *tx_cons_sb(0x%x)\n",
961 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
962 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
964 loop = CHIP_IS_E2(bp) ?
965 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
973 BNX2X_ERR(" run indexes (");
974 for (j = 0; j < HC_SB_MAX_SM; j++)
976 fp->sb_running_index[j],
977 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
979 BNX2X_ERR(" indexes (");
980 for (j = 0; j < loop; j++)
982 fp->sb_index_values[j],
983 (j == loop - 1) ? ")" : " ");
985 data_size = CHIP_IS_E2(bp) ?
986 sizeof(struct hc_status_block_data_e2) :
987 sizeof(struct hc_status_block_data_e1x);
988 data_size /= sizeof(u32);
989 sb_data_p = CHIP_IS_E2(bp) ?
992 /* copy sb data in here */
993 for (j = 0; j < data_size; j++)
994 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
995 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
998 if (CHIP_IS_E2(bp)) {
999 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1000 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1001 sb_data_e2.common.p_func.pf_id,
1002 sb_data_e2.common.p_func.vf_id,
1003 sb_data_e2.common.p_func.vf_valid,
1004 sb_data_e2.common.p_func.vnic_id,
1005 sb_data_e2.common.same_igu_sb_1b);
1007 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1008 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1009 sb_data_e1x.common.p_func.pf_id,
1010 sb_data_e1x.common.p_func.vf_id,
1011 sb_data_e1x.common.p_func.vf_valid,
1012 sb_data_e1x.common.p_func.vnic_id,
1013 sb_data_e1x.common.same_igu_sb_1b);
1017 for (j = 0; j < HC_SB_MAX_SM; j++) {
1018 pr_cont("SM[%d] __flags (0x%x) "
1019 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1020 "time_to_expire (0x%x) "
1021 "timer_value(0x%x)\n", j,
1023 hc_sm_p[j].igu_sb_id,
1024 hc_sm_p[j].igu_seg_id,
1025 hc_sm_p[j].time_to_expire,
1026 hc_sm_p[j].timer_value);
1030 for (j = 0; j < loop; j++) {
1031 pr_cont("INDEX[%d] flags (0x%x) "
1032 "timeout (0x%x)\n", j,
1033 hc_index_p[j].flags,
1034 hc_index_p[j].timeout);
1038 #ifdef BNX2X_STOP_ON_ERROR
1041 for_each_rx_queue(bp, i) {
1042 struct bnx2x_fastpath *fp = &bp->fp[i];
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046 for (j = start; j != end; j = RX_BD(j + 1)) {
1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1075 for_each_tx_queue(bp, i) {
1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1078 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1079 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1080 for (j = start; j != end; j = TX_BD(j + 1)) {
1081 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1083 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1084 i, j, sw_bd->skb, sw_bd->first_bd);
1087 start = TX_BD(fp->tx_bd_cons - 10);
1088 end = TX_BD(fp->tx_bd_cons + 254);
1089 for (j = start; j != end; j = TX_BD(j + 1)) {
1090 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1092 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1093 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1098 bnx2x_mc_assert(bp);
1099 BNX2X_ERR("end crash dump -----------------\n");
1102 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1104 int port = BP_PORT(bp);
1105 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1106 u32 val = REG_RD(bp, addr);
1107 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1108 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1111 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1112 HC_CONFIG_0_REG_INT_LINE_EN_0);
1113 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1114 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1116 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1117 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1118 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1119 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1121 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1122 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1123 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1124 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1126 if (!CHIP_IS_E1(bp)) {
1127 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1130 REG_WR(bp, addr, val);
1132 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1137 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1139 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1140 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1142 REG_WR(bp, addr, val);
1144 * Ensure that HC_CONFIG is written before leading/trailing edge config
1149 if (!CHIP_IS_E1(bp)) {
1150 /* init leading/trailing edge */
1152 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1154 /* enable nig and gpio3 attention */
1159 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1160 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1163 /* Make sure that interrupts are indeed enabled from here on */
1167 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1170 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1171 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1173 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1176 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1177 IGU_PF_CONF_SINGLE_ISR_EN);
1178 val |= (IGU_PF_CONF_FUNC_EN |
1179 IGU_PF_CONF_MSI_MSIX_EN |
1180 IGU_PF_CONF_ATTN_BIT_EN);
1182 val &= ~IGU_PF_CONF_INT_LINE_EN;
1183 val |= (IGU_PF_CONF_FUNC_EN |
1184 IGU_PF_CONF_MSI_MSIX_EN |
1185 IGU_PF_CONF_ATTN_BIT_EN |
1186 IGU_PF_CONF_SINGLE_ISR_EN);
1188 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1189 val |= (IGU_PF_CONF_FUNC_EN |
1190 IGU_PF_CONF_INT_LINE_EN |
1191 IGU_PF_CONF_ATTN_BIT_EN |
1192 IGU_PF_CONF_SINGLE_ISR_EN);
1195 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1196 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1198 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1202 /* init leading/trailing edge */
1204 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1206 /* enable nig and gpio3 attention */
1211 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1212 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1214 /* Make sure that interrupts are indeed enabled from here on */
1218 void bnx2x_int_enable(struct bnx2x *bp)
1220 if (bp->common.int_block == INT_BLOCK_HC)
1221 bnx2x_hc_int_enable(bp);
1223 bnx2x_igu_int_enable(bp);
1226 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1228 int port = BP_PORT(bp);
1229 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1230 u32 val = REG_RD(bp, addr);
1233 * in E1 we must use only PCI configuration space to disable
1234 * MSI/MSIX capablility
1235 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1237 if (CHIP_IS_E1(bp)) {
1238 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1239 * Use mask register to prevent from HC sending interrupts
1240 * after we exit the function
1242 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1244 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1245 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1246 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1248 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1249 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1250 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1251 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1253 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1256 /* flush all outstanding writes */
1259 REG_WR(bp, addr, val);
1260 if (REG_RD(bp, addr) != val)
1261 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1264 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1266 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1268 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1269 IGU_PF_CONF_INT_LINE_EN |
1270 IGU_PF_CONF_ATTN_BIT_EN);
1272 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1274 /* flush all outstanding writes */
1277 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1278 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1279 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1282 static void bnx2x_int_disable(struct bnx2x *bp)
1284 if (bp->common.int_block == INT_BLOCK_HC)
1285 bnx2x_hc_int_disable(bp);
1287 bnx2x_igu_int_disable(bp);
1290 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1292 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1295 /* disable interrupt handling */
1296 atomic_inc(&bp->intr_sem);
1297 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1300 /* prevent the HW from sending interrupts */
1301 bnx2x_int_disable(bp);
1303 /* make sure all ISRs are done */
1305 synchronize_irq(bp->msix_table[0].vector);
1310 for_each_eth_queue(bp, i)
1311 synchronize_irq(bp->msix_table[i + offset].vector);
1313 synchronize_irq(bp->pdev->irq);
1315 /* make sure sp_task is not running */
1316 cancel_delayed_work(&bp->sp_task);
1317 flush_workqueue(bnx2x_wq);
1323 * General service functions
1326 /* Return true if succeeded to acquire the lock */
1327 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1330 u32 resource_bit = (1 << resource);
1331 int func = BP_FUNC(bp);
1332 u32 hw_lock_control_reg;
1334 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1336 /* Validating that the resource is within range */
1337 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1339 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1340 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1345 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1347 hw_lock_control_reg =
1348 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1350 /* Try to acquire the lock */
1351 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1352 lock_status = REG_RD(bp, hw_lock_control_reg);
1353 if (lock_status & resource_bit)
1356 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1361 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1364 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1365 union eth_rx_cqe *rr_cqe)
1367 struct bnx2x *bp = fp->bp;
1368 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1369 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1372 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1373 fp->index, cid, command, bp->state,
1374 rr_cqe->ramrod_cqe.ramrod_type);
1376 switch (command | fp->state) {
1377 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1378 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1379 fp->state = BNX2X_FP_STATE_OPEN;
1382 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1383 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1384 fp->state = BNX2X_FP_STATE_HALTED;
1387 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1388 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1389 fp->state = BNX2X_FP_STATE_TERMINATED;
1393 BNX2X_ERR("unexpected MC reply (%d) "
1394 "fp[%d] state is %x\n",
1395 command, fp->index, fp->state);
1399 smp_mb__before_atomic_inc();
1400 atomic_inc(&bp->spq_left);
1401 /* push the change in fp->state and towards the memory */
1407 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1409 struct bnx2x *bp = netdev_priv(dev_instance);
1410 u16 status = bnx2x_ack_int(bp);
1414 /* Return here if interrupt is shared and it's not for us */
1415 if (unlikely(status == 0)) {
1416 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1419 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1421 /* Return here if interrupt is disabled */
1422 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1423 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1427 #ifdef BNX2X_STOP_ON_ERROR
1428 if (unlikely(bp->panic))
1432 for_each_eth_queue(bp, i) {
1433 struct bnx2x_fastpath *fp = &bp->fp[i];
1435 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1436 if (status & mask) {
1437 /* Handle Rx and Tx according to SB id */
1438 prefetch(fp->rx_cons_sb);
1439 prefetch(fp->tx_cons_sb);
1440 prefetch(&fp->sb_running_index[SM_RX_ID]);
1441 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1448 if (status & (mask | 0x1)) {
1449 struct cnic_ops *c_ops = NULL;
1452 c_ops = rcu_dereference(bp->cnic_ops);
1454 c_ops->cnic_handler(bp->cnic_data, NULL);
1461 if (unlikely(status & 0x1)) {
1462 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1469 if (unlikely(status))
1470 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1476 /* end of fast path */
1482 * General service functions
1485 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1488 u32 resource_bit = (1 << resource);
1489 int func = BP_FUNC(bp);
1490 u32 hw_lock_control_reg;
1493 /* Validating that the resource is within range */
1494 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1496 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1497 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1502 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1504 hw_lock_control_reg =
1505 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1508 /* Validating that the resource is not already taken */
1509 lock_status = REG_RD(bp, hw_lock_control_reg);
1510 if (lock_status & resource_bit) {
1511 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1512 lock_status, resource_bit);
1516 /* Try for 5 second every 5ms */
1517 for (cnt = 0; cnt < 1000; cnt++) {
1518 /* Try to acquire the lock */
1519 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1520 lock_status = REG_RD(bp, hw_lock_control_reg);
1521 if (lock_status & resource_bit)
1526 DP(NETIF_MSG_HW, "Timeout\n");
1530 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1533 u32 resource_bit = (1 << resource);
1534 int func = BP_FUNC(bp);
1535 u32 hw_lock_control_reg;
1537 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1539 /* Validating that the resource is within range */
1540 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1542 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1543 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1548 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1550 hw_lock_control_reg =
1551 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1554 /* Validating that the resource is currently taken */
1555 lock_status = REG_RD(bp, hw_lock_control_reg);
1556 if (!(lock_status & resource_bit)) {
1557 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1558 lock_status, resource_bit);
1562 REG_WR(bp, hw_lock_control_reg, resource_bit);
1567 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1569 /* The GPIO should be swapped if swap register is set and active */
1570 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1571 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1572 int gpio_shift = gpio_num +
1573 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1574 u32 gpio_mask = (1 << gpio_shift);
1578 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1579 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1583 /* read GPIO value */
1584 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1586 /* get the requested pin value */
1587 if ((gpio_reg & gpio_mask) == gpio_mask)
1592 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1597 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1599 /* The GPIO should be swapped if swap register is set and active */
1600 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1601 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1602 int gpio_shift = gpio_num +
1603 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1604 u32 gpio_mask = (1 << gpio_shift);
1607 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1608 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1612 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1613 /* read GPIO and mask except the float bits */
1614 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1617 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1618 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1619 gpio_num, gpio_shift);
1620 /* clear FLOAT and set CLR */
1621 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1622 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1625 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1626 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1627 gpio_num, gpio_shift);
1628 /* clear FLOAT and set SET */
1629 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1633 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1634 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1635 gpio_num, gpio_shift);
1637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1644 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1645 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1650 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1652 /* The GPIO should be swapped if swap register is set and active */
1653 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1654 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1655 int gpio_shift = gpio_num +
1656 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1657 u32 gpio_mask = (1 << gpio_shift);
1660 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1661 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1665 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1667 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1670 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1671 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1672 "output low\n", gpio_num, gpio_shift);
1673 /* clear SET and set CLR */
1674 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1675 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1678 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1679 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1680 "output high\n", gpio_num, gpio_shift);
1681 /* clear CLR and set SET */
1682 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1683 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1690 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1691 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1696 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1698 u32 spio_mask = (1 << spio_num);
1701 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1702 (spio_num > MISC_REGISTERS_SPIO_7)) {
1703 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1707 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1708 /* read SPIO and mask except the float bits */
1709 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1712 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1714 /* clear FLOAT and set CLR */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1719 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1721 /* clear FLOAT and set SET */
1722 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1723 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1726 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1727 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1729 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1736 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1737 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1742 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1744 u32 sel_phy_idx = 0;
1745 if (bp->link_vars.link_up) {
1746 sel_phy_idx = EXT_PHY1;
1747 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1748 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1749 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1750 sel_phy_idx = EXT_PHY2;
1753 switch (bnx2x_phy_selection(&bp->link_params)) {
1754 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1755 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1756 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1757 sel_phy_idx = EXT_PHY1;
1759 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1760 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1761 sel_phy_idx = EXT_PHY2;
1766 * The selected actived PHY is always after swapping (in case PHY
1767 * swapping is enabled). So when swapping is enabled, we need to reverse
1771 if (bp->link_params.multi_phy_config &
1772 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1773 if (sel_phy_idx == EXT_PHY1)
1774 sel_phy_idx = EXT_PHY2;
1775 else if (sel_phy_idx == EXT_PHY2)
1776 sel_phy_idx = EXT_PHY1;
1778 return LINK_CONFIG_IDX(sel_phy_idx);
1781 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1783 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1784 switch (bp->link_vars.ieee_fc &
1785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1786 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1787 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1791 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1792 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1796 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1797 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1801 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1807 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1809 if (!BP_NOMCP(bp)) {
1811 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1812 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1813 /* Initialize link parameters structure variables */
1814 /* It is recommended to turn off RX FC for jumbo frames
1815 for better performance */
1816 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1817 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1819 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1821 bnx2x_acquire_phy_lock(bp);
1823 if (load_mode == LOAD_DIAG) {
1824 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1825 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1828 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1830 bnx2x_release_phy_lock(bp);
1832 bnx2x_calc_fc_adv(bp);
1834 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1835 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1836 bnx2x_link_report(bp);
1838 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1841 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1845 void bnx2x_link_set(struct bnx2x *bp)
1847 if (!BP_NOMCP(bp)) {
1848 bnx2x_acquire_phy_lock(bp);
1849 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1850 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1851 bnx2x_release_phy_lock(bp);
1853 bnx2x_calc_fc_adv(bp);
1855 BNX2X_ERR("Bootcode is missing - can not set link\n");
1858 static void bnx2x__link_reset(struct bnx2x *bp)
1860 if (!BP_NOMCP(bp)) {
1861 bnx2x_acquire_phy_lock(bp);
1862 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1863 bnx2x_release_phy_lock(bp);
1865 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1868 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1872 if (!BP_NOMCP(bp)) {
1873 bnx2x_acquire_phy_lock(bp);
1874 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1876 bnx2x_release_phy_lock(bp);
1878 BNX2X_ERR("Bootcode is missing - can not test link\n");
1883 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1885 u32 r_param = bp->link_vars.line_speed / 8;
1886 u32 fair_periodic_timeout_usec;
1889 memset(&(bp->cmng.rs_vars), 0,
1890 sizeof(struct rate_shaping_vars_per_port));
1891 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1893 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1894 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1896 /* this is the threshold below which no timer arming will occur
1897 1.25 coefficient is for the threshold to be a little bigger
1898 than the real time, to compensate for timer in-accuracy */
1899 bp->cmng.rs_vars.rs_threshold =
1900 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1902 /* resolution of fairness timer */
1903 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1904 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1905 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1907 /* this is the threshold below which we won't arm the timer anymore */
1908 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1910 /* we multiply by 1e3/8 to get bytes/msec.
1911 We don't want the credits to pass a credit
1912 of the t_fair*FAIR_MEM (algorithm resolution) */
1913 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1914 /* since each tick is 4 usec */
1915 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1918 /* Calculates the sum of vn_min_rates.
1919 It's needed for further normalizing of the min_rates.
1921 sum of vn_min_rates.
1923 0 - if all the min_rates are 0.
1924 In the later case fainess algorithm should be deactivated.
1925 If not all min_rates are zero then those that are zeroes will be set to 1.
1927 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1932 bp->vn_weight_sum = 0;
1933 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1934 u32 vn_cfg = bp->mf_config[vn];
1935 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1936 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1938 /* Skip hidden vns */
1939 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1942 /* If min rate is zero - set it to 1 */
1944 vn_min_rate = DEF_MIN_RATE;
1948 bp->vn_weight_sum += vn_min_rate;
1951 /* ... only if all min rates are zeros - disable fairness */
1953 bp->cmng.flags.cmng_enables &=
1954 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1956 " fairness will be disabled\n");
1958 bp->cmng.flags.cmng_enables |=
1959 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1962 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1964 struct rate_shaping_vars_per_vn m_rs_vn;
1965 struct fairness_vars_per_vn m_fair_vn;
1966 u32 vn_cfg = bp->mf_config[vn];
1967 int func = 2*vn + BP_PORT(bp);
1968 u16 vn_min_rate, vn_max_rate;
1971 /* If function is hidden - set min and max to zeroes */
1972 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1977 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1978 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1979 /* If min rate is zero - set it to 1 */
1980 if (bp->vn_weight_sum && (vn_min_rate == 0))
1981 vn_min_rate = DEF_MIN_RATE;
1982 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1983 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
1987 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1988 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1990 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1991 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1993 /* global vn counter - maximal Mbps for this vn */
1994 m_rs_vn.vn_counter.rate = vn_max_rate;
1996 /* quota - number of bytes transmitted in this period */
1997 m_rs_vn.vn_counter.quota =
1998 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2000 if (bp->vn_weight_sum) {
2001 /* credit for each period of the fairness algorithm:
2002 number of bytes in T_FAIR (the vn share the port rate).
2003 vn_weight_sum should not be larger than 10000, thus
2004 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2006 m_fair_vn.vn_credit_delta =
2007 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2008 (8 * bp->vn_weight_sum))),
2009 (bp->cmng.fair_vars.fair_threshold * 2));
2010 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2011 m_fair_vn.vn_credit_delta);
2014 /* Store it to internal memory */
2015 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2016 REG_WR(bp, BAR_XSTRORM_INTMEM +
2017 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2018 ((u32 *)(&m_rs_vn))[i]);
2020 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2021 REG_WR(bp, BAR_XSTRORM_INTMEM +
2022 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2023 ((u32 *)(&m_fair_vn))[i]);
2026 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2028 if (CHIP_REV_IS_SLOW(bp))
2029 return CMNG_FNS_NONE;
2031 return CMNG_FNS_MINMAX;
2033 return CMNG_FNS_NONE;
2036 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
2038 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2041 return; /* what should be the default bvalue in this case */
2043 /* For 2 port configuration the absolute function number formula
2045 * abs_func = 2 * vn + BP_PORT + BP_PATH
2047 * and there are 4 functions per port
2049 * For 4 port configuration it is
2050 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2052 * and there are 2 functions per port
2054 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2055 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2057 if (func >= E1H_FUNC_MAX)
2061 MF_CFG_RD(bp, func_mf_config[func].config);
2065 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2068 if (cmng_type == CMNG_FNS_MINMAX) {
2071 /* clear cmng_enables */
2072 bp->cmng.flags.cmng_enables = 0;
2074 /* read mf conf from shmem */
2076 bnx2x_read_mf_cfg(bp);
2078 /* Init rate shaping and fairness contexts */
2079 bnx2x_init_port_minmax(bp);
2081 /* vn_weight_sum and enable fairness if not 0 */
2082 bnx2x_calc_vn_weight_sum(bp);
2084 /* calculate and set min-max rate for each vn */
2085 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2086 bnx2x_init_vn_minmax(bp, vn);
2088 /* always enable rate shaping and fairness */
2089 bp->cmng.flags.cmng_enables |=
2090 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2091 if (!bp->vn_weight_sum)
2092 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2093 " fairness will be disabled\n");
2097 /* rate shaping and fairness are disabled */
2099 "rate shaping and fairness are disabled\n");
2102 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2104 int port = BP_PORT(bp);
2108 /* Set the attention towards other drivers on the same port */
2109 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2110 if (vn == BP_E1HVN(bp))
2113 func = ((vn << 1) | port);
2114 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2115 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2119 /* This function is called upon link interrupt */
2120 static void bnx2x_link_attn(struct bnx2x *bp)
2122 u32 prev_link_status = bp->link_vars.link_status;
2123 /* Make sure that we are synced with the current statistics */
2124 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2126 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2128 if (bp->link_vars.link_up) {
2130 /* dropless flow control */
2131 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2132 int port = BP_PORT(bp);
2133 u32 pause_enabled = 0;
2135 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2138 REG_WR(bp, BAR_USTRORM_INTMEM +
2139 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2143 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2144 struct host_port_stats *pstats;
2146 pstats = bnx2x_sp(bp, port_stats);
2147 /* reset old bmac stats */
2148 memset(&(pstats->mac_stx[0]), 0,
2149 sizeof(struct mac_stx));
2151 if (bp->state == BNX2X_STATE_OPEN)
2152 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2155 /* indicate link status only if link status actually changed */
2156 if (prev_link_status != bp->link_vars.link_status)
2157 bnx2x_link_report(bp);
2160 bnx2x_link_sync_notify(bp);
2162 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2163 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2165 if (cmng_fns != CMNG_FNS_NONE) {
2166 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2167 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2169 /* rate shaping and fairness are disabled */
2171 "single function mode without fairness\n");
2175 void bnx2x__link_status_update(struct bnx2x *bp)
2177 if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
2180 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2182 if (bp->link_vars.link_up)
2183 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2185 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2187 /* the link status update could be the result of a DCC event
2188 hence re-read the shmem mf configuration */
2189 bnx2x_read_mf_cfg(bp);
2191 /* indicate link status */
2192 bnx2x_link_report(bp);
2195 static void bnx2x_pmf_update(struct bnx2x *bp)
2197 int port = BP_PORT(bp);
2201 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2203 /* enable nig attention */
2204 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2205 if (bp->common.int_block == INT_BLOCK_HC) {
2206 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2207 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2208 } else if (CHIP_IS_E2(bp)) {
2209 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2210 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2213 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2221 * General service functions
2224 /* send the MCP a request, block until there is a reply */
2225 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2227 int mb_idx = BP_FW_MB_IDX(bp);
2228 u32 seq = ++bp->fw_seq;
2231 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2233 mutex_lock(&bp->fw_mb_mutex);
2234 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2235 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2237 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2240 /* let the FW do it's magic ... */
2243 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2245 /* Give the FW up to 5 second (500*10ms) */
2246 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2248 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2249 cnt*delay, rc, seq);
2251 /* is this a reply to our command? */
2252 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2253 rc &= FW_MSG_CODE_MASK;
2256 BNX2X_ERR("FW failed to respond!\n");
2260 mutex_unlock(&bp->fw_mb_mutex);
2265 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2268 if (IS_FCOE_FP(fp) && IS_MF(bp))
2274 /* must be called under rtnl_lock */
2275 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2277 u32 mask = (1 << cl_id);
2279 /* initial seeting is BNX2X_ACCEPT_NONE */
2280 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2281 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2282 u8 unmatched_unicast = 0;
2284 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2285 unmatched_unicast = 1;
2287 if (filters & BNX2X_PROMISCUOUS_MODE) {
2288 /* promiscious - accept all, drop none */
2289 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2290 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2293 * SI mode defines to accept in promiscuos mode
2294 * only unmatched packets
2296 unmatched_unicast = 1;
2300 if (filters & BNX2X_ACCEPT_UNICAST) {
2301 /* accept matched ucast */
2304 if (filters & BNX2X_ACCEPT_MULTICAST) {
2305 /* accept matched mcast */
2308 /* since mcast addresses won't arrive with ovlan,
2309 * fw needs to accept all of them in
2310 * switch-independent mode */
2313 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2314 /* accept all mcast */
2318 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2319 /* accept all mcast */
2323 if (filters & BNX2X_ACCEPT_BROADCAST) {
2324 /* accept (all) bcast */
2329 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2330 bp->mac_filters.ucast_drop_all | mask :
2331 bp->mac_filters.ucast_drop_all & ~mask;
2333 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2334 bp->mac_filters.mcast_drop_all | mask :
2335 bp->mac_filters.mcast_drop_all & ~mask;
2337 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2338 bp->mac_filters.bcast_drop_all | mask :
2339 bp->mac_filters.bcast_drop_all & ~mask;
2341 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2342 bp->mac_filters.ucast_accept_all | mask :
2343 bp->mac_filters.ucast_accept_all & ~mask;
2345 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2346 bp->mac_filters.mcast_accept_all | mask :
2347 bp->mac_filters.mcast_accept_all & ~mask;
2349 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2350 bp->mac_filters.bcast_accept_all | mask :
2351 bp->mac_filters.bcast_accept_all & ~mask;
2353 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2354 bp->mac_filters.unmatched_unicast | mask :
2355 bp->mac_filters.unmatched_unicast & ~mask;
2358 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2360 struct tstorm_eth_function_common_config tcfg = {0};
2364 if (p->func_flgs & FUNC_FLG_TPA)
2365 tcfg.config_flags |=
2366 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2369 rss_flgs = (p->rss->mode <<
2370 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2372 if (p->rss->cap & RSS_IPV4_CAP)
2373 rss_flgs |= RSS_IPV4_CAP_MASK;
2374 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2375 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2376 if (p->rss->cap & RSS_IPV6_CAP)
2377 rss_flgs |= RSS_IPV6_CAP_MASK;
2378 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2379 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2381 tcfg.config_flags |= rss_flgs;
2382 tcfg.rss_result_mask = p->rss->result_mask;
2384 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2386 /* Enable the function in the FW */
2387 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2388 storm_memset_func_en(bp, p->func_id, 1);
2391 if (p->func_flgs & FUNC_FLG_STATS) {
2392 struct stats_indication_flags stats_flags = {0};
2393 stats_flags.collect_eth = 1;
2395 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2396 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2398 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2399 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2401 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2402 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2404 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2405 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2409 if (p->func_flgs & FUNC_FLG_SPQ) {
2410 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2411 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2412 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2416 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2417 struct bnx2x_fastpath *fp)
2421 /* calculate queue flags */
2422 flags |= QUEUE_FLG_CACHE_ALIGN;
2423 flags |= QUEUE_FLG_HC;
2424 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2426 flags |= QUEUE_FLG_VLAN;
2427 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2429 if (!fp->disable_tpa)
2430 flags |= QUEUE_FLG_TPA;
2432 flags = stat_counter_valid(bp, fp) ?
2433 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2438 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2439 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2440 struct bnx2x_rxq_init_params *rxq_init)
2444 u16 tpa_agg_size = 0;
2446 /* calculate queue flags */
2447 u16 flags = bnx2x_get_cl_flags(bp, fp);
2449 if (!fp->disable_tpa) {
2450 pause->sge_th_hi = 250;
2451 pause->sge_th_lo = 150;
2452 tpa_agg_size = min_t(u32,
2453 (min_t(u32, 8, MAX_SKB_FRAGS) *
2454 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2455 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2457 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2458 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2459 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2463 /* pause - not for e1 */
2464 if (!CHIP_IS_E1(bp)) {
2465 pause->bd_th_hi = 350;
2466 pause->bd_th_lo = 250;
2467 pause->rcq_th_hi = 350;
2468 pause->rcq_th_lo = 250;
2469 pause->sge_th_hi = 0;
2470 pause->sge_th_lo = 0;
2475 rxq_init->flags = flags;
2476 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2477 rxq_init->dscr_map = fp->rx_desc_mapping;
2478 rxq_init->sge_map = fp->rx_sge_mapping;
2479 rxq_init->rcq_map = fp->rx_comp_mapping;
2480 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2481 rxq_init->mtu = bp->dev->mtu;
2482 rxq_init->buf_sz = bp->rx_buf_size;
2483 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2484 rxq_init->cl_id = fp->cl_id;
2485 rxq_init->spcl_id = fp->cl_id;
2486 rxq_init->stat_id = fp->cl_id;
2487 rxq_init->tpa_agg_sz = tpa_agg_size;
2488 rxq_init->sge_buf_sz = sge_sz;
2489 rxq_init->max_sges_pkt = max_sge;
2490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2491 rxq_init->fw_sb_id = fp->fw_sb_id;
2494 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2496 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2498 rxq_init->cid = HW_CID(bp, fp->cid);
2500 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2503 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2504 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2506 u16 flags = bnx2x_get_cl_flags(bp, fp);
2508 txq_init->flags = flags;
2509 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2510 txq_init->dscr_map = fp->tx_desc_mapping;
2511 txq_init->stat_id = fp->cl_id;
2512 txq_init->cid = HW_CID(bp, fp->cid);
2513 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2514 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2515 txq_init->fw_sb_id = fp->fw_sb_id;
2517 if (IS_FCOE_FP(fp)) {
2518 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2519 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2522 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2525 static void bnx2x_pf_init(struct bnx2x *bp)
2527 struct bnx2x_func_init_params func_init = {0};
2528 struct bnx2x_rss_params rss = {0};
2529 struct event_ring_data eq_data = { {0} };
2532 /* pf specific setups */
2533 if (!CHIP_IS_E1(bp))
2534 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2536 if (CHIP_IS_E2(bp)) {
2537 /* reset IGU PF statistics: MSIX + ATTN */
2539 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2540 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2541 (CHIP_MODE_IS_4_PORT(bp) ?
2542 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2544 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2545 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2546 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2547 (CHIP_MODE_IS_4_PORT(bp) ?
2548 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2551 /* function setup flags */
2552 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2554 if (CHIP_IS_E1x(bp))
2555 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2557 flags |= FUNC_FLG_TPA;
2559 /* function setup */
2562 * Although RSS is meaningless when there is a single HW queue we
2563 * still need it enabled in order to have HW Rx hash generated.
2565 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2566 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2567 rss.mode = bp->multi_mode;
2568 rss.result_mask = MULTI_MASK;
2569 func_init.rss = &rss;
2571 func_init.func_flgs = flags;
2572 func_init.pf_id = BP_FUNC(bp);
2573 func_init.func_id = BP_FUNC(bp);
2574 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2575 func_init.spq_map = bp->spq_mapping;
2576 func_init.spq_prod = bp->spq_prod_idx;
2578 bnx2x_func_init(bp, &func_init);
2580 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2583 Congestion management values depend on the link rate
2584 There is no active link so initial link rate is set to 10 Gbps.
2585 When the link comes up The congestion management values are
2586 re-calculated according to the actual link rate.
2588 bp->link_vars.line_speed = SPEED_10000;
2589 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2591 /* Only the PMF sets the HW */
2593 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2595 /* no rx until link is up */
2596 bp->rx_mode = BNX2X_RX_MODE_NONE;
2597 bnx2x_set_storm_rx_mode(bp);
2599 /* init Event Queue */
2600 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2601 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2602 eq_data.producer = bp->eq_prod;
2603 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2604 eq_data.sb_id = DEF_SB_ID;
2605 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2609 static void bnx2x_e1h_disable(struct bnx2x *bp)
2611 int port = BP_PORT(bp);
2613 netif_tx_disable(bp->dev);
2615 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2617 netif_carrier_off(bp->dev);
2620 static void bnx2x_e1h_enable(struct bnx2x *bp)
2622 int port = BP_PORT(bp);
2624 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2626 /* Tx queue should be only reenabled */
2627 netif_tx_wake_all_queues(bp->dev);
2630 * Should not call netif_carrier_on since it will be called if the link
2631 * is up when checking for link state
2635 /* called due to MCP event (on pmf):
2636 * reread new bandwidth configuration
2638 * notify others function about the change
2640 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2642 if (bp->link_vars.link_up) {
2643 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2644 bnx2x_link_sync_notify(bp);
2646 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2649 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2651 bnx2x_config_mf_bw(bp);
2652 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2655 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2657 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2659 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2662 * This is the only place besides the function initialization
2663 * where the bp->flags can change so it is done without any
2666 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2667 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2668 bp->flags |= MF_FUNC_DIS;
2670 bnx2x_e1h_disable(bp);
2672 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2673 bp->flags &= ~MF_FUNC_DIS;
2675 bnx2x_e1h_enable(bp);
2677 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2679 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2680 bnx2x_config_mf_bw(bp);
2681 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2684 /* Report results to MCP */
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2688 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2691 /* must be called under the spq lock */
2692 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2694 struct eth_spe *next_spe = bp->spq_prod_bd;
2696 if (bp->spq_prod_bd == bp->spq_last_bd) {
2697 bp->spq_prod_bd = bp->spq;
2698 bp->spq_prod_idx = 0;
2699 DP(NETIF_MSG_TIMER, "end of spq\n");
2707 /* must be called under the spq lock */
2708 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2710 int func = BP_FUNC(bp);
2712 /* Make sure that BD data is updated before writing the producer */
2715 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2720 /* the slow path queue is odd since completions arrive on the fastpath ring */
2721 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2722 u32 data_hi, u32 data_lo, int common)
2724 struct eth_spe *spe;
2727 #ifdef BNX2X_STOP_ON_ERROR
2728 if (unlikely(bp->panic))
2732 spin_lock_bh(&bp->spq_lock);
2734 if (!atomic_read(&bp->spq_left)) {
2735 BNX2X_ERR("BUG! SPQ ring full!\n");
2736 spin_unlock_bh(&bp->spq_lock);
2741 spe = bnx2x_sp_get_next(bp);
2743 /* CID needs port number to be encoded int it */
2744 spe->hdr.conn_and_cmd_data =
2745 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2750 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2751 * TRAFFIC_STOP, TRAFFIC_START
2753 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2754 & SPE_HDR_CONN_TYPE;
2756 /* ETH ramrods: SETUP, HALT */
2757 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2758 & SPE_HDR_CONN_TYPE;
2760 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2761 SPE_HDR_FUNCTION_ID);
2763 spe->hdr.type = cpu_to_le16(type);
2765 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2766 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2768 /* stats ramrod has it's own slot on the spq */
2769 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY)
2770 /* It's ok if the actual decrement is issued towards the memory
2771 * somewhere between the spin_lock and spin_unlock. Thus no
2772 * more explict memory barrier is needed.
2774 atomic_dec(&bp->spq_left);
2776 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2777 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2778 "type(0x%x) left %x\n",
2779 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2780 (u32)(U64_LO(bp->spq_mapping) +
2781 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2782 HW_CID(bp, cid), data_hi, data_lo, type, atomic_read(&bp->spq_left));
2784 bnx2x_sp_prod_update(bp);
2785 spin_unlock_bh(&bp->spq_lock);
2789 /* acquire split MCP access lock register */
2790 static int bnx2x_acquire_alr(struct bnx2x *bp)
2796 for (j = 0; j < 1000; j++) {
2798 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2799 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2800 if (val & (1L << 31))
2805 if (!(val & (1L << 31))) {
2806 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2813 /* release split MCP access lock register */
2814 static void bnx2x_release_alr(struct bnx2x *bp)
2816 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2819 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2820 #define BNX2X_DEF_SB_IDX 0x0002
2822 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2824 struct host_sp_status_block *def_sb = bp->def_status_blk;
2827 barrier(); /* status block is written to by the chip */
2828 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2829 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2830 rc |= BNX2X_DEF_SB_ATT_IDX;
2833 if (bp->def_idx != def_sb->sp_sb.running_index) {
2834 bp->def_idx = def_sb->sp_sb.running_index;
2835 rc |= BNX2X_DEF_SB_IDX;
2838 /* Do not reorder: indecies reading should complete before handling */
2844 * slow path service functions
2847 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2849 int port = BP_PORT(bp);
2850 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2851 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2852 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2853 NIG_REG_MASK_INTERRUPT_PORT0;
2858 if (bp->attn_state & asserted)
2859 BNX2X_ERR("IGU ERROR\n");
2861 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2862 aeu_mask = REG_RD(bp, aeu_addr);
2864 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2865 aeu_mask, asserted);
2866 aeu_mask &= ~(asserted & 0x3ff);
2867 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2869 REG_WR(bp, aeu_addr, aeu_mask);
2870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2872 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2873 bp->attn_state |= asserted;
2874 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2876 if (asserted & ATTN_HARD_WIRED_MASK) {
2877 if (asserted & ATTN_NIG_FOR_FUNC) {
2879 bnx2x_acquire_phy_lock(bp);
2881 /* save nig interrupt mask */
2882 nig_mask = REG_RD(bp, nig_int_mask_addr);
2883 REG_WR(bp, nig_int_mask_addr, 0);
2885 bnx2x_link_attn(bp);
2887 /* handle unicore attn? */
2889 if (asserted & ATTN_SW_TIMER_4_FUNC)
2890 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2892 if (asserted & GPIO_2_FUNC)
2893 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2895 if (asserted & GPIO_3_FUNC)
2896 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2898 if (asserted & GPIO_4_FUNC)
2899 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2902 if (asserted & ATTN_GENERAL_ATTN_1) {
2903 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2904 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2906 if (asserted & ATTN_GENERAL_ATTN_2) {
2907 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2908 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2910 if (asserted & ATTN_GENERAL_ATTN_3) {
2911 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2912 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2915 if (asserted & ATTN_GENERAL_ATTN_4) {
2916 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2917 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2919 if (asserted & ATTN_GENERAL_ATTN_5) {
2920 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2921 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2923 if (asserted & ATTN_GENERAL_ATTN_6) {
2924 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2925 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2929 } /* if hardwired */
2931 if (bp->common.int_block == INT_BLOCK_HC)
2932 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2933 COMMAND_REG_ATTN_BITS_SET);
2935 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2937 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2938 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2939 REG_WR(bp, reg_addr, asserted);
2941 /* now set back the mask */
2942 if (asserted & ATTN_NIG_FOR_FUNC) {
2943 REG_WR(bp, nig_int_mask_addr, nig_mask);
2944 bnx2x_release_phy_lock(bp);
2948 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2950 int port = BP_PORT(bp);
2952 /* mark the failure */
2955 dev_info.port_hw_config[port].external_phy_config);
2957 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2958 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2959 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2962 /* log the failure */
2963 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2964 " the driver to shutdown the card to prevent permanent"
2965 " damage. Please contact OEM Support for assistance\n");
2968 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2970 int port = BP_PORT(bp);
2974 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2975 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2977 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2979 val = REG_RD(bp, reg_offset);
2980 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2981 REG_WR(bp, reg_offset, val);
2983 BNX2X_ERR("SPIO5 hw attention\n");
2985 /* Fan failure attention */
2986 bnx2x_hw_reset_phy(&bp->link_params);
2987 bnx2x_fan_failure(bp);
2990 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
2991 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
2992 bnx2x_acquire_phy_lock(bp);
2993 bnx2x_handle_module_detect_int(&bp->link_params);
2994 bnx2x_release_phy_lock(bp);
2997 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2999 val = REG_RD(bp, reg_offset);
3000 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3001 REG_WR(bp, reg_offset, val);
3003 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3004 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3009 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3013 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3015 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3016 BNX2X_ERR("DB hw attention 0x%x\n", val);
3017 /* DORQ discard attention */
3019 BNX2X_ERR("FATAL error from DORQ\n");
3022 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3024 int port = BP_PORT(bp);
3027 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3028 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3030 val = REG_RD(bp, reg_offset);
3031 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3032 REG_WR(bp, reg_offset, val);
3034 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3035 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3040 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3044 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3046 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3047 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3048 /* CFC error attention */
3050 BNX2X_ERR("FATAL error from CFC\n");
3053 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3055 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3056 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3057 /* RQ_USDMDP_FIFO_OVERFLOW */
3059 BNX2X_ERR("FATAL error from PXP\n");
3060 if (CHIP_IS_E2(bp)) {
3061 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3062 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3066 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3068 int port = BP_PORT(bp);
3071 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3072 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3074 val = REG_RD(bp, reg_offset);
3075 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3076 REG_WR(bp, reg_offset, val);
3078 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3079 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3084 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3088 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3090 if (attn & BNX2X_PMF_LINK_ASSERT) {
3091 int func = BP_FUNC(bp);
3093 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3094 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3095 func_mf_config[BP_ABS_FUNC(bp)].config);
3097 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3098 if (val & DRV_STATUS_DCC_EVENT_MASK)
3100 (val & DRV_STATUS_DCC_EVENT_MASK));
3102 if (val & DRV_STATUS_SET_MF_BW)
3103 bnx2x_set_mf_bw(bp);
3105 bnx2x__link_status_update(bp);
3106 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3107 bnx2x_pmf_update(bp);
3110 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3111 bp->dcbx_enabled > 0)
3112 /* start dcbx state machine */
3113 bnx2x_dcbx_set_params(bp,
3114 BNX2X_DCBX_STATE_NEG_RECEIVED);
3115 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3117 BNX2X_ERR("MC assert!\n");
3118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3119 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3120 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3121 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3124 } else if (attn & BNX2X_MCP_ASSERT) {
3126 BNX2X_ERR("MCP assert!\n");
3127 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3131 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3134 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3135 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3136 if (attn & BNX2X_GRC_TIMEOUT) {
3137 val = CHIP_IS_E1(bp) ? 0 :
3138 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3139 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3141 if (attn & BNX2X_GRC_RSV) {
3142 val = CHIP_IS_E1(bp) ? 0 :
3143 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3144 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3146 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3150 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3151 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3152 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3153 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3154 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3157 * should be run under rtnl lock
3159 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3161 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3162 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3163 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3169 * should be run under rtnl lock
3171 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3173 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3175 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3181 * should be run under rtnl lock
3183 bool bnx2x_reset_is_done(struct bnx2x *bp)
3185 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3186 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3187 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3191 * should be run under rtnl lock
3193 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3195 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3197 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3199 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3200 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3206 * should be run under rtnl lock
3208 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3214 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3223 * should be run under rtnl lock
3225 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3227 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3230 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3232 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3233 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3236 static inline void _print_next_block(int idx, const char *blk)
3243 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3247 for (i = 0; sig; i++) {
3248 cur_bit = ((u32)0x1 << i);
3249 if (sig & cur_bit) {
3251 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3252 _print_next_block(par_num++, "BRB");
3254 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3255 _print_next_block(par_num++, "PARSER");
3257 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3258 _print_next_block(par_num++, "TSDM");
3260 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3261 _print_next_block(par_num++, "SEARCHER");
3263 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3264 _print_next_block(par_num++, "TSEMI");
3276 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3280 for (i = 0; sig; i++) {
3281 cur_bit = ((u32)0x1 << i);
3282 if (sig & cur_bit) {
3284 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3285 _print_next_block(par_num++, "PBCLIENT");
3287 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3288 _print_next_block(par_num++, "QM");
3290 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3291 _print_next_block(par_num++, "XSDM");
3293 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3294 _print_next_block(par_num++, "XSEMI");
3296 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3297 _print_next_block(par_num++, "DOORBELLQ");
3299 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3300 _print_next_block(par_num++, "VAUX PCI CORE");
3302 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3303 _print_next_block(par_num++, "DEBUG");
3305 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "USDM");
3308 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "USEMI");
3311 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3312 _print_next_block(par_num++, "UPB");
3314 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3315 _print_next_block(par_num++, "CSDM");
3327 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3331 for (i = 0; sig; i++) {
3332 cur_bit = ((u32)0x1 << i);
3333 if (sig & cur_bit) {
3335 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3336 _print_next_block(par_num++, "CSEMI");
3338 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3339 _print_next_block(par_num++, "PXP");
3341 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3342 _print_next_block(par_num++,
3343 "PXPPCICLOCKCLIENT");
3345 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3346 _print_next_block(par_num++, "CFC");
3348 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3349 _print_next_block(par_num++, "CDU");
3351 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3352 _print_next_block(par_num++, "IGU");
3354 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3355 _print_next_block(par_num++, "MISC");
3367 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3371 for (i = 0; sig; i++) {
3372 cur_bit = ((u32)0x1 << i);
3373 if (sig & cur_bit) {
3375 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3376 _print_next_block(par_num++, "MCP ROM");
3378 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3379 _print_next_block(par_num++, "MCP UMP RX");
3381 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3382 _print_next_block(par_num++, "MCP UMP TX");
3384 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3385 _print_next_block(par_num++, "MCP SCPAD");
3397 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3400 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3401 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3403 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3404 "[0]:0x%08x [1]:0x%08x "
3405 "[2]:0x%08x [3]:0x%08x\n",
3406 sig0 & HW_PRTY_ASSERT_SET_0,
3407 sig1 & HW_PRTY_ASSERT_SET_1,
3408 sig2 & HW_PRTY_ASSERT_SET_2,
3409 sig3 & HW_PRTY_ASSERT_SET_3);
3410 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3412 par_num = bnx2x_print_blocks_with_parity0(
3413 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3414 par_num = bnx2x_print_blocks_with_parity1(
3415 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3416 par_num = bnx2x_print_blocks_with_parity2(
3417 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3418 par_num = bnx2x_print_blocks_with_parity3(
3419 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3426 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3428 struct attn_route attn;
3429 int port = BP_PORT(bp);
3431 attn.sig[0] = REG_RD(bp,
3432 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3434 attn.sig[1] = REG_RD(bp,
3435 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3437 attn.sig[2] = REG_RD(bp,
3438 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3440 attn.sig[3] = REG_RD(bp,
3441 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3444 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3449 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3452 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3454 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3455 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3456 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3457 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3459 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3460 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3461 "INCORRECT_RCV_BEHAVIOR\n");
3462 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3463 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3464 "WAS_ERROR_ATTN\n");
3465 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3466 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3467 "VF_LENGTH_VIOLATION_ATTN\n");
3469 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3470 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3471 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3473 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3474 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3475 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3477 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3478 "TCPL_ERROR_ATTN\n");
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3480 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3481 "TCPL_IN_TWO_RCBS_ATTN\n");
3482 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3483 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3484 "CSSNOOP_FIFO_OVERFLOW\n");
3486 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3487 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3488 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3489 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3490 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3491 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3492 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3493 "_ATC_TCPL_TO_NOT_PEND\n");
3494 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3495 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3496 "ATC_GPA_MULTIPLE_HITS\n");
3497 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3498 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3499 "ATC_RCPL_TO_EMPTY_CNT\n");
3500 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3501 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3502 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3503 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3504 "ATC_IREQ_LESS_THAN_STU\n");
3507 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3508 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3509 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3510 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3511 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3516 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3518 struct attn_route attn, *group_mask;
3519 int port = BP_PORT(bp);
3525 /* need to take HW lock because MCP or other port might also
3526 try to handle this event */
3527 bnx2x_acquire_alr(bp);
3529 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
3530 bp->recovery_state = BNX2X_RECOVERY_INIT;
3531 bnx2x_set_reset_in_progress(bp);
3532 schedule_delayed_work(&bp->reset_task, 0);
3533 /* Disable HW interrupts */
3534 bnx2x_int_disable(bp);
3535 bnx2x_release_alr(bp);
3536 /* In case of parity errors don't handle attentions so that
3537 * other function would "see" parity errors.
3542 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3543 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3544 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3545 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3548 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3552 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3553 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3555 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3556 if (deasserted & (1 << index)) {
3557 group_mask = &bp->attn_group[index];
3559 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3562 group_mask->sig[0], group_mask->sig[1],
3563 group_mask->sig[2], group_mask->sig[3],
3564 group_mask->sig[4]);
3566 bnx2x_attn_int_deasserted4(bp,
3567 attn.sig[4] & group_mask->sig[4]);
3568 bnx2x_attn_int_deasserted3(bp,
3569 attn.sig[3] & group_mask->sig[3]);
3570 bnx2x_attn_int_deasserted1(bp,
3571 attn.sig[1] & group_mask->sig[1]);
3572 bnx2x_attn_int_deasserted2(bp,
3573 attn.sig[2] & group_mask->sig[2]);
3574 bnx2x_attn_int_deasserted0(bp,
3575 attn.sig[0] & group_mask->sig[0]);
3579 bnx2x_release_alr(bp);
3581 if (bp->common.int_block == INT_BLOCK_HC)
3582 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3583 COMMAND_REG_ATTN_BITS_CLR);
3585 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3588 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3589 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3590 REG_WR(bp, reg_addr, val);
3592 if (~bp->attn_state & deasserted)
3593 BNX2X_ERR("IGU ERROR\n");
3595 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3596 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3598 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3599 aeu_mask = REG_RD(bp, reg_addr);
3601 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3602 aeu_mask, deasserted);
3603 aeu_mask |= (deasserted & 0x3ff);
3604 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3606 REG_WR(bp, reg_addr, aeu_mask);
3607 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3609 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3610 bp->attn_state &= ~deasserted;
3611 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3614 static void bnx2x_attn_int(struct bnx2x *bp)
3616 /* read local copy of bits */
3617 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3619 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3621 u32 attn_state = bp->attn_state;
3623 /* look for changed bits */
3624 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3625 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3628 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3629 attn_bits, attn_ack, asserted, deasserted);
3631 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3632 BNX2X_ERR("BAD attention state\n");
3634 /* handle bits that were raised */
3636 bnx2x_attn_int_asserted(bp, asserted);
3639 bnx2x_attn_int_deasserted(bp, deasserted);
3642 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3644 /* No memory barriers */
3645 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3646 mmiowb(); /* keep prod updates ordered */
3650 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3651 union event_ring_elem *elem)
3653 if (!bp->cnic_eth_dev.starting_cid ||
3654 cid < bp->cnic_eth_dev.starting_cid)
3657 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3659 if (unlikely(elem->message.data.cfc_del_event.error)) {
3660 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3662 bnx2x_panic_dump(bp);
3664 bnx2x_cnic_cfc_comp(bp, cid);
3669 static void bnx2x_eq_int(struct bnx2x *bp)
3671 u16 hw_cons, sw_cons, sw_prod;
3672 union event_ring_elem *elem;
3677 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3679 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3680 * when we get the the next-page we nned to adjust so the loop
3681 * condition below will be met. The next element is the size of a
3682 * regular element and hence incrementing by 1
3684 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3687 /* This function may never run in parralel with itself for a
3688 * specific bp, thus there is no need in "paired" read memory
3691 sw_cons = bp->eq_cons;
3692 sw_prod = bp->eq_prod;
3694 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->spq_left %u\n",
3695 hw_cons, sw_cons, atomic_read(&bp->spq_left));
3697 for (; sw_cons != hw_cons;
3698 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3701 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3703 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3704 opcode = elem->message.opcode;
3707 /* handle eq element */
3709 case EVENT_RING_OPCODE_STAT_QUERY:
3710 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3711 /* nothing to do with stats comp */
3714 case EVENT_RING_OPCODE_CFC_DEL:
3715 /* handle according to cid range */
3717 * we may want to verify here that the bp state is
3720 DP(NETIF_MSG_IFDOWN,
3721 "got delete ramrod for MULTI[%d]\n", cid);
3723 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3725 if (cid == BNX2X_FCOE_ETH_CID)
3726 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3729 bnx2x_fp(bp, cid, state) =
3730 BNX2X_FP_STATE_CLOSED;
3734 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3735 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3736 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3738 case EVENT_RING_OPCODE_START_TRAFFIC:
3739 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3740 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3744 switch (opcode | bp->state) {
3745 case (EVENT_RING_OPCODE_FUNCTION_START |
3746 BNX2X_STATE_OPENING_WAIT4_PORT):
3747 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3748 bp->state = BNX2X_STATE_FUNC_STARTED;
3751 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3752 BNX2X_STATE_CLOSING_WAIT4_HALT):
3753 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3754 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3757 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3758 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3759 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3760 bp->set_mac_pending = 0;
3763 case (EVENT_RING_OPCODE_SET_MAC |
3764 BNX2X_STATE_CLOSING_WAIT4_HALT):
3765 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3766 bp->set_mac_pending = 0;
3769 /* unknown event log error and continue */
3770 BNX2X_ERR("Unknown EQ event %d\n",
3771 elem->message.opcode);
3777 smp_mb__before_atomic_inc();
3778 atomic_add(spqe_cnt, &bp->spq_left);
3780 bp->eq_cons = sw_cons;
3781 bp->eq_prod = sw_prod;
3782 /* Make sure that above mem writes were issued towards the memory */
3785 /* update producer */
3786 bnx2x_update_eq_prod(bp, bp->eq_prod);
3789 static void bnx2x_sp_task(struct work_struct *work)
3791 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3794 /* Return here if interrupt is disabled */
3795 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3796 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3800 status = bnx2x_update_dsb_idx(bp);
3801 /* if (status == 0) */
3802 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3804 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3807 if (status & BNX2X_DEF_SB_ATT_IDX) {
3809 status &= ~BNX2X_DEF_SB_ATT_IDX;
3812 /* SP events: STAT_QUERY and others */
3813 if (status & BNX2X_DEF_SB_IDX) {
3815 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3817 if ((!NO_FCOE(bp)) &&
3818 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3819 napi_schedule(&bnx2x_fcoe(bp, napi));
3821 /* Handle EQ completions */
3824 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3825 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3827 status &= ~BNX2X_DEF_SB_IDX;
3830 if (unlikely(status))
3831 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3834 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3835 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3838 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3840 struct net_device *dev = dev_instance;
3841 struct bnx2x *bp = netdev_priv(dev);
3843 /* Return here if interrupt is disabled */
3844 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3845 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3849 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3850 IGU_INT_DISABLE, 0);
3852 #ifdef BNX2X_STOP_ON_ERROR
3853 if (unlikely(bp->panic))
3859 struct cnic_ops *c_ops;
3862 c_ops = rcu_dereference(bp->cnic_ops);
3864 c_ops->cnic_handler(bp->cnic_data, NULL);
3868 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3873 /* end of slow path */
3875 static void bnx2x_timer(unsigned long data)
3877 struct bnx2x *bp = (struct bnx2x *) data;
3879 if (!netif_running(bp->dev))
3882 if (atomic_read(&bp->intr_sem) != 0)
3886 struct bnx2x_fastpath *fp = &bp->fp[0];
3890 rc = bnx2x_rx_int(fp, 1000);
3893 if (!BP_NOMCP(bp)) {
3894 int mb_idx = BP_FW_MB_IDX(bp);
3898 ++bp->fw_drv_pulse_wr_seq;
3899 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3900 /* TBD - add SYSTEM_TIME */
3901 drv_pulse = bp->fw_drv_pulse_wr_seq;
3902 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3904 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3905 MCP_PULSE_SEQ_MASK);
3906 /* The delta between driver pulse and mcp response
3907 * should be 1 (before mcp response) or 0 (after mcp response)
3909 if ((drv_pulse != mcp_pulse) &&
3910 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3911 /* someone lost a heartbeat... */
3912 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3913 drv_pulse, mcp_pulse);
3917 if (bp->state == BNX2X_STATE_OPEN)
3918 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3921 mod_timer(&bp->timer, jiffies + bp->current_interval);
3924 /* end of Statistics */
3929 * nic init service functions
3932 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3935 if (!(len%4) && !(addr%4))
3936 for (i = 0; i < len; i += 4)
3937 REG_WR(bp, addr + i, fill);
3939 for (i = 0; i < len; i++)
3940 REG_WR8(bp, addr + i, fill);
3944 /* helper: writes FP SP data to FW - data_size in dwords */
3945 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3951 for (index = 0; index < data_size; index++)
3952 REG_WR(bp, BAR_CSTRORM_INTMEM +
3953 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3955 *(sb_data_p + index));
3958 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3962 struct hc_status_block_data_e2 sb_data_e2;
3963 struct hc_status_block_data_e1x sb_data_e1x;
3965 /* disable the function first */
3966 if (CHIP_IS_E2(bp)) {
3967 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3968 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3969 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3970 sb_data_e2.common.p_func.vf_valid = false;
3971 sb_data_p = (u32 *)&sb_data_e2;
3972 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3974 memset(&sb_data_e1x, 0,
3975 sizeof(struct hc_status_block_data_e1x));
3976 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3977 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3978 sb_data_e1x.common.p_func.vf_valid = false;
3979 sb_data_p = (u32 *)&sb_data_e1x;
3980 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3982 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
3984 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3985 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
3986 CSTORM_STATUS_BLOCK_SIZE);
3987 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
3988 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
3989 CSTORM_SYNC_BLOCK_SIZE);
3992 /* helper: writes SP SB data to FW */
3993 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
3994 struct hc_sp_status_block_data *sp_sb_data)
3996 int func = BP_FUNC(bp);
3998 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
3999 REG_WR(bp, BAR_CSTRORM_INTMEM +
4000 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4002 *((u32 *)sp_sb_data + i));
4005 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4007 int func = BP_FUNC(bp);
4008 struct hc_sp_status_block_data sp_sb_data;
4009 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4011 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4012 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4013 sp_sb_data.p_func.vf_valid = false;
4015 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4017 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4018 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4019 CSTORM_SP_STATUS_BLOCK_SIZE);
4020 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4021 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4022 CSTORM_SP_SYNC_BLOCK_SIZE);
4028 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4029 int igu_sb_id, int igu_seg_id)
4031 hc_sm->igu_sb_id = igu_sb_id;
4032 hc_sm->igu_seg_id = igu_seg_id;
4033 hc_sm->timer_value = 0xFF;
4034 hc_sm->time_to_expire = 0xFFFFFFFF;
4037 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4038 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4042 struct hc_status_block_data_e2 sb_data_e2;
4043 struct hc_status_block_data_e1x sb_data_e1x;
4044 struct hc_status_block_sm *hc_sm_p;
4045 struct hc_index_data *hc_index_p;
4049 if (CHIP_INT_MODE_IS_BC(bp))
4050 igu_seg_id = HC_SEG_ACCESS_NORM;
4052 igu_seg_id = IGU_SEG_ACCESS_NORM;
4054 bnx2x_zero_fp_sb(bp, fw_sb_id);
4056 if (CHIP_IS_E2(bp)) {
4057 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4058 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4059 sb_data_e2.common.p_func.vf_id = vfid;
4060 sb_data_e2.common.p_func.vf_valid = vf_valid;
4061 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4062 sb_data_e2.common.same_igu_sb_1b = true;
4063 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4064 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4065 hc_sm_p = sb_data_e2.common.state_machine;
4066 hc_index_p = sb_data_e2.index_data;
4067 sb_data_p = (u32 *)&sb_data_e2;
4068 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4070 memset(&sb_data_e1x, 0,
4071 sizeof(struct hc_status_block_data_e1x));
4072 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4073 sb_data_e1x.common.p_func.vf_id = 0xff;
4074 sb_data_e1x.common.p_func.vf_valid = false;
4075 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4076 sb_data_e1x.common.same_igu_sb_1b = true;
4077 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4078 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4079 hc_sm_p = sb_data_e1x.common.state_machine;
4080 hc_index_p = sb_data_e1x.index_data;
4081 sb_data_p = (u32 *)&sb_data_e1x;
4082 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4085 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4086 igu_sb_id, igu_seg_id);
4087 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4088 igu_sb_id, igu_seg_id);
4090 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4092 /* write indecies to HW */
4093 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4096 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4097 u8 sb_index, u8 disable, u16 usec)
4099 int port = BP_PORT(bp);
4100 u8 ticks = usec / BNX2X_BTR;
4102 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4104 disable = disable ? 1 : (usec ? 0 : 1);
4105 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4108 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4109 u16 tx_usec, u16 rx_usec)
4111 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4113 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4117 static void bnx2x_init_def_sb(struct bnx2x *bp)
4119 struct host_sp_status_block *def_sb = bp->def_status_blk;
4120 dma_addr_t mapping = bp->def_status_blk_mapping;
4121 int igu_sp_sb_index;
4123 int port = BP_PORT(bp);
4124 int func = BP_FUNC(bp);
4128 struct hc_sp_status_block_data sp_sb_data;
4129 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4131 if (CHIP_INT_MODE_IS_BC(bp)) {
4132 igu_sp_sb_index = DEF_SB_IGU_ID;
4133 igu_seg_id = HC_SEG_ACCESS_DEF;
4135 igu_sp_sb_index = bp->igu_dsb_id;
4136 igu_seg_id = IGU_SEG_ACCESS_DEF;
4140 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4141 atten_status_block);
4142 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4146 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4148 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4150 /* take care of sig[0]..sig[4] */
4151 for (sindex = 0; sindex < 4; sindex++)
4152 bp->attn_group[index].sig[sindex] =
4153 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4157 * enable5 is separate from the rest of the registers,
4158 * and therefore the address skip is 4
4159 * and not 16 between the different groups
4161 bp->attn_group[index].sig[4] = REG_RD(bp,
4162 reg_offset + 0x10 + 0x4*index);
4164 bp->attn_group[index].sig[4] = 0;
4167 if (bp->common.int_block == INT_BLOCK_HC) {
4168 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4169 HC_REG_ATTN_MSG0_ADDR_L);
4171 REG_WR(bp, reg_offset, U64_LO(section));
4172 REG_WR(bp, reg_offset + 4, U64_HI(section));
4173 } else if (CHIP_IS_E2(bp)) {
4174 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4175 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4178 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4181 bnx2x_zero_sp_sb(bp);
4183 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4184 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4185 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4186 sp_sb_data.igu_seg_id = igu_seg_id;
4187 sp_sb_data.p_func.pf_id = func;
4188 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4189 sp_sb_data.p_func.vf_id = 0xff;
4191 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4193 bp->stats_pending = 0;
4194 bp->set_mac_pending = 0;
4196 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4199 void bnx2x_update_coalesce(struct bnx2x *bp)
4203 for_each_eth_queue(bp, i)
4204 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4205 bp->rx_ticks, bp->tx_ticks);
4208 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4210 spin_lock_init(&bp->spq_lock);
4211 atomic_set(&bp->spq_left, MAX_SPQ_PENDING);
4213 bp->spq_prod_idx = 0;
4214 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4215 bp->spq_prod_bd = bp->spq;
4216 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4219 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4222 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4223 union event_ring_elem *elem =
4224 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4226 elem->next_page.addr.hi =
4227 cpu_to_le32(U64_HI(bp->eq_mapping +
4228 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4229 elem->next_page.addr.lo =
4230 cpu_to_le32(U64_LO(bp->eq_mapping +
4231 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4234 bp->eq_prod = NUM_EQ_DESC;
4235 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4238 static void bnx2x_init_ind_table(struct bnx2x *bp)
4240 int func = BP_FUNC(bp);
4243 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4247 "Initializing indirection table multi_mode %d\n", bp->multi_mode);
4248 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4249 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4250 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4251 bp->fp->cl_id + (i % (bp->num_queues -
4252 NONE_ETH_CONTEXT_USE)));
4255 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4257 int mode = bp->rx_mode;
4258 int port = BP_PORT(bp);
4260 u32 def_q_filters = 0;
4262 /* All but management unicast packets should pass to the host as well */
4264 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4265 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4266 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4267 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4270 case BNX2X_RX_MODE_NONE: /* no Rx */
4271 def_q_filters = BNX2X_ACCEPT_NONE;
4274 cl_id = bnx2x_fcoe(bp, cl_id);
4275 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4280 case BNX2X_RX_MODE_NORMAL:
4281 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4282 BNX2X_ACCEPT_MULTICAST;
4284 cl_id = bnx2x_fcoe(bp, cl_id);
4285 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4286 BNX2X_ACCEPT_MULTICAST);
4290 case BNX2X_RX_MODE_ALLMULTI:
4291 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4292 BNX2X_ACCEPT_ALL_MULTICAST;
4294 cl_id = bnx2x_fcoe(bp, cl_id);
4295 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4296 BNX2X_ACCEPT_MULTICAST);
4300 case BNX2X_RX_MODE_PROMISC:
4301 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4303 cl_id = bnx2x_fcoe(bp, cl_id);
4304 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
4305 BNX2X_ACCEPT_MULTICAST);
4307 /* pass management unicast packets as well */
4308 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4312 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4316 cl_id = BP_L_ID(bp);
4317 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4320 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4321 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4323 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4324 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4325 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4326 "unmatched_ucast 0x%x\n", mode,
4327 bp->mac_filters.ucast_drop_all,
4328 bp->mac_filters.mcast_drop_all,
4329 bp->mac_filters.bcast_drop_all,
4330 bp->mac_filters.ucast_accept_all,
4331 bp->mac_filters.mcast_accept_all,
4332 bp->mac_filters.bcast_accept_all,
4333 bp->mac_filters.unmatched_unicast
4336 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4339 static void bnx2x_init_internal_common(struct bnx2x *bp)
4343 if (!CHIP_IS_E1(bp)) {
4345 /* xstorm needs to know whether to add ovlan to packets or not,
4346 * in switch-independent we'll write 0 to here... */
4347 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4349 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4351 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4353 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4359 * In switch independent mode, the TSTORM needs to accept
4360 * packets that failed classification, since approximate match
4361 * mac addresses aren't written to NIG LLH
4363 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4364 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4366 /* Zero this manually as its initialization is
4367 currently missing in the initTool */
4368 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4369 REG_WR(bp, BAR_USTRORM_INTMEM +
4370 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4371 if (CHIP_IS_E2(bp)) {
4372 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4373 CHIP_INT_MODE_IS_BC(bp) ?
4374 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4378 static void bnx2x_init_internal_port(struct bnx2x *bp)
4381 bnx2x_dcb_init_intmem_pfc(bp);
4384 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4386 switch (load_code) {
4387 case FW_MSG_CODE_DRV_LOAD_COMMON:
4388 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4389 bnx2x_init_internal_common(bp);
4392 case FW_MSG_CODE_DRV_LOAD_PORT:
4393 bnx2x_init_internal_port(bp);
4396 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4397 /* internal memory per function is
4398 initialized inside bnx2x_pf_init */
4402 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4407 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4409 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4411 fp->state = BNX2X_FP_STATE_CLOSED;
4413 fp->index = fp->cid = fp_idx;
4414 fp->cl_id = BP_L_ID(bp) + fp_idx;
4415 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4416 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4417 /* qZone id equals to FW (per path) client id */
4418 fp->cl_qzone_id = fp->cl_id +
4419 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4420 ETH_MAX_RX_CLIENTS_E1H);
4422 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4423 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4424 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4425 /* Setup SB indicies */
4426 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4427 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4429 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4430 "cl_id %d fw_sb %d igu_sb %d\n",
4431 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4433 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4434 fp->fw_sb_id, fp->igu_sb_id);
4436 bnx2x_update_fpsb_idx(fp);
4439 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4443 for_each_eth_queue(bp, i)
4444 bnx2x_init_fp_sb(bp, i);
4447 bnx2x_init_fcoe_fp(bp);
4449 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4450 BNX2X_VF_ID_INVALID, false,
4451 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4455 /* ensure status block indices were read */
4458 bnx2x_init_def_sb(bp);
4459 bnx2x_update_dsb_idx(bp);
4460 bnx2x_init_rx_rings(bp);
4461 bnx2x_init_tx_rings(bp);
4462 bnx2x_init_sp_ring(bp);
4463 bnx2x_init_eq_ring(bp);
4464 bnx2x_init_internal(bp, load_code);
4466 bnx2x_init_ind_table(bp);
4467 bnx2x_stats_init(bp);
4469 /* At this point, we are ready for interrupts */
4470 atomic_set(&bp->intr_sem, 0);
4472 /* flush all before enabling interrupts */
4476 bnx2x_int_enable(bp);
4478 /* Check for SPIO5 */
4479 bnx2x_attn_int_deasserted0(bp,
4480 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4481 AEU_INPUTS_ATTN_BITS_SPIO5);
4484 /* end of nic init */
4487 * gzip service functions
4490 static int bnx2x_gunzip_init(struct bnx2x *bp)
4492 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4493 &bp->gunzip_mapping, GFP_KERNEL);
4494 if (bp->gunzip_buf == NULL)
4497 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4498 if (bp->strm == NULL)
4501 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4503 if (bp->strm->workspace == NULL)
4513 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4514 bp->gunzip_mapping);
4515 bp->gunzip_buf = NULL;
4518 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4519 " un-compression\n");
4523 static void bnx2x_gunzip_end(struct bnx2x *bp)
4525 kfree(bp->strm->workspace);
4529 if (bp->gunzip_buf) {
4530 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4531 bp->gunzip_mapping);
4532 bp->gunzip_buf = NULL;
4536 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4540 /* check gzip header */
4541 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4542 BNX2X_ERR("Bad gzip header\n");
4550 if (zbuf[3] & FNAME)
4551 while ((zbuf[n++] != 0) && (n < len));
4553 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4554 bp->strm->avail_in = len - n;
4555 bp->strm->next_out = bp->gunzip_buf;
4556 bp->strm->avail_out = FW_BUF_SIZE;
4558 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4562 rc = zlib_inflate(bp->strm, Z_FINISH);
4563 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4564 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4567 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4568 if (bp->gunzip_outlen & 0x3)
4569 netdev_err(bp->dev, "Firmware decompression error:"
4570 " gunzip_outlen (%d) not aligned\n",
4572 bp->gunzip_outlen >>= 2;
4574 zlib_inflateEnd(bp->strm);
4576 if (rc == Z_STREAM_END)
4582 /* nic load/unload */
4585 * General service functions
4588 /* send a NIG loopback debug packet */
4589 static void bnx2x_lb_pckt(struct bnx2x *bp)
4593 /* Ethernet source and destination addresses */
4594 wb_write[0] = 0x55555555;
4595 wb_write[1] = 0x55555555;
4596 wb_write[2] = 0x20; /* SOP */
4597 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4599 /* NON-IP protocol */
4600 wb_write[0] = 0x09000000;
4601 wb_write[1] = 0x55555555;
4602 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4603 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4606 /* some of the internal memories
4607 * are not directly readable from the driver
4608 * to test them we send debug packets
4610 static int bnx2x_int_mem_test(struct bnx2x *bp)
4616 if (CHIP_REV_IS_FPGA(bp))
4618 else if (CHIP_REV_IS_EMUL(bp))
4623 /* Disable inputs of parser neighbor blocks */
4624 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4625 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4626 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4627 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4629 /* Write 0 to parser credits for CFC search request */
4630 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4632 /* send Ethernet packet */
4635 /* TODO do i reset NIG statistic? */
4636 /* Wait until NIG register shows 1 packet of size 0x10 */
4637 count = 1000 * factor;
4640 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4641 val = *bnx2x_sp(bp, wb_data[0]);
4649 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4653 /* Wait until PRS register shows 1 packet */
4654 count = 1000 * factor;
4656 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4664 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4668 /* Reset and init BRB, PRS */
4669 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4673 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4674 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4676 DP(NETIF_MSG_HW, "part2\n");
4678 /* Disable inputs of parser neighbor blocks */
4679 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4680 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4681 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4682 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4684 /* Write 0 to parser credits for CFC search request */
4685 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4687 /* send 10 Ethernet packets */
4688 for (i = 0; i < 10; i++)
4691 /* Wait until NIG register shows 10 + 1
4692 packets of size 11*0x10 = 0xb0 */
4693 count = 1000 * factor;
4696 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4697 val = *bnx2x_sp(bp, wb_data[0]);
4705 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4709 /* Wait until PRS register shows 2 packets */
4710 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4712 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4714 /* Write 1 to parser credits for CFC search request */
4715 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4717 /* Wait until PRS register shows 3 packets */
4718 msleep(10 * factor);
4719 /* Wait until NIG register shows 1 packet of size 0x10 */
4720 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4722 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4724 /* clear NIG EOP FIFO */
4725 for (i = 0; i < 11; i++)
4726 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4727 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4729 BNX2X_ERR("clear of NIG failed\n");
4733 /* Reset and init BRB, PRS, NIG */
4734 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4736 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4738 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4739 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4742 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4745 /* Enable inputs of parser neighbor blocks */
4746 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4747 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4748 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4749 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4751 DP(NETIF_MSG_HW, "done\n");
4756 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
4758 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4760 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4762 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4763 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4764 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4766 * mask read length error interrupts in brb for parser
4767 * (parsing unit and 'checksum and crc' unit)
4768 * these errors are legal (PU reads fixed length and CAC can cause
4769 * read length error on truncated packets)
4771 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4772 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4773 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4774 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4775 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4776 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4777 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4778 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4779 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4780 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4781 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4782 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4783 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4784 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4785 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4786 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4787 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4788 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4789 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4791 if (CHIP_REV_IS_FPGA(bp))
4792 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4793 else if (CHIP_IS_E2(bp))
4794 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4795 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4796 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4797 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4798 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4799 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4801 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4802 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4803 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4804 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4805 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4806 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4807 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4808 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4809 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4810 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
4813 static void bnx2x_reset_common(struct bnx2x *bp)
4816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4818 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4821 static void bnx2x_init_pxp(struct bnx2x *bp)
4824 int r_order, w_order;
4826 pci_read_config_word(bp->pdev,
4827 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4828 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4829 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4831 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4833 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4837 bnx2x_init_pxp_arb(bp, r_order, w_order);
4840 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4850 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4851 SHARED_HW_CFG_FAN_FAILURE_MASK;
4853 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4857 * The fan failure mechanism is usually related to the PHY type since
4858 * the power consumption of the board is affected by the PHY. Currently,
4859 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4861 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4862 for (port = PORT_0; port < PORT_MAX; port++) {
4864 bnx2x_fan_failure_det_req(
4866 bp->common.shmem_base,
4867 bp->common.shmem2_base,
4871 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4873 if (is_required == 0)
4876 /* Fan failure is indicated by SPIO 5 */
4877 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4878 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4880 /* set to active low mode */
4881 val = REG_RD(bp, MISC_REG_SPIO_INT);
4882 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4883 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4884 REG_WR(bp, MISC_REG_SPIO_INT, val);
4886 /* enable interrupt to signal the IGU */
4887 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4888 val |= (1 << MISC_REGISTERS_SPIO_5);
4889 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4892 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4898 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4901 switch (BP_ABS_FUNC(bp)) {
4903 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4906 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4909 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4912 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4915 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4918 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4921 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4924 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4930 REG_WR(bp, offset, pretend_func_num);
4932 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4935 static void bnx2x_pf_disable(struct bnx2x *bp)
4937 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4938 val &= ~IGU_PF_CONF_FUNC_EN;
4940 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4941 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4942 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4945 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4949 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4951 bnx2x_reset_common(bp);
4952 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4953 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4955 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
4956 if (!CHIP_IS_E1(bp))
4957 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
4959 if (CHIP_IS_E2(bp)) {
4963 * 4-port mode or 2-port mode we need to turn of master-enable
4964 * for everyone, after that, turn it back on for self.
4965 * so, we disregard multi-function or not, and always disable
4966 * for all functions on the given path, this means 0,2,4,6 for
4967 * path 0 and 1,3,5,7 for path 1
4969 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
4970 if (fid == BP_ABS_FUNC(bp)) {
4972 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
4977 bnx2x_pretend_func(bp, fid);
4978 /* clear pf enable */
4979 bnx2x_pf_disable(bp);
4980 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
4984 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
4985 if (CHIP_IS_E1(bp)) {
4986 /* enable HW interrupt from PXP on USDM overflow
4987 bit 16 on INT_MASK_0 */
4988 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4991 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
4995 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
4996 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
4997 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
4998 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
4999 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5000 /* make sure this value is 0 */
5001 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5003 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5004 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5005 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5006 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5007 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5010 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5012 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5013 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5015 /* let the HW do it's magic ... */
5017 /* finish PXP init */
5018 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5020 BNX2X_ERR("PXP2 CFG failed\n");
5023 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5025 BNX2X_ERR("PXP2 RD_INIT failed\n");
5029 /* Timers bug workaround E2 only. We need to set the entire ILT to
5030 * have entries with value "0" and valid bit on.
5031 * This needs to be done by the first PF that is loaded in a path
5032 * (i.e. common phase)
5034 if (CHIP_IS_E2(bp)) {
5035 struct ilt_client_info ilt_cli;
5036 struct bnx2x_ilt ilt;
5037 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5038 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5040 /* initialize dummy TM client */
5042 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5043 ilt_cli.client_num = ILT_CLIENT_TM;
5045 /* Step 1: set zeroes to all ilt page entries with valid bit on
5046 * Step 2: set the timers first/last ilt entry to point
5047 * to the entire range to prevent ILT range error for 3rd/4th
5048 * vnic (this code assumes existance of the vnic)
5050 * both steps performed by call to bnx2x_ilt_client_init_op()
5051 * with dummy TM client
5053 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5054 * and his brother are split registers
5056 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5057 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5058 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5060 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5061 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5062 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5066 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5067 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5069 if (CHIP_IS_E2(bp)) {
5070 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5071 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5072 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5074 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5076 /* let the HW do it's magic ... */
5079 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5080 } while (factor-- && (val != 1));
5083 BNX2X_ERR("ATC_INIT failed\n");
5088 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5090 /* clean the DMAE memory */
5092 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5094 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5095 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5096 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5097 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5099 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5100 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5101 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5102 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5104 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5106 if (CHIP_MODE_IS_4_PORT(bp))
5107 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5109 /* QM queues pointers table */
5110 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5112 /* soft reset pulse */
5113 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5114 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5117 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5120 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5121 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5123 if (!CHIP_REV_IS_SLOW(bp)) {
5124 /* enable hw interrupt from doorbell Q */
5125 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5128 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5129 if (CHIP_MODE_IS_4_PORT(bp)) {
5130 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5131 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5134 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5135 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5138 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5140 if (!CHIP_IS_E1(bp))
5141 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5143 if (CHIP_IS_E2(bp)) {
5144 /* Bit-map indicating which L2 hdrs may appear after the
5145 basic Ethernet header */
5146 int has_ovlan = IS_MF_SD(bp);
5147 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5148 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5151 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5152 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5153 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5154 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5156 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5157 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5158 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5159 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5161 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5162 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5163 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5164 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5166 if (CHIP_MODE_IS_4_PORT(bp))
5167 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5170 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5172 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5175 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5176 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5177 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5179 if (CHIP_IS_E2(bp)) {
5180 int has_ovlan = IS_MF_SD(bp);
5181 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5182 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5185 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5186 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5187 REG_WR(bp, i, random32());
5189 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5191 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5192 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5193 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5194 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5195 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5196 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5197 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5198 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5199 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5200 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5202 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5204 if (sizeof(union cdu_context) != 1024)
5205 /* we currently assume that a context is 1024 bytes */
5206 dev_alert(&bp->pdev->dev, "please adjust the size "
5207 "of cdu_context(%ld)\n",
5208 (long)sizeof(union cdu_context));
5210 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5211 val = (4 << 24) + (0 << 12) + 1024;
5212 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5214 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5215 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5216 /* enable context validation interrupt from CFC */
5217 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5219 /* set the thresholds to prevent CFC/CDU race */
5220 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5222 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5224 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5225 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5227 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5228 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5230 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5231 /* Reset PCIE errors for debug */
5232 REG_WR(bp, 0x2814, 0xffffffff);
5233 REG_WR(bp, 0x3820, 0xffffffff);
5235 if (CHIP_IS_E2(bp)) {
5236 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5237 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5238 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5239 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5240 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5241 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5242 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5243 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5244 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5245 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5246 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5249 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5250 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5251 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5252 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5254 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5255 if (!CHIP_IS_E1(bp)) {
5256 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5257 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5259 if (CHIP_IS_E2(bp)) {
5260 /* Bit-map indicating which L2 hdrs may appear after the
5261 basic Ethernet header */
5262 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5265 if (CHIP_REV_IS_SLOW(bp))
5268 /* finish CFC init */
5269 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5271 BNX2X_ERR("CFC LL_INIT failed\n");
5274 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5276 BNX2X_ERR("CFC AC_INIT failed\n");
5279 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5281 BNX2X_ERR("CFC CAM_INIT failed\n");
5284 REG_WR(bp, CFC_REG_DEBUG0, 0);
5286 if (CHIP_IS_E1(bp)) {
5287 /* read NIG statistic
5288 to see if this is our first up since powerup */
5289 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5290 val = *bnx2x_sp(bp, wb_data[0]);
5292 /* do internal memory self test */
5293 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5294 BNX2X_ERR("internal mem self test failed\n");
5299 bnx2x_setup_fan_failure_detection(bp);
5301 /* clear PXP2 attentions */
5302 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5304 bnx2x_enable_blocks_attention(bp);
5305 if (CHIP_PARITY_ENABLED(bp))
5306 bnx2x_enable_blocks_parity(bp);
5308 if (!BP_NOMCP(bp)) {
5309 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5310 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5312 u32 shmem_base[2], shmem2_base[2];
5313 shmem_base[0] = bp->common.shmem_base;
5314 shmem2_base[0] = bp->common.shmem2_base;
5315 if (CHIP_IS_E2(bp)) {
5317 SHMEM2_RD(bp, other_shmem_base_addr);
5319 SHMEM2_RD(bp, other_shmem2_base_addr);
5321 bnx2x_acquire_phy_lock(bp);
5322 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5323 bp->common.chip_id);
5324 bnx2x_release_phy_lock(bp);
5327 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5332 static int bnx2x_init_hw_port(struct bnx2x *bp)
5334 int port = BP_PORT(bp);
5335 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5339 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5341 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5343 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5344 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5346 /* Timers bug workaround: disables the pf_master bit in pglue at
5347 * common phase, we need to enable it here before any dmae access are
5348 * attempted. Therefore we manually added the enable-master to the
5349 * port phase (it also happens in the function phase)
5352 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5354 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5355 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5356 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5357 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5359 /* QM cid (connection) count */
5360 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5363 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5364 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5365 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5368 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5370 if (CHIP_MODE_IS_4_PORT(bp))
5371 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5373 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5374 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5375 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5376 /* no pause for emulation and FPGA */
5381 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5382 else if (bp->dev->mtu > 4096) {
5383 if (bp->flags & ONE_PORT_FLAG)
5387 /* (24*1024 + val*4)/256 */
5388 low = 96 + (val/64) +
5389 ((val % 64) ? 1 : 0);
5392 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5393 high = low + 56; /* 14*1024/256 */
5395 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5396 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5399 if (CHIP_MODE_IS_4_PORT(bp)) {
5400 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5401 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5402 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5403 BRB1_REG_MAC_GUARANTIED_0), 40);
5406 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5408 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5409 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5410 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5411 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5413 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5414 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5415 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5416 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5417 if (CHIP_MODE_IS_4_PORT(bp))
5418 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5420 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5421 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5423 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5425 if (!CHIP_IS_E2(bp)) {
5426 /* configure PBF to work without PAUSE mtu 9000 */
5427 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5429 /* update threshold */
5430 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5431 /* update init credit */
5432 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5435 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5437 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5441 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5443 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5444 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5446 if (CHIP_IS_E1(bp)) {
5447 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5448 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5450 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5452 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5454 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5455 /* init aeu_mask_attn_func_0/1:
5456 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5457 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5458 * bits 4-7 are used for "per vn group attention" */
5459 val = IS_MF(bp) ? 0xF7 : 0x7;
5460 /* Enable DCBX attention for all but E1 */
5461 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5462 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5464 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5465 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5466 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5467 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5468 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5470 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5472 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5474 if (!CHIP_IS_E1(bp)) {
5475 /* 0x2 disable mf_ov, 0x1 enable */
5476 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5477 (IS_MF_SD(bp) ? 0x1 : 0x2));
5479 if (CHIP_IS_E2(bp)) {
5481 switch (bp->mf_mode) {
5482 case MULTI_FUNCTION_SD:
5485 case MULTI_FUNCTION_SI:
5490 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5491 NIG_REG_LLH0_CLS_TYPE), val);
5494 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5495 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5496 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5500 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5501 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5502 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5503 bp->common.shmem2_base, port)) {
5504 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5505 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5506 val = REG_RD(bp, reg_addr);
5507 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5508 REG_WR(bp, reg_addr, val);
5510 bnx2x__link_reset(bp);
5515 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5520 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5522 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5524 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5527 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5529 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5532 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5534 u32 i, base = FUNC_ILT_BASE(func);
5535 for (i = base; i < base + ILT_PER_FUNC; i++)
5536 bnx2x_ilt_wr(bp, i, 0);
5539 static int bnx2x_init_hw_func(struct bnx2x *bp)
5541 int port = BP_PORT(bp);
5542 int func = BP_FUNC(bp);
5543 struct bnx2x_ilt *ilt = BP_ILT(bp);
5546 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5547 int i, main_mem_width;
5549 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5551 /* set MSI reconfigure capability */
5552 if (bp->common.int_block == INT_BLOCK_HC) {
5553 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5554 val = REG_RD(bp, addr);
5555 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5556 REG_WR(bp, addr, val);
5560 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5562 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5563 ilt->lines[cdu_ilt_start + i].page =
5564 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5565 ilt->lines[cdu_ilt_start + i].page_mapping =
5566 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5567 /* cdu ilt pages are allocated manually so there's no need to
5570 bnx2x_ilt_init_op(bp, INITOP_SET);
5573 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5575 /* T1 hash bits value determines the T1 number of entries */
5576 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5581 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5582 #endif /* BCM_CNIC */
5584 if (CHIP_IS_E2(bp)) {
5585 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5587 /* Turn on a single ISR mode in IGU if driver is going to use
5590 if (!(bp->flags & USING_MSIX_FLAG))
5591 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5593 * Timers workaround bug: function init part.
5594 * Need to wait 20msec after initializing ILT,
5595 * needed to make sure there are no requests in
5596 * one of the PXP internal queues with "old" ILT addresses
5600 * Master enable - Due to WB DMAE writes performed before this
5601 * register is re-initialized as part of the regular function
5604 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5605 /* Enable the function in IGU */
5606 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5611 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5614 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5616 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5617 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5618 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5619 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5620 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5621 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5622 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5623 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5624 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5626 if (CHIP_IS_E2(bp)) {
5627 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5629 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5633 if (CHIP_MODE_IS_4_PORT(bp))
5634 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5637 REG_WR(bp, QM_REG_PF_EN, 1);
5639 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5641 if (CHIP_MODE_IS_4_PORT(bp))
5642 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5644 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5645 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5646 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5647 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5648 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5649 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5650 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5651 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5652 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5653 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5654 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5656 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5658 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5663 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5666 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5667 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5670 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5672 /* HC init per function */
5673 if (bp->common.int_block == INT_BLOCK_HC) {
5674 if (CHIP_IS_E1H(bp)) {
5675 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5677 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5678 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5680 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5683 int num_segs, sb_idx, prod_offset;
5685 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5687 if (CHIP_IS_E2(bp)) {
5688 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5689 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5692 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5694 if (CHIP_IS_E2(bp)) {
5698 * E2 mode: address 0-135 match to the mapping memory;
5699 * 136 - PF0 default prod; 137 - PF1 default prod;
5700 * 138 - PF2 default prod; 139 - PF3 default prod;
5701 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5702 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5705 * E1.5 mode - In backward compatible mode;
5706 * for non default SB; each even line in the memory
5707 * holds the U producer and each odd line hold
5708 * the C producer. The first 128 producers are for
5709 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5710 * producers are for the DSB for each PF.
5711 * Each PF has five segments: (the order inside each
5712 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5713 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5714 * 144-147 attn prods;
5716 /* non-default-status-blocks */
5717 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5718 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5719 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5720 prod_offset = (bp->igu_base_sb + sb_idx) *
5723 for (i = 0; i < num_segs; i++) {
5724 addr = IGU_REG_PROD_CONS_MEMORY +
5725 (prod_offset + i) * 4;
5726 REG_WR(bp, addr, 0);
5728 /* send consumer update with value 0 */
5729 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5730 USTORM_ID, 0, IGU_INT_NOP, 1);
5731 bnx2x_igu_clear_sb(bp,
5732 bp->igu_base_sb + sb_idx);
5735 /* default-status-blocks */
5736 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5737 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5739 if (CHIP_MODE_IS_4_PORT(bp))
5740 dsb_idx = BP_FUNC(bp);
5742 dsb_idx = BP_E1HVN(bp);
5744 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5745 IGU_BC_BASE_DSB_PROD + dsb_idx :
5746 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5748 for (i = 0; i < (num_segs * E1HVN_MAX);
5750 addr = IGU_REG_PROD_CONS_MEMORY +
5751 (prod_offset + i)*4;
5752 REG_WR(bp, addr, 0);
5754 /* send consumer update with 0 */
5755 if (CHIP_INT_MODE_IS_BC(bp)) {
5756 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5757 USTORM_ID, 0, IGU_INT_NOP, 1);
5758 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5759 CSTORM_ID, 0, IGU_INT_NOP, 1);
5760 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5761 XSTORM_ID, 0, IGU_INT_NOP, 1);
5762 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5763 TSTORM_ID, 0, IGU_INT_NOP, 1);
5764 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5765 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5767 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5768 USTORM_ID, 0, IGU_INT_NOP, 1);
5769 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5770 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5772 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5774 /* !!! these should become driver const once
5775 rf-tool supports split-68 const */
5776 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5777 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5778 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5779 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5780 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5781 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5785 /* Reset PCIE errors for debug */
5786 REG_WR(bp, 0x2114, 0xffffffff);
5787 REG_WR(bp, 0x2120, 0xffffffff);
5789 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5790 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5791 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5792 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5793 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5794 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5796 if (CHIP_IS_E1x(bp)) {
5797 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5798 main_mem_base = HC_REG_MAIN_MEMORY +
5799 BP_PORT(bp) * (main_mem_size * 4);
5800 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5803 val = REG_RD(bp, main_mem_prty_clr);
5805 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5807 "function init (0x%x)!\n", val);
5809 /* Clear "false" parity errors in MSI-X table */
5810 for (i = main_mem_base;
5811 i < main_mem_base + main_mem_size * 4;
5812 i += main_mem_width) {
5813 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5814 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5815 i, main_mem_width / 4);
5817 /* Clear HC parity attention */
5818 REG_RD(bp, main_mem_prty_clr);
5821 bnx2x_phy_probe(&bp->link_params);
5826 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5830 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5831 BP_ABS_FUNC(bp), load_code);
5834 mutex_init(&bp->dmae_mutex);
5835 rc = bnx2x_gunzip_init(bp);
5839 switch (load_code) {
5840 case FW_MSG_CODE_DRV_LOAD_COMMON:
5841 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5842 rc = bnx2x_init_hw_common(bp, load_code);
5847 case FW_MSG_CODE_DRV_LOAD_PORT:
5848 rc = bnx2x_init_hw_port(bp);
5853 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5854 rc = bnx2x_init_hw_func(bp);
5860 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5864 if (!BP_NOMCP(bp)) {
5865 int mb_idx = BP_FW_MB_IDX(bp);
5867 bp->fw_drv_pulse_wr_seq =
5868 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5869 DRV_PULSE_SEQ_MASK);
5870 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5874 bnx2x_gunzip_end(bp);
5879 void bnx2x_free_mem(struct bnx2x *bp)
5882 #define BNX2X_PCI_FREE(x, y, size) \
5885 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
5891 #define BNX2X_FREE(x) \
5903 for_each_queue(bp, i) {
5905 /* FCoE client uses default status block */
5906 if (IS_FCOE_IDX(i)) {
5907 union host_hc_status_block *sb =
5908 &bnx2x_fp(bp, i, status_blk);
5909 memset(sb, 0, sizeof(union host_hc_status_block));
5910 bnx2x_fp(bp, i, status_blk_mapping) = 0;
5915 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
5916 bnx2x_fp(bp, i, status_blk_mapping),
5917 sizeof(struct host_hc_status_block_e2));
5919 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
5920 bnx2x_fp(bp, i, status_blk_mapping),
5921 sizeof(struct host_hc_status_block_e1x));
5927 for_each_rx_queue(bp, i) {
5929 /* fastpath rx rings: rx_buf rx_desc rx_comp */
5930 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5931 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5932 bnx2x_fp(bp, i, rx_desc_mapping),
5933 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5935 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5936 bnx2x_fp(bp, i, rx_comp_mapping),
5937 sizeof(struct eth_fast_path_rx_cqe) *
5941 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5942 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5943 bnx2x_fp(bp, i, rx_sge_mapping),
5944 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5947 for_each_tx_queue(bp, i) {
5949 /* fastpath tx rings: tx_buf tx_desc */
5950 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5951 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5952 bnx2x_fp(bp, i, tx_desc_mapping),
5953 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
5955 /* end of fastpath */
5957 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5958 sizeof(struct host_sp_status_block));
5960 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5961 sizeof(struct bnx2x_slowpath));
5963 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5966 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5968 BNX2X_FREE(bp->ilt->lines);
5972 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5973 sizeof(struct host_hc_status_block_e2));
5975 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5976 sizeof(struct host_hc_status_block_e1x));
5978 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
5981 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5983 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5984 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5986 #undef BNX2X_PCI_FREE
5990 static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
5992 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
5993 if (CHIP_IS_E2(bp)) {
5994 bnx2x_fp(bp, index, sb_index_values) =
5995 (__le16 *)status_blk.e2_sb->sb.index_values;
5996 bnx2x_fp(bp, index, sb_running_index) =
5997 (__le16 *)status_blk.e2_sb->sb.running_index;
5999 bnx2x_fp(bp, index, sb_index_values) =
6000 (__le16 *)status_blk.e1x_sb->sb.index_values;
6001 bnx2x_fp(bp, index, sb_running_index) =
6002 (__le16 *)status_blk.e1x_sb->sb.running_index;
6006 int bnx2x_alloc_mem(struct bnx2x *bp)
6008 #define BNX2X_PCI_ALLOC(x, y, size) \
6010 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
6012 goto alloc_mem_err; \
6013 memset(x, 0, size); \
6016 #define BNX2X_ALLOC(x, size) \
6018 x = kzalloc(size, GFP_KERNEL); \
6020 goto alloc_mem_err; \
6027 for_each_queue(bp, i) {
6028 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
6029 bnx2x_fp(bp, i, bp) = bp;
6032 if (!IS_FCOE_IDX(i)) {
6035 BNX2X_PCI_ALLOC(sb->e2_sb,
6036 &bnx2x_fp(bp, i, status_blk_mapping),
6037 sizeof(struct host_hc_status_block_e2));
6039 BNX2X_PCI_ALLOC(sb->e1x_sb,
6040 &bnx2x_fp(bp, i, status_blk_mapping),
6041 sizeof(struct host_hc_status_block_e1x));
6045 set_sb_shortcuts(bp, i);
6048 for_each_queue(bp, i) {
6050 /* fastpath rx rings: rx_buf rx_desc rx_comp */
6051 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
6052 sizeof(struct sw_rx_bd) * NUM_RX_BD);
6053 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
6054 &bnx2x_fp(bp, i, rx_desc_mapping),
6055 sizeof(struct eth_rx_bd) * NUM_RX_BD);
6057 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
6058 &bnx2x_fp(bp, i, rx_comp_mapping),
6059 sizeof(struct eth_fast_path_rx_cqe) *
6063 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
6064 sizeof(struct sw_rx_page) * NUM_RX_SGE);
6065 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
6066 &bnx2x_fp(bp, i, rx_sge_mapping),
6067 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
6070 for_each_queue(bp, i) {
6072 /* fastpath tx rings: tx_buf tx_desc */
6073 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
6074 sizeof(struct sw_tx_bd) * NUM_TX_BD);
6075 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
6076 &bnx2x_fp(bp, i, tx_desc_mapping),
6077 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
6079 /* end of fastpath */
6083 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6084 sizeof(struct host_hc_status_block_e2));
6086 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6087 sizeof(struct host_hc_status_block_e1x));
6089 /* allocate searcher T2 table */
6090 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6094 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6095 sizeof(struct host_sp_status_block));
6097 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6098 sizeof(struct bnx2x_slowpath));
6100 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
6102 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6105 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6107 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6110 /* Slow path ring */
6111 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6114 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6115 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6122 #undef BNX2X_PCI_ALLOC
6127 * Init service functions
6129 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6130 int *state_p, int flags);
6132 int bnx2x_func_start(struct bnx2x *bp)
6134 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6136 /* Wait for completion */
6137 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6138 WAIT_RAMROD_COMMON);
6141 static int bnx2x_func_stop(struct bnx2x *bp)
6143 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6145 /* Wait for completion */
6146 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6147 0, &(bp->state), WAIT_RAMROD_COMMON);
6151 * Sets a MAC in a CAM for a few L2 Clients for E1x chips
6153 * @param bp driver descriptor
6154 * @param set set or clear an entry (1 or 0)
6155 * @param mac pointer to a buffer containing a MAC
6156 * @param cl_bit_vec bit vector of clients to register a MAC for
6157 * @param cam_offset offset in a CAM to use
6158 * @param is_bcast is the set MAC a broadcast address (for E1 only)
6160 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6161 u32 cl_bit_vec, u8 cam_offset,
6164 struct mac_configuration_cmd *config =
6165 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6166 int ramrod_flags = WAIT_RAMROD_COMMON;
6168 bp->set_mac_pending = 1;
6171 config->hdr.length = 1;
6172 config->hdr.offset = cam_offset;
6173 config->hdr.client_id = 0xff;
6174 config->hdr.reserved1 = 0;
6177 config->config_table[0].msb_mac_addr =
6178 swab16(*(u16 *)&mac[0]);
6179 config->config_table[0].middle_mac_addr =
6180 swab16(*(u16 *)&mac[2]);
6181 config->config_table[0].lsb_mac_addr =
6182 swab16(*(u16 *)&mac[4]);
6183 config->config_table[0].clients_bit_vector =
6184 cpu_to_le32(cl_bit_vec);
6185 config->config_table[0].vlan_id = 0;
6186 config->config_table[0].pf_id = BP_FUNC(bp);
6188 SET_FLAG(config->config_table[0].flags,
6189 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6190 T_ETH_MAC_COMMAND_SET);
6192 SET_FLAG(config->config_table[0].flags,
6193 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6194 T_ETH_MAC_COMMAND_INVALIDATE);
6197 SET_FLAG(config->config_table[0].flags,
6198 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6200 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6201 (set ? "setting" : "clearing"),
6202 config->config_table[0].msb_mac_addr,
6203 config->config_table[0].middle_mac_addr,
6204 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6206 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6207 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6208 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6210 /* Wait for a completion */
6211 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6214 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6215 int *state_p, int flags)
6217 /* can take a while if any port is running */
6219 u8 poll = flags & WAIT_RAMROD_POLL;
6220 u8 common = flags & WAIT_RAMROD_COMMON;
6222 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6223 poll ? "polling" : "waiting", state, idx);
6231 bnx2x_rx_int(bp->fp, 10);
6232 /* if index is different from 0
6233 * the reply for some commands will
6234 * be on the non default queue
6237 bnx2x_rx_int(&bp->fp[idx], 10);
6241 mb(); /* state is changed by bnx2x_sp_event() */
6242 if (*state_p == state) {
6243 #ifdef BNX2X_STOP_ON_ERROR
6244 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6256 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6257 poll ? "polling" : "waiting", state, idx);
6258 #ifdef BNX2X_STOP_ON_ERROR
6265 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6267 if (CHIP_IS_E1H(bp))
6268 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6269 else if (CHIP_MODE_IS_4_PORT(bp))
6270 return BP_FUNC(bp) * 32 + rel_offset;
6272 return BP_VN(bp) * 32 + rel_offset;
6276 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6277 * relevant. In addition, current implementation is tuned for a
6280 * When multiple unicast ETH MACs PF configuration in switch
6281 * independent mode is required (NetQ, multiple netdev MACs,
6282 * etc.), consider better utilisation of 16 per function MAC
6283 * entries in the LLH memory.
6286 LLH_CAM_ISCSI_ETH_LINE = 0,
6288 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6291 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6293 unsigned char *dev_addr,
6297 u32 mem_offset, ena_offset, mem_index;
6300 * 0..7 - goes to MEM
6301 * 8..15 - goes to MEM2
6304 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6307 /* calculate memory start offset according to the mapping
6308 * and index in the memory */
6309 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6310 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6311 NIG_REG_LLH0_FUNC_MEM;
6312 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6313 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6316 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6317 NIG_REG_P0_LLH_FUNC_MEM2;
6318 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6319 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6320 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6324 /* LLH_FUNC_MEM is a u64 WB register */
6325 mem_offset += 8*mem_index;
6327 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6328 (dev_addr[4] << 8) | dev_addr[5]);
6329 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6331 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6334 /* enable/disable the entry */
6335 REG_WR(bp, ena_offset + 4*mem_index, set);
6339 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6341 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6342 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6344 /* networking MAC */
6345 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6346 (1 << bp->fp->cl_id), cam_offset , 0);
6348 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6350 if (CHIP_IS_E1(bp)) {
6352 static const u8 bcast[ETH_ALEN] = {
6353 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6355 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6358 static void bnx2x_set_e1_mc_list(struct bnx2x *bp, u8 offset)
6361 struct net_device *dev = bp->dev;
6362 struct netdev_hw_addr *ha;
6363 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6364 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6366 netdev_for_each_mc_addr(ha, dev) {
6368 config_cmd->config_table[i].msb_mac_addr =
6369 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6370 config_cmd->config_table[i].middle_mac_addr =
6371 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6372 config_cmd->config_table[i].lsb_mac_addr =
6373 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6375 config_cmd->config_table[i].vlan_id = 0;
6376 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6377 config_cmd->config_table[i].clients_bit_vector =
6378 cpu_to_le32(1 << BP_L_ID(bp));
6380 SET_FLAG(config_cmd->config_table[i].flags,
6381 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6382 T_ETH_MAC_COMMAND_SET);
6385 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6386 config_cmd->config_table[i].msb_mac_addr,
6387 config_cmd->config_table[i].middle_mac_addr,
6388 config_cmd->config_table[i].lsb_mac_addr);
6391 old = config_cmd->hdr.length;
6393 for (; i < old; i++) {
6394 if (CAM_IS_INVALID(config_cmd->
6396 /* already invalidated */
6400 SET_FLAG(config_cmd->config_table[i].flags,
6401 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6402 T_ETH_MAC_COMMAND_INVALIDATE);
6406 config_cmd->hdr.length = i;
6407 config_cmd->hdr.offset = offset;
6408 config_cmd->hdr.client_id = 0xff;
6409 config_cmd->hdr.reserved1 = 0;
6411 bp->set_mac_pending = 1;
6414 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6415 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6417 static void bnx2x_invlidate_e1_mc_list(struct bnx2x *bp)
6420 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6421 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6422 int ramrod_flags = WAIT_RAMROD_COMMON;
6424 bp->set_mac_pending = 1;
6427 for (i = 0; i < config_cmd->hdr.length; i++)
6428 SET_FLAG(config_cmd->config_table[i].flags,
6429 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6430 T_ETH_MAC_COMMAND_INVALIDATE);
6432 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6433 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6435 /* Wait for a completion */
6436 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6443 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
6444 * MAC(s). This function will wait until the ramdord completion
6447 * @param bp driver handle
6448 * @param set set or clear the CAM entry
6450 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6452 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6454 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6455 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6456 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6457 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6458 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6460 /* Send a SET_MAC ramrod */
6461 bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
6464 bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6470 * Set FCoE L2 MAC(s) at the next enties in the CAM after the
6471 * ETH MAC(s). This function will wait until the ramdord
6472 * completion returns.
6474 * @param bp driver handle
6475 * @param set set or clear the CAM entry
6477 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
6479 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6481 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6483 * CAM allocation for E1H
6484 * eth unicasts: by func number
6485 * iscsi: by func number
6486 * fip unicast: by func number
6487 * fip multicast: by func number
6489 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6490 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6495 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6497 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6500 * CAM allocation for E1H
6501 * eth unicasts: by func number
6502 * iscsi: by func number
6503 * fip unicast: by func number
6504 * fip multicast: by func number
6506 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6507 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6513 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6514 struct bnx2x_client_init_params *params,
6516 struct client_init_ramrod_data *data)
6518 /* Clear the buffer */
6519 memset(data, 0, sizeof(*data));
6522 data->general.client_id = params->rxq_params.cl_id;
6523 data->general.statistics_counter_id = params->rxq_params.stat_id;
6524 data->general.statistics_en_flg =
6525 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6526 data->general.is_fcoe_flg =
6527 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6528 data->general.activate_flg = activate;
6529 data->general.sp_client_id = params->rxq_params.spcl_id;
6532 data->rx.tpa_en_flg =
6533 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6534 data->rx.vmqueue_mode_en_flg = 0;
6535 data->rx.cache_line_alignment_log_size =
6536 params->rxq_params.cache_line_log;
6537 data->rx.enable_dynamic_hc =
6538 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6539 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6540 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6541 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6543 /* We don't set drop flags */
6544 data->rx.drop_ip_cs_err_flg = 0;
6545 data->rx.drop_tcp_cs_err_flg = 0;
6546 data->rx.drop_ttl0_flg = 0;
6547 data->rx.drop_udp_cs_err_flg = 0;
6549 data->rx.inner_vlan_removal_enable_flg =
6550 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6551 data->rx.outer_vlan_removal_enable_flg =
6552 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6553 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6554 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6555 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6556 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6557 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6558 data->rx.bd_page_base.lo =
6559 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6560 data->rx.bd_page_base.hi =
6561 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6562 data->rx.sge_page_base.lo =
6563 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6564 data->rx.sge_page_base.hi =
6565 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6566 data->rx.cqe_page_base.lo =
6567 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6568 data->rx.cqe_page_base.hi =
6569 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6570 data->rx.is_leading_rss =
6571 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6572 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6575 data->tx.enforce_security_flg = 0; /* VF specific */
6576 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6577 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6578 data->tx.mtu = 0; /* VF specific */
6579 data->tx.tx_bd_page_base.lo =
6580 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6581 data->tx.tx_bd_page_base.hi =
6582 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6584 /* flow control data */
6585 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6586 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6587 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6588 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6589 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6590 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6591 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6593 data->fc.safc_group_num = params->txq_params.cos;
6594 data->fc.safc_group_en_flg =
6595 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6596 data->fc.traffic_type =
6597 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6598 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6601 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6603 /* ustorm cxt validation */
6604 cxt->ustorm_ag_context.cdu_usage =
6605 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6606 ETH_CONNECTION_TYPE);
6607 /* xcontext validation */
6608 cxt->xstorm_ag_context.cdu_reserved =
6609 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6610 ETH_CONNECTION_TYPE);
6613 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6614 struct bnx2x_client_init_params *params,
6616 struct client_init_ramrod_data *data,
6617 dma_addr_t data_mapping)
6620 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6621 int ramrod_flags = 0, rc;
6623 /* HC and context validation values */
6624 hc_usec = params->txq_params.hc_rate ?
6625 1000000 / params->txq_params.hc_rate : 0;
6626 bnx2x_update_coalesce_sb_index(bp,
6627 params->txq_params.fw_sb_id,
6628 params->txq_params.sb_cq_index,
6629 !(params->txq_params.flags & QUEUE_FLG_HC),
6632 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6634 hc_usec = params->rxq_params.hc_rate ?
6635 1000000 / params->rxq_params.hc_rate : 0;
6636 bnx2x_update_coalesce_sb_index(bp,
6637 params->rxq_params.fw_sb_id,
6638 params->rxq_params.sb_cq_index,
6639 !(params->rxq_params.flags & QUEUE_FLG_HC),
6642 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6643 params->rxq_params.cid);
6646 if (params->txq_params.flags & QUEUE_FLG_STATS)
6647 storm_memset_xstats_zero(bp, BP_PORT(bp),
6648 params->txq_params.stat_id);
6650 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6651 storm_memset_ustats_zero(bp, BP_PORT(bp),
6652 params->rxq_params.stat_id);
6653 storm_memset_tstats_zero(bp, BP_PORT(bp),
6654 params->rxq_params.stat_id);
6657 /* Fill the ramrod data */
6658 bnx2x_fill_cl_init_data(bp, params, activate, data);
6662 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6663 * barrier except from mmiowb() is needed to impose a
6664 * proper ordering of memory operations.
6669 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6670 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6672 /* Wait for completion */
6673 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6674 params->ramrod_params.index,
6675 params->ramrod_params.pstate,
6681 * Configure interrupt mode according to current configuration.
6682 * In case of MSI-X it will also try to enable MSI-X.
6688 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6692 switch (bp->int_mode) {
6694 bnx2x_enable_msi(bp);
6695 /* falling through... */
6697 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6698 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6701 /* Set number of queues according to bp->multi_mode value */
6702 bnx2x_set_num_queues(bp);
6704 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6707 /* if we can't use MSI-X we only need one fp,
6708 * so try to enable MSI-X with the requested number of fp's
6709 * and fallback to MSI or legacy INTx with one fp
6711 rc = bnx2x_enable_msix(bp);
6713 /* failed to enable MSI-X */
6716 "Multi requested but failed to "
6717 "enable MSI-X (%d), "
6718 "set number of queues to %d\n",
6720 1 + NONE_ETH_CONTEXT_USE);
6721 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6723 if (!(bp->flags & DISABLE_MSI_FLAG))
6724 bnx2x_enable_msi(bp);
6733 /* must be called prioir to any HW initializations */
6734 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6736 return L2_ILT_LINES(bp);
6739 void bnx2x_ilt_set_info(struct bnx2x *bp)
6741 struct ilt_client_info *ilt_client;
6742 struct bnx2x_ilt *ilt = BP_ILT(bp);
6745 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6746 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6749 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6750 ilt_client->client_num = ILT_CLIENT_CDU;
6751 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6752 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6753 ilt_client->start = line;
6754 line += L2_ILT_LINES(bp);
6756 line += CNIC_ILT_LINES;
6758 ilt_client->end = line - 1;
6760 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6761 "flags 0x%x, hw psz %d\n",
6764 ilt_client->page_size,
6766 ilog2(ilt_client->page_size >> 12));
6769 if (QM_INIT(bp->qm_cid_count)) {
6770 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6771 ilt_client->client_num = ILT_CLIENT_QM;
6772 ilt_client->page_size = QM_ILT_PAGE_SZ;
6773 ilt_client->flags = 0;
6774 ilt_client->start = line;
6776 /* 4 bytes for each cid */
6777 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6780 ilt_client->end = line - 1;
6782 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6783 "flags 0x%x, hw psz %d\n",
6786 ilt_client->page_size,
6788 ilog2(ilt_client->page_size >> 12));
6792 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6794 ilt_client->client_num = ILT_CLIENT_SRC;
6795 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6796 ilt_client->flags = 0;
6797 ilt_client->start = line;
6798 line += SRC_ILT_LINES;
6799 ilt_client->end = line - 1;
6801 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6802 "flags 0x%x, hw psz %d\n",
6805 ilt_client->page_size,
6807 ilog2(ilt_client->page_size >> 12));
6810 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6814 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6816 ilt_client->client_num = ILT_CLIENT_TM;
6817 ilt_client->page_size = TM_ILT_PAGE_SZ;
6818 ilt_client->flags = 0;
6819 ilt_client->start = line;
6820 line += TM_ILT_LINES;
6821 ilt_client->end = line - 1;
6823 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6824 "flags 0x%x, hw psz %d\n",
6827 ilt_client->page_size,
6829 ilog2(ilt_client->page_size >> 12));
6832 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6836 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6839 struct bnx2x_client_init_params params = { {0} };
6842 /* reset IGU state skip FCoE L2 queue */
6843 if (!IS_FCOE_FP(fp))
6844 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6847 params.ramrod_params.pstate = &fp->state;
6848 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6849 params.ramrod_params.index = fp->index;
6850 params.ramrod_params.cid = fp->cid;
6854 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6859 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6861 bnx2x_pf_rx_cl_prep(bp, fp, ¶ms.pause, ¶ms.rxq_params);
6863 bnx2x_pf_tx_cl_prep(bp, fp, ¶ms.txq_params);
6865 rc = bnx2x_setup_fw_client(bp, ¶ms, 1,
6866 bnx2x_sp(bp, client_init_data),
6867 bnx2x_sp_mapping(bp, client_init_data));
6871 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6872 struct bnx2x_client_ramrod_params *p)
6876 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6878 /* halt the connection */
6879 *p->pstate = BNX2X_FP_STATE_HALTING;
6880 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6883 /* Wait for completion */
6884 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6885 p->pstate, poll_flag);
6886 if (rc) /* timeout */
6889 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6890 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6892 /* Wait for completion */
6893 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6894 p->pstate, poll_flag);
6895 if (rc) /* timeout */
6899 /* delete cfc entry */
6900 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6902 /* Wait for completion */
6903 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6904 p->pstate, WAIT_RAMROD_COMMON);
6908 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6910 struct bnx2x_client_ramrod_params client_stop = {0};
6911 struct bnx2x_fastpath *fp = &bp->fp[index];
6913 client_stop.index = index;
6914 client_stop.cid = fp->cid;
6915 client_stop.cl_id = fp->cl_id;
6916 client_stop.pstate = &(fp->state);
6917 client_stop.poll = 0;
6919 return bnx2x_stop_fw_client(bp, &client_stop);
6923 static void bnx2x_reset_func(struct bnx2x *bp)
6925 int port = BP_PORT(bp);
6926 int func = BP_FUNC(bp);
6928 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6930 offsetof(struct hc_status_block_data_e2, common) :
6931 offsetof(struct hc_status_block_data_e1x, common));
6932 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6933 int pfid_offset = offsetof(struct pci_entity, pf_id);
6935 /* Disable the function in the FW */
6936 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6937 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6938 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6939 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6942 for_each_eth_queue(bp, i) {
6943 struct bnx2x_fastpath *fp = &bp->fp[i];
6945 BAR_CSTRORM_INTMEM +
6946 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6947 + pfunc_offset_fp + pfid_offset,
6948 HC_FUNCTION_DISABLED);
6953 BAR_CSTRORM_INTMEM +
6954 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6955 pfunc_offset_sp + pfid_offset,
6956 HC_FUNCTION_DISABLED);
6959 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6960 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6964 if (bp->common.int_block == INT_BLOCK_HC) {
6965 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6966 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6968 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6969 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6973 /* Disable Timer scan */
6974 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6976 * Wait for at least 10ms and up to 2 second for the timers scan to
6979 for (i = 0; i < 200; i++) {
6981 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6986 bnx2x_clear_func_ilt(bp, func);
6988 /* Timers workaround bug for E2: if this is vnic-3,
6989 * we need to set the entire ilt range for this timers.
6991 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6992 struct ilt_client_info ilt_cli;
6993 /* use dummy TM client */
6994 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6996 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6997 ilt_cli.client_num = ILT_CLIENT_TM;
6999 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7002 /* this assumes that reset_port() called before reset_func()*/
7004 bnx2x_pf_disable(bp);
7009 static void bnx2x_reset_port(struct bnx2x *bp)
7011 int port = BP_PORT(bp);
7014 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7016 /* Do not rcv packets to BRB */
7017 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7018 /* Do not direct rcv packets that are not for MCP to the BRB */
7019 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7020 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7023 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7026 /* Check for BRB port occupancy */
7027 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7029 DP(NETIF_MSG_IFDOWN,
7030 "BRB1 is not empty %d blocks are occupied\n", val);
7032 /* TODO: Close Doorbell port? */
7035 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
7037 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
7038 BP_ABS_FUNC(bp), reset_code);
7040 switch (reset_code) {
7041 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7042 bnx2x_reset_port(bp);
7043 bnx2x_reset_func(bp);
7044 bnx2x_reset_common(bp);
7047 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7048 bnx2x_reset_port(bp);
7049 bnx2x_reset_func(bp);
7052 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7053 bnx2x_reset_func(bp);
7057 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7063 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7065 if (bp->flags & FCOE_MACS_SET) {
7067 bnx2x_set_fip_eth_mac_addr(bp, 0);
7069 bnx2x_set_all_enode_macs(bp, 0);
7071 bp->flags &= ~FCOE_MACS_SET;
7076 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7078 int port = BP_PORT(bp);
7082 /* Wait until tx fastpath tasks complete */
7083 for_each_tx_queue(bp, i) {
7084 struct bnx2x_fastpath *fp = &bp->fp[i];
7087 while (bnx2x_has_tx_work_unload(fp)) {
7090 BNX2X_ERR("timeout waiting for queue[%d]\n",
7092 #ifdef BNX2X_STOP_ON_ERROR
7103 /* Give HW time to discard old tx messages */
7106 if (CHIP_IS_E1(bp)) {
7107 /* invalidate mc list,
7108 * wait and poll (interrupts are off)
7110 bnx2x_invlidate_e1_mc_list(bp);
7111 bnx2x_set_eth_mac(bp, 0);
7114 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7116 bnx2x_set_eth_mac(bp, 0);
7118 for (i = 0; i < MC_HASH_SIZE; i++)
7119 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
7123 bnx2x_del_fcoe_eth_macs(bp);
7126 if (unload_mode == UNLOAD_NORMAL)
7127 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7129 else if (bp->flags & NO_WOL_FLAG)
7130 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7133 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7134 u8 *mac_addr = bp->dev->dev_addr;
7136 /* The mac address is written to entries 1-4 to
7137 preserve entry 0 which is used by the PMF */
7138 u8 entry = (BP_E1HVN(bp) + 1)*8;
7140 val = (mac_addr[0] << 8) | mac_addr[1];
7141 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7143 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7144 (mac_addr[4] << 8) | mac_addr[5];
7145 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7147 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7150 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7152 /* Close multi and leading connections
7153 Completions for ramrods are collected in a synchronous way */
7154 for_each_queue(bp, i)
7156 if (bnx2x_stop_client(bp, i))
7157 #ifdef BNX2X_STOP_ON_ERROR
7163 rc = bnx2x_func_stop(bp);
7165 BNX2X_ERR("Function stop failed!\n");
7166 #ifdef BNX2X_STOP_ON_ERROR
7172 #ifndef BNX2X_STOP_ON_ERROR
7176 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7178 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7179 "%d, %d, %d\n", BP_PATH(bp),
7180 load_count[BP_PATH(bp)][0],
7181 load_count[BP_PATH(bp)][1],
7182 load_count[BP_PATH(bp)][2]);
7183 load_count[BP_PATH(bp)][0]--;
7184 load_count[BP_PATH(bp)][1 + port]--;
7185 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7186 "%d, %d, %d\n", BP_PATH(bp),
7187 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7188 load_count[BP_PATH(bp)][2]);
7189 if (load_count[BP_PATH(bp)][0] == 0)
7190 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7191 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7192 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7194 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7197 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7198 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7199 bnx2x__link_reset(bp);
7201 /* Disable HW interrupts, NAPI */
7202 bnx2x_netif_stop(bp, 1);
7207 /* Reset the chip */
7208 bnx2x_reset_chip(bp, reset_code);
7210 /* Report UNLOAD_DONE to MCP */
7212 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7216 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7220 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7222 if (CHIP_IS_E1(bp)) {
7223 int port = BP_PORT(bp);
7224 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7225 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7227 val = REG_RD(bp, addr);
7229 REG_WR(bp, addr, val);
7230 } else if (CHIP_IS_E1H(bp)) {
7231 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7232 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7233 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7234 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7238 /* Close gates #2, #3 and #4: */
7239 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7243 /* Gates #2 and #4a are closed/opened for "not E1" only */
7244 if (!CHIP_IS_E1(bp)) {
7246 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7247 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7248 close ? (val | 0x1) : (val & (~(u32)1)));
7250 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7251 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7252 close ? (val | 0x1) : (val & (~(u32)1)));
7256 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7257 val = REG_RD(bp, addr);
7258 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7260 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7261 close ? "closing" : "opening");
7265 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7267 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7269 /* Do some magic... */
7270 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7271 *magic_val = val & SHARED_MF_CLP_MAGIC;
7272 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7275 /* Restore the value of the `magic' bit.
7277 * @param pdev Device handle.
7278 * @param magic_val Old value of the `magic' bit.
7280 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7282 /* Restore the `magic' bit value... */
7283 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7284 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7285 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7289 * Prepares for MCP reset: takes care of CLP configurations.
7292 * @param magic_val Old value of 'magic' bit.
7294 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7297 u32 validity_offset;
7299 DP(NETIF_MSG_HW, "Starting\n");
7301 /* Set `magic' bit in order to save MF config */
7302 if (!CHIP_IS_E1(bp))
7303 bnx2x_clp_reset_prep(bp, magic_val);
7305 /* Get shmem offset */
7306 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7307 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7309 /* Clear validity map flags */
7311 REG_WR(bp, shmem + validity_offset, 0);
7314 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7315 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7317 /* Waits for MCP_ONE_TIMEOUT or MCP_ONE_TIMEOUT*10,
7318 * depending on the HW type.
7322 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7324 /* special handling for emulation and FPGA,
7325 wait 10 times longer */
7326 if (CHIP_REV_IS_SLOW(bp))
7327 msleep(MCP_ONE_TIMEOUT*10);
7329 msleep(MCP_ONE_TIMEOUT);
7332 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7334 u32 shmem, cnt, validity_offset, val;
7339 /* Get shmem offset */
7340 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7342 BNX2X_ERR("Shmem 0 return failure\n");
7347 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7349 /* Wait for MCP to come up */
7350 for (cnt = 0; cnt < (MCP_TIMEOUT / MCP_ONE_TIMEOUT); cnt++) {
7351 /* TBD: its best to check validity map of last port.
7352 * currently checks on port 0.
7354 val = REG_RD(bp, shmem + validity_offset);
7355 DP(NETIF_MSG_HW, "shmem 0x%x validity map(0x%x)=0x%x\n", shmem,
7356 shmem + validity_offset, val);
7358 /* check that shared memory is valid. */
7359 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7360 == (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7363 bnx2x_mcp_wait_one(bp);
7366 DP(NETIF_MSG_HW, "Cnt=%d Shmem validity map 0x%x\n", cnt, val);
7368 /* Check that shared memory is valid. This indicates that MCP is up. */
7369 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
7370 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
7371 BNX2X_ERR("Shmem signature not present. MCP is not up !!\n");
7377 /* Restore the `magic' bit value */
7378 if (!CHIP_IS_E1(bp))
7379 bnx2x_clp_reset_done(bp, magic_val);
7384 static void bnx2x_pxp_prep(struct bnx2x *bp)
7386 if (!CHIP_IS_E1(bp)) {
7387 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7388 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7389 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7395 * Reset the whole chip except for:
7397 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7400 * - MISC (including AEU)
7404 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7406 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7409 MISC_REGISTERS_RESET_REG_1_RST_HC |
7410 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7411 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7414 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7415 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7416 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7417 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7418 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7419 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7420 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7421 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7423 reset_mask1 = 0xffffffff;
7426 reset_mask2 = 0xffff;
7428 reset_mask2 = 0x1ffff;
7430 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7431 reset_mask1 & (~not_reset_mask1));
7432 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7433 reset_mask2 & (~not_reset_mask2));
7438 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7439 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7443 static int bnx2x_process_kill(struct bnx2x *bp)
7447 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7450 /* Empty the Tetris buffer, wait for 1s */
7452 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7453 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7454 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7455 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7456 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7457 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7458 ((port_is_idle_0 & 0x1) == 0x1) &&
7459 ((port_is_idle_1 & 0x1) == 0x1) &&
7460 (pgl_exp_rom2 == 0xffffffff))
7463 } while (cnt-- > 0);
7466 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7468 " outstanding read requests after 1s!\n");
7469 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7470 " port_is_idle_0=0x%08x,"
7471 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7472 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7479 /* Close gates #2, #3 and #4 */
7480 bnx2x_set_234_gates(bp, true);
7482 /* TBD: Indicate that "process kill" is in progress to MCP */
7484 /* Clear "unprepared" bit */
7485 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7488 /* Make sure all is written to the chip before the reset */
7491 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7492 * PSWHST, GRC and PSWRD Tetris buffer.
7496 /* Prepare to chip reset: */
7498 bnx2x_reset_mcp_prep(bp, &val);
7504 /* reset the chip */
7505 bnx2x_process_kill_chip_reset(bp);
7508 /* Recover after reset: */
7510 if (bnx2x_reset_mcp_comp(bp, val))
7516 /* Open the gates #2, #3 and #4 */
7517 bnx2x_set_234_gates(bp, false);
7519 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7520 * reset state, re-enable attentions. */
7525 static int bnx2x_leader_reset(struct bnx2x *bp)
7528 /* Try to recover after the failure */
7529 if (bnx2x_process_kill(bp)) {
7530 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7533 goto exit_leader_reset;
7536 /* Clear "reset is in progress" bit and update the driver state */
7537 bnx2x_set_reset_done(bp);
7538 bp->recovery_state = BNX2X_RECOVERY_DONE;
7542 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7547 /* Assumption: runs under rtnl lock. This together with the fact
7548 * that it's called only from bnx2x_reset_task() ensure that it
7549 * will never be called when netif_running(bp->dev) is false.
7551 static void bnx2x_parity_recover(struct bnx2x *bp)
7553 DP(NETIF_MSG_HW, "Handling parity\n");
7555 switch (bp->recovery_state) {
7556 case BNX2X_RECOVERY_INIT:
7557 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7558 /* Try to get a LEADER_LOCK HW lock */
7559 if (bnx2x_trylock_hw_lock(bp,
7560 HW_LOCK_RESOURCE_RESERVED_08))
7563 /* Stop the driver */
7564 /* If interface has been removed - break */
7565 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7568 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7569 /* Ensure "is_leader" and "recovery_state"
7570 * update values are seen on other CPUs
7575 case BNX2X_RECOVERY_WAIT:
7576 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7577 if (bp->is_leader) {
7578 u32 load_counter = bnx2x_get_load_cnt(bp);
7580 /* Wait until all other functions get
7583 schedule_delayed_work(&bp->reset_task,
7587 /* If all other functions got down -
7588 * try to bring the chip back to
7589 * normal. In any case it's an exit
7590 * point for a leader.
7592 if (bnx2x_leader_reset(bp) ||
7593 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7594 printk(KERN_ERR"%s: Recovery "
7595 "has failed. Power cycle is "
7596 "needed.\n", bp->dev->name);
7597 /* Disconnect this device */
7598 netif_device_detach(bp->dev);
7599 /* Block ifup for all function
7600 * of this ASIC until
7601 * "process kill" or power
7604 bnx2x_set_reset_in_progress(bp);
7605 /* Shut down the power */
7606 bnx2x_set_power_state(bp,
7613 } else { /* non-leader */
7614 if (!bnx2x_reset_is_done(bp)) {
7615 /* Try to get a LEADER_LOCK HW lock as
7616 * long as a former leader may have
7617 * been unloaded by the user or
7618 * released a leadership by another
7621 if (bnx2x_trylock_hw_lock(bp,
7622 HW_LOCK_RESOURCE_RESERVED_08)) {
7623 /* I'm a leader now! Restart a
7630 schedule_delayed_work(&bp->reset_task,
7634 } else { /* A leader has completed
7635 * the "process kill". It's an exit
7636 * point for a non-leader.
7638 bnx2x_nic_load(bp, LOAD_NORMAL);
7639 bp->recovery_state =
7640 BNX2X_RECOVERY_DONE;
7651 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7652 * scheduled on a general queue in order to prevent a dead lock.
7654 static void bnx2x_reset_task(struct work_struct *work)
7656 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7658 #ifdef BNX2X_STOP_ON_ERROR
7659 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7660 " so reset not done to allow debug dump,\n"
7661 KERN_ERR " you will need to reboot when done\n");
7667 if (!netif_running(bp->dev))
7668 goto reset_task_exit;
7670 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7671 bnx2x_parity_recover(bp);
7673 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7674 bnx2x_nic_load(bp, LOAD_NORMAL);
7681 /* end of nic load/unload */
7684 * Init service functions
7687 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7689 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7690 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7691 return base + (BP_ABS_FUNC(bp)) * stride;
7694 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7696 u32 reg = bnx2x_get_pretend_reg(bp);
7698 /* Flush all outstanding writes */
7701 /* Pretend to be function 0 */
7703 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7705 /* From now we are in the "like-E1" mode */
7706 bnx2x_int_disable(bp);
7708 /* Flush all outstanding writes */
7711 /* Restore the original function */
7712 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7716 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7719 bnx2x_int_disable(bp);
7721 bnx2x_undi_int_disable_e1h(bp);
7724 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7728 /* Check if there is any driver already loaded */
7729 val = REG_RD(bp, MISC_REG_UNPREPARED);
7731 /* Check if it is the UNDI driver
7732 * UNDI driver initializes CID offset for normal bell to 0x7
7734 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7735 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7737 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7738 /* save our pf_num */
7739 int orig_pf_num = bp->pf_num;
7743 /* clear the UNDI indication */
7744 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7746 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7748 /* try unload UNDI on port 0 */
7751 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7752 DRV_MSG_SEQ_NUMBER_MASK);
7753 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7755 /* if UNDI is loaded on the other port */
7756 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7758 /* send "DONE" for previous unload */
7759 bnx2x_fw_command(bp,
7760 DRV_MSG_CODE_UNLOAD_DONE, 0);
7762 /* unload UNDI on port 1 */
7765 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7766 DRV_MSG_SEQ_NUMBER_MASK);
7767 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7769 bnx2x_fw_command(bp, reset_code, 0);
7772 /* now it's safe to release the lock */
7773 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7775 bnx2x_undi_int_disable(bp);
7777 /* close input traffic and wait for it */
7778 /* Do not rcv packets to BRB */
7780 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7781 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7782 /* Do not direct rcv packets that are not for MCP to
7785 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7786 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7789 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7790 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7793 /* save NIG port swap info */
7794 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7795 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7798 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7801 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7803 /* take the NIG out of reset and restore swap values */
7805 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7806 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7807 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7808 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7810 /* send unload done to the MCP */
7811 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7813 /* restore our func and fw_seq */
7814 bp->pf_num = orig_pf_num;
7816 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7817 DRV_MSG_SEQ_NUMBER_MASK);
7819 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7823 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7825 u32 val, val2, val3, val4, id;
7828 /* Get the chip revision id and number. */
7829 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7830 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7831 id = ((val & 0xffff) << 16);
7832 val = REG_RD(bp, MISC_REG_CHIP_REV);
7833 id |= ((val & 0xf) << 12);
7834 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7835 id |= ((val & 0xff) << 4);
7836 val = REG_RD(bp, MISC_REG_BOND_ID);
7838 bp->common.chip_id = id;
7840 /* Set doorbell size */
7841 bp->db_size = (1 << BNX2X_DB_SHIFT);
7843 if (CHIP_IS_E2(bp)) {
7844 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7846 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7848 val = (val >> 1) & 1;
7849 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7851 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7854 if (CHIP_MODE_IS_4_PORT(bp))
7855 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7857 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7859 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7860 bp->pfid = bp->pf_num; /* 0..7 */
7864 * set base FW non-default (fast path) status block id, this value is
7865 * used to initialize the fw_sb_id saved on the fp/queue structure to
7866 * determine the id used by the FW.
7868 if (CHIP_IS_E1x(bp))
7869 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7871 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7873 bp->link_params.chip_id = bp->common.chip_id;
7874 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7876 val = (REG_RD(bp, 0x2874) & 0x55);
7877 if ((bp->common.chip_id & 0x1) ||
7878 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7879 bp->flags |= ONE_PORT_FLAG;
7880 BNX2X_DEV_INFO("single port device\n");
7883 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7884 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7885 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7886 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7887 bp->common.flash_size, bp->common.flash_size);
7889 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7890 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7891 MISC_REG_GENERIC_CR_1 :
7892 MISC_REG_GENERIC_CR_0));
7893 bp->link_params.shmem_base = bp->common.shmem_base;
7894 bp->link_params.shmem2_base = bp->common.shmem2_base;
7895 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7896 bp->common.shmem_base, bp->common.shmem2_base);
7898 if (!bp->common.shmem_base) {
7899 BNX2X_DEV_INFO("MCP not active\n");
7900 bp->flags |= NO_MCP_FLAG;
7904 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7905 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7906 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
7907 BNX2X_ERR("BAD MCP validity signature\n");
7909 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7910 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7912 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7913 SHARED_HW_CFG_LED_MODE_MASK) >>
7914 SHARED_HW_CFG_LED_MODE_SHIFT);
7916 bp->link_params.feature_config_flags = 0;
7917 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7918 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7919 bp->link_params.feature_config_flags |=
7920 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7922 bp->link_params.feature_config_flags &=
7923 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7925 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7926 bp->common.bc_ver = val;
7927 BNX2X_DEV_INFO("bc_ver %X\n", val);
7928 if (val < BNX2X_BC_VER) {
7929 /* for now only warn
7930 * later we might need to enforce this */
7931 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7932 "please upgrade BC\n", BNX2X_BC_VER, val);
7934 bp->link_params.feature_config_flags |=
7935 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7936 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7938 bp->link_params.feature_config_flags |=
7939 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7940 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7942 if (BP_E1HVN(bp) == 0) {
7943 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7944 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7946 /* no WOL capability for E1HVN != 0 */
7947 bp->flags |= NO_WOL_FLAG;
7949 BNX2X_DEV_INFO("%sWoL capable\n",
7950 (bp->flags & NO_WOL_FLAG) ? "not " : "");
7952 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7953 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7954 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7955 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7957 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7958 val, val2, val3, val4);
7961 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7962 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7964 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7966 int pfid = BP_FUNC(bp);
7967 int vn = BP_E1HVN(bp);
7972 bp->igu_base_sb = 0xff;
7974 if (CHIP_INT_MODE_IS_BC(bp)) {
7975 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
7976 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7978 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7981 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7982 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7987 /* IGU in normal mode - read CAM */
7988 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7990 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7991 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7994 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7995 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7997 if (IGU_VEC(val) == 0)
7998 /* default status block */
7999 bp->igu_dsb_id = igu_sb_id;
8001 if (bp->igu_base_sb == 0xff)
8002 bp->igu_base_sb = igu_sb_id;
8007 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8008 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8009 if (bp->igu_sb_cnt == 0)
8010 BNX2X_ERR("CAM configuration error\n");
8013 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8016 int cfg_size = 0, idx, port = BP_PORT(bp);
8018 /* Aggregation of supported attributes of all external phys */
8019 bp->port.supported[0] = 0;
8020 bp->port.supported[1] = 0;
8021 switch (bp->link_params.num_phys) {
8023 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8027 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8031 if (bp->link_params.multi_phy_config &
8032 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8033 bp->port.supported[1] =
8034 bp->link_params.phy[EXT_PHY1].supported;
8035 bp->port.supported[0] =
8036 bp->link_params.phy[EXT_PHY2].supported;
8038 bp->port.supported[0] =
8039 bp->link_params.phy[EXT_PHY1].supported;
8040 bp->port.supported[1] =
8041 bp->link_params.phy[EXT_PHY2].supported;
8047 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8048 BNX2X_ERR("NVRAM config error. BAD phy config."
8049 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8051 dev_info.port_hw_config[port].external_phy_config),
8053 dev_info.port_hw_config[port].external_phy_config2));
8057 switch (switch_cfg) {
8059 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
8061 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8064 case SWITCH_CFG_10G:
8065 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8067 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8071 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8072 bp->port.link_config[0]);
8075 /* mask what we support according to speed_cap_mask per configuration */
8076 for (idx = 0; idx < cfg_size; idx++) {
8077 if (!(bp->link_params.speed_cap_mask[idx] &
8078 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8079 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8081 if (!(bp->link_params.speed_cap_mask[idx] &
8082 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8083 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8085 if (!(bp->link_params.speed_cap_mask[idx] &
8086 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8087 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8089 if (!(bp->link_params.speed_cap_mask[idx] &
8090 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8091 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8093 if (!(bp->link_params.speed_cap_mask[idx] &
8094 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8095 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8096 SUPPORTED_1000baseT_Full);
8098 if (!(bp->link_params.speed_cap_mask[idx] &
8099 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8100 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8102 if (!(bp->link_params.speed_cap_mask[idx] &
8103 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8104 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8108 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8109 bp->port.supported[1]);
8112 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8114 u32 link_config, idx, cfg_size = 0;
8115 bp->port.advertising[0] = 0;
8116 bp->port.advertising[1] = 0;
8117 switch (bp->link_params.num_phys) {
8126 for (idx = 0; idx < cfg_size; idx++) {
8127 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8128 link_config = bp->port.link_config[idx];
8129 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8130 case PORT_FEATURE_LINK_SPEED_AUTO:
8131 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8132 bp->link_params.req_line_speed[idx] =
8134 bp->port.advertising[idx] |=
8135 bp->port.supported[idx];
8137 /* force 10G, no AN */
8138 bp->link_params.req_line_speed[idx] =
8140 bp->port.advertising[idx] |=
8141 (ADVERTISED_10000baseT_Full |
8147 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8148 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8149 bp->link_params.req_line_speed[idx] =
8151 bp->port.advertising[idx] |=
8152 (ADVERTISED_10baseT_Full |
8155 BNX2X_ERROR("NVRAM config error. "
8156 "Invalid link_config 0x%x"
8157 " speed_cap_mask 0x%x\n",
8159 bp->link_params.speed_cap_mask[idx]);
8164 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8165 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8166 bp->link_params.req_line_speed[idx] =
8168 bp->link_params.req_duplex[idx] =
8170 bp->port.advertising[idx] |=
8171 (ADVERTISED_10baseT_Half |
8174 BNX2X_ERROR("NVRAM config error. "
8175 "Invalid link_config 0x%x"
8176 " speed_cap_mask 0x%x\n",
8178 bp->link_params.speed_cap_mask[idx]);
8183 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8184 if (bp->port.supported[idx] &
8185 SUPPORTED_100baseT_Full) {
8186 bp->link_params.req_line_speed[idx] =
8188 bp->port.advertising[idx] |=
8189 (ADVERTISED_100baseT_Full |
8192 BNX2X_ERROR("NVRAM config error. "
8193 "Invalid link_config 0x%x"
8194 " speed_cap_mask 0x%x\n",
8196 bp->link_params.speed_cap_mask[idx]);
8201 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8202 if (bp->port.supported[idx] &
8203 SUPPORTED_100baseT_Half) {
8204 bp->link_params.req_line_speed[idx] =
8206 bp->link_params.req_duplex[idx] =
8208 bp->port.advertising[idx] |=
8209 (ADVERTISED_100baseT_Half |
8212 BNX2X_ERROR("NVRAM config error. "
8213 "Invalid link_config 0x%x"
8214 " speed_cap_mask 0x%x\n",
8216 bp->link_params.speed_cap_mask[idx]);
8221 case PORT_FEATURE_LINK_SPEED_1G:
8222 if (bp->port.supported[idx] &
8223 SUPPORTED_1000baseT_Full) {
8224 bp->link_params.req_line_speed[idx] =
8226 bp->port.advertising[idx] |=
8227 (ADVERTISED_1000baseT_Full |
8230 BNX2X_ERROR("NVRAM config error. "
8231 "Invalid link_config 0x%x"
8232 " speed_cap_mask 0x%x\n",
8234 bp->link_params.speed_cap_mask[idx]);
8239 case PORT_FEATURE_LINK_SPEED_2_5G:
8240 if (bp->port.supported[idx] &
8241 SUPPORTED_2500baseX_Full) {
8242 bp->link_params.req_line_speed[idx] =
8244 bp->port.advertising[idx] |=
8245 (ADVERTISED_2500baseX_Full |
8248 BNX2X_ERROR("NVRAM config error. "
8249 "Invalid link_config 0x%x"
8250 " speed_cap_mask 0x%x\n",
8252 bp->link_params.speed_cap_mask[idx]);
8257 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8258 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8259 case PORT_FEATURE_LINK_SPEED_10G_KR:
8260 if (bp->port.supported[idx] &
8261 SUPPORTED_10000baseT_Full) {
8262 bp->link_params.req_line_speed[idx] =
8264 bp->port.advertising[idx] |=
8265 (ADVERTISED_10000baseT_Full |
8268 BNX2X_ERROR("NVRAM config error. "
8269 "Invalid link_config 0x%x"
8270 " speed_cap_mask 0x%x\n",
8272 bp->link_params.speed_cap_mask[idx]);
8278 BNX2X_ERROR("NVRAM config error. "
8279 "BAD link speed link_config 0x%x\n",
8281 bp->link_params.req_line_speed[idx] =
8283 bp->port.advertising[idx] =
8284 bp->port.supported[idx];
8288 bp->link_params.req_flow_ctrl[idx] = (link_config &
8289 PORT_FEATURE_FLOW_CONTROL_MASK);
8290 if ((bp->link_params.req_flow_ctrl[idx] ==
8291 BNX2X_FLOW_CTRL_AUTO) &&
8292 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8293 bp->link_params.req_flow_ctrl[idx] =
8294 BNX2X_FLOW_CTRL_NONE;
8297 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8298 " 0x%x advertising 0x%x\n",
8299 bp->link_params.req_line_speed[idx],
8300 bp->link_params.req_duplex[idx],
8301 bp->link_params.req_flow_ctrl[idx],
8302 bp->port.advertising[idx]);
8306 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8308 mac_hi = cpu_to_be16(mac_hi);
8309 mac_lo = cpu_to_be32(mac_lo);
8310 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8311 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8314 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8316 int port = BP_PORT(bp);
8318 u32 ext_phy_type, ext_phy_config;
8320 bp->link_params.bp = bp;
8321 bp->link_params.port = port;
8323 bp->link_params.lane_config =
8324 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8326 bp->link_params.speed_cap_mask[0] =
8328 dev_info.port_hw_config[port].speed_capability_mask);
8329 bp->link_params.speed_cap_mask[1] =
8331 dev_info.port_hw_config[port].speed_capability_mask2);
8332 bp->port.link_config[0] =
8333 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8335 bp->port.link_config[1] =
8336 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8338 bp->link_params.multi_phy_config =
8339 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8340 /* If the device is capable of WoL, set the default state according
8343 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8344 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8345 (config & PORT_FEATURE_WOL_ENABLED));
8347 BNX2X_DEV_INFO("lane_config 0x%08x "
8348 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8349 bp->link_params.lane_config,
8350 bp->link_params.speed_cap_mask[0],
8351 bp->port.link_config[0]);
8353 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8354 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8355 bnx2x_phy_probe(&bp->link_params);
8356 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8358 bnx2x_link_settings_requested(bp);
8361 * If connected directly, work with the internal PHY, otherwise, work
8362 * with the external PHY
8366 dev_info.port_hw_config[port].external_phy_config);
8367 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8368 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8369 bp->mdio.prtad = bp->port.phy_addr;
8371 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8372 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8374 XGXS_EXT_PHY_ADDR(ext_phy_config);
8377 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8378 * In MF mode, it is set to cover self test cases
8381 bp->port.need_hw_lock = 1;
8383 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8384 bp->common.shmem_base,
8385 bp->common.shmem2_base);
8388 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8391 int func = BP_ABS_FUNC(bp);
8392 int port = BP_PORT(bp);
8395 BNX2X_ERROR("warning: random MAC workaround active\n");
8396 random_ether_addr(bp->dev->dev_addr);
8397 } else if (IS_MF(bp)) {
8398 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8399 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8400 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8401 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8402 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8405 /* iSCSI NPAR MAC */
8407 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8408 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8409 val2 = MF_CFG_RD(bp, func_ext_config[func].
8410 iscsi_mac_addr_upper);
8411 val = MF_CFG_RD(bp, func_ext_config[func].
8412 iscsi_mac_addr_lower);
8413 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8418 /* in SF read MACs from port configuration */
8419 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8420 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8421 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8424 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8426 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8428 bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
8432 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8433 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8436 /* Inform the upper layers about FCoE MAC */
8437 if (!CHIP_IS_E1x(bp)) {
8439 memcpy(bp->fip_mac, bp->dev->dev_addr,
8440 sizeof(bp->fip_mac));
8442 memcpy(bp->fip_mac, bp->iscsi_mac,
8443 sizeof(bp->fip_mac));
8448 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8450 int /*abs*/func = BP_ABS_FUNC(bp);
8455 bnx2x_get_common_hwinfo(bp);
8457 if (CHIP_IS_E1x(bp)) {
8458 bp->common.int_block = INT_BLOCK_HC;
8460 bp->igu_dsb_id = DEF_SB_IGU_ID;
8461 bp->igu_base_sb = 0;
8462 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8463 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8465 bp->common.int_block = INT_BLOCK_IGU;
8466 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8467 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8468 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8469 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8471 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8473 bnx2x_get_igu_cam_info(bp);
8476 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8477 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8480 * Initialize MF configuration
8488 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8490 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8491 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8492 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8493 if (SHMEM2_HAS(bp, mf_cfg_addr))
8494 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8496 bp->common.mf_cfg_base = bp->common.shmem_base +
8497 offsetof(struct shmem_region, func_mb) +
8498 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8500 * get mf configuration:
8501 * 1. existance of MF configuration
8502 * 2. MAC address must be legal (check only upper bytes)
8503 * for Switch-Independent mode;
8504 * OVLAN must be legal for Switch-Dependent mode
8505 * 3. SF_MODE configures specific MF mode
8507 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8508 /* get mf configuration */
8510 dev_info.shared_feature_config.config);
8511 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8514 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8515 val = MF_CFG_RD(bp, func_mf_config[func].
8517 /* check for legal mac (upper bytes)*/
8518 if (val != 0xffff) {
8519 bp->mf_mode = MULTI_FUNCTION_SI;
8520 bp->mf_config[vn] = MF_CFG_RD(bp,
8521 func_mf_config[func].config);
8523 DP(NETIF_MSG_PROBE, "illegal MAC "
8524 "address for SI\n");
8526 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8527 /* get OV configuration */
8529 func_mf_config[FUNC_0].e1hov_tag);
8530 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8532 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8533 bp->mf_mode = MULTI_FUNCTION_SD;
8534 bp->mf_config[vn] = MF_CFG_RD(bp,
8535 func_mf_config[func].config);
8537 DP(NETIF_MSG_PROBE, "illegal OV for "
8541 /* Unknown configuration: reset mf_config */
8542 bp->mf_config[vn] = 0;
8543 DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
8548 BNX2X_DEV_INFO("%s function mode\n",
8549 IS_MF(bp) ? "multi" : "single");
8551 switch (bp->mf_mode) {
8552 case MULTI_FUNCTION_SD:
8553 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8554 FUNC_MF_CFG_E1HOV_TAG_MASK;
8555 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8557 BNX2X_DEV_INFO("MF OV for func %d is %d"
8558 " (0x%04x)\n", func,
8559 bp->mf_ov, bp->mf_ov);
8561 BNX2X_ERR("No valid MF OV for func %d,"
8562 " aborting\n", func);
8566 case MULTI_FUNCTION_SI:
8567 BNX2X_DEV_INFO("func %d is in MF "
8568 "switch-independent mode\n", func);
8572 BNX2X_ERR("VN %d in single function mode,"
8581 /* adjust igu_sb_cnt to MF for E1x */
8582 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8583 bp->igu_sb_cnt /= E1HVN_MAX;
8586 * adjust E2 sb count: to be removed when FW will support
8587 * more then 16 L2 clients
8589 #define MAX_L2_CLIENTS 16
8591 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8592 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8594 if (!BP_NOMCP(bp)) {
8595 bnx2x_get_port_hwinfo(bp);
8598 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8599 DRV_MSG_SEQ_NUMBER_MASK);
8600 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8603 /* Get MAC addresses */
8604 bnx2x_get_mac_hwinfo(bp);
8609 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8611 int cnt, i, block_end, rodi;
8612 char vpd_data[BNX2X_VPD_LEN+1];
8613 char str_id_reg[VENDOR_ID_LEN+1];
8614 char str_id_cap[VENDOR_ID_LEN+1];
8617 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8618 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8620 if (cnt < BNX2X_VPD_LEN)
8623 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8624 PCI_VPD_LRDT_RO_DATA);
8629 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8630 pci_vpd_lrdt_size(&vpd_data[i]);
8632 i += PCI_VPD_LRDT_TAG_SIZE;
8634 if (block_end > BNX2X_VPD_LEN)
8637 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8638 PCI_VPD_RO_KEYWORD_MFR_ID);
8642 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8644 if (len != VENDOR_ID_LEN)
8647 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8649 /* vendor specific info */
8650 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8651 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8652 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8653 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8655 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8656 PCI_VPD_RO_KEYWORD_VENDOR0);
8658 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8660 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8662 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8663 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8664 bp->fw_ver[len] = ' ';
8673 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8679 /* Disable interrupt handling until HW is initialized */
8680 atomic_set(&bp->intr_sem, 1);
8681 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8683 mutex_init(&bp->port.phy_mutex);
8684 mutex_init(&bp->fw_mb_mutex);
8685 spin_lock_init(&bp->stats_lock);
8687 mutex_init(&bp->cnic_mutex);
8690 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8691 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8693 rc = bnx2x_get_hwinfo(bp);
8696 rc = bnx2x_alloc_mem_bp(bp);
8698 bnx2x_read_fwinfo(bp);
8702 /* need to reset chip if undi was active */
8704 bnx2x_undi_unload(bp);
8706 if (CHIP_REV_IS_FPGA(bp))
8707 dev_err(&bp->pdev->dev, "FPGA detected\n");
8709 if (BP_NOMCP(bp) && (func == 0))
8710 dev_err(&bp->pdev->dev, "MCP disabled, "
8711 "must load devices in order!\n");
8713 bp->multi_mode = multi_mode;
8714 bp->int_mode = int_mode;
8716 bp->dev->features |= NETIF_F_GRO;
8720 bp->flags &= ~TPA_ENABLE_FLAG;
8721 bp->dev->features &= ~NETIF_F_LRO;
8723 bp->flags |= TPA_ENABLE_FLAG;
8724 bp->dev->features |= NETIF_F_LRO;
8726 bp->disable_tpa = disable_tpa;
8729 bp->dropless_fc = 0;
8731 bp->dropless_fc = dropless_fc;
8735 bp->tx_ring_size = MAX_TX_AVAIL;
8739 /* make sure that the numbers are in the right granularity */
8740 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8741 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8743 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8744 bp->current_interval = (poll ? poll : timer_interval);
8746 init_timer(&bp->timer);
8747 bp->timer.expires = jiffies + bp->current_interval;
8748 bp->timer.data = (unsigned long) bp;
8749 bp->timer.function = bnx2x_timer;
8751 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8752 bnx2x_dcbx_init_params(bp);
8758 /****************************************************************************
8759 * General service functions
8760 ****************************************************************************/
8762 /* called with rtnl_lock */
8763 static int bnx2x_open(struct net_device *dev)
8765 struct bnx2x *bp = netdev_priv(dev);
8767 netif_carrier_off(dev);
8769 bnx2x_set_power_state(bp, PCI_D0);
8771 if (!bnx2x_reset_is_done(bp)) {
8773 /* Reset MCP mail box sequence if there is on going
8778 /* If it's the first function to load and reset done
8779 * is still not cleared it may mean that. We don't
8780 * check the attention state here because it may have
8781 * already been cleared by a "common" reset but we
8782 * shell proceed with "process kill" anyway.
8784 if ((bnx2x_get_load_cnt(bp) == 0) &&
8785 bnx2x_trylock_hw_lock(bp,
8786 HW_LOCK_RESOURCE_RESERVED_08) &&
8787 (!bnx2x_leader_reset(bp))) {
8788 DP(NETIF_MSG_HW, "Recovered in open\n");
8792 bnx2x_set_power_state(bp, PCI_D3hot);
8794 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8795 " completed yet. Try again later. If u still see this"
8796 " message after a few retries then power cycle is"
8797 " required.\n", bp->dev->name);
8803 bp->recovery_state = BNX2X_RECOVERY_DONE;
8805 return bnx2x_nic_load(bp, LOAD_OPEN);
8808 /* called with rtnl_lock */
8809 static int bnx2x_close(struct net_device *dev)
8811 struct bnx2x *bp = netdev_priv(dev);
8813 /* Unload the driver, release IRQs */
8814 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8815 bnx2x_set_power_state(bp, PCI_D3hot);
8820 /* called with netif_tx_lock from dev_mcast.c */
8821 void bnx2x_set_rx_mode(struct net_device *dev)
8823 struct bnx2x *bp = netdev_priv(dev);
8824 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
8825 int port = BP_PORT(bp);
8827 if (bp->state != BNX2X_STATE_OPEN) {
8828 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
8832 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
8834 if (dev->flags & IFF_PROMISC)
8835 rx_mode = BNX2X_RX_MODE_PROMISC;
8836 else if ((dev->flags & IFF_ALLMULTI) ||
8837 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
8839 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8840 else { /* some multicasts */
8841 if (CHIP_IS_E1(bp)) {
8843 * set mc list, do not wait as wait implies sleep
8844 * and set_rx_mode can be invoked from non-sleepable
8847 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
8848 BNX2X_MAX_EMUL_MULTI*(1 + port) :
8849 BNX2X_MAX_MULTICAST*(1 + port));
8851 bnx2x_set_e1_mc_list(bp, offset);
8853 /* Accept one or more multicasts */
8854 struct netdev_hw_addr *ha;
8855 u32 mc_filter[MC_HASH_SIZE];
8856 u32 crc, bit, regidx;
8859 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
8861 netdev_for_each_mc_addr(ha, dev) {
8862 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
8865 crc = crc32c_le(0, bnx2x_mc_addr(ha),
8867 bit = (crc >> 24) & 0xff;
8870 mc_filter[regidx] |= (1 << bit);
8873 for (i = 0; i < MC_HASH_SIZE; i++)
8874 REG_WR(bp, MC_HASH_OFFSET(bp, i),
8879 bp->rx_mode = rx_mode;
8880 bnx2x_set_storm_rx_mode(bp);
8883 /* called with rtnl_lock */
8884 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
8885 int devad, u16 addr)
8887 struct bnx2x *bp = netdev_priv(netdev);
8891 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
8892 prtad, devad, addr);
8894 /* The HW expects different devad if CL22 is used */
8895 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8897 bnx2x_acquire_phy_lock(bp);
8898 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
8899 bnx2x_release_phy_lock(bp);
8900 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
8907 /* called with rtnl_lock */
8908 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
8909 u16 addr, u16 value)
8911 struct bnx2x *bp = netdev_priv(netdev);
8914 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
8915 " value 0x%x\n", prtad, devad, addr, value);
8917 /* The HW expects different devad if CL22 is used */
8918 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
8920 bnx2x_acquire_phy_lock(bp);
8921 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
8922 bnx2x_release_phy_lock(bp);
8926 /* called with rtnl_lock */
8927 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8929 struct bnx2x *bp = netdev_priv(dev);
8930 struct mii_ioctl_data *mdio = if_mii(ifr);
8932 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
8933 mdio->phy_id, mdio->reg_num, mdio->val_in);
8935 if (!netif_running(dev))
8938 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
8941 #ifdef CONFIG_NET_POLL_CONTROLLER
8942 static void poll_bnx2x(struct net_device *dev)
8944 struct bnx2x *bp = netdev_priv(dev);
8946 disable_irq(bp->pdev->irq);
8947 bnx2x_interrupt(bp->pdev->irq, dev);
8948 enable_irq(bp->pdev->irq);
8952 static const struct net_device_ops bnx2x_netdev_ops = {
8953 .ndo_open = bnx2x_open,
8954 .ndo_stop = bnx2x_close,
8955 .ndo_start_xmit = bnx2x_start_xmit,
8956 .ndo_select_queue = bnx2x_select_queue,
8957 .ndo_set_multicast_list = bnx2x_set_rx_mode,
8958 .ndo_set_mac_address = bnx2x_change_mac_addr,
8959 .ndo_validate_addr = eth_validate_addr,
8960 .ndo_do_ioctl = bnx2x_ioctl,
8961 .ndo_change_mtu = bnx2x_change_mtu,
8962 .ndo_tx_timeout = bnx2x_tx_timeout,
8963 #ifdef CONFIG_NET_POLL_CONTROLLER
8964 .ndo_poll_controller = poll_bnx2x,
8968 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
8969 struct net_device *dev)
8974 SET_NETDEV_DEV(dev, &pdev->dev);
8975 bp = netdev_priv(dev);
8980 bp->pf_num = PCI_FUNC(pdev->devfn);
8982 rc = pci_enable_device(pdev);
8984 dev_err(&bp->pdev->dev,
8985 "Cannot enable PCI device, aborting\n");
8989 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
8990 dev_err(&bp->pdev->dev,
8991 "Cannot find PCI device base address, aborting\n");
8993 goto err_out_disable;
8996 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8997 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
8998 " base address, aborting\n");
9000 goto err_out_disable;
9003 if (atomic_read(&pdev->enable_cnt) == 1) {
9004 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9006 dev_err(&bp->pdev->dev,
9007 "Cannot obtain PCI resources, aborting\n");
9008 goto err_out_disable;
9011 pci_set_master(pdev);
9012 pci_save_state(pdev);
9015 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9016 if (bp->pm_cap == 0) {
9017 dev_err(&bp->pdev->dev,
9018 "Cannot find power management capability, aborting\n");
9020 goto err_out_release;
9023 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9024 if (bp->pcie_cap == 0) {
9025 dev_err(&bp->pdev->dev,
9026 "Cannot find PCI Express capability, aborting\n");
9028 goto err_out_release;
9031 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9032 bp->flags |= USING_DAC_FLAG;
9033 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9034 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9035 " failed, aborting\n");
9037 goto err_out_release;
9040 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9041 dev_err(&bp->pdev->dev,
9042 "System does not support DMA, aborting\n");
9044 goto err_out_release;
9047 dev->mem_start = pci_resource_start(pdev, 0);
9048 dev->base_addr = dev->mem_start;
9049 dev->mem_end = pci_resource_end(pdev, 0);
9051 dev->irq = pdev->irq;
9053 bp->regview = pci_ioremap_bar(pdev, 0);
9055 dev_err(&bp->pdev->dev,
9056 "Cannot map register space, aborting\n");
9058 goto err_out_release;
9061 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9062 min_t(u64, BNX2X_DB_SIZE(bp),
9063 pci_resource_len(pdev, 2)));
9064 if (!bp->doorbells) {
9065 dev_err(&bp->pdev->dev,
9066 "Cannot map doorbell space, aborting\n");
9071 bnx2x_set_power_state(bp, PCI_D0);
9073 /* clean indirect addresses */
9074 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9075 PCICFG_VENDOR_ID_OFFSET);
9076 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9077 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9078 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9079 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9081 /* Reset the load counter */
9082 bnx2x_clear_load_cnt(bp);
9084 dev->watchdog_timeo = TX_TIMEOUT;
9086 dev->netdev_ops = &bnx2x_netdev_ops;
9087 bnx2x_set_ethtool_ops(dev);
9088 dev->features |= NETIF_F_SG;
9089 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9090 if (bp->flags & USING_DAC_FLAG)
9091 dev->features |= NETIF_F_HIGHDMA;
9092 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9093 dev->features |= NETIF_F_TSO6;
9094 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
9096 dev->vlan_features |= NETIF_F_SG;
9097 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
9098 if (bp->flags & USING_DAC_FLAG)
9099 dev->vlan_features |= NETIF_F_HIGHDMA;
9100 dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
9101 dev->vlan_features |= NETIF_F_TSO6;
9104 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9107 /* get_port_hwinfo() will set prtad and mmds properly */
9108 bp->mdio.prtad = MDIO_PRTAD_NONE;
9110 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9112 bp->mdio.mdio_read = bnx2x_mdio_read;
9113 bp->mdio.mdio_write = bnx2x_mdio_write;
9119 iounmap(bp->regview);
9122 if (bp->doorbells) {
9123 iounmap(bp->doorbells);
9124 bp->doorbells = NULL;
9128 if (atomic_read(&pdev->enable_cnt) == 1)
9129 pci_release_regions(pdev);
9132 pci_disable_device(pdev);
9133 pci_set_drvdata(pdev, NULL);
9139 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9140 int *width, int *speed)
9142 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9144 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9146 /* return value of 1=2.5GHz 2=5GHz */
9147 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9150 static int bnx2x_check_firmware(struct bnx2x *bp)
9152 const struct firmware *firmware = bp->firmware;
9153 struct bnx2x_fw_file_hdr *fw_hdr;
9154 struct bnx2x_fw_file_section *sections;
9155 u32 offset, len, num_ops;
9160 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9163 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9164 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9166 /* Make sure none of the offsets and sizes make us read beyond
9167 * the end of the firmware data */
9168 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9169 offset = be32_to_cpu(sections[i].offset);
9170 len = be32_to_cpu(sections[i].len);
9171 if (offset + len > firmware->size) {
9172 dev_err(&bp->pdev->dev,
9173 "Section %d length is out of bounds\n", i);
9178 /* Likewise for the init_ops offsets */
9179 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9180 ops_offsets = (u16 *)(firmware->data + offset);
9181 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9183 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9184 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9185 dev_err(&bp->pdev->dev,
9186 "Section offset %d is out of bounds\n", i);
9191 /* Check FW version */
9192 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9193 fw_ver = firmware->data + offset;
9194 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9195 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9196 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9197 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9198 dev_err(&bp->pdev->dev,
9199 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9200 fw_ver[0], fw_ver[1], fw_ver[2],
9201 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9202 BCM_5710_FW_MINOR_VERSION,
9203 BCM_5710_FW_REVISION_VERSION,
9204 BCM_5710_FW_ENGINEERING_VERSION);
9211 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9213 const __be32 *source = (const __be32 *)_source;
9214 u32 *target = (u32 *)_target;
9217 for (i = 0; i < n/4; i++)
9218 target[i] = be32_to_cpu(source[i]);
9222 Ops array is stored in the following format:
9223 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9225 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9227 const __be32 *source = (const __be32 *)_source;
9228 struct raw_op *target = (struct raw_op *)_target;
9231 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9232 tmp = be32_to_cpu(source[j]);
9233 target[i].op = (tmp >> 24) & 0xff;
9234 target[i].offset = tmp & 0xffffff;
9235 target[i].raw_data = be32_to_cpu(source[j + 1]);
9240 * IRO array is stored in the following format:
9241 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9243 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9245 const __be32 *source = (const __be32 *)_source;
9246 struct iro *target = (struct iro *)_target;
9249 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9250 target[i].base = be32_to_cpu(source[j]);
9252 tmp = be32_to_cpu(source[j]);
9253 target[i].m1 = (tmp >> 16) & 0xffff;
9254 target[i].m2 = tmp & 0xffff;
9256 tmp = be32_to_cpu(source[j]);
9257 target[i].m3 = (tmp >> 16) & 0xffff;
9258 target[i].size = tmp & 0xffff;
9263 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9265 const __be16 *source = (const __be16 *)_source;
9266 u16 *target = (u16 *)_target;
9269 for (i = 0; i < n/2; i++)
9270 target[i] = be16_to_cpu(source[i]);
9273 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9275 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9276 bp->arr = kmalloc(len, GFP_KERNEL); \
9278 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9281 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9282 (u8 *)bp->arr, len); \
9285 int bnx2x_init_firmware(struct bnx2x *bp)
9287 const char *fw_file_name;
9288 struct bnx2x_fw_file_hdr *fw_hdr;
9292 fw_file_name = FW_FILE_NAME_E1;
9293 else if (CHIP_IS_E1H(bp))
9294 fw_file_name = FW_FILE_NAME_E1H;
9295 else if (CHIP_IS_E2(bp))
9296 fw_file_name = FW_FILE_NAME_E2;
9298 BNX2X_ERR("Unsupported chip revision\n");
9302 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9304 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9306 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9307 goto request_firmware_exit;
9310 rc = bnx2x_check_firmware(bp);
9312 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9313 goto request_firmware_exit;
9316 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9318 /* Initialize the pointers to the init arrays */
9320 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9323 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9326 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9329 /* STORMs firmware */
9330 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9331 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9332 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9333 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9334 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9335 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9336 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9337 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9338 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9339 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9340 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9341 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9342 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9343 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9344 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9345 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9347 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9352 kfree(bp->init_ops_offsets);
9353 init_offsets_alloc_err:
9354 kfree(bp->init_ops);
9356 kfree(bp->init_data);
9357 request_firmware_exit:
9358 release_firmware(bp->firmware);
9363 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9365 int cid_count = L2_FP_COUNT(l2_cid_count);
9368 cid_count += CNIC_CID_MAX;
9370 return roundup(cid_count, QM_CID_ROUND);
9373 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9374 const struct pci_device_id *ent)
9376 struct net_device *dev = NULL;
9378 int pcie_width, pcie_speed;
9381 switch (ent->driver_data) {
9385 cid_count = FP_SB_MAX_E1x;
9390 cid_count = FP_SB_MAX_E2;
9394 pr_err("Unknown board_type (%ld), aborting\n",
9399 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9401 /* dev zeroed in init_etherdev */
9402 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9404 dev_err(&pdev->dev, "Cannot allocate net device\n");
9408 bp = netdev_priv(dev);
9409 bp->msg_enable = debug;
9411 pci_set_drvdata(pdev, dev);
9413 bp->l2_cid_count = cid_count;
9415 rc = bnx2x_init_dev(pdev, dev);
9421 rc = bnx2x_init_bp(bp);
9425 /* calc qm_cid_count */
9426 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9429 /* disable FCOE L2 queue for E1x*/
9430 if (CHIP_IS_E1x(bp))
9431 bp->flags |= NO_FCOE_FLAG;
9435 /* Configure interupt mode: try to enable MSI-X/MSI if
9436 * needed, set bp->num_queues appropriately.
9438 bnx2x_set_int_mode(bp);
9440 /* Add all NAPI objects */
9441 bnx2x_add_all_napi(bp);
9443 rc = register_netdev(dev);
9445 dev_err(&pdev->dev, "Cannot register net device\n");
9451 /* Add storage MAC address */
9453 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9458 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9460 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9461 " IRQ %d, ", board_info[ent->driver_data].name,
9462 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9464 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9465 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9466 "5GHz (Gen2)" : "2.5GHz",
9467 dev->base_addr, bp->pdev->irq);
9468 pr_cont("node addr %pM\n", dev->dev_addr);
9474 iounmap(bp->regview);
9477 iounmap(bp->doorbells);
9481 if (atomic_read(&pdev->enable_cnt) == 1)
9482 pci_release_regions(pdev);
9484 pci_disable_device(pdev);
9485 pci_set_drvdata(pdev, NULL);
9490 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9492 struct net_device *dev = pci_get_drvdata(pdev);
9496 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9499 bp = netdev_priv(dev);
9502 /* Delete storage MAC address */
9505 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9510 unregister_netdev(dev);
9512 /* Delete all NAPI objects */
9513 bnx2x_del_all_napi(bp);
9515 /* Power on: we can't let PCI layer write to us while we are in D3 */
9516 bnx2x_set_power_state(bp, PCI_D0);
9518 /* Disable MSI/MSI-X */
9519 bnx2x_disable_msi(bp);
9522 bnx2x_set_power_state(bp, PCI_D3hot);
9524 /* Make sure RESET task is not scheduled before continuing */
9525 cancel_delayed_work_sync(&bp->reset_task);
9528 iounmap(bp->regview);
9531 iounmap(bp->doorbells);
9533 bnx2x_free_mem_bp(bp);
9537 if (atomic_read(&pdev->enable_cnt) == 1)
9538 pci_release_regions(pdev);
9540 pci_disable_device(pdev);
9541 pci_set_drvdata(pdev, NULL);
9544 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9548 bp->state = BNX2X_STATE_ERROR;
9550 bp->rx_mode = BNX2X_RX_MODE_NONE;
9552 bnx2x_netif_stop(bp, 0);
9553 netif_carrier_off(bp->dev);
9555 del_timer_sync(&bp->timer);
9556 bp->stats_state = STATS_STATE_DISABLED;
9557 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9562 /* Free SKBs, SGEs, TPA pool and driver internals */
9563 bnx2x_free_skbs(bp);
9565 for_each_rx_queue(bp, i)
9566 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9570 bp->state = BNX2X_STATE_CLOSED;
9575 static void bnx2x_eeh_recover(struct bnx2x *bp)
9579 mutex_init(&bp->port.phy_mutex);
9581 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9582 bp->link_params.shmem_base = bp->common.shmem_base;
9583 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9585 if (!bp->common.shmem_base ||
9586 (bp->common.shmem_base < 0xA0000) ||
9587 (bp->common.shmem_base >= 0xC0000)) {
9588 BNX2X_DEV_INFO("MCP not active\n");
9589 bp->flags |= NO_MCP_FLAG;
9593 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9594 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9595 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9596 BNX2X_ERR("BAD MCP validity signature\n");
9598 if (!BP_NOMCP(bp)) {
9600 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9601 DRV_MSG_SEQ_NUMBER_MASK);
9602 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9607 * bnx2x_io_error_detected - called when PCI error is detected
9608 * @pdev: Pointer to PCI device
9609 * @state: The current pci connection state
9611 * This function is called after a PCI bus error affecting
9612 * this device has been detected.
9614 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9615 pci_channel_state_t state)
9617 struct net_device *dev = pci_get_drvdata(pdev);
9618 struct bnx2x *bp = netdev_priv(dev);
9622 netif_device_detach(dev);
9624 if (state == pci_channel_io_perm_failure) {
9626 return PCI_ERS_RESULT_DISCONNECT;
9629 if (netif_running(dev))
9630 bnx2x_eeh_nic_unload(bp);
9632 pci_disable_device(pdev);
9636 /* Request a slot reset */
9637 return PCI_ERS_RESULT_NEED_RESET;
9641 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9642 * @pdev: Pointer to PCI device
9644 * Restart the card from scratch, as if from a cold-boot.
9646 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9648 struct net_device *dev = pci_get_drvdata(pdev);
9649 struct bnx2x *bp = netdev_priv(dev);
9653 if (pci_enable_device(pdev)) {
9655 "Cannot re-enable PCI device after reset\n");
9657 return PCI_ERS_RESULT_DISCONNECT;
9660 pci_set_master(pdev);
9661 pci_restore_state(pdev);
9663 if (netif_running(dev))
9664 bnx2x_set_power_state(bp, PCI_D0);
9668 return PCI_ERS_RESULT_RECOVERED;
9672 * bnx2x_io_resume - called when traffic can start flowing again
9673 * @pdev: Pointer to PCI device
9675 * This callback is called when the error recovery driver tells us that
9676 * its OK to resume normal operation.
9678 static void bnx2x_io_resume(struct pci_dev *pdev)
9680 struct net_device *dev = pci_get_drvdata(pdev);
9681 struct bnx2x *bp = netdev_priv(dev);
9683 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9684 printk(KERN_ERR "Handling parity error recovery. "
9685 "Try again later\n");
9691 bnx2x_eeh_recover(bp);
9693 if (netif_running(dev))
9694 bnx2x_nic_load(bp, LOAD_NORMAL);
9696 netif_device_attach(dev);
9701 static struct pci_error_handlers bnx2x_err_handler = {
9702 .error_detected = bnx2x_io_error_detected,
9703 .slot_reset = bnx2x_io_slot_reset,
9704 .resume = bnx2x_io_resume,
9707 static struct pci_driver bnx2x_pci_driver = {
9708 .name = DRV_MODULE_NAME,
9709 .id_table = bnx2x_pci_tbl,
9710 .probe = bnx2x_init_one,
9711 .remove = __devexit_p(bnx2x_remove_one),
9712 .suspend = bnx2x_suspend,
9713 .resume = bnx2x_resume,
9714 .err_handler = &bnx2x_err_handler,
9717 static int __init bnx2x_init(void)
9721 pr_info("%s", version);
9723 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9724 if (bnx2x_wq == NULL) {
9725 pr_err("Cannot create workqueue\n");
9729 ret = pci_register_driver(&bnx2x_pci_driver);
9731 pr_err("Cannot register driver\n");
9732 destroy_workqueue(bnx2x_wq);
9737 static void __exit bnx2x_cleanup(void)
9739 pci_unregister_driver(&bnx2x_pci_driver);
9741 destroy_workqueue(bnx2x_wq);
9744 module_init(bnx2x_init);
9745 module_exit(bnx2x_cleanup);
9749 /* count denotes the number of new completions we have seen */
9750 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9752 struct eth_spe *spe;
9754 #ifdef BNX2X_STOP_ON_ERROR
9755 if (unlikely(bp->panic))
9759 spin_lock_bh(&bp->spq_lock);
9760 BUG_ON(bp->cnic_spq_pending < count);
9761 bp->cnic_spq_pending -= count;
9764 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9765 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9766 & SPE_HDR_CONN_TYPE) >>
9767 SPE_HDR_CONN_TYPE_SHIFT;
9769 /* Set validation for iSCSI L2 client before sending SETUP
9772 if (type == ETH_CONNECTION_TYPE) {
9773 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9774 hdr.conn_and_cmd_data) >>
9775 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9777 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9778 bnx2x_set_ctx_validation(&bp->context.
9779 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9780 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9783 /* There may be not more than 8 L2 and COMMON SPEs and not more
9784 * than 8 L5 SPEs in the air.
9786 if ((type == NONE_CONNECTION_TYPE) ||
9787 (type == ETH_CONNECTION_TYPE)) {
9788 if (!atomic_read(&bp->spq_left))
9791 atomic_dec(&bp->spq_left);
9792 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9793 (type == FCOE_CONNECTION_TYPE)) {
9794 if (bp->cnic_spq_pending >=
9795 bp->cnic_eth_dev.max_kwqe_pending)
9798 bp->cnic_spq_pending++;
9800 BNX2X_ERR("Unknown SPE type: %d\n", type);
9805 spe = bnx2x_sp_get_next(bp);
9806 *spe = *bp->cnic_kwq_cons;
9808 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9809 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9811 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9812 bp->cnic_kwq_cons = bp->cnic_kwq;
9814 bp->cnic_kwq_cons++;
9816 bnx2x_sp_prod_update(bp);
9817 spin_unlock_bh(&bp->spq_lock);
9820 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9821 struct kwqe_16 *kwqes[], u32 count)
9823 struct bnx2x *bp = netdev_priv(dev);
9826 #ifdef BNX2X_STOP_ON_ERROR
9827 if (unlikely(bp->panic))
9831 spin_lock_bh(&bp->spq_lock);
9833 for (i = 0; i < count; i++) {
9834 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
9836 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
9839 *bp->cnic_kwq_prod = *spe;
9841 bp->cnic_kwq_pending++;
9843 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
9844 spe->hdr.conn_and_cmd_data, spe->hdr.type,
9845 spe->data.update_data_addr.hi,
9846 spe->data.update_data_addr.lo,
9847 bp->cnic_kwq_pending);
9849 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
9850 bp->cnic_kwq_prod = bp->cnic_kwq;
9852 bp->cnic_kwq_prod++;
9855 spin_unlock_bh(&bp->spq_lock);
9857 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
9858 bnx2x_cnic_sp_post(bp, 0);
9863 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9865 struct cnic_ops *c_ops;
9868 mutex_lock(&bp->cnic_mutex);
9869 c_ops = bp->cnic_ops;
9871 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9872 mutex_unlock(&bp->cnic_mutex);
9877 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
9879 struct cnic_ops *c_ops;
9883 c_ops = rcu_dereference(bp->cnic_ops);
9885 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
9892 * for commands that have no data
9894 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
9896 struct cnic_ctl_info ctl = {0};
9900 return bnx2x_cnic_ctl_send(bp, &ctl);
9903 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
9905 struct cnic_ctl_info ctl;
9907 /* first we tell CNIC and only then we count this as a completion */
9908 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
9909 ctl.data.comp.cid = cid;
9911 bnx2x_cnic_ctl_send_bh(bp, &ctl);
9912 bnx2x_cnic_sp_post(bp, 0);
9915 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
9917 struct bnx2x *bp = netdev_priv(dev);
9921 case DRV_CTL_CTXTBL_WR_CMD: {
9922 u32 index = ctl->data.io.offset;
9923 dma_addr_t addr = ctl->data.io.dma_addr;
9925 bnx2x_ilt_wr(bp, index, addr);
9929 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
9930 int count = ctl->data.credit.credit_count;
9932 bnx2x_cnic_sp_post(bp, count);
9936 /* rtnl_lock is held. */
9937 case DRV_CTL_START_L2_CMD: {
9938 u32 cli = ctl->data.ring.client_id;
9940 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
9941 bnx2x_del_fcoe_eth_macs(bp);
9943 /* Set iSCSI MAC address */
9944 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
9949 /* Start accepting on iSCSI L2 ring. Accept all multicasts
9950 * because it's the only way for UIO Client to accept
9951 * multicasts (in non-promiscuous mode only one Client per
9952 * function will receive multicast packets (leading in our
9955 bnx2x_rxq_set_mac_filters(bp, cli,
9956 BNX2X_ACCEPT_UNICAST |
9957 BNX2X_ACCEPT_BROADCAST |
9958 BNX2X_ACCEPT_ALL_MULTICAST);
9959 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9964 /* rtnl_lock is held. */
9965 case DRV_CTL_STOP_L2_CMD: {
9966 u32 cli = ctl->data.ring.client_id;
9968 /* Stop accepting on iSCSI L2 ring */
9969 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
9970 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
9975 /* Unset iSCSI L2 MAC */
9976 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
9979 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
9980 int count = ctl->data.credit.credit_count;
9982 smp_mb__before_atomic_inc();
9983 atomic_add(count, &bp->spq_left);
9984 smp_mb__after_atomic_inc();
9989 BNX2X_ERR("unknown command %x\n", ctl->cmd);
9996 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
9998 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10000 if (bp->flags & USING_MSIX_FLAG) {
10001 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10002 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10003 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10005 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10006 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10008 if (CHIP_IS_E2(bp))
10009 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10011 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10013 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10014 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10015 cp->irq_arr[1].status_blk = bp->def_status_blk;
10016 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10017 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10022 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10025 struct bnx2x *bp = netdev_priv(dev);
10026 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10031 if (atomic_read(&bp->intr_sem) != 0)
10034 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10038 bp->cnic_kwq_cons = bp->cnic_kwq;
10039 bp->cnic_kwq_prod = bp->cnic_kwq;
10040 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10042 bp->cnic_spq_pending = 0;
10043 bp->cnic_kwq_pending = 0;
10045 bp->cnic_data = data;
10048 cp->drv_state = CNIC_DRV_STATE_REGD;
10049 cp->iro_arr = bp->iro_arr;
10051 bnx2x_setup_cnic_irq_info(bp);
10053 rcu_assign_pointer(bp->cnic_ops, ops);
10058 static int bnx2x_unregister_cnic(struct net_device *dev)
10060 struct bnx2x *bp = netdev_priv(dev);
10061 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10063 mutex_lock(&bp->cnic_mutex);
10065 rcu_assign_pointer(bp->cnic_ops, NULL);
10066 mutex_unlock(&bp->cnic_mutex);
10068 kfree(bp->cnic_kwq);
10069 bp->cnic_kwq = NULL;
10074 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10076 struct bnx2x *bp = netdev_priv(dev);
10077 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10079 cp->drv_owner = THIS_MODULE;
10080 cp->chip_id = CHIP_ID(bp);
10081 cp->pdev = bp->pdev;
10082 cp->io_base = bp->regview;
10083 cp->io_base2 = bp->doorbells;
10084 cp->max_kwqe_pending = 8;
10085 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10086 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10087 bnx2x_cid_ilt_lines(bp);
10088 cp->ctx_tbl_len = CNIC_ILT_LINES;
10089 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10090 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10091 cp->drv_ctl = bnx2x_drv_ctl;
10092 cp->drv_register_cnic = bnx2x_register_cnic;
10093 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10094 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10095 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10096 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10097 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10099 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10100 "starting cid %d\n",
10102 cp->ctx_tbl_offset,
10107 EXPORT_SYMBOL(bnx2x_cnic_probe);
10109 #endif /* BCM_CNIC */