2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
12 * Your platform definition file should specify something like:
14 * static struct at91_can_data ek_can_data = {
15 * transceiver_switch = sam9263ek_transceiver_switch,
18 * at91_add_device_can(&ek_can_data);
22 #include <linux/clk.h>
23 #include <linux/errno.h>
24 #include <linux/if_arp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/platform_device.h>
31 #include <linux/rtnetlink.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/string.h>
35 #include <linux/types.h>
36 #include <linux/platform_data/atmel.h>
38 #include <linux/can/dev.h>
39 #include <linux/can/error.h>
41 #define AT91_MB_MASK(i) ((1 << (i)) - 1)
43 /* Common registers */
58 /* Mailbox registers (0 <= i <= 15) */
59 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
60 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
61 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
62 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
63 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
64 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
65 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
66 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
69 #define AT91_MR_CANEN BIT(0)
70 #define AT91_MR_LPM BIT(1)
71 #define AT91_MR_ABM BIT(2)
72 #define AT91_MR_OVL BIT(3)
73 #define AT91_MR_TEOF BIT(4)
74 #define AT91_MR_TTM BIT(5)
75 #define AT91_MR_TIMFRZ BIT(6)
76 #define AT91_MR_DRPT BIT(7)
78 #define AT91_SR_RBSY BIT(29)
80 #define AT91_MMR_PRIO_SHIFT (16)
82 #define AT91_MID_MIDE BIT(29)
84 #define AT91_MSR_MRTR BIT(20)
85 #define AT91_MSR_MABT BIT(22)
86 #define AT91_MSR_MRDY BIT(23)
87 #define AT91_MSR_MMI BIT(24)
89 #define AT91_MCR_MRTR BIT(20)
90 #define AT91_MCR_MTCR BIT(23)
94 AT91_MB_MODE_DISABLED = 0,
96 AT91_MB_MODE_RX_OVRWR = 2,
98 AT91_MB_MODE_CONSUMER = 4,
99 AT91_MB_MODE_PRODUCER = 5,
102 /* Interrupt mask bits */
103 #define AT91_IRQ_ERRA (1 << 16)
104 #define AT91_IRQ_WARN (1 << 17)
105 #define AT91_IRQ_ERRP (1 << 18)
106 #define AT91_IRQ_BOFF (1 << 19)
107 #define AT91_IRQ_SLEEP (1 << 20)
108 #define AT91_IRQ_WAKEUP (1 << 21)
109 #define AT91_IRQ_TOVF (1 << 22)
110 #define AT91_IRQ_TSTP (1 << 23)
111 #define AT91_IRQ_CERR (1 << 24)
112 #define AT91_IRQ_SERR (1 << 25)
113 #define AT91_IRQ_AERR (1 << 26)
114 #define AT91_IRQ_FERR (1 << 27)
115 #define AT91_IRQ_BERR (1 << 28)
117 #define AT91_IRQ_ERR_ALL (0x1fff0000)
118 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
119 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
120 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
121 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
123 #define AT91_IRQ_ALL (0x1fffffff)
126 AT91_DEVTYPE_SAM9263,
130 struct at91_devtype_data {
131 unsigned int rx_first;
132 unsigned int rx_split;
133 unsigned int rx_last;
134 unsigned int tx_shift;
135 enum at91_devtype type;
139 struct can_priv can; /* must be the first member! */
140 struct net_device *dev;
141 struct napi_struct napi;
143 void __iomem *reg_base;
146 unsigned int tx_next;
147 unsigned int tx_echo;
148 unsigned int rx_next;
149 struct at91_devtype_data devtype_data;
152 struct at91_can_data *pdata;
157 static const struct at91_devtype_data at91_devtype_data[] __devinitconst = {
158 [AT91_DEVTYPE_SAM9263] = {
164 [AT91_DEVTYPE_SAM9X5] = {
172 static const struct can_bittiming_const at91_bittiming_const = {
173 .name = KBUILD_MODNAME,
184 #define AT91_IS(_model) \
185 static inline int at91_is_sam##_model(const struct at91_priv *priv) \
187 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
193 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
195 return priv->devtype_data.rx_first;
198 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
200 return priv->devtype_data.rx_last;
203 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
205 return priv->devtype_data.rx_split;
208 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
210 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
213 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
215 return get_mb_rx_split(priv) - 1;
218 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
220 return AT91_MB_MASK(get_mb_rx_split(priv)) &
221 ~AT91_MB_MASK(get_mb_rx_first(priv));
224 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
226 return priv->devtype_data.tx_shift;
229 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
231 return 1 << get_mb_tx_shift(priv);
234 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
236 return get_mb_rx_last(priv) + 1;
239 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
241 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
244 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
246 return get_mb_tx_shift(priv);
249 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
251 return 0xf << get_mb_tx_shift(priv);
254 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
256 return AT91_MB_MASK(get_mb_tx_shift(priv));
259 static inline unsigned int get_next_mask(const struct at91_priv *priv)
261 return get_next_mb_mask(priv) | get_next_prio_mask(priv);
264 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
266 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
267 ~AT91_MB_MASK(get_mb_rx_first(priv));
270 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
272 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
273 ~AT91_MB_MASK(get_mb_tx_first(priv));
276 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
278 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
281 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
283 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
286 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
288 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
291 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
293 return __raw_readl(priv->reg_base + reg);
296 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
299 __raw_writel(value, priv->reg_base + reg);
302 static inline void set_mb_mode_prio(const struct at91_priv *priv,
303 unsigned int mb, enum at91_mb_mode mode, int prio)
305 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
308 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
309 enum at91_mb_mode mode)
311 set_mb_mode_prio(priv, mb, mode, 0);
314 static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
318 if (can_id & CAN_EFF_FLAG)
319 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
321 reg_mid = (can_id & CAN_SFF_MASK) << 18;
327 * Swtich transceiver on or off
329 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
331 if (priv->pdata && priv->pdata->transceiver_switch)
332 priv->pdata->transceiver_switch(on);
335 static void at91_setup_mailboxes(struct net_device *dev)
337 struct at91_priv *priv = netdev_priv(dev);
342 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
343 * mailbox is disabled. The next 11 mailboxes are used as a
344 * reception FIFO. The last mailbox is configured with
345 * overwrite option. The overwrite flag indicates a FIFO
348 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
349 for (i = 0; i < get_mb_rx_first(priv); i++) {
350 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
351 at91_write(priv, AT91_MID(i), reg_mid);
352 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */
355 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
356 set_mb_mode(priv, i, AT91_MB_MODE_RX);
357 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
359 /* reset acceptance mask and id register */
360 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
361 at91_write(priv, AT91_MAM(i), 0x0);
362 at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
365 /* The last 4 mailboxes are used for transmitting. */
366 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
367 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
369 /* Reset tx and rx helper pointers */
370 priv->tx_next = priv->tx_echo = 0;
371 priv->rx_next = get_mb_rx_first(priv);
374 static int at91_set_bittiming(struct net_device *dev)
376 const struct at91_priv *priv = netdev_priv(dev);
377 const struct can_bittiming *bt = &priv->can.bittiming;
380 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
381 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
382 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
383 ((bt->phase_seg2 - 1) << 0);
385 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
387 at91_write(priv, AT91_BR, reg_br);
392 static int at91_get_berr_counter(const struct net_device *dev,
393 struct can_berr_counter *bec)
395 const struct at91_priv *priv = netdev_priv(dev);
396 u32 reg_ecr = at91_read(priv, AT91_ECR);
398 bec->rxerr = reg_ecr & 0xff;
399 bec->txerr = reg_ecr >> 16;
404 static void at91_chip_start(struct net_device *dev)
406 struct at91_priv *priv = netdev_priv(dev);
409 /* disable interrupts */
410 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
413 reg_mr = at91_read(priv, AT91_MR);
414 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
416 at91_set_bittiming(dev);
417 at91_setup_mailboxes(dev);
418 at91_transceiver_switch(priv, 1);
421 at91_write(priv, AT91_MR, AT91_MR_CANEN);
423 priv->can.state = CAN_STATE_ERROR_ACTIVE;
425 /* Enable interrupts */
426 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
427 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
428 at91_write(priv, AT91_IER, reg_ier);
431 static void at91_chip_stop(struct net_device *dev, enum can_state state)
433 struct at91_priv *priv = netdev_priv(dev);
436 /* disable interrupts */
437 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
439 reg_mr = at91_read(priv, AT91_MR);
440 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
442 at91_transceiver_switch(priv, 0);
443 priv->can.state = state;
447 * theory of operation:
449 * According to the datasheet priority 0 is the highest priority, 15
450 * is the lowest. If two mailboxes have the same priority level the
451 * message of the mailbox with the lowest number is sent first.
453 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
454 * the next mailbox with prio 0, and so on, until all mailboxes are
455 * used. Then we start from the beginning with mailbox
456 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
457 * prio 1. When we reach the last mailbox with prio 15, we have to
458 * stop sending, waiting for all messages to be delivered, then start
459 * again with mailbox AT91_MB_TX_FIRST prio 0.
461 * We use the priv->tx_next as counter for the next transmission
462 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
463 * encode the mailbox number, the upper 4 bits the mailbox priority:
465 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
466 * (mb - get_mb_tx_first(priv));
469 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
471 struct at91_priv *priv = netdev_priv(dev);
472 struct net_device_stats *stats = &dev->stats;
473 struct can_frame *cf = (struct can_frame *)skb->data;
474 unsigned int mb, prio;
475 u32 reg_mid, reg_mcr;
477 if (can_dropped_invalid_skb(dev, skb))
480 mb = get_tx_next_mb(priv);
481 prio = get_tx_next_prio(priv);
483 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
484 netif_stop_queue(dev);
486 netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
487 return NETDEV_TX_BUSY;
489 reg_mid = at91_can_id_to_reg_mid(cf->can_id);
490 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
491 (cf->can_dlc << 16) | AT91_MCR_MTCR;
493 /* disable MB while writing ID (see datasheet) */
494 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
495 at91_write(priv, AT91_MID(mb), reg_mid);
496 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
498 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
499 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
501 /* This triggers transmission */
502 at91_write(priv, AT91_MCR(mb), reg_mcr);
504 stats->tx_bytes += cf->can_dlc;
506 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
507 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
510 * we have to stop the queue and deliver all messages in case
511 * of a prio+mb counter wrap around. This is the case if
512 * tx_next buffer prio and mailbox equals 0.
514 * also stop the queue if next buffer is still in use
518 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
520 (priv->tx_next & get_next_mask(priv)) == 0)
521 netif_stop_queue(dev);
523 /* Enable interrupt for this mailbox */
524 at91_write(priv, AT91_IER, 1 << mb);
530 * at91_activate_rx_low - activate lower rx mailboxes
533 * Reenables the lower mailboxes for reception of new CAN messages
535 static inline void at91_activate_rx_low(const struct at91_priv *priv)
537 u32 mask = get_mb_rx_low_mask(priv);
538 at91_write(priv, AT91_TCR, mask);
542 * at91_activate_rx_mb - reactive single rx mailbox
544 * @mb: mailbox to reactivate
546 * Reenables given mailbox for reception of new CAN messages
548 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
552 at91_write(priv, AT91_TCR, mask);
556 * at91_rx_overflow_err - send error frame due to rx overflow
559 static void at91_rx_overflow_err(struct net_device *dev)
561 struct net_device_stats *stats = &dev->stats;
563 struct can_frame *cf;
565 netdev_dbg(dev, "RX buffer overflow\n");
566 stats->rx_over_errors++;
569 skb = alloc_can_err_skb(dev, &cf);
573 cf->can_id |= CAN_ERR_CRTL;
574 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
575 netif_receive_skb(skb);
578 stats->rx_bytes += cf->can_dlc;
582 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
584 * @mb: mailbox number to read from
585 * @cf: can frame where to store message
587 * Reads a CAN message from the given mailbox and stores data into
588 * given can frame. "mb" and "cf" must be valid.
590 static void at91_read_mb(struct net_device *dev, unsigned int mb,
591 struct can_frame *cf)
593 const struct at91_priv *priv = netdev_priv(dev);
594 u32 reg_msr, reg_mid;
596 reg_mid = at91_read(priv, AT91_MID(mb));
597 if (reg_mid & AT91_MID_MIDE)
598 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
600 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
602 reg_msr = at91_read(priv, AT91_MSR(mb));
603 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
605 if (reg_msr & AT91_MSR_MRTR)
606 cf->can_id |= CAN_RTR_FLAG;
608 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
609 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
612 /* allow RX of extended frames */
613 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
615 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
616 at91_rx_overflow_err(dev);
620 * at91_read_msg - read CAN message from mailbox
622 * @mb: mail box to read from
624 * Reads a CAN message from given mailbox, and put into linux network
625 * RX queue, does all housekeeping chores (stats, ...)
627 static void at91_read_msg(struct net_device *dev, unsigned int mb)
629 struct net_device_stats *stats = &dev->stats;
630 struct can_frame *cf;
633 skb = alloc_can_skb(dev, &cf);
634 if (unlikely(!skb)) {
639 at91_read_mb(dev, mb, cf);
640 netif_receive_skb(skb);
643 stats->rx_bytes += cf->can_dlc;
647 * at91_poll_rx - read multiple CAN messages from mailboxes
649 * @quota: max number of pkgs we're allowed to receive
651 * Theory of Operation:
653 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
654 * on the chip are reserved for RX. We split them into 2 groups. The
655 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
657 * Like it or not, but the chip always saves a received CAN message
658 * into the first free mailbox it finds (starting with the
659 * lowest). This makes it very difficult to read the messages in the
660 * right order from the chip. This is how we work around that problem:
662 * The first message goes into mb nr. 1 and issues an interrupt. All
663 * rx ints are disabled in the interrupt handler and a napi poll is
664 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
665 * receive another message).
670 * +-+-+-+-+-+-+-+-++-+-+-+-+
671 * | |x|x|x|x|x|x|x|| | | | |
672 * +-+-+-+-+-+-+-+-++-+-+-+-+
673 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
674 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
678 * unused, due to chip bug
680 * The variable priv->rx_next points to the next mailbox to read a
681 * message from. As long we're in the lower mailboxes we just read the
682 * mailbox but not reenable it.
684 * With completion of the last of the lower mailboxes, we reenable the
685 * whole first group, but continue to look for filled mailboxes in the
686 * upper mailboxes. Imagine the second group like overflow mailboxes,
687 * which takes CAN messages if the lower goup is full. While in the
688 * upper group we reenable the mailbox right after reading it. Giving
689 * the chip more room to store messages.
691 * After finishing we look again in the lower group if we've still
695 static int at91_poll_rx(struct net_device *dev, int quota)
697 struct at91_priv *priv = netdev_priv(dev);
698 u32 reg_sr = at91_read(priv, AT91_SR);
699 const unsigned long *addr = (unsigned long *)®_sr;
703 if (priv->rx_next > get_mb_rx_low_last(priv) &&
704 reg_sr & get_mb_rx_low_mask(priv))
706 "order of incoming frames cannot be guaranteed\n");
709 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
710 mb < get_mb_tx_first(priv) && quota > 0;
711 reg_sr = at91_read(priv, AT91_SR),
712 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
713 at91_read_msg(dev, mb);
715 /* reactivate mailboxes */
716 if (mb == get_mb_rx_low_last(priv))
717 /* all lower mailboxed, if just finished it */
718 at91_activate_rx_low(priv);
719 else if (mb > get_mb_rx_low_last(priv))
720 /* only the mailbox we read */
721 at91_activate_rx_mb(priv, mb);
727 /* upper group completed, look again in lower */
728 if (priv->rx_next > get_mb_rx_low_last(priv) &&
729 quota > 0 && mb > get_mb_rx_last(priv)) {
730 priv->rx_next = get_mb_rx_first(priv);
737 static void at91_poll_err_frame(struct net_device *dev,
738 struct can_frame *cf, u32 reg_sr)
740 struct at91_priv *priv = netdev_priv(dev);
743 if (reg_sr & AT91_IRQ_CERR) {
744 netdev_dbg(dev, "CERR irq\n");
745 dev->stats.rx_errors++;
746 priv->can.can_stats.bus_error++;
747 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
751 if (reg_sr & AT91_IRQ_SERR) {
752 netdev_dbg(dev, "SERR irq\n");
753 dev->stats.rx_errors++;
754 priv->can.can_stats.bus_error++;
755 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
756 cf->data[2] |= CAN_ERR_PROT_STUFF;
759 /* Acknowledgement Error */
760 if (reg_sr & AT91_IRQ_AERR) {
761 netdev_dbg(dev, "AERR irq\n");
762 dev->stats.tx_errors++;
763 cf->can_id |= CAN_ERR_ACK;
767 if (reg_sr & AT91_IRQ_FERR) {
768 netdev_dbg(dev, "FERR irq\n");
769 dev->stats.rx_errors++;
770 priv->can.can_stats.bus_error++;
771 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
772 cf->data[2] |= CAN_ERR_PROT_FORM;
776 if (reg_sr & AT91_IRQ_BERR) {
777 netdev_dbg(dev, "BERR irq\n");
778 dev->stats.tx_errors++;
779 priv->can.can_stats.bus_error++;
780 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
781 cf->data[2] |= CAN_ERR_PROT_BIT;
785 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
788 struct can_frame *cf;
793 skb = alloc_can_err_skb(dev, &cf);
797 at91_poll_err_frame(dev, cf, reg_sr);
798 netif_receive_skb(skb);
800 dev->stats.rx_packets++;
801 dev->stats.rx_bytes += cf->can_dlc;
806 static int at91_poll(struct napi_struct *napi, int quota)
808 struct net_device *dev = napi->dev;
809 const struct at91_priv *priv = netdev_priv(dev);
810 u32 reg_sr = at91_read(priv, AT91_SR);
813 if (reg_sr & get_irq_mb_rx(priv))
814 work_done += at91_poll_rx(dev, quota - work_done);
817 * The error bits are clear on read,
818 * so use saved value from irq handler.
820 reg_sr |= priv->reg_sr;
821 if (reg_sr & AT91_IRQ_ERR_FRAME)
822 work_done += at91_poll_err(dev, quota - work_done, reg_sr);
824 if (work_done < quota) {
825 /* enable IRQs for frame errors and all mailboxes >= rx_next */
826 u32 reg_ier = AT91_IRQ_ERR_FRAME;
827 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
830 at91_write(priv, AT91_IER, reg_ier);
837 * theory of operation:
839 * priv->tx_echo holds the number of the oldest can_frame put for
840 * transmission into the hardware, but not yet ACKed by the CAN tx
843 * We iterate from priv->tx_echo to priv->tx_next and check if the
844 * packet has been transmitted, echo it back to the CAN framework. If
845 * we discover a not yet transmitted package, stop looking for more.
848 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
850 struct at91_priv *priv = netdev_priv(dev);
854 /* masking of reg_sr not needed, already done by at91_irq */
856 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
857 mb = get_tx_echo_mb(priv);
859 /* no event in mailbox? */
860 if (!(reg_sr & (1 << mb)))
863 /* Disable irq for this TX mailbox */
864 at91_write(priv, AT91_IDR, 1 << mb);
867 * only echo if mailbox signals us a transfer
868 * complete (MSR_MRDY). Otherwise it's a tansfer
869 * abort. "can_bus_off()" takes care about the skbs
870 * parked in the echo queue.
872 reg_msr = at91_read(priv, AT91_MSR(mb));
873 if (likely(reg_msr & AT91_MSR_MRDY &&
874 ~reg_msr & AT91_MSR_MABT)) {
875 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
876 can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
877 dev->stats.tx_packets++;
882 * restart queue if we don't have a wrap around but restart if
883 * we get a TX int for the last can frame directly before a
886 if ((priv->tx_next & get_next_mask(priv)) != 0 ||
887 (priv->tx_echo & get_next_mask(priv)) == 0)
888 netif_wake_queue(dev);
891 static void at91_irq_err_state(struct net_device *dev,
892 struct can_frame *cf, enum can_state new_state)
894 struct at91_priv *priv = netdev_priv(dev);
895 u32 reg_idr = 0, reg_ier = 0;
896 struct can_berr_counter bec;
898 at91_get_berr_counter(dev, &bec);
900 switch (priv->can.state) {
901 case CAN_STATE_ERROR_ACTIVE:
904 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
905 * => : there was a warning int
907 if (new_state >= CAN_STATE_ERROR_WARNING &&
908 new_state <= CAN_STATE_BUS_OFF) {
909 netdev_dbg(dev, "Error Warning IRQ\n");
910 priv->can.can_stats.error_warning++;
912 cf->can_id |= CAN_ERR_CRTL;
913 cf->data[1] = (bec.txerr > bec.rxerr) ?
914 CAN_ERR_CRTL_TX_WARNING :
915 CAN_ERR_CRTL_RX_WARNING;
917 case CAN_STATE_ERROR_WARNING: /* fallthrough */
919 * from: ERROR_ACTIVE, ERROR_WARNING
920 * to : ERROR_PASSIVE, BUS_OFF
921 * => : error passive int
923 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
924 new_state <= CAN_STATE_BUS_OFF) {
925 netdev_dbg(dev, "Error Passive IRQ\n");
926 priv->can.can_stats.error_passive++;
928 cf->can_id |= CAN_ERR_CRTL;
929 cf->data[1] = (bec.txerr > bec.rxerr) ?
930 CAN_ERR_CRTL_TX_PASSIVE :
931 CAN_ERR_CRTL_RX_PASSIVE;
934 case CAN_STATE_BUS_OFF:
937 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
939 if (new_state <= CAN_STATE_ERROR_PASSIVE) {
940 cf->can_id |= CAN_ERR_RESTARTED;
942 netdev_dbg(dev, "restarted\n");
943 priv->can.can_stats.restarts++;
945 netif_carrier_on(dev);
946 netif_wake_queue(dev);
954 /* process state changes depending on the new state */
956 case CAN_STATE_ERROR_ACTIVE:
958 * actually we want to enable AT91_IRQ_WARN here, but
959 * it screws up the system under certain
960 * circumstances. so just enable AT91_IRQ_ERRP, thus
963 netdev_dbg(dev, "Error Active\n");
964 cf->can_id |= CAN_ERR_PROT;
965 cf->data[2] = CAN_ERR_PROT_ACTIVE;
966 case CAN_STATE_ERROR_WARNING: /* fallthrough */
967 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
968 reg_ier = AT91_IRQ_ERRP;
970 case CAN_STATE_ERROR_PASSIVE:
971 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
972 reg_ier = AT91_IRQ_BOFF;
974 case CAN_STATE_BUS_OFF:
975 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
976 AT91_IRQ_WARN | AT91_IRQ_BOFF;
979 cf->can_id |= CAN_ERR_BUSOFF;
981 netdev_dbg(dev, "bus-off\n");
982 netif_carrier_off(dev);
983 priv->can.can_stats.bus_off++;
985 /* turn off chip, if restart is disabled */
986 if (!priv->can.restart_ms) {
987 at91_chip_stop(dev, CAN_STATE_BUS_OFF);
995 at91_write(priv, AT91_IDR, reg_idr);
996 at91_write(priv, AT91_IER, reg_ier);
999 static int at91_get_state_by_bec(const struct net_device *dev,
1000 enum can_state *state)
1002 struct can_berr_counter bec;
1005 err = at91_get_berr_counter(dev, &bec);
1009 if (bec.txerr < 96 && bec.rxerr < 96)
1010 *state = CAN_STATE_ERROR_ACTIVE;
1011 else if (bec.txerr < 128 && bec.rxerr < 128)
1012 *state = CAN_STATE_ERROR_WARNING;
1013 else if (bec.txerr < 256 && bec.rxerr < 256)
1014 *state = CAN_STATE_ERROR_PASSIVE;
1016 *state = CAN_STATE_BUS_OFF;
1022 static void at91_irq_err(struct net_device *dev)
1024 struct at91_priv *priv = netdev_priv(dev);
1025 struct sk_buff *skb;
1026 struct can_frame *cf;
1027 enum can_state new_state;
1031 if (at91_is_sam9263(priv)) {
1032 reg_sr = at91_read(priv, AT91_SR);
1034 /* we need to look at the unmasked reg_sr */
1035 if (unlikely(reg_sr & AT91_IRQ_BOFF))
1036 new_state = CAN_STATE_BUS_OFF;
1037 else if (unlikely(reg_sr & AT91_IRQ_ERRP))
1038 new_state = CAN_STATE_ERROR_PASSIVE;
1039 else if (unlikely(reg_sr & AT91_IRQ_WARN))
1040 new_state = CAN_STATE_ERROR_WARNING;
1041 else if (likely(reg_sr & AT91_IRQ_ERRA))
1042 new_state = CAN_STATE_ERROR_ACTIVE;
1044 netdev_err(dev, "BUG! hardware in undefined state\n");
1048 err = at91_get_state_by_bec(dev, &new_state);
1053 /* state hasn't changed */
1054 if (likely(new_state == priv->can.state))
1057 skb = alloc_can_err_skb(dev, &cf);
1061 at91_irq_err_state(dev, cf, new_state);
1064 dev->stats.rx_packets++;
1065 dev->stats.rx_bytes += cf->can_dlc;
1067 priv->can.state = new_state;
1073 static irqreturn_t at91_irq(int irq, void *dev_id)
1075 struct net_device *dev = dev_id;
1076 struct at91_priv *priv = netdev_priv(dev);
1077 irqreturn_t handled = IRQ_NONE;
1078 u32 reg_sr, reg_imr;
1080 reg_sr = at91_read(priv, AT91_SR);
1081 reg_imr = at91_read(priv, AT91_IMR);
1083 /* Ignore masked interrupts */
1088 handled = IRQ_HANDLED;
1090 /* Receive or error interrupt? -> napi */
1091 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1093 * The error bits are clear on read,
1094 * save for later use.
1096 priv->reg_sr = reg_sr;
1097 at91_write(priv, AT91_IDR,
1098 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1099 napi_schedule(&priv->napi);
1102 /* Transmission complete interrupt */
1103 if (reg_sr & get_irq_mb_tx(priv))
1104 at91_irq_tx(dev, reg_sr);
1112 static int at91_open(struct net_device *dev)
1114 struct at91_priv *priv = netdev_priv(dev);
1117 clk_enable(priv->clk);
1119 /* check or determine and set bittime */
1120 err = open_candev(dev);
1124 /* register interrupt handler */
1125 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1131 /* start chip and queuing */
1132 at91_chip_start(dev);
1133 napi_enable(&priv->napi);
1134 netif_start_queue(dev);
1141 clk_disable(priv->clk);
1147 * stop CAN bus activity
1149 static int at91_close(struct net_device *dev)
1151 struct at91_priv *priv = netdev_priv(dev);
1153 netif_stop_queue(dev);
1154 napi_disable(&priv->napi);
1155 at91_chip_stop(dev, CAN_STATE_STOPPED);
1157 free_irq(dev->irq, dev);
1158 clk_disable(priv->clk);
1165 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1168 case CAN_MODE_START:
1169 at91_chip_start(dev);
1170 netif_wake_queue(dev);
1180 static const struct net_device_ops at91_netdev_ops = {
1181 .ndo_open = at91_open,
1182 .ndo_stop = at91_close,
1183 .ndo_start_xmit = at91_start_xmit,
1186 static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
1187 struct device_attribute *attr, char *buf)
1189 struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1191 if (priv->mb0_id & CAN_EFF_FLAG)
1192 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
1194 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
1197 static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
1198 struct device_attribute *attr, const char *buf, size_t count)
1200 struct net_device *ndev = to_net_dev(dev);
1201 struct at91_priv *priv = netdev_priv(ndev);
1202 unsigned long can_id;
1208 if (ndev->flags & IFF_UP) {
1213 err = strict_strtoul(buf, 0, &can_id);
1219 if (can_id & CAN_EFF_FLAG)
1220 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1222 can_id &= CAN_SFF_MASK;
1224 priv->mb0_id = can_id;
1232 static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
1233 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
1235 static struct attribute *at91_sysfs_attrs[] = {
1236 &dev_attr_mb0_id.attr,
1240 static struct attribute_group at91_sysfs_attr_group = {
1241 .attrs = at91_sysfs_attrs,
1244 static int __devinit at91_can_probe(struct platform_device *pdev)
1246 const struct at91_devtype_data *devtype_data;
1247 enum at91_devtype devtype;
1248 struct net_device *dev;
1249 struct at91_priv *priv;
1250 struct resource *res;
1255 devtype = pdev->id_entry->driver_data;
1256 devtype_data = &at91_devtype_data[devtype];
1258 clk = clk_get(&pdev->dev, "can_clk");
1260 dev_err(&pdev->dev, "no clock defined\n");
1265 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1266 irq = platform_get_irq(pdev, 0);
1267 if (!res || irq <= 0) {
1272 if (!request_mem_region(res->start,
1279 addr = ioremap_nocache(res->start, resource_size(res));
1285 dev = alloc_candev(sizeof(struct at91_priv),
1286 1 << devtype_data->tx_shift);
1292 dev->netdev_ops = &at91_netdev_ops;
1294 dev->flags |= IFF_ECHO;
1296 priv = netdev_priv(dev);
1297 priv->can.clock.freq = clk_get_rate(clk);
1298 priv->can.bittiming_const = &at91_bittiming_const;
1299 priv->can.do_set_mode = at91_set_mode;
1300 priv->can.do_get_berr_counter = at91_get_berr_counter;
1301 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
1303 priv->reg_base = addr;
1304 priv->devtype_data = *devtype_data;
1305 priv->devtype_data.type = devtype;
1307 priv->pdata = pdev->dev.platform_data;
1308 priv->mb0_id = 0x7ff;
1310 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1312 if (at91_is_sam9263(priv))
1313 dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1315 dev_set_drvdata(&pdev->dev, dev);
1316 SET_NETDEV_DEV(dev, &pdev->dev);
1318 err = register_candev(dev);
1320 dev_err(&pdev->dev, "registering netdev failed\n");
1324 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1325 priv->reg_base, dev->irq);
1334 release_mem_region(res->start, resource_size(res));
1341 static int __devexit at91_can_remove(struct platform_device *pdev)
1343 struct net_device *dev = platform_get_drvdata(pdev);
1344 struct at91_priv *priv = netdev_priv(dev);
1345 struct resource *res;
1347 unregister_netdev(dev);
1349 platform_set_drvdata(pdev, NULL);
1351 iounmap(priv->reg_base);
1353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354 release_mem_region(res->start, resource_size(res));
1363 static const struct platform_device_id at91_can_id_table[] = {
1366 .driver_data = AT91_DEVTYPE_SAM9263,
1368 .name = "at91sam9x5_can",
1369 .driver_data = AT91_DEVTYPE_SAM9X5,
1375 static struct platform_driver at91_can_driver = {
1376 .probe = at91_can_probe,
1377 .remove = __devexit_p(at91_can_remove),
1379 .name = KBUILD_MODNAME,
1380 .owner = THIS_MODULE,
1382 .id_table = at91_can_id_table,
1385 module_platform_driver(at91_can_driver);
1387 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1388 MODULE_LICENSE("GPL v2");
1389 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");