2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/can.h>
40 #include <linux/can/dev.h>
41 #include <linux/can/error.h>
45 /* Number of interface registers */
46 #define IF_ENUM_REG_LEN 11
47 #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
49 /* control extension register D_CAN specific */
50 #define CONTROL_EX_PDR BIT(8)
52 /* control register */
53 #define CONTROL_TEST BIT(7)
54 #define CONTROL_CCE BIT(6)
55 #define CONTROL_DISABLE_AR BIT(5)
56 #define CONTROL_ENABLE_AR (0 << 5)
57 #define CONTROL_EIE BIT(3)
58 #define CONTROL_SIE BIT(2)
59 #define CONTROL_IE BIT(1)
60 #define CONTROL_INIT BIT(0)
63 #define TEST_RX BIT(7)
64 #define TEST_TX1 BIT(6)
65 #define TEST_TX2 BIT(5)
66 #define TEST_LBACK BIT(4)
67 #define TEST_SILENT BIT(3)
68 #define TEST_BASIC BIT(2)
71 #define STATUS_PDA BIT(10)
72 #define STATUS_BOFF BIT(7)
73 #define STATUS_EWARN BIT(6)
74 #define STATUS_EPASS BIT(5)
75 #define STATUS_RXOK BIT(4)
76 #define STATUS_TXOK BIT(3)
78 /* error counter register */
79 #define ERR_CNT_TEC_MASK 0xff
80 #define ERR_CNT_TEC_SHIFT 0
81 #define ERR_CNT_REC_SHIFT 8
82 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
83 #define ERR_CNT_RP_SHIFT 15
84 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
86 /* bit-timing register */
87 #define BTR_BRP_MASK 0x3f
88 #define BTR_BRP_SHIFT 0
89 #define BTR_SJW_SHIFT 6
90 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
91 #define BTR_TSEG1_SHIFT 8
92 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
93 #define BTR_TSEG2_SHIFT 12
94 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
96 /* brp extension register */
97 #define BRP_EXT_BRPE_MASK 0x0f
98 #define BRP_EXT_BRPE_SHIFT 0
100 /* IFx command request */
101 #define IF_COMR_BUSY BIT(15)
103 /* IFx command mask */
104 #define IF_COMM_WR BIT(7)
105 #define IF_COMM_MASK BIT(6)
106 #define IF_COMM_ARB BIT(5)
107 #define IF_COMM_CONTROL BIT(4)
108 #define IF_COMM_CLR_INT_PND BIT(3)
109 #define IF_COMM_TXRQST BIT(2)
110 #define IF_COMM_DATAA BIT(1)
111 #define IF_COMM_DATAB BIT(0)
112 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
113 IF_COMM_CONTROL | IF_COMM_TXRQST | \
114 IF_COMM_DATAA | IF_COMM_DATAB)
116 /* IFx arbitration */
117 #define IF_ARB_MSGVAL BIT(15)
118 #define IF_ARB_MSGXTD BIT(14)
119 #define IF_ARB_TRANSMIT BIT(13)
121 /* IFx message control */
122 #define IF_MCONT_NEWDAT BIT(15)
123 #define IF_MCONT_MSGLST BIT(14)
124 #define IF_MCONT_CLR_MSGLST (0 << 14)
125 #define IF_MCONT_INTPND BIT(13)
126 #define IF_MCONT_UMASK BIT(12)
127 #define IF_MCONT_TXIE BIT(11)
128 #define IF_MCONT_RXIE BIT(10)
129 #define IF_MCONT_RMTEN BIT(9)
130 #define IF_MCONT_TXRQST BIT(8)
131 #define IF_MCONT_EOB BIT(7)
132 #define IF_MCONT_DLC_MASK 0xf
135 * IFx register masks:
136 * allow easy operation on 16-bit registers when the
137 * argument is 32-bit instead
139 #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
140 #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
142 /* message object split */
143 #define C_CAN_NO_OF_OBJECTS 32
144 #define C_CAN_MSG_OBJ_RX_NUM 16
145 #define C_CAN_MSG_OBJ_TX_NUM 16
147 #define C_CAN_MSG_OBJ_RX_FIRST 1
148 #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
149 C_CAN_MSG_OBJ_RX_NUM - 1)
151 #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
152 #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
153 C_CAN_MSG_OBJ_TX_NUM - 1)
155 #define C_CAN_MSG_OBJ_RX_SPLIT 9
156 #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
158 #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
159 #define RECEIVE_OBJECT_BITS 0x0000ffff
161 /* status interrupt */
162 #define STATUS_INTERRUPT 0x8000
164 /* global interrupt masks */
165 #define ENABLE_ALL_INTERRUPTS 1
166 #define DISABLE_ALL_INTERRUPTS 0
168 /* minimum timeout for checking BUSY status */
169 #define MIN_TIMEOUT_VALUE 6
171 /* Wait for ~1 sec for INIT bit */
172 #define INIT_WAIT_MS 1000
175 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
177 /* c_can lec values */
178 enum c_can_lec_type {
191 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
193 enum c_can_bus_error_types {
200 static const struct can_bittiming_const c_can_bittiming_const = {
201 .name = KBUILD_MODNAME,
202 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
204 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
208 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
212 static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv)
215 pm_runtime_enable(priv->device);
218 static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv)
221 pm_runtime_disable(priv->device);
224 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
227 pm_runtime_get_sync(priv->device);
230 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
233 pm_runtime_put_sync(priv->device);
236 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
238 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
239 C_CAN_MSG_OBJ_TX_FIRST;
242 static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
244 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
245 C_CAN_MSG_OBJ_TX_FIRST;
248 static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index)
250 u32 val = priv->read_reg(priv, index);
251 val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
255 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
258 unsigned int cntrl_save = priv->read_reg(priv,
262 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
264 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
266 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save);
269 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
271 int count = MIN_TIMEOUT_VALUE;
273 while (count && priv->read_reg(priv,
274 C_CAN_IFACE(COMREQ_REG, iface)) &
286 static inline void c_can_object_get(struct net_device *dev,
287 int iface, int objno, int mask)
289 struct c_can_priv *priv = netdev_priv(dev);
292 * As per specs, after writting the message object number in the
293 * IF command request register the transfer b/w interface
294 * register and message RAM must be complete in 6 CAN-CLK
297 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
298 IFX_WRITE_LOW_16BIT(mask));
299 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
300 IFX_WRITE_LOW_16BIT(objno));
302 if (c_can_msg_obj_is_busy(priv, iface))
303 netdev_err(dev, "timed out in object get\n");
306 static inline void c_can_object_put(struct net_device *dev,
307 int iface, int objno, int mask)
309 struct c_can_priv *priv = netdev_priv(dev);
312 * As per specs, after writting the message object number in the
313 * IF command request register the transfer b/w interface
314 * register and message RAM must be complete in 6 CAN-CLK
317 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface),
318 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
319 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface),
320 IFX_WRITE_LOW_16BIT(objno));
322 if (c_can_msg_obj_is_busy(priv, iface))
323 netdev_err(dev, "timed out in object put\n");
326 static void c_can_write_msg_object(struct net_device *dev,
327 int iface, struct can_frame *frame, int objno)
332 struct c_can_priv *priv = netdev_priv(dev);
334 if (!(frame->can_id & CAN_RTR_FLAG))
335 flags |= IF_ARB_TRANSMIT;
337 if (frame->can_id & CAN_EFF_FLAG) {
338 id = frame->can_id & CAN_EFF_MASK;
339 flags |= IF_ARB_MSGXTD;
341 id = ((frame->can_id & CAN_SFF_MASK) << 18);
343 flags |= IF_ARB_MSGVAL;
345 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
346 IFX_WRITE_LOW_16BIT(id));
347 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags |
348 IFX_WRITE_HIGH_16BIT(id));
350 for (i = 0; i < frame->can_dlc; i += 2) {
351 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2,
352 frame->data[i] | (frame->data[i + 1] << 8));
355 /* enable interrupt for this message object */
356 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
357 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
359 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
362 static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
363 int iface, int ctrl_mask,
366 struct c_can_priv *priv = netdev_priv(dev);
368 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
369 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
370 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
374 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
379 struct c_can_priv *priv = netdev_priv(dev);
381 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
382 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
383 ctrl_mask & ~(IF_MCONT_MSGLST |
384 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
385 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
389 static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
390 int iface, int ctrl_mask,
393 struct c_can_priv *priv = netdev_priv(dev);
395 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
396 ctrl_mask & ~(IF_MCONT_MSGLST |
397 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
398 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
401 static void c_can_handle_lost_msg_obj(struct net_device *dev,
402 int iface, int objno)
404 struct c_can_priv *priv = netdev_priv(dev);
405 struct net_device_stats *stats = &dev->stats;
407 struct can_frame *frame;
409 netdev_err(dev, "msg lost in buffer %d\n", objno);
411 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
413 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface),
414 IF_MCONT_CLR_MSGLST);
416 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
418 /* create an error msg */
419 skb = alloc_can_err_skb(dev, &frame);
423 frame->can_id |= CAN_ERR_CRTL;
424 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
426 stats->rx_over_errors++;
428 netif_receive_skb(skb);
431 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
436 struct c_can_priv *priv = netdev_priv(dev);
437 struct net_device_stats *stats = &dev->stats;
439 struct can_frame *frame;
441 skb = alloc_can_skb(dev, &frame);
447 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
449 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface));
450 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) |
453 if (flags & IF_ARB_MSGXTD)
454 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
456 frame->can_id = (val >> 18) & CAN_SFF_MASK;
458 if (flags & IF_ARB_TRANSMIT)
459 frame->can_id |= CAN_RTR_FLAG;
461 for (i = 0; i < frame->can_dlc; i += 2) {
462 data = priv->read_reg(priv,
463 C_CAN_IFACE(DATA1_REG, iface) + i / 2);
464 frame->data[i] = data;
465 frame->data[i + 1] = data >> 8;
469 netif_receive_skb(skb);
472 stats->rx_bytes += frame->can_dlc;
477 static void c_can_setup_receive_object(struct net_device *dev, int iface,
478 int objno, unsigned int mask,
479 unsigned int id, unsigned int mcont)
481 struct c_can_priv *priv = netdev_priv(dev);
483 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface),
484 IFX_WRITE_LOW_16BIT(mask));
485 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface),
486 IFX_WRITE_HIGH_16BIT(mask));
488 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface),
489 IFX_WRITE_LOW_16BIT(id));
490 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface),
491 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
493 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
494 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
496 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
497 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
500 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
502 struct c_can_priv *priv = netdev_priv(dev);
504 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
505 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0);
506 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
508 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
510 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
511 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG));
514 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
516 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
519 * as transmission request register's bit n-1 corresponds to
520 * message object n, we need to handle the same properly.
522 if (val & (1 << (objno - 1)))
528 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
529 struct net_device *dev)
532 struct c_can_priv *priv = netdev_priv(dev);
533 struct can_frame *frame = (struct can_frame *)skb->data;
535 if (can_dropped_invalid_skb(dev, skb))
538 msg_obj_no = get_tx_next_msg_obj(priv);
540 /* prepare message object for transmission */
541 c_can_write_msg_object(dev, 0, frame, msg_obj_no);
542 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
545 * we have to stop the queue in case of a wrap around or
546 * if the next TX message object is still in use
549 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
550 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
551 netif_stop_queue(dev);
556 static int c_can_set_bittiming(struct net_device *dev)
558 unsigned int reg_btr, reg_brpe, ctrl_save;
559 u8 brp, brpe, sjw, tseg1, tseg2;
561 struct c_can_priv *priv = netdev_priv(dev);
562 const struct can_bittiming *bt = &priv->can.bittiming;
564 /* c_can provides a 6-bit brp and 4-bit brpe fields */
565 ten_bit_brp = bt->brp - 1;
566 brp = ten_bit_brp & BTR_BRP_MASK;
567 brpe = ten_bit_brp >> 6;
570 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
571 tseg2 = bt->phase_seg2 - 1;
572 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
573 (tseg2 << BTR_TSEG2_SHIFT);
574 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
577 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
579 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
580 priv->write_reg(priv, C_CAN_CTRL_REG,
581 ctrl_save | CONTROL_CCE | CONTROL_INIT);
582 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
583 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
584 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
590 * Configure C_CAN message objects for Tx and Rx purposes:
591 * C_CAN provides a total of 32 message objects that can be configured
592 * either for Tx or Rx purposes. Here the first 16 message objects are used as
593 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
594 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
595 * See user guide document for further details on configuring message
598 static void c_can_configure_msg_objects(struct net_device *dev)
602 /* first invalidate all message objects */
603 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
604 c_can_inval_msg_object(dev, 0, i);
606 /* setup receive message objects */
607 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
608 c_can_setup_receive_object(dev, 0, i, 0, 0,
609 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
611 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
612 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
616 * Configure C_CAN chip:
617 * - enable/disable auto-retransmission
618 * - set operating mode
619 * - configure message objects
621 static void c_can_chip_config(struct net_device *dev)
623 struct c_can_priv *priv = netdev_priv(dev);
625 /* enable automatic retransmission */
626 priv->write_reg(priv, C_CAN_CTRL_REG,
629 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
630 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
631 /* loopback + silent mode : useful for hot self-test */
632 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
633 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
634 priv->write_reg(priv, C_CAN_TEST_REG,
635 TEST_LBACK | TEST_SILENT);
636 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
637 /* loopback mode : useful for self-test function */
638 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
639 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
640 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
641 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
642 /* silent mode : bus-monitoring mode */
643 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE |
644 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
645 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
648 priv->write_reg(priv, C_CAN_CTRL_REG,
649 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
651 /* configure message objects */
652 c_can_configure_msg_objects(dev);
654 /* set a `lec` value so that we can check for updates later */
655 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
657 /* set bittiming params */
658 c_can_set_bittiming(dev);
661 static void c_can_start(struct net_device *dev)
663 struct c_can_priv *priv = netdev_priv(dev);
665 /* basic c_can configuration */
666 c_can_chip_config(dev);
668 priv->can.state = CAN_STATE_ERROR_ACTIVE;
670 /* reset tx helper pointers */
671 priv->tx_next = priv->tx_echo = 0;
673 /* enable status change, error and module interrupts */
674 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
677 static void c_can_stop(struct net_device *dev)
679 struct c_can_priv *priv = netdev_priv(dev);
681 /* disable all interrupts */
682 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
684 /* set the state as STOPPED */
685 priv->can.state = CAN_STATE_STOPPED;
688 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
693 netif_wake_queue(dev);
702 static int c_can_get_berr_counter(const struct net_device *dev,
703 struct can_berr_counter *bec)
705 unsigned int reg_err_counter;
706 struct c_can_priv *priv = netdev_priv(dev);
708 c_can_pm_runtime_get_sync(priv);
710 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
711 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
713 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
715 c_can_pm_runtime_put_sync(priv);
721 * theory of operation:
723 * priv->tx_echo holds the number of the oldest can_frame put for
724 * transmission into the hardware, but not yet ACKed by the CAN tx
727 * We iterate from priv->tx_echo to priv->tx_next and check if the
728 * packet has been transmitted, echo it back to the CAN framework.
729 * If we discover a not yet transmitted packet, stop looking for more.
731 static void c_can_do_tx(struct net_device *dev)
735 struct c_can_priv *priv = netdev_priv(dev);
736 struct net_device_stats *stats = &dev->stats;
738 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
739 msg_obj_no = get_tx_echo_msg_obj(priv);
740 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG);
741 if (!(val & (1 << (msg_obj_no - 1)))) {
742 can_get_echo_skb(dev,
743 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
744 stats->tx_bytes += priv->read_reg(priv,
745 C_CAN_IFACE(MSGCTRL_REG, 0))
748 c_can_inval_msg_object(dev, 0, msg_obj_no);
754 /* restart queue if wrap-up or if queue stalled on last pkt */
755 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
756 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
757 netif_wake_queue(dev);
761 * theory of operation:
763 * c_can core saves a received CAN message into the first free message
764 * object it finds free (starting with the lowest). Bits NEWDAT and
765 * INTPND are set for this message object indicating that a new message
766 * has arrived. To work-around this issue, we keep two groups of message
767 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
769 * To ensure in-order frame reception we use the following
770 * approach while re-activating a message object to receive further
772 * - if the current message object number is lower than
773 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
775 * - if the current message object number is equal to
776 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
777 * receive message objects.
778 * - if the current message object number is greater than
779 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
780 * only this message object.
782 static int c_can_do_rx_poll(struct net_device *dev, int quota)
785 unsigned int msg_obj, msg_ctrl_save;
786 struct c_can_priv *priv = netdev_priv(dev);
787 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG);
789 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
790 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
791 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG),
794 * as interrupt pending register's bit n-1 corresponds to
795 * message object n, we need to handle the same properly.
797 if (val & (1 << (msg_obj - 1))) {
798 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
800 msg_ctrl_save = priv->read_reg(priv,
801 C_CAN_IFACE(MSGCTRL_REG, 0));
803 if (msg_ctrl_save & IF_MCONT_EOB)
806 if (msg_ctrl_save & IF_MCONT_MSGLST) {
807 c_can_handle_lost_msg_obj(dev, 0, msg_obj);
813 if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
816 /* read the data from the message object */
817 c_can_read_msg_object(dev, 0, msg_ctrl_save);
819 if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
820 c_can_mark_rx_msg_obj(dev, 0,
821 msg_ctrl_save, msg_obj);
822 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
823 /* activate this msg obj */
824 c_can_activate_rx_msg_obj(dev, 0,
825 msg_ctrl_save, msg_obj);
826 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
827 /* activate all lower message objects */
828 c_can_activate_all_lower_rx_msg_obj(dev,
839 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
841 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
842 (priv->current_status & LEC_UNUSED);
845 static int c_can_handle_state_change(struct net_device *dev,
846 enum c_can_bus_error_types error_type)
848 unsigned int reg_err_counter;
849 unsigned int rx_err_passive;
850 struct c_can_priv *priv = netdev_priv(dev);
851 struct net_device_stats *stats = &dev->stats;
852 struct can_frame *cf;
854 struct can_berr_counter bec;
856 /* propagate the error condition to the CAN stack */
857 skb = alloc_can_err_skb(dev, &cf);
861 c_can_get_berr_counter(dev, &bec);
862 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
863 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
866 switch (error_type) {
867 case C_CAN_ERROR_WARNING:
868 /* error warning state */
869 priv->can.can_stats.error_warning++;
870 priv->can.state = CAN_STATE_ERROR_WARNING;
871 cf->can_id |= CAN_ERR_CRTL;
872 cf->data[1] = (bec.txerr > bec.rxerr) ?
873 CAN_ERR_CRTL_TX_WARNING :
874 CAN_ERR_CRTL_RX_WARNING;
875 cf->data[6] = bec.txerr;
876 cf->data[7] = bec.rxerr;
879 case C_CAN_ERROR_PASSIVE:
880 /* error passive state */
881 priv->can.can_stats.error_passive++;
882 priv->can.state = CAN_STATE_ERROR_PASSIVE;
883 cf->can_id |= CAN_ERR_CRTL;
885 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
887 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
889 cf->data[6] = bec.txerr;
890 cf->data[7] = bec.rxerr;
894 priv->can.state = CAN_STATE_BUS_OFF;
895 cf->can_id |= CAN_ERR_BUSOFF;
897 * disable all interrupts in bus-off mode to ensure that
898 * the CPU is not hogged down
900 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
907 netif_receive_skb(skb);
909 stats->rx_bytes += cf->can_dlc;
914 static int c_can_handle_bus_err(struct net_device *dev,
915 enum c_can_lec_type lec_type)
917 struct c_can_priv *priv = netdev_priv(dev);
918 struct net_device_stats *stats = &dev->stats;
919 struct can_frame *cf;
923 * early exit if no lec update or no error.
924 * no lec update means that no CAN bus event has been detected
925 * since CPU wrote 0x7 value to status reg.
927 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
930 /* propagate the error condition to the CAN stack */
931 skb = alloc_can_err_skb(dev, &cf);
936 * check for 'last error code' which tells us the
937 * type of the last error to occur on the CAN bus
940 /* common for all type of bus errors */
941 priv->can.can_stats.bus_error++;
943 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
944 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
947 case LEC_STUFF_ERROR:
948 netdev_dbg(dev, "stuff error\n");
949 cf->data[2] |= CAN_ERR_PROT_STUFF;
952 netdev_dbg(dev, "form error\n");
953 cf->data[2] |= CAN_ERR_PROT_FORM;
956 netdev_dbg(dev, "ack error\n");
957 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
958 CAN_ERR_PROT_LOC_ACK_DEL);
961 netdev_dbg(dev, "bit1 error\n");
962 cf->data[2] |= CAN_ERR_PROT_BIT1;
965 netdev_dbg(dev, "bit0 error\n");
966 cf->data[2] |= CAN_ERR_PROT_BIT0;
969 netdev_dbg(dev, "CRC error\n");
970 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
971 CAN_ERR_PROT_LOC_CRC_DEL);
977 /* set a `lec` value so that we can check for updates later */
978 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
980 netif_receive_skb(skb);
982 stats->rx_bytes += cf->can_dlc;
987 static int c_can_poll(struct napi_struct *napi, int quota)
992 struct net_device *dev = napi->dev;
993 struct c_can_priv *priv = netdev_priv(dev);
995 irqstatus = priv->irqstatus;
999 /* status events have the highest priority */
1000 if (irqstatus == STATUS_INTERRUPT) {
1001 priv->current_status = priv->read_reg(priv,
1004 /* handle Tx/Rx events */
1005 if (priv->current_status & STATUS_TXOK)
1006 priv->write_reg(priv, C_CAN_STS_REG,
1007 priv->current_status & ~STATUS_TXOK);
1009 if (priv->current_status & STATUS_RXOK)
1010 priv->write_reg(priv, C_CAN_STS_REG,
1011 priv->current_status & ~STATUS_RXOK);
1013 /* handle state changes */
1014 if ((priv->current_status & STATUS_EWARN) &&
1015 (!(priv->last_status & STATUS_EWARN))) {
1016 netdev_dbg(dev, "entered error warning state\n");
1017 work_done += c_can_handle_state_change(dev,
1018 C_CAN_ERROR_WARNING);
1020 if ((priv->current_status & STATUS_EPASS) &&
1021 (!(priv->last_status & STATUS_EPASS))) {
1022 netdev_dbg(dev, "entered error passive state\n");
1023 work_done += c_can_handle_state_change(dev,
1024 C_CAN_ERROR_PASSIVE);
1026 if ((priv->current_status & STATUS_BOFF) &&
1027 (!(priv->last_status & STATUS_BOFF))) {
1028 netdev_dbg(dev, "entered bus off state\n");
1029 work_done += c_can_handle_state_change(dev,
1033 /* handle bus recovery events */
1034 if ((!(priv->current_status & STATUS_BOFF)) &&
1035 (priv->last_status & STATUS_BOFF)) {
1036 netdev_dbg(dev, "left bus off state\n");
1037 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1039 if ((!(priv->current_status & STATUS_EPASS)) &&
1040 (priv->last_status & STATUS_EPASS)) {
1041 netdev_dbg(dev, "left error passive state\n");
1042 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1045 priv->last_status = priv->current_status;
1047 /* handle lec errors on the bus */
1048 lec_type = c_can_has_and_handle_berr(priv);
1050 work_done += c_can_handle_bus_err(dev, lec_type);
1051 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1052 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1053 /* handle events corresponding to receive message objects */
1054 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1055 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1056 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1057 /* handle events corresponding to transmit message objects */
1062 if (work_done < quota) {
1063 napi_complete(napi);
1064 /* enable all IRQs */
1065 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1071 static irqreturn_t c_can_isr(int irq, void *dev_id)
1073 struct net_device *dev = (struct net_device *)dev_id;
1074 struct c_can_priv *priv = netdev_priv(dev);
1076 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG);
1077 if (!priv->irqstatus)
1080 /* disable all interrupts and schedule the NAPI */
1081 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1082 napi_schedule(&priv->napi);
1087 static int c_can_open(struct net_device *dev)
1090 struct c_can_priv *priv = netdev_priv(dev);
1092 c_can_pm_runtime_get_sync(priv);
1094 /* open the can device */
1095 err = open_candev(dev);
1097 netdev_err(dev, "failed to open can device\n");
1098 goto exit_open_fail;
1101 /* register interrupt handler */
1102 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1105 netdev_err(dev, "failed to request interrupt\n");
1109 napi_enable(&priv->napi);
1111 /* start the c_can controller */
1114 netif_start_queue(dev);
1121 c_can_pm_runtime_put_sync(priv);
1125 static int c_can_close(struct net_device *dev)
1127 struct c_can_priv *priv = netdev_priv(dev);
1129 netif_stop_queue(dev);
1130 napi_disable(&priv->napi);
1132 free_irq(dev->irq, dev);
1134 c_can_pm_runtime_put_sync(priv);
1139 struct net_device *alloc_c_can_dev(void)
1141 struct net_device *dev;
1142 struct c_can_priv *priv;
1144 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1148 priv = netdev_priv(dev);
1149 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1152 priv->can.bittiming_const = &c_can_bittiming_const;
1153 priv->can.do_set_mode = c_can_set_mode;
1154 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1155 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1156 CAN_CTRLMODE_LISTENONLY |
1157 CAN_CTRLMODE_BERR_REPORTING;
1161 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1164 int c_can_power_down(struct net_device *dev)
1167 unsigned long time_out;
1168 struct c_can_priv *priv = netdev_priv(dev);
1170 if (!(dev->flags & IFF_UP))
1173 WARN_ON(priv->type != BOSCH_D_CAN);
1175 /* set PDR value so the device goes to power down mode */
1176 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1177 val |= CONTROL_EX_PDR;
1178 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1180 /* Wait for the PDA bit to get set */
1181 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1182 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1183 time_after(time_out, jiffies))
1186 if (time_after(jiffies, time_out))
1191 c_can_pm_runtime_put_sync(priv);
1195 EXPORT_SYMBOL_GPL(c_can_power_down);
1197 int c_can_power_up(struct net_device *dev)
1200 unsigned long time_out;
1201 struct c_can_priv *priv = netdev_priv(dev);
1203 if (!(dev->flags & IFF_UP))
1206 WARN_ON(priv->type != BOSCH_D_CAN);
1208 c_can_pm_runtime_get_sync(priv);
1210 /* Clear PDR and INIT bits */
1211 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1212 val &= ~CONTROL_EX_PDR;
1213 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1214 val = priv->read_reg(priv, C_CAN_CTRL_REG);
1215 val &= ~CONTROL_INIT;
1216 priv->write_reg(priv, C_CAN_CTRL_REG, val);
1218 /* Wait for the PDA bit to get clear */
1219 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1220 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1221 time_after(time_out, jiffies))
1224 if (time_after(jiffies, time_out))
1231 EXPORT_SYMBOL_GPL(c_can_power_up);
1234 void free_c_can_dev(struct net_device *dev)
1238 EXPORT_SYMBOL_GPL(free_c_can_dev);
1240 static const struct net_device_ops c_can_netdev_ops = {
1241 .ndo_open = c_can_open,
1242 .ndo_stop = c_can_close,
1243 .ndo_start_xmit = c_can_start_xmit,
1246 int register_c_can_dev(struct net_device *dev)
1248 struct c_can_priv *priv = netdev_priv(dev);
1251 c_can_pm_runtime_enable(priv);
1253 dev->flags |= IFF_ECHO; /* we support local echo */
1254 dev->netdev_ops = &c_can_netdev_ops;
1256 err = register_candev(dev);
1258 c_can_pm_runtime_disable(priv);
1262 EXPORT_SYMBOL_GPL(register_c_can_dev);
1264 void unregister_c_can_dev(struct net_device *dev)
1266 struct c_can_priv *priv = netdev_priv(dev);
1268 unregister_candev(dev);
1270 c_can_pm_runtime_disable(priv);
1272 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1274 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1275 MODULE_LICENSE("GPL v2");
1276 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");