2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/platform/flexcan.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/platform_device.h>
38 #include <linux/pinctrl/consumer.h>
40 #define DRV_NAME "flexcan"
42 /* 8 for RX fifo and 2 error handling */
43 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
45 /* FLEXCAN module configuration register (CANMCR) bits */
46 #define FLEXCAN_MCR_MDIS BIT(31)
47 #define FLEXCAN_MCR_FRZ BIT(30)
48 #define FLEXCAN_MCR_FEN BIT(29)
49 #define FLEXCAN_MCR_HALT BIT(28)
50 #define FLEXCAN_MCR_NOT_RDY BIT(27)
51 #define FLEXCAN_MCR_WAK_MSK BIT(26)
52 #define FLEXCAN_MCR_SOFTRST BIT(25)
53 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
54 #define FLEXCAN_MCR_SUPV BIT(23)
55 #define FLEXCAN_MCR_SLF_WAK BIT(22)
56 #define FLEXCAN_MCR_WRN_EN BIT(21)
57 #define FLEXCAN_MCR_LPM_ACK BIT(20)
58 #define FLEXCAN_MCR_WAK_SRC BIT(19)
59 #define FLEXCAN_MCR_DOZE BIT(18)
60 #define FLEXCAN_MCR_SRX_DIS BIT(17)
61 #define FLEXCAN_MCR_BCC BIT(16)
62 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
63 #define FLEXCAN_MCR_AEN BIT(12)
64 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
65 #define FLEXCAN_MCR_IDAM_A (0 << 8)
66 #define FLEXCAN_MCR_IDAM_B (1 << 8)
67 #define FLEXCAN_MCR_IDAM_C (2 << 8)
68 #define FLEXCAN_MCR_IDAM_D (3 << 8)
70 /* FLEXCAN control register (CANCTRL) bits */
71 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
72 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
73 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
74 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
75 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
76 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
77 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
78 #define FLEXCAN_CTRL_LPB BIT(12)
79 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
80 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
81 #define FLEXCAN_CTRL_SMP BIT(7)
82 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
83 #define FLEXCAN_CTRL_TSYN BIT(5)
84 #define FLEXCAN_CTRL_LBUF BIT(4)
85 #define FLEXCAN_CTRL_LOM BIT(3)
86 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
87 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
88 #define FLEXCAN_CTRL_ERR_STATE \
89 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
90 FLEXCAN_CTRL_BOFF_MSK)
91 #define FLEXCAN_CTRL_ERR_ALL \
92 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94 /* FLEXCAN error and status register (ESR) bits */
95 #define FLEXCAN_ESR_TWRN_INT BIT(17)
96 #define FLEXCAN_ESR_RWRN_INT BIT(16)
97 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
98 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
99 #define FLEXCAN_ESR_ACK_ERR BIT(13)
100 #define FLEXCAN_ESR_CRC_ERR BIT(12)
101 #define FLEXCAN_ESR_FRM_ERR BIT(11)
102 #define FLEXCAN_ESR_STF_ERR BIT(10)
103 #define FLEXCAN_ESR_TX_WRN BIT(9)
104 #define FLEXCAN_ESR_RX_WRN BIT(8)
105 #define FLEXCAN_ESR_IDLE BIT(7)
106 #define FLEXCAN_ESR_TXRX BIT(6)
107 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
108 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
109 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_BOFF_INT BIT(2)
112 #define FLEXCAN_ESR_ERR_INT BIT(1)
113 #define FLEXCAN_ESR_WAK_INT BIT(0)
114 #define FLEXCAN_ESR_ERR_BUS \
115 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
116 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
117 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
118 #define FLEXCAN_ESR_ERR_STATE \
119 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
120 #define FLEXCAN_ESR_ERR_ALL \
121 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
122 #define FLEXCAN_ESR_ALL_INT \
123 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
124 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
126 /* FLEXCAN interrupt flag register (IFLAG) bits */
127 #define FLEXCAN_TX_BUF_ID 8
128 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
129 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
130 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
131 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
132 #define FLEXCAN_IFLAG_DEFAULT \
133 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
134 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136 /* FLEXCAN message buffers */
137 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
138 #define FLEXCAN_MB_CNT_SRR BIT(22)
139 #define FLEXCAN_MB_CNT_IDE BIT(21)
140 #define FLEXCAN_MB_CNT_RTR BIT(20)
141 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
142 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146 /* Structure of the message buffer */
153 /* Structure of the hardware registers */
154 struct flexcan_regs {
157 u32 timer; /* 0x08 */
158 u32 _reserved1; /* 0x0c */
159 u32 rxgmask; /* 0x10 */
160 u32 rx14mask; /* 0x14 */
161 u32 rx15mask; /* 0x18 */
164 u32 imask2; /* 0x24 */
165 u32 imask1; /* 0x28 */
166 u32 iflag2; /* 0x2c */
167 u32 iflag1; /* 0x30 */
169 struct flexcan_mb cantxfg[64];
172 struct flexcan_priv {
174 struct net_device *dev;
175 struct napi_struct napi;
179 u32 reg_ctrl_default;
182 struct flexcan_platform_data *pdata;
185 static struct can_bittiming_const flexcan_bittiming_const = {
198 * Abstract off the read/write for arm versus ppc.
200 #if defined(__BIG_ENDIAN)
201 static inline u32 flexcan_read(void __iomem *addr)
203 return in_be32(addr);
206 static inline void flexcan_write(u32 val, void __iomem *addr)
211 static inline u32 flexcan_read(void __iomem *addr)
216 static inline void flexcan_write(u32 val, void __iomem *addr)
223 * Swtich transceiver on or off
225 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
227 if (priv->pdata && priv->pdata->transceiver_switch)
228 priv->pdata->transceiver_switch(on);
231 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
234 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
235 (reg_esr & FLEXCAN_ESR_ERR_BUS);
238 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
240 struct flexcan_regs __iomem *regs = priv->base;
243 reg = flexcan_read(®s->mcr);
244 reg &= ~FLEXCAN_MCR_MDIS;
245 flexcan_write(reg, ®s->mcr);
250 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
252 struct flexcan_regs __iomem *regs = priv->base;
255 reg = flexcan_read(®s->mcr);
256 reg |= FLEXCAN_MCR_MDIS;
257 flexcan_write(reg, ®s->mcr);
260 static int flexcan_get_berr_counter(const struct net_device *dev,
261 struct can_berr_counter *bec)
263 const struct flexcan_priv *priv = netdev_priv(dev);
264 struct flexcan_regs __iomem *regs = priv->base;
265 u32 reg = flexcan_read(®s->ecr);
267 bec->txerr = (reg >> 0) & 0xff;
268 bec->rxerr = (reg >> 8) & 0xff;
273 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
275 const struct flexcan_priv *priv = netdev_priv(dev);
276 struct flexcan_regs __iomem *regs = priv->base;
277 struct can_frame *cf = (struct can_frame *)skb->data;
279 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
281 if (can_dropped_invalid_skb(dev, skb))
284 netif_stop_queue(dev);
286 if (cf->can_id & CAN_EFF_FLAG) {
287 can_id = cf->can_id & CAN_EFF_MASK;
288 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
290 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
293 if (cf->can_id & CAN_RTR_FLAG)
294 ctrl |= FLEXCAN_MB_CNT_RTR;
296 if (cf->can_dlc > 0) {
297 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
298 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
300 if (cf->can_dlc > 3) {
301 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
302 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
305 can_put_echo_skb(skb, dev, 0);
307 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
308 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
313 static void do_bus_err(struct net_device *dev,
314 struct can_frame *cf, u32 reg_esr)
316 struct flexcan_priv *priv = netdev_priv(dev);
317 int rx_errors = 0, tx_errors = 0;
319 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
321 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
322 netdev_dbg(dev, "BIT1_ERR irq\n");
323 cf->data[2] |= CAN_ERR_PROT_BIT1;
326 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
327 netdev_dbg(dev, "BIT0_ERR irq\n");
328 cf->data[2] |= CAN_ERR_PROT_BIT0;
331 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
332 netdev_dbg(dev, "ACK_ERR irq\n");
333 cf->can_id |= CAN_ERR_ACK;
334 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
337 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
338 netdev_dbg(dev, "CRC_ERR irq\n");
339 cf->data[2] |= CAN_ERR_PROT_BIT;
340 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
343 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
344 netdev_dbg(dev, "FRM_ERR irq\n");
345 cf->data[2] |= CAN_ERR_PROT_FORM;
348 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
349 netdev_dbg(dev, "STF_ERR irq\n");
350 cf->data[2] |= CAN_ERR_PROT_STUFF;
354 priv->can.can_stats.bus_error++;
356 dev->stats.rx_errors++;
358 dev->stats.tx_errors++;
361 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
364 struct can_frame *cf;
366 skb = alloc_can_err_skb(dev, &cf);
370 do_bus_err(dev, cf, reg_esr);
371 netif_receive_skb(skb);
373 dev->stats.rx_packets++;
374 dev->stats.rx_bytes += cf->can_dlc;
379 static void do_state(struct net_device *dev,
380 struct can_frame *cf, enum can_state new_state)
382 struct flexcan_priv *priv = netdev_priv(dev);
383 struct can_berr_counter bec;
385 flexcan_get_berr_counter(dev, &bec);
387 switch (priv->can.state) {
388 case CAN_STATE_ERROR_ACTIVE:
391 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
392 * => : there was a warning int
394 if (new_state >= CAN_STATE_ERROR_WARNING &&
395 new_state <= CAN_STATE_BUS_OFF) {
396 netdev_dbg(dev, "Error Warning IRQ\n");
397 priv->can.can_stats.error_warning++;
399 cf->can_id |= CAN_ERR_CRTL;
400 cf->data[1] = (bec.txerr > bec.rxerr) ?
401 CAN_ERR_CRTL_TX_WARNING :
402 CAN_ERR_CRTL_RX_WARNING;
404 case CAN_STATE_ERROR_WARNING: /* fallthrough */
406 * from: ERROR_ACTIVE, ERROR_WARNING
407 * to : ERROR_PASSIVE, BUS_OFF
408 * => : error passive int
410 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
411 new_state <= CAN_STATE_BUS_OFF) {
412 netdev_dbg(dev, "Error Passive IRQ\n");
413 priv->can.can_stats.error_passive++;
415 cf->can_id |= CAN_ERR_CRTL;
416 cf->data[1] = (bec.txerr > bec.rxerr) ?
417 CAN_ERR_CRTL_TX_PASSIVE :
418 CAN_ERR_CRTL_RX_PASSIVE;
421 case CAN_STATE_BUS_OFF:
422 netdev_err(dev, "BUG! "
423 "hardware recovered automatically from BUS_OFF\n");
429 /* process state changes depending on the new state */
431 case CAN_STATE_ERROR_ACTIVE:
432 netdev_dbg(dev, "Error Active\n");
433 cf->can_id |= CAN_ERR_PROT;
434 cf->data[2] = CAN_ERR_PROT_ACTIVE;
436 case CAN_STATE_BUS_OFF:
437 cf->can_id |= CAN_ERR_BUSOFF;
445 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
447 struct flexcan_priv *priv = netdev_priv(dev);
449 struct can_frame *cf;
450 enum can_state new_state;
453 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
454 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
455 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
456 FLEXCAN_ESR_RX_WRN))))
457 new_state = CAN_STATE_ERROR_ACTIVE;
459 new_state = CAN_STATE_ERROR_WARNING;
460 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
461 new_state = CAN_STATE_ERROR_PASSIVE;
463 new_state = CAN_STATE_BUS_OFF;
465 /* state hasn't changed */
466 if (likely(new_state == priv->can.state))
469 skb = alloc_can_err_skb(dev, &cf);
473 do_state(dev, cf, new_state);
474 priv->can.state = new_state;
475 netif_receive_skb(skb);
477 dev->stats.rx_packets++;
478 dev->stats.rx_bytes += cf->can_dlc;
483 static void flexcan_read_fifo(const struct net_device *dev,
484 struct can_frame *cf)
486 const struct flexcan_priv *priv = netdev_priv(dev);
487 struct flexcan_regs __iomem *regs = priv->base;
488 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
489 u32 reg_ctrl, reg_id;
491 reg_ctrl = flexcan_read(&mb->can_ctrl);
492 reg_id = flexcan_read(&mb->can_id);
493 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
494 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
496 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
498 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
499 cf->can_id |= CAN_RTR_FLAG;
500 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
502 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
503 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
506 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
507 flexcan_read(®s->timer);
510 static int flexcan_read_frame(struct net_device *dev)
512 struct net_device_stats *stats = &dev->stats;
513 struct can_frame *cf;
516 skb = alloc_can_skb(dev, &cf);
517 if (unlikely(!skb)) {
522 flexcan_read_fifo(dev, cf);
523 netif_receive_skb(skb);
526 stats->rx_bytes += cf->can_dlc;
531 static int flexcan_poll(struct napi_struct *napi, int quota)
533 struct net_device *dev = napi->dev;
534 const struct flexcan_priv *priv = netdev_priv(dev);
535 struct flexcan_regs __iomem *regs = priv->base;
536 u32 reg_iflag1, reg_esr;
540 * The error bits are cleared on read,
541 * use saved value from irq handler.
543 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
545 /* handle state changes */
546 work_done += flexcan_poll_state(dev, reg_esr);
549 reg_iflag1 = flexcan_read(®s->iflag1);
550 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
552 work_done += flexcan_read_frame(dev);
553 reg_iflag1 = flexcan_read(®s->iflag1);
556 /* report bus errors */
557 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
558 work_done += flexcan_poll_bus_err(dev, reg_esr);
560 if (work_done < quota) {
563 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
564 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
570 static irqreturn_t flexcan_irq(int irq, void *dev_id)
572 struct net_device *dev = dev_id;
573 struct net_device_stats *stats = &dev->stats;
574 struct flexcan_priv *priv = netdev_priv(dev);
575 struct flexcan_regs __iomem *regs = priv->base;
576 u32 reg_iflag1, reg_esr;
578 reg_iflag1 = flexcan_read(®s->iflag1);
579 reg_esr = flexcan_read(®s->esr);
580 /* ACK all bus error and state change IRQ sources */
581 if (reg_esr & FLEXCAN_ESR_ALL_INT)
582 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
585 * schedule NAPI in case of:
588 * - bus error IRQ and bus error reporting is activated
590 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
591 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
592 flexcan_has_and_handle_berr(priv, reg_esr)) {
594 * The error bits are cleared on read,
595 * save them for later use.
597 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
598 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
599 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
600 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
602 napi_schedule(&priv->napi);
606 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
607 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
608 dev->stats.rx_over_errors++;
609 dev->stats.rx_errors++;
612 /* transmission complete interrupt */
613 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
614 stats->tx_bytes += can_get_echo_skb(dev, 0);
616 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
617 netif_wake_queue(dev);
623 static void flexcan_set_bittiming(struct net_device *dev)
625 const struct flexcan_priv *priv = netdev_priv(dev);
626 const struct can_bittiming *bt = &priv->can.bittiming;
627 struct flexcan_regs __iomem *regs = priv->base;
630 reg = flexcan_read(®s->ctrl);
631 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
632 FLEXCAN_CTRL_RJW(0x3) |
633 FLEXCAN_CTRL_PSEG1(0x7) |
634 FLEXCAN_CTRL_PSEG2(0x7) |
635 FLEXCAN_CTRL_PROPSEG(0x7) |
640 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
641 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
642 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
643 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
644 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
646 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
647 reg |= FLEXCAN_CTRL_LPB;
648 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
649 reg |= FLEXCAN_CTRL_LOM;
650 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
651 reg |= FLEXCAN_CTRL_SMP;
653 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
654 flexcan_write(reg, ®s->ctrl);
656 /* print chip status */
657 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
658 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
664 * this functions is entered with clocks enabled
667 static int flexcan_chip_start(struct net_device *dev)
669 struct flexcan_priv *priv = netdev_priv(dev);
670 struct flexcan_regs __iomem *regs = priv->base;
673 u32 reg_mcr, reg_ctrl;
676 flexcan_chip_enable(priv);
679 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
682 reg_mcr = flexcan_read(®s->mcr);
683 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
684 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
690 flexcan_set_bittiming(dev);
698 * only supervisor access
704 reg_mcr = flexcan_read(®s->mcr);
705 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
706 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
707 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
708 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
709 flexcan_write(reg_mcr, ®s->mcr);
714 * disable timer sync feature
716 * disable auto busoff recovery
717 * transmit lowest buffer first
719 * enable tx and rx warning interrupt
720 * enable bus off interrupt
721 * (== FLEXCAN_CTRL_ERR_STATE)
723 * _note_: we enable the "error interrupt"
724 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
725 * warning or bus passive interrupts.
727 reg_ctrl = flexcan_read(®s->ctrl);
728 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
729 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
730 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
732 /* save for later use */
733 priv->reg_ctrl_default = reg_ctrl;
734 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
735 flexcan_write(reg_ctrl, ®s->ctrl);
737 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
738 flexcan_write(0, ®s->cantxfg[i].can_ctrl);
739 flexcan_write(0, ®s->cantxfg[i].can_id);
740 flexcan_write(0, ®s->cantxfg[i].data[0]);
741 flexcan_write(0, ®s->cantxfg[i].data[1]);
743 /* put MB into rx queue */
744 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
745 ®s->cantxfg[i].can_ctrl);
748 /* acceptance mask/acceptance code (accept everything) */
749 flexcan_write(0x0, ®s->rxgmask);
750 flexcan_write(0x0, ®s->rx14mask);
751 flexcan_write(0x0, ®s->rx15mask);
753 flexcan_transceiver_switch(priv, 1);
755 /* synchronize with the can bus */
756 reg_mcr = flexcan_read(®s->mcr);
757 reg_mcr &= ~FLEXCAN_MCR_HALT;
758 flexcan_write(reg_mcr, ®s->mcr);
760 priv->can.state = CAN_STATE_ERROR_ACTIVE;
762 /* enable FIFO interrupts */
763 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
765 /* print chip status */
766 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
767 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
772 flexcan_chip_disable(priv);
779 * this functions is entered with clocks enabled
782 static void flexcan_chip_stop(struct net_device *dev)
784 struct flexcan_priv *priv = netdev_priv(dev);
785 struct flexcan_regs __iomem *regs = priv->base;
788 /* Disable all interrupts */
789 flexcan_write(0, ®s->imask1);
791 /* Disable + halt module */
792 reg = flexcan_read(®s->mcr);
793 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
794 flexcan_write(reg, ®s->mcr);
796 flexcan_transceiver_switch(priv, 0);
797 priv->can.state = CAN_STATE_STOPPED;
802 static int flexcan_open(struct net_device *dev)
804 struct flexcan_priv *priv = netdev_priv(dev);
807 clk_prepare_enable(priv->clk);
809 err = open_candev(dev);
813 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
817 /* start chip and queuing */
818 err = flexcan_chip_start(dev);
821 napi_enable(&priv->napi);
822 netif_start_queue(dev);
829 clk_disable_unprepare(priv->clk);
834 static int flexcan_close(struct net_device *dev)
836 struct flexcan_priv *priv = netdev_priv(dev);
838 netif_stop_queue(dev);
839 napi_disable(&priv->napi);
840 flexcan_chip_stop(dev);
842 free_irq(dev->irq, dev);
843 clk_disable_unprepare(priv->clk);
850 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
856 err = flexcan_chip_start(dev);
860 netif_wake_queue(dev);
870 static const struct net_device_ops flexcan_netdev_ops = {
871 .ndo_open = flexcan_open,
872 .ndo_stop = flexcan_close,
873 .ndo_start_xmit = flexcan_start_xmit,
876 static int __devinit register_flexcandev(struct net_device *dev)
878 struct flexcan_priv *priv = netdev_priv(dev);
879 struct flexcan_regs __iomem *regs = priv->base;
882 clk_prepare_enable(priv->clk);
884 /* select "bus clock", chip must be disabled */
885 flexcan_chip_disable(priv);
886 reg = flexcan_read(®s->ctrl);
887 reg |= FLEXCAN_CTRL_CLK_SRC;
888 flexcan_write(reg, ®s->ctrl);
890 flexcan_chip_enable(priv);
892 /* set freeze, halt and activate FIFO, restrict register access */
893 reg = flexcan_read(®s->mcr);
894 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
895 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
896 flexcan_write(reg, ®s->mcr);
899 * Currently we only support newer versions of this core
900 * featuring a RX FIFO. Older cores found on some Coldfire
901 * derivates are not yet supported.
903 reg = flexcan_read(®s->mcr);
904 if (!(reg & FLEXCAN_MCR_FEN)) {
905 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
910 err = register_candev(dev);
913 /* disable core and turn off clocks */
914 flexcan_chip_disable(priv);
915 clk_disable_unprepare(priv->clk);
920 static void __devexit unregister_flexcandev(struct net_device *dev)
922 unregister_candev(dev);
925 static int __devinit flexcan_probe(struct platform_device *pdev)
927 struct net_device *dev;
928 struct flexcan_priv *priv;
929 struct resource *mem;
930 struct clk *clk = NULL;
931 struct pinctrl *pinctrl;
933 resource_size_t mem_size;
937 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
939 return PTR_ERR(pinctrl);
941 if (pdev->dev.of_node) {
942 const u32 *clock_freq_p;
944 clock_freq_p = of_get_property(pdev->dev.of_node,
945 "clock-frequency", NULL);
947 clock_freq = *clock_freq_p;
951 clk = clk_get(&pdev->dev, NULL);
953 dev_err(&pdev->dev, "no clock defined\n");
957 clock_freq = clk_get_rate(clk);
960 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
961 irq = platform_get_irq(pdev, 0);
962 if (!mem || irq <= 0) {
967 mem_size = resource_size(mem);
968 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
973 base = ioremap(mem->start, mem_size);
979 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
985 dev->netdev_ops = &flexcan_netdev_ops;
987 dev->flags |= IFF_ECHO;
989 priv = netdev_priv(dev);
990 priv->can.clock.freq = clock_freq;
991 priv->can.bittiming_const = &flexcan_bittiming_const;
992 priv->can.do_set_mode = flexcan_set_mode;
993 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
994 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
995 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
996 CAN_CTRLMODE_BERR_REPORTING;
1000 priv->pdata = pdev->dev.platform_data;
1002 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1004 dev_set_drvdata(&pdev->dev, dev);
1005 SET_NETDEV_DEV(dev, &pdev->dev);
1007 err = register_flexcandev(dev);
1009 dev_err(&pdev->dev, "registering netdev failed\n");
1010 goto failed_register;
1013 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1014 priv->base, dev->irq);
1023 release_mem_region(mem->start, mem_size);
1031 static int __devexit flexcan_remove(struct platform_device *pdev)
1033 struct net_device *dev = platform_get_drvdata(pdev);
1034 struct flexcan_priv *priv = netdev_priv(dev);
1035 struct resource *mem;
1037 unregister_flexcandev(dev);
1038 platform_set_drvdata(pdev, NULL);
1039 iounmap(priv->base);
1041 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1042 release_mem_region(mem->start, resource_size(mem));
1052 static struct of_device_id flexcan_of_match[] = {
1054 .compatible = "fsl,p1010-flexcan",
1059 static struct platform_driver flexcan_driver = {
1062 .owner = THIS_MODULE,
1063 .of_match_table = flexcan_of_match,
1065 .probe = flexcan_probe,
1066 .remove = __devexit_p(flexcan_remove),
1069 module_platform_driver(flexcan_driver);
1071 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1072 "Marc Kleine-Budde <kernel@pengutronix.de>");
1073 MODULE_LICENSE("GPL v2");
1074 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");