2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/platform/flexcan.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/pinctrl/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN error and status register (ESR) bits */
96 #define FLEXCAN_ESR_TWRN_INT BIT(17)
97 #define FLEXCAN_ESR_RWRN_INT BIT(16)
98 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
99 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
100 #define FLEXCAN_ESR_ACK_ERR BIT(13)
101 #define FLEXCAN_ESR_CRC_ERR BIT(12)
102 #define FLEXCAN_ESR_FRM_ERR BIT(11)
103 #define FLEXCAN_ESR_STF_ERR BIT(10)
104 #define FLEXCAN_ESR_TX_WRN BIT(9)
105 #define FLEXCAN_ESR_RX_WRN BIT(8)
106 #define FLEXCAN_ESR_IDLE BIT(7)
107 #define FLEXCAN_ESR_TXRX BIT(6)
108 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112 #define FLEXCAN_ESR_BOFF_INT BIT(2)
113 #define FLEXCAN_ESR_ERR_INT BIT(1)
114 #define FLEXCAN_ESR_WAK_INT BIT(0)
115 #define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119 #define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121 #define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123 #define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
127 /* FLEXCAN interrupt flag register (IFLAG) bits */
128 #define FLEXCAN_TX_BUF_ID 8
129 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
130 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133 #define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
137 /* FLEXCAN message buffers */
138 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139 #define FLEXCAN_MB_CNT_SRR BIT(22)
140 #define FLEXCAN_MB_CNT_IDE BIT(21)
141 #define FLEXCAN_MB_CNT_RTR BIT(20)
142 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
145 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
147 /* FLEXCAN hardware feature flags */
148 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
149 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* Broken error state handling */
151 /* Structure of the message buffer */
158 /* Structure of the hardware registers */
159 struct flexcan_regs {
162 u32 timer; /* 0x08 */
163 u32 _reserved1; /* 0x0c */
164 u32 rxgmask; /* 0x10 */
165 u32 rx14mask; /* 0x14 */
166 u32 rx15mask; /* 0x18 */
169 u32 imask2; /* 0x24 */
170 u32 imask1; /* 0x28 */
171 u32 iflag2; /* 0x2c */
172 u32 iflag1; /* 0x30 */
175 u32 imeur; /* 0x3c */
178 u32 rxfgmask; /* 0x48 */
179 u32 rxfir; /* 0x4c */
181 struct flexcan_mb cantxfg[64];
184 struct flexcan_devtype_data {
185 u32 features; /* hardware controller features */
188 struct flexcan_priv {
190 struct net_device *dev;
191 struct napi_struct napi;
195 u32 reg_ctrl_default;
199 struct flexcan_platform_data *pdata;
200 const struct flexcan_devtype_data *devtype_data;
203 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
204 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
206 static struct flexcan_devtype_data fsl_imx28_devtype_data;
207 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
208 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_BROKEN_ERR_STATE,
211 static const struct can_bittiming_const flexcan_bittiming_const = {
224 * Abstract off the read/write for arm versus ppc.
226 #if defined(__BIG_ENDIAN)
227 static inline u32 flexcan_read(void __iomem *addr)
229 return in_be32(addr);
232 static inline void flexcan_write(u32 val, void __iomem *addr)
237 static inline u32 flexcan_read(void __iomem *addr)
242 static inline void flexcan_write(u32 val, void __iomem *addr)
249 * Swtich transceiver on or off
251 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
253 if (priv->pdata && priv->pdata->transceiver_switch)
254 priv->pdata->transceiver_switch(on);
257 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
260 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
261 (reg_esr & FLEXCAN_ESR_ERR_BUS);
264 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
266 struct flexcan_regs __iomem *regs = priv->base;
269 reg = flexcan_read(®s->mcr);
270 reg &= ~FLEXCAN_MCR_MDIS;
271 flexcan_write(reg, ®s->mcr);
276 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
278 struct flexcan_regs __iomem *regs = priv->base;
281 reg = flexcan_read(®s->mcr);
282 reg |= FLEXCAN_MCR_MDIS;
283 flexcan_write(reg, ®s->mcr);
286 static int flexcan_get_berr_counter(const struct net_device *dev,
287 struct can_berr_counter *bec)
289 const struct flexcan_priv *priv = netdev_priv(dev);
290 struct flexcan_regs __iomem *regs = priv->base;
291 u32 reg = flexcan_read(®s->ecr);
293 bec->txerr = (reg >> 0) & 0xff;
294 bec->rxerr = (reg >> 8) & 0xff;
299 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
301 const struct flexcan_priv *priv = netdev_priv(dev);
302 struct flexcan_regs __iomem *regs = priv->base;
303 struct can_frame *cf = (struct can_frame *)skb->data;
305 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
307 if (can_dropped_invalid_skb(dev, skb))
310 netif_stop_queue(dev);
312 if (cf->can_id & CAN_EFF_FLAG) {
313 can_id = cf->can_id & CAN_EFF_MASK;
314 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
316 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
319 if (cf->can_id & CAN_RTR_FLAG)
320 ctrl |= FLEXCAN_MB_CNT_RTR;
322 if (cf->can_dlc > 0) {
323 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
324 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
326 if (cf->can_dlc > 3) {
327 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
328 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
331 can_put_echo_skb(skb, dev, 0);
333 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
334 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
339 static void do_bus_err(struct net_device *dev,
340 struct can_frame *cf, u32 reg_esr)
342 struct flexcan_priv *priv = netdev_priv(dev);
343 int rx_errors = 0, tx_errors = 0;
345 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
347 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
348 netdev_dbg(dev, "BIT1_ERR irq\n");
349 cf->data[2] |= CAN_ERR_PROT_BIT1;
352 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
353 netdev_dbg(dev, "BIT0_ERR irq\n");
354 cf->data[2] |= CAN_ERR_PROT_BIT0;
357 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
358 netdev_dbg(dev, "ACK_ERR irq\n");
359 cf->can_id |= CAN_ERR_ACK;
360 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
363 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
364 netdev_dbg(dev, "CRC_ERR irq\n");
365 cf->data[2] |= CAN_ERR_PROT_BIT;
366 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
369 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
370 netdev_dbg(dev, "FRM_ERR irq\n");
371 cf->data[2] |= CAN_ERR_PROT_FORM;
374 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
375 netdev_dbg(dev, "STF_ERR irq\n");
376 cf->data[2] |= CAN_ERR_PROT_STUFF;
380 priv->can.can_stats.bus_error++;
382 dev->stats.rx_errors++;
384 dev->stats.tx_errors++;
387 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
390 struct can_frame *cf;
392 skb = alloc_can_err_skb(dev, &cf);
396 do_bus_err(dev, cf, reg_esr);
397 netif_receive_skb(skb);
399 dev->stats.rx_packets++;
400 dev->stats.rx_bytes += cf->can_dlc;
405 static void do_state(struct net_device *dev,
406 struct can_frame *cf, enum can_state new_state)
408 struct flexcan_priv *priv = netdev_priv(dev);
409 struct can_berr_counter bec;
411 flexcan_get_berr_counter(dev, &bec);
413 switch (priv->can.state) {
414 case CAN_STATE_ERROR_ACTIVE:
417 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
418 * => : there was a warning int
420 if (new_state >= CAN_STATE_ERROR_WARNING &&
421 new_state <= CAN_STATE_BUS_OFF) {
422 netdev_dbg(dev, "Error Warning IRQ\n");
423 priv->can.can_stats.error_warning++;
425 cf->can_id |= CAN_ERR_CRTL;
426 cf->data[1] = (bec.txerr > bec.rxerr) ?
427 CAN_ERR_CRTL_TX_WARNING :
428 CAN_ERR_CRTL_RX_WARNING;
430 case CAN_STATE_ERROR_WARNING: /* fallthrough */
432 * from: ERROR_ACTIVE, ERROR_WARNING
433 * to : ERROR_PASSIVE, BUS_OFF
434 * => : error passive int
436 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
437 new_state <= CAN_STATE_BUS_OFF) {
438 netdev_dbg(dev, "Error Passive IRQ\n");
439 priv->can.can_stats.error_passive++;
441 cf->can_id |= CAN_ERR_CRTL;
442 cf->data[1] = (bec.txerr > bec.rxerr) ?
443 CAN_ERR_CRTL_TX_PASSIVE :
444 CAN_ERR_CRTL_RX_PASSIVE;
447 case CAN_STATE_BUS_OFF:
448 netdev_err(dev, "BUG! "
449 "hardware recovered automatically from BUS_OFF\n");
455 /* process state changes depending on the new state */
457 case CAN_STATE_ERROR_ACTIVE:
458 netdev_dbg(dev, "Error Active\n");
459 cf->can_id |= CAN_ERR_PROT;
460 cf->data[2] = CAN_ERR_PROT_ACTIVE;
462 case CAN_STATE_BUS_OFF:
463 cf->can_id |= CAN_ERR_BUSOFF;
471 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
473 struct flexcan_priv *priv = netdev_priv(dev);
475 struct can_frame *cf;
476 enum can_state new_state;
479 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
480 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
481 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
482 FLEXCAN_ESR_RX_WRN))))
483 new_state = CAN_STATE_ERROR_ACTIVE;
485 new_state = CAN_STATE_ERROR_WARNING;
486 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
487 new_state = CAN_STATE_ERROR_PASSIVE;
489 new_state = CAN_STATE_BUS_OFF;
491 /* state hasn't changed */
492 if (likely(new_state == priv->can.state))
495 skb = alloc_can_err_skb(dev, &cf);
499 do_state(dev, cf, new_state);
500 priv->can.state = new_state;
501 netif_receive_skb(skb);
503 dev->stats.rx_packets++;
504 dev->stats.rx_bytes += cf->can_dlc;
509 static void flexcan_read_fifo(const struct net_device *dev,
510 struct can_frame *cf)
512 const struct flexcan_priv *priv = netdev_priv(dev);
513 struct flexcan_regs __iomem *regs = priv->base;
514 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
515 u32 reg_ctrl, reg_id;
517 reg_ctrl = flexcan_read(&mb->can_ctrl);
518 reg_id = flexcan_read(&mb->can_id);
519 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
520 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
522 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
524 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
525 cf->can_id |= CAN_RTR_FLAG;
526 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
528 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
529 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
532 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
533 flexcan_read(®s->timer);
536 static int flexcan_read_frame(struct net_device *dev)
538 struct net_device_stats *stats = &dev->stats;
539 struct can_frame *cf;
542 skb = alloc_can_skb(dev, &cf);
543 if (unlikely(!skb)) {
548 flexcan_read_fifo(dev, cf);
549 netif_receive_skb(skb);
552 stats->rx_bytes += cf->can_dlc;
557 static int flexcan_poll(struct napi_struct *napi, int quota)
559 struct net_device *dev = napi->dev;
560 const struct flexcan_priv *priv = netdev_priv(dev);
561 struct flexcan_regs __iomem *regs = priv->base;
562 u32 reg_iflag1, reg_esr;
566 * The error bits are cleared on read,
567 * use saved value from irq handler.
569 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
571 /* handle state changes */
572 work_done += flexcan_poll_state(dev, reg_esr);
575 reg_iflag1 = flexcan_read(®s->iflag1);
576 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
578 work_done += flexcan_read_frame(dev);
579 reg_iflag1 = flexcan_read(®s->iflag1);
582 /* report bus errors */
583 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
584 work_done += flexcan_poll_bus_err(dev, reg_esr);
586 if (work_done < quota) {
589 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
590 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
596 static irqreturn_t flexcan_irq(int irq, void *dev_id)
598 struct net_device *dev = dev_id;
599 struct net_device_stats *stats = &dev->stats;
600 struct flexcan_priv *priv = netdev_priv(dev);
601 struct flexcan_regs __iomem *regs = priv->base;
602 u32 reg_iflag1, reg_esr;
604 reg_iflag1 = flexcan_read(®s->iflag1);
605 reg_esr = flexcan_read(®s->esr);
606 /* ACK all bus error and state change IRQ sources */
607 if (reg_esr & FLEXCAN_ESR_ALL_INT)
608 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
611 * schedule NAPI in case of:
614 * - bus error IRQ and bus error reporting is activated
616 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
617 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
618 flexcan_has_and_handle_berr(priv, reg_esr)) {
620 * The error bits are cleared on read,
621 * save them for later use.
623 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
624 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
625 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
626 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
628 napi_schedule(&priv->napi);
632 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
633 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
634 dev->stats.rx_over_errors++;
635 dev->stats.rx_errors++;
638 /* transmission complete interrupt */
639 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
640 stats->tx_bytes += can_get_echo_skb(dev, 0);
642 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
643 netif_wake_queue(dev);
649 static void flexcan_set_bittiming(struct net_device *dev)
651 const struct flexcan_priv *priv = netdev_priv(dev);
652 const struct can_bittiming *bt = &priv->can.bittiming;
653 struct flexcan_regs __iomem *regs = priv->base;
656 reg = flexcan_read(®s->ctrl);
657 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
658 FLEXCAN_CTRL_RJW(0x3) |
659 FLEXCAN_CTRL_PSEG1(0x7) |
660 FLEXCAN_CTRL_PSEG2(0x7) |
661 FLEXCAN_CTRL_PROPSEG(0x7) |
666 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
667 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
668 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
669 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
670 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
672 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
673 reg |= FLEXCAN_CTRL_LPB;
674 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
675 reg |= FLEXCAN_CTRL_LOM;
676 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
677 reg |= FLEXCAN_CTRL_SMP;
679 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
680 flexcan_write(reg, ®s->ctrl);
682 /* print chip status */
683 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
684 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
690 * this functions is entered with clocks enabled
693 static int flexcan_chip_start(struct net_device *dev)
695 struct flexcan_priv *priv = netdev_priv(dev);
696 struct flexcan_regs __iomem *regs = priv->base;
699 u32 reg_mcr, reg_ctrl;
702 flexcan_chip_enable(priv);
705 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
708 reg_mcr = flexcan_read(®s->mcr);
709 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
710 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
716 flexcan_set_bittiming(dev);
724 * only supervisor access
730 reg_mcr = flexcan_read(®s->mcr);
731 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
732 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
733 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
734 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
735 flexcan_write(reg_mcr, ®s->mcr);
740 * disable timer sync feature
742 * disable auto busoff recovery
743 * transmit lowest buffer first
745 * enable tx and rx warning interrupt
746 * enable bus off interrupt
747 * (== FLEXCAN_CTRL_ERR_STATE)
749 reg_ctrl = flexcan_read(®s->ctrl);
750 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
751 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
752 FLEXCAN_CTRL_ERR_STATE;
754 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
755 * on most Flexcan cores, too. Otherwise we don't get
756 * any error warning or passive interrupts.
758 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
759 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
760 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
762 /* save for later use */
763 priv->reg_ctrl_default = reg_ctrl;
764 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
765 flexcan_write(reg_ctrl, ®s->ctrl);
767 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
768 flexcan_write(0, ®s->cantxfg[i].can_ctrl);
769 flexcan_write(0, ®s->cantxfg[i].can_id);
770 flexcan_write(0, ®s->cantxfg[i].data[0]);
771 flexcan_write(0, ®s->cantxfg[i].data[1]);
773 /* put MB into rx queue */
774 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
775 ®s->cantxfg[i].can_ctrl);
778 /* acceptance mask/acceptance code (accept everything) */
779 flexcan_write(0x0, ®s->rxgmask);
780 flexcan_write(0x0, ®s->rx14mask);
781 flexcan_write(0x0, ®s->rx15mask);
783 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
784 flexcan_write(0x0, ®s->rxfgmask);
786 flexcan_transceiver_switch(priv, 1);
788 /* synchronize with the can bus */
789 reg_mcr = flexcan_read(®s->mcr);
790 reg_mcr &= ~FLEXCAN_MCR_HALT;
791 flexcan_write(reg_mcr, ®s->mcr);
793 priv->can.state = CAN_STATE_ERROR_ACTIVE;
795 /* enable FIFO interrupts */
796 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
798 /* print chip status */
799 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
800 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
805 flexcan_chip_disable(priv);
812 * this functions is entered with clocks enabled
815 static void flexcan_chip_stop(struct net_device *dev)
817 struct flexcan_priv *priv = netdev_priv(dev);
818 struct flexcan_regs __iomem *regs = priv->base;
821 /* Disable all interrupts */
822 flexcan_write(0, ®s->imask1);
824 /* Disable + halt module */
825 reg = flexcan_read(®s->mcr);
826 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
827 flexcan_write(reg, ®s->mcr);
829 flexcan_transceiver_switch(priv, 0);
830 priv->can.state = CAN_STATE_STOPPED;
835 static int flexcan_open(struct net_device *dev)
837 struct flexcan_priv *priv = netdev_priv(dev);
840 clk_prepare_enable(priv->clk_ipg);
841 clk_prepare_enable(priv->clk_per);
843 err = open_candev(dev);
847 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
851 /* start chip and queuing */
852 err = flexcan_chip_start(dev);
855 napi_enable(&priv->napi);
856 netif_start_queue(dev);
863 clk_disable_unprepare(priv->clk_per);
864 clk_disable_unprepare(priv->clk_ipg);
869 static int flexcan_close(struct net_device *dev)
871 struct flexcan_priv *priv = netdev_priv(dev);
873 netif_stop_queue(dev);
874 napi_disable(&priv->napi);
875 flexcan_chip_stop(dev);
877 free_irq(dev->irq, dev);
878 clk_disable_unprepare(priv->clk_per);
879 clk_disable_unprepare(priv->clk_ipg);
886 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
892 err = flexcan_chip_start(dev);
896 netif_wake_queue(dev);
906 static const struct net_device_ops flexcan_netdev_ops = {
907 .ndo_open = flexcan_open,
908 .ndo_stop = flexcan_close,
909 .ndo_start_xmit = flexcan_start_xmit,
912 static int __devinit register_flexcandev(struct net_device *dev)
914 struct flexcan_priv *priv = netdev_priv(dev);
915 struct flexcan_regs __iomem *regs = priv->base;
918 clk_prepare_enable(priv->clk_ipg);
919 clk_prepare_enable(priv->clk_per);
921 /* select "bus clock", chip must be disabled */
922 flexcan_chip_disable(priv);
923 reg = flexcan_read(®s->ctrl);
924 reg |= FLEXCAN_CTRL_CLK_SRC;
925 flexcan_write(reg, ®s->ctrl);
927 flexcan_chip_enable(priv);
929 /* set freeze, halt and activate FIFO, restrict register access */
930 reg = flexcan_read(®s->mcr);
931 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
932 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
933 flexcan_write(reg, ®s->mcr);
936 * Currently we only support newer versions of this core
937 * featuring a RX FIFO. Older cores found on some Coldfire
938 * derivates are not yet supported.
940 reg = flexcan_read(®s->mcr);
941 if (!(reg & FLEXCAN_MCR_FEN)) {
942 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
947 err = register_candev(dev);
950 /* disable core and turn off clocks */
951 flexcan_chip_disable(priv);
952 clk_disable_unprepare(priv->clk_per);
953 clk_disable_unprepare(priv->clk_ipg);
958 static void __devexit unregister_flexcandev(struct net_device *dev)
960 unregister_candev(dev);
963 static const struct of_device_id flexcan_of_match[] = {
964 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
965 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
966 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
970 static const struct platform_device_id flexcan_id_table[] = {
971 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
975 static int __devinit flexcan_probe(struct platform_device *pdev)
977 const struct of_device_id *of_id;
978 const struct flexcan_devtype_data *devtype_data;
979 struct net_device *dev;
980 struct flexcan_priv *priv;
981 struct resource *mem;
982 struct clk *clk_ipg = NULL, *clk_per = NULL;
983 struct pinctrl *pinctrl;
985 resource_size_t mem_size;
989 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
991 return PTR_ERR(pinctrl);
993 if (pdev->dev.of_node)
994 of_property_read_u32(pdev->dev.of_node,
995 "clock-frequency", &clock_freq);
998 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
999 if (IS_ERR(clk_ipg)) {
1000 dev_err(&pdev->dev, "no ipg clock defined\n");
1001 err = PTR_ERR(clk_ipg);
1004 clock_freq = clk_get_rate(clk_ipg);
1006 clk_per = devm_clk_get(&pdev->dev, "per");
1007 if (IS_ERR(clk_per)) {
1008 dev_err(&pdev->dev, "no per clock defined\n");
1009 err = PTR_ERR(clk_per);
1014 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1015 irq = platform_get_irq(pdev, 0);
1016 if (!mem || irq <= 0) {
1021 mem_size = resource_size(mem);
1022 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
1027 base = ioremap(mem->start, mem_size);
1033 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1039 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1041 devtype_data = of_id->data;
1042 } else if (pdev->id_entry->driver_data) {
1043 devtype_data = (struct flexcan_devtype_data *)
1044 pdev->id_entry->driver_data;
1047 goto failed_devtype;
1050 dev->netdev_ops = &flexcan_netdev_ops;
1052 dev->flags |= IFF_ECHO;
1054 priv = netdev_priv(dev);
1055 priv->can.clock.freq = clock_freq;
1056 priv->can.bittiming_const = &flexcan_bittiming_const;
1057 priv->can.do_set_mode = flexcan_set_mode;
1058 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1059 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1060 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1061 CAN_CTRLMODE_BERR_REPORTING;
1064 priv->clk_ipg = clk_ipg;
1065 priv->clk_per = clk_per;
1066 priv->pdata = pdev->dev.platform_data;
1067 priv->devtype_data = devtype_data;
1069 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1071 dev_set_drvdata(&pdev->dev, dev);
1072 SET_NETDEV_DEV(dev, &pdev->dev);
1074 err = register_flexcandev(dev);
1076 dev_err(&pdev->dev, "registering netdev failed\n");
1077 goto failed_register;
1080 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1081 priv->base, dev->irq);
1091 release_mem_region(mem->start, mem_size);
1097 static int __devexit flexcan_remove(struct platform_device *pdev)
1099 struct net_device *dev = platform_get_drvdata(pdev);
1100 struct flexcan_priv *priv = netdev_priv(dev);
1101 struct resource *mem;
1103 unregister_flexcandev(dev);
1104 platform_set_drvdata(pdev, NULL);
1105 iounmap(priv->base);
1107 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 release_mem_region(mem->start, resource_size(mem));
1116 static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
1118 struct net_device *dev = platform_get_drvdata(pdev);
1119 struct flexcan_priv *priv = netdev_priv(dev);
1121 flexcan_chip_disable(priv);
1123 if (netif_running(dev)) {
1124 netif_stop_queue(dev);
1125 netif_device_detach(dev);
1127 priv->can.state = CAN_STATE_SLEEPING;
1132 static int flexcan_resume(struct platform_device *pdev)
1134 struct net_device *dev = platform_get_drvdata(pdev);
1135 struct flexcan_priv *priv = netdev_priv(dev);
1137 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1138 if (netif_running(dev)) {
1139 netif_device_attach(dev);
1140 netif_start_queue(dev);
1142 flexcan_chip_enable(priv);
1147 #define flexcan_suspend NULL
1148 #define flexcan_resume NULL
1151 static struct platform_driver flexcan_driver = {
1154 .owner = THIS_MODULE,
1155 .of_match_table = flexcan_of_match,
1157 .probe = flexcan_probe,
1158 .remove = __devexit_p(flexcan_remove),
1159 .suspend = flexcan_suspend,
1160 .resume = flexcan_resume,
1161 .id_table = flexcan_id_table,
1164 module_platform_driver(flexcan_driver);
1166 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1167 "Marc Kleine-Budde <kernel@pengutronix.de>");
1168 MODULE_LICENSE("GPL v2");
1169 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");